diff --git a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga
index 4dd7f21c3..0431c5f75 100644
--- a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga
@@ -59,8 +59,6 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
 write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
-write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --explicit_port_mapping
-write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping 
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key/config/task.conf
index 787e469d0..474f802dc 100644
--- a/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key/config/task.conf
@@ -36,4 +36,3 @@ bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=
-#vpr_fpga_verilog_formal_verification_top_netlist=