diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index f547743c8..d6f3bed34 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -2121,514 +2121,6 @@ void update_routing_connection_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_inf return; } - -/* Dump port list of a subckt describing a side of a switch block - * Only output ports will be printed on the specified side - * Only input ports will be printed on the other sides - */ -static -void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp, - const RRGSB& rr_sb, - enum e_side sb_side, - size_t seg_id, - boolean dump_port_type, - bool is_explicit_mapping) { - /* Check file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d])Invalid file handler!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Create a side manager */ - Side sb_side_manager(sb_side); - - for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) { - Side side_manager(side); - /* Print ports */ - fprintf(fp, "//----- Inputs/outputs of %s side -----\n", side_manager.c_str()); - DeviceCoordinator port_coordinator = rr_sb.get_side_block_coordinator(side_manager.get_side()); - - for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { - switch (rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)) { - case OUT_PORT: - /* if this is the specified side, we only consider output ports */ - if (sb_side_manager.get_side() != side_manager.get_side()) { - break; - } - /* Bypass unwanted segments */ - if (seg_id != rr_sb.get_chan_node_segment(side_manager.get_side(), itrack)) { - continue; - } - fprintf(fp, " "); - if (TRUE == dump_port_type) { - fprintf(fp, "output "); - is_explicit_mapping = false; /* Both cannot be true together */ - } - if (true == is_explicit_mapping) { - fprintf(fp, ".%s(", - gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), - port_coordinator.get_x(), port_coordinator.get_y(), itrack, - rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); - } - fprintf(fp, "%s", - gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), - port_coordinator.get_x(), port_coordinator.get_y(), itrack, - rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); - if (true == is_explicit_mapping) { - fprintf(fp, ")"); - } - fprintf(fp, ",\n"); - break; - case IN_PORT: - /* if this is not the specified side, we only consider input ports */ - if (sb_side_manager.get_side() == side_manager.get_side()) { - break; - } - fprintf(fp, " "); - if (TRUE == dump_port_type) { - fprintf(fp, "input "); - } - if (true == is_explicit_mapping) { - fprintf(fp, ".%s(", - gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), - port_coordinator.get_x(), port_coordinator.get_y(), itrack, - rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); - } - fprintf(fp, "%s", - gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), - port_coordinator.get_x(), port_coordinator.get_y(), itrack, - rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); - if (true == is_explicit_mapping) { - fprintf(fp, ")"); - } - fprintf(fp, ",\n"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File: %s [LINE%d]) Invalid direction of chan[%d][%d]_track[%d]!\n", - __FILE__, __LINE__, rr_sb.get_sb_x(), rr_sb.get_sb_y(), itrack); - exit(1); - } - } - - /* Dump OPINs of adjacent CLBs */ - for (size_t inode = 0; inode < rr_sb.get_num_opin_nodes(side_manager.get_side()); ++inode) { - fprintf(fp, " "); - dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an input of a SB */ - rr_sb.get_opin_node(side_manager.get_side(), inode)->ptc_num, - rr_sb.get_opin_node_grid_side(side_manager.get_side(), inode), - rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow, - rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow, - dump_port_type, is_explicit_mapping); /* Dump the direction of the port ! */ - if (FALSE == dump_port_type) { - fprintf(fp, ",\n"); - } - } - } - - return; -} - - -/* Task: Print the subckt of a side of a Switch Box. - * For TOP side: - * 1. Channel Y [x][y+1] inputs - * 2. Grid[x][y+1] Right side outputs pins - * 3. Grid[x+1][y+1] Left side output pins - * For RIGHT side: - * 1. Channel X [x+1][y] inputs - * 2. Grid[x+1][y+1] Bottom side output pins - * 3. Grid[x+1][y] Top side output pins - * For BOTTOM side: - * 1. Channel Y [x][y] outputs - * 2. Grid[x][y] Right side output pins - * 3. Grid[x+1][y] Left side output pins - * For LEFT side: - * 1. Channel X [x][y] outputs - * 2. Grid[x][y] Top side output pins - * 3. Grid[x][y+1] Bottom side output pins - * - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y+1] | [x][y+1] | [x+1][y+1] | - * | | | | - * -------------- -------------- - * ---------- - * ChanX | Switch | ChanX - * [x][y] | Box | [x+1][y] - * | [x][y] | - * ---------- - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y] | [x][y] | [x+1][y] | - * | | | | - * -------------- -------------- - */ -static -void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sram_orgz_info, - char* verilog_dir, char* subckt_dir, - size_t module_id, size_t seg_id, - const RRGSB& rr_sb, enum e_side side, - bool is_explicit_mapping) { - FILE* fp = NULL; - char* fname = NULL; - Side side_manager(side); - - /* Get the channel width on this side, if it is zero, we return */ - if (0 == rr_sb.get_chan_width(side)) { - return; - } - - /* Count the number of configuration bits to be consumed by this Switch block */ - int num_conf_bits = count_verilog_switch_box_side_conf_bits(cur_sram_orgz_info, rr_sb, side, seg_id); - /* Count the number of reserved configuration bits to be consumed by this Switch block */ - int num_reserved_conf_bits = count_verilog_switch_box_side_reserved_conf_bits(cur_sram_orgz_info, rr_sb, side, seg_id); - /* Estimate the sram_verilog_model->cnt */ - int cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); - int esti_sram_cnt = cur_num_sram + num_conf_bits; - - /* Create file name */ - std::string fname_prefix(sb_verilog_file_name_prefix); - fname_prefix += side_manager.c_str(); - - std::string file_description("Unique module for Switch Block side: "); - file_description += side_manager.c_str(); - file_description += "seg"; - file_description += std::to_string(seg_id); - - /* Create file handler */ - fp = verilog_create_one_subckt_file(subckt_dir, file_description.c_str(), - fname_prefix.c_str(), module_id, seg_id, &fname); - - /* Print preprocessing flags */ - verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Comment lines */ - fprintf(fp, - "//----- Verilog Module of Unique Switch Box[%lu][%lu] at Side %s, Segment id: %lu -----\n", - rr_sb.get_sb_x(), rr_sb.get_sb_y(), side_manager.c_str(), seg_id); - /* Print the definition of subckt*/ - fprintf(fp, "module %s ( \n", rr_sb.gen_sb_verilog_side_module_name(side, seg_id)); - /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { - fprintf(fp, ",\n"); - } - - dump_verilog_routing_switch_box_unique_side_subckt_portmap(fp, rr_sb, side, - seg_id, TRUE, - false); - - /* Put down configuration port */ - /* output of each configuration bit */ - /* Reserved sram ports */ - dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info, - 0, - num_reserved_conf_bits - 1, - VERILOG_PORT_INPUT); - if (0 < num_reserved_conf_bits) { - fprintf(fp, ",\n"); - } - /* Normal sram ports */ - dump_verilog_sram_ports(fp, cur_sram_orgz_info, - cur_num_sram, - esti_sram_cnt - 1, - VERILOG_PORT_INPUT); - - /* Dump ports only visible during formal verification*/ - if (0 < num_conf_bits) { - fprintf(fp, "\n"); - fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag); - fprintf(fp, ",\n"); - dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, - cur_num_sram, - esti_sram_cnt - 1, - VERILOG_PORT_INPUT, false); - fprintf(fp, "\n"); - fprintf(fp, "`endif\n"); - } - fprintf(fp, "); \n"); - - /* Local wires for memory configurations */ - dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info, - cur_num_sram, - esti_sram_cnt - 1); - - /* Put down all the multiplexers */ - fprintf(fp, "//----- %s side Multiplexers -----\n", - side_manager.c_str()); - for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { - assert((CHANX == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type) - ||(CHANY == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type)); - /* We care INC_DIRECTION tracks at this side*/ - if (OUT_PORT == rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)) { - /* Bypass unwanted segments */ - if (seg_id != rr_sb.get_chan_node_segment(side_manager.get_side(), itrack)) { - continue; - } - dump_verilog_unique_switch_box_interc(cur_sram_orgz_info, fp, rr_sb, - side_manager.get_side(), - itrack, is_explicit_mapping); - } - } - - fprintf(fp, "endmodule\n"); - - /* Comment lines */ - fprintf(fp, - "//----- END Verilog Module of Switch Box[%lu][%lu] Side %s -----\n\n", - rr_sb.get_sb_x(), rr_sb.get_sb_y(), side_manager.c_str()); - - /* Check */ - assert(esti_sram_cnt == get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info)); - - /* Close file handler */ - fclose(fp); - - /* Add fname to the linked list */ - routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, fname); - - /* Free chan_rr_nodes */ - my_free(fname); - - return; -} - -/* Task: Print the subckt of a Switch Box. - * Call the four submodules dumped in function: unique_side_module - * - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y+1] | [x][y+1] | [x+1][y+1] | - * | | | | - * -------------- -------------- - * ---------- - * ChanX | Switch | ChanX - * [x][y] | Box | [x+1][y] - * | [x][y] | - * ---------- - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y] | [x][y] | [x+1][y] | - * | | | | - * -------------- -------------- - */ -static -void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_orgz_info, - char* verilog_dir, char* subckt_dir, - const RRGSB& rr_sb, - bool is_explicit_mapping) { - FILE* fp = NULL; - char* fname = NULL; - - /* Count the number of configuration bits to be consumed by this Switch block */ - int num_conf_bits = count_verilog_switch_box_conf_bits(cur_sram_orgz_info, rr_sb); - /* Count the number of reserved configuration bits to be consumed by this Switch block */ - int num_reserved_conf_bits = count_verilog_switch_box_reserved_conf_bits(cur_sram_orgz_info, rr_sb); - /* Estimate the sram_verilog_model->cnt */ - int cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); - RRGSB rr_gsb = rr_sb; /* IMPORTANT: this copy will be removed when the config ports are initialized when created!!! */ - rr_gsb.set_sb_num_reserved_conf_bits(num_reserved_conf_bits); - rr_gsb.set_sb_conf_bits_lsb(cur_num_sram); - rr_gsb.set_sb_conf_bits_msb(cur_num_sram + num_conf_bits - 1); - - /* Create file handler */ - fp = verilog_create_one_subckt_file(subckt_dir, "Unique Switch Block ", - sb_verilog_file_name_prefix, rr_gsb.get_sb_x(), rr_gsb.get_sb_y(), &fname); - - /* Print preprocessing flags */ - verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Comment lines */ - fprintf(fp, "//----- Verilog Module of Unique Switch Box[%lu][%lu] -----\n", rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); - /* Print the definition of subckt*/ - fprintf(fp, "module %s ( \n", rr_gsb.gen_sb_verilog_module_name()); - /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { - fprintf(fp, ",\n"); - } - - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side side_manager(side); - /* Print ports */ - fprintf(fp, "//----- Channel Inputs/outputs of %s side -----\n", side_manager.c_str()); - DeviceCoordinator port_coordinator = rr_gsb.get_side_block_coordinator(side_manager.get_side()); - - for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { - switch (rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { - case OUT_PORT: - fprintf(fp, " output %s,\n", - gen_verilog_routing_channel_one_pin_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack), - port_coordinator.get_x(), port_coordinator.get_y(), itrack, - rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack))); - break; - case IN_PORT: - fprintf(fp, " input %s,\n", - gen_verilog_routing_channel_one_pin_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack), - port_coordinator.get_x(), port_coordinator.get_y(), itrack, - rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack))); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File: %s [LINE%d]) Invalid direction of chan[%d][%d]_track[%d]!\n", - __FILE__, __LINE__, rr_gsb.get_sb_x(), rr_gsb.get_sb_y(), itrack); - exit(1); - } - } - /* Dump OPINs of adjacent CLBs */ - fprintf(fp, "//----- Grid Inputs/outputs of %s side -----\n", side_manager.c_str()); - for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) { - fprintf(fp, " "); - dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an input of a SB */ - rr_gsb.get_opin_node(side_manager.get_side(), inode)->ptc_num, - rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), - rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, - rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow, - TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ - } - } - - /* Put down configuration port */ - /* output of each configuration bit */ - /* Reserved sram ports */ - fprintf(fp, "//----- Reserved SRAM Ports -----\n"); - if (0 < rr_gsb.get_sb_num_reserved_conf_bits()) { - dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info, - rr_gsb.get_sb_reserved_conf_bits_lsb(), - rr_gsb.get_sb_reserved_conf_bits_msb(), - VERILOG_PORT_INPUT); - fprintf(fp, ",\n"); - } - /* Normal sram ports */ - fprintf(fp, "//----- Regular SRAM Ports -----\n"); - dump_verilog_sram_ports(fp, cur_sram_orgz_info, - rr_gsb.get_sb_conf_bits_lsb(), - rr_gsb.get_sb_conf_bits_msb(), - VERILOG_PORT_INPUT); - - /* Dump ports only visible during formal verification*/ - if (0 < rr_gsb.get_sb_num_conf_bits()) { - fprintf(fp, "\n"); - fprintf(fp, "//----- SRAM Ports for formal verification -----\n"); - fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag); - fprintf(fp, ",\n"); - dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, - rr_gsb.get_sb_conf_bits_lsb(), - rr_gsb.get_sb_conf_bits_msb(), - VERILOG_PORT_INPUT, - false); - fprintf(fp, "\n"); - fprintf(fp, "`endif\n"); - } - fprintf(fp, "); \n"); - - /* Local wires for memory configurations */ - dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info, - rr_gsb.get_sb_conf_bits_lsb(), - rr_gsb.get_sb_conf_bits_msb()); - - /* Call submodules */ - int cur_sram_lsb = cur_num_sram; - int cur_sram_msb = cur_num_sram; - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side side_manager(side); - fprintf(fp, "//----- %s side Submodule -----\n", - side_manager.c_str()); - - /* Get the channel width on this side, if it is zero, we return */ - if (0 == rr_gsb.get_chan_width(side_manager.get_side())) { - fprintf(fp, "//----- %s side has zero channel width, module dump skipped -----\n", - side_manager.c_str()); - continue; - } - - /* get segment ids */ - std::vector seg_ids = rr_gsb.get_chan(side_manager.get_side()).get_segment_ids(); - for (size_t iseg = 0; iseg < seg_ids.size(); ++iseg) { - fprintf(fp, "//----- %s side Submodule with Segment id: %lu -----\n", - side_manager.c_str(), seg_ids[iseg]); - - /* Count the number of configuration bits to be consumed by this Switch block */ - int side_num_conf_bits = count_verilog_switch_box_side_conf_bits(cur_sram_orgz_info, rr_gsb, side_manager.get_side(), seg_ids[iseg]); - /* Count the number of reserved configuration bits to be consumed by this Switch block */ - int side_num_reserved_conf_bits = count_verilog_switch_box_side_reserved_conf_bits(cur_sram_orgz_info, rr_gsb, side_manager.get_side(), seg_ids[iseg]); - - /* Cache the sram counter */ - cur_sram_msb = cur_sram_lsb + side_num_conf_bits - 1; - - /* Instanciate the subckt*/ - fprintf(fp, - "%s %s ( \n", - rr_gsb.gen_sb_verilog_side_module_name(side_manager.get_side(), seg_ids[iseg]), - rr_gsb.gen_sb_verilog_side_instance_name(side_manager.get_side(), seg_ids[iseg])); - /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { - fprintf(fp, ",\n"); - } - - dump_verilog_routing_switch_box_unique_side_subckt_portmap(fp, rr_gsb, side_manager.get_side(), seg_ids[iseg], FALSE, is_explicit_mapping); - - /* Put down configuration port */ - /* output of each configuration bit */ - /* Reserved sram ports */ - dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info, - 0, - side_num_reserved_conf_bits - 1, - VERILOG_PORT_CONKT); - if (0 < side_num_reserved_conf_bits) { - fprintf(fp, ",\n"); - } - /* Normal sram ports */ - dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, - cur_sram_lsb, - cur_sram_msb, - VERILOG_PORT_CONKT, is_explicit_mapping); - - /* Dump ports only visible during formal verification*/ - if (0 < side_num_conf_bits) { - fprintf(fp, "\n"); - fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag); - fprintf(fp, ",\n"); - dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, - cur_sram_lsb, - cur_sram_msb, - VERILOG_PORT_CONKT, is_explicit_mapping); - fprintf(fp, "\n"); - fprintf(fp, "`endif\n"); - } - fprintf(fp, "); \n"); - - /* Update sram_lsb */ - cur_sram_lsb = cur_sram_msb + 1; - } - } - /* checker */ - assert(cur_sram_msb == cur_num_sram + num_conf_bits - 1); - - fprintf(fp, "endmodule\n"); - - /* Comment lines */ - fprintf(fp, "//----- END Verilog Module of Switch Box[%lu][%lu] -----\n\n", rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); - - /* Close file handler */ - fclose(fp); - - /* Add fname to the linked list */ - routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, fname); - - /* Free chan_rr_nodes */ - my_free(fname); - - return; -} - - - /* Task: Print the subckt of a Switch Box. * A Switch Box subckt consists of following ports: * 1. Channel Y [x][y] inputs