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Merge pull request #150 from lnis-uofu/dev 

Misc Updates
This commit is contained in:
Laboratory for Nano Integrated Systems (LNIS) 2020-12-06 15:44:37 -07:00 committed by GitHub
parent 2eaff52c13 d11a3d9fef
commit c5d9bac126
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 21 additions and 13 deletions
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5
openfpga/src/fabric/build_decoder_modules.cpp
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@ -232,8 +232,11 @@ void build_mux_local_decoder_module(ModuleManager& module_manager,
module_manager.add_port(module_id, data_port, ModuleManager::MODULE_OUTPUT_PORT);
/* Data port is registered. It should be outputted as
* output reg [lsb:msb] data
* Only applicable to data port size > 1
*/
module_manager.set_port_is_register(module_id, data_port.get_name(), true);
if (1 < data_port.get_width()) {
module_manager.set_port_is_register(module_id, data_port.get_name(), true);
}
/* Add data_in port */
BasicPort data_inv_port(generate_mux_local_decoder_data_inv_port_name(), data_size);
VTR_ASSERT(true == decoder_lib.use_data_inv_port(decoder));

3
openfpga/src/fpga_verilog/verilog_api.cpp
View File

@ -210,8 +210,7 @@ void fpga_verilog_testbench(const ModuleManager &module_manager,
netlist_name,
top_testbench_file_path,
simulation_setting,
options.fast_configuration(),
options.explicit_port_mapping());
options);
}
/* Generate exchangeable files which contains simulation settings */

22
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -1779,8 +1779,10 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
const std::string& circuit_name,
const std::string& verilog_fname,
const SimulationSetting& simulation_parameters,
const bool& fast_configuration,
const bool& explicit_port_mapping) {
const VerilogTestbenchOption& options) {
bool fast_configuration = options.fast_configuration();
bool explicit_port_mapping = options.explicit_port_mapping();
std::string timer_message = std::string("Write autocheck testbench for FPGA top-level Verilog netlist for '") + circuit_name + std::string("'");
@ -1917,12 +1919,16 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
module_manager, top_module,
bitstream_manager, fabric_bitstream);
/* Add signal initialization */
print_verilog_testbench_signal_initialization(fp,
std::string(TOP_TESTBENCH_FPGA_INSTANCE_NAME),
circuit_lib,
module_manager,
top_module);
/* Add signal initialization:
* Bypass writing codes to files due to the autogenerated codes are very large.
*/
if (true == options.include_signal_init()) {
print_verilog_testbench_signal_initialization(fp,
std::string(TOP_TESTBENCH_FPGA_INSTANCE_NAME),
circuit_lib,
module_manager,
top_module);
}
/* Add stimuli for reset, set, clock and iopad signals */
print_verilog_testbench_random_stimuli(fp, atom_ctx,

4
openfpga/src/fpga_verilog/verilog_top_testbench.h
View File

@ -16,6 +16,7 @@
#include "fabric_global_port_info.h"
#include "vpr_netlist_annotation.h"
#include "simulation_setting.h"
#include "verilog_testbench_options.h"
/********************************************************************
* Function declaration
@ -37,8 +38,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
const std::string& circuit_name,
const std::string& verilog_fname,
const SimulationSetting& simulation_parameters,
const bool& fast_configuration,
const bool& explicit_port_mapping);
const VerilogTestbenchOption& options);
} /* end namespace openfpga */