diff --git a/openfpga_flow/misc/fpgaflow_default_tool_path_timing.conf b/openfpga_flow/misc/fpgaflow_default_tool_path_timing.conf
new file mode 100644
index 000000000..f67572299
--- /dev/null
+++ b/openfpga_flow/misc/fpgaflow_default_tool_path_timing.conf
@@ -0,0 +1,76 @@
+# Standard Configuration Example
+[CAD_TOOLS_PATH]
+openfpga_shell_path = ${PATH:OPENFPGA_PATH}/build/openfpga/openfpga
+yosys_path = ${PATH:OPENFPGA_PATH}/build/yosys/bin/yosys
+misc_dir = ${PATH:OPENFPGA_PATH}/openfpga_flow/misc
+odin2_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/not_used_atm/odin2.exe
+abc_path = ${PATH:OPENFPGA_PATH}/build/yosys/bin/yosys-abc
+abc_mccl_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/abc/abc
+abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/abc/abc
+vpr_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/vpr/vpr
+ace_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/ace2/ace
+pro_blif_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/scripts/pro_blif.pl
+iverilog_path = iverilog
+include_netlist_verification = ${PATH:OPENFPGA_PATH}/vpr/VerilogNetlists
+
+[FLOW_SCRIPT_CONFIG]
+valid_flows = vpr_blif,yosys_vpr
+
+[DEFAULT_PARSE_RESULT_VPR]
+# parser format <name of variable> = <regex string>, <lambda function/type>
+clb_blocks = "Netlist clb blocks: ([0-9]+)", str
+io_blocks = "Netlist io blocks: ([0-9]+)", str
+mult_blocks = "Netlist mult_36 blocks: ([0-9]+)", str
+memory_blocks = "Netlist memory blocks: ([0-9]+)", str
+total_routing_area = "Total routing area: ([0-9.]+[e|E\+[0-9]+)", str
+total_logic_block_area = "Total used logic block area: ([0-9.]+[e|E\+[0-9]+)", str
+total_wire_length = "Total wirelength: ([0-9]+)", str
+packing_time = "Packing took ([0-9.]+) seconds", str
+placement_time = "Placement took ([0-9.]+) seconds", str
+routing_time = "Routing took ([0-9.]+) seconds", str
+average_net_length = "average net length: ([0-9.]+)", str
+critical_path = "Final critical path (least slack): ([0-9.]+) ([a-z])s", scientific
+vclk0_critical_path = "virtual_io_clock to clk0 CPD: ([0-9.]+) ([a-z])s", scientific
+clk0_critical_path = "clk0 to clk0 CPD: ([0-9.]+) ([a-z])s", scientific
+vclk1_critical_path = "virtual_io_clock to clk1 CPD: ([0-9.]+) ([a-z])s", scientific
+clk1_critical_path = "clk1 to clk1 CPD: ([0-9.]+) ([a-z])s", scientific
+total_routing_time = "Routing took ([0-9.]+) seconds", float
+
+[DEFAULT_PARSE_RESULT_POWER]
+pb_type_power="PB Types\s+([0-9]+)", str
+routing_power="Routing\s+([0-9]+)", str
+switch_box_power="Switch Box\s+([0-9]+)", str
+connection_box_power="Connection Box\s+([0-9]+)", str
+primitives_power="Primitives\s+([0-9]+)", str
+interc_structures_power="Interc Structures\s+([0-9]+)", str
+lut6_power="^\s+lut6\s+([0-9]+)", str
+ff_power="^\s+ff\s+([0-9]+)", str
+
+[INTERMIDIATE_FILE_PREFIX]
+# Yosys files
+yosys_out_blif=${PATH:TOP_MODULE}_yosys_out.blif
+yosys_output=yosys_output.txt
+
+# ACE2 and intermidiate file
+activity_file=${PATH:TOP_MODULE}_ace_out.act
+ace_output_blif=${PATH:TOP_MODULE}_ace_out.blif
+corrected_format_blif=${PATH:TOP_MODULE}.blif
+blackbox_blif=${PATH:TOP_MODULE}_bb.blif
+
+# VPR Files
+min_chann_vpr_output=${PATH:TOP_MODULE}_min_chan_width_vpr.txt
+reroute_chan_vpr_output=${PATH:TOP_MODULE}_reroute_vpr.txt
+fixed_chan_vpr_output=${PATH:TOP_MODULE}_fr_chan_width.txt
+vpr_stat_parse_fn=vpr_stat.txt
+vpr_power_stat_parse_fn=vpr_power_stat.txt
+vpr_net_file=${PATH:TOP_MODULE}_vpr.net
+vpr_place_file=${PATH:TOP_MODULE}_vpr.place
+vpr_route_file=${PATH:TOP_MODULE}_vpr.route
+
+#Iverilog verification file
+iverilog_output=iverilog_output.txt
+vvp_output=vvp_sim_output.txt
+
+[CMD_ARGUMENT_DEPENDANCY]
+vpr_fpga_verilog=vpr_fpga_verilog_dir|abc
+vpr_fpga_verilog_dir=vpr_fpga_verilog