diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.cpp b/libopenfpga/libarchopenfpga/src/circuit_library.cpp index f56b94199..537a436bc 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/circuit_library.cpp @@ -1214,6 +1214,16 @@ CircuitModelId CircuitLibrary::add_model(const enum e_circuit_model_type& type) /* Build the fast look-up for circuit models */ build_model_lookup(); + /* Add a placeholder in the fast look-up for model port + * This is to avoid memory holes when a circuit model + * does not have any ports. + * As a result, the fast look-up may not even create an entry + * for this model id, which cause fast look-up abort when there is + * a query on the model + */ + model_port_lookup_.resize(model_ids_.size()); + model_port_lookup_[model_id].resize(NUM_CIRCUIT_MODEL_PORT_TYPES); + return model_id; } diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp index 91efe88c8..3611909bb 100644 --- a/openfpga/src/repack/repack.cpp +++ b/openfpga/src/repack/repack.cpp @@ -259,13 +259,25 @@ std::vector find_pb_route_remapped_source_pb_pin(const t_pb* pb, /* Only care the pin has the same parent port as source_pb_pin * Due to that the source_pb_pin may be swapped during routing * the pb_route is out-of-date + * + * For those parent port is defined as non-equivalent, + * the source pin and the pin recorded in the routing trace must match! + * * TODO: should update pb_route by post routing results * On the other side, the swapping can only happen between equivalent pins * in a port. So the port must match here! */ - if (source_pb_pin->port == pb->pb_route.at(pin).pb_graph_pin->port) { - pb_route_indices.push_back(pin); - } + if (PortEquivalence::FULL == source_pb_pin->port->equivalent) { + if (source_pb_pin->port == pb->pb_route.at(pin).pb_graph_pin->port) { + pb_route_indices.push_back(pin); + } + } else { + /* NOTE: INSTANCE is NOT supported! We support only NONE equivalent */ + VTR_ASSERT (PortEquivalence::NONE == source_pb_pin->port->equivalent); + if (source_pb_pin == pb->pb_route.at(pin).pb_graph_pin) { + pb_route_indices.push_back(pin); + } + } } return pb_route_indices; diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index e00faa1d1..d40e7bea2 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -197,6 +197,18 @@ + + + diff --git a/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga index ac0a1eafd..a5cbbaf16 100644 --- a/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga @@ -58,7 +58,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator #--explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh b/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh index 776c20079..2d3bd1202 100755 --- a/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh @@ -14,3 +14,6 @@ run-task quicklogic_tests/flow_test --debug --show_thread_logs echo -e "Testing yosys flow using custom ys script for running multi-clock quicklogic device"; run-task quicklogic_tests/counter_5clock_test --debug --show_thread_logs run-task quicklogic_tests/sdc_controller_test --debug --show_thread_logs + +echo -e "Testing yosys flow using custom ys script for adders in quicklogic device"; +run-task quicklogic_tests/lut_adder_test --debug --show_thread_logs diff --git a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml new file mode 100644 index 000000000..735d45c23 --- /dev/null +++ b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml @@ -0,0 +1,3 @@ + + + diff --git a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf new file mode 100644 index 000000000..6a5f29063 --- /dev/null +++ b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf @@ -0,0 +1,41 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 1*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_bitstream_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml +openfpga_vpr_circuit_format=eblif + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml + +[BENCHMARKS] +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v + +[SYNTHESIS_PARAM] +bench1_top = adder_8 +bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +########################## +# The output verilog of yosys is not synthesizable!!! +# Turn off verification for now +# SHOULD focus on fixing the Verilog problem and run verification at the end of the flow +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml index 3d71ffff9..17e37ee04 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -125,21 +125,21 @@ - + - + - + - + - + - + - + - + @@ -333,27 +333,27 @@ - - + - + - + - + - + - + - + - + @@ -507,9 +507,8 @@ - - - + +