diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp index 62b06be92..2607aa558 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp @@ -246,6 +246,8 @@ MuxGraph MuxGraph::subgraph(const MuxNodeId& root_node) const { /* Not found, we add a memory bit and record in the mem-to-mem map */ MuxMemId mem_subgraph = mux_graph.add_mem(); mem2mem_map[mem_origin] = mem_subgraph; + /* configure the edge */ + mux_graph.edge_mem_ids_[edge2edge_map[edge_origin]] = mem_subgraph; } /* Since the graph is finalized, it is time to build the fast look-up */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index 908a78ff9..bad43d388 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -109,7 +109,7 @@ void generate_verilog_cmos_mux_branch_module_structural(ModuleManager& module_ma /* Iterate over the outputs */ for (const auto& mux_output : mux_graph.outputs()) { /* TODO: the magic number 0 should be generated by MUX graph */ - BasicPort cur_output_port(output_port.get_name(), 0); + BasicPort cur_output_port(output_port.get_name(), 0, 0); /* if there is a connection between the input and output, a tgate will be outputted */ std::vector edges = mux_graph.find_edges(mux_input, mux_output); /* There should be only one edge or no edge*/ @@ -120,11 +120,11 @@ void generate_verilog_cmos_mux_branch_module_structural(ModuleManager& module_ma } /* TODO: Output a tgate use a module manager */ /* Create a port-to-port name map */ - std::map port2port_name_map; + std::map port2port_name_map; /* input port */ - port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[0])] = generate_verilog_port(VERILOG_PORT_CONKT, cur_input_port); + port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[0])] = cur_input_port; /* output port */ - port2port_name_map[circuit_lib.port_lib_name(tgate_output_ports[0])] = generate_verilog_port(VERILOG_PORT_CONKT, cur_output_port); + port2port_name_map[circuit_lib.port_lib_name(tgate_output_ports[0])] = cur_output_port; /* Find the mem_id controlling the edge */ MuxMemId mux_mem = mux_graph.find_edge_mem(edges[0]); BasicPort cur_mem_port(mem_port.get_name(), size_t(mux_mem), size_t(mux_mem)); @@ -132,12 +132,12 @@ void generate_verilog_cmos_mux_branch_module_structural(ModuleManager& module_ma /* mem port */ if (false == mux_graph.is_edge_use_inv_mem(edges[0])) { /* wire mem to mem of module, and wire mem_inv to mem_inv of module */ - port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[1])] = generate_verilog_port(VERILOG_PORT_CONKT, cur_mem_port); - port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[2])] = generate_verilog_port(VERILOG_PORT_CONKT, cur_mem_inv_port); + port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[1])] = cur_mem_port; + port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[2])] = cur_mem_inv_port; } else { /* wire mem_inv to mem of module, wire mem to mem_inv of module */ - port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[1])] = generate_verilog_port(VERILOG_PORT_CONKT, cur_mem_inv_port); - port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[2])] = generate_verilog_port(VERILOG_PORT_CONKT, cur_mem_port); + port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[1])] = cur_mem_inv_port; + port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[2])] = cur_mem_port; } /* Output an instance of the module */ print_verilog_module_instance(fp, module_manager, module_id, tgate_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(tgate_model)); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 2d104126b..fb78b8a86 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -132,7 +132,7 @@ void print_verilog_module_declaration(std::fstream& fp, void print_verilog_module_instance(std::fstream& fp, const ModuleManager& module_manager, const ModuleId& parent_module_id, const ModuleId& child_module_id, - std::map& port2port_name_map, + const std::map& port2port_name_map, const bool& explicit_port_map) { check_file_handler(fp); @@ -166,11 +166,9 @@ void print_verilog_module_instance(std::fstream& fp, fp << "." << port.get_name() << "("; } /* Try to find the instanced port name in the name map */ - std::map::iterator it = port2port_name_map.find(port.get_name()); - if (it != port2port_name_map.end()) { + if (port2port_name_map.find(port.get_name()) != port2port_name_map.end()) { /* Found it, we assign the port name */ - BasicPort instance_port(port.get_name(), 1); - fp << generate_verilog_port(kv.second, instance_port); + fp << generate_verilog_port(kv.second, port2port_name_map.at(port.get_name())); } else { /* Not found, we give the default port name */ fp << generate_verilog_port(kv.second, port); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index c1283804c..03626e4b6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -31,7 +31,7 @@ void print_verilog_module_declaration(std::fstream& fp, void print_verilog_module_instance(std::fstream& fp, const ModuleManager& module_manager, const ModuleId& parent_module_id, const ModuleId& child_module_id, - std::map& port2port_name_map, + const std::map& port2port_name_map, const bool& explicit_port_map); void print_verilog_module_end(std::fstream& fp,