From c2c37d7555944a0daca30b7083b104ba990e8e72 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 21:34:23 -0600 Subject: [PATCH] [OpenFPGA Tool] Add more print-out for smart fast configuration --- openfpga/src/fpga_verilog/verilog_top_testbench.cpp | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index d6f7d1075..28200696e 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -1164,6 +1164,8 @@ bool find_bit_value_to_skip_for_fast_configuration(const e_config_protocol_type& VTR_ASSERT(!global_prog_set_ports.empty() && !global_prog_reset_ports.empty()); bool bit_value_to_skip = false; + VTR_LOG("Both reset and set ports are defined for programming controls, selecting the best-fit one...\n"); + size_t num_ones_to_skip = 0; size_t num_zeros_to_skip = 0; @@ -1210,9 +1212,20 @@ bool find_bit_value_to_skip_for_fast_configuration(const e_config_protocol_type& exit(1); } + VTR_LOG("Using reset will skip %g% (%lu/%lu) of configuration bitstream.\n", + 100. * (float) num_zeros_to_skip / (float) fabric_bitstream.num_bits(), + num_zeros_to_skip, fabric_bitstream.num_bits()); + + VTR_LOG("Using set will skip %g% (%lu/%lu) of configuration bitstream.\n", + 100. * (float) num_ones_to_skip / (float) fabric_bitstream.num_bits(), + num_ones_to_skip, fabric_bitstream.num_bits()); + /* By default, we prefer to skip zeros (when the numbers are the same */ if (num_ones_to_skip > num_zeros_to_skip) { + VTR_LOG("Will use set signal in fast configuration\n"); bit_value_to_skip = true; + } else { + VTR_LOG("Will use reset signal in fast configuration\n"); } return bit_value_to_skip;