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[Script] Update yosys script due to arch changes in DPRAM sizes

This commit is contained in:
tangxifan 2021-04-28 10:55:59 -06:00
parent ec4b60f3cc
commit c24edbd674
3 changed files with 17 additions and 17 deletions
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6
openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_bram.txt → openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram.txt
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@ -1,6 +1,6 @@
bram $__MY_DPRAM_2048x8 bram $__MY_DPRAM_128x8
init 0 init 0
abits 11 abits 7
dbits 8 dbits 8
groups 2 groups 2
ports 1 1 ports 1 1
@ -11,7 +11,7 @@ bram $__MY_DPRAM_2048x8
clkpol 1 1 clkpol 1 1
endbram endbram
match $__MY_DPRAM_2048x8 match $__MY_DPRAM_128x8
min efficiency 0 min efficiency 0
make_transp make_transp
endmatch endmatch

8
openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_bram_map.v → openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v
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@ -1,14 +1,14 @@
module $__MY_DPRAM_2048x8 ( module $__MY_DPRAM_128x8 (
output [0:7] B1DATA, output [0:7] B1DATA,
input CLK1, input CLK1,
input [0:10] B1ADDR, input [0:6] B1ADDR,
input [0:10] A1ADDR, input [0:6] A1ADDR,
input [0:7] A1DATA, input [0:7] A1DATA,
input A1EN, input A1EN,
input B1EN ); input B1EN );
generate generate
dpram_2048x8 #() _TECHMAP_REPLACE_ ( dpram_128x8 #() _TECHMAP_REPLACE_ (
.clk (CLK1), .clk (CLK1),
.wen (A1EN), .wen (A1EN),
.waddr (A1ADDR), .waddr (A1ADDR),

20
openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_cell_sim.v → openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v
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@ -1,18 +1,18 @@
//----------------------------- //-----------------------------
// Dual-port RAM 2048x8 bit (8Kbit) // Dual-port RAM 128x8 bit (1Kbit)
// Core logic // Core logic
//----------------------------- //-----------------------------
module dpram_2048x8_core ( module dpram_128x8_core (
input wclk, input wclk,
input wen, input wen,
input [0:10] waddr, input [0:6] waddr,
input [0:7] data_in, input [0:7] data_in,
input rclk, input rclk,
input ren, input ren,
input [0:10] raddr, input [0:6] raddr,
output [0:7] data_out ); output [0:7] data_out );
reg [0:7] ram[0:2047]; reg [0:7] ram[0:127];
reg [0:7] internal; reg [0:7] internal;
assign data_out = internal; assign data_out = internal;
@ -32,20 +32,20 @@ module dpram_2048x8_core (
endmodule endmodule
//----------------------------- //-----------------------------
// Dual-port RAM 2048x8 bit (8Kbit) wrapper // Dual-port RAM 128x8 bit (1Kbit) wrapper
// where the read clock and write clock // where the read clock and write clock
// are combined to a unified clock // are combined to a unified clock
//----------------------------- //-----------------------------
module dpram_2048x8 ( module dpram_128x8 (
input clk, input clk,
input wen, input wen,
input ren, input ren,
input [0:10] waddr, input [0:6] waddr,
input [0:10] raddr, input [0:6] raddr,
input [0:7] data_in, input [0:7] data_in,
output [0:7] data_out ); output [0:7] data_out );
dpram_2048x8_core memory_0 ( dpram_128x8_core memory_0 (
.wclk (clk), .wclk (clk),
.wen (wen), .wen (wen),
.waddr (waddr), .waddr (waddr),