diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_bram.txt b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram.txt
similarity index 73%
rename from openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_bram.txt
rename to openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram.txt
index 327dbe9bf..51617f271 100644
--- a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_bram.txt
+++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram.txt
@@ -1,6 +1,6 @@
-bram $__MY_DPRAM_2048x8
+bram $__MY_DPRAM_128x8
   init 0
-  abits 11
+  abits 7
   dbits 8
   groups 2
   ports  1  1
@@ -11,7 +11,7 @@ bram $__MY_DPRAM_2048x8
   clkpol 1  1
 endbram
 
-match $__MY_DPRAM_2048x8
+match $__MY_DPRAM_128x8
   min efficiency 0
   make_transp
 endmatch
diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_bram_map.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v
similarity index 72%
rename from openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_bram_map.v
rename to openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v
index 35ec892dc..8cf462c1a 100644
--- a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_bram_map.v
+++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v
@@ -1,14 +1,14 @@
-module $__MY_DPRAM_2048x8 (
+module $__MY_DPRAM_128x8 (
   output [0:7] B1DATA,
   input CLK1,
-  input [0:10] B1ADDR,
-  input [0:10] A1ADDR,
+  input [0:6] B1ADDR,
+  input [0:6] A1ADDR,
   input [0:7] A1DATA,
   input A1EN,
   input B1EN );
 
   generate
-    dpram_2048x8 #() _TECHMAP_REPLACE_ (
+    dpram_128x8 #() _TECHMAP_REPLACE_ (
       .clk    (CLK1),
       .wen    (A1EN),
       .waddr    (A1ADDR),
diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v
similarity index 76%
rename from openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_cell_sim.v
rename to openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v
index 9fc6a1aa1..9ec66e6ee 100644
--- a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_cell_sim.v
+++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v
@@ -1,18 +1,18 @@
 //-----------------------------
-// Dual-port RAM 2048x8 bit (8Kbit)
+// Dual-port RAM 128x8 bit (1Kbit)
 // Core logic
 //-----------------------------
-module dpram_2048x8_core (
+module dpram_128x8_core (
   input wclk,
   input wen,
-  input [0:10] waddr,
+  input [0:6] waddr,
   input [0:7] data_in,
   input rclk,
   input ren,
-  input [0:10] raddr,
+  input [0:6] raddr,
   output [0:7] data_out );
 
-  reg [0:7] ram[0:2047];
+  reg [0:7] ram[0:127];
   reg [0:7] internal;
 
   assign data_out = internal;
@@ -32,20 +32,20 @@ module dpram_2048x8_core (
 endmodule
 
 //-----------------------------
-// Dual-port RAM 2048x8 bit (8Kbit) wrapper
+// Dual-port RAM 128x8 bit (1Kbit) wrapper
 // where the read clock and write clock
 // are combined to a unified clock
 //-----------------------------
-module dpram_2048x8 (
+module dpram_128x8 (
   input clk,
   input wen,
   input ren,
-  input [0:10] waddr,
-  input [0:10] raddr,
+  input [0:6] waddr,
+  input [0:6] raddr,
   input [0:7] data_in,
   output [0:7] data_out );
 
-    dpram_2048x8_core memory_0 (
+    dpram_128x8_core memory_0 (
       .wclk    (clk),
       .wen    (wen),
       .waddr    (waddr),