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[Architecture] Bug fix in no local routing architecture

This commit is contained in:
tangxifan 2020-09-16 18:07:52 -06:00
parent c40c9f5876
commit c22d8e2421
1 changed files with 4 additions and 4 deletions
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8
openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
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@ -265,10 +265,10 @@
<!-- 6-LUT mode definition end -->
</pb_type>
<interconnect>
<direct name="crossbar0" input="clb.I0" output="fle[0:0].in">
<direct name="crossbar1" input="clb.I1" output="fle[1:1].in">
<direct name="crossbar2" input="clb.I2" output="fle[2:2].in">
<direct name="crossbar3" input="clb.I3" output="fle[3:3].in">
<direct name="crossbar0" input="clb.I0" output="fle[0:0].in"/>
<direct name="crossbar1" input="clb.I1" output="fle[1:1].in"/>
<direct name="crossbar2" input="clb.I2" output="fle[2:2].in"/>
<direct name="crossbar3" input="clb.I3" output="fle[3:3].in"/>
<complete name="clks" input="clb.clk" output="fle[3:0].clk">
</complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.