From 12b44e0eca0c2164d89baff6ceb455d4cac38138 Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Thu, 13 May 2021 10:04:23 -0600 Subject: [PATCH 01/41] added configuration benchmark files --- .../config_loader/bitstream_loader.v | 195 ++++++++++++++++++ .../benchmarks/config_loader/clock_divider.v | 45 ++++ .../config_loader/configuration_manager.v | 71 +++++++ .../config_loader/pulse_generator.v | 76 +++++++ .../config_loader/reset_generator.v | 47 +++++ .../benchmarks/config_loader/test_top.v | 176 ++++++++++++++++ 6 files changed, 610 insertions(+) create mode 100644 openfpga_flow/benchmarks/config_loader/bitstream_loader.v create mode 100644 openfpga_flow/benchmarks/config_loader/clock_divider.v create mode 100644 openfpga_flow/benchmarks/config_loader/configuration_manager.v create mode 100644 openfpga_flow/benchmarks/config_loader/pulse_generator.v create mode 100644 openfpga_flow/benchmarks/config_loader/reset_generator.v create mode 100644 openfpga_flow/benchmarks/config_loader/test_top.v diff --git a/openfpga_flow/benchmarks/config_loader/bitstream_loader.v b/openfpga_flow/benchmarks/config_loader/bitstream_loader.v new file mode 100644 index 000000000..68b04aee1 --- /dev/null +++ b/openfpga_flow/benchmarks/config_loader/bitstream_loader.v @@ -0,0 +1,195 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 05/05/2021 09:43:10 AM +// Design Name: +// Module Name: bitstream_loader +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module bitstream_loader( + input prog_clk, + input start, + output config_chain_head, + output reg done + ); + + parameter BITSTREAM_FILE=""; + parameter BITSTREAM_SIZE=6140; + + reg [BITSTREAM_SIZE<=2 ? 2 : $clog2(BITSTREAM_SIZE):0] bitstream_index; + + reg [13:0] bram_addr; + reg [3:0] bram_line_index; + + wire bram_output; + assign config_chain_head = bram_output; + + RAMB18E1 #( + // Address Collision Mode: "PERFORMANCE" or "DELAYED_WRITE" + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + // Collision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE") + .SIM_COLLISION_CHECK("ALL"), + // RAM Mode: "SDP" or "TDP" + .RAM_MODE("TDP"), + // READ_WIDTH_A/B, WRITE_WIDTH_A/B: Read/write width per port + .READ_WIDTH_A(1), // 0-72 + .READ_WIDTH_B(0), // 0-18 + .WRITE_WIDTH_A(0), // 0-18 + .WRITE_WIDTH_B(0), // 0-72 + + .INIT_00(256'h00000000000000000000000000000000000000000000007f00000000000000ff), + .INIT_01(256'h0000fff8ffffffff000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h00000003f8000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000078000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0021000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + + + + // RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE") + .RSTREG_PRIORITY_A("RSTREG"), + .RSTREG_PRIORITY_B("RSTREG"), + // SRVAL_A, SRVAL_B: Set/reset value for output + .SRVAL_A(18'hFFFFF), + .SRVAL_B(18'h00000), + // Simulation Device: Must be set to "7SERIES" for simulation behavior + .SIM_DEVICE("7SERIES"), + // WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE") + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST") + ) + RAMB18E1_inst ( + // Port A Data: 16-bit (each) output: Port A data + .DOADO(bram_output), // 16-bit output: A port data/LSB data + .DOPADOP(), // 2-bit output: A port parity/LSB parity + // Port B Data: 16-bit (each) output: Port B data + .DOBDO(), // 16-bit output: B port data/MSB data + .DOPBDOP(), // 2-bit output: B port parity/MSB parity + // Port A Address/Control Signals: 14-bit (each) input: Port A address and control signals (read port + // when RAM_MODE="SDP") + .ADDRARDADDR(bram_addr), // 14-bit input: A port address/Read address + .CLKARDCLK(~prog_clk), // 1-bit input: A port clock/Read clock + .ENARDEN(1'b1), // 1-bit input: A port enable/Read enable + .REGCEAREGCE(1'b1), // 1-bit input: A port register enable/Register enable + .RSTRAMARSTRAM(0), // 1-bit input: A port set/reset + .RSTREGARSTREG(0), // 1-bit input: A port register set/reset + .WEA(2'b00), // 2-bit input: A port write enable + // Port A Data: 16-bit (each) input: Port A data + .DIADI(0), // 16-bit input: A port data/LSB data + .DIPADIP(0), // 2-bit input: A port parity/LSB parity + // Port B Address/Control Signals: 14-bit (each) input: Port B address and control signals (write port + // when RAM_MODE="SDP") + .ADDRBWRADDR(0), // 14-bit input: B port address/Write address + .CLKBWRCLK(0), // 1-bit input: B port clock/Write clock + .ENBWREN(0), // 1-bit input: B port enable/Write enable + .REGCEB(0), // 1-bit input: B port register enable + .RSTRAMB(0), // 1-bit input: B port set/reset + .RSTREGB(0), // 1-bit input: B port register set/reset + .WEBWE(0), // 4-bit input: B port write enable/Write enable + // Port B Data: 16-bit (each) input: Port B data + .DIBDI(0), // 16-bit input: B port data/MSB data + .DIPBDIP(0) // 2-bit input: B port parity/MSB parity + ); + + + initial begin + bram_addr <= 0; + bram_line_index <= 0; + bitstream_index <= 0; + done <= 1'b0; + end + + always @(posedge prog_clk) begin + if (start && !done) begin + + bram_addr <= bram_addr + 1; + bitstream_index <= bitstream_index + 1; + end + if (bitstream_index == BITSTREAM_SIZE) begin + done <= 1'b1; + end + end + + +endmodule + + + + + + + + + \ No newline at end of file diff --git a/openfpga_flow/benchmarks/config_loader/clock_divider.v b/openfpga_flow/benchmarks/config_loader/clock_divider.v new file mode 100644 index 000000000..4127cd9f3 --- /dev/null +++ b/openfpga_flow/benchmarks/config_loader/clock_divider.v @@ -0,0 +1,45 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 05/03/2021 03:25:29 PM +// Design Name: +// Module Name: clk_divider +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module clock_divider ( + input clk_in, + output reg clk_out + ); + + parameter CLK_DIVIDER_SIZE=8; + + reg [CLK_DIVIDER_SIZE - 1:0] clkdiv_counter; + + initial begin + clkdiv_counter <= 0; + clk_out <= 0; + end + + // Divide pl_clk (50MHz) to 1MHz + always @(posedge clk_in) begin + if (clkdiv_counter == 1 << CLK_DIVIDER_SIZE - 1) begin + clk_out <= ~clk_out; + end + clkdiv_counter <= clkdiv_counter +1; + end + +endmodule diff --git a/openfpga_flow/benchmarks/config_loader/configuration_manager.v b/openfpga_flow/benchmarks/config_loader/configuration_manager.v new file mode 100644 index 000000000..e3c20c2c1 --- /dev/null +++ b/openfpga_flow/benchmarks/config_loader/configuration_manager.v @@ -0,0 +1,71 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 05/05/2021 10:29:55 AM +// Design Name: +// Module Name: configuration_manager +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +`include "clock_divider.v" +`include "pulse_generator.v" + +module configuration_manager( + input clk_in, + output prog_reset, + output prog_clk, + output ccff_head, + output configuration_done + ); + + parameter START_CYCLE=3; // Start configuration on cycle 3 of prog_clk + parameter CONFIGURATION_CLK_DIV_SIZE=12; // Divide clk_in (50MHz) by 4096 (2^12) times + + wire prog_clk_out; // prog_clk signal from clk_divider + wire ccff_head_out; + + assign ccff_head = ccff_head_out & ~prog_reset; + assign prog_clk = prog_clk_out & ~configuration_done; // prog_clk will stop when configuration done + + // PRESET + // Programming reset will be enabled until START_CYCLE + reset_generator #( + .INITIAL_VALUE(1), + .ACTIVE_CYCLES(START_CYCLE) + ) prog_reset_generator( + .clk(~prog_clk), + .pulse(prog_reset) + ); + + + // PROG_CLK + // Divide pl_clk (50MHz) by 4096 (2^12) times + clock_divider #( + .CLK_DIVIDER_SIZE(CONFIGURATION_CLK_DIV_SIZE) + ) prog_clk_divider ( + .clk_in(clk_in), + .clk_out(prog_clk_out) + ); + + + // Instantiate bitstream loader + bitstream_loader loader ( + .prog_clk(prog_clk), + .config_chain_head(ccff_head_out), + .start(~prog_reset), + .done(configuration_done) + ); + +endmodule diff --git a/openfpga_flow/benchmarks/config_loader/pulse_generator.v b/openfpga_flow/benchmarks/config_loader/pulse_generator.v new file mode 100644 index 000000000..a73fc37f6 --- /dev/null +++ b/openfpga_flow/benchmarks/config_loader/pulse_generator.v @@ -0,0 +1,76 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 05/03/2021 03:37:44 PM +// Design Name: +// Module Name: pulse_generator +// Project Name: +// Target Devices: +// Tool Versions: +// Description: A simple pulse generator with configurable initial values and waiting cycles +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module pulse_generator( + input clk_in, + input repeated, // Specify if the pulse should be generated repeatedly + output reg pulse + ); + + + parameter INITIAL_VALUE=0; // Define the initial value for the pulse, either 0 or 1; The pulse logic level will be a flip over the initial value + parameter WAIT_CYCLES=0; // Define the number of clock cycles to wait before the pulse is applied + parameter PULSE_WIDTH=1; // Define the length of the pulse width + parameter PULSE_COUNTER_SIZE=10; // Define the size of the pulse width counter + + reg [WAIT_CYCLES<=2 ? 2 : $clog2(WAIT_CYCLES) : 0] wait_cycle_counter; // Size of wait counter is determined by WAIT_CYCLES + reg [PULSE_COUNTER_SIZE - 1 : 0] pulse_width_counter; + reg pulse_start; + reg pulse_end; + + initial begin + pulse <= INITIAL_VALUE; + pulse_start <= 1'b0; + pulse_end <= 1'b0; + wait_cycle_counter <= 0; + pulse_width_counter <= 0; + end + + // Wait a number of clock cycles, hold the initial value + always @(posedge clk_in) begin + if (wait_cycle_counter == WAIT_CYCLES) begin + pulse_start <= 1'b1; + end + if (~pulse_start) begin + wait_cycle_counter <= wait_cycle_counter + 1; + end + end + + // Wait a number of clock cycles, hold the initial value + always @(posedge clk_in) begin + pulse <= INITIAL_VALUE; + if (pulse_start && ~pulse_end) begin + // Reach the pulse width limit, stop counting + if (pulse_width_counter < PULSE_WIDTH) begin + pulse <= ~INITIAL_VALUE; + if (~repeated) begin + pulse_end = 1'b1; + end + end + // When pulse ends, flip to initial value + if (pulse_end) begin + pulse <= INITIAL_VALUE; + end + pulse_width_counter <= pulse_width_counter + 1; + end + end + +endmodule diff --git a/openfpga_flow/benchmarks/config_loader/reset_generator.v b/openfpga_flow/benchmarks/config_loader/reset_generator.v new file mode 100644 index 000000000..f949e722a --- /dev/null +++ b/openfpga_flow/benchmarks/config_loader/reset_generator.v @@ -0,0 +1,47 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 05/03/2021 04:52:18 PM +// Design Name: +// Module Name: reset_generator +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module reset_generator( + input clk, + output reg pulse + ); + + parameter INITIAL_VALUE=0; // Define the initial value for the pulse, either 0 or 1; The pulse logic level will be a flip over the initial value + parameter ACTIVE_CYCLES=0; // Define the number of clock cycles to wait before the pulse is applied + + reg [ACTIVE_CYCLES<=2 ? 2 : $clog2(ACTIVE_CYCLES) - 1 : 0] active_cycle_counter; + + initial begin + pulse <= INITIAL_VALUE; + active_cycle_counter <= 0; + end + + // Wait a number of clock cycles, hold the initial value + always @(posedge clk) begin + if (active_cycle_counter == ACTIVE_CYCLES) begin + pulse <= ~INITIAL_VALUE; + end else begin + active_cycle_counter <= active_cycle_counter + 1; + end + end + +endmodule diff --git a/openfpga_flow/benchmarks/config_loader/test_top.v b/openfpga_flow/benchmarks/config_loader/test_top.v new file mode 100644 index 000000000..e9a9c3783 --- /dev/null +++ b/openfpga_flow/benchmarks/config_loader/test_top.v @@ -0,0 +1,176 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 03/11/2021 03:01:46 PM +// Design Name: +// Module Name: top +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +`include "clock_divider.v" +`include "pulse_generator.v" + +module test_top ( + input sys_clk, + + + // Commented out i/o means it is floating and inaccessable to MPSoC + + // input LUT5_OUT_1_pad, + input GPIO3_pad, + input GPIO0_pad, + input CC_SPYPAD_1_pad, + // input PERF_SPYPAD_0_pad, + // input LUT5_OUT_0_pad, + output RESET_pad, + output CLK_pad, + // input GPIO4_pad, + // input GPIO5_pad, + input GPIO2_pad, + input GPIO1_pad, + input LUT6_OUT_0_pad, + input TEST_EN_pad, + input LUT4_OUT_0_pad, + // input LUT4_OUT_1_pad, + // input LUT4_OUT_2_pad, + // input LUT4_OUT_3_pad, + input SC_HEAD_pad, + input CCFF_TAIL_pad, + input GPIO23_pad, + input GPIO11_pad, + // input GPIO21_pad, + input GPIO22_pad, + input GPIO20_pad, + input GPIO10_pad, + input GPIO8_pad, + input GPIO9_pad, + input GPIO18_pad, + input GPIO19_pad, + input GPIO6_pad, + input GPIO7_pad, + input CC_SPYPAD_0_pad, + input CC_SPYPAD_2_pad, + input SC_TAIL_pad, + input COUT_SPYPAD_0_pad, + output CCFF_HEAD_pad, + // input SHIFTREG_SPY_pad, + // input SC_SPYPAD_0_pad, + output PRESET_pad, + input GPIO12_pad, + input GPIO16_pad, + // input GPIO15_pad, + // input GPIO14_pad, + input GPIO13_pad, + output PROG_CLK_pad, + input GPIO17_pad, + + + output t0_pad, + output t1_pad, + output t2_pad, + input t3_pad, + + output t0_is_output, + output t1_is_output, + output t2_is_output, + output t3_is_output + ); + + + parameter RESET_LENGTH=10; // Start off test with 10 cycle reset + parameter TEST_START_CYCLE=11; // Start the test on cycle 11 + + // Local signals + wire logic_reset; + wire prog_reset; + + wire logic_clk; + wire prog_clk; + + wire ccff_head; + wire configuration_done; + + // ****** GF12 Inputs / MPSoC Outputs ****** + assign RESET_pad = logic_reset; + assign SC_HEAD_pad = 0; + assign CCFF_HEAD_pad = ccff_head; + assign PRESET_pad = prog_reset; + assign PROG_CLK_pad = prog_clk; + assign CLK_pad = logic_clk; + assign TEST_EN_pad = 0; + // ************************* + + + // ******* MPSoC GPIO (4 inputs/outputs) ******* + assign t0_pad = 0; + assign t1_pad = 0; + assign t2_pad = 0; +// assign start_signal = t3_pad; + + assign t0_is_output = 1; + assign t1_is_output = 1; + assign t2_is_output = 1; + assign t3_is_output = 0; + // ******************************************** + + + // ########################### CLOCKS ########################### + + // CLK + // Divide pl_clk (50MHz) by 67108864 (2^26) times + clock_divider #( + .CLK_DIVIDER_SIZE(26) + ) logic_clk_divider ( + .clk_in(sys_clk), + .clk_out(logic_clk) + ); + + // ############################################################## + + + + + // ########################### RESETS ########################### + + // RESET + // Logic reset will be enabled in the first 2 clock cycles + reset_generator #( + .INITIAL_VALUE(1), + .ACTIVE_CYCLES(100) + ) logic_reset_generator( + .clk(sys_clk), + .pulse(logic_reset) + ); + + // ############################################################## + + + + + // ####################### CONFIGURATION ####################### + + // Configuration manager + configuration_manager config_manager ( + .clk_in(sys_clk), + .prog_reset(prog_reset), + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .configuration_done(configuration_done) + ); + + // ############################################################## + + +endmodule \ No newline at end of file From 3cfc42cdf933326c805bfdf840b1c9a0e371c6f5 Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Tue, 15 Jun 2021 14:16:31 -0600 Subject: [PATCH 02/41] added testbench CI --- .../benchmarks/config_loader/test_top.v | 176 ------------------ .../config_loader/bitstream_loader.v | 0 .../config_loader/configuration_manager.v | 0 .../signal_gen}/clock_divider.v | 0 .../signal_gen}/pulse_generator.v | 0 .../signal_gen}/reset_generator.v | 0 .../benchmark_sweep_test.sh | 11 ++ .../signal_gen/config/task.conf | 38 ++++ 8 files changed, 49 insertions(+), 176 deletions(-) delete mode 100644 openfpga_flow/benchmarks/config_loader/test_top.v rename openfpga_flow/benchmarks/{ => micro_benchmark}/config_loader/bitstream_loader.v (100%) rename openfpga_flow/benchmarks/{ => micro_benchmark}/config_loader/configuration_manager.v (100%) rename openfpga_flow/benchmarks/{config_loader => micro_benchmark/signal_gen}/clock_divider.v (100%) rename openfpga_flow/benchmarks/{config_loader => micro_benchmark/signal_gen}/pulse_generator.v (100%) rename openfpga_flow/benchmarks/{config_loader => micro_benchmark/signal_gen}/reset_generator.v (100%) create mode 100755 openfpga_flow/regression_test_scripts/benchmark_sweep_test.sh create mode 100644 openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf diff --git a/openfpga_flow/benchmarks/config_loader/test_top.v b/openfpga_flow/benchmarks/config_loader/test_top.v deleted file mode 100644 index e9a9c3783..000000000 --- a/openfpga_flow/benchmarks/config_loader/test_top.v +++ /dev/null @@ -1,176 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 03/11/2021 03:01:46 PM -// Design Name: -// Module Name: top -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - -`include "clock_divider.v" -`include "pulse_generator.v" - -module test_top ( - input sys_clk, - - - // Commented out i/o means it is floating and inaccessable to MPSoC - - // input LUT5_OUT_1_pad, - input GPIO3_pad, - input GPIO0_pad, - input CC_SPYPAD_1_pad, - // input PERF_SPYPAD_0_pad, - // input LUT5_OUT_0_pad, - output RESET_pad, - output CLK_pad, - // input GPIO4_pad, - // input GPIO5_pad, - input GPIO2_pad, - input GPIO1_pad, - input LUT6_OUT_0_pad, - input TEST_EN_pad, - input LUT4_OUT_0_pad, - // input LUT4_OUT_1_pad, - // input LUT4_OUT_2_pad, - // input LUT4_OUT_3_pad, - input SC_HEAD_pad, - input CCFF_TAIL_pad, - input GPIO23_pad, - input GPIO11_pad, - // input GPIO21_pad, - input GPIO22_pad, - input GPIO20_pad, - input GPIO10_pad, - input GPIO8_pad, - input GPIO9_pad, - input GPIO18_pad, - input GPIO19_pad, - input GPIO6_pad, - input GPIO7_pad, - input CC_SPYPAD_0_pad, - input CC_SPYPAD_2_pad, - input SC_TAIL_pad, - input COUT_SPYPAD_0_pad, - output CCFF_HEAD_pad, - // input SHIFTREG_SPY_pad, - // input SC_SPYPAD_0_pad, - output PRESET_pad, - input GPIO12_pad, - input GPIO16_pad, - // input GPIO15_pad, - // input GPIO14_pad, - input GPIO13_pad, - output PROG_CLK_pad, - input GPIO17_pad, - - - output t0_pad, - output t1_pad, - output t2_pad, - input t3_pad, - - output t0_is_output, - output t1_is_output, - output t2_is_output, - output t3_is_output - ); - - - parameter RESET_LENGTH=10; // Start off test with 10 cycle reset - parameter TEST_START_CYCLE=11; // Start the test on cycle 11 - - // Local signals - wire logic_reset; - wire prog_reset; - - wire logic_clk; - wire prog_clk; - - wire ccff_head; - wire configuration_done; - - // ****** GF12 Inputs / MPSoC Outputs ****** - assign RESET_pad = logic_reset; - assign SC_HEAD_pad = 0; - assign CCFF_HEAD_pad = ccff_head; - assign PRESET_pad = prog_reset; - assign PROG_CLK_pad = prog_clk; - assign CLK_pad = logic_clk; - assign TEST_EN_pad = 0; - // ************************* - - - // ******* MPSoC GPIO (4 inputs/outputs) ******* - assign t0_pad = 0; - assign t1_pad = 0; - assign t2_pad = 0; -// assign start_signal = t3_pad; - - assign t0_is_output = 1; - assign t1_is_output = 1; - assign t2_is_output = 1; - assign t3_is_output = 0; - // ******************************************** - - - // ########################### CLOCKS ########################### - - // CLK - // Divide pl_clk (50MHz) by 67108864 (2^26) times - clock_divider #( - .CLK_DIVIDER_SIZE(26) - ) logic_clk_divider ( - .clk_in(sys_clk), - .clk_out(logic_clk) - ); - - // ############################################################## - - - - - // ########################### RESETS ########################### - - // RESET - // Logic reset will be enabled in the first 2 clock cycles - reset_generator #( - .INITIAL_VALUE(1), - .ACTIVE_CYCLES(100) - ) logic_reset_generator( - .clk(sys_clk), - .pulse(logic_reset) - ); - - // ############################################################## - - - - - // ####################### CONFIGURATION ####################### - - // Configuration manager - configuration_manager config_manager ( - .clk_in(sys_clk), - .prog_reset(prog_reset), - .prog_clk(prog_clk), - .ccff_head(ccff_head), - .configuration_done(configuration_done) - ); - - // ############################################################## - - -endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/config_loader/bitstream_loader.v b/openfpga_flow/benchmarks/micro_benchmark/config_loader/bitstream_loader.v similarity index 100% rename from openfpga_flow/benchmarks/config_loader/bitstream_loader.v rename to openfpga_flow/benchmarks/micro_benchmark/config_loader/bitstream_loader.v diff --git a/openfpga_flow/benchmarks/config_loader/configuration_manager.v b/openfpga_flow/benchmarks/micro_benchmark/config_loader/configuration_manager.v similarity index 100% rename from openfpga_flow/benchmarks/config_loader/configuration_manager.v rename to openfpga_flow/benchmarks/micro_benchmark/config_loader/configuration_manager.v diff --git a/openfpga_flow/benchmarks/config_loader/clock_divider.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v similarity index 100% rename from openfpga_flow/benchmarks/config_loader/clock_divider.v rename to openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v diff --git a/openfpga_flow/benchmarks/config_loader/pulse_generator.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v similarity index 100% rename from openfpga_flow/benchmarks/config_loader/pulse_generator.v rename to openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v diff --git a/openfpga_flow/benchmarks/config_loader/reset_generator.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v similarity index 100% rename from openfpga_flow/benchmarks/config_loader/reset_generator.v rename to openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v diff --git a/openfpga_flow/regression_test_scripts/benchmark_sweep_test.sh b/openfpga_flow/regression_test_scripts/benchmark_sweep_test.sh new file mode 100755 index 000000000..01f278fe9 --- /dev/null +++ b/openfpga_flow/regression_test_scripts/benchmark_sweep_test.sh @@ -0,0 +1,11 @@ +#!/bin/bash + +set -e +source openfpga.sh +PYTHON_EXEC=python3.8 +############################################### +# OpenFPGA Shell with VPR8 +############################################## + +echo -e "Benchmark sweep tests"; +run-task benchmark_sweep/signal_gen --debug --show_thread_logs \ No newline at end of file diff --git a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf new file mode 100644 index 000000000..b1f3d4e47 --- /dev/null +++ b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf @@ -0,0 +1,38 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v +# bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v +# bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v + +[SYNTHESIS_PARAM] +bench0_top = pulse_generator +# bench1_top = reset_generator +# bench2_top = clock_divider + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist= From 4d4577bb835779a90578d65b902ac1aa9f058d6a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 30 Jun 2021 15:13:47 -0600 Subject: [PATCH 03/41] [Benchmark] Added multiple adder benchmarks to have better coverage in testing FPGA arch with adders --- .../micro_benchmark/adder/adder_16/adder_16.v | 21 ++++++ .../micro_benchmark/adder/adder_4/adder_4.v | 21 ++++++ .../micro_benchmark/adder/adder_6/adder_6.v | 21 ++++++ .../{ => adder}/adder_8/adder_8.act | 0 .../{ => adder}/adder_8/adder_8.eblif | 0 .../{ => adder}/adder_8/adder_8.v | 0 .../{ => adder}/adder_8/adder_8_out.v | 0 .../adder/adder_8/adder_8_post_synthesis.v | 65 +++++++++++++++++++ 8 files changed, 128 insertions(+) create mode 100644 openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/adder/adder_4/adder_4.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/adder/adder_6/adder_6.v rename openfpga_flow/benchmarks/micro_benchmark/{ => adder}/adder_8/adder_8.act (100%) rename openfpga_flow/benchmarks/micro_benchmark/{ => adder}/adder_8/adder_8.eblif (100%) rename openfpga_flow/benchmarks/micro_benchmark/{ => adder}/adder_8/adder_8.v (100%) rename openfpga_flow/benchmarks/micro_benchmark/{ => adder}/adder_8/adder_8_out.v (100%) create mode 100644 openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_post_synthesis.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v new file mode 100644 index 000000000..2e7d31076 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v @@ -0,0 +1,21 @@ +// Creating a scaleable adder + +module adder_16(cout, sum, a, b, cin); +parameter size = 6; /* declare a parameter. default required */ +output cout; +output [size-1:0] sum; // sum uses the size parameter +input cin; +input [size-1:0] a, b; // 'a' and 'b' use the size parameter + +assign {cout, sum} = a + b + cin; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_4/adder_4.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_4/adder_4.v new file mode 100644 index 000000000..b444bfa3a --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_4/adder_4.v @@ -0,0 +1,21 @@ +// Creating a scaleable adder + +module adder_4(cout, sum, a, b, cin); +parameter size = 4; /* declare a parameter. default required */ +output cout; +output [size-1:0] sum; // sum uses the size parameter +input cin; +input [size-1:0] a, b; // 'a' and 'b' use the size parameter + +assign {cout, sum} = a + b + cin; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_6/adder_6.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_6/adder_6.v new file mode 100644 index 000000000..74a09005d --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_6/adder_6.v @@ -0,0 +1,21 @@ +// Creating a scaleable adder + +module adder_6(cout, sum, a, b, cin); +parameter size = 6; /* declare a parameter. default required */ +output cout; +output [size-1:0] sum; // sum uses the size parameter +input cin; +input [size-1:0] a, b; // 'a' and 'b' use the size parameter + +assign {cout, sum} = a + b + cin; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.act b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.act similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.act rename to openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.act diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.eblif similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif rename to openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.eblif diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v rename to openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8_out.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_out.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8_out.v rename to openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_out.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_post_synthesis.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_post_synthesis.v new file mode 100644 index 000000000..1e7069e8c --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_post_synthesis.v @@ -0,0 +1,65 @@ +/* Generated by Yosys 0.9+2406 (git sha1 3a9968de, gcc 8.4.0 -fPIC -Os) */ + +module adder_8(\a[0] , \a[1] , \a[2] , \a[3] , \a[4] , \a[5] , \a[6] , \a[7] , \b[0] , \b[1] , \b[2] , \b[3] , \b[4] , \b[5] , \b[6] , \b[7] , cin, cout, \sum[0] , \sum[1] , \sum[2] , \sum[3] , \sum[4] , \sum[5] , \sum[6] , \sum[7] ); + wire _00_; + wire _01_; + wire _02_; + wire _03_; + wire _04_; + wire _05_; + wire _06_; + wire _07_; + wire _08_; + wire _09_; + wire _10_; + wire _11_; + wire _12_; + input \a[0] ; + input \a[1] ; + input \a[2] ; + input \a[3] ; + input \a[4] ; + input \a[5] ; + input \a[6] ; + input \a[7] ; + input \b[0] ; + input \b[1] ; + input \b[2] ; + input \b[3] ; + input \b[4] ; + input \b[5] ; + input \b[6] ; + input \b[7] ; + input cin; + output cout; + output \sum[0] ; + output \sum[1] ; + output \sum[2] ; + output \sum[3] ; + output \sum[4] ; + output \sum[5] ; + output \sum[6] ; + output \sum[7] ; + assign cout = 8'h8e >> { _00_, \a[7] , \b[7] }; + assign _08_ = 4'h8 >> { \a[5] , \b[5] }; + assign \sum[0] = 8'h96 >> { \a[0] , \b[0] , cin }; + assign \sum[1] = 8'h69 >> { _05_, \a[1] , \b[1] }; + assign \sum[2] = 16'h6a56 >> { _05_, \a[1] , \b[1] , _04_ }; + assign \sum[3] = 16'h9996 >> { _03_, _06_, \a[3] , \b[3] }; + assign \sum[4] = 8'h69 >> { _02_, \a[4] , \b[4] }; + assign \sum[5] = 8'h69 >> { _09_, \a[5] , \b[5] }; + assign _09_ = 8'h71 >> { _02_, \a[4] , \b[4] }; + assign \sum[6] = 16'h9996 >> { _01_, _08_, \a[6] , \b[6] }; + assign \sum[7] = 8'h69 >> { _00_, \a[7] , \b[7] }; + assign _00_ = 16'h011f >> { \a[6] , \b[6] , _01_, _08_ }; + assign _01_ = 16'h4054 >> { _02_, \a[4] , \b[4] , _07_ }; + assign _02_ = 16'h011f >> { \a[3] , \b[3] , _03_, _06_ }; + assign _03_ = 16'h80a8 >> { _05_, \a[1] , \b[1] , _04_ }; + assign _04_ = 4'h6 >> { \a[2] , \b[2] }; + assign _05_ = 8'h17 >> { \a[0] , \b[0] , cin }; + assign _06_ = 4'h8 >> { \a[2] , \b[2] }; + assign _07_ = 4'h1 >> { \a[5] , \b[5] }; + assign _10_ = 1'h0; + assign _11_ = 1'h1; + assign _12_ = 1'hx; +endmodule From 83d177b13b11a9a2d77a00612f570667bdcdb38c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 30 Jun 2021 15:14:24 -0600 Subject: [PATCH 04/41] [Test] Deploy the newly added adder benchmarks to tests --- .../lut_adder_test/config/task.conf | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf index 4f501a1c3..12f1bebe1 100644 --- a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf @@ -27,18 +27,20 @@ yosys_args = -family qlf_k4n8 -no_ff_map arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml [BENCHMARKS] -bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_4/adder_4.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_6/adder_6.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.v +bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v [SYNTHESIS_PARAM] bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys -bench1_top = adder_8 +bench0_top = adder_4 +bench1_top = adder_6 +bench2_top = adder_8 +bench3_top = adder_16 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -########################## -# The output verilog of yosys is not synthesizable!!! -# Turn off verification for now -# SHOULD focus on fixing the Verilog problem and run verification at the end of the flow end_flow_with_test= vpr_fpga_verilog_formal_verification_top_netlist= From a89853747404ea63eb9378763771d9d295069a4b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 30 Jun 2021 15:29:13 -0600 Subject: [PATCH 05/41] [Benchmark] Remove redundant post-synthesis netlist for ``adder_8`` --- .../adder/adder_8/adder_8_post_synthesis.v | 65 ------------------- 1 file changed, 65 deletions(-) delete mode 100644 openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_post_synthesis.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_post_synthesis.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_post_synthesis.v deleted file mode 100644 index 1e7069e8c..000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_post_synthesis.v +++ /dev/null @@ -1,65 +0,0 @@ -/* Generated by Yosys 0.9+2406 (git sha1 3a9968de, gcc 8.4.0 -fPIC -Os) */ - -module adder_8(\a[0] , \a[1] , \a[2] , \a[3] , \a[4] , \a[5] , \a[6] , \a[7] , \b[0] , \b[1] , \b[2] , \b[3] , \b[4] , \b[5] , \b[6] , \b[7] , cin, cout, \sum[0] , \sum[1] , \sum[2] , \sum[3] , \sum[4] , \sum[5] , \sum[6] , \sum[7] ); - wire _00_; - wire _01_; - wire _02_; - wire _03_; - wire _04_; - wire _05_; - wire _06_; - wire _07_; - wire _08_; - wire _09_; - wire _10_; - wire _11_; - wire _12_; - input \a[0] ; - input \a[1] ; - input \a[2] ; - input \a[3] ; - input \a[4] ; - input \a[5] ; - input \a[6] ; - input \a[7] ; - input \b[0] ; - input \b[1] ; - input \b[2] ; - input \b[3] ; - input \b[4] ; - input \b[5] ; - input \b[6] ; - input \b[7] ; - input cin; - output cout; - output \sum[0] ; - output \sum[1] ; - output \sum[2] ; - output \sum[3] ; - output \sum[4] ; - output \sum[5] ; - output \sum[6] ; - output \sum[7] ; - assign cout = 8'h8e >> { _00_, \a[7] , \b[7] }; - assign _08_ = 4'h8 >> { \a[5] , \b[5] }; - assign \sum[0] = 8'h96 >> { \a[0] , \b[0] , cin }; - assign \sum[1] = 8'h69 >> { _05_, \a[1] , \b[1] }; - assign \sum[2] = 16'h6a56 >> { _05_, \a[1] , \b[1] , _04_ }; - assign \sum[3] = 16'h9996 >> { _03_, _06_, \a[3] , \b[3] }; - assign \sum[4] = 8'h69 >> { _02_, \a[4] , \b[4] }; - assign \sum[5] = 8'h69 >> { _09_, \a[5] , \b[5] }; - assign _09_ = 8'h71 >> { _02_, \a[4] , \b[4] }; - assign \sum[6] = 16'h9996 >> { _01_, _08_, \a[6] , \b[6] }; - assign \sum[7] = 8'h69 >> { _00_, \a[7] , \b[7] }; - assign _00_ = 16'h011f >> { \a[6] , \b[6] , _01_, _08_ }; - assign _01_ = 16'h4054 >> { _02_, \a[4] , \b[4] , _07_ }; - assign _02_ = 16'h011f >> { \a[3] , \b[3] , _03_, _06_ }; - assign _03_ = 16'h80a8 >> { _05_, \a[1] , \b[1] , _04_ }; - assign _04_ = 4'h6 >> { \a[2] , \b[2] }; - assign _05_ = 8'h17 >> { \a[0] , \b[0] , cin }; - assign _06_ = 4'h8 >> { \a[2] , \b[2] }; - assign _07_ = 4'h1 >> { \a[5] , \b[5] }; - assign _10_ = 1'h0; - assign _11_ = 1'h1; - assign _12_ = 1'hx; -endmodule From fab2b069f0bb83dc27530c70e8f79fd2612024e9 Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Wed, 30 Jun 2021 16:18:09 -0600 Subject: [PATCH 06/41] added signal gen regression test to shell script --- .../config_loader/bitstream_loader.v | 143 ++++-------------- .../micro_benchmark_reg_test.sh | 3 + 2 files changed, 34 insertions(+), 112 deletions(-) diff --git a/openfpga_flow/benchmarks/micro_benchmark/config_loader/bitstream_loader.v b/openfpga_flow/benchmarks/micro_benchmark/config_loader/bitstream_loader.v index 68b04aee1..69a92ff92 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/config_loader/bitstream_loader.v +++ b/openfpga_flow/benchmarks/micro_benchmark/config_loader/bitstream_loader.v @@ -38,35 +38,26 @@ module bitstream_loader( wire bram_output; assign config_chain_head = bram_output; - RAMB18E1 #( - // Address Collision Mode: "PERFORMANCE" or "DELAYED_WRITE" - .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), - // Collision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE") - .SIM_COLLISION_CHECK("ALL"), - // RAM Mode: "SDP" or "TDP" - .RAM_MODE("TDP"), - // READ_WIDTH_A/B, WRITE_WIDTH_A/B: Read/write width per port - .READ_WIDTH_A(1), // 0-72 - .READ_WIDTH_B(0), // 0-18 - .WRITE_WIDTH_A(0), // 0-18 - .WRITE_WIDTH_B(0), // 0-72 + EFX_RAM_5K #( + .READ_WIDTH(1), + .WRITE_WIDTH(0), - .INIT_00(256'h00000000000000000000000000000000000000000000007f00000000000000ff), - .INIT_01(256'h0000fff8ffffffff000000000000000000000000000000000000000000000000), - .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_04(256'h00000003f8000000000000000000000000000000000000000000000000000000), - .INIT_05(256'h0000000000000000078000000000000000000000000000000000000000000000), - .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0(256'h00000000000000000000000000000000000000000000007f00000000000000ff), + .INIT_1(256'h0000fff8ffffffff000000000000000000000000000000000000000000000000), + .INIT_2(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4(256'h00000003f8000000000000000000000000000000000000000000000000000000), + .INIT_5(256'h0000000000000000078000000000000000000000000000000000000000000000), + .INIT_6(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_8(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_9(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), @@ -75,92 +66,20 @@ module bitstream_loader( .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0021000000000000000000000000000000000000000000000000000000000000), - .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), - .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), - - - - // RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE") - .RSTREG_PRIORITY_A("RSTREG"), - .RSTREG_PRIORITY_B("RSTREG"), - // SRVAL_A, SRVAL_B: Set/reset value for output - .SRVAL_A(18'hFFFFF), - .SRVAL_B(18'h00000), - // Simulation Device: Must be set to "7SERIES" for simulation behavior - .SIM_DEVICE("7SERIES"), - // WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE") - .WRITE_MODE_A("WRITE_FIRST"), - .WRITE_MODE_B("WRITE_FIRST") ) - RAMB18E1_inst ( + EFX_RAM_5K_inst ( // Port A Data: 16-bit (each) output: Port A data - .DOADO(bram_output), // 16-bit output: A port data/LSB data - .DOPADOP(), // 2-bit output: A port parity/LSB parity - // Port B Data: 16-bit (each) output: Port B data - .DOBDO(), // 16-bit output: B port data/MSB data - .DOPBDOP(), // 2-bit output: B port parity/MSB parity - // Port A Address/Control Signals: 14-bit (each) input: Port A address and control signals (read port - // when RAM_MODE="SDP") - .ADDRARDADDR(bram_addr), // 14-bit input: A port address/Read address - .CLKARDCLK(~prog_clk), // 1-bit input: A port clock/Read clock - .ENARDEN(1'b1), // 1-bit input: A port enable/Read enable - .REGCEAREGCE(1'b1), // 1-bit input: A port register enable/Register enable - .RSTRAMARSTRAM(0), // 1-bit input: A port set/reset - .RSTREGARSTREG(0), // 1-bit input: A port register set/reset - .WEA(2'b00), // 2-bit input: A port write enable - // Port A Data: 16-bit (each) input: Port A data - .DIADI(0), // 16-bit input: A port data/LSB data - .DIPADIP(0), // 2-bit input: A port parity/LSB parity - // Port B Address/Control Signals: 14-bit (each) input: Port B address and control signals (write port - // when RAM_MODE="SDP") - .ADDRBWRADDR(0), // 14-bit input: B port address/Write address - .CLKBWRCLK(0), // 1-bit input: B port clock/Write clock - .ENBWREN(0), // 1-bit input: B port enable/Write enable - .REGCEB(0), // 1-bit input: B port register enable - .RSTRAMB(0), // 1-bit input: B port set/reset - .RSTREGB(0), // 1-bit input: B port register set/reset - .WEBWE(0), // 4-bit input: B port write enable/Write enable - // Port B Data: 16-bit (each) input: Port B data - .DIBDI(0), // 16-bit input: B port data/MSB data - .DIPBDIP(0) // 2-bit input: B port parity/MSB parity + .WDATA(0), // Write data + .WADDR(0), // Write address + .WE(0), // Write enable + + .WCLK(0), + .WCLKE(0), + + .RDATA(bram_output), + .RADDR(bram_addr), + .RE(1'b1), + .RCLK(prog_clk) ); diff --git a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh index 28b24aef3..0790421bb 100755 --- a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh @@ -15,3 +15,6 @@ run-task benchmark_sweep/mac_units --debug --show_thread_logs # Otherwise, it will fail run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs #python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim + + +run-task benchmark_sweep/signal_gen --debug --show_thread_logs From db9231c2251a6be9e20f0c75181b596d54a6a783 Mon Sep 17 00:00:00 2001 From: ANDREW HARRIS POND Date: Thu, 1 Jul 2021 13:52:28 -0600 Subject: [PATCH 07/41] tests failing with initial blocks --- .../signal_gen/clock_divider.v | 8 +++---- .../signal_gen/pulse_generator.v | 14 ++++++------ .../benchmark_sweep_test.sh | 11 ---------- .../micro_benchmark_reg_test.sh | 7 +++--- .../signal_gen/config/task.conf | 22 ++++++++++++------- 5 files changed, 29 insertions(+), 33 deletions(-) delete mode 100755 openfpga_flow/regression_test_scripts/benchmark_sweep_test.sh diff --git a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v index 4127cd9f3..8172b7c6d 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v +++ b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v @@ -29,10 +29,10 @@ module clock_divider ( reg [CLK_DIVIDER_SIZE - 1:0] clkdiv_counter; - initial begin - clkdiv_counter <= 0; - clk_out <= 0; - end + // initial begin + // clkdiv_counter <= 0; + // clk_out <= 0; + // end // Divide pl_clk (50MHz) to 1MHz always @(posedge clk_in) begin diff --git a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v index a73fc37f6..ff3391d55 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v +++ b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v @@ -36,13 +36,13 @@ module pulse_generator( reg pulse_start; reg pulse_end; - initial begin - pulse <= INITIAL_VALUE; - pulse_start <= 1'b0; - pulse_end <= 1'b0; - wait_cycle_counter <= 0; - pulse_width_counter <= 0; - end + // initial begin + // pulse <= INITIAL_VALUE; + // pulse_start <= 1'b0; + // pulse_end <= 1'b0; + // wait_cycle_counter <= 0; + // pulse_width_counter <= 0; + // end // Wait a number of clock cycles, hold the initial value always @(posedge clk_in) begin diff --git a/openfpga_flow/regression_test_scripts/benchmark_sweep_test.sh b/openfpga_flow/regression_test_scripts/benchmark_sweep_test.sh deleted file mode 100755 index 01f278fe9..000000000 --- a/openfpga_flow/regression_test_scripts/benchmark_sweep_test.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/bash - -set -e -source openfpga.sh -PYTHON_EXEC=python3.8 -############################################### -# OpenFPGA Shell with VPR8 -############################################## - -echo -e "Benchmark sweep tests"; -run-task benchmark_sweep/signal_gen --debug --show_thread_logs \ No newline at end of file diff --git a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh index 0790421bb..44ecacd30 100755 --- a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh @@ -7,14 +7,15 @@ PYTHON_EXEC=python3.8 # OpenFPGA Shell with VPR8 ############################################## echo -e "Micro benchmark regression tests"; -run-task benchmark_sweep/counter --debug --show_thread_logs -run-task benchmark_sweep/mac_units --debug --show_thread_logs +# run-task benchmark_sweep/counter --debug --show_thread_logs +# run-task benchmark_sweep/mac_units --debug --show_thread_logs # Verify MCNC big20 benchmark suite with ModelSim # Please make sure you have ModelSim installed in the environment # Otherwise, it will fail -run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs +# run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs #python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim +# run-task basic_tests/full_testbench/configuration_chain --debug --show_thread_logs run-task benchmark_sweep/signal_gen --debug --show_thread_logs diff --git a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf index b1f3d4e47..6158af998 100644 --- a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf @@ -16,23 +16,29 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v -# bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v -# bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v +# bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v [SYNTHESIS_PARAM] -bench0_top = pulse_generator -# bench1_top = reset_generator -# bench2_top = clock_divider +bench0_top = clock_divider +bench0_chan_width = 300 + +bench1_top = pulse_generator +bench1_chan_width = 300 + +# bench2_top = reset_generator +# bench2_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= -#vpr_fpga_verilog_formal_verification_top_netlist= From 2567fbee05ac26d2b6c1a015464f03267945c586 Mon Sep 17 00:00:00 2001 From: ANDREW HARRIS POND Date: Thu, 1 Jul 2021 15:28:59 -0600 Subject: [PATCH 08/41] ready to merge --- .../signal_gen/clock_divider.v | 13 +++++++---- .../signal_gen/pulse_generator.v | 22 ++++++++++++------- .../signal_gen/reset_generator.v | 5 +++++ .../micro_benchmark_reg_test.sh | 8 +++---- .../signal_gen/config/task.conf | 6 ++--- 5 files changed, 34 insertions(+), 20 deletions(-) diff --git a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v index 8172b7c6d..3cb3f9899 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v +++ b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v @@ -19,6 +19,9 @@ // ////////////////////////////////////////////////////////////////////////////////// +// Uncomment if using Vivado to synthesize the design. This will enable the initial block +// If using Yosys, initial blocks are not supported, and cannot be included. +// `define VIVADO_SYNTHESIS module clock_divider ( input clk_in, @@ -29,10 +32,12 @@ module clock_divider ( reg [CLK_DIVIDER_SIZE - 1:0] clkdiv_counter; - // initial begin - // clkdiv_counter <= 0; - // clk_out <= 0; - // end +`ifdef VIVADO_SYNTHESIS + initial begin + clkdiv_counter <= 0; + clk_out <= 0; + end +`endif // Divide pl_clk (50MHz) to 1MHz always @(posedge clk_in) begin diff --git a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v index ff3391d55..1f092e6a0 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v +++ b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v @@ -19,6 +19,10 @@ // ////////////////////////////////////////////////////////////////////////////////// +// Uncomment if using Vivado to synthesize the design. This will enable the initial block +// If using Yosys, initial blocks are not supported, and cannot be included. +// `define VIVADO_SYNTHESIS + module pulse_generator( input clk_in, input repeated, // Specify if the pulse should be generated repeatedly @@ -35,14 +39,16 @@ module pulse_generator( reg [PULSE_COUNTER_SIZE - 1 : 0] pulse_width_counter; reg pulse_start; reg pulse_end; - - // initial begin - // pulse <= INITIAL_VALUE; - // pulse_start <= 1'b0; - // pulse_end <= 1'b0; - // wait_cycle_counter <= 0; - // pulse_width_counter <= 0; - // end + +`ifdef VIVADO_SYNTHESIS + initial begin + pulse <= INITIAL_VALUE; + pulse_start <= 1'b0; + pulse_end <= 1'b0; + wait_cycle_counter <= 0; + pulse_width_counter <= 0; + end +`endif // Wait a number of clock cycles, hold the initial value always @(posedge clk_in) begin diff --git a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v index f949e722a..6de4b6980 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v +++ b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v @@ -19,6 +19,9 @@ // ////////////////////////////////////////////////////////////////////////////////// +// Uncomment if using Vivado to synthesize the design. This will enable the initial block +// If using Yosys, initial blocks are not supported, and cannot be included. +// `define VIVADO_SYNTHESIS module reset_generator( input clk, @@ -30,10 +33,12 @@ module reset_generator( reg [ACTIVE_CYCLES<=2 ? 2 : $clog2(ACTIVE_CYCLES) - 1 : 0] active_cycle_counter; +`ifdef VIVADO_SYNTHESIS initial begin pulse <= INITIAL_VALUE; active_cycle_counter <= 0; end +`endif // Wait a number of clock cycles, hold the initial value always @(posedge clk) begin diff --git a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh index 44ecacd30..5f958e261 100755 --- a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh @@ -7,15 +7,13 @@ PYTHON_EXEC=python3.8 # OpenFPGA Shell with VPR8 ############################################## echo -e "Micro benchmark regression tests"; -# run-task benchmark_sweep/counter --debug --show_thread_logs -# run-task benchmark_sweep/mac_units --debug --show_thread_logs +run-task benchmark_sweep/counter --debug --show_thread_logs +run-task benchmark_sweep/mac_units --debug --show_thread_logs # Verify MCNC big20 benchmark suite with ModelSim # Please make sure you have ModelSim installed in the environment # Otherwise, it will fail -# run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs +run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs #python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim - -# run-task basic_tests/full_testbench/configuration_chain --debug --show_thread_logs run-task benchmark_sweep/signal_gen --debug --show_thread_logs diff --git a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf index 6158af998..c6306d7da 100644 --- a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf @@ -27,15 +27,15 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v -bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v +# bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v # bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v [SYNTHESIS_PARAM] bench0_top = clock_divider bench0_chan_width = 300 -bench1_top = pulse_generator -bench1_chan_width = 300 +# bench1_top = pulse_generator +# bench1_chan_width = 300 # bench2_top = reset_generator # bench2_chan_width = 300 From 006b54c4bcc42dd09de78f2b45c83a3091df2b81 Mon Sep 17 00:00:00 2001 From: ANDREW HARRIS POND Date: Thu, 1 Jul 2021 15:35:39 -0600 Subject: [PATCH 09/41] ready for merge --- .../benchmark_sweep/signal_gen/config/task.conf | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf index c6306d7da..9ada9e960 100644 --- a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf @@ -27,18 +27,18 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v -# bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v -# bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v [SYNTHESIS_PARAM] bench0_top = clock_divider bench0_chan_width = 300 -# bench1_top = pulse_generator -# bench1_chan_width = 300 +bench1_top = pulse_generator +bench1_chan_width = 300 -# bench2_top = reset_generator -# bench2_chan_width = 300 +bench2_top = reset_generator +bench2_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= From 808821bb8c6fcd89cf2e53d5fb42e46d87ca95fd Mon Sep 17 00:00:00 2001 From: ANDREW HARRIS POND Date: Thu, 1 Jul 2021 16:40:03 -0600 Subject: [PATCH 10/41] fixed errors --- .../signal_gen/reset_generator.v | 41 ++++++++++--------- 1 file changed, 21 insertions(+), 20 deletions(-) diff --git a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v index 6de4b6980..84e957cb1 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v +++ b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v @@ -24,29 +24,30 @@ // `define VIVADO_SYNTHESIS module reset_generator( - input clk, - output reg pulse + input clk, + output reg pulse ); + + parameter INITIAL_VALUE=0; // Define the initial value for the pulse, either 0 or 1; The pulse logic level will be a flip over the initial value + parameter ACTIVE_CYCLES=0; // Define the number of clock cycles to wait before the pulse is applied - parameter INITIAL_VALUE=0; // Define the initial value for the pulse, either 0 or 1; The pulse logic level will be a flip over the initial value - parameter ACTIVE_CYCLES=0; // Define the number of clock cycles to wait before the pulse is applied - - reg [ACTIVE_CYCLES<=2 ? 2 : $clog2(ACTIVE_CYCLES) - 1 : 0] active_cycle_counter; - + reg [ACTIVE_CYCLES<=2 ? 2 : $clog2(ACTIVE_CYCLES) - 1 : 0] active_cycle_counter; + `ifdef VIVADO_SYNTHESIS - initial begin - pulse <= INITIAL_VALUE; - active_cycle_counter <= 0; - end -`endif - - // Wait a number of clock cycles, hold the initial value - always @(posedge clk) begin - if (active_cycle_counter == ACTIVE_CYCLES) begin - pulse <= ~INITIAL_VALUE; - end else begin - active_cycle_counter <= active_cycle_counter + 1; + initial begin + clkdiv_counter <= 0; + active_cycle_counter <= 0; + pulse <= INITIAL_VALUE; end - end +`endif + // Wait a number of clock cycles, hold the initial value + always @(posedge clk) begin + if (active_cycle_counter == ACTIVE_CYCLES) begin + pulse <= ~pulse; + end else begin + active_cycle_counter <= active_cycle_counter + 1; + end + end + endmodule From 1d281765ea6d520b96a27f3c4e50fa3d25110ad6 Mon Sep 17 00:00:00 2001 From: ANDREW HARRIS POND Date: Thu, 1 Jul 2021 16:42:04 -0600 Subject: [PATCH 11/41] fixed tab spacing --- .../signal_gen/reset_generator.v | 22 +++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v index 84e957cb1..bbb73e440 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v +++ b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v @@ -24,21 +24,21 @@ // `define VIVADO_SYNTHESIS module reset_generator( - input clk, - output reg pulse - ); - + input clk, + output reg pulse + ); + parameter INITIAL_VALUE=0; // Define the initial value for the pulse, either 0 or 1; The pulse logic level will be a flip over the initial value parameter ACTIVE_CYCLES=0; // Define the number of clock cycles to wait before the pulse is applied reg [ACTIVE_CYCLES<=2 ? 2 : $clog2(ACTIVE_CYCLES) - 1 : 0] active_cycle_counter; - + `ifdef VIVADO_SYNTHESIS - initial begin - clkdiv_counter <= 0; - active_cycle_counter <= 0; - pulse <= INITIAL_VALUE; - end + initial begin + clkdiv_counter <= 0; + active_cycle_counter <= 0; + pulse <= INITIAL_VALUE; + end `endif // Wait a number of clock cycles, hold the initial value @@ -49,5 +49,5 @@ module reset_generator( active_cycle_counter <= active_cycle_counter + 1; end end - + endmodule From d0e4f8521f89e804c6bd9e139a3bff946876728f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Jul 2021 19:58:54 -0600 Subject: [PATCH 12/41] [Tool] Bug fix on the reset stimuli --- .../src/fpga_verilog/verilog_formal_random_top_testbench.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp index 7b54ceb44..7194f208f 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp @@ -230,7 +230,7 @@ void print_verilog_random_testbench_reset_stimuli(std::fstream& fp, */ fp << "\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ");" << std::endl; fp << "\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ");" << std::endl; - print_verilog_wire_connection(fp, reset_port, reset_port, true); + print_verilog_register_connection(fp, reset_port, reset_port, true); fp << "\tend" << std::endl; } From 81f9dff9ff413ab6c27d2a96cb4ce28eb2c372dd Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Thu, 1 Jul 2021 22:19:53 -0600 Subject: [PATCH 13/41] [Flow] Allows benchmark specific var declaraton --- openfpga_flow/scripts/run_fpga_task.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 0cb6612e1..1a373df9b 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -271,6 +271,9 @@ def generate_each_task_actions(taskname): fallback=ys_rewrite_for_task_common) CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width", fallback=chan_width_common) + for eachKey, eachValue in SynthSection.items(): + eachKey = eachKey.replace(bech_name+"_","") + CurrBenchPara[eachKey] = eachValue if GeneralSection.get("fpga_flow") == "vpr_blif": # Check if activity file exist @@ -320,7 +323,7 @@ def generate_each_task_actions(taskname): flow_run_dir = get_flow_rundir(arch, "bench" + str(benchmark_list.index(bench)) + "_" + bench["top_module"], lbl) else: flow_run_dir = get_flow_rundir(arch, bench["top_module"], lbl) - + command = create_run_command( curr_job_dir=flow_run_dir, archfile=arch, From 1de1f2f2e23f5caa14f859a77a427b48590a0ba8 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Thu, 1 Jul 2021 22:26:00 -0600 Subject: [PATCH 14/41] [FLOW] Variable in capital case --- openfpga_flow/scripts/run_fpga_task.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 1a373df9b..66ac0f838 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -272,7 +272,7 @@ def generate_each_task_actions(taskname): CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width", fallback=chan_width_common) for eachKey, eachValue in SynthSection.items(): - eachKey = eachKey.replace(bech_name+"_","") + eachKey = eachKey.replace(bech_name+"_","").upper() CurrBenchPara[eachKey] = eachValue if GeneralSection.get("fpga_flow") == "vpr_blif": From 9074bffa68f8bcb3c142855bc15ecc08bf49c434 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Jul 2021 23:43:19 -0600 Subject: [PATCH 15/41] [Tool] Support customized default value in pin constraint file --- libopenfpga/libpcf/src/pin_constraints.cpp | 51 +++++++++++++++++++ libopenfpga/libpcf/src/pin_constraints.h | 38 ++++++++++++++ .../libpcf/src/read_xml_pin_constraints.cpp | 8 +++ .../libpcf/src/write_xml_pin_constraints.cpp | 1 + .../verilog_formal_random_top_testbench.cpp | 4 ++ .../fpga_verilog/verilog_top_testbench.cpp | 8 ++- 6 files changed, 109 insertions(+), 1 deletion(-) diff --git a/libopenfpga/libpcf/src/pin_constraints.cpp b/libopenfpga/libpcf/src/pin_constraints.cpp index 25cd1048d..bc68b3bd8 100644 --- a/libopenfpga/libpcf/src/pin_constraints.cpp +++ b/libopenfpga/libpcf/src/pin_constraints.cpp @@ -60,6 +60,36 @@ openfpga::BasicPort PinConstraints::net_pin(const std::string& net) const { return constrained_pin; } +PinConstraints::e_logic_level PinConstraints::net_default_value(const std::string& net) const { + PinConstraints::e_logic_level logic_level = PinConstraints::NUM_LOGIC_LEVELS; + for (const PinConstraintId& pin_constraint : pin_constraints()) { + if (net == pin_constraint_nets_[pin_constraint]) { + logic_level = pin_constraint_net_default_values_[pin_constraint]; + break; + } + } + return logic_level; +} + +std::string PinConstraints::net_default_value_to_string(const PinConstraintId& pin_constraint) const { + VTR_ASSERT(valid_pin_constraint_id(pin_constraint)); + if (PinConstraints::LOGIC_HIGH == pin_constraint_net_default_values_[pin_constraint]) { + return std::string("1"); + } else if (PinConstraints::LOGIC_LOW == pin_constraint_net_default_values_[pin_constraint]) { + return std::string("0"); + } + return std::string(); +} + +size_t PinConstraints::net_default_value_to_int(const std::string& net) const { + if (PinConstraints::LOGIC_HIGH == net_default_value(net)) { + return 1; + } else if (PinConstraints::LOGIC_LOW == net_default_value(net)) { + return 0; + } + return -1; +} + bool PinConstraints::empty() const { return 0 == pin_constraint_ids_.size(); } @@ -71,6 +101,7 @@ void PinConstraints::reserve_pin_constraints(const size_t& num_pin_constraints) pin_constraint_ids_.reserve(num_pin_constraints); pin_constraint_pins_.reserve(num_pin_constraints); pin_constraint_nets_.reserve(num_pin_constraints); + pin_constraint_net_default_values_.reserve(num_pin_constraints); } PinConstraintId PinConstraints::create_pin_constraint(const openfpga::BasicPort& pin, @@ -81,10 +112,21 @@ PinConstraintId PinConstraints::create_pin_constraint(const openfpga::BasicPort& pin_constraint_ids_.push_back(pin_constraint_id); pin_constraint_pins_.push_back(pin); pin_constraint_nets_.push_back(net); + pin_constraint_net_default_values_.push_back(PinConstraints::NUM_LOGIC_LEVELS); return pin_constraint_id; } +void PinConstraints::set_net_default_value(const PinConstraintId& pin_constraint, + const std::string& default_value) { + VTR_ASSERT(valid_pin_constraint_id(pin_constraint)); + if (default_value == std::string("1")) { + pin_constraint_net_default_values_[pin_constraint] = PinConstraints::LOGIC_HIGH; + } else if (default_value == std::string("0")) { + pin_constraint_net_default_values_[pin_constraint] = PinConstraints::LOGIC_LOW; + } +} + /************************************************************************ * Internal invalidators/validators ***********************************************************************/ @@ -100,3 +142,12 @@ bool PinConstraints::unconstrained_net(const std::string& net) const { bool PinConstraints::unmapped_net(const std::string& net) const { return std::string(PIN_CONSTRAINT_OPEN_NET) == net; } + +bool PinConstraints::valid_net_default_value(const PinConstraintId& pin_constraint) const { + VTR_ASSERT(valid_pin_constraint_id(pin_constraint)); + return PinConstraints::NUM_LOGIC_LEVELS != pin_constraint_net_default_values_[pin_constraint]; +} + +bool PinConstraints::valid_net_default_value(const std::string& net) const { + return PinConstraints::NUM_LOGIC_LEVELS != net_default_value(net); +} diff --git a/libopenfpga/libpcf/src/pin_constraints.h b/libopenfpga/libpcf/src/pin_constraints.h index 3ea3aad2f..a60f0aae4 100644 --- a/libopenfpga/libpcf/src/pin_constraints.h +++ b/libopenfpga/libpcf/src/pin_constraints.h @@ -41,6 +41,12 @@ class PinConstraints { typedef vtr::vector::const_iterator pin_constraint_iterator; /* Create range */ typedef vtr::Range pin_constraint_range; + /* Logic value */ + enum e_logic_level { + LOGIC_HIGH, + LOGIC_LOW, + NUM_LOGIC_LEVELS + }; public: /* Constructors */ PinConstraints(); public: /* Accessors: aggregates */ @@ -63,6 +69,21 @@ class PinConstraints { */ openfpga::BasicPort net_pin(const std::string& net) const; + /* Find the default value that a net is constrained to + * If not found, return an invalid value + */ + e_logic_level net_default_value(const std::string& net) const; + + /* Generate the string of the default value + * If not found, return an empty string + */ + std::string net_default_value_to_string(const PinConstraintId& pin_constraint) const; + + /* Generate the integer representation of the default value + * If not found, return -1 + */ + size_t net_default_value_to_int(const std::string& net) const; + /* Check if there are any pin constraints */ bool empty() const; @@ -74,6 +95,10 @@ class PinConstraints { PinConstraintId create_pin_constraint(const openfpga::BasicPort& pin, const std::string& net); + /* Set the default value for the net under a given pin constraint */ + void set_net_default_value(const PinConstraintId& pin_constraint, + const std::string& default_value); + public: /* Public invalidators/validators */ /* Show if the pin constraint id is a valid for data queries */ bool valid_pin_constraint_id(const PinConstraintId& pin_constraint_id) const; @@ -91,6 +116,16 @@ class PinConstraints { * - net() */ bool unmapped_net(const std::string& net) const; + + /* Check if default value is a valid one or not + * This is to check if the default value is constrained or not + */ + bool valid_net_default_value(const PinConstraintId& pin_constraint) const; + + /* Check if default value is a valid one or not + * This is to check if the default value is constrained or not + */ + bool valid_net_default_value(const std::string& net) const; private: /* Internal data */ /* Unique ids for each design constraint */ vtr::vector pin_constraint_ids_; @@ -100,6 +135,9 @@ class PinConstraints { /* Nets to constraint */ vtr::vector pin_constraint_nets_; + + /* Default value of the nets to constraint */ + vtr::vector pin_constraint_net_default_values_; }; #endif diff --git a/libopenfpga/libpcf/src/read_xml_pin_constraints.cpp b/libopenfpga/libpcf/src/read_xml_pin_constraints.cpp index b0c662da5..98527cb32 100644 --- a/libopenfpga/libpcf/src/read_xml_pin_constraints.cpp +++ b/libopenfpga/libpcf/src/read_xml_pin_constraints.cpp @@ -41,6 +41,14 @@ void read_xml_pin_constraint(pugi::xml_node& xml_pin_constraint, archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_pin_constraint), "Fail to create pin constraint!\n"); } + + /* Set default value if defined */ + std::string default_value = get_attribute(xml_pin_constraint, "default_value", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string(); + pin_constraints.set_net_default_value(pin_constraint_id, default_value); + if (!default_value.empty() && !pin_constraints.valid_net_default_value(pin_constraint_id)) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_pin_constraint), + "Invalid default value for pin constraints. Expect [0|1]!\n"); + } } /******************************************************************** diff --git a/libopenfpga/libpcf/src/write_xml_pin_constraints.cpp b/libopenfpga/libpcf/src/write_xml_pin_constraints.cpp index 80a664f3f..ef728be95 100644 --- a/libopenfpga/libpcf/src/write_xml_pin_constraints.cpp +++ b/libopenfpga/libpcf/src/write_xml_pin_constraints.cpp @@ -44,6 +44,7 @@ int write_xml_pin_constraint(std::fstream& fp, write_xml_attribute(fp, "pin", generate_xml_port_name(pin_constraints.pin(pin_constraint)).c_str()); write_xml_attribute(fp, "net", pin_constraints.net(pin_constraint).c_str()); + write_xml_attribute(fp, "default_value", pin_constraints.net_default_value_to_string(pin_constraint).c_str()); fp << "/>" << "\n"; diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp index 7194f208f..6be38f425 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp @@ -213,6 +213,10 @@ void print_verilog_random_testbench_reset_stimuli(std::fstream& fp, if (1 == global_ports.global_port_default_value(find_fabric_global_port(global_ports, module_manager, pin_constraints.net_pin(block_name)))) { initial_value = 0; } + /* Pin constraints has the final decision on the default value */ + if (pin_constraints.valid_net_default_value(block_name)) { + initial_value = pin_constraints.net_default_value_to_int(block_name); + } fp << "initial" << std::endl; fp << "\tbegin" << std::endl; diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 47300ce1e..1e82b7e81 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -1789,11 +1789,17 @@ void print_verilog_top_testbench_reset_stimuli(std::fstream& fp, continue; } + /* Pin constraints has the final decision on the default value */ + size_t initial_value = global_ports.global_port_default_value(find_fabric_global_port(global_ports, module_manager, pin_constraints.net_pin(block_name))); + if (pin_constraints.valid_net_default_value(block_name)) { + initial_value = pin_constraints.net_default_value_to_int(block_name); + } + /* Connect stimuli to greset with an optional inversion, depending on the default value */ BasicPort reset_port(block_name, 1); print_verilog_wire_connection(fp, reset_port, BasicPort(TOP_TB_RESET_PORT_NAME, 1), - 1 == global_ports.global_port_default_value(find_fabric_global_port(global_ports, module_manager, pin_constraints.net_pin(block_name)))); + 1 == initial_value); } } From 0851075bc96fe9bd4116bf7e65f89aeeb90ff372 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Jul 2021 23:47:36 -0600 Subject: [PATCH 16/41] [Doc] Update documentation about the new feature in pin constraint file --- docs/source/manual/file_formats/pin_constraints_file.rst | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/docs/source/manual/file_formats/pin_constraints_file.rst b/docs/source/manual/file_formats/pin_constraints_file.rst index c2a71c596..a172396f1 100644 --- a/docs/source/manual/file_formats/pin_constraints_file.rst +++ b/docs/source/manual/file_formats/pin_constraints_file.rst @@ -10,7 +10,7 @@ An example of design constraints is shown as follows. .. code-block:: xml - + @@ -23,3 +23,9 @@ An example of design constraints is shown as follows. .. option:: net="" The net name of the pin to be mapped, which should be consistent with net definition in your ``.blif`` file. The reserved word ``OPEN`` means that no net should be mapped to a given pin. Please ensure that it is not conflicted with any net names in your ``.blif`` file. + +.. option:: default_value="" + + The default value of a net to be constrained. This is mainly used when generating testbenches. Valid value is ``0`` or ``1``. If defined as ``1``, the net is be driven by the inversion of its stimuli. + + .. note:: This feature is mainly used to generate the correct stimuli for some pin whose polarity can be configurable. For example, the ``Reset`` pin of an FPGA fabric may be active-low or active-high depending on its configuration. From 43afaca17c0b406d3b58a347dd37677fd4b90ed0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Jul 2021 23:51:54 -0600 Subject: [PATCH 17/41] [Doc] Add more details about the new syntax --- docs/source/manual/file_formats/pin_constraints_file.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/source/manual/file_formats/pin_constraints_file.rst b/docs/source/manual/file_formats/pin_constraints_file.rst index a172396f1..063b27542 100644 --- a/docs/source/manual/file_formats/pin_constraints_file.rst +++ b/docs/source/manual/file_formats/pin_constraints_file.rst @@ -29,3 +29,5 @@ An example of design constraints is shown as follows. The default value of a net to be constrained. This is mainly used when generating testbenches. Valid value is ``0`` or ``1``. If defined as ``1``, the net is be driven by the inversion of its stimuli. .. note:: This feature is mainly used to generate the correct stimuli for some pin whose polarity can be configurable. For example, the ``Reset`` pin of an FPGA fabric may be active-low or active-high depending on its configuration. + + .. note:: The default value in pin constraint file has a higher priority than the ``default_value`` syntax in the :ref:`circuit_library`. From 0b6a9b06f593b6eb5f29726a23147baad7b0c9ec Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 10:39:07 -0600 Subject: [PATCH 18/41] [Benchmark] Reorganize counter benchmarks. Move them to a directory and give specific naming regarding their functionality --- .../counter_128bit_async_reset/counter.v | 0 .../counter_128bit_async_reset/counter_tb.v | 0 .../counter_128bit_async_resetb/counter.v | 0 .../counter_128bit_async_resetb/counter_tb.v | 0 .../counter4bit_2clock.act | 0 .../counter4bit_2clock.blif | 0 .../counter_4bit_2clock}/counter4bit_2clock.v | 0 .../counter4bit_2clock_post_yosys.v | 0 .../counter4bit_2clock_tb.v | 0 .../counter_8bit_async_reset}/counter.v | 0 .../counter_8bit_async_reset}/counter_tb.v | 0 .../counter_8bit_async_resetb/counter.v | 25 +++++++++++++++++++ .../counter_8bit_async_resetb/counter_tb.v | 25 +++++++++++++++++++ .../counter_8bit_sync_reset}/counter.v | 0 .../counter_8bit_sync_reset}/counter_tb.v | 0 15 files changed, 50 insertions(+) rename openfpga_flow/benchmarks/micro_benchmark/{ => counters}/counter_128bit_async_reset/counter.v (100%) rename openfpga_flow/benchmarks/micro_benchmark/{ => counters}/counter_128bit_async_reset/counter_tb.v (100%) rename openfpga_flow/benchmarks/micro_benchmark/{ => counters}/counter_128bit_async_resetb/counter.v (100%) rename openfpga_flow/benchmarks/micro_benchmark/{ => counters}/counter_128bit_async_resetb/counter_tb.v (100%) rename openfpga_flow/benchmarks/micro_benchmark/{counter4bit_2clock => counters/counter_4bit_2clock}/counter4bit_2clock.act (100%) rename openfpga_flow/benchmarks/micro_benchmark/{counter4bit_2clock => counters/counter_4bit_2clock}/counter4bit_2clock.blif (100%) rename openfpga_flow/benchmarks/micro_benchmark/{counter4bit_2clock => counters/counter_4bit_2clock}/counter4bit_2clock.v (100%) rename openfpga_flow/benchmarks/micro_benchmark/{counter4bit_2clock => counters/counter_4bit_2clock}/counter4bit_2clock_post_yosys.v (100%) rename openfpga_flow/benchmarks/micro_benchmark/{counter4bit_2clock => counters/counter_4bit_2clock}/counter4bit_2clock_tb.v (100%) rename openfpga_flow/benchmarks/micro_benchmark/{counter_async_reset => counters/counter_8bit_async_reset}/counter.v (100%) rename openfpga_flow/benchmarks/micro_benchmark/{counter_async_reset => counters/counter_8bit_async_reset}/counter_tb.v (100%) create mode 100644 openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter_tb.v rename openfpga_flow/benchmarks/micro_benchmark/{counter => counters/counter_8bit_sync_reset}/counter.v (100%) rename openfpga_flow/benchmarks/micro_benchmark/{counter => counters/counter_8bit_sync_reset}/counter_tb.v (100%) diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter_tb.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter_tb.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter_tb.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter_tb.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter_tb.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter_tb.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.act b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.act similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.act rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.act diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.blif b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.blif similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.blif rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.blif diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_post_yosys.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock_post_yosys.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_post_yosys.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock_post_yosys.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock_tb.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_tb.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock_tb.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_async_reset/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter_async_reset/counter.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_async_reset/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter_tb.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter_async_reset/counter_tb.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter_tb.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v new file mode 100644 index 000000000..3d929091d --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v @@ -0,0 +1,25 @@ +/////////////////////////////////////////// +// Functionality: Counter with asynchronous reset +// Author: Xifan Tang +//////////////////////////////////////// + +module counter ( + clk, + resetb, + result +); + + input clk; + input resetb; + output [7:0] result; + + reg [7:0] result; + + always @(posedge clk or negedge resetb) + begin + if (!resetb) + result = 0; + else + result = result + 1; + end +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter_tb.v new file mode 100644 index 000000000..8813aa0c4 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter_tb.v @@ -0,0 +1,25 @@ +module counter_tb; + + reg clk, resetb; + wire [7:0] result; + + counter DUT( + .clk(clk), + .resetb(resetb), + .result(result) + ); + + initial begin + #0 resetb = 1'b0; clk = 1'b0; + #100 resetb = 1'b1; + end + + always begin + #10 clk = ~clk; + end + + initial begin + #5000 $stop; + end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter/counter.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter_tb.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter/counter_tb.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter_tb.v From fd85f956c9d8ea46dd7b5d13c522ff6a4d5806ec Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 11:08:39 -0600 Subject: [PATCH 19/41] [Arch] Update k4n4 arch with true multi-mode flip-flop --- .../k4_frac_N4_fracff_40nm_cc_openfpga.xml | 24 ++- .../k4_frac_N4_tileable_fracff_40nm.xml | 171 +++++++++++++++--- 2 files changed, 167 insertions(+), 28 deletions(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml index 5aca72a87..bc4e0de63 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml @@ -139,15 +139,15 @@ - + - + @@ -220,20 +220,34 @@ - + - + + + + + + + + - + + + + + + + + diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml index af701b3c9..ebd712620 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml @@ -7,11 +7,7 @@ with optionally registered outputs - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1 - Details on Modelling: - - Based on flagship k4_frac_N4_mem32K_40nm.xml architecture. - - Authors: Jason Luu, Jeff Goeders, Vaughn Betz + Authors: Xifan Tang --> + + + + + + + + + + - - + + - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -417,16 +483,75 @@ 261e-12 - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 477e5353447987281dda10144c8fcb5242203e2d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 11:13:03 -0600 Subject: [PATCH 20/41] [HDL] Added a multi-mode FF design with configurable asynchronous reset --- .../openfpga_cell_library/verilog/dff.v | 33 ++++++++++++++++--- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/openfpga_flow/openfpga_cell_library/verilog/dff.v b/openfpga_flow/openfpga_cell_library/verilog/dff.v index c3a5e538e..2eb5765c9 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/dff.v +++ b/openfpga_flow/openfpga_cell_library/verilog/dff.v @@ -246,9 +246,9 @@ endmodule //End Of Module //----------------------------------------------------- // Function : A multi-functional D-type flip-flop with // - asynchronous reset -// which can be switched between active-low and active hight -// - asynchronous set which can be switched -// which can be switched between active-low and active hight +// which can be switched between active-low and active high +// - asynchronous set +// which can be switched between active-low and active high //----------------------------------------------------- module MULTI_MODE_DFFSRQ ( input SET, // Set input @@ -259,8 +259,8 @@ module MULTI_MODE_DFFSRQ ( input [0:1] mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity ); -wire post_set = mode ? ~SET : SET; -wire post_reset = mode ? ~RST : RST; +wire post_set = mode[1] ? ~SET : SET; +wire post_reset = mode[0] ? ~RST : RST; DFFSRQ FF_CORE (.SET(post_set), .RST(post_rst), @@ -271,6 +271,29 @@ DFFSRQ FF_CORE (.SET(post_set), endmodule //End Of Module +//----------------------------------------------------- +// Function : A multi-functional D-type flip-flop with +// - asynchronous reset +// which can be switched between active-low and active high +//----------------------------------------------------- +module MULTI_MODE_DFFRQ ( + input RST, // Reset input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + input mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity +); + +wire post_reset = mode ? ~RST : RST; + +DFFRQ FF_CORE (.RST(post_rst), + .CK(CK), + .D(D), + .Q(Q) + ); + +endmodule //End Of Module + //----------------------------------------------------- // Function : D-type flip-flop with // - asynchronous active high reset From 02fd2a69b313fb7c84a248e4503e4a0b64459b07 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 11:17:43 -0600 Subject: [PATCH 21/41] [Script] Add dff with active-low async reset to default yosys tech lib --- .../openfpga_yosys_techlib/openfpga_dff_map.v | 10 ++++++ .../openfpga_yosys_techlib/openfpga_dff_sim.v | 31 +++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v index 707d9c0e6..8c6c149c4 100644 --- a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +++ b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v @@ -17,6 +17,16 @@ module \$_DFF_PP0_ (D, C, R, Q); dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); endmodule +// Async active-low reset +module \$_DFF_PN0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R)); +endmodule + // Async reset, enable module \$_DFFE_PP0P_ (D, C, E, R, Q); input D; diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v index d4798a906..12b9e8ec3 100644 --- a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +++ b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v @@ -76,6 +76,37 @@ module dffre( endcase endmodule +//----------------------------- +// D-type flip-flop with active-low asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffrn( + output reg Q, + input D, + input RN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + (* abc9_flop, lib_whitebox *) module latchre ( output reg Q, From 5286f9ba255edce8343c4a448b7565fae817b5d7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 11:39:00 -0600 Subject: [PATCH 22/41] [Test] Reworked the test case for k4n4 multi-mode FF architecture by including more counter benchmarking --- .../{pin_constraints.xml => pin_constraints_reset.xml} | 0 .../k4n4_fracff/config/pin_constraints_resetb.xml | 7 +++++++ .../basic_tests/k4_series/k4n4_fracff/config/task.conf | 7 ++++++- 3 files changed, 13 insertions(+), 1 deletion(-) rename openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/{pin_constraints.xml => pin_constraints_reset.xml} (100%) create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_reset.xml similarity index 100% rename from openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints.xml rename to openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_reset.xml diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml new file mode 100644 index 000000000..cdef2ad86 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml @@ -0,0 +1,7 @@ + + + + + diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf index 07e326a1e..364f94ef5 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf @@ -28,13 +28,18 @@ yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_async_reset/counter.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v [SYNTHESIS_PARAM] bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys bench0_top = counter +bench0_pin_conf_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml + +bench1_top = counter +bench1_pin_conf_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= From dcb89cb16b7d85efef01e7420faebfb791ab7bf0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 11:41:29 -0600 Subject: [PATCH 23/41] [Arch] Patch architecture due to missing mode bit definition --- .../k4_frac_N4_fracff_40nm_cc_openfpga.xml | 2 +- .../vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml | 10 ++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml index bc4e0de63..cd12856c5 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml @@ -220,7 +220,7 @@ - + diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml index ebd712620..5351486bc 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml @@ -40,6 +40,16 @@ + + + + + + + + + + From edd5be2cae572f45ff036b644d2ac184adc4bf6b Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 2 Jul 2021 12:51:34 -0600 Subject: [PATCH 24/41] [CI] Added testcase for benchmark variable --- openfpga_flow/scripts/run_fpga_task.py | 10 +++++++--- .../global_tile_4clock/config/task.conf | 3 ++- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 66ac0f838..2fedb5cf6 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -271,9 +271,11 @@ def generate_each_task_actions(taskname): fallback=ys_rewrite_for_task_common) CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width", fallback=chan_width_common) + benchVariable = [] for eachKey, eachValue in SynthSection.items(): - eachKey = eachKey.replace(bech_name+"_","").upper() - CurrBenchPara[eachKey] = eachValue + if bech_name in eachKey: + eachKey = eachKey.replace(bech_name+"_", "").upper() + benchVariable = benchVariable+[f"--{eachKey}"] + [eachValue] if GeneralSection.get("fpga_flow") == "vpr_blif": # Check if activity file exist @@ -335,7 +337,7 @@ def generate_each_task_actions(taskname): "bench": bench, "name": "%02d_%s_%s" % (indx, bench["top_module"], lbl), "run_dir": flow_run_dir, - "commands": command, + "commands": command + benchVariable, "finished": False, "status": False}) @@ -346,6 +348,8 @@ def generate_each_task_actions(taskname): # Make the directory name unique by including the benchmark index in the list. # This is because benchmarks may share the same top module names + + def get_flow_rundir(arch, top_module, flow_params=None): path = [ os.path.basename(arch).replace(".xml", ""), diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf index e7cbcb5ab..679b8e6ac 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf @@ -20,7 +20,6 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTile4Clk_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_4clock_sim_openfpga.xml openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml -openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml @@ -31,7 +30,9 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch [SYNTHESIS_PARAM] bench0_top = counter4bit_2clock +bench0_openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml bench1_top = and2_latch_2clock +bench1_openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= From 6e6c3e9fa4269f023ff8e8571e50207ccd651b31 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 15:26:21 -0600 Subject: [PATCH 25/41] [Tool] Patch the critical bug in the use of signal polarity in pin constraints --- .../verilog_formal_random_top_testbench.cpp | 7 +++---- openfpga/src/fpga_verilog/verilog_testbench_utils.cpp | 10 ++++++++++ openfpga/src/fpga_verilog/verilog_testbench_utils.h | 1 + openfpga/src/fpga_verilog/verilog_top_testbench.cpp | 7 +++---- 4 files changed, 17 insertions(+), 8 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp index 6be38f425..d27baccbd 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp @@ -105,6 +105,7 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp, const std::string& reference_verilog_top_name, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const PinConstraints& pin_constraints, const bool& explicit_port_mapping) { /* Validate the file stream */ valid_file_stream(fp); @@ -125,6 +126,7 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp, prefix_to_remove, std::string(BENCHMARK_PORT_POSTFIX), atom_ctx, netlist_annotation, + pin_constraints, explicit_port_mapping); print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------")); @@ -213,10 +215,6 @@ void print_verilog_random_testbench_reset_stimuli(std::fstream& fp, if (1 == global_ports.global_port_default_value(find_fabric_global_port(global_ports, module_manager, pin_constraints.net_pin(block_name)))) { initial_value = 0; } - /* Pin constraints has the final decision on the default value */ - if (pin_constraints.valid_net_default_value(block_name)) { - initial_value = pin_constraints.net_default_value_to_int(block_name); - } fp << "initial" << std::endl; fp << "\tbegin" << std::endl; @@ -308,6 +306,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name, if (!options.no_self_checking()) { print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name, atom_ctx, netlist_annotation, + pin_constraints, options.explicit_port_mapping()); } diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp index bd530cc3e..01cdb0a22 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp @@ -69,6 +69,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp, const std::string& output_port_postfix, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const PinConstraints& pin_constraints, const bool& use_explicit_port_map) { /* Validate the file stream */ valid_file_stream(fp); @@ -99,6 +100,15 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp, if (true == use_explicit_port_map) { fp << "." << block_name << module_input_port_postfix << "("; } + + /* Polarity of some input may have to be inverted, as defined in pin constraints + * For example, the reset signal of the benchmark is active low + * while the reset signal of the FPGA fabric is active high (inside FPGA, the reset signal will be inverted) + * However, to ensure correct stimuli to the benchmark, we have to invert the signal + */ + if (LOGIC_HIGH == pin_constraints.net_default_value(block_name)) { + fp << "~"; + } fp << block_name; if (true == use_explicit_port_map) { fp << ")"; diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.h b/openfpga/src/fpga_verilog/verilog_testbench_utils.h index f45452c6d..d06f267c9 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.h +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.h @@ -38,6 +38,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp, const std::string& output_port_postfix, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const PinConstraints& pin_constraints, const bool& use_explicit_port_map); void print_verilog_testbench_connect_fpga_ios(std::fstream& fp, diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 1e82b7e81..e4778c292 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -912,6 +912,7 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp, const std::string& reference_verilog_top_name, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const PinConstraints& pin_constraints, const bool& explicit_port_mapping) { /* Validate the file stream */ valid_file_stream(fp); @@ -932,6 +933,7 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp, prefix_to_remove, std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX), atom_ctx, netlist_annotation, + pin_constraints, explicit_port_mapping); print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------")); @@ -1789,11 +1791,7 @@ void print_verilog_top_testbench_reset_stimuli(std::fstream& fp, continue; } - /* Pin constraints has the final decision on the default value */ size_t initial_value = global_ports.global_port_default_value(find_fabric_global_port(global_ports, module_manager, pin_constraints.net_pin(block_name))); - if (pin_constraints.valid_net_default_value(block_name)) { - initial_value = pin_constraints.net_default_value_to_int(block_name); - } /* Connect stimuli to greset with an optional inversion, depending on the default value */ BasicPort reset_port(block_name, 1); @@ -2004,6 +2002,7 @@ int print_verilog_full_testbench(const ModuleManager& module_manager, circuit_name, atom_ctx, netlist_annotation, + pin_constraints, explicit_port_mapping); } From c67807868c76b988c876b0733c6d492f52472390 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 2 Jul 2021 15:26:39 -0600 Subject: [PATCH 26/41] [bugFix] Benchamrk variable declaration --- openfpga_flow/scripts/run_fpga_task.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 2fedb5cf6..9ae4d87c7 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -271,11 +271,11 @@ def generate_each_task_actions(taskname): fallback=ys_rewrite_for_task_common) CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width", fallback=chan_width_common) - benchVariable = [] + CurrBenchPara["benchVariable"] = [] for eachKey, eachValue in SynthSection.items(): if bech_name in eachKey: eachKey = eachKey.replace(bech_name+"_", "").upper() - benchVariable = benchVariable+[f"--{eachKey}"] + [eachValue] + CurrBenchPara["benchVariable"] += [eachKey,eachValue] if GeneralSection.get("fpga_flow") == "vpr_blif": # Check if activity file exist @@ -337,7 +337,7 @@ def generate_each_task_actions(taskname): "bench": bench, "name": "%02d_%s_%s" % (indx, bench["top_module"], lbl), "run_dir": flow_run_dir, - "commands": command + benchVariable, + "commands": command + bench["benchVariable"], "finished": False, "status": False}) From 3cbe266c4412b319a08b309befbf8b065d3b09e3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 15:27:27 -0600 Subject: [PATCH 27/41] [Test] Bug fix on the test case for multi-mode FF and pin constraints --- .../tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf index 364f94ef5..2408323ed 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf @@ -19,7 +19,6 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml -openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints.xml # Yosys script parameters yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v @@ -36,10 +35,10 @@ bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_df bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys bench0_top = counter -bench0_pin_conf_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml +bench0_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_reset.xml bench1_top = counter -bench1_pin_conf_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml +bench1_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= From e9d29e27e50d49269f515c2298312093d987092c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 15:32:30 -0600 Subject: [PATCH 28/41] [Tool] Bug fix --- .../src/fpga_verilog/verilog_formal_random_top_testbench.cpp | 1 + openfpga/src/fpga_verilog/verilog_testbench_utils.cpp | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp index d27baccbd..47fc6a13d 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp @@ -157,6 +157,7 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp, std::vector(), std::string(FPGA_PORT_POSTFIX), atom_ctx, netlist_annotation, + PinConstraints(), explicit_port_mapping); print_verilog_comment(fp, std::string("----- End FPGA Fabric Instanication -------")); diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp index 01cdb0a22..3542cdcfc 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp @@ -106,7 +106,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp, * while the reset signal of the FPGA fabric is active high (inside FPGA, the reset signal will be inverted) * However, to ensure correct stimuli to the benchmark, we have to invert the signal */ - if (LOGIC_HIGH == pin_constraints.net_default_value(block_name)) { + if (PinConstraints::LOGIC_HIGH == pin_constraints.net_default_value(block_name)) { fp << "~"; } fp << block_name; From 8baf60603a5aeeffe638b1de48b67653d703e3d8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 15:59:29 -0600 Subject: [PATCH 29/41] [Script] Patching the run_fpga_task.py on pin constraint files --- openfpga_flow/scripts/run_fpga_task.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 9ae4d87c7..7665cfb1b 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -275,7 +275,7 @@ def generate_each_task_actions(taskname): for eachKey, eachValue in SynthSection.items(): if bech_name in eachKey: eachKey = eachKey.replace(bech_name+"_", "").upper() - CurrBenchPara["benchVariable"] += [eachKey,eachValue] + CurrBenchPara["benchVariable"] += [f"--{eachKey}", eachValue] if GeneralSection.get("fpga_flow") == "vpr_blif": # Check if activity file exist From 5a6874e9f173f613c237d525f63e0eebf8025e70 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 17:28:17 -0600 Subject: [PATCH 30/41] [Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks --- .../counter4bit_2clock.act | 22 ------- .../counter4bit_2clock.blif | 48 --------------- .../counter4bit_2clock_post_yosys.v | 60 ------------------- ...ter4bit_2clock.v => counter_4bit_2clock.v} | 2 +- ...t_2clock_tb.v => counter_4bit_2clock_tb.v} | 6 +- 5 files changed, 4 insertions(+), 134 deletions(-) delete mode 100644 openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.act delete mode 100644 openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.blif delete mode 100644 openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock_post_yosys.v rename openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/{counter4bit_2clock.v => counter_4bit_2clock.v} (85%) rename openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/{counter4bit_2clock_tb.v => counter_4bit_2clock_tb.v} (75%) diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.act b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.act deleted file mode 100644 index e0e56d449..000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.act +++ /dev/null @@ -1,22 +0,0 @@ -clk0 0.505000 0.204400 -rst0 0.491000 0.206000 -clk1 0.472000 0.204400 -rst1 0.501400 0.204600 -q1[0] 0.278800 0.557400 -q1[1] 0.240600 0.268800 -q1[2] 0.178200 0.120000 -q1[3] 0.098400 0.041600 -q0[0] 0.283400 0.566600 -q0[1] 0.246800 0.272000 -q0[2] 0.181000 0.122200 -q0[3] 0.093200 0.048800 -n34 0.178200 0.068356 -n38 0.098400 0.002698 -$abc$226$new_n22_ 0.880800 0.004943 -n42 0.283400 0.129291 -n46 0.246800 0.084119 -n50 0.181000 0.067113 -n54 0.093200 0.002644 -$abc$226$new_n27_ 0.883200 0.005398 -n26 0.278800 0.038636 -n30 0.240600 0.082416 diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.blif b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.blif deleted file mode 100644 index 0ae3c95a7..000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.blif +++ /dev/null @@ -1,48 +0,0 @@ -# Benchmark "counter4bit_2clock" written by ABC on Wed Jan 13 13:27:00 2021 -.model counter4bit_2clock -.inputs clk0 rst0 clk1 rst1 -.outputs q0[0] q0[1] q0[2] q0[3] q1[0] q1[1] \ -q1[2] q1[3] - -.latch n26 q1[0] re clk1 2 -.latch n30 q1[1] re clk1 2 -.latch n34 q1[2] re clk1 2 -.latch n38 q1[3] re clk1 2 -.latch n42 q0[0] re clk0 2 -.latch n46 q0[1] re clk0 2 -.latch n50 q0[2] re clk0 2 -.latch n54 q0[3] re clk0 2 - -.names q1[0] q1[1] rst1 q1[2] n34 --001 1 -0-01 1 -1100 1 -.names rst1 $abc$226$new_n22_ n38 -00 1 -.names q1[2] q1[0] q1[1] q1[3] $abc$226$new_n22_ ---00 1 --0-0 1 -0--0 1 -1111 1 -.names rst0 q0[0] n42 -00 1 -.names rst0 q0[1] q0[0] n46 -001 1 -010 1 -.names q0[1] q0[0] rst0 q0[2] n50 --001 1 -0-01 1 -1100 1 -.names rst0 $abc$226$new_n27_ n54 -00 1 -.names q0[2] q0[1] q0[0] q0[3] $abc$226$new_n27_ ---00 1 --0-0 1 -0--0 1 -1111 1 -.names q1[0] rst1 n26 -00 1 -.names rst1 q1[0] q1[1] n30 -001 1 -010 1 -.end diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock_post_yosys.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock_post_yosys.v deleted file mode 100644 index 2b14fc540..000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock_post_yosys.v +++ /dev/null @@ -1,60 +0,0 @@ -/* Generated by Yosys 0.9+2406 (git sha1 a0606e09, gcc 8.4.0 -fPIC -Os) */ - -module counter4bit_2clock(clk0, rst0, clk1, rst1, \q0[0] , \q0[1] , \q0[2] , \q0[3] , \q1[0] , \q1[1] , \q1[2] , \q1[3] ); - wire _00_; - wire _01_; - input clk0; - input clk1; - wire n26; - wire n30; - wire n34; - wire n38; - wire n42; - wire n46; - wire n50; - wire n54; - output \q0[0] ; - reg \q0[0] ; - output \q0[1] ; - reg \q0[1] ; - output \q0[2] ; - reg \q0[2] ; - output \q0[3] ; - reg \q0[3] ; - output \q1[0] ; - reg \q1[0] ; - output \q1[1] ; - reg \q1[1] ; - output \q1[2] ; - reg \q1[2] ; - output \q1[3] ; - reg \q1[3] ; - input rst0; - input rst1; - always @(posedge clk1) - \q1[0] <= n26; - always @(posedge clk1) - \q1[1] <= n30; - always @(posedge clk1) - \q1[2] <= n34; - always @(posedge clk1) - \q1[3] <= n38; - always @(posedge clk1) - \q0[0] <= n42; - always @(posedge clk1) - \q0[1] <= n46; - always @(posedge clk1) - \q0[2] <= n50; - always @(posedge clk1) - \q0[3] <= n54; - assign n38 = 4'h1 >> { _00_, rst1 }; - assign _00_ = 16'h807f >> { \q1[3] , \q1[1] , \q1[0] , \q1[2] }; - assign n42 = 4'h1 >> { \q0[0] , rst0 }; - assign n46 = 8'h14 >> { \q0[0] , \q0[1] , rst0 }; - assign n50 = 16'h0708 >> { \q0[2] , rst0, \q0[0] , \q0[1] }; - assign n54 = 4'h1 >> { _01_, rst0 }; - assign _01_ = 16'h807f >> { \q0[3] , \q0[0] , \q0[1] , \q0[2] }; - assign n26 = 4'h1 >> { rst1, \q1[0] }; - assign n30 = 8'h14 >> { \q1[1] , \q1[0] , rst1 }; - assign n34 = 16'h0708 >> { \q1[2] , rst1, \q1[1] , \q1[0] }; -endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v similarity index 85% rename from openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v index 93f7dc07b..c1b5f2ee6 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock.v +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v @@ -1,4 +1,4 @@ -module counter4bit_2clock(clk0, rst0, clk1, rst1, q0, q1); +module counter_4bit_2clock(clk0, rst0, clk1, rst1, q0, q1); input clk0; input rst0; diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock_tb.v similarity index 75% rename from openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock_tb.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock_tb.v index 880b99088..9150f55b9 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter4bit_2clock_tb.v +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock_tb.v @@ -1,4 +1,4 @@ -module counter4bit_2clock_tb; +module counter_4bit_2clock_tb; reg clk0, rst0; wire [3:0] q0; @@ -6,12 +6,12 @@ module counter4bit_2clock_tb; reg clk1, rst1; wire [3:0] q1; - counter_2clock C_1( + counter_4bit_2clock C_1( clk0, q0, rst0); - counter_2clock C_1( + counter_4bit_2clock C_1( clk1, q1, rst1); From 64dcdaec6111fe5c68007e234ac16eeccaf0e5f5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 17:29:13 -0600 Subject: [PATCH 31/41] [Test] Update all the tasks that use counter benchmark --- .../global_tile_ports/global_tile_4clock/config/task.conf | 4 ++-- .../tasks/benchmark_sweep/counter/config/task.conf | 8 ++++---- .../implicit_verilog/config/task.conf | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf index 679b8e6ac..feb6dfbaa 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf @@ -25,11 +25,11 @@ openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/task arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch_2clock/and2_latch_2clock.v [SYNTHESIS_PARAM] -bench0_top = counter4bit_2clock +bench0_top = counter_4bit_2clock bench0_openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml bench1_top = and2_latch_2clock bench1_openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml diff --git a/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf index eb0079516..6fefdb16d 100644 --- a/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf @@ -34,10 +34,10 @@ vpr_route_chan_width=50 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v -bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_async_reset/counter.v -bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter.v -bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter.v +bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v [SYNTHESIS_PARAM] bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf index f7f2a8b06..df4d8b854 100644 --- a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf @@ -25,7 +25,7 @@ openfpga_verilog_default_net_type=none arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v [SYNTHESIS_PARAM] bench0_top = counter From 9f03ecb160354fa8251e8502ea6041653570e556 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Jul 2021 17:57:39 -0600 Subject: [PATCH 32/41] [Test] Patch test case due to the changes in counter benchmarks --- .../implicit_verilog_default_nettype_wire/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf index 898412cd2..568ded5e4 100644 --- a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf @@ -25,7 +25,7 @@ openfpga_verilog_default_net_type=wire arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v [SYNTHESIS_PARAM] bench0_top = counter From 3ce866f2eb273cf75e3fa7d53d78612b338ef7c0 Mon Sep 17 00:00:00 2001 From: Andrew Pond <32227768+apond308@users.noreply.github.com> Date: Mon, 26 Jul 2021 15:12:59 -0600 Subject: [PATCH 33/41] Update compile.rst --- docs/source/tutorials/getting_started/compile.rst | 3 +++ 1 file changed, 3 insertions(+) diff --git a/docs/source/tutorials/getting_started/compile.rst b/docs/source/tutorials/getting_started/compile.rst index 85c9702db..5c5b7e55d 100644 --- a/docs/source/tutorials/getting_started/compile.rst +++ b/docs/source/tutorials/getting_started/compile.rst @@ -46,6 +46,9 @@ In particular, OpenFPGA requires specific versions for the following dependencie :iverilog: version 10.1+ is required to run Verilog-to-Verification flow + +:envyaml: + python package envyaml is required: 'python3 -m pip install envyaml' .. _install_dependencies_build: https://github.com/lnis-uofu/OpenFPGA/blob/master/.github/workflows/install_dependencies_build.sh From 1c0bec1c5a256e55e14513aa37367361f8d01e11 Mon Sep 17 00:00:00 2001 From: Andrew Pond <32227768+apond308@users.noreply.github.com> Date: Mon, 26 Jul 2021 15:17:25 -0600 Subject: [PATCH 34/41] Update compile.rst --- docs/source/tutorials/getting_started/compile.rst | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/docs/source/tutorials/getting_started/compile.rst b/docs/source/tutorials/getting_started/compile.rst index 5c5b7e55d..caeeb50cc 100644 --- a/docs/source/tutorials/getting_started/compile.rst +++ b/docs/source/tutorials/getting_started/compile.rst @@ -48,7 +48,10 @@ In particular, OpenFPGA requires specific versions for the following dependencie version 10.1+ is required to run Verilog-to-Verification flow :envyaml: - python package envyaml is required: 'python3 -m pip install envyaml' + python package envyaml is required. + .. code-block:: shell + + python3 -m pip install envyaml .. _install_dependencies_build: https://github.com/lnis-uofu/OpenFPGA/blob/master/.github/workflows/install_dependencies_build.sh From a8a8c25a216f1e94c1d2a9bfe575c67fc8d9b2a0 Mon Sep 17 00:00:00 2001 From: Andrew Pond <32227768+apond308@users.noreply.github.com> Date: Mon, 26 Jul 2021 15:18:23 -0600 Subject: [PATCH 35/41] Update compile.rst --- docs/source/tutorials/getting_started/compile.rst | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/docs/source/tutorials/getting_started/compile.rst b/docs/source/tutorials/getting_started/compile.rst index caeeb50cc..0e8cb8563 100644 --- a/docs/source/tutorials/getting_started/compile.rst +++ b/docs/source/tutorials/getting_started/compile.rst @@ -48,9 +48,8 @@ In particular, OpenFPGA requires specific versions for the following dependencie version 10.1+ is required to run Verilog-to-Verification flow :envyaml: - python package envyaml is required. - .. code-block:: shell - + python package envyaml is required: + python3 -m pip install envyaml .. _install_dependencies_build: https://github.com/lnis-uofu/OpenFPGA/blob/master/.github/workflows/install_dependencies_build.sh From c31c1d8b049e1cc09fdcb2850d564971c51b0a44 Mon Sep 17 00:00:00 2001 From: Will <5217539+WRansohoff@users.noreply.github.com> Date: Fri, 13 Aug 2021 11:08:09 -0400 Subject: [PATCH 36/41] Accept absolute project paths as inputs to the 'run_fpga_task.py' script. --- openfpga_flow/scripts/run_fpga_task.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 7665cfb1b..c1ced3ccb 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -168,13 +168,19 @@ def generate_each_task_actions(taskname): # Check if task directory exists and consistent local_tasks = os.path.join(*(taskname)) repo_tasks = os.path.join(gc["task_dir"], *(taskname)) + abs_tasks = os.path.abspath('/' + local_tasks) if os.path.isdir(local_tasks): os.chdir(local_tasks) curr_task_dir = os.path.abspath(os.getcwd()) + elif os.path.isdir(abs_tasks): + curr_task_dir = abs_tasks elif os.path.isdir(repo_tasks): curr_task_dir = repo_tasks else: - clean_up_and_exit("Task directory [%s] not found" % taskname + " locally at [%s]" % local_tasks + " or in OpenFPGA task directory [%s]" % repo_tasks) + clean_up_and_exit("Task directory [%s] not found" % taskname + + " locally at [%s]" % local_tasks + + ", absolutely at [%s]" % abs_tasks + + ", or in OpenFPGA task directory [%s]" % repo_tasks) os.chdir(curr_task_dir) From 1c09b8c3e0dc773a4bf774cac2f0e6473b7b9bc2 Mon Sep 17 00:00:00 2001 From: ANDREW HARRIS POND Date: Tue, 17 Aug 2021 10:18:51 -0600 Subject: [PATCH 37/41] fixed python instruction --- docs/source/tutorials/getting_started/compile.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/source/tutorials/getting_started/compile.rst b/docs/source/tutorials/getting_started/compile.rst index 0e8cb8563..17d333be0 100644 --- a/docs/source/tutorials/getting_started/compile.rst +++ b/docs/source/tutorials/getting_started/compile.rst @@ -47,10 +47,10 @@ In particular, OpenFPGA requires specific versions for the following dependencie :iverilog: version 10.1+ is required to run Verilog-to-Verification flow -:envyaml: - python package envyaml is required: +:python dependencies: + python packages are also required: - python3 -m pip install envyaml + python3 -m pip install -r requirements.txt .. _install_dependencies_build: https://github.com/lnis-uofu/OpenFPGA/blob/master/.github/workflows/install_dependencies_build.sh From cc546cdedc62c07e27b91c8742eef4dc7ad83b0a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 2 Sep 2021 16:42:24 -0700 Subject: [PATCH 38/41] [CI] Enable github actions --- .github/workflows/build.yml | 9 ++++----- yosys | 2 +- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 6b88712f1..77ccb1527 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -3,11 +3,10 @@ name: linux_build # Run CI on push, PR, and weekly. on: - workflow_dispatch: -# push: -# pull_request: -# schedule: -# - cron: "0 0 * * 0 " # weekly + push: + pull_request: + schedule: + - cron: "0 0 * * 0 " # weekly # Environment variables env: diff --git a/yosys b/yosys index f44a4f908..c9555c9ad 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit f44a4f90867b49837da048f9055fdcd8a13c335b +Subproject commit c9555c9adeba886a308c60615ac794ec20d9276e From a2a5d6b97bde22166d45f0b095a573d356f41b1b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 2 Sep 2021 16:46:35 -0700 Subject: [PATCH 39/41] [Git] Removed RTL benchmarks now as it is failing CI; Should consider bring it back sometime --- .gitmodules | 3 --- 1 file changed, 3 deletions(-) diff --git a/.gitmodules b/.gitmodules index e99222f81..1fb1d4212 100644 --- a/.gitmodules +++ b/.gitmodules @@ -2,6 +2,3 @@ path = yosys url = https://github.com/QuickLogic-Corp/yosys.git branch = quicklogic-rebased -[submodule "RTL_Benchmark"] - path = RTL_Benchmark - url = git@github.com:RapidSilicon/RTL_Benchmark.git From d37cfe96bdfa88bf15200d40d890f4628ffe2ecb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 2 Sep 2021 16:51:07 -0700 Subject: [PATCH 40/41] [Git] Remove RTL benchmarks submodule --- RTL_Benchmark | 1 - 1 file changed, 1 deletion(-) delete mode 160000 RTL_Benchmark diff --git a/RTL_Benchmark b/RTL_Benchmark deleted file mode 160000 index 16bc04733..000000000 --- a/RTL_Benchmark +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 16bc04733bc63c1f3b137ebe52628a3ffe127c13 From 5d22de7ac9fca30bc98b8c75bea8dd6922e343f7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 2 Sep 2021 20:00:47 -0700 Subject: [PATCH 41/41] [Yosys] Revert to an older version of yosys that works in regresstion tests --- yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys b/yosys index c9555c9ad..f44a4f908 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit c9555c9adeba886a308c60615ac794ec20d9276e +Subproject commit f44a4f90867b49837da048f9055fdcd8a13c335b