riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[core] fixed a bug where pb/cb/sb instance name is not assigned correctly in bitstream manager under tile modules

This commit is contained in:
tangxifan 2023-07-27 13:33:23 -07:00
parent 156cb800aa
commit c2066cc63c
4 changed files with 110 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
openfpga/src/annotation/fabric_tile.cpp
View File

@ -23,6 +23,11 @@ vtr::Point<size_t> FabricTile::unique_tile_coordinate(
return tile_coordinate(unique_fabric_tile_id);
}
FabricTileId FabricTile::find_unique_tile(const FabricTileId& tile_id) const {
vtr::Point<size_t> tile_coord = tile_coordinate(tile_id);
return unique_tile(tile_coord);
}
std::vector<vtr::Point<size_t>> FabricTile::pb_coordinates(
const FabricTileId& tile_id) const {
VTR_ASSERT(valid_tile_id(tile_id));
@ -280,6 +285,29 @@ size_t FabricTile::find_cb_index_in_tile(
}
}
vtr::Point<size_t> FabricTile::find_cb_coordinate_in_unique_tile(
const FabricTileId& tile_id, const t_rr_type& cb_type,
const vtr::Point<size_t>& cb_coord) const {
size_t cb_idx_in_curr_tile =
find_cb_index_in_tile(tile_id, cb_type, cb_coord);
FabricTileId unique_tile = find_unique_tile(tile_id);
return cb_coordinates(unique_tile, cb_type)[cb_idx_in_curr_tile];
}
vtr::Point<size_t> FabricTile::find_pb_coordinate_in_unique_tile(
const FabricTileId& tile_id, const vtr::Point<size_t>& pb_coord) const {
size_t pb_idx_in_curr_tile = find_pb_index_in_tile(tile_id, pb_coord);
FabricTileId unique_tile = find_unique_tile(tile_id);
return pb_coordinates(unique_tile)[pb_idx_in_curr_tile];
}
vtr::Point<size_t> FabricTile::find_sb_coordinate_in_unique_tile(
const FabricTileId& tile_id, const vtr::Point<size_t>& sb_coord) const {
size_t sb_idx_in_curr_tile = find_sb_index_in_tile(tile_id, sb_coord);
FabricTileId unique_tile = find_unique_tile(tile_id);
return sb_coordinates(unique_tile)[sb_idx_in_curr_tile];
}
std::vector<FabricTileId> FabricTile::unique_tiles() const {
return unique_tile_ids_;
}

25
openfpga/src/annotation/fabric_tile.h
View File

@ -34,6 +34,9 @@ class FabricTile {
/** @brief With a given coordinate, find the id of the unique tile (which is
* the same as the tile in structure) */
FabricTileId unique_tile(const vtr::Point<size_t>& coord) const;
/** @brief With a given tile id, find the id of its unique tile (which is
* the same as the tile in structure) */
FabricTileId find_unique_tile(const FabricTileId& tile_id) const;
/** @brief Find the tile info with a given coordinate */
FabricTileId find_tile(const vtr::Point<size_t>& coord) const;
/** @brief Find the id of a tile, with a given coordinate of the programmable
@ -68,6 +71,28 @@ class FabricTile {
size_t find_cb_index_in_tile(const FabricTileId& tile_id,
const t_rr_type& cb_type,
const vtr::Point<size_t>& coord) const;
/** @brief Find the coodinate of a connection block in its unique tile. For
* example, a cbx[1][0] is the 2nd element of the connection block list in
* tile[1][1], while the unique tile of tile[1][1] is tile[2][2]. We will find
* the 2nd element of the connection block list in tile[2][2] and return its
* coordinate. Error out on any exception. */
vtr::Point<size_t> find_cb_coordinate_in_unique_tile(
const FabricTileId& tile_id, const t_rr_type& cb_type,
const vtr::Point<size_t>& cb_coord) const;
/** @brief Find the coodinate of a programmable block in its unique tile. For
* example, a pb[1][0] is the 2nd element of the programmable block list in
* tile[1][1], while the unique tile of tile[1][1] is tile[2][2]. We will find
* the 2nd element of the programmable block list in tile[2][2] and return its
* coordinate. Error out on any exception. */
vtr::Point<size_t> find_pb_coordinate_in_unique_tile(
const FabricTileId& tile_id, const vtr::Point<size_t>& pb_coord) const;
/** @brief Find the coodinate of a switch block in its unique tile. For
* example, a pb[1][0] is the 2nd element of the switch block list in
* tile[1][1], while the unique tile of tile[1][1] is tile[2][2]. We will find
* the 2nd element of the switch block list in tile[2][2] and return its
* coordinate. Error out on any exception. */
vtr::Point<size_t> find_sb_coordinate_in_unique_tile(
const FabricTileId& tile_id, const vtr::Point<size_t>& sb_coord) const;
/** @brief Check if a programmable block (with a coordinate) exists in a tile.
* Note that the coord can be either the one in device grid or the one of gsb
* which the programmable block belongs to

35
openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
View File

@ -727,7 +727,8 @@ static void rec_build_physical_block_bitstream(
*******************************************************************/
static void build_physical_block_bitstream(
BitstreamManager& bitstream_manager, const ConfigBlockId& top_block,
const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
const ModuleManager& module_manager, const FabricTile& fabric_tile,
const FabricTileId& curr_tile, const CircuitLibrary& circuit_lib,
const MuxLibrary& mux_lib, const AtomContext& atom_ctx,
const VprDeviceAnnotation& device_annotation,
const VprClusteringAnnotation& cluster_annotation,
@ -751,9 +752,17 @@ static void build_physical_block_bitstream(
return;
}
vtr::Point<size_t> grid_coord_in_unique_tile = grid_coord;
if (fabric_tile.valid_tile_id(curr_tile)) {
/* For tile modules, need to find the specific instance name under its
* unique tile */
grid_coord_in_unique_tile =
fabric_tile.find_pb_coordinate_in_unique_tile(curr_tile, grid_coord);
}
std::string grid_block_name = generate_grid_block_instance_name(
grid_module_name_prefix, std::string(grid_type->name),
is_io_type(grid_type), border_side, grid_coord);
is_io_type(grid_type), border_side, grid_coord_in_unique_tile);
ConfigBlockId grid_configurable_block =
bitstream_manager.add_block(grid_block_name);
bitstream_manager.add_child_block(top_block, grid_configurable_block);
@ -854,12 +863,17 @@ void build_grid_bitstream(
std::string tile_inst_name = generate_tile_module_name(tile_coord);
parent_block = bitstream_manager.find_or_create_child_block(
top_block, tile_inst_name);
VTR_LOGV(verbose,
"Add configurable block '%s' as a child under configurable "
"block '%s'\n",
tile_inst_name.c_str(),
bitstream_manager.block_name(top_block).c_str());
}
build_physical_block_bitstream(
bitstream_manager, parent_block, module_manager, circuit_lib, mux_lib,
atom_ctx, device_annotation, cluster_annotation, place_annotation,
bitstream_annotation, grids, grid_coord, NUM_SIDES);
bitstream_manager, parent_block, module_manager, fabric_tile, curr_tile,
circuit_lib, mux_lib, atom_ctx, device_annotation, cluster_annotation,
place_annotation, bitstream_annotation, grids, grid_coord, NUM_SIDES);
}
}
VTR_LOGV(verbose, "Done\n");
@ -895,12 +909,17 @@ void build_grid_bitstream(
std::string tile_inst_name = generate_tile_module_name(tile_coord);
parent_block = bitstream_manager.find_or_create_child_block(
top_block, tile_inst_name);
VTR_LOGV(verbose,
"Add configurable block '%s' as a child under configurable "
"block '%s'\n",
tile_inst_name.c_str(),
bitstream_manager.block_name(parent_block).c_str());
}
build_physical_block_bitstream(
bitstream_manager, parent_block, module_manager, circuit_lib, mux_lib,
atom_ctx, device_annotation, cluster_annotation, place_annotation,
bitstream_annotation, grids, io_coordinate, io_side);
bitstream_manager, parent_block, module_manager, fabric_tile, curr_tile,
circuit_lib, mux_lib, atom_ctx, device_annotation, cluster_annotation,
place_annotation, bitstream_annotation, grids, io_coordinate, io_side);
}
}
VTR_LOGV(verbose, "Done\n");

40
openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
View File

@ -498,17 +498,29 @@ static void build_connection_block_bitstreams(
ConfigBlockId parent_block = top_configurable_block;
FabricTileId curr_tile = fabric_tile.find_tile_by_cb_coordinate(
cb_type, vtr::Point<size_t>(ix, iy));
ConfigBlockId cb_configurable_block;
if (fabric_tile.valid_tile_id(curr_tile)) {
vtr::Point<size_t> tile_coord = fabric_tile.tile_coordinate(curr_tile);
std::string tile_inst_name = generate_tile_module_name(tile_coord);
parent_block = bitstream_manager.find_or_create_child_block(
top_configurable_block, tile_inst_name);
/* For tile modules, need to find the specific instance name under its
* unique tile */
vtr::Point<size_t> cb_coord_in_unique_tile =
fabric_tile.find_cb_coordinate_in_unique_tile(
curr_tile, cb_type, vtr::Point<size_t>(ix, iy));
const RRGSB& unique_tile_cb_rr_gsb =
device_rr_gsb.get_gsb(cb_coord_in_unique_tile);
cb_configurable_block =
bitstream_manager.add_block(generate_connection_block_module_name(
cb_type, unique_tile_cb_rr_gsb.get_cb_coordinate(cb_type)));
} else {
/* Create a block for the bitstream which corresponds to the Switch
* block
*/
cb_configurable_block = bitstream_manager.add_block(
generate_connection_block_module_name(cb_type, cb_coord));
}
/* Create a block for the bitstream which corresponds to the Switch block
*/
ConfigBlockId cb_configurable_block = bitstream_manager.add_block(
generate_connection_block_module_name(cb_type, cb_coord));
/* Set switch block as a child of top block */
bitstream_manager.add_child_block(parent_block, cb_configurable_block);
@ -592,17 +604,25 @@ void build_routing_bitstream(
* If any block is missing during the back tracing, create it. */
ConfigBlockId parent_block = top_configurable_block;
FabricTileId curr_tile = fabric_tile.find_tile_by_sb_coordinate(sb_coord);
ConfigBlockId sb_configurable_block;
if (fabric_tile.valid_tile_id(curr_tile)) {
vtr::Point<size_t> tile_coord = fabric_tile.tile_coordinate(curr_tile);
std::string tile_inst_name = generate_tile_module_name(tile_coord);
parent_block = bitstream_manager.find_or_create_child_block(
top_configurable_block, tile_inst_name);
/* For tile modules, need to find the specific instance name under its
* unique tile */
vtr::Point<size_t> sb_coord_in_unique_tile =
fabric_tile.find_sb_coordinate_in_unique_tile(curr_tile, sb_coord);
sb_configurable_block = bitstream_manager.add_block(
generate_switch_block_module_name(sb_coord_in_unique_tile));
} else {
/* Create a block for the bitstream which corresponds to the Switch
* block
*/
sb_configurable_block = bitstream_manager.add_block(
generate_switch_block_module_name(sb_coord));
}
/* Create a block for the bitstream which corresponds to the Switch block
*/
ConfigBlockId sb_configurable_block = bitstream_manager.add_block(
generate_switch_block_module_name(sb_coord));
/* Set switch block as a child of top block */
bitstream_manager.add_child_block(parent_block, sb_configurable_block);