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[core] fixed a critical bug where clock network entry is on a CHANY

This commit is contained in:
tangxifan 2024-07-16 17:04:44 -07:00
parent cbd10e1222
commit c1f46c448a
1 changed files with 0 additions and 11 deletions
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11
openfpga/src/annotation/device_rr_gsb.cpp
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@ -47,17 +47,6 @@ const RRGSB& DeviceRRGSB::get_gsb(const size_t& x, const size_t& y) const {
const RRGSB& DeviceRRGSB::get_gsb_by_cb_coordinate( const RRGSB& DeviceRRGSB::get_gsb_by_cb_coordinate(
const t_rr_type& cb_type, const vtr::Point<size_t>& coordinate) const { const t_rr_type& cb_type, const vtr::Point<size_t>& coordinate) const {
vtr::Point<size_t> gsb_coord = coordinate; vtr::Point<size_t> gsb_coord = coordinate;
/* TODO move the coordinate conversion to RRGSB */
switch (cb_type) {
case CHANX:
break;
case CHANY:
gsb_coord.set_y(gsb_coord.y() - 1);
break;
default:
VTR_LOG("Invalid type of connection block!\n");
exit(1);
}
VTR_ASSERT(validate_coordinate(gsb_coord)); VTR_ASSERT(validate_coordinate(gsb_coord));
return rr_gsb_[gsb_coord.x()][gsb_coord.y()]; return rr_gsb_[gsb_coord.x()][gsb_coord.y()];