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Merge branch 'master' into openfpga-issue-1256

This commit is contained in:
chungshien 2023-07-31 01:18:10 -07:00 committed by GitHub
parent aae037bf77 4e332f22d4
commit c1b5ca0941
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GPG Key ID: 4AEE18F83AFDEB23
26 changed files with 619 additions and 51 deletions
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2
VERSION.md
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@ -1 +1 @@
1.2.1281
1.2.1301

95
openfpga/src/annotation/fabric_tile.cpp
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@ -4,6 +4,7 @@
#include "fabric_tile.h"
#include "build_top_module_utils.h"
#include "command_exit_codes.h"
#include "vtr_assert.h"
#include "vtr_log.h"
@ -23,10 +24,20 @@ vtr::Point<size_t> FabricTile::unique_tile_coordinate(
return tile_coordinate(unique_fabric_tile_id);
}
FabricTileId FabricTile::find_unique_tile(const FabricTileId& tile_id) const {
vtr::Point<size_t> tile_coord = tile_coordinate(tile_id);
return unique_tile(tile_coord);
}
std::vector<vtr::Point<size_t>> FabricTile::pb_coordinates(
const FabricTileId& tile_id) const {
VTR_ASSERT(valid_tile_id(tile_id));
return pb_coords_[tile_id];
std::vector<vtr::Point<size_t>> pb_root_coords;
pb_root_coords.reserve(pb_coords_[tile_id].size());
for (auto curr_rect : pb_coords_[tile_id]) {
pb_root_coords.push_back(curr_rect.bottom_left());
}
return pb_root_coords;
}
std::vector<vtr::Point<size_t>> FabricTile::cb_coordinates(
@ -206,8 +217,7 @@ size_t FabricTile::find_pb_index_in_tile(const FabricTileId& tile_id,
return pb_gsb_coords_[tile_id].size();
} else {
for (size_t idx = 0; idx < pb_coords_[tile_id].size(); ++idx) {
vtr::Point<size_t> curr_coord = pb_coords_[tile_id][idx];
if (curr_coord == coord) {
if (pb_coords_[tile_id][idx].coincident(coord)) {
return idx;
}
}
@ -241,11 +251,11 @@ bool FabricTile::cb_in_tile(const FabricTileId& tile_id,
switch (cb_type) {
case CHANX:
return !cbx_coords_[tile_id].empty() &&
find_cb_index_in_tile(tile_id, cb_type, coord) ==
find_cb_index_in_tile(tile_id, cb_type, coord) !=
cbx_coords_[tile_id].size();
case CHANY:
return !cby_coords_[tile_id].empty() &&
find_cb_index_in_tile(tile_id, cb_type, coord) ==
find_cb_index_in_tile(tile_id, cb_type, coord) !=
cby_coords_[tile_id].size();
default:
VTR_LOG("Invalid type of connection block!\n");
@ -280,6 +290,29 @@ size_t FabricTile::find_cb_index_in_tile(
}
}
vtr::Point<size_t> FabricTile::find_cb_coordinate_in_unique_tile(
const FabricTileId& tile_id, const t_rr_type& cb_type,
const vtr::Point<size_t>& cb_coord) const {
size_t cb_idx_in_curr_tile =
find_cb_index_in_tile(tile_id, cb_type, cb_coord);
FabricTileId unique_tile = find_unique_tile(tile_id);
return cb_coordinates(unique_tile, cb_type)[cb_idx_in_curr_tile];
}
vtr::Point<size_t> FabricTile::find_pb_coordinate_in_unique_tile(
const FabricTileId& tile_id, const vtr::Point<size_t>& pb_coord) const {
size_t pb_idx_in_curr_tile = find_pb_index_in_tile(tile_id, pb_coord);
FabricTileId unique_tile = find_unique_tile(tile_id);
return pb_coordinates(unique_tile)[pb_idx_in_curr_tile];
}
vtr::Point<size_t> FabricTile::find_sb_coordinate_in_unique_tile(
const FabricTileId& tile_id, const vtr::Point<size_t>& sb_coord) const {
size_t sb_idx_in_curr_tile = find_sb_index_in_tile(tile_id, sb_coord);
FabricTileId unique_tile = find_unique_tile(tile_id);
return sb_coordinates(unique_tile)[sb_idx_in_curr_tile];
}
std::vector<FabricTileId> FabricTile::unique_tiles() const {
return unique_tile_ids_;
}
@ -493,12 +526,49 @@ int FabricTile::add_pb_coordinate(const FabricTileId& tile_id,
const vtr::Point<size_t>& coord,
const vtr::Point<size_t>& gsb_coord) {
VTR_ASSERT(valid_tile_id(tile_id));
pb_coords_[tile_id].push_back(coord);
pb_coords_[tile_id].push_back(vtr::Rect<size_t>(coord, coord));
pb_gsb_coords_[tile_id].push_back(gsb_coord);
/* Register in fast look-up */
return register_pb_in_lookup(tile_id, coord);
}
int FabricTile::set_pb_max_coordinate(const FabricTileId& tile_id,
const size_t& pb_index,
const vtr::Point<size_t>& max_coord) {
VTR_ASSERT(valid_tile_id(tile_id));
if (pb_index >= pb_coords_[tile_id].size()) {
VTR_LOG_ERROR(
"Invalid pb_index '%lu' is out of range of programmable block list "
"(size='%lu') of tile[%lu][%lu]!\n",
pb_index, pb_coords_[tile_id].size(), tile_coordinate(tile_id).x(),
tile_coordinate(tile_id).y());
return CMD_EXEC_FATAL_ERROR;
}
if (max_coord.x() < pb_coords_[tile_id][pb_index].xmin() ||
max_coord.y() < pb_coords_[tile_id][pb_index].ymin()) {
VTR_LOG_ERROR(
"Invalid max. coordinate (%lu, %lu) is out of range of programmable "
"block list (%lu, %lu) <-> (%lu, %lu) of tile[%lu][%lu]!\n",
max_coord.x(), max_coord.y(), pb_coords_[tile_id][pb_index].xmin(),
pb_coords_[tile_id][pb_index].ymin(),
pb_coords_[tile_id][pb_index].xmax(),
pb_coords_[tile_id][pb_index].ymax(), tile_coordinate(tile_id).x(),
tile_coordinate(tile_id).y());
return CMD_EXEC_FATAL_ERROR;
}
pb_coords_[tile_id][pb_index].set_xmax(max_coord.x());
pb_coords_[tile_id][pb_index].set_ymax(max_coord.y());
/* Update fast lookup */
for (size_t ix = pb_coords_[tile_id][pb_index].xmin();
ix <= pb_coords_[tile_id][pb_index].xmax(); ++ix) {
for (size_t iy = pb_coords_[tile_id][pb_index].ymin();
iy <= pb_coords_[tile_id][pb_index].ymax(); ++iy) {
register_pb_in_lookup(tile_id, vtr::Point<size_t>(ix, iy));
}
}
return CMD_EXEC_SUCCESS;
}
int FabricTile::add_cb_coordinate(const FabricTileId& tile_id,
const t_rr_type& cb_type,
const vtr::Point<size_t>& coord) {
@ -561,8 +631,8 @@ bool FabricTile::equivalent_tile(const FabricTileId& tile_a,
}
/* The pb of two tiles should be the same, otherwise not equivalent */
for (size_t iblk = 0; iblk < pb_coords_[tile_a].size(); ++iblk) {
vtr::Point<size_t> tile_a_pb_coord = pb_coords_[tile_a][iblk];
vtr::Point<size_t> tile_b_pb_coord = pb_coords_[tile_b][iblk];
vtr::Point<size_t> tile_a_pb_coord = pb_coords_[tile_a][iblk].bottom_left();
vtr::Point<size_t> tile_b_pb_coord = pb_coords_[tile_b][iblk].bottom_left();
if (generate_grid_block_module_name_in_top_module(std::string(), grids,
tile_a_pb_coord) !=
generate_grid_block_module_name_in_top_module(std::string(), grids,
@ -597,7 +667,8 @@ bool FabricTile::equivalent_tile(const FabricTileId& tile_a,
}
int FabricTile::build_unique_tiles(const DeviceGrid& grids,
const DeviceRRGSB& device_rr_gsb) {
const DeviceRRGSB& device_rr_gsb,
const bool& verbose) {
for (size_t ix = 0; ix < grids.width(); ++ix) {
for (size_t iy = 0; iy < grids.height(); ++iy) {
if (!valid_tile_id(tile_coord2id_lookup_[ix][iy])) {
@ -607,6 +678,10 @@ int FabricTile::build_unique_tiles(const DeviceGrid& grids,
for (FabricTileId unique_tile_id : unique_tile_ids_) {
if (equivalent_tile(tile_coord2id_lookup_[ix][iy], unique_tile_id,
grids, device_rr_gsb)) {
VTR_LOGV(verbose,
"Tile[%lu][%lu] is a mirror to the unique tile[%lu][%lu]\n",
ix, iy, tile_coordinate(unique_tile_id).x(),
tile_coordinate(unique_tile_id).y());
is_unique_tile = false;
tile_coord2unique_tile_ids_[ix][iy] = unique_tile_id;
break;
@ -614,6 +689,8 @@ int FabricTile::build_unique_tiles(const DeviceGrid& grids,
}
/* Update list if this is a unique tile */
if (is_unique_tile) {
VTR_LOGV(verbose, "Tile[%lu][%lu] is added as a new unique tile\n", ix,
iy);
unique_tile_ids_.push_back(tile_coord2id_lookup_[ix][iy]);
tile_coord2unique_tile_ids_[ix][iy] = tile_coord2id_lookup_[ix][iy];
}

35
openfpga/src/annotation/fabric_tile.h
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@ -25,6 +25,8 @@ namespace openfpga {
class FabricTile {
public: /* Accessors */
vtr::Point<size_t> tile_coordinate(const FabricTileId& tile_id) const;
/* Return all the root (bottom-left point) coordinates of programmable blocks
* under a given tile. */
std::vector<vtr::Point<size_t>> pb_coordinates(
const FabricTileId& tile_id) const;
std::vector<vtr::Point<size_t>> cb_coordinates(
@ -34,6 +36,9 @@ class FabricTile {
/** @brief With a given coordinate, find the id of the unique tile (which is
* the same as the tile in structure) */
FabricTileId unique_tile(const vtr::Point<size_t>& coord) const;
/** @brief With a given tile id, find the id of its unique tile (which is
* the same as the tile in structure) */
FabricTileId find_unique_tile(const FabricTileId& tile_id) const;
/** @brief Find the tile info with a given coordinate */
FabricTileId find_tile(const vtr::Point<size_t>& coord) const;
/** @brief Find the id of a tile, with a given coordinate of the programmable
@ -68,6 +73,28 @@ class FabricTile {
size_t find_cb_index_in_tile(const FabricTileId& tile_id,
const t_rr_type& cb_type,
const vtr::Point<size_t>& coord) const;
/** @brief Find the coodinate of a connection block in its unique tile. For
* example, a cbx[1][0] is the 2nd element of the connection block list in
* tile[1][1], while the unique tile of tile[1][1] is tile[2][2]. We will find
* the 2nd element of the connection block list in tile[2][2] and return its
* coordinate. Error out on any exception. */
vtr::Point<size_t> find_cb_coordinate_in_unique_tile(
const FabricTileId& tile_id, const t_rr_type& cb_type,
const vtr::Point<size_t>& cb_coord) const;
/** @brief Find the coodinate of a programmable block in its unique tile. For
* example, a pb[1][0] is the 2nd element of the programmable block list in
* tile[1][1], while the unique tile of tile[1][1] is tile[2][2]. We will find
* the 2nd element of the programmable block list in tile[2][2] and return its
* coordinate. Error out on any exception. */
vtr::Point<size_t> find_pb_coordinate_in_unique_tile(
const FabricTileId& tile_id, const vtr::Point<size_t>& pb_coord) const;
/** @brief Find the coodinate of a switch block in its unique tile. For
* example, a pb[1][0] is the 2nd element of the switch block list in
* tile[1][1], while the unique tile of tile[1][1] is tile[2][2]. We will find
* the 2nd element of the switch block list in tile[2][2] and return its
* coordinate. Error out on any exception. */
vtr::Point<size_t> find_sb_coordinate_in_unique_tile(
const FabricTileId& tile_id, const vtr::Point<size_t>& sb_coord) const;
/** @brief Check if a programmable block (with a coordinate) exists in a tile.
* Note that the coord can be either the one in device grid or the one of gsb
* which the programmable block belongs to
@ -90,6 +117,10 @@ class FabricTile {
int add_pb_coordinate(const FabricTileId& tile_id,
const vtr::Point<size_t>& coord,
const vtr::Point<size_t>& gsb_coord);
/* Set the top-right coordinate of a pb. This is mainly for heterogeneous
* blocks, whose height or width can be > 1 */
int set_pb_max_coordinate(const FabricTileId& tile_id, const size_t& pb_index,
const vtr::Point<size_t>& max_coord);
int add_cb_coordinate(const FabricTileId& tile_id, const t_rr_type& cb_type,
const vtr::Point<size_t>& coord);
int add_sb_coordinate(const FabricTileId& tile_id,
@ -103,7 +134,7 @@ class FabricTile {
void init(const vtr::Point<size_t>& max_coord);
/** @brief Identify the number of unique tiles and keep in the lookup */
int build_unique_tiles(const DeviceGrid& grids,
const DeviceRRGSB& device_rr_gsb);
const DeviceRRGSB& device_rr_gsb, const bool& verbose);
public: /* Validators */
bool valid_tile_id(const FabricTileId& tile_id) const;
@ -143,7 +174,7 @@ class FabricTile {
* organization (to follow bottom-left corner style). This limitation can be
* resolved.
*/
vtr::vector<FabricTileId, std::vector<vtr::Point<size_t>>> pb_coords_;
vtr::vector<FabricTileId, std::vector<vtr::Rect<size_t>>> pb_coords_;
vtr::vector<FabricTileId, std::vector<vtr::Point<size_t>>> pb_gsb_coords_;
vtr::vector<FabricTileId, std::vector<vtr::Point<size_t>>> cbx_coords_;
vtr::vector<FabricTileId, std::vector<vtr::Point<size_t>>> cby_coords_;

10
openfpga/src/fabric/build_fabric_tile.cpp
View File

@ -72,6 +72,14 @@ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile,
curr_tile_coord.x(), curr_tile_coord.y(), root_tile_coord.x(),
root_tile_coord.y());
curr_tile_id = fabric_tile.find_tile(root_tile_coord);
/* Update the coordinates of the pb in tiles */
size_t root_pb_idx_in_curr_tile =
fabric_tile.find_pb_index_in_tile(curr_tile_id, root_tile_coord);
status_code = fabric_tile.set_pb_max_coordinate(
curr_tile_id, root_pb_idx_in_curr_tile, vtr::Point<size_t>(ix, iy));
if (status_code != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
} else {
/* Need to create a new tile here */
VTR_LOGV(verbose, "Create a regular tile[%lu][%lu]\n",
@ -153,7 +161,7 @@ int build_fabric_tile(FabricTile& fabric_tile, const TileConfig& tile_config,
/* Build unique tiles to compress the number of tile modules to be built in
* later steps */
status_code = fabric_tile.build_unique_tiles(grids, device_rr_gsb);
status_code = fabric_tile.build_unique_tiles(grids, device_rr_gsb, verbose);
VTR_LOGV(verbose, "Extracted %lu uniques tiles from the FPGA fabric\n",
fabric_tile.unique_tiles().size());

39
openfpga/src/fabric/build_tile_modules.cpp
View File

@ -599,11 +599,18 @@ static int build_tile_module_port_and_nets_between_sb_and_cb(
/* Check if the grid is inside the tile, if not, create ports */
if (fabric_tile.cb_in_tile(fabric_tile_id, cb_type,
instance_cb_coordinate)) {
instance_gsb_cb_coordinate)) {
VTR_LOGV(
verbose,
"Skip adding ports to tile as connection block '%s' is part of the "
"tile along with the switch block '%s'...\n",
generate_connection_block_module_name(cb_type, instance_cb_coordinate)
.c_str(),
sb_module_name.c_str());
if (!frame_view) {
size_t cb_instance =
cb_instances.at(cb_type)[fabric_tile.find_cb_index_in_tile(
fabric_tile_id, cb_type, instance_cb_coordinate)];
fabric_tile_id, cb_type, instance_gsb_cb_coordinate)];
for (size_t itrack = 0;
itrack < module_sb.get_chan_width(side_manager.get_side());
@ -902,8 +909,9 @@ static int build_tile_module_ports_from_cb(
*/
vtr::Point<size_t> cb_coord_in_unique_tile =
fabric_tile.cb_coordinates(curr_fabric_tile_id, cb_type)[icb];
std::string cb_instance_name_in_tile =
generate_connection_block_module_name(cb_type, cb_coord_in_unique_tile);
const RRGSB& unique_rr_gsb = device_rr_gsb.get_gsb(cb_coord_in_unique_tile);
std::string cb_instance_name_in_tile = generate_connection_block_module_name(
cb_type, unique_rr_gsb.get_cb_coordinate(cb_type));
vtr::Point<size_t> tile_coord =
fabric_tile.tile_coordinate(curr_fabric_tile_id);
@ -1112,7 +1120,8 @@ static int build_tile_port_and_nets_from_pb(
size_t num_fanout_in_tile =
module_manager.module_net_sinks(tile_module, curr_net).size();
RRNodeId rr_node = rr_graph.node_lookup().find_node(
pb_coord.x(), pb_coord.y(), OPIN, ipin, side);
pb_coord.x() + iwidth, pb_coord.y() + iheight, OPIN, ipin,
side);
size_t num_fanout_required =
rr_graph.node_out_edges(rr_node).size();
if (num_fanout_in_tile == num_fanout_required) {
@ -1325,8 +1334,11 @@ static int build_tile_module(
module_manager.add_configurable_child(tile_module, pb_module,
pb_instance);
}
VTR_LOGV(verbose, "Added programmable module '%s' to tile[%lu][%lu]\n",
pb_module_name.c_str(), tile_coord.x(), tile_coord.y());
VTR_LOGV(
verbose,
"Added programmable module '%s' (instance: '%s') to tile[%lu][%lu]\n",
pb_module_name.c_str(), pb_instance_name.c_str(), tile_coord.x(),
tile_coord.y());
pb_instances.push_back(pb_instance);
/* Add a custom I/O child with the grid */
module_manager.add_io_child(
@ -1370,8 +1382,10 @@ static int build_tile_module(
cb_instance);
}
VTR_LOGV(verbose,
"Added connection block module '%s' to tile[%lu][%lu]\n",
cb_module_name.c_str(), tile_coord.x(), tile_coord.y());
"Added connection block module '%s' (instance: '%s') to "
"tile[%lu][%lu]\n",
cb_module_name.c_str(), cb_instance_name.c_str(), tile_coord.x(),
tile_coord.y());
cb_instances[cb_type].push_back(cb_instance);
}
}
@ -1406,8 +1420,11 @@ static int build_tile_module(
module_manager.add_configurable_child(tile_module, sb_module,
sb_instance);
}
VTR_LOGV(verbose, "Added switch block module '%s' to tile[%lu][%lu]\n",
sb_module_name.c_str(), tile_coord.x(), tile_coord.y());
VTR_LOGV(
verbose,
"Added switch block module '%s' (instance: %s') to tile[%lu][%lu]\n",
sb_module_name.c_str(), sb_instance_name.c_str(), tile_coord.x(),
tile_coord.y());
sb_instances.push_back(sb_instance);
}

11
openfpga/src/fabric/build_top_module_child_tile_instance.cpp
View File

@ -816,7 +816,7 @@ static int build_top_module_tile_nets_between_sb_and_cb(
/* Check if the grid is inside the tile, if not, create ports */
if (fabric_tile.cb_in_tile(curr_fabric_tile_id, cb_type,
instance_cb_coordinate)) {
instance_gsb_cb_coordinate)) {
continue;
}
/* Collect cb tile information */
@ -830,9 +830,11 @@ static int build_top_module_tile_nets_between_sb_and_cb(
fabric_tile.tile_coordinate(cb_unique_tile);
vtr::Point<size_t> cb_coord_in_cb_unique_tile =
fabric_tile.cb_coordinates(cb_unique_tile, cb_type)[cb_idx_in_cb_tile];
const RRGSB& unique_cb_rr_gsb =
device_rr_gsb.get_gsb(cb_coord_in_cb_unique_tile);
std::string cb_instance_name_in_unique_tile =
generate_connection_block_module_name(cb_type,
cb_coord_in_cb_unique_tile);
generate_connection_block_module_name(
cb_type, unique_cb_rr_gsb.get_cb_coordinate(cb_type));
std::string cb_tile_module_name =
generate_tile_module_name(cb_unique_tile_coord);
ModuleId cb_tile_module = module_manager.find_module(cb_tile_module_name);
@ -878,6 +880,9 @@ static int build_top_module_tile_nets_between_sb_and_cb(
cb_type, cb_port_direction, use_cb_upper_port);
std::string cb_tile_cb_port_name = generate_tile_module_port_name(
cb_instance_name_in_unique_tile, cb_port_name);
VTR_LOGV(
verbose, "Finding port '%s' from connection block in tile [%lu][%lu]\n",
cb_tile_cb_port_name.c_str(), cb_tile_coord.x(), cb_tile_coord.y());
ModulePortId cb_port_id =
module_manager.find_module_port(cb_tile_module, cb_tile_cb_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(cb_tile_module,

35
openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
View File

@ -727,7 +727,8 @@ static void rec_build_physical_block_bitstream(
*******************************************************************/
static void build_physical_block_bitstream(
BitstreamManager& bitstream_manager, const ConfigBlockId& top_block,
const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
const ModuleManager& module_manager, const FabricTile& fabric_tile,
const FabricTileId& curr_tile, const CircuitLibrary& circuit_lib,
const MuxLibrary& mux_lib, const AtomContext& atom_ctx,
const VprDeviceAnnotation& device_annotation,
const VprClusteringAnnotation& cluster_annotation,
@ -751,9 +752,17 @@ static void build_physical_block_bitstream(
return;
}
vtr::Point<size_t> grid_coord_in_unique_tile = grid_coord;
if (fabric_tile.valid_tile_id(curr_tile)) {
/* For tile modules, need to find the specific instance name under its
* unique tile */
grid_coord_in_unique_tile =
fabric_tile.find_pb_coordinate_in_unique_tile(curr_tile, grid_coord);
}
std::string grid_block_name = generate_grid_block_instance_name(
grid_module_name_prefix, std::string(grid_type->name),
is_io_type(grid_type), border_side, grid_coord);
is_io_type(grid_type), border_side, grid_coord_in_unique_tile);
ConfigBlockId grid_configurable_block =
bitstream_manager.add_block(grid_block_name);
bitstream_manager.add_child_block(top_block, grid_configurable_block);
@ -854,12 +863,17 @@ void build_grid_bitstream(
std::string tile_inst_name = generate_tile_module_name(tile_coord);
parent_block = bitstream_manager.find_or_create_child_block(
top_block, tile_inst_name);
VTR_LOGV(verbose,
"Add configurable block '%s' as a child under configurable "
"block '%s'\n",
tile_inst_name.c_str(),
bitstream_manager.block_name(top_block).c_str());
}
build_physical_block_bitstream(
bitstream_manager, parent_block, module_manager, circuit_lib, mux_lib,
atom_ctx, device_annotation, cluster_annotation, place_annotation,
bitstream_annotation, grids, grid_coord, NUM_SIDES);
bitstream_manager, parent_block, module_manager, fabric_tile, curr_tile,
circuit_lib, mux_lib, atom_ctx, device_annotation, cluster_annotation,
place_annotation, bitstream_annotation, grids, grid_coord, NUM_SIDES);
}
}
VTR_LOGV(verbose, "Done\n");
@ -895,12 +909,17 @@ void build_grid_bitstream(
std::string tile_inst_name = generate_tile_module_name(tile_coord);
parent_block = bitstream_manager.find_or_create_child_block(
top_block, tile_inst_name);
VTR_LOGV(verbose,
"Add configurable block '%s' as a child under configurable "
"block '%s'\n",
tile_inst_name.c_str(),
bitstream_manager.block_name(parent_block).c_str());
}
build_physical_block_bitstream(
bitstream_manager, parent_block, module_manager, circuit_lib, mux_lib,
atom_ctx, device_annotation, cluster_annotation, place_annotation,
bitstream_annotation, grids, io_coordinate, io_side);
bitstream_manager, parent_block, module_manager, fabric_tile, curr_tile,
circuit_lib, mux_lib, atom_ctx, device_annotation, cluster_annotation,
place_annotation, bitstream_annotation, grids, io_coordinate, io_side);
}
}
VTR_LOGV(verbose, "Done\n");

36
openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
View File

@ -498,17 +498,29 @@ static void build_connection_block_bitstreams(
ConfigBlockId parent_block = top_configurable_block;
FabricTileId curr_tile = fabric_tile.find_tile_by_cb_coordinate(
cb_type, vtr::Point<size_t>(ix, iy));
ConfigBlockId cb_configurable_block;
if (fabric_tile.valid_tile_id(curr_tile)) {
vtr::Point<size_t> tile_coord = fabric_tile.tile_coordinate(curr_tile);
std::string tile_inst_name = generate_tile_module_name(tile_coord);
parent_block = bitstream_manager.find_or_create_child_block(
top_configurable_block, tile_inst_name);
}
/* Create a block for the bitstream which corresponds to the Switch block
/* For tile modules, need to find the specific instance name under its
* unique tile */
vtr::Point<size_t> cb_coord_in_unique_tile =
fabric_tile.find_cb_coordinate_in_unique_tile(
curr_tile, cb_type, vtr::Point<size_t>(ix, iy));
const RRGSB& unique_tile_cb_rr_gsb =
device_rr_gsb.get_gsb(cb_coord_in_unique_tile);
cb_configurable_block =
bitstream_manager.add_block(generate_connection_block_module_name(
cb_type, unique_tile_cb_rr_gsb.get_cb_coordinate(cb_type)));
} else {
/* Create a block for the bitstream which corresponds to the Switch
* block
*/
ConfigBlockId cb_configurable_block = bitstream_manager.add_block(
cb_configurable_block = bitstream_manager.add_block(
generate_connection_block_module_name(cb_type, cb_coord));
}
/* Set switch block as a child of top block */
bitstream_manager.add_child_block(parent_block, cb_configurable_block);
@ -592,17 +604,25 @@ void build_routing_bitstream(
* If any block is missing during the back tracing, create it. */
ConfigBlockId parent_block = top_configurable_block;
FabricTileId curr_tile = fabric_tile.find_tile_by_sb_coordinate(sb_coord);
ConfigBlockId sb_configurable_block;
if (fabric_tile.valid_tile_id(curr_tile)) {
vtr::Point<size_t> tile_coord = fabric_tile.tile_coordinate(curr_tile);
std::string tile_inst_name = generate_tile_module_name(tile_coord);
parent_block = bitstream_manager.find_or_create_child_block(
top_configurable_block, tile_inst_name);
}
/* Create a block for the bitstream which corresponds to the Switch block
/* For tile modules, need to find the specific instance name under its
* unique tile */
vtr::Point<size_t> sb_coord_in_unique_tile =
fabric_tile.find_sb_coordinate_in_unique_tile(curr_tile, sb_coord);
sb_configurable_block = bitstream_manager.add_block(
generate_switch_block_module_name(sb_coord_in_unique_tile));
} else {
/* Create a block for the bitstream which corresponds to the Switch
* block
*/
ConfigBlockId sb_configurable_block = bitstream_manager.add_block(
sb_configurable_block = bitstream_manager.add_block(
generate_switch_block_module_name(sb_coord));
}
/* Set switch block as a child of top block */
bitstream_manager.add_child_block(parent_block, sb_configurable_block);

82
openfpga_flow/openfpga_shell_scripts/group_tile_clkntwk_preconfig_testbench_example_script.openfpga Normal file
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@ -0,0 +1,82 @@
# Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Read OpenFPGA clock architecture
read_openfpga_clock_arch -f ${OPENFPGA_CLOCK_ARCH_FILE}
# Append clock network to vpr's routing resource graph
append_clock_rr_graph
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --sort_gsb_chan_node_in_edges
# Route clock based on clock network definition
route_clock_rr_graph
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
# Apply fix-up to Look-Up Table truth tables based on packing results
lut_truth_table_fixup
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
build_fabric --compress_routing --group_tile ${OPENFPGA_GROUP_TILE_CONFIG_FILE} #--verbose
# Write the fabric hierarchy of module graph to a file
# This is used by hierarchical PnR flows
write_fabric_hierarchy --file ./fabric_hierarchy.txt
# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation
# Strongly recommend it is done after all the fix-up have been applied
repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
# Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists
# - Must specify the reference benchmark file if you want to output any testbenches
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS}
# Write the SDC files for PnR backend
# - Turn on every options here
# FIXME: Not supported yet.
#write_pnr_sdc --file ./SDC
# Write SDC to disable timing for configure ports
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
# Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ./SDC_analysis
# Finish and exit OpenFPGA
exit
# Note :
# To run verification at the end of the flow maintain source in ./SRC directory

11
openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga
View File

@ -1,6 +1,6 @@
# Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal ${OPENFPGA_VPR_EXTRA_OPTIONS}
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
@ -10,11 +10,14 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
link_openfpga_arch --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
# Optionally pb pin fixup
${OPENFPGA_PB_PIN_FIXUP_COMMAND}
# Apply fix-up to Look-Up Table truth tables based on packing results
lut_truth_table_fixup
@ -52,8 +55,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS}
# Write the SDC files for PnR backend
# - Turn on every options here

6
openfpga_flow/regression_test_scripts/basic_reg_test.sh
View File

@ -179,6 +179,12 @@ echo -e "Testing tile grouping on a homogeneous FPGA fabric (Full testbench)";
run-task basic_tests/tile_organization/homo_fabric_tile $@
echo -e "Testing tile grouping on a homogeneous FPGA fabric (Preconfigured testbench)";
run-task basic_tests/tile_organization/homo_fabric_tile_preconfig $@
run-task basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig $@
run-task basic_tests/tile_organization/homo_fabric_tile_4x4_preconfig $@
run-task basic_tests/tile_organization/homo_fabric_tile_global_tile_clock $@
run-task basic_tests/tile_organization/homo_fabric_tile_adder_chain $@
run-task basic_tests/tile_organization/homo_fabric_tile_clkntwk $@
run-task basic_tests/tile_organization/hetero_fabric_tile $@
echo -e "Testing global port definition from tiles";
run-task basic_tests/global_tile_ports/global_tile_clock $@

54
openfpga_flow/tasks/basic_tests/tile_organization/hetero_fabric_tile/config/task.conf Normal file
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@ -0,0 +1,54 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_vpr_extra_options=--constant_net_method route --skip_sync_clustering_and_routing_results on
openfpga_pb_pin_fixup_command = pb_pin_fixup --verbose
openfpga_vpr_device=3x2
openfpga_vpr_route_chan_width=60
openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml
openfpga_verilog_testbench_options=
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_2/mac_2.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_4/mac_4.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_6/mac_6.v
bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8/mac_8.v
[SYNTHESIS_PARAM]
# Yosys script parameters
bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_cell_sim.v
bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_dsp_map.v
bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
bench0_top = mac_2
bench1_top = mac_4
bench2_top = mac_6
bench3_top = mac_8
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=

1
openfpga_flow/tasks/basic_tests/tile_organization/hetero_fabric_tile/config/tile_config.xml Normal file
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@ -0,0 +1 @@
<tiles style="top_left"/>

41
openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig/config/task.conf Normal file
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@ -0,0 +1,41 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_vpr_extra_options=
openfpga_pb_pin_fixup_command=
openfpga_vpr_device=2x2
openfpga_vpr_route_chan_width=20
openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml
openfpga_verilog_testbench_options=--explicit_port_mapping
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = or2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=

1
openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig/config/tile_config.xml Normal file
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@ -0,0 +1 @@
<tiles style="top_left"/>

41
openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_4x4_preconfig/config/task.conf Normal file
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@ -0,0 +1,41 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_vpr_extra_options=
openfpga_pb_pin_fixup_command=
openfpga_vpr_device=4x4
openfpga_vpr_route_chan_width=20
openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml
openfpga_verilog_testbench_options=--explicit_port_mapping
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = or2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=

1
openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_4x4_preconfig/config/tile_config.xml Normal file
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@ -0,0 +1 @@
<tiles style="top_left"/>

48
openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_adder_chain/config/task.conf Normal file
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@ -0,0 +1,48 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_vpr_extra_options=
openfpga_pb_pin_fixup_command=
openfpga_vpr_device=auto
openfpga_vpr_route_chan_width=40
openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml
openfpga_verilog_testbench_options=
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.v
[SYNTHESIS_PARAM]
# Yosys script parameters
bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_adders_sim.v
bench_yosys_adder_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_arith_map.v
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
# Benchmark information
bench0_top = adder_8
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=

1
openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_adder_chain/config/tile_config.xml Normal file
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@ -0,0 +1 @@
<tiles style="top_left"/>

17
openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_clkntwk/config/clk_arch_1clk_2layer.xml Normal file
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@ -0,0 +1,17 @@
<clock_networks default_segment="L1" default_switch="ipin_cblock">
<clock_network name="clk_tree_2lvl" width="1">
<spine name="spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1">
<switch_point tap="rib_lvl1_sw0_upper" x="1" y="1"/>
<switch_point tap="rib_lvl1_sw0_lower" x="1" y="1"/>
<switch_point tap="rib_lvl1_sw1_upper" x="2" y="1"/>
<switch_point tap="rib_lvl1_sw1_lower" x="2" y="1"/>
</spine>
<spine name="rib_lvl1_sw0_upper" start_x="1" start_y="2" end_x="1" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
<spine name="rib_lvl1_sw0_lower" start_x="1" start_y="1" end_x="1" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
<spine name="rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
<spine name="rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
<taps>
<tap tile_pin="clb[0:0].clk[0:0]"/>
</taps>
</clock_network>
</clock_networks>

40
openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_clkntwk/config/task.conf Normal file
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@ -0,0 +1,40 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_clkntwk_preconfig_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk1clk2lvl_cc_openfpga.xml
openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_2layer.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_vpr_device=2x2
openfpga_vpr_route_chan_width=24
openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml
openfpga_verilog_testbench_options=--explicit_port_mapping
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk1clk2lvl_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2_latch
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=

1
openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_clkntwk/config/tile_config.xml Normal file
View File

@ -0,0 +1 @@
<tiles style="top_left"/>

41
openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_global_tile_clock/config/task.conf Normal file
View File

@ -0,0 +1,41 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_vpr_extra_options=
openfpga_pb_pin_fixup_command=
openfpga_vpr_device=auto
openfpga_vpr_route_chan_width=20
openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml
openfpga_verilog_testbench_options=--explicit_port_mapping
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2_latch
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=

1
openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_global_tile_clock/config/tile_config.xml Normal file
View File

@ -0,0 +1 @@
<tiles style="top_left"/>

9
openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_preconfig/config/task.conf
View File

@ -9,7 +9,7 @@
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 20*60
@ -18,8 +18,13 @@ fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_vpr_extra_options=
openfpga_pb_pin_fixup_command=
openfpga_vpr_device=auto
openfpga_vpr_route_chan_width=20
openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml
openfpga_verilog_testbench_options=--explicit_port_mapping
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml

7
openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml
View File

@ -87,6 +87,13 @@
<!--Fill with 'clb'-->
<fill type="clb" priority="10"/>
</fixed_layout>
<fixed_layout name="4x4" width="6" height="6">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'-->
<fill type="clb" priority="10"/>
</fixed_layout>
</layout>
<device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM