From c16bcd7f63a97291d484119414b9d20bec42199e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 28 Jul 2022 16:35:13 -0700 Subject: [PATCH] [doc] add file formates required by pcf2place --- docs/source/manual/file_formats/index.rst | 2 + .../manual/file_formats/pin_table_file.rst | 48 +++++++++++++++++++ .../openfpga_commands/setup_commands.rst | 2 +- 3 files changed, 51 insertions(+), 1 deletion(-) create mode 100644 docs/source/manual/file_formats/pin_table_file.rst diff --git a/docs/source/manual/file_formats/index.rst b/docs/source/manual/file_formats/index.rst index 97c735112..49332c134 100644 --- a/docs/source/manual/file_formats/index.rst +++ b/docs/source/manual/file_formats/index.rst @@ -31,3 +31,5 @@ OpenFPGA widely uses XML format for interchangable files bus_group_file pcf_file + + pin_table_file diff --git a/docs/source/manual/file_formats/pin_table_file.rst b/docs/source/manual/file_formats/pin_table_file.rst new file mode 100644 index 000000000..033f7c9b7 --- /dev/null +++ b/docs/source/manual/file_formats/pin_table_file.rst @@ -0,0 +1,48 @@ +.. _file_format_pin_table_file: + +Pin Table File (.csv) +--------------------- + +.. note:: This file is typically a spreadsheet provided by FPGA vendors. Please contact your vendor for the exact file. + +.. note:: OpenFPGA will not include or guarantee the correctness of the file!!! + +The pin table file is the file which describes the pin mapping between a chip and an FPGA inside the chip. + +An example of the file is shown as follows. + +.. code-block:: xml + + orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge + TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],,, + TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],,, + TOP,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[1],,, + TOP,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[1],,, + TOP,,,,gfpga_pad_IO_A2F[8],pad_fpga_io[2],,, + TOP,,,,gfpga_pad_IO_F2A[8],pad_fpga_io[2],,, + TOP,,,,gfpga_pad_IO_A2F[31],pad_fpga_io[3],,, + TOP,,,,gfpga_pad_IO_F2A[31],pad_fpga_io[3],,, + RIGHT,,,,gfpga_pad_IO_A2F[32],pad_fpga_io[4],,, + RIGHT,,,,gfpga_pad_IO_F2A[32],pad_fpga_io[4],,, + RIGHT,,,,gfpga_pad_IO_A2F[40],pad_fpga_io[5],,, + RIGHT,,,,gfpga_pad_IO_F2A[40],pad_fpga_io[5],,, + BOTTOM,,,,gfpga_pad_IO_A2F[64],pad_fpga_io[6],,, + BOTTOM,,,,gfpga_pad_IO_F2A[64],pad_fpga_io[6],,, + LEFT,,,,gfpga_pad_IO_F2A[127],pad_fpga_io[7],,, + LEFT,,,,gfpga_pad_IO_A2F[127],pad_fpga_io[7],,, + +An pin table may serve in various purposes. However, for OpenFPGA, the following attributes are required + +.. option:: orientation + + Specify on which side the pin locates + +.. option:: port_name + + Specify the port name of the FPGA fabric + +.. option:: mapped_pin + + Specify the pin name of the FPGA chip + +.. warning:: Currently, the direction of the port is inferred by the ``port_name``. A postfix of ``A2F`` indicates an input port, while a postfix of ``F2A`` indicates an output port. diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst index 37e8ead09..c49c9a0bc 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst @@ -258,7 +258,7 @@ pcf2place .. option:: --pin_table - Specify the path to the pin table file, which describes the pin mapping between chip I/Os to FPGA I/Os + Specify the path to the pin table file, which describes the pin mapping between chip I/Os and FPGA I/Os. See details in :ref:`file_format_pin_table_file` .. option:: --fpga_fix_pins