[HDL] Add embedded I/O HDL for Caravel SoC interface

openfpga_flow/openfpga_cell_library/verilog/gpio.v

@@ -38,3 +38,22 @@ module GPOUT (
 );
   assign Y = A;
 endmodule
+
+//-----------------------------------------------------
+// Function    : A minimum embedded I/O
+//               just an overlay to interface other components
+//-----------------------------------------------------
+module EMBEDDED_IO (
+  input SOC_IN, // Input to drive the inpad signal
+  output SOC_OUT, // Output the outpad signal
+  output SOC_DIR, // Output the directionality
+  output FPGA_IN, // Input data to FPGA
+  input FPGA_OUT, // Output data from FPGA
+  input FPGA_DIR // direction control 
+);
+
+  assign FPGA_IN = SOC_IN;
+  assign SOC_OUT = FPGA_OUT;
+  assign SOC_DIR = FPGA_DIR;
+endmodule
+