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[HDL] Bug fix in the GP output pad

This commit is contained in:
tangxifan 2020-11-02 18:37:53 -07:00
parent 1e47203c7c
commit c036c87d6d
1 changed files with 3 additions and 3 deletions
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6
openfpga_flow/openfpga_cell_library/verilog/gpio.v
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@ -33,8 +33,8 @@ endmodule
// Function : A minimum output pad // Function : A minimum output pad
//----------------------------------------------------- //-----------------------------------------------------
module GPOUT ( module GPOUT (
inout A, // External PAD signal inout Y, // External PAD signal
input Y // Data output input A // Data output
); );
assign A = Y; assign Y = A;
endmodule endmodule