Merge pull request #1593 from lnis-uofu/disable_repack_error_message

suppress repack commands' error message

docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst

@@ -460,6 +460,12 @@ pcf2place
   .. option:: --no_time_stamp
 
     Do not print time stamp in output files
+  
+  .. option:: --reduce_error_to_warning
+
+    Reduce error to warning while reading commands in pcf file
+  
+  .. warning:: Exercise extreme caution when adding this option – be sure you completely understand why the issue is being flagged, and why it is OK to treat as a warning instead of an error.
 
   .. option:: --verbose
 

libs/libpcf/src/io/pcf_reader.cpp

@@ -27,7 +27,8 @@ constexpr const char COMMENT = '#';
  * Return 1 if there are serious errors when parsing data
  * Return 2 if fail when opening files
  *******************************************************************/
-int read_pcf(const char* fname, PcfData& pcf_data) {
+int read_pcf(const char* fname, PcfData& pcf_data,
+             bool reduce_error_to_warning) {
   vtr::ScopedStartFinishTimer timer("Read " + std::string(fname));
 
   /* Create a file handler */
@@ -58,11 +59,16 @@ int read_pcf(const char* fname, PcfData& pcf_data) {
         } else if (word[0] == COMMENT) {  // if it's a comment
           break;  // or ignore the full line comment and move on
         } else {
-          /* Reach unknown command, error out */
+          if (reduce_error_to_warning) {
-          VTR_LOG_ERROR("Unknown command '%s'!\n", word.c_str());
+            VTR_LOG_WARN("Bypass unknown command '%s' !\n", word.c_str());
-          num_err++;
+            break;
-          break;  // and move onto next line. without this, it will accept more
+          } else {
-                  // following values on this line
+            /* Reach unknown command for OpenFpga, error out */
+            VTR_LOG_ERROR("Unknown command '%s'!\n", word.c_str());
+            num_err++;
+            break;  // and move onto next line. without this, it will accept
+                    // more following values on this line
+          }
         }
       }
     }

libs/libpcf/src/io/pcf_reader.h

@@ -16,7 +16,8 @@ namespace openfpga {
 
 /* Parse a .pcf file through a stream, return an object which contains all the
  * data */
-int read_pcf(const char* fname, PcfData& pcf_data);
+int read_pcf(const char* fname, PcfData& pcf_data,
+             bool reduce_error_to_warning = false);
 
 } /* End namespace openfpga*/
 

openfpga/src/base/openfpga_pcf2place_template.h

@@ -35,6 +35,8 @@ int pcf2place_wrapper_template(const Command& cmd,
   CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
   CommandOptionId opt_pin_table_dir_convention =
     cmd.option("pin_table_direction_convention");
+  CommandOptionId opt_reduce_error_to_warning =
+    cmd.option("reduce_error_to_warning");
   CommandOptionId opt_verbose = cmd.option("verbose");
 
   std::string pcf_fname = cmd_context.option_value(cmd, opt_pcf);
@@ -71,7 +73,9 @@ int pcf2place_wrapper_template(const Command& cmd,
 
   /* Parse the input files */
   openfpga::PcfData pcf_data;
-  openfpga::read_pcf(pcf_fname.c_str(), pcf_data);
+  openfpga::read_pcf(
+    pcf_fname.c_str(), pcf_data,
+    cmd_context.option_enable(cmd, opt_reduce_error_to_warning));
   VTR_LOG("Read the design constraints from a pcf file: %s.\n",
           pcf_fname.c_str());
 

openfpga/src/base/openfpga_setup_command_template.h

@@ -599,6 +599,11 @@ ShellCommandId add_pcf2place_command_template(
   shell_cmd.add_option("no_time_stamp", false,
                        "Do not print time stamp in output files");
 
+  /* Add an option '--reduce_error_to_warning' */
+  shell_cmd.add_option(
+    "reduce_error_to_warning", false,
+    "reduce error to warning while reading commands in pcf file");
+
   /* Add an option '--verbose' */
   shell_cmd.add_option("verbose", false, "Enable verbose output");
 

openfpga_flow/openfpga_shell_scripts/test_pcf.openfpga

@@ -0,0 +1,76 @@
+# Convert .pcf to a .place file that VPR can accept
+pcf2place --pcf ${OPENFPGA_PCF} --reduce_error_to_warning --blif ${VPR_TESTBENCH_BLIF} --pin_table ${OPENFPGA_PIN_TABLE} --fpga_io_map ${OPENFPGA_IO_MAP_FILE} --fpga_fix_pins ${OPENFPGA_VPR_FIX_PINS_FILE} --pin_table_direction_convention ${OPENFPGA_PIN_TABLE_DIRECTION_CONVENTION}
+
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --fix_clusters ${OPENFPGA_VPR_FIX_PINS_FILE}
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Read OpenFPGA simulation settings
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing #--verbose
+
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit 
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --explicit_port_mapping
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping 
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here
+write_pnr_sdc --file ./SDC
+
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file ./SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory

openfpga_flow/regression_test_scripts/basic_reg_test.sh

@@ -308,6 +308,7 @@ run-task basic_tests/bus_group/auto_gen_bus_group $@
 echo -e "Testing fix pins features";
 run-task basic_tests/io_constraints/fix_pins $@
 run-task basic_tests/io_constraints/example_pcf $@
+run-task basic_tests/io_constraints/pcf_reduce_error $@
 run-task basic_tests/io_constraints/empty_pcf $@
 run-task basic_tests/io_constraints/pcf_ql_style $@
 

openfpga_flow/tasks/basic_tests/io_constraints/pcf_reduce_error/config/and2.pcf

@@ -0,0 +1,4 @@
+set_io a pad_fpga_io[0]
+set_io b pad_fpga_io[4]
+set_io c pad_fpga_io[6]
+set_clk clk0 clk_in 

openfpga_flow/tasks/basic_tests/io_constraints/pcf_reduce_error/config/fpga_io_location.xml

@@ -0,0 +1,18 @@
+<io_coordinates>
+  <io pad="gfpga_pad_IO_A2F[0]" x="1" y="0" z="0"/>
+  <io pad="gfpga_pad_IO_F2A[0]" x="1" y="0" z="1"/>
+  <io pad="gfpga_pad_IO_A2F[1]" x="1" y="0" z="2"/>
+  <io pad="gfpga_pad_IO_F2A[1]" x="1" y="0" z="3"/>
+  <io pad="gfpga_pad_IO_A2F[2]" x="1" y="0" z="4"/>
+  <io pad="gfpga_pad_IO_F2A[2]" x="1" y="0" z="5"/>
+  <io pad="gfpga_pad_IO_A2F[3]" x="1" y="0" z="6"/>
+  <io pad="gfpga_pad_IO_F2A[3]" x="1" y="0" z="7"/>
+  <io pad="gfpga_pad_IO_A2F[4]" x="2" y="0" z="0"/>
+  <io pad="gfpga_pad_IO_F2A[4]" x="2" y="0" z="1"/>
+  <io pad="gfpga_pad_IO_A2F[5]" x="2" y="0" z="2"/>
+  <io pad="gfpga_pad_IO_F2A[5]" x="2" y="0" z="3"/>
+  <io pad="gfpga_pad_IO_A2F[6]" x="2" y="0" z="4"/>
+  <io pad="gfpga_pad_IO_F2A[6]" x="2" y="0" z="5"/>
+  <io pad="gfpga_pad_IO_A2F[7]" x="2" y="0" z="6"/>
+  <io pad="gfpga_pad_IO_F2A[7]" x="2" y="0" z="7"/>
+</io_coordinates>

openfpga_flow/tasks/basic_tests/io_constraints/pcf_reduce_error/config/pinmap_k4_N4_tileable_40nm.csv

@@ -0,0 +1,17 @@
+orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge
+TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],in,,
+TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],out,,
+TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],in,,
+TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],out,,
+TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],in,,
+TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],out,,
+TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],in,,
+TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],out,,
+RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],in,,
+RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],out,,
+RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],in,,
+RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],out,,
+BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],in,,
+BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],out,,
+LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],in,,
+LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],out,,

openfpga_flow/tasks/basic_tests/io_constraints/pcf_reduce_error/config/task.conf

@@ -0,0 +1,42 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/test_pcf.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
+openfpga_vpr_route_chan_width=20
+openfpga_pcf=${PATH:TASK_DIR}/config/and2.pcf
+openfpga_io_map_file=${PATH:TASK_DIR}/config/fpga_io_location.xml
+openfpga_pin_table=${PATH:TASK_DIR}/config/pinmap_k4_N4_tileable_40nm.csv
+openfpga_vpr_fix_pins_file=and2_fix_pins.place 
+openfpga_pin_table_direction_convention=explicit
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=