add option data structure for FPGA Verilog

openfpga/src/base/openfpga_verilog.cpp

@@ -22,17 +22,29 @@ void write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
 
   CommandOptionId opt_output_dir = cmd.option("file");
   CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
+  CommandOptionId opt_include_timing = cmd.option("include_timing");
+  CommandOptionId opt_include_signal_init = cmd.option("include_signal_init");
+  CommandOptionId opt_support_icarus_simulator = cmd.option("support_icarus_simulator");
   CommandOptionId opt_verbose = cmd.option("verbose");
+
+  /* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
+   * Keep it independent from any other outside data structures
+   */
+  FabricVerilogOption options;
+  options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
+  options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
+  options.set_include_timing(cmd_context.option_enable(cmd, opt_include_timing));
+  options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init));
+  options.set_support_icarus_simulator(cmd_context.option_enable(cmd, opt_support_icarus_simulator));
+  options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
+  options.set_compress_routing(openfpga_ctx.flow_manager().compress_routing());
   
   fpga_fabric_verilog(openfpga_ctx.module_graph(),
                       openfpga_ctx.arch().circuit_lib,
                       openfpga_ctx.mux_lib(),
                       g_vpr_ctx.device().grid,
                       openfpga_ctx.device_rr_gsb(),
-                      cmd_context.option_value(cmd, opt_output_dir),
+                      options);
-                      openfpga_ctx.flow_manager().compress_routing(),
-                      cmd_context.option_enable(cmd, opt_explicit_port_mapping),
-                      cmd_context.option_enable(cmd, opt_verbose));
 } 
 
 } /* end namespace openfpga */

openfpga/src/fpga_verilog/verilog_api.cpp

@@ -45,14 +45,11 @@ void fpga_fabric_verilog(const ModuleManager& module_manager,
                          const MuxLibrary& mux_lib,
                          const DeviceGrid& grids, 
                          const DeviceRRGSB& device_rr_gsb,
-                         const std::string& output_directory,
+                         const FabricVerilogOption& options) {
-                         const bool& compress_routing,
-                         const bool& dump_explict_verilog,
-                         const bool& verbose) {
 
   vtr::ScopedStartFinishTimer timer("Write Verilog netlists for FPGA fabric\n");
 
-  std::string src_dir_path = format_dir_path(output_directory);
+  std::string src_dir_path = format_dir_path(options.output_directory());
 
   /* Create directories */
   create_dir_path(src_dir_path.c_str());
@@ -110,7 +107,7 @@ void fpga_fabric_verilog(const ModuleManager& module_manager,
   //                         dump_explicit_verilog);
 
   /* Given a brief stats on how many Verilog modules have been written to files */
-  VTR_LOGV(verbose, 
+  VTR_LOGV(options.verbose_output(), 
            "Outputted %lu Verilog modules in total\n", 
            module_manager.num_modules());  
 }

openfpga/src/fpga_verilog/verilog_api.h

@@ -13,6 +13,7 @@
 #include "device_grid.h"
 #include "device_rr_gsb.h"
 #include "module_manager.h"
+#include "verilog_options.h"
 
 /********************************************************************
  * Function declaration
@@ -26,10 +27,7 @@ void fpga_fabric_verilog(const ModuleManager& module_manager,
                          const MuxLibrary& mux_lib,
                          const DeviceGrid& grids, 
                          const DeviceRRGSB& device_rr_gsb,
-                         const std::string& output_directory,
+                         const FabricVerilogOption& options);
-                         const bool& compress_routing,
-                         const bool& dump_explict_verilog,
-                         const bool& verbose);
 
 } /* end namespace openfpga */
 

openfpga/src/fpga_verilog/verilog_options.cpp

@@ -0,0 +1,73 @@
+/******************************************************************************
+ * Memember functions for data structure FabricVerilogOption
+ ******************************************************************************/
+#include "vtr_assert.h"
+
+#include "verilog_options.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/**************************************************
+ * Public Accessors 
+ *************************************************/
+std::string FabricVerilogOption::output_directory() const {
+  return output_directory_;
+}
+
+bool FabricVerilogOption::support_icarus_simulator() const {
+  return support_icarus_simulator_;
+}
+
+bool FabricVerilogOption::include_timing() const {
+  return include_timing_;
+}
+
+bool FabricVerilogOption::include_signal_init() const {
+  return include_signal_init_;
+}
+
+bool FabricVerilogOption::explicit_port_mapping() const {
+  return explicit_port_mapping_;
+}
+
+bool FabricVerilogOption::compress_routing() const {
+  return compress_routing_;
+}
+
+bool FabricVerilogOption::verbose_output() const {
+  return verbose_output_;
+}
+
+/******************************************************************************
+ * Private Mutators
+ ******************************************************************************/
+void FabricVerilogOption::set_output_directory(const std::string& output_dir) {
+  output_directory_ = output_dir;
+}
+
+void FabricVerilogOption::set_support_icarus_simulator(const bool& enabled) {
+  support_icarus_simulator_ = enabled;
+}
+
+void FabricVerilogOption::set_include_timing(const bool& enabled) {
+  include_timing_ = enabled;
+}
+
+void FabricVerilogOption::set_include_signal_init(const bool& enabled) {
+  include_signal_init_ = enabled;
+}
+
+void FabricVerilogOption::set_explicit_port_mapping(const bool& enabled) {
+  explicit_port_mapping_ = enabled;
+}
+
+void FabricVerilogOption::set_compress_routing(const bool& enabled) {
+  compress_routing_ = enabled;
+}
+
+void FabricVerilogOption::set_verbose_output(const bool& enabled) {
+  verbose_output_ = enabled;
+}
+
+} /* end namespace openfpga */

openfpga/src/fpga_verilog/verilog_options.h

@@ -0,0 +1,48 @@
+#ifndef VERILOG_OPTIONS_H
+#define VERILOG_OPTIONS_H
+
+/********************************************************************
+ * Include header files required by the data structure definition
+ *******************************************************************/
+#include <string>
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * FlowManager aims to resolve the dependency between OpenFPGA functional
+ * code blocks
+ * It can provide flags for downstream modules about if the data structures
+ * they require have already been constructed
+ *
+ *******************************************************************/
+class FabricVerilogOption {
+  public: /* Public accessors */
+    std::string output_directory() const;
+    bool support_icarus_simulator() const;
+    bool include_timing() const;
+    bool include_signal_init() const;
+    bool explicit_port_mapping() const;
+    bool compress_routing() const;
+    bool verbose_output() const;
+  public: /* Public mutators */
+    void set_output_directory(const std::string& output_dir);
+    void set_support_icarus_simulator(const bool& enabled);
+    void set_include_timing(const bool& enabled);
+    void set_include_signal_init(const bool& enabled);
+    void set_explicit_port_mapping(const bool& enabled);
+    void set_compress_routing(const bool& enabled);
+    void set_verbose_output(const bool& enabled);
+  private: /* Internal Data */
+    std::string output_directory_;
+    bool support_icarus_simulator_;
+    bool include_signal_init_;
+    bool include_timing_;
+    bool explicit_port_mapping_;
+    bool compress_routing_;
+    bool verbose_output_;
+};
+
+} /* End namespace openfpga*/
+
+#endif