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[core] fixed a bug

This commit is contained in:
tangxifan 2023-08-05 22:06:17 -07:00
parent a1f8b3c441
commit beee2369c9
1 changed files with 3 additions and 3 deletions
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6
openfpga/src/fpga_verilog/verilog_memory.cpp
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@ -211,9 +211,9 @@ void print_verilog_submodule_memories(const ModuleManager& module_manager,
fp << std::endl;
/* Create the module name for the memory block */
std::string feedthru_module_name = generate_memory_module_name(
circuit_lib, model, sram_models[0],
std::string(MEMORY_FEEDTHROUGH_MODULE_POSTFIX));
std::string feedthru_module_name =
generate_memory_module_name(circuit_lib, model, sram_models[0],
std::string(MEMORY_MODULE_POSTFIX), true);
ModuleId feedthru_mem_module =
module_manager.find_module(feedthru_module_name);