From bee070d7cc034d68ac4ea110d1ffd398eac7f2c3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 19 Aug 2019 12:22:51 -0600 Subject: [PATCH] start plug in MUX library --- vpr7_x2p/vpr/SRC/device/mux_graph.cpp | 29 ++++++++++++---- vpr7_x2p/vpr/SRC/device/mux_utils.cpp | 34 +++++++++++++++++++ vpr7_x2p/vpr/SRC/device/mux_utils.h | 4 +++ .../SRC/fpga_x2p/verilog/verilog_submodules.c | 5 +++ 4 files changed, 65 insertions(+), 7 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp index 69e2da14e..eb978750c 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp @@ -186,12 +186,14 @@ MuxEdgeId MuxGraph::add_edge(const MuxNodeId& from_node, const MuxNodeId& to_nod /* update the edge-node connections */ VTR_ASSERT(valid_node_id(from_node)); + edge_src_nodes_.emplace_back(); edge_src_nodes_[edge].push_back(from_node); node_out_edges_[from_node].push_back(edge); VTR_ASSERT(valid_node_id(to_node)); - node_in_edges_[to_node].push_back(edge); + edge_sink_nodes_.emplace_back(); edge_sink_nodes_[edge].push_back(to_node); + node_in_edges_[to_node].push_back(edge); return edge; } @@ -265,8 +267,17 @@ void MuxGraph::set_edge_mem_id(const MuxEdgeId& edge, const MuxMemId& mem) { void MuxGraph::build_multilevel_mux_graph(const size_t& mux_size, const size_t& num_levels, const size_t& num_inputs_per_branch, const enum e_spice_model_pass_gate_logic_type& pgl_type) { + /* Make sure mux_size for each branch is valid */ + VTR_ASSERT(valid_mux_implementation_num_inputs(num_inputs_per_branch)); + + /* In regular cases, there is 1 mem bit for each input of a branch */ + size_t num_mems_per_level = num_inputs_per_branch; + /* For 2-input branch, only 1 mem bit is needed for each level! */ + if (2 == num_inputs_per_branch) { + num_mems_per_level = 1; + } /* Number of memory bits is definite, add them */ - for (size_t i = 0; i < num_inputs_per_branch * num_levels; ++i) { + for (size_t i = 0; i < num_mems_per_level * num_levels; ++i) { add_mem(); } @@ -317,14 +328,14 @@ void MuxGraph::build_multilevel_mux_graph(const size_t& mux_size, */ if ( 2 == num_inputs_per_branch) { - MuxMemId mem_id = MuxMemId( (lvl - 1) ); + MuxMemId mem_id = MuxMemId(lvl); set_edge_mem_id(edge, mem_id); /* If this is a second edge in the branch, we will assign it to an inverted edge */ if (0 != i % num_inputs_per_branch) { edge_inv_mem_[edge] = true; } } else { - MuxMemId mem_id = MuxMemId( (lvl - 1) * num_inputs_per_branch + i ); + MuxMemId mem_id = MuxMemId( lvl * num_inputs_per_branch + i ); set_edge_mem_id(edge, mem_id); } @@ -387,6 +398,9 @@ void MuxGraph::build_multilevel_mux_graph(const size_t& mux_size, */ void MuxGraph::build_onelevel_mux_graph(const size_t& mux_size, const enum e_spice_model_pass_gate_logic_type& pgl_type) { + /* Make sure mux_size is valid */ + VTR_ASSERT(valid_mux_implementation_num_inputs(mux_size)); + /* We definitely know how many nodes we need, * N inputs, 1 output and 0 internal nodes */ @@ -419,7 +433,8 @@ void MuxGraph::build_mux_graph(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size) { /* Make sure this model is a MUX */ - VTR_ASSERT(SPICE_MODEL_MUX == circuit_lib.circuit_model_type(circuit_model)); + VTR_ASSERT((SPICE_MODEL_MUX == circuit_lib.circuit_model_type(circuit_model)) + || (SPICE_MODEL_LUT == circuit_lib.circuit_model_type(circuit_model)) ); /* Make sure mux_size is valid */ VTR_ASSERT(valid_mux_implementation_num_inputs(mux_size)); @@ -433,7 +448,7 @@ void MuxGraph::build_mux_graph(const CircuitLibrary& circuit_lib, switch (impl_structure) { case SPICE_MODEL_STRUCTURE_TREE: { /* Find the number of levels */ - size_t num_levels = find_treelike_mux_num_levels(mux_size); + size_t num_levels = find_treelike_mux_num_levels(impl_mux_size); /* Find the number of inputs per branch, this is not final */ size_t num_inputs_per_branch = 2; @@ -448,7 +463,7 @@ void MuxGraph::build_mux_graph(const CircuitLibrary& circuit_lib, } case SPICE_MODEL_STRUCTURE_MULTILEVEL: { /* Find the number of inputs per branch, this is not final */ - size_t num_inputs_per_branch = find_multilevel_mux_branch_num_inputs(mux_size, circuit_lib.mux_num_levels(circuit_model)); + size_t num_inputs_per_branch = find_multilevel_mux_branch_num_inputs(impl_mux_size, circuit_lib.mux_num_levels(circuit_model)); /* Build a multilevel mux graph */ build_multilevel_mux_graph(impl_mux_size, circuit_lib.mux_num_levels(circuit_model), diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp index 555304647..cc5b04ec8 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp @@ -4,6 +4,7 @@ *************************************************/ #include +#include "spice_types.h" #include "util.h" #include "vtr_assert.h" #include "mux_utils.h" @@ -123,3 +124,36 @@ size_t find_multilevel_mux_branch_num_inputs(const size_t& mux_size, return num_input_per_unit; } +/************************************************** + * Convert a linked list of MUX architecture to MuxLibrary + * TODO: this function will be deleted when MUXLibrary fully + * replace legacy data structures + *************************************************/ +MuxLibrary convert_mux_arch_to_library(const CircuitLibrary& circuit_lib, t_llist* muxes_head) { + t_llist* temp = muxes_head; + MuxLibrary mux_lib; + + /* Walk through the linked list */ + while(temp) { + VTR_ASSERT_SAFE(NULL != temp->dptr); + t_spice_mux_model* cur_spice_mux_model = (t_spice_mux_model*)(temp->dptr); + + /* Bypass the spice models who has a user-defined subckt */ + if (NULL != cur_spice_mux_model->spice_model->verilog_netlist) { + /* Move on to the next*/ + temp = temp->next; + continue; + } + + /* Build a MUX graph for the model */ + /* Find the circuit model id by the name */ + CircuitModelId circuit_model = circuit_lib.circuit_model(cur_spice_mux_model->spice_model->name); + mux_lib.add_mux(circuit_lib, circuit_model, cur_spice_mux_model->size); + + /* Move on to the next*/ + temp = temp->next; + } + + return mux_lib; +} + diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.h b/vpr7_x2p/vpr/SRC/device/mux_utils.h index 9e21305d8..730109957 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.h +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.h @@ -6,7 +6,9 @@ #ifndef MUX_UTILS_H #define MUX_UTILS_H +#include "linkedlist.h" #include "circuit_library.h" +#include "mux_library.h" bool valid_mux_implementation_num_inputs(const size_t& mux_size); @@ -24,4 +26,6 @@ size_t find_treelike_mux_num_levels(const size_t& mux_size); size_t find_multilevel_mux_branch_num_inputs(const size_t& mux_size, const size_t& mux_level); +MuxLibrary convert_mux_arch_to_library(const CircuitLibrary& circuit_lib, t_llist* muxes_head); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index d3661126b..d9183c91e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -38,6 +38,8 @@ #include "verilog_submodules.h" +#include "mux_utils.h" + /***** Subroutines *****/ static @@ -2762,6 +2764,9 @@ void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info, /* Alloc the muxes*/ muxes_head = stats_spice_muxes(num_switch, switches, spice, routing_arch); + + /* TODO: this is temporary. Will be removed after code reconstruction */ + MuxLibrary mux_lib = convert_mux_arch_to_library(spice->circuit_lib, muxes_head); /* Print the muxes netlist*/ fp = fopen(verilog_name, "w");