diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 2e8a8246c..8b04312d5 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -1,13 +1,19 @@ name: Test # Run CI on push, PR, and weekly. - on: - push: + workflow_dispatch: pull_request: + push: + branches: + - 'master' schedule: - cron: "0 0 * * 0 " # weekly +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: true + # Environment variables env: # Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.) @@ -22,7 +28,7 @@ env: jobs: change_detect: name: "Detect code changes" - runs-on: ubuntu-20.04 + runs-on: ubuntu-22.04 outputs: # this is output as string, see https://docs.github.com/en/actions/reference/workflow-syntax-for-github-actions#jobsjob_idoutputs source_modified: ${{ steps.changes.outputs.status_code == '1' }} @@ -36,7 +42,7 @@ jobs: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v3 + uses: actions/checkout@v4 with: fetch-depth: 0 @@ -67,7 +73,7 @@ jobs: needs: change_detect if: ${{ fromJSON(needs.change_detect.outputs.source_modified) }} name: ${{ matrix.config.name }} - runs-on: ubuntu-20.04 + runs-on: ubuntu-22.04 # Note: dependencies are installed in the container. See details about dependency list in docker/Dockerfile.master # Comment the line out when base image is built again #container: ghcr.io/${{ needs.change_detect.outputs.docker_repo }}/openfpga-build-${{ matrix.config.cc}} @@ -76,30 +82,38 @@ jobs: fail-fast: false matrix: config: - - name: "Build Compatibility: GCC-8 (Ubuntu 20.04)" - cc: gcc-8 - cxx: g++-8 - - name: "Build Compatibility: GCC-9 (Ubuntu 20.04)" + - name: "Build Compatibility: GCC-9 (Ubuntu 22.04)" cc: gcc-9 cxx: g++-9 - - name: "Build Compatibility: GCC-10 (Ubuntu 20.04)" + dependency_version: "ubuntu22p04" + - name: "Build Compatibility: GCC-10 (Ubuntu 22.04)" cc: gcc-10 cxx: g++-10 - - name: "Build Compatibility: GCC-11 (Ubuntu 20.04)" + dependency_version: "ubuntu22p04" + - name: "Build Compatibility: GCC-11 (Ubuntu 22.04)" cc: gcc-11 cxx: g++-11 - - name: "Build Compatibility: Clang-6 (Ubuntu 20.04)" - cc: clang-6.0 - cxx: clang++-6.0 - - name: "Build Compatibility: Clang-7 (Ubuntu 20.04)" - cc: clang-7 - cxx: clang++-7 - - name: "Build Compatibility: Clang-8 (Ubuntu 20.04)" - cc: clang-8 - cxx: clang++-8 - - name: "Build Compatibility: Clang-10 (Ubuntu 20.04)" - cc: clang-10 - cxx: clang++-10 + dependency_version: "ubuntu22p04" + - name: "Build Compatibility: GCC-12 (Ubuntu 22.04)" + cc: gcc-12 + cxx: g++-12 + dependency_version: "ubuntu22p04" + - name: "Build Compatibility: Clang-11 (Ubuntu 22.04)" + cc: clang-11 + cxx: clang++-11 + dependency_version: "ubuntu22p04" + - name: "Build Compatibility: Clang-12 (Ubuntu 22.04)" + cc: clang-12 + cxx: clang++-12 + dependency_version: "ubuntu22p04" + - name: "Build Compatibility: Clang-13 (Ubuntu 22.04)" + cc: clang-13 + cxx: clang++-13 + dependency_version: "ubuntu22p04" + - name: "Build Compatibility: Clang-14 (Ubuntu 22.04)" + cc: clang-14 + cxx: clang++-14 + dependency_version: "ubuntu22p04" # Define the steps to run the build job env: CC: ${{ matrix.config.cc }} @@ -111,10 +125,10 @@ jobs: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v3 + uses: actions/checkout@v4 - name: Install dependencies - run: sudo bash ./.github/workflows/install_dependencies_build.sh + run: sudo bash ./.github/workflows/install_dependencies_build_${{ matrix.config.dependency_version }}.sh - name: Dump tool versions run: | @@ -129,12 +143,18 @@ jobs: run: | make all BUILD_TYPE=$BUILD_TYPE + - name: Clear error log + if: ${{ failure() }} + shell: bash + run: | + make all BUILD_TYPE=$BUILD_TYPE -j1 + # Check the cache size and see if it is over the limit - name: Check ccache size run: ccache -s - name: Upload artifact uses: actions/upload-artifact@v2 - if: ${{ matrix.config.cc == 'gcc-9'}} + if: ${{ matrix.config.cc == 'gcc-11'}} with: name: openfpga path: | @@ -151,11 +171,12 @@ jobs: openfpga_flow openfpga.sh + linux_build_opt: needs: change_detect if: ${{ fromJSON(needs.change_detect.outputs.source_modified) }} name: ${{ matrix.config.name }} - runs-on: ubuntu-20.04 + runs-on: ubuntu-22.04 # Note: dependencies are installed in the container. See details about dependency list in docker/Dockerfile.master # Comment the line out when base image is built again #container: ghcr.io/${{ needs.change_detect.outputs.docker_repo }}/openfpga-build-${{ matrix.config.cc}} @@ -164,26 +185,31 @@ jobs: fail-fast: false matrix: config: - - name: "Build w/o Yosys (Ubuntu 20.04)" - cc: gcc-9 - cxx: g++-9 + - name: "Build w/o Yosys (Ubuntu 22.04)" + cc: gcc-11 + cxx: g++-11 cmake_flags: "-DOPENFPGA_WITH_YOSYS=OFF" - - name: "Build w/o Yosys plugin (Ubuntu 20.04)" - cc: gcc-9 - cxx: g++-9 + dependency_version: "ubuntu22p04" + - name: "Build w/o Yosys plugin (Ubuntu 22.04)" + cc: gcc-11 + cxx: g++-11 cmake_flags: "-DOPENFPGA_WITH_YOSYS_PLUGIN=OFF" - - name: "Build w/o test (Ubuntu 20.04)" - cc: gcc-9 - cxx: g++-9 + dependency_version: "ubuntu22p04" + - name: "Build w/o test (Ubuntu 22.04)" + cc: gcc-11 + cxx: g++-11 cmake_flags: "-DOPENFPGA_WITH_TEST=OFF" - - name: "Build w/o version number (Ubuntu 20.04)" - cc: gcc-9 - cxx: g++-9 + dependency_version: "ubuntu22p04" + - name: "Build w/o version number (Ubuntu 22.04)" + cc: gcc-11 + cxx: g++-11 cmake_flags: "-DOPENFPGA_WITH_VERSION=OFF" - - name: "Build w/o SWIG support (Ubuntu 20.04)" - cc: gcc-9 - cxx: g++-9 + dependency_version: "ubuntu22p04" + - name: "Build w/o SWIG support (Ubuntu 22.04)" + cc: gcc-11 + cxx: g++-11 cmake_flags: "-DOPENFPGA_WITH_SWIG=OFF" + dependency_version: "ubuntu22p04" # Define the steps to run the build job env: CC: ${{ matrix.config.cc }} @@ -195,10 +221,10 @@ jobs: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v3 + uses: actions/checkout@v4 - name: Install dependencies - run: sudo bash ./.github/workflows/install_dependencies_build.sh + run: sudo bash ./.github/workflows/install_dependencies_build_${{ matrix.config.dependency_version }}.sh - name: Dump tool versions run: | @@ -217,14 +243,19 @@ jobs: needs: change_detect if: ${{ fromJSON(needs.change_detect.outputs.source_modified) }} name: ${{ matrix.config.name }} - runs-on: ubuntu-22.04 + runs-on: ubuntu-20.04 strategy: fail-fast: false matrix: config: - - name: "Build (Ubuntu 22.04)" + - name: "Build (GCC-11 on Ubuntu 20.04)" cc: gcc-11 cxx: g++-11 + dependency_version: "ubuntu20p04" + - name: "Build (Clang-10 on Ubuntu 20.04)" + cc: clang-10 + cxx: clang++-10 + dependency_version: "ubuntu20p04" # Define the steps to run the build job env: CC: ${{ matrix.config.cc }} @@ -236,10 +267,10 @@ jobs: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v3 + uses: actions/checkout@v4 - name: Install dependencies - run: sudo bash ./.github/workflows/install_dependencies_build_ubuntu22p04.sh + run: sudo bash ./.github/workflows/install_dependencies_build_${{ matrix.config.dependency_version }}.sh - name: Dump tool versions run: | @@ -270,6 +301,7 @@ jobs: cxx: g++-11 build_type: debug cores: 4 + dependency_version: "ubuntu22p04" # Define the steps to run the build job env: CC: ${{ matrix.config.cc }} @@ -281,12 +313,12 @@ jobs: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v3 + uses: actions/checkout@v4 - name: Install dependencies run: | - sudo bash ./.github/workflows/install_dependencies_build_ubuntu22p04.sh - sudo bash ./.github/workflows/install_dependencies_run_ubuntu22p04.sh + sudo bash ./.github/workflows/install_dependencies_build_${{ matrix.config.dependency_version }}.sh + sudo bash ./.github/workflows/install_dependencies_run_${{ matrix.config.dependency_version }}.sh sudo python3 -m pip install -r requirements.txt - name: Dump tool versions @@ -321,6 +353,7 @@ jobs: cxx: g++-11 build_type: release cores: 4 + dependency_version: "ubuntu22p04" # Define the steps to run the build job env: CC: ${{ matrix.config.cc }} @@ -332,12 +365,12 @@ jobs: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v3 + uses: actions/checkout@v4 - name: Install dependencies run: | - sudo bash ./.github/workflows/install_dependencies_build_ubuntu22p04.sh - sudo bash ./.github/workflows/install_dependencies_run_ubuntu22p04.sh + sudo bash ./.github/workflows/install_dependencies_build_${{ matrix.config.dependency_version }}.sh + sudo bash ./.github/workflows/install_dependencies_run_${{ matrix.config.dependency_version }}.sh sudo python3 -m pip install -r requirements.txt - name: Dump tool versions @@ -360,7 +393,7 @@ jobs: docker_distribution: name: Build docker image for distribution - runs-on: ubuntu-20.04 + runs-on: ubuntu-22.04 needs: [linux_build, change_detect] steps: - name: Cancel previous @@ -369,7 +402,7 @@ jobs: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v3 + uses: actions/checkout@v4 - name: Download a built artifacts uses: actions/download-artifact@v2 with: @@ -397,7 +430,7 @@ jobs: linux_regression_tests: name: linux_regression_tests - runs-on: ubuntu-20.04 + runs-on: ubuntu-22.04 needs: [linux_build, change_detect] container: ghcr.io/${{ needs.change_detect.outputs.docker_repo }}/openfpga-env strategy: @@ -422,7 +455,7 @@ jobs: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v3 + uses: actions/checkout@v4 - name: Download a built artifacts uses: actions/download-artifact@v2 with: @@ -438,7 +471,7 @@ jobs: chmod +x build/yosys/bin/yosys-config chmod +x build/yosys/bin/yosys-filterlib chmod +x build/yosys/bin/yosys-smtbmc - - name: ${{matrix.config.name}}_GCC-9_(Ubuntu 20.04) + - name: ${{matrix.config.name}}_GCC-11_(Ubuntu 22.04) shell: bash run: source openfpga.sh && source openfpga_flow/regression_test_scripts/${{matrix.config.name}}.sh --debug --show_thread_logs - name: Upload artifact @@ -454,7 +487,7 @@ jobs: needs: change_detect if: ${{ !fromJSON(needs.change_detect.outputs.source_modified) }} name: docker_regression_tests - runs-on: ubuntu-20.04 + runs-on: ubuntu-22.04 container: image: ghcr.io/${{ needs.change_detect.outputs.docker_repo }}/openfpga-master:latest options: --user root --workdir /home/openfpga_user @@ -480,12 +513,12 @@ jobs: access_token: ${{ github.token }} - name: Checkout OpenFPGA repo - uses: actions/checkout@v3 + uses: actions/checkout@v4 - - name: ${{matrix.config.name}}_GCC-9_(Ubuntu 20.04) + - name: ${{matrix.config.name}}_GCC-11_(Ubuntu 22.04) shell: bash run: | - bash .github/workflows/install_dependencies_run.sh + bash .github/workflows/install_dependencies_run_ubuntu22p04.sh ${PYTHON_EXEC} -m pip install -r requirements.txt rsync -am --exclude='openfpga_flow/**' /opt/openfpga/. . unset OPENFPGA_PATH diff --git a/.github/workflows/cell_lib_test.yml b/.github/workflows/cell_lib_test.yml index 7d5b08984..5d590dc90 100644 --- a/.github/workflows/cell_lib_test.yml +++ b/.github/workflows/cell_lib_test.yml @@ -1,13 +1,19 @@ name: Cell Library Tests # Run CI on push, PR, and weekly. - on: - push: + workflow_dispatch: pull_request: + push: + branches: + - 'master' schedule: - cron: "0 0 * * 0 " # weekly +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: true + # Multiple job to tests jobs: # Test the RTL compilation compatibility diff --git a/.github/workflows/docker.yml b/.github/workflows/docker.yml index f29dbd883..ef77be6ed 100644 --- a/.github/workflows/docker.yml +++ b/.github/workflows/docker.yml @@ -7,10 +7,14 @@ env: DOCKER_REPO: ${{ secrets.DOCKER_REPO }} REPO_OWNER: ${{ github.repository_owner }} +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: true + jobs: change_detect: name: "Detect code changes" - runs-on: ubuntu-20.04 + runs-on: ubuntu-22.04 outputs: docker_repo: ${{ steps.changes.outputs.docker_repo }} steps: @@ -31,7 +35,7 @@ jobs: runs-on: ubuntu-latest steps: - name: Checkout - uses: actions/checkout@v2 + uses: actions/checkout@v4 - name: Set up QEMU uses: docker/setup-qemu-action@v1 - name: Set up Docker Buildx @@ -64,18 +68,17 @@ jobs: strategy: matrix: compiler: - - gcc-7 - - gcc-8 - gcc-9 - gcc-10 - gcc-11 - - clang-6.0 - - clang-7 - - clang-8 - - clang-10 + - gcc-12 + - clang-11 + - clang-12 + - clang-13 + - clang-14 steps: - name: Checkout - uses: actions/checkout@v2 + uses: actions/checkout@v4 - name: Set up QEMU uses: docker/setup-qemu-action@v1 - name: Set up Docker Buildx diff --git a/.github/workflows/format.yaml b/.github/workflows/format.yaml index fd1365272..2631f135b 100644 --- a/.github/workflows/format.yaml +++ b/.github/workflows/format.yaml @@ -3,26 +3,36 @@ name: Code Format # Run CI on push, PR, and weekly. on: - push: + workflow_dispatch: pull_request: + push: + branches: + - 'master' schedule: - cron: "0 0 * * 0 " # weekly +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: true + # Multiple job to tests jobs: change_detect: name: "Check" - runs-on: ubuntu-20.04 + runs-on: ubuntu-22.04 strategy: fail-fast: false matrix: config: - name: "C/C++" code_type: "-cpp" + dependency_version: "ubuntu22p04" - name: "XML" code_type: "-xml" + dependency_version: "ubuntu22p04" - name: "Python" code_type: "-py" + dependency_version: "ubuntu22p04" steps: - name: Cancel previous uses: styfle/cancel-workflow-action@0.9.1 @@ -34,12 +44,12 @@ jobs: - name: Install dependencies run: | - sudo bash ./.github/workflows/install_dependencies_build.sh + sudo bash ./.github/workflows/install_dependencies_build_${{ matrix.config.dependency_version }}.sh sudo python3 -m pip install -r requirements.txt - name: Dump tool versions run: | - clang-format-10 --version + clang-format-14 --version black --version - name: Check format diff --git a/.github/workflows/install_dependencies_build.sh b/.github/workflows/install_dependencies_build_ubuntu20p04.sh similarity index 100% rename from .github/workflows/install_dependencies_build.sh rename to .github/workflows/install_dependencies_build_ubuntu20p04.sh diff --git a/.github/workflows/install_dependencies_build_ubuntu22p04.sh b/.github/workflows/install_dependencies_build_ubuntu22p04.sh index e49f0b9d4..19d806add 100755 --- a/.github/workflows/install_dependencies_build_ubuntu22p04.sh +++ b/.github/workflows/install_dependencies_build_ubuntu22p04.sh @@ -53,6 +53,9 @@ apt-get install -y \ gcc-10 \ g++-11 \ gcc-11 \ + clang-11 \ clang-12 \ - clang-format-12 \ + clang-13 \ + clang-14 \ + clang-format-14 \ libxml2-utils diff --git a/.github/workflows/install_dependencies_run.sh b/.github/workflows/install_dependencies_run_ubuntu20p04.sh similarity index 100% rename from .github/workflows/install_dependencies_run.sh rename to .github/workflows/install_dependencies_run_ubuntu20p04.sh diff --git a/.github/workflows/patch_updater.yml b/.github/workflows/patch_updater.yml index 7a579acf9..38c406e98 100644 --- a/.github/workflows/patch_updater.yml +++ b/.github/workflows/patch_updater.yml @@ -1,8 +1,9 @@ name: Count Patches on: workflow_dispatch: - schedule: - - cron: '0 0 * * *' + push: + branches: + - 'master' env: TAG_COMMIT: 8ee3fb8.. @@ -41,6 +42,7 @@ jobs: with: github_token: ${{ secrets.GITHUB_TOKEN }} branch: ${{env.BRANCH_NAME}} + force: true - name: Create Auto PR if: "!contains(steps.log.outputs.message, 'Updated Patch Count') && contains(steps.repo.outputs.message, 'lnis-uofu/OpenFPGA')" diff --git a/Makefile b/Makefile index 23c2cdab6..9f39d6c22 100644 --- a/Makefile +++ b/Makefile @@ -42,7 +42,7 @@ endif # Define executables PYTHON_EXEC ?= python3 -CLANG_FORMAT_EXEC ?= clang-format-10 +CLANG_FORMAT_EXEC ?= clang-format-14 XML_FORMAT_EXEC ?= xmllint PYTHON_FORMAT_EXEC ?= black diff --git a/README.md b/README.md index 0b4bb8fd6..a66ddc216 100644 --- a/README.md +++ b/README.md @@ -11,16 +11,19 @@ Version: see [`VERSION.md`](VERSION.md) The award-winning OpenFPGA framework is the **first open-source FPGA IP generator with silicon proofs** supporting highly-customizable FPGA architectures. OpenFPGA provides complete EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers. -**If this is your first time working with OpenFPGA, we strongly **recommend you watch the** [introduction video about OpenFPGA](https://youtu.be/ocODUGcYGqo)** +> [!TIP] +> If this is your first time working with OpenFPGA, we strongly recommend you watch the [introduction video about OpenFPGA](https://youtu.be/ocODUGcYGqo) A quick overview of OpenFPGA tools can be found [**here**](https://openfpga.readthedocs.io/en/master/tutorials/getting_started/tools/). We also recommend potential users check out the summary of [**technical capabilities**](https://openfpga.readthedocs.io/en/master/overview/tech_highlights/#) before compiling. -**Before asking for help, please checkout the** [Frequently Asked Questions](https://github.com/lnis-uofu/OpenFPGA/discussions/937) +> [!TIP] +> Before asking for help, please checkout the [Frequently Asked Questions](https://github.com/lnis-uofu/OpenFPGA/discussions/937) ## Compilation -**A tutorial **video about **how to compile** can be** found [here](https://youtu.be/F9sMRmDewM0)** +> [!NOTE] +> A tutorial video about how to compile can be found [here](https://youtu.be/F9sMRmDewM0) Detailed guidelines are available at [**compilation guidelines**](https://openfpga.readthedocs.io/en/master/tutorials/getting_started/compile/). Before starting, we strongly recommend you read the required dependencies and ensure that they are correctly installed. @@ -36,7 +39,7 @@ You can find a set of [tutorials](https://openfpga.readthedocs.io/en/master/tuto ## Backward Compatibility -If you were using an old version of OpenFPGA and are now interested to move to the latest version, please check out the [developer guidelines](https://openfpga.readthedocs.io/en/master/dev_manual/back_compatibile). +If you were using an old version of OpenFPGA and are now interested to move to the latest version, please check out the [developer guidelines](https://openfpga.readthedocs.io/en/master/dev_manual/back_compatible/). ## License @@ -54,8 +57,8 @@ Bibtex: @ARTICLE{9098028, author={Tang, Xifan and Giacomin, Edouard and Chauviere, Baudouin and Alacchi, Aurélien and Gaillardon, Pierre-Emmanuel}, journal={IEEE Micro}, title={OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs}, year={2020}, volume={40}, number={4}, pages={41-48}, doi={10.1109/MM.2020.2995854}} ``` -A list of related publications can be found [here](https://openfpga.readthedocs.io/en/master/reference/). +A list of related publications can be found [here](https://openfpga.readthedocs.io/en/master/appendix/reference/). ## Contributing to OpenFPGA -Please read the [contributor guidelines](https://openfpga.readthedocs.io/en/master/dev_manual/contributor_guide) if you would like to contribute to OpenFPGA. +Please read the [contributor guidelines](https://openfpga.readthedocs.io/en/master/dev_manual/contributor_guide/) if you would like to contribute to OpenFPGA. diff --git a/VERSION.md b/VERSION.md index d97109f27..9c34ef6a6 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.1961 +1.2.2258 diff --git a/cmake/modules/FindTBB.cmake b/cmake/modules/FindTBB.cmake deleted file mode 100644 index 0a1a5bb77..000000000 --- a/cmake/modules/FindTBB.cmake +++ /dev/null @@ -1,303 +0,0 @@ -# The MIT License (MIT) -# -# Copyright (c) 2015 Justus Calvin -# -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), to deal -# in the Software without restriction, including without limitation the rights -# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -# copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in all -# copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -# SOFTWARE. - -# -# FindTBB -# ------- -# -# Find TBB include directories and libraries. -# -# Usage: -# -# find_package(TBB [major[.minor]] [EXACT] -# [QUIET] [REQUIRED] -# [[COMPONENTS] [components...]] -# [OPTIONAL_COMPONENTS components...]) -# -# where the allowed components are tbbmalloc and tbb_preview. Users may modify -# the behavior of this module with the following variables: -# -# * TBB_ROOT_DIR - The base directory the of TBB installation. -# * TBB_INCLUDE_DIR - The directory that contains the TBB headers files. -# * TBB_LIBRARY - The directory that contains the TBB library files. -# * TBB__LIBRARY - The path of the TBB the corresponding TBB library. -# These libraries, if specified, override the -# corresponding library search results, where -# may be tbb, tbb_debug, tbbmalloc, tbbmalloc_debug, -# tbb_preview, or tbb_preview_debug. -# * TBB_USE_DEBUG_BUILD - The debug version of tbb libraries, if present, will -# be used instead of the release version. -# -# Users may modify the behavior of this module with the following environment -# variables: -# -# * TBB_INSTALL_DIR -# * TBBROOT -# * LIBRARY_PATH -# -# This module will set the following variables: -# -# * TBB_FOUND - Set to false, or undefined, if we haven’t found, or -# don’t want to use TBB. -# * TBB__FOUND - If False, optional part of TBB sytem is -# not available. -# * TBB_VERSION - The full version string -# * TBB_VERSION_MAJOR - The major version -# * TBB_VERSION_MINOR - The minor version -# * TBB_INTERFACE_VERSION - The interface version number defined in -# tbb/tbb_stddef.h. -# * TBB__LIBRARY_RELEASE - The path of the TBB release version of -# , where may be tbb, tbb_debug, -# tbbmalloc, tbbmalloc_debug, tbb_preview, or -# tbb_preview_debug. -# * TBB__LIBRARY_DEGUG - The path of the TBB release version of -# , where may be tbb, tbb_debug, -# tbbmalloc, tbbmalloc_debug, tbb_preview, or -# tbb_preview_debug. -# -# The following varibles should be used to build and link with TBB: -# -# * TBB_INCLUDE_DIRS - The include directory for TBB. -# * TBB_LIBRARIES - The libraries to link against to use TBB. -# * TBB_LIBRARIES_RELEASE - The release libraries to link against to use TBB. -# * TBB_LIBRARIES_DEBUG - The debug libraries to link against to use TBB. -# * TBB_DEFINITIONS - Definitions to use when compiling code that uses -# TBB. -# * TBB_DEFINITIONS_RELEASE - Definitions to use when compiling release code that -# uses TBB. -# * TBB_DEFINITIONS_DEBUG - Definitions to use when compiling debug code that -# uses TBB. -# -# This module will also create the "tbb" target that may be used when building -# executables and libraries. - -include(FindPackageHandleStandardArgs) - -if(NOT TBB_FOUND) - - ################################## - # Check the build type - ################################## - - if(NOT DEFINED TBB_USE_DEBUG_BUILD) - if(CMAKE_BUILD_TYPE MATCHES "(Debug|DEBUG|debug|RelWithDebInfo|RELWITHDEBINFO|relwithdebinfo)") - set(TBB_BUILD_TYPE DEBUG) - else() - set(TBB_BUILD_TYPE RELEASE) - endif() - elseif(TBB_USE_DEBUG_BUILD) - set(TBB_BUILD_TYPE DEBUG) - else() - set(TBB_BUILD_TYPE RELEASE) - endif() - - ################################## - # Set the TBB search directories - ################################## - - # Define search paths based on user input and environment variables - set(TBB_SEARCH_DIR ${TBB_ROOT_DIR} $ENV{TBB_INSTALL_DIR} $ENV{TBBROOT}) - - # Define the search directories based on the current platform - if(CMAKE_SYSTEM_NAME STREQUAL "Windows") - set(TBB_DEFAULT_SEARCH_DIR "C:/Program Files/Intel/TBB" - "C:/Program Files (x86)/Intel/TBB") - - # Set the target architecture - if(CMAKE_SIZEOF_VOID_P EQUAL 8) - set(TBB_ARCHITECTURE "intel64") - else() - set(TBB_ARCHITECTURE "ia32") - endif() - - # Set the TBB search library path search suffix based on the version of VC - if(WINDOWS_STORE) - set(TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc11_ui") - elseif(MSVC14) - set(TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc14") - elseif(MSVC12) - set(TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc12") - elseif(MSVC11) - set(TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc11") - elseif(MSVC10) - set(TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc10") - endif() - - # Add the library path search suffix for the VC independent version of TBB - list(APPEND TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc_mt") - - elseif(CMAKE_SYSTEM_NAME STREQUAL "Darwin") - # OS X - set(TBB_DEFAULT_SEARCH_DIR "/opt/intel/tbb") - - # TODO: Check to see which C++ library is being used by the compiler. - if(NOT ${CMAKE_SYSTEM_VERSION} VERSION_LESS 13.0) - # The default C++ library on OS X 10.9 and later is libc++ - set(TBB_LIB_PATH_SUFFIX "lib/libc++" "lib") - else() - set(TBB_LIB_PATH_SUFFIX "lib") - endif() - elseif(CMAKE_SYSTEM_NAME STREQUAL "Linux") - # Linux - set(TBB_DEFAULT_SEARCH_DIR "/opt/intel/tbb") - - # TODO: Check compiler version to see the suffix should be /gcc4.1 or - # /gcc4.1. For now, assume that the compiler is more recent than - # gcc 4.4.x or later. - if(CMAKE_SYSTEM_PROCESSOR STREQUAL "x86_64") - set(TBB_LIB_PATH_SUFFIX "lib/intel64/gcc4.4") - elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "^i.86$") - set(TBB_LIB_PATH_SUFFIX "lib/ia32/gcc4.4") - endif() - endif() - - ################################## - # Find the TBB include dir - ################################## - - find_path(TBB_INCLUDE_DIRS tbb/tbb.h - HINTS ${TBB_INCLUDE_DIR} ${TBB_SEARCH_DIR} - PATHS ${TBB_DEFAULT_SEARCH_DIR} - PATH_SUFFIXES include) - - ################################## - # Set version strings - ################################## - - if(TBB_INCLUDE_DIRS) - file(READ "${TBB_INCLUDE_DIRS}/tbb/tbb_stddef.h" _tbb_version_file) - string(REGEX REPLACE ".*#define TBB_VERSION_MAJOR ([0-9]+).*" "\\1" - TBB_VERSION_MAJOR "${_tbb_version_file}") - string(REGEX REPLACE ".*#define TBB_VERSION_MINOR ([0-9]+).*" "\\1" - TBB_VERSION_MINOR "${_tbb_version_file}") - string(REGEX REPLACE ".*#define TBB_INTERFACE_VERSION ([0-9]+).*" "\\1" - TBB_INTERFACE_VERSION "${_tbb_version_file}") - set(TBB_VERSION "${TBB_VERSION_MAJOR}.${TBB_VERSION_MINOR}") - endif() - - ################################## - # Find TBB components - ################################## - - if(TBB_VERSION VERSION_LESS 4.3) - set(TBB_SEARCH_COMPOMPONENTS tbb_preview tbbmalloc tbb) - else() - set(TBB_SEARCH_COMPOMPONENTS tbb_preview tbbmalloc_proxy tbbmalloc tbb) - endif() - - # Find each component - foreach(_comp ${TBB_SEARCH_COMPOMPONENTS}) - if(";${TBB_FIND_COMPONENTS};tbb;" MATCHES ";${_comp};") - - # Search for the libraries - find_library(TBB_${_comp}_LIBRARY_RELEASE ${_comp} - HINTS ${TBB_LIBRARY} ${TBB_SEARCH_DIR} - PATHS ${TBB_DEFAULT_SEARCH_DIR} ENV LIBRARY_PATH - PATH_SUFFIXES ${TBB_LIB_PATH_SUFFIX}) - - find_library(TBB_${_comp}_LIBRARY_DEBUG ${_comp}_debug - HINTS ${TBB_LIBRARY} ${TBB_SEARCH_DIR} - PATHS ${TBB_DEFAULT_SEARCH_DIR} ENV LIBRARY_PATH - PATH_SUFFIXES ${TBB_LIB_PATH_SUFFIX}) - - if(TBB_${_comp}_LIBRARY_DEBUG) - list(APPEND TBB_LIBRARIES_DEBUG "${TBB_${_comp}_LIBRARY_DEBUG}") - endif() - if(TBB_${_comp}_LIBRARY_RELEASE) - list(APPEND TBB_LIBRARIES_RELEASE "${TBB_${_comp}_LIBRARY_RELEASE}") - endif() - if(TBB_${_comp}_LIBRARY_${TBB_BUILD_TYPE} AND NOT TBB_${_comp}_LIBRARY) - set(TBB_${_comp}_LIBRARY "${TBB_${_comp}_LIBRARY_${TBB_BUILD_TYPE}}") - endif() - - if(TBB_${_comp}_LIBRARY AND EXISTS "${TBB_${_comp}_LIBRARY}") - set(TBB_${_comp}_FOUND TRUE) - else() - set(TBB_${_comp}_FOUND FALSE) - endif() - - # Mark internal variables as advanced - mark_as_advanced(TBB_${_comp}_LIBRARY_RELEASE) - mark_as_advanced(TBB_${_comp}_LIBRARY_DEBUG) - mark_as_advanced(TBB_${_comp}_LIBRARY) - - endif() - endforeach() - - ################################## - # Set compile flags and libraries - ################################## - - set(TBB_DEFINITIONS_RELEASE "") - set(TBB_DEFINITIONS_DEBUG "-DTBB_USE_DEBUG=1") - - if(TBB_LIBRARIES_${TBB_BUILD_TYPE}) - set(TBB_DEFINITIONS "${TBB_DEFINITIONS_${TBB_BUILD_TYPE}}") - set(TBB_LIBRARIES "${TBB_LIBRARIES_${TBB_BUILD_TYPE}}") - elseif(TBB_LIBRARIES_RELEASE) - set(TBB_DEFINITIONS "${TBB_DEFINITIONS_RELEASE}") - set(TBB_LIBRARIES "${TBB_LIBRARIES_RELEASE}") - elseif(TBB_LIBRARIES_DEBUG) - set(TBB_DEFINITIONS "${TBB_DEFINITIONS_DEBUG}") - set(TBB_LIBRARIES "${TBB_LIBRARIES_DEBUG}") - endif() - - find_package_handle_standard_args(TBB - REQUIRED_VARS TBB_INCLUDE_DIRS TBB_LIBRARIES - HANDLE_COMPONENTS - VERSION_VAR TBB_VERSION) - - ################################## - # Create targets - ################################## - - if(NOT CMAKE_VERSION VERSION_LESS 3.0 AND TBB_FOUND) - add_library(tbb SHARED IMPORTED) - set_target_properties(tbb PROPERTIES - INTERFACE_INCLUDE_DIRECTORIES ${TBB_INCLUDE_DIRS} - IMPORTED_LOCATION ${TBB_LIBRARIES}) - if(TBB_LIBRARIES_RELEASE AND TBB_LIBRARIES_DEBUG) - set_target_properties(tbb PROPERTIES - INTERFACE_COMPILE_DEFINITIONS "$<$,$>:TBB_USE_DEBUG=1>" - IMPORTED_LOCATION_DEBUG ${TBB_LIBRARIES_DEBUG} - IMPORTED_LOCATION_RELWITHDEBINFO ${TBB_LIBRARIES_DEBUG} - IMPORTED_LOCATION_RELEASE ${TBB_LIBRARIES_RELEASE} - IMPORTED_LOCATION_MINSIZEREL ${TBB_LIBRARIES_RELEASE} - ) - elseif(TBB_LIBRARIES_RELEASE) - set_target_properties(tbb PROPERTIES IMPORTED_LOCATION ${TBB_LIBRARIES_RELEASE}) - else() - set_target_properties(tbb PROPERTIES - INTERFACE_COMPILE_DEFINITIONS "${TBB_DEFINITIONS_DEBUG}" - IMPORTED_LOCATION ${TBB_LIBRARIES_DEBUG} - ) - endif() - endif() - - mark_as_advanced(TBB_INCLUDE_DIRS TBB_LIBRARIES) - - unset(TBB_ARCHITECTURE) - unset(TBB_BUILD_TYPE) - unset(TBB_LIB_PATH_SUFFIX) - unset(TBB_DEFAULT_SEARCH_DIR) - -endif() diff --git a/docker/Dockerfile.base b/docker/Dockerfile.base index fafef66d3..bffd33166 100755 --- a/docker/Dockerfile.base +++ b/docker/Dockerfile.base @@ -1,9 +1,9 @@ -FROM ubuntu:20.04 +FROM ubuntu:22.04 ENV DEBIAN_FRONTEND=noninteractive RUN apt-get update && apt-get install software-properties-common -y # 18.04 includes 2.17 but github requires 2.18+ to support submodules. RUN add-apt-repository ppa:git-core/ppa -ADD .github/workflows/install_dependencies_build.sh install_dependencies_build.sh +ADD .github/workflows/install_dependencies_build_ubuntu22p04.sh install_dependencies_build.sh RUN bash install_dependencies_build.sh ADD requirements.txt requirements.txt RUN python3 -m pip install -r requirements.txt diff --git a/docker/Dockerfile.clang-10 b/docker/Dockerfile.clang-10 deleted file mode 100644 index 447c5fc81..000000000 --- a/docker/Dockerfile.clang-10 +++ /dev/null @@ -1,2 +0,0 @@ -FROM ghcr.io/lnis-uofu/openfpga-build-base -RUN apt-get update && apt-get install -y clang-format-7 clang-10 diff --git a/docker/Dockerfile.clang-11 b/docker/Dockerfile.clang-11 new file mode 100644 index 000000000..4ba9ad201 --- /dev/null +++ b/docker/Dockerfile.clang-11 @@ -0,0 +1,2 @@ +FROM ghcr.io/lnis-uofu/openfpga-build-base +RUN apt-get update && apt-get install -y clang-format-14 clang-11 diff --git a/docker/Dockerfile.clang-12 b/docker/Dockerfile.clang-12 new file mode 100644 index 000000000..57a8dbd0d --- /dev/null +++ b/docker/Dockerfile.clang-12 @@ -0,0 +1,2 @@ +FROM ghcr.io/lnis-uofu/openfpga-build-base +RUN apt-get update && apt-get install -y clang-format-14 clang-12 diff --git a/docker/Dockerfile.clang-13 b/docker/Dockerfile.clang-13 new file mode 100644 index 000000000..902e8f29f --- /dev/null +++ b/docker/Dockerfile.clang-13 @@ -0,0 +1,2 @@ +FROM ghcr.io/lnis-uofu/openfpga-build-base +RUN apt-get update && apt-get install -y clang-format-14 clang-13 diff --git a/docker/Dockerfile.clang-14 b/docker/Dockerfile.clang-14 new file mode 100644 index 000000000..bad23c8b0 --- /dev/null +++ b/docker/Dockerfile.clang-14 @@ -0,0 +1,2 @@ +FROM ghcr.io/lnis-uofu/openfpga-build-base +RUN apt-get update && apt-get install -y clang-format-14 clang-14 diff --git a/docker/Dockerfile.clang-6.0 b/docker/Dockerfile.clang-6.0 deleted file mode 100644 index 6d7c36b3e..000000000 --- a/docker/Dockerfile.clang-6.0 +++ /dev/null @@ -1,2 +0,0 @@ -FROM ghcr.io/lnis-uofu/openfpga-build-base -RUN apt-get update && apt-get install -y clang-format-7 clang-6.0 diff --git a/docker/Dockerfile.clang-7 b/docker/Dockerfile.clang-7 deleted file mode 100644 index 485a61318..000000000 --- a/docker/Dockerfile.clang-7 +++ /dev/null @@ -1,2 +0,0 @@ -FROM ghcr.io/lnis-uofu/openfpga-build-base -RUN apt-get update && apt-get install -y clang-format-7 clang-7 diff --git a/docker/Dockerfile.clang-8 b/docker/Dockerfile.clang-8 deleted file mode 100644 index 5a4a5f4ef..000000000 --- a/docker/Dockerfile.clang-8 +++ /dev/null @@ -1,2 +0,0 @@ -FROM ghcr.io/lnis-uofu/openfpga-build-base -RUN apt-get update && apt-get install -y clang-format-7 clang-8 diff --git a/docker/Dockerfile.env b/docker/Dockerfile.env index b2ca7c202..642d8589b 100644 --- a/docker/Dockerfile.env +++ b/docker/Dockerfile.env @@ -1,15 +1,13 @@ -FROM ubuntu:20.04 +FROM ubuntu:22.04 ENV DEBIAN_FRONTEND=noninteractive RUN apt-get update && apt-get install --no-install-recommends software-properties-common -y # 18.04 includes 2.17 but github requires 2.18+ to support submodules. #RUN add-apt-repository ppa:git-core/ppa -ADD .github/workflows/install_dependencies_run.sh install_dependencies_run.sh +ADD .github/workflows/install_dependencies_run_ubuntu22p04.sh install_dependencies_run.sh RUN bash install_dependencies_run.sh RUN curl https://bootstrap.pypa.io/get-pip.py -o get-pip.py -RUN python3.8 get-pip.py && rm get-pip.py -RUN update-alternatives --install /usr/bin/python3 python3 /usr/bin/python3.8 2 -# Comment out this line since Ubuntu 20.04 does not support it -# RUN update-alternatives --install /usr/bin/python3 python3 /usr/bin/python3.6 1 +RUN python3.10 get-pip.py && rm get-pip.py +RUN update-alternatives --install /usr/bin/python3 python3 /usr/bin/python3.10 2 ADD requirements.txt requirements.txt -ENV PYTHON_EXEC=python3.8 +ENV PYTHON_EXEC=python3.10 RUN ${PYTHON_EXEC} -m pip install -r requirements.txt diff --git a/docker/Dockerfile.gcc-12 b/docker/Dockerfile.gcc-12 new file mode 100644 index 000000000..d21a8e1ed --- /dev/null +++ b/docker/Dockerfile.gcc-12 @@ -0,0 +1,2 @@ +FROM ghcr.io/lnis-uofu/openfpga-build-base +RUN add-apt-repository -y ppa:ubuntu-toolchain-r/test && apt-get update && apt-get install -y gcc-12 g++-12 diff --git a/docker/Dockerfile.gcc-7 b/docker/Dockerfile.gcc-7 deleted file mode 100644 index d7638677b..000000000 --- a/docker/Dockerfile.gcc-7 +++ /dev/null @@ -1,2 +0,0 @@ -FROM ghcr.io/lnis-uofu/openfpga-build-base -RUN apt-get update && apt-get install -y gcc-7 g++-7 diff --git a/docker/Dockerfile.gcc-8 b/docker/Dockerfile.gcc-8 deleted file mode 100644 index 187a47623..000000000 --- a/docker/Dockerfile.gcc-8 +++ /dev/null @@ -1,2 +0,0 @@ -FROM ghcr.io/lnis-uofu/openfpga-build-base -RUN apt-get update && apt-get install -y gcc-8 g++-8 diff --git a/docs/source/dev_manual/cicd_setup.rst b/docs/source/dev_manual/ci.rst similarity index 62% rename from docs/source/dev_manual/cicd_setup.rst rename to docs/source/dev_manual/ci.rst index 92609ccd3..043edb1db 100644 --- a/docs/source/dev_manual/cicd_setup.rst +++ b/docs/source/dev_manual/ci.rst @@ -1,4 +1,64 @@ -.. dev_manual_cicd_setup:: +.. _developer_ci: + +Continous Integration +===================== + +Motivation +---------- + +Continous Integration (CI) systems are built to ensure that input and output files of each teams are + +- Correct +- Reproducable +- Consistent with other teams + +CI system is automatically triggered on + +- Main branch: the master branch of the codebase +- A pull request on main branch + +Workflows +--------- + +Principles +^^^^^^^^^^ + +Continous Integration system consists a number of workflows, each of which is designed to validate a specific aspect of the codebase. +For the work of each team, there is at least 1 dedicated workflow. + +Workflows can categorized in two types + +.. option:: Generation flow + + Such type of workflow is designed to ensure that golden files (netlists, bitstreams, etc.) are reproduciable. + A generation workflow consists of three steps: + + - Detect changes on input files, e.g., architecture files, IPs and related scripts. + + - If no changes detected, the workflow ends, since the golden outputs are not changed in a pull request + - If any changes are detected, the workflow will continue to the next steps + + - Regenerate golden files by calling scripts. By the end of this step, it will compare the newly generated files with the golden reference (current branch) + - If there are no changes, the workflow ends. + - If any changes on golden reference are detected, this will error out. It means that the current golden reference are not reproduciable. + + .. warning:: If any changes on golden references are detected, code review has to be enforced. Ensure that all the teams impacted agree on the changes. + +.. option:: Validation flow + + Such type of workflow is designed to verify the correctness of golden files + A validation workflow consists of three steps: + + - Detect changes on golden reference (some pull requests update golden references) + + - If no changes detected, the workflow ends. There is no need to validate the correctness of the golden reference (previous pull request should already do so). + - If any changes are detected, the workflow will continue to the next steps + + - Run validation by calling scripts. For example, verification may call HDL simulations to verify the correctness of netlists. + - If the new golden reference passes all the tests, this will end. + - If the new golden reference fails any test, this will error out. It means that the current golden reference can not meet basic requirements. + + .. warning:: If any validation flow failed, the pull request cannot be merged in general. CI/CD setup ----------- diff --git a/docs/source/dev_manual/contributor_guidelines/general_rules.rst b/docs/source/dev_manual/contributor_guidelines/general_rules.rst new file mode 100644 index 000000000..3df8e658b --- /dev/null +++ b/docs/source/dev_manual/contributor_guidelines/general_rules.rst @@ -0,0 +1,44 @@ +.. _developer_contributor_guidelines_general_rules: + +General Rules +============= + +Motivation +---------- +Github projects involve many parties with different interests. +It is necessary to establish rules to + +- guarantee the quality of each pull request by establishing a standard +- code review for each pull request is straightforward +- contributors have confidence when submitting changes + +Create Pull requests +-------------------- + +- Contributors should state clearly their motivation and the principles of code changes in each pull request +- Contributors should be active in resolving conflicts with other contributors as well as maintainers. In principle, all the maintainers want every pull request in and are looking for reasons to approve it. +- Each pull request should pass all the existing tests in CI (See :ref:`developer_contributor_guidelines_checkin_system` for details). Otherwise, it should not be merged unless you get a waiver from all the maintainers. +- Contributors should not modify any codes/tests which are unrelated to the scope of their pull requests. +- The size of each pull request should be small. Large pull request takes weeks to be merged. The recommend size of pull request is up to 500 lines of codes changes. If you have one large file, this can be waived. However, the number of files to be changed should be as small as possible. + + .. note:: For large pull requests, it is strongly recommended that contributors should talk to maintainers first or create an issue on the Github. Contributors should clearly define the motivation, detailed technical plan as well as deliverables. Through discussions, the technical plan may be requested to change. Please do not start code changes blindly before the technical plan is approved. + +- For any new feature/functionality to be added, there should be + + - Dedicated test cases in CI which validates its correctness + - An update on the documentation, if it changes user interface + - Provide sufficient code comments to ease the maintenance + +.. _developer_contributor_guidelines_checkin_system: + +Check-in System +--------------- + +.. seealso:: The check-in system is based on continous integration (CI). See details in :ref:`developer_ci` + +The check-in system aims to offer a standardized way to + +- ensure quailty of each contribution +- resolve conflicts between teams + +It is designed for efficient communication between teams. diff --git a/docs/source/dev_manual/contributor_guidelines/index.rst b/docs/source/dev_manual/contributor_guidelines/index.rst new file mode 100644 index 000000000..0fa7b108b --- /dev/null +++ b/docs/source/dev_manual/contributor_guidelines/index.rst @@ -0,0 +1,11 @@ +.. _developer_contributor_guidelines: + +Contributor Guidelines +====================== + +.. toctree:: + :maxdepth: 2 + + general_rules + + naming_convention diff --git a/docs/source/dev_manual/contributor_guidelines/naming_convention.rst b/docs/source/dev_manual/contributor_guidelines/naming_convention.rst new file mode 100644 index 000000000..34b775654 --- /dev/null +++ b/docs/source/dev_manual/contributor_guidelines/naming_convention.rst @@ -0,0 +1,224 @@ +.. _developer_naming_convention: + +Naming Convention +================= + +.. _developer_naming_convention_cell_names: + +Cell Names +---------- + +.. warning:: This is a different concept than the cell names in :ref:`developer_naming_convention_ff_model_names`! + +.. note:: we refer to standard cell wrapper here. Wrappers are built to make netlists portable between PDKs as well as across standard cell libraries in a PDK. + +For code readability, the cell name should follow the convention +:: + _ + +.. option:: Cell_Function + + Name of logic function, e.g., AND2, XNOR3, etc. + +.. option:: Set_Features + + This is mainly for sequential cells, e.g., D-type flip-flops. If a cell contains a set signal, its existence and polarity must be inferreable by the cell name. The available options are + + - S: Asynchronous active-high set + - SYNS: Synchronous active-hight set + - SN: Asynchronous active-low set + - SYNSN: Synchronous active-low set + + .. note:: For cells without set, this keyword should be empty + +.. option:: Reset_Features + + This is mainly for sequential cells, e.g., D-type flip-flops. If a cell contains a reset signal, its existence and polarity must be inferreable by the cell name. The available options are + + - R: Asynchronous active-high reset + - SYNR: Synchronous active-hight reset + - RN: Asynchronous active-low reset + - SYNRN: Synchronous active-low reset + + .. note:: For cells without reset, this keyword should be empty + +.. option:: Output_Features + + This is mainly for sequential cells, e.g., D-type flip-flops. + + - If not specified, the sequential cell contains a pair of differential outputs, e.g., ``Q`` and ``QN`` + - If specified, the sequential cell only contains single output, e.g., ``Q`` + + The available options are + + - Q: single output which is positive + - QN: single ouput which is negative + + .. note:: For cells without reset, this keyword should be empty + +.. option:: Drive_Strength + + This is to specify the drive strength of a cell + + - If not specified, we assume minimum drive strength, i.e., ``D0``. + - If specified, we expect a format of ``D``, where the integer indicates the drive strength + +.. option:: Wrapper + + This is to specify if the cell is a wrapper of an existing standard cell + + - If not specified, we assume this cell contains RTL + - If specified, we assume this cell is a wrapper of an existing standard cell + +A quick example +:: + NAND2D4_WRAPPER + +represents a wrapper for a standard cell that is a 2-input NAND gate with a drive strength of 4 + +Another example +:: + SDFFSSYNRNQ + +represents a scan-chain flip-flop which contains + + - Asynchronous active-high set + - Synchronous active-low reset + - Single output + +Pin Names +--------- + +.. note:: Please use lowercase as much as you can + +For code readability, the pin name should follow the convention +:: + _ + + +.. option:: Pin_Name + + Represents the pin name + +.. option:: Polarity + + Represents polarity of the pin, it can be + + - ``n`` denotes a negative-enable (active_low) signal + + .. note:: When not specified, by default we assume this is a postive-enable (active-high) signal + +.. option:: Direction + + Represents the direction of a pin, it can be + + - ``i`` denotes an input signal + - ``o`` denotes an output signal + +A quick example +:: + clk_ni + +represents an input clock signal which is negative-enable + +Another example +:: + q_no + +represents an output Q signal which is negative to the input + +.. _developer_naming_convention_ff_model_names: + +Flip-flop Model Names +--------------------- + +.. warning:: This is a different concept than the cell names in :ref:`developer_naming_convention_cell_names`! + +.. note:: we refer to virtual cell model (used by VPR and Yosys for cell mapping) here. + +For code readability, D-type flip-flop model names should follow the convention +:: + dff + +.. option:: Sync_Features + + Represents if the reset/set is synchronous or asynchronous to the clock, it can be + + - ``s`` denotes a synchronous behavior + - an empty string "" denotes an asynchronous behavior, e.g., ``ffr`` + +.. option:: Trigger_Type + + Represents if the flip-flop is triggered by rising edge or falling edge of a clock, it can be + + - ``n`` means triggered by failling edge + - an empty string "" means triggered by rising edge, e.g., ``ff`` + +.. option:: Set_Type + + Represents if the flip-flop has a set and the polarity of the set, it can be + + - ``s`` means that the flip-flop has an active-high set pin + - ``sn`` means that the flip-flop has an active-low set pin + - an empty string "" means the flip-flop does not have a set pin, e.g., ``ff`` + +.. option:: Reset_Type + + Represents if the flip-flop has a reset and the polarity of the reset, it can be + + - ``r`` means that the flip-flop has an active-high reset pin + - ``rn`` means that the flip-flop has an active-low reset pin + - an empty string "" means the flip-flop does not have a reset pin, e.g., ``ff`` + + +A quick example +:: + ffnrn + +represents a flip-flop + +- triggered by falling edge +- with an asynchronous active-low reset + +Another example +:: + sffs + +represents a flip-flop + +- triggered by rising edge +- with a synchronous active-high set + +.. _developer_naming_convention_mux_model_names: + +Multiplexer Model Names +----------------------- + +.. warning:: This is a different concept than the cell names in :ref:`developer_naming_convention_cell_names`! + +.. note:: Here, we refer to the circuit model name used in OpenFPGA architecture file. + +For code readability, a routing multiplexer circuit model name should follow the convention +:: + _mux_ + +.. option:: Location + + Represents the location of the routing multiplexers, it can be + + - ``cb`` denotes a routing multiplexer in a connection block + - ``sb`` denotes a routing multiplexer in a switch block + - ``pb`` denotes a routing multiplexer in a programmable block + +.. option:: Load + + Represents the output load condition of the routing multiplexers, it can be + + - ``highload`` means that the routing multiplexer has to drive a very high capacitive load, which potentially requires a big buffer at output + - an empty string "" means the routing multiplexer requires only a typical buffer size. + +A quick example +:: + pb_mux_highload + +represents a routing multiplexer used in a programmable block which drives a high capacitive load diff --git a/docs/source/dev_manual/index.rst b/docs/source/dev_manual/index.rst index 6f5fd58ba..0a86d4b12 100644 --- a/docs/source/dev_manual/index.rst +++ b/docs/source/dev_manual/index.rst @@ -1,16 +1,22 @@ +.. _developer: + Developer Guidelines .. toctree:: - :maxdepth: 1 + :maxdepth: 2 version_number back_compatible - contributor_guidelines - - cicd_setup + ci regression_tests tcl_api + +.. toctree:: + :maxdepth: 2 + :caption: Contributor Guidelines + + contributor_guidelines/index diff --git a/docs/source/manual/arch_lang/config_protocol.rst b/docs/source/manual/arch_lang/config_protocol.rst index d4d4d052e..f1a816eb3 100644 --- a/docs/source/manual/arch_lang/config_protocol.rst +++ b/docs/source/manual/arch_lang/config_protocol.rst @@ -7,6 +7,17 @@ Configuration protocol is the circuitry designed to program an FPGA. As an interface, configuration protocol could be really different in FPGAs, depending on the application context. OpenFPGA supports versatile configuration protocol, providing different trade-offs between speed and area. +Under configuration protocol, if the configuration is QL Memory Bank with flatten BL/WL protocol, there might be +optional configuration setting call . +In QL Memory Bank configuration protocol, configuration bits are organized as BitLine (BL) x WordLine (WL) +By default, OpenFPGA will keep BL and WL in square shape if possible where BL might be one bit longer than WL in some cases + For example: + - If the configuration bits of a PB is 9 bits, then BL=3 and WL=3 + - If the configuration bits of a PB is 11 bits, then BL=4 and WL=3 (where there is one extra bit as phantom bit) + - If the configuration bits of a PB is 14 bits, then BL=4 and WL=4 (where there is two extra bits as phantom bits) + +This QL Memory Bank configuration setting allow OpenFPGA to use a fixed WL size, instead of default approach + Template ~~~~~~~~ @@ -14,6 +25,9 @@ Template + + + .. option:: type="scan_chain|memory_bank|standalone|frame_based|ql_memory_bank" @@ -54,6 +68,29 @@ Template .. note:: For ``ql_memory_bank`` configuration protocol when BL/WL protocol ``shift_register`` is selected, different configuration regions **cannot** share any WLs on the same row! In such case, the default fabric key may not work. Strongly recommend to craft your own fabric key based on your configuration region plannning! +.. option:: name="" + + Specify the name of PB type, for example: clb, dsp, bram and etc + +.. option:: num_wl="" + + Fix the size of WL + + For example: + Considered that the configuration bits of a PB is 400 bits. + + If num_wl is not defined, then + - BL will be 20 [=ceiling(square_root(400))] + - WL will be 20 [=ceiling(400/20)] + + If num_wl is defined as 10, then + - WL will be fixed as 10 + - BL will be 40 [=ceiling(400/10)] + + If num_wl is defined as 32, then + - WL will be fixed as 32 + - BL will be 13 [=ceiling(400/32)] + - There will be 16 bits [=(32x13)-400] as phantom bits. Configuration Chain Example ~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/source/manual/arch_lang/direct_interconnect.rst b/docs/source/manual/arch_lang/direct_interconnect.rst index 21b91b74b..5024171cb 100644 --- a/docs/source/manual/arch_lang/direct_interconnect.rst +++ b/docs/source/manual/arch_lang/direct_interconnect.rst @@ -1,12 +1,12 @@ .. _direct_interconnect: -Inter-Tile Direct Interconnection extensions --------------------------------------------- +Direct Interconnect +------------------- -This section introduces extensions on the architecture description file about existing interconnection description. +This section introduces extensions on the architecture description file about direct connections between programmable blocks. -Directlist -~~~~~~~~~~ +Syntax +~~~~~~ The original direct connections in the directlist section are documented here_. Its description is given below: @@ -20,20 +20,26 @@ The original direct connections in the directlist section are documented here_. .. note:: These options are required -Our extension include three more options: +In the OpenFPGA architecture file, you may define additional attributes for each VPR's direct connection: .. code-block:: xml - - + + -.. note:: these options are optional. However, if `interconnection_type` is set `x_dir` and `y_dir` are required. +.. note:: these options are optional. However, if ``interconnection_type`` is set to ``inter_column`` or ``inter_row``, then ``x_dir`` and ``y_dir`` are required. .. option:: interconnection_type="" - the type of interconnection should be a string. - Available types are ``NONE`` | ``column`` | ``row``, specifies if it applies on a column or a row ot if it doesn't apply. + Available types are ``inner_column_or_row`` | ``part_of_cb`` | ``inter_column`` | ``inter_row`` + + - ``inner_column_or_row`` indicates the direct connections are between tiles in the same column or row. This is the default value. + - ``part_of_cb`` indicates the direct connections will drive routing multiplexers in connection blocks. Therefore, it is no longer a strict point-to-point direct connection. + - ``inter_column`` indicates the direct connections are between tiles in two columns + - ``inter_row`` indicates the direct connections are between tiles in two rows + +.. note:: The following syntax is only applicable to ``inter_column`` and ``inter_row`` .. option:: x_dir="" @@ -42,15 +48,15 @@ Our extension include three more options: - x_dir="positive": - - interconnection_type="column": a column will be connected to a column on the ``right``, if it exists. + - interconnection_type="inter_column": a column will be connected to a column on the ``right``, if it exists. - - interconnection_type="row": the most on the ``right`` cell from a row connection will connect the most on the ``left`` cell of next row, if it exists. + - interconnection_type="inter_row": the most on the ``right`` cell from a row connection will connect the most on the ``left`` cell of next row, if it exists. - x_dir="negative": - - interconnection_type="column": a column will be connected to a column on the ``left``, if it exists. + - interconnection_type="inter_column": a column will be connected to a column on the ``left``, if it exists. - - interconnection_type="row": the most on the ``left`` cell from a row connection will connect the most on the ``right`` cell of next row, if it exists. + - interconnection_type="inter_row": the most on the ``left`` cell from a row connection will connect the most on the ``right`` cell of next row, if it exists. .. option:: y_dir="" @@ -59,27 +65,96 @@ Our extension include three more options: - y_dir="positive": - - interconnection_type="column": the ``bottom`` cell of a column will be connected to the next column ``top`` cell, if it exists. + - interconnection_type="inter_column": the ``bottom`` cell of a column will be connected to the next column ``top`` cell, if it exists. - - interconnection_type="row": a row will be connected on an ``above`` row, if it exists. + - interconnection_type="inter_row": a row will be connected on an ``above`` row, if it exists. - y_dir="negative": - - interconnection_type="column": the ``top`` cell of a column will be connected to the next column ``bottom`` cell, if it exists. + - interconnection_type="inter_column": the ``top`` cell of a column will be connected to the next column ``bottom`` cell, if it exists. - - interconnection_type="row": a row will be connected on a row ``below``, if it exists. + - interconnection_type="inter_row": a row will be connected on a row ``below``, if it exists. -Example -~~~~~~~ +Enhanced Connection Block +~~~~~~~~~~~~~~~~~~~~~~~~~ -For this example, we will study a scan-chain implementation. The description could be: +The direct connection can also drive routing multiplexers of connection blocks. When such connection occures in a connection block, it is called enhanced connection block. +:numref:`fig_ecb` illustrates the difference between a regular connection block and an enhanced connection block. + +.. _fig_ecb: + +.. figure:: ./figures/ecb.png + + Enhanced connection block vs. Regular connection block + +In such scenario, the type ``part_of_cb`` is required. + +.. warning:: Restrictions may be applied when building the direct connections as part of a connection block. + +Direct connections can be inside a tile or across two tiles. Currently, across more than two tiles are not supported! +:numref:`fig_ecb_allowed_direct_connection` illustrates the region (in red) where any input pin is allowed to be driven by any output pin. + +.. _fig_ecb_allowed_direct_connection: + +.. figure:: ./figures/ecb_allowed_direct_connection.png + + Allowed connections inside a tile for enhanced connection block (see the highlighted region) + +:numref:`fig_ecb_allowed_direct_connection_inner_tile_example` shows a few feedback connections which can be built inside connection blocks. Note that feedback connections are fully allowed between any pins on the same side of a programmable block. + +.. _fig_ecb_allowed_direct_connection_inner_tile_example: + +.. figure:: ./figures/ecb_allowed_direct_connection_inner_tile_example.png + + Example of feedback connections inside a tile for enhanced connection block + +For instance, VPR architecture defines feedback connections like: .. code-block:: xml - + + + +:numref:`fig_ecb_allowed_direct_connection_inter_tile_example` shows a few inter-tile connections which can be built inside connection blocks. Note that inter-tile connections are subjected to the restrictions depicted in :numref:`fig_ecb_allowed_direct_connection` + +.. _fig_ecb_allowed_direct_connection_inter_tile_example: + +.. figure:: ./figures/ecb_allowed_direct_connection_inter_tile_example.png + + Example of connections across two tiles for enhanced connection block + +:numref:`fig_ecb_forbid_direct_connection_example` illustrates some inner-tile and inter-tile connections which are not allowed. Note that feedback connections across different sides are restricted! + +.. _fig_ecb_forbid_direct_connection_example: + +.. figure:: ./figures/ecb_forbid_direct_connection_example.png + + Restrictions on building direct connections as part of a connection block + +Inter-tile Connections +~~~~~~~~~~~~~~~~~~~~~~ + +For this example, we will study a scan-chain implementation. The description could be: + +In VPR architecture: + +.. code-block:: xml + + + + + +In OpenFPGA architecture: + +.. code-block:: xml + + + + + :numref:`fig_p2p_exple` is the graphical representation of the above scan-chain description on a 4x4 FPGA. .. _fig_p2p_exple: @@ -91,9 +166,6 @@ For this example, we will study a scan-chain implementation. The description cou In this figure, the red arrows represent the initial direct connection. The green arrows represent the point to point connection to connect all the columns of CLB. -Truth table -~~~~~~~~~~~ - A point to point connection can be applied in different ways than showed in the example section. To help the designer implement his point to point connection, a truth table with our new parameters id provided below. :numref:`fig_p2p_trtable` provides all possible variable combination and the connection it will generate. diff --git a/docs/source/manual/arch_lang/figures/ecb.png b/docs/source/manual/arch_lang/figures/ecb.png new file mode 100644 index 000000000..5a6afd99c Binary files /dev/null and b/docs/source/manual/arch_lang/figures/ecb.png differ diff --git a/docs/source/manual/arch_lang/figures/ecb_allowed_direct_connection.png b/docs/source/manual/arch_lang/figures/ecb_allowed_direct_connection.png new file mode 100644 index 000000000..bc8e07855 Binary files /dev/null and b/docs/source/manual/arch_lang/figures/ecb_allowed_direct_connection.png differ diff --git a/docs/source/manual/arch_lang/figures/ecb_allowed_direct_connection_inner_tile_example.png b/docs/source/manual/arch_lang/figures/ecb_allowed_direct_connection_inner_tile_example.png new file mode 100644 index 000000000..e084cfdff Binary files /dev/null and b/docs/source/manual/arch_lang/figures/ecb_allowed_direct_connection_inner_tile_example.png differ diff --git a/docs/source/manual/arch_lang/figures/ecb_allowed_direct_connection_inter_tile_example.png b/docs/source/manual/arch_lang/figures/ecb_allowed_direct_connection_inter_tile_example.png new file mode 100644 index 000000000..156e8cb20 Binary files /dev/null and b/docs/source/manual/arch_lang/figures/ecb_allowed_direct_connection_inter_tile_example.png differ diff --git a/docs/source/manual/arch_lang/figures/ecb_forbid_direct_connection_example.png b/docs/source/manual/arch_lang/figures/ecb_forbid_direct_connection_example.png new file mode 100644 index 000000000..3a2391283 Binary files /dev/null and b/docs/source/manual/arch_lang/figures/ecb_forbid_direct_connection_example.png differ diff --git a/docs/source/manual/file_formats/fabric_hierarchy_file.rst b/docs/source/manual/file_formats/fabric_hierarchy_file.rst new file mode 100644 index 000000000..0d717afd3 --- /dev/null +++ b/docs/source/manual/file_formats/fabric_hierarchy_file.rst @@ -0,0 +1,62 @@ +.. _file_format_fabric_hierarchy_file: + +Fabric Hierarchy File (.yaml) +---------------------------------------- + +This file is generated by command :ref:`openfpga_setup_commands_write_fabric_hierarchy` + + +The fabric hierarchy file aims to show module trees of a number of given roots + +This file is created for netlist manipulation and detailed floorplanning during physical design steps + +By using the options of the command :ref:`openfpga_setup_commands_write_fabric_hierarchy`, user can selectively output the module tree on their needs. + +An example of the file is shown as follows. + +.. code-block:: yaml + + fpga_top: + tile_0__2_: + sb_0__1_: + mux_tree_tapbuf_size2: + INVTX1 + const1 + tap_buf4 + mux_tree_tapbuf_basis_input2_mem1: + - TGATE + mux_tree_tapbuf_size2_feedthrough_mem + sb_1__config_group_mem_size40: + mux_tree_tapbuf_size2_mem: + - DFF + tile_1__2_: + grid_io_top: + logical_tile_io_mode_io_: + logical_tile_io_mode_physical__iopad: + - GPIO + - GPIO_feedthrough_DFF_mem + direct_interc + +In this example, the root module is ``fpga_top``. +The child modules under ``fpga_top`` are ``tile_0__2_`` and ``tile_1__2_``. +Note that the leaf nodes are shown as a list, e.g., ``GPIO`` and ``GPIO_feedthrough_DFF_mem``. + +When multiple root modules are defined, the output could be + +.. code-block:: yaml + + sb_0__1_: + - mux_tree_tapbuf_size2 + sb_1__0_: + - mux_tree_tapbuf_size2 + sb_1__1_: + - mux_tree_tapbuf_size2 + cbx_1__0_: + - mux_tree_tapbuf_size4 + cbx_1__1_: + - mux_tree_tapbuf_size4 + cby_0__1_: + - mux_tree_tapbuf_size2 + - mux_tree_tapbuf_size4 + cby_1__1_: + - mux_tree_tapbuf_size4 diff --git a/docs/source/manual/file_formats/fabric_pin_physical_location_file.rst b/docs/source/manual/file_formats/fabric_pin_physical_location_file.rst new file mode 100644 index 000000000..ee24916e7 --- /dev/null +++ b/docs/source/manual/file_formats/fabric_pin_physical_location_file.rst @@ -0,0 +1,109 @@ +.. _file_format_fabric_pin_physical_location_file: + +Fabric Pin Physical Location File (.xml) +---------------------------------------- + +This file is generated by command :ref:`openfpga_setup_commands_write_fabric_pin_physical_location` + + +The fabric pin physical location file aims to show + +- Pin names of each module in an eFPGA fabric +- Preferred physical side of each pin on its module + +This file is created for pin guidelines during physical design steps + +An example of the file is shown as follows. + +.. code-block:: xml + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +.. option:: name="" + + The module name in FPGA fabric, which should be a valid module defined in output Verilog netlist. + + .. note:: You should be find the exact module in the FPGA fabric if you output the Verilog netlists. + +.. option:: pin="" + + The name of the pin in FPGA fabric. Note that all the bus port will be flatten in this file. + + .. note:: You should be find the exact pin in the module if you output the Verilog netlists. + +.. option:: side="" + + The physical side of the pin should appear on the perimeter of the module. diff --git a/docs/source/manual/file_formats/index.rst b/docs/source/manual/file_formats/index.rst index 6ec94c3b9..e873286fd 100644 --- a/docs/source/manual/file_formats/index.rst +++ b/docs/source/manual/file_formats/index.rst @@ -41,3 +41,7 @@ OpenFPGA widely uses XML format for interchangeable files module_naming_file tile_config_file + + fabric_pin_physical_location_file + + fabric_hierarchy_file diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index a78828484..2ad413605 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -176,6 +176,10 @@ __ iverilog_website_ .. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable. + .. option:: --dump_waveform + + Enable waveform output when runnign HDL simulation on the preconfigured wrapper. When enabled, waveform files can be outputted in two formats: ``fsdb`` and ``vcd`` through preprocessing flags ``DUMP_FSDB`` and ``DUMP_VCD`` respectively. For example, when using VCS,. the flag can be activiated by ``+define+DUMP_FSDB=1``. + .. option:: --no_time_stamp Do not print time stamp in Verilog netlists diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst index 9ea4b2145..ea2a20723 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst @@ -359,20 +359,33 @@ add_fpga_core_to_fabric Show verbose log +.. _openfpga_setup_commands_write_fabric_hierarchy: write_fabric_hierarchy ~~~~~~~~~~~~~~~~~~~~~~ - Write the hierarchy of FPGA fabric graph to a plain-text file + Write the hierarchy of FPGA fabric graph to a YAML file .. option:: --file or -f - Specify the file name to write the hierarchy. + Specify the file name to write the hierarchy. See details in :ref:`file_format_fabric_hierarchy_file`. .. option:: --depth Specify at which depth of the fabric module graph should the writer stop outputting. The root module start from depth 0. For example, if you want a two-level hierarchy, you should specify depth as 1. + .. option:: --module + + Specify the root module name(s) which should be considered. By default, it is ``fpga_top``. Note that regular expression is supported. For example, ``grid_*`` will output all the modules with a prefix of ``grid_`` + + .. option:: --filter + + Specify the filter which allows user to select modules to appear under each root module tree. By default, it is ``*``. Regular expression is supported. For example, ``*mux*`` will output all the modules which contains ``mux``. In the other words, the filter defines a white list. + + .. option:: --exclude_empty_modules + + Exclude modules with no qualified children (match the names defined through filter) from the output file + .. option:: --verbose Show verbose log @@ -392,7 +405,7 @@ write_fabric_io_info .. option:: --no_time_stamp - Do not print time stamp in bitstream files + Do not print time stamp in output files .. option:: --verbose @@ -433,7 +446,7 @@ pcf2place .. option:: --no_time_stamp - Do not print time stamp in bitstream files + Do not print time stamp in output files .. option:: --verbose @@ -467,7 +480,34 @@ write_module_naming_rules .. option:: --no_time_stamp - Do not print time stamp in bitstream files + Do not print time stamp in output files + + .. option:: --verbose + + Show verbose log + +.. _openfpga_setup_commands_write_fabric_pin_physical_location: + +write_fabric_pin_physical_location +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + Output the physical location of each pin for each module of an FPGA fabric to a given file + + .. option:: --file + + Specify the file path to be written to. See details in :ref:`file_format_fabric_pin_physical_location_file`. + + .. option:: --module + + Specify the name of modules to be considered. Support regular expression, e.g., ``tile*``. When provided, only pins of selected modules will be outputted. By default, a wildcard ``*`` is considered, which means all the modules will be considered. + + .. option:: --show_invalid_side + + Show sides for each pin, even these pin does not have a specific valid side. This is mainly used for debugging. + + .. option:: --no_time_stamp + + Do not print time stamp in output files .. option:: --verbose diff --git a/docs/source/tutorials/getting_started/compile.rst b/docs/source/tutorials/getting_started/compile.rst index 1a1cc89c0..fe7f0b5d6 100644 --- a/docs/source/tutorials/getting_started/compile.rst +++ b/docs/source/tutorials/getting_started/compile.rst @@ -12,7 +12,7 @@ How to Compile Supported Operating Systems ~~~~~~~~~~~~~~~~~~~~~~~~~~~ -OpenFPGA is continously tested with Ubuntu 20.04 and partially on Ubuntu 22.04 +OpenFPGA is continously tested with Ubuntu 22.04 and partially on Ubuntu 20.04 It might work with earlier versions and other distributions. In addition to continous integration, our community users have tested OpenFPGA on their local machines using the following operating systems: @@ -21,7 +21,6 @@ In addition to continous integration, our community users have tested OpenFPGA o - CentOS 8 - Ubuntu 18.04 - Ubuntu 21.04 -- Ubuntu 22.04 Build Steps ~~~~~~~~~~~ @@ -34,7 +33,7 @@ In general, please follow the steps to compile cd OpenFPGA make all -.. note:: OpenFPGA requires gcc/g++ version > 7 and clang version > 6. +.. note:: OpenFPGA requires gcc/g++ version > 9 and clang version > 10. .. note:: cmake3.12+ is recommended to compile OpenFPGA with GUI @@ -111,7 +110,7 @@ Ubuntu 20.04 - Dependencies required to run regression tests -.. include:: regtest_dependencies.sh +.. include:: ubuntu20p04_regtest_dependencies.sh :code: shell .. note:: Python packages are also required @@ -135,7 +134,7 @@ Ubuntu 22.04 - Dependencies required to run regression tests -.. include:: regtest_dependencies.sh +.. include:: ubuntu22p04_regtest_dependencies.sh :code: shell .. note:: Python packages are also required diff --git a/docs/source/tutorials/getting_started/regtest_dependencies.sh b/docs/source/tutorials/getting_started/regtest_dependencies.sh index 39fb7c71f..9454e026f 120000 --- a/docs/source/tutorials/getting_started/regtest_dependencies.sh +++ b/docs/source/tutorials/getting_started/regtest_dependencies.sh @@ -1 +1 @@ -../../../../.github/workflows/install_dependencies_run.sh \ No newline at end of file +../../../../.github/workflows/install_dependencies_run_ubuntu22p04.sh \ No newline at end of file diff --git a/docs/source/tutorials/getting_started/ubuntu20p04_dependencies.sh b/docs/source/tutorials/getting_started/ubuntu20p04_dependencies.sh index 326a04511..b5c829840 120000 --- a/docs/source/tutorials/getting_started/ubuntu20p04_dependencies.sh +++ b/docs/source/tutorials/getting_started/ubuntu20p04_dependencies.sh @@ -1 +1 @@ -../../../../.github/workflows/install_dependencies_build.sh \ No newline at end of file +../../../../.github/workflows/install_dependencies_build_ubuntu20p04.sh \ No newline at end of file diff --git a/docs/source/tutorials/getting_started/ubuntu20p04_regtest_dependencies.sh b/docs/source/tutorials/getting_started/ubuntu20p04_regtest_dependencies.sh new file mode 120000 index 000000000..67a110927 --- /dev/null +++ b/docs/source/tutorials/getting_started/ubuntu20p04_regtest_dependencies.sh @@ -0,0 +1 @@ +../../../../.github/workflows/install_dependencies_run_ubuntu20p04.sh \ No newline at end of file diff --git a/docs/source/tutorials/getting_started/ubuntu22p04_regtest_dependencies.sh b/docs/source/tutorials/getting_started/ubuntu22p04_regtest_dependencies.sh new file mode 120000 index 000000000..9454e026f --- /dev/null +++ b/docs/source/tutorials/getting_started/ubuntu22p04_regtest_dependencies.sh @@ -0,0 +1 @@ +../../../../.github/workflows/install_dependencies_run_ubuntu22p04.sh \ No newline at end of file diff --git a/libs/libarchopenfpga/src/arch_direct.cpp b/libs/libarchopenfpga/src/arch_direct.cpp index 33565deeb..41ed809b6 100644 --- a/libs/libarchopenfpga/src/arch_direct.cpp +++ b/libs/libarchopenfpga/src/arch_direct.cpp @@ -71,7 +71,7 @@ ArchDirectId ArchDirect::add_direct(const std::string& name) { direct_ids_.push_back(direct); names_.push_back(name); circuit_models_.push_back(CircuitModelId::INVALID()); - types_.emplace_back(NUM_DIRECT_TYPES); + types_.emplace_back(e_direct_type::NUM_DIRECT_TYPES); directions_.emplace_back(vtr::Point( NUM_DIRECT_DIRECTIONS, NUM_DIRECT_DIRECTIONS)); diff --git a/libs/libarchopenfpga/src/arch_direct.h b/libs/libarchopenfpga/src/arch_direct.h index 5508095eb..2dbe6fce8 100644 --- a/libs/libarchopenfpga/src/arch_direct.h +++ b/libs/libarchopenfpga/src/arch_direct.h @@ -14,15 +14,16 @@ * These types are supplementary to the original VPR direct connections * Here we extend to the cross-row and cross-column connections ********************************************************************/ -enum e_direct_type { - INNER_COLUMN, - INNER_ROW, +enum class e_direct_type { + INNER_COLUMN_OR_ROW, + PART_OF_CB, INTER_COLUMN, INTER_ROW, NUM_DIRECT_TYPES }; -constexpr std::array DIRECT_TYPE_STRING = { - {"inner_column", "inner_row", "inter_column", "inter_row"}}; +constexpr std::array + DIRECT_TYPE_STRING = { + {"inner_column_or_row", "part_of_cb", "inter_column", "inter_row"}}; enum e_direct_direction { POSITIVE_DIR, NEGATIVE_DIR, NUM_DIRECT_DIRECTIONS }; constexpr std::array diff --git a/libs/libarchopenfpga/src/config_protocol.cpp b/libs/libarchopenfpga/src/config_protocol.cpp index 00de87a41..d4a40833c 100644 --- a/libs/libarchopenfpga/src/config_protocol.cpp +++ b/libs/libarchopenfpga/src/config_protocol.cpp @@ -116,6 +116,11 @@ CircuitModelId ConfigProtocol::wl_memory_model() const { size_t ConfigProtocol::wl_num_banks() const { return wl_num_banks_; } +const QLMemoryBankConfigSetting* ConfigProtocol::ql_memory_bank_config_setting() + const { + return &ql_memory_bank_config_setting_; +} + /************************************************************************ * Public Mutators ***********************************************************************/ @@ -256,6 +261,10 @@ void ConfigProtocol::set_wl_num_banks(const size_t& num_banks) { wl_num_banks_ = num_banks; } +QLMemoryBankConfigSetting* ConfigProtocol::get_ql_memory_bank_config_setting() { + return &ql_memory_bank_config_setting_; +} + /************************************************************************ * Private Validators ***********************************************************************/ diff --git a/libs/libarchopenfpga/src/config_protocol.h b/libs/libarchopenfpga/src/config_protocol.h index 42ca982c4..7805d3c36 100644 --- a/libs/libarchopenfpga/src/config_protocol.h +++ b/libs/libarchopenfpga/src/config_protocol.h @@ -7,6 +7,7 @@ #include "circuit_library_fwd.h" #include "circuit_types.h" #include "openfpga_port.h" +#include "ql_memory_bank_config_setting.h" /* Data type to define the protocol through which BL/WL can be manipulated */ enum e_blwl_protocol_type { @@ -54,6 +55,9 @@ class ConfigProtocol { CircuitModelId wl_memory_model() const; size_t wl_num_banks() const; + /* QL Memory Bank Config Setting */ + const QLMemoryBankConfigSetting* ql_memory_bank_config_setting() const; + public: /* Public Mutators */ void set_type(const e_config_protocol_type& type); void set_memory_model_name(const std::string& memory_model_name); @@ -76,6 +80,9 @@ class ConfigProtocol { void set_wl_memory_model(const CircuitModelId& memory_model); void set_wl_num_banks(const size_t& num_banks); + /* QL Memory Bank Config Setting */ + QLMemoryBankConfigSetting* get_ql_memory_bank_config_setting(); + public: /* Public validators */ /* Check if internal data has any conflicts to each other. Return number of * errors detected */ @@ -131,6 +138,9 @@ class ConfigProtocol { std::string wl_memory_model_name_; CircuitModelId wl_memory_model_; size_t wl_num_banks_; + + /* QL Memory Bank Config Setting */ + QLMemoryBankConfigSetting ql_memory_bank_config_setting_; }; #endif diff --git a/libs/libarchopenfpga/src/ql_memory_bank_config_setting.cpp b/libs/libarchopenfpga/src/ql_memory_bank_config_setting.cpp new file mode 100644 index 000000000..87318adc2 --- /dev/null +++ b/libs/libarchopenfpga/src/ql_memory_bank_config_setting.cpp @@ -0,0 +1,34 @@ +#include "ql_memory_bank_config_setting.h" + +#include "openfpga_tokenizer.h" +#include "vtr_assert.h" +#include "vtr_log.h" + +/************************************************************************ + * Member functions for class QLMemoryBankConfigSetting + ***********************************************************************/ + +/************************************************************************ + * Constructors + ***********************************************************************/ +QLMemoryBankConfigSetting::QLMemoryBankConfigSetting() {} + +/************************************************************************ + * Public Accessors + ***********************************************************************/ +QLMemoryBankPBSetting QLMemoryBankConfigSetting::pb_setting( + const std::string& name) const { + if (settings_.find(name) != settings_.end()) { + return settings_.at(name); + } + return QLMemoryBankPBSetting(); +} + +/************************************************************************ + * Public Mutators + ***********************************************************************/ +void QLMemoryBankConfigSetting::add_pb_setting(const std::string& name, + uint32_t num_wl) { + VTR_ASSERT(settings_.find(name) == settings_.end()); + settings_[name] = QLMemoryBankPBSetting(num_wl); +} diff --git a/libs/libarchopenfpga/src/ql_memory_bank_config_setting.h b/libs/libarchopenfpga/src/ql_memory_bank_config_setting.h new file mode 100644 index 000000000..82dcd4989 --- /dev/null +++ b/libs/libarchopenfpga/src/ql_memory_bank_config_setting.h @@ -0,0 +1,30 @@ +#ifndef QL_MEMORY_BANK_CONFIG_SETTING_H +#define QL_MEMORY_BANK_CONFIG_SETTING_H + +#include +#include +#include + +struct QLMemoryBankPBSetting { + QLMemoryBankPBSetting(uint32_t n = 0) : num_wl(n) {} + uint32_t num_wl = 0; +}; + +/******************************************************************** + * A data structure to store QL Memory Bank configuration setting + *******************************************************************/ +class QLMemoryBankConfigSetting { + public: /* Constructors */ + QLMemoryBankConfigSetting(); + + public: /* Public Accessors */ + QLMemoryBankPBSetting pb_setting(const std::string& name) const; + + public: /* Public Mutators */ + void add_pb_setting(const std::string& name, uint32_t num_wl); + + private: /* Internal data */ + std::map settings_; +}; + +#endif diff --git a/libs/libarchopenfpga/src/read_xml_config_protocol.cpp b/libs/libarchopenfpga/src/read_xml_config_protocol.cpp index b51d9f237..d93ff131e 100644 --- a/libs/libarchopenfpga/src/read_xml_config_protocol.cpp +++ b/libs/libarchopenfpga/src/read_xml_config_protocol.cpp @@ -249,6 +249,32 @@ static void read_xml_config_organization(pugi::xml_node& xml_config_orgz, } } +/******************************************************************** + * Parse XML codes about to + *QLMemoryBankConfigSetting + *******************************************************************/ +static void read_xml_ql_memory_bank_config_setting( + QLMemoryBankConfigSetting* setting, pugi::xml_node& Node, + const pugiutil::loc_data& loc_data) { + /* Parse configuration protocol root node */ + pugi::xml_node config_setting = + get_single_child(Node, "ql_memory_bank_config_setting", loc_data, + pugiutil::ReqOpt::OPTIONAL); + + if (config_setting) { + /* Add to ql_memory_bank_config_setting_ */ + for (pugi::xml_node xml_child : config_setting.children()) { + if (xml_child.name() != std::string("pb_type")) { + bad_tag(xml_child, loc_data, config_setting, {"pb_type"}); + } + const std::string& name_attr = + get_attribute(xml_child, "name", loc_data).as_string(); + uint32_t num_wl = get_attribute(xml_child, "num_wl", loc_data).as_uint(); + setting->add_pb_setting(name_attr, num_wl); + } + } +} + /******************************************************************** * Parse XML codes about to an object of ConfigProtocol *******************************************************************/ @@ -264,5 +290,14 @@ ConfigProtocol read_xml_config_protocol(pugi::xml_node& Node, get_single_child(xml_config, "organization", loc_data); read_xml_config_organization(xml_config_orgz, loc_data, config_protocol); + /* Parse QL Memory Bank configuration setting */ + if (config_protocol.type() == CONFIG_MEM_QL_MEMORY_BANK && + config_protocol.bl_protocol_type() == BLWL_PROTOCOL_FLATTEN && + config_protocol.wl_protocol_type() == BLWL_PROTOCOL_FLATTEN) { + read_xml_ql_memory_bank_config_setting( + config_protocol.get_ql_memory_bank_config_setting(), xml_config, + loc_data); + } + return config_protocol; } diff --git a/libs/libarchopenfpga/src/read_xml_routing_circuit.cpp b/libs/libarchopenfpga/src/read_xml_routing_circuit.cpp index 1ac6675b8..0a48531c0 100644 --- a/libs/libarchopenfpga/src/read_xml_routing_circuit.cpp +++ b/libs/libarchopenfpga/src/read_xml_routing_circuit.cpp @@ -11,6 +11,7 @@ /* Headers from vtr util library */ #include "vtr_assert.h" +#include "vtr_log.h" /* Headers from libarchfpga */ #include "arch_error.h" @@ -198,15 +199,20 @@ std::map read_xml_routing_segment_circuit( * Convert string to the enumerate of direct type *******************************************************************/ static e_direct_type string_to_direct_type(const std::string& type_string) { - if (std::string("column") == type_string) { - return INTER_COLUMN; + if (std::string("part_of_cb") == type_string) { + return e_direct_type::PART_OF_CB; + } + if (std::string("inner_column_or_row") == type_string) { + return e_direct_type::INNER_COLUMN_OR_ROW; + } + if (std::string("inter_column") == type_string) { + return e_direct_type::INTER_COLUMN; + } + if (std::string("inter_row") == type_string) { + return e_direct_type::INTER_ROW; } - if (std::string("row") == type_string) { - return INTER_ROW; - } - - return NUM_DIRECT_TYPES; + return e_direct_type::NUM_DIRECT_TYPES; } /******************************************************************** @@ -255,13 +261,6 @@ ArchDirect read_xml_direct_circuit(pugi::xml_node& Node, std::string direct_name = get_attribute(xml_direct, "name", loc_data).as_string(); - /* Get the routing segment circuit model name */ - std::string direct_model_name = - get_attribute(xml_direct, "circuit_model_name", loc_data).as_string(); - - CircuitModelId direct_model = find_routing_circuit_model( - xml_direct, loc_data, circuit_lib, direct_model_name, CIRCUIT_MODEL_WIRE); - /* Add to the Arch direct database */ ArchDirectId direct = arch_direct.add_direct(direct_name); if (false == arch_direct.valid_direct_id(direct)) { @@ -269,28 +268,48 @@ ArchDirect read_xml_direct_circuit(pugi::xml_node& Node, "Direct name '%s' has been defined more than once!\n", direct_name.c_str()); } - arch_direct.set_circuit_model(direct, direct_model); /* Add more information*/ std::string direct_type_name = get_attribute(xml_direct, "type", loc_data, pugiutil::ReqOpt::OPTIONAL) - .as_string("none"); - /* If not defined, we go to the next */ - if (std::string("none") == direct_type_name) { - continue; - } + .as_string( + DIRECT_TYPE_STRING[size_t(e_direct_type::INNER_COLUMN_OR_ROW)]); e_direct_type direct_type = string_to_direct_type(direct_type_name); - if (NUM_DIRECT_TYPES == direct_type) { + if (e_direct_type::NUM_DIRECT_TYPES == direct_type) { archfpga_throw( loc_data.filename_c_str(), loc_data.line(xml_direct), - "Direct type '%s' is not support! Acceptable values are [column|row]\n", + "Direct type '%s' is not support! Acceptable values are " + "[inner_column_or_row|part_of_cb|inter_column|inter_row]\n", direct_type_name.c_str()); } arch_direct.set_type(direct, direct_type); + /* Get the routing segment circuit model name */ + std::string direct_model_name = + get_attribute(xml_direct, "circuit_model_name", loc_data).as_string(); + + /* If a direct connection is part of a connection block, the circuit model + * should be a MUX */ + e_circuit_model_type expected_circuit_model_type = CIRCUIT_MODEL_WIRE; + if (arch_direct.type(direct) == e_direct_type::PART_OF_CB) { + VTR_LOG("Direct '%s' will modelled as part of a connection block.\n", + direct_name.c_str()); + expected_circuit_model_type = CIRCUIT_MODEL_MUX; + } + CircuitModelId direct_model = find_routing_circuit_model( + xml_direct, loc_data, circuit_lib, direct_model_name, + expected_circuit_model_type); + arch_direct.set_circuit_model(direct, direct_model); + + /* The following syntax is only available for inter-column/row */ + if (arch_direct.type(direct) != e_direct_type::INTER_COLUMN && + arch_direct.type(direct) != e_direct_type::INTER_ROW) { + continue; + } + std::string x_dir_name = get_attribute(xml_direct, "x_dir", loc_data).as_string(); std::string y_dir_name = diff --git a/libs/libarchopenfpga/src/write_xml_routing_circuit.cpp b/libs/libarchopenfpga/src/write_xml_routing_circuit.cpp index 74eb8beac..691bfff6d 100644 --- a/libs/libarchopenfpga/src/write_xml_routing_circuit.cpp +++ b/libs/libarchopenfpga/src/write_xml_routing_circuit.cpp @@ -57,7 +57,7 @@ static void write_xml_direct_component_circuit( fp, "circuit_model_name", circuit_lib.model_name(arch_direct.circuit_model(direct_id)).c_str()); write_xml_attribute(fp, "type", - DIRECT_TYPE_STRING[arch_direct.type(direct_id)]); + DIRECT_TYPE_STRING[size_t(arch_direct.type(direct_id))]); write_xml_attribute(fp, "x_dir", DIRECT_DIRECTION_STRING[arch_direct.x_dir(direct_id)]); write_xml_attribute(fp, "y_dir", diff --git a/libs/libnamemanager/src/base/io_name_map.h b/libs/libnamemanager/src/base/io_name_map.h index b1f107a10..5e4370b3b 100644 --- a/libs/libnamemanager/src/base/io_name_map.h +++ b/libs/libnamemanager/src/base/io_name_map.h @@ -4,7 +4,10 @@ /******************************************************************** * Include header files required by the data structure definition *******************************************************************/ +#include #include +#include +#include #include "openfpga_port.h" diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index 3a904aefd..291d9cd9b 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -398,6 +398,9 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, temp_ipin_rr_nodes.clear(); } + /* Build OPIN node lists for connection blocks */ + rr_gsb.build_cb_opin_nodes(vpr_device_ctx.rr_graph); + return rr_gsb; } @@ -701,14 +704,26 @@ static void annotate_direct_circuit_models( } /* Check the circuit model type */ - if (CIRCUIT_MODEL_WIRE != - openfpga_arch.circuit_lib.model_type(circuit_model)) { + if (openfpga_arch.arch_direct.type(direct_id) != + e_direct_type::PART_OF_CB && + CIRCUIT_MODEL_WIRE != + openfpga_arch.circuit_lib.model_type(circuit_model)) { VTR_LOG_ERROR( "Require circuit model type '%s' for a direct connection '%s'!\nPlease " "check your OpenFPGA architecture XML!\n", CIRCUIT_MODEL_TYPE_STRING[CIRCUIT_MODEL_WIRE], direct_name.c_str()); exit(1); } + if (openfpga_arch.arch_direct.type(direct_id) == + e_direct_type::PART_OF_CB && + CIRCUIT_MODEL_MUX != + openfpga_arch.circuit_lib.model_type(circuit_model)) { + VTR_LOG_ERROR( + "Require circuit model type '%s' for a direct connection '%s'!\nPlease " + "check your OpenFPGA architecture XML!\n", + CIRCUIT_MODEL_TYPE_STRING[CIRCUIT_MODEL_MUX], direct_name.c_str()); + exit(1); + } /* Now update the device annotation */ vpr_device_annotation.add_direct_annotation(idirect, direct_id); diff --git a/openfpga/src/annotation/write_xml_device_rr_gsb.cpp b/openfpga/src/annotation/write_xml_device_rr_gsb.cpp index 89b31d9c6..1dd447d25 100644 --- a/openfpga/src/annotation/write_xml_device_rr_gsb.cpp +++ b/openfpga/src/annotation/write_xml_device_rr_gsb.cpp @@ -166,7 +166,7 @@ static void write_rr_gsb_chan_connection_to_xml( fp << "\" node_id=\"" << size_t(driver_rr_node) << "\" grid_side=\"" << grid_side.to_string() << "\" sb_module_pin_name=\"" << generate_sb_module_grid_port_name( - gsb_side, driver_node_side, vpr_device_grid, + gsb_side, grid_side.get_side(), vpr_device_grid, vpr_device_annotation, rr_graph, driver_rr_node); } fp << "\"/>" << std::endl; diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index 63e623398..b36903a22 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -23,6 +23,7 @@ #include "rename_modules.h" #include "vtr_log.h" #include "vtr_time.h" +#include "write_xml_fabric_pin_physical_location.h" #include "write_xml_module_name_map.h" /* begin namespace openfpga */ @@ -269,6 +270,8 @@ template int write_fabric_hierarchy_template(const T& openfpga_ctx, const Command& cmd, const CommandContext& cmd_context) { CommandOptionId opt_verbose = cmd.option("verbose"); + CommandOptionId opt_exclude_empty_modules = + cmd.option("exclude_empty_modules"); /* Check the option '--file' is enabled or not * Actually, it must be enabled as the shell interface will check @@ -278,6 +281,19 @@ int write_fabric_hierarchy_template(const T& openfpga_ctx, const Command& cmd, VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file)); VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty()); + CommandOptionId opt_module = cmd.option("module"); + std::string root_module = + openfpga_ctx.module_name_map().name(generate_fpga_top_module_name()); + if (true == cmd_context.option_enable(cmd, opt_module)) { + root_module = cmd_context.option_value(cmd, opt_module); + } + + CommandOptionId opt_filter = cmd.option("filter"); + std::string filter("*"); + if (true == cmd_context.option_enable(cmd, opt_filter)) { + filter = cmd_context.option_value(cmd, opt_filter); + } + /* Default depth requirement, will not stop until the leaf */ int depth = -1; CommandOptionId opt_depth = cmd.option("depth"); @@ -296,7 +312,9 @@ int write_fabric_hierarchy_template(const T& openfpga_ctx, const Command& cmd, /* Write hierarchy to a file */ return write_fabric_hierarchy_to_text_file( openfpga_ctx.module_graph(), openfpga_ctx.module_name_map(), hie_file_name, - size_t(depth), cmd_context.option_enable(cmd, opt_verbose)); + root_module, filter, size_t(depth), + cmd_context.option_enable(cmd, opt_exclude_empty_modules), + cmd_context.option_enable(cmd, opt_verbose)); } /******************************************************************** @@ -419,6 +437,41 @@ int write_module_naming_rules_template(const T& openfpga_ctx, cmd_context.option_enable(cmd, opt_verbose)); } +/******************************************************************** + * Write fabric pin physical location to a file + *******************************************************************/ +template +int write_fabric_pin_physical_location_template( + const T& openfpga_ctx, const Command& cmd, + const CommandContext& cmd_context) { + CommandOptionId opt_verbose = cmd.option("verbose"); + CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp"); + CommandOptionId opt_show_invalid_side = cmd.option("show_invalid_side"); + + /* Check the option '--file' is enabled or not + * Actually, it must be enabled as the shell interface will check + * before reaching this fuction + */ + CommandOptionId opt_file = cmd.option("file"); + VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file)); + VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty()); + + std::string file_name = cmd_context.option_value(cmd, opt_file); + + std::string module_name("*"); /* Use a wildcard for everything */ + CommandOptionId opt_module = cmd.option("module"); + if (true == cmd_context.option_enable(cmd, opt_module)) { + module_name = cmd_context.option_value(cmd, opt_module); + } + + /* Write hierarchy to a file */ + return write_xml_fabric_pin_physical_location( + file_name.c_str(), module_name, openfpga_ctx.module_graph(), + cmd_context.option_enable(cmd, opt_show_invalid_side), + !cmd_context.option_enable(cmd, opt_no_time_stamp), + cmd_context.option_enable(cmd, opt_verbose)); +} + } /* end namespace openfpga */ #endif diff --git a/openfpga/src/base/openfpga_link_arch_template.h b/openfpga/src/base/openfpga_link_arch_template.h index dc2e04ac4..cb16de224 100644 --- a/openfpga/src/base/openfpga_link_arch_template.h +++ b/openfpga/src/base/openfpga_link_arch_template.h @@ -86,6 +86,9 @@ int link_arch_template(T& openfpga_ctx, const Command& cmd, openfpga_ctx.mutable_vpr_routing_annotation().init( g_vpr_ctx.device().rr_graph); + // Incase the incoming edges are not built. This may happen when loading + // rr_graph from an external file + g_vpr_ctx.mutable_device().rr_graph_builder.build_in_edges(); annotate_vpr_rr_node_nets(g_vpr_ctx.device(), g_vpr_ctx.clustering(), g_vpr_ctx.routing(), openfpga_ctx.mutable_vpr_routing_annotation(), @@ -105,7 +108,6 @@ int link_arch_template(T& openfpga_ctx, const Command& cmd, } /* Build incoming edges as VPR only builds fan-out edges for each node */ - g_vpr_ctx.mutable_device().rr_graph_builder.build_in_edges(); VTR_LOG("Built %ld incoming edges for routing resource graph\n", g_vpr_ctx.device().rr_graph.in_edges_count()); VTR_ASSERT(g_vpr_ctx.device().rr_graph.validate_in_edges()); diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp index b80c3ba36..c76273935 100644 --- a/openfpga/src/base/openfpga_naming.cpp +++ b/openfpga/src/base/openfpga_naming.cpp @@ -413,6 +413,35 @@ std::string generate_sb_module_track_port_name(const t_rr_type& chan_type, return port_name; } +/********************************************************************* + * Get the physical side for a routing track in a Connection Block module + * Upper_location: specify if an upper/lower prefix to be added. + * The location indicates where the bus port should be + * placed on the perimeter of the connection block + * - For X-directional CB: + * - upper is the left side + * - lower is the right side + * - For Y-directional CB: + * - upper is the bottom side + * - lower is the top side + *********************************************************************/ +e_side get_cb_module_track_port_side(const t_rr_type& chan_type, + const bool& upper_location) { + /* Channel must be either CHANX or CHANY */ + VTR_ASSERT((CHANX == chan_type) || (CHANY == chan_type)); + + /* Create a map between chan_type and module_prefix */ + std::map> port_side_map; + /* TODO: use a constexpr string to replace the fixed name? */ + /* IMPORTANT: This part must be consistent with the mapping in the + * generate_cb_module_track_port_name() !!! */ + port_side_map[CHANX][true] = LEFT; + port_side_map[CHANX][false] = RIGHT; + port_side_map[CHANY][true] = BOTTOM; + port_side_map[CHANY][false] = TOP; + return port_side_map[chan_type][upper_location]; +} + /********************************************************************* * Generate the port name for a routing track in a Connection Block module * This function is created to ease the PnR for each unique routing module diff --git a/openfpga/src/base/openfpga_naming.h b/openfpga/src/base/openfpga_naming.h index 378a2836a..bbad6e510 100644 --- a/openfpga/src/base/openfpga_naming.h +++ b/openfpga/src/base/openfpga_naming.h @@ -97,6 +97,9 @@ std::string generate_sb_module_track_port_name(const t_rr_type& chan_type, const e_side& module_side, const PORTS& port_direction); +e_side get_cb_module_track_port_side(const t_rr_type& chan_type, + const bool& upper_location); + std::string generate_cb_module_track_port_name(const t_rr_type& chan_type, const PORTS& port_direction, const bool& upper_location); diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h index 96d8e3e3b..3d178ee17 100644 --- a/openfpga/src/base/openfpga_setup_command_template.h +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -461,12 +461,29 @@ ShellCommandId add_write_fabric_hierarchy_command_template( shell_cmd.set_option_short_name(opt_file, "f"); shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + /* Add an option '--module' */ + CommandOptionId opt_module = shell_cmd.add_option( + "module", false, + "Specify the root module name(s) which should be considered. By default, " + "it is fpga_top. Regular expression is supported"); + shell_cmd.set_option_require_value(opt_module, openfpga::OPT_STRING); + CommandOptionId opt_filter = + shell_cmd.add_option("filter", false, + "Specify the filter which allows user to select " + "modules to appear under each root module tree. By " + "default, it is *. Regular expression is supported"); + shell_cmd.set_option_require_value(opt_filter, openfpga::OPT_STRING); + /* Add an option '--depth' */ CommandOptionId opt_depth = shell_cmd.add_option( "depth", false, "Specify the depth of hierarchy to which the writer should stop"); shell_cmd.set_option_require_value(opt_depth, openfpga::OPT_INT); + shell_cmd.add_option("exclude_empty_modules", false, + "Exclude modules with no qualified children (match the " + "names defined through filter) from the output file"); + /* Add an option '--verbose' */ shell_cmd.add_option("verbose", false, "Show verbose outputs"); @@ -858,6 +875,55 @@ ShellCommandId add_write_module_naming_rules_command_template( return shell_cmd_id; } +/******************************************************************** + * - Add a command to Shell environment: write_pin_physical_location + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_write_fabric_pin_physical_location_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("write_fabric_pin_physical_location"); + /* Add an option '--file' in short '-f'*/ + CommandOptionId opt_file = shell_cmd.add_option( + "file", true, + "file path to the XML file that contains pin physical location"); + shell_cmd.set_option_short_name(opt_file, "f"); + shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + + /* Add an option '--module'*/ + CommandOptionId opt_module = shell_cmd.add_option( + "module", false, + "specify the module whose pin physical location should be outputted"); + shell_cmd.set_option_require_value(opt_module, openfpga::OPT_STRING); + + /* Add an option '--no_time_stamp' */ + shell_cmd.add_option("no_time_stamp", false, + "Do not print time stamp in output files"); + + shell_cmd.add_option( + "show_invalid_side", false, + "Include pins with invalid sides in output files. Recommended for " + "debugging as the output file may include a lot of useless information"); + + shell_cmd.add_option("verbose", false, "Show verbose outputs"); + + /* Add command to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, + "Output the pin physical location of an FPGA fabric to a given file", + hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_const_execute_function( + shell_cmd_id, write_fabric_pin_physical_location_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + template void add_setup_command_templates(openfpga::Shell& shell, const bool& hidden = false) { @@ -1098,6 +1164,17 @@ void add_setup_command_templates(openfpga::Shell& shell, add_write_module_naming_rules_command_template( shell, openfpga_setup_cmd_class, cmd_dependency_write_module_naming_rules, hidden); + + /******************************** + * Command 'write_fabric_pin_physical_location' + */ + /* The command should NOT be executed before 'build_fabric' */ + std::vector cmd_dependency_write_fabric_pin_physical_location; + cmd_dependency_write_fabric_pin_physical_location.push_back( + build_fabric_cmd_id); + add_write_fabric_pin_physical_location_command_template( + shell, openfpga_setup_cmd_class, + cmd_dependency_write_fabric_pin_physical_location, hidden); } } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_verilog_command_template.h b/openfpga/src/base/openfpga_verilog_command_template.h index 000c7d564..5fa7d6171 100644 --- a/openfpga/src/base/openfpga_verilog_command_template.h +++ b/openfpga/src/base/openfpga_verilog_command_template.h @@ -250,6 +250,10 @@ ShellCommandId add_write_preconfigured_fabric_wrapper_command_template( shell_cmd.add_option("include_signal_init", false, "initialize all the signals in verilog testbenches"); + /* add an option '--dump_waveform' */ + shell_cmd.add_option("dump_waveform", false, + "add waveform output commands to the output file"); + /* Add an option '--no_time_stamp' */ shell_cmd.add_option("no_time_stamp", false, "Do not print a time stamp in the output files"); diff --git a/openfpga/src/base/openfpga_verilog_template.h b/openfpga/src/base/openfpga_verilog_template.h index 71e97ccc8..2c9656eaa 100644 --- a/openfpga/src/base/openfpga_verilog_template.h +++ b/openfpga/src/base/openfpga_verilog_template.h @@ -169,6 +169,7 @@ int write_preconfigured_fabric_wrapper_template( CommandOptionId opt_include_signal_init = cmd.option("include_signal_init"); CommandOptionId opt_embed_bitstream = cmd.option("embed_bitstream"); CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp"); + CommandOptionId opt_dump_waveform = cmd.option("dump_waveform"); CommandOptionId opt_verbose = cmd.option("verbose"); /* This is an intermediate data structure which is designed to modularize the @@ -184,6 +185,7 @@ int write_preconfigured_fabric_wrapper_template( options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); options.set_include_signal_init( cmd_context.option_enable(cmd, opt_include_signal_init)); + options.set_dump_waveform(cmd_context.option_enable(cmd, opt_dump_waveform)); options.set_print_formal_verification_top_netlist(true); if (true == cmd_context.option_enable(cmd, opt_dut_module)) { diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp index 012e3a529..757171c78 100644 --- a/openfpga/src/fabric/build_device_module.cpp +++ b/openfpga/src/fabric/build_device_module.cpp @@ -88,8 +88,9 @@ int build_device_module_graph( module_manager, decoder_lib, vpr_device_ctx, openfpga_ctx.vpr_device_annotation(), openfpga_ctx.arch().circuit_lib, openfpga_ctx.mux_lib(), openfpga_ctx.arch().tile_annotations, - openfpga_ctx.arch().config_protocol.type(), sram_model, duplicate_grid_pin, - group_config_block, verbose); + openfpga_ctx.arch().config_protocol.type(), sram_model, + openfpga_ctx.arch().config_protocol.ql_memory_bank_config_setting(), + duplicate_grid_pin, group_config_block, verbose); if (CMD_EXEC_FATAL_ERROR == status) { return status; } diff --git a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp index cae215259..32304bdc7 100644 --- a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp +++ b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp @@ -123,8 +123,10 @@ void add_grid_module_duplicated_pb_type_ports( } BasicPort grid_port(port_name, 0, 0); /* Add the port to the module */ - module_manager.add_port(grid_module, grid_port, - pin_type2type_map[pin_class_type]); + ModulePortId grid_port_id = module_manager.add_port( + grid_module, grid_port, pin_type2type_map[pin_class_type]); + /* Set port side */ + module_manager.set_port_side(grid_module, grid_port_id, side); } else { /* For each DRIVER pin, we create two copies. * One with a postfix of upper, indicating it is located on the @@ -136,15 +138,19 @@ void add_grid_module_duplicated_pb_type_ports( iwidth, iheight, subtile_index, side, pin_info, true); BasicPort grid_upper_port(upper_port_name, 0, 0); /* Add the port to the module */ - module_manager.add_port(grid_module, grid_upper_port, - pin_type2type_map[pin_class_type]); + ModulePortId grid_upper_port_id = module_manager.add_port( + grid_module, grid_upper_port, pin_type2type_map[pin_class_type]); + /* Set port side */ + module_manager.set_port_side(grid_module, grid_upper_port_id, side); std::string lower_port_name = generate_grid_duplicated_port_name( iwidth, iheight, subtile_index, side, pin_info, false); BasicPort grid_lower_port(lower_port_name, 0, 0); /* Add the port to the module */ - module_manager.add_port(grid_module, grid_lower_port, - pin_type2type_map[pin_class_type]); + ModulePortId grid_lower_port_id = module_manager.add_port( + grid_module, grid_lower_port, pin_type2type_map[pin_class_type]); + /* Set port side */ + module_manager.set_port_side(grid_module, grid_lower_port_id, side); } } } diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp index 94b9d884c..eaa24246b 100644 --- a/openfpga/src/fabric/build_grid_modules.cpp +++ b/openfpga/src/fabric/build_grid_modules.cpp @@ -103,8 +103,10 @@ static void add_grid_module_pb_type_ports( } BasicPort grid_port(port_name, 0, 0); /* Add the port to the module */ - module_manager.add_port(grid_module, grid_port, - pin_type2type_map[pin_class_type]); + ModulePortId grid_port_id = module_manager.add_port( + grid_module, grid_port, pin_type2type_map[pin_class_type]); + /* Set port side */ + module_manager.set_port_side(grid_module, grid_port_id, side); } } } @@ -1164,6 +1166,7 @@ static int build_physical_tile_module( const e_config_protocol_type& sram_orgz_type, const CircuitModelId& sram_model, t_physical_tile_type_ptr phy_block_type, const TileAnnotation& tile_annotation, const e_side& border_side, + const QLMemoryBankConfigSetting* ql_memory_bank_config_setting, const bool& duplicate_grid_pin, const bool& group_config_block, const bool& verbose) { int status = CMD_EXEC_SUCCESS; @@ -1332,9 +1335,10 @@ static int build_physical_tile_module( module_manager, grid_module, circuit_lib, sram_model, sram_orgz_type, config_child_type); if (0 < module_num_config_bits) { - add_pb_sram_ports_to_module_manager(module_manager, grid_module, - circuit_lib, sram_model, sram_orgz_type, - module_num_config_bits); + add_pb_sram_ports_to_module_manager( + module_manager, grid_module, circuit_lib, sram_model, sram_orgz_type, + module_num_config_bits, + ql_memory_bank_config_setting->pb_setting(phy_block_type->name).num_wl); } /* Add module nets to connect memory cells inside @@ -1372,8 +1376,10 @@ int build_grid_modules( const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const TileAnnotation& tile_annotation, const e_config_protocol_type& sram_orgz_type, - const CircuitModelId& sram_model, const bool& duplicate_grid_pin, - const bool& group_config_block, const bool& verbose) { + const CircuitModelId& sram_model, + const QLMemoryBankConfigSetting* ql_memory_bank_config_setting, + const bool& duplicate_grid_pin, const bool& group_config_block, + const bool& verbose) { /* Start time count */ vtr::ScopedStartFinishTimer timer("Build grid modules"); @@ -1429,7 +1435,8 @@ int build_grid_modules( status = build_physical_tile_module( module_manager, decoder_lib, device_annotation, circuit_lib, sram_orgz_type, sram_model, &physical_tile, tile_annotation, - io_type_side, duplicate_grid_pin, group_config_block, verbose); + io_type_side, ql_memory_bank_config_setting, duplicate_grid_pin, + group_config_block, verbose); if (status != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } @@ -1439,7 +1446,8 @@ int build_grid_modules( status = build_physical_tile_module( module_manager, decoder_lib, device_annotation, circuit_lib, sram_orgz_type, sram_model, &physical_tile, tile_annotation, NUM_SIDES, - duplicate_grid_pin, group_config_block, verbose); + ql_memory_bank_config_setting, duplicate_grid_pin, group_config_block, + verbose); if (status != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } diff --git a/openfpga/src/fabric/build_grid_modules.h b/openfpga/src/fabric/build_grid_modules.h index 996b9bda2..523b545ea 100644 --- a/openfpga/src/fabric/build_grid_modules.h +++ b/openfpga/src/fabric/build_grid_modules.h @@ -7,6 +7,7 @@ #include "decoder_library.h" #include "module_manager.h" #include "mux_library.h" +#include "ql_memory_bank_config_setting.h" #include "tile_annotation.h" #include "vpr_context.h" #include "vpr_device_annotation.h" @@ -24,8 +25,10 @@ int build_grid_modules( const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const TileAnnotation& tile_annotation, const e_config_protocol_type& sram_orgz_type, - const CircuitModelId& sram_model, const bool& duplicate_grid_pin, - const bool& group_config_block, const bool& verbose); + const CircuitModelId& sram_model, + const QLMemoryBankConfigSetting* ql_memory_bank_config_setting, + const bool& duplicate_grid_pin, const bool& group_config_block, + const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_routing_module_utils.cpp b/openfpga/src/fabric/build_routing_module_utils.cpp index e1f3db9ad..b8f9b4c0d 100644 --- a/openfpga/src/fabric/build_routing_module_utils.cpp +++ b/openfpga/src/fabric/build_routing_module_utils.cpp @@ -320,19 +320,58 @@ ModulePortId find_connection_block_module_ipin_port( return ipin_port_id; } +/********************************************************************* + * Generate a port for a connection block + ********************************************************************/ +ModulePortId find_connection_block_module_opin_port( + const ModuleManager& module_manager, const ModuleId& cb_module, + const DeviceGrid& grids, const VprDeviceAnnotation& vpr_device_annotation, + const RRGraphView& rr_graph, const RRGSB& rr_gsb, + const RRNodeId& src_rr_node) { + /* Ensure the src_rr_node is an input pin of a CLB */ + VTR_ASSERT(OPIN == rr_graph.node_type(src_rr_node)); + /* Search all the sides of a SB, see this drive_rr_node is an INPUT of this SB + */ + enum e_side cb_opin_side = NUM_SIDES; + int cb_opin_index = -1; + rr_gsb.get_node_side_and_index(rr_graph, src_rr_node, IN_PORT, cb_opin_side, + cb_opin_index); + /* We need to be sure that drive_rr_node is part of the CB */ + VTR_ASSERT((-1 != cb_opin_index) && (NUM_SIDES != cb_opin_side)); + std::string port_name = generate_cb_module_grid_port_name( + cb_opin_side, grids, vpr_device_annotation, rr_graph, + rr_gsb.get_opin_node(cb_opin_side, cb_opin_index)); + + /* Must find a valid port id in the Switch Block module */ + ModulePortId opin_port_id = + module_manager.find_module_port(cb_module, port_name); + VTR_ASSERT(true == + module_manager.valid_module_port_id(cb_module, opin_port_id)); + return opin_port_id; +} + /********************************************************************* * Generate a list of routing track middle output ports * for routing multiplexer inside the connection block ********************************************************************/ std::vector find_connection_block_module_input_ports( const ModuleManager& module_manager, const ModuleId& cb_module, + const DeviceGrid& grids, const VprDeviceAnnotation& vpr_device_annotation, const RRGraphView& rr_graph, const RRGSB& rr_gsb, const t_rr_type& cb_type, const std::vector& input_rr_nodes) { std::vector input_ports; for (auto input_rr_node : input_rr_nodes) { - input_ports.push_back(find_connection_block_module_chan_port( - module_manager, cb_module, rr_graph, rr_gsb, cb_type, input_rr_node)); + if (OPIN == rr_graph.node_type(input_rr_node)) { + input_ports.push_back(ModulePinInfo( + find_connection_block_module_opin_port(module_manager, cb_module, grids, + vpr_device_annotation, rr_graph, + rr_gsb, input_rr_node), + 0)); + } else { + input_ports.push_back(find_connection_block_module_chan_port( + module_manager, cb_module, rr_graph, rr_gsb, cb_type, input_rr_node)); + } } return input_ports; diff --git a/openfpga/src/fabric/build_routing_module_utils.h b/openfpga/src/fabric/build_routing_module_utils.h index 8c3907dfa..f2995f27e 100644 --- a/openfpga/src/fabric/build_routing_module_utils.h +++ b/openfpga/src/fabric/build_routing_module_utils.h @@ -62,8 +62,15 @@ ModulePortId find_connection_block_module_ipin_port( const RRGraphView& rr_graph, const RRGSB& rr_gsb, const RRNodeId& src_rr_node); +ModulePortId find_connection_block_module_opin_port( + const ModuleManager& module_manager, const ModuleId& cb_module, + const DeviceGrid& grids, const VprDeviceAnnotation& vpr_device_annotation, + const RRGraphView& rr_graph, const RRGSB& rr_gsb, + const RRNodeId& src_rr_node); + std::vector find_connection_block_module_input_ports( const ModuleManager& module_manager, const ModuleId& cb_module, + const DeviceGrid& grids, const VprDeviceAnnotation& vpr_device_annotation, const RRGraphView& rr_graph, const RRGSB& rr_gsb, const t_rr_type& cb_type, const std::vector& input_rr_nodes); diff --git a/openfpga/src/fabric/build_routing_modules.cpp b/openfpga/src/fabric/build_routing_modules.cpp index d552a611c..6b7cf92a1 100644 --- a/openfpga/src/fabric/build_routing_modules.cpp +++ b/openfpga/src/fabric/build_routing_modules.cpp @@ -435,6 +435,9 @@ static void build_switch_block_module( BasicPort chan_input_port(chan_input_port_name, chan_input_port_size); ModulePortId chan_input_port_id = module_manager.add_port( sb_module, chan_input_port, ModuleManager::MODULE_INPUT_PORT); + /* Add side to the port */ + module_manager.set_port_side(sb_module, chan_input_port_id, + side_manager.get_side()); /* Cache the input net */ for (const size_t& pin : chan_input_port.pins()) { @@ -446,8 +449,11 @@ static void build_switch_block_module( std::string chan_output_port_name = generate_sb_module_track_port_name( chan_type, side_manager.get_side(), OUT_PORT); BasicPort chan_output_port(chan_output_port_name, chan_output_port_size); - module_manager.add_port(sb_module, chan_output_port, - ModuleManager::MODULE_OUTPUT_PORT); + ModulePortId chan_output_port_id = module_manager.add_port( + sb_module, chan_output_port, ModuleManager::MODULE_OUTPUT_PORT); + /* Add side to the port */ + module_manager.set_port_side(sb_module, chan_output_port_id, + side_manager.get_side()); } /* Dump OPINs of adjacent CLBs */ @@ -468,6 +474,9 @@ static void build_switch_block_module( /* Grid outputs are inputs of switch blocks */ ModulePortId input_port_id = module_manager.add_port( sb_module, module_port, ModuleManager::MODULE_INPUT_PORT); + /* Add side to the port */ + module_manager.set_port_side(sb_module, input_port_id, + side_manager.get_side()); /* Cache the input net */ ModuleNetId net = create_module_source_pin_net( @@ -682,8 +691,9 @@ static void build_connection_block_mux_module( /* TODO: Generate input ports that are wired to the input bus of the routing * multiplexer */ std::vector cb_input_port_ids = - find_connection_block_module_input_ports( - module_manager, cb_module, rr_graph, rr_gsb, cb_type, driver_rr_nodes); + find_connection_block_module_input_ports(module_manager, cb_module, grids, + device_annotation, rr_graph, + rr_gsb, cb_type, driver_rr_nodes); /* Link input bus port to Switch Block inputs */ std::vector mux_model_input_ports = @@ -925,6 +935,9 @@ static void build_connection_block_module( rr_gsb.get_cb_chan_width(cb_type) / 2); ModulePortId chan_upper_input_port_id = module_manager.add_port( cb_module, chan_upper_input_port, ModuleManager::MODULE_INPUT_PORT); + /* Add side to the port */ + module_manager.set_port_side(cb_module, chan_upper_input_port_id, + get_cb_module_track_port_side(cb_type, true)); /* Lower input port: W/2 == 1 tracks */ std::string chan_lower_input_port_name = @@ -933,6 +946,9 @@ static void build_connection_block_module( rr_gsb.get_cb_chan_width(cb_type) / 2); ModulePortId chan_lower_input_port_id = module_manager.add_port( cb_module, chan_lower_input_port, ModuleManager::MODULE_INPUT_PORT); + /* Add side to the port */ + module_manager.set_port_side(cb_module, chan_lower_input_port_id, + get_cb_module_track_port_side(cb_type, false)); /* Upper output port: W/2 == 0 tracks */ std::string chan_upper_output_port_name = @@ -941,6 +957,9 @@ static void build_connection_block_module( rr_gsb.get_cb_chan_width(cb_type) / 2); ModulePortId chan_upper_output_port_id = module_manager.add_port( cb_module, chan_upper_output_port, ModuleManager::MODULE_OUTPUT_PORT); + /* Add side to the port */ + module_manager.set_port_side(cb_module, chan_upper_output_port_id, + get_cb_module_track_port_side(cb_type, true)); /* Lower output port: W/2 == 1 tracks */ std::string chan_lower_output_port_name = @@ -949,6 +968,9 @@ static void build_connection_block_module( rr_gsb.get_cb_chan_width(cb_type) / 2); ModulePortId chan_lower_output_port_id = module_manager.add_port( cb_module, chan_lower_output_port, ModuleManager::MODULE_OUTPUT_PORT); + /* Add side to the port */ + module_manager.set_port_side(cb_module, chan_lower_output_port_id, + get_cb_module_track_port_side(cb_type, false)); /* Add the input pins of grids, which are output ports of the connection block */ @@ -957,16 +979,39 @@ static void build_connection_block_module( enum e_side cb_ipin_side = cb_ipin_sides[iside]; for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { - const RRNodeId& ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); - vtr::Point port_coord(rr_graph.node_xlow(ipin_node), - rr_graph.node_ylow(ipin_node)); + RRNodeId ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); std::string port_name = generate_cb_module_grid_port_name( cb_ipin_side, grids, device_annotation, rr_graph, ipin_node); BasicPort module_port(port_name, 1); /* Every grid output has a port size of 1 */ /* Grid outputs are inputs of switch blocks */ - module_manager.add_port(cb_module, module_port, - ModuleManager::MODULE_OUTPUT_PORT); + ModulePortId module_port_id = module_manager.add_port( + cb_module, module_port, ModuleManager::MODULE_OUTPUT_PORT); + /* Add side to the port */ + module_manager.set_port_side(cb_module, module_port_id, cb_ipin_side); + } + } + + /* Add the output pins of grids which are input ports of the connection block, + * if there is any */ + std::vector opin_module_port_ids; + std::vector cb_opin_sides = rr_gsb.get_cb_opin_sides(cb_type); + for (size_t iside = 0; iside < cb_opin_sides.size(); ++iside) { + enum e_side cb_opin_side = cb_opin_sides[iside]; + for (size_t inode = 0; + inode < rr_gsb.get_num_cb_opin_nodes(cb_type, cb_opin_side); ++inode) { + RRNodeId opin_node = + rr_gsb.get_cb_opin_node(cb_type, cb_opin_side, inode); + std::string port_name = generate_cb_module_grid_port_name( + cb_opin_side, grids, device_annotation, rr_graph, opin_node); + BasicPort module_port(port_name, + 1); /* Every grid output has a port size of 1 */ + /* Grid outputs are inputs of switch blocks */ + ModulePortId module_port_id = module_manager.add_port( + cb_module, module_port, ModuleManager::MODULE_INPUT_PORT); + /* Add side to the port */ + module_manager.set_port_side(cb_module, module_port_id, cb_opin_side); + opin_module_port_ids.push_back(module_port_id); } } @@ -1011,6 +1056,13 @@ static void build_connection_block_module( chan_lower_input_port_id, chan_lower_input_port.pins()[pin_id])] = net; } + for (ModulePortId opin_module_port_id : opin_module_port_ids) { + ModuleNetId net = create_module_source_pin_net( + module_manager, cb_module, cb_module, 0, opin_module_port_id, 0); + /* Cache the module net */ + input_port_to_module_nets[ModulePinInfo(opin_module_port_id, 0)] = net; + } + /* Add sub modules of routing multiplexers or direct interconnect*/ for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { enum e_side cb_ipin_side = cb_ipin_sides[iside]; diff --git a/openfpga/src/fabric/build_tile_modules.cpp b/openfpga/src/fabric/build_tile_modules.cpp index caf82f075..74797aa39 100644 --- a/openfpga/src/fabric/build_tile_modules.cpp +++ b/openfpga/src/fabric/build_tile_modules.cpp @@ -211,6 +211,10 @@ static int build_tile_module_port_and_nets_between_sb_and_pb( ModulePortId src_tile_port_id = module_manager.add_port( tile_module, src_grid_port, ModuleManager::e_module_port_type::MODULE_INPUT_PORT); + /* Set port side, inherit from the child module */ + module_manager.set_port_side( + tile_module, src_tile_port_id, + module_manager.port_side(sink_sb_module, sink_sb_port_id)); VTR_LOGV( verbose, "Adding ports '%s' to tile as required by the switch block '%s'...\n", @@ -442,6 +446,10 @@ static int build_tile_module_port_and_nets_between_cb_and_pb( ModulePortId sink_tile_port_id = module_manager.add_port( tile_module, src_cb_port, ModuleManager::e_module_port_type::MODULE_OUTPUT_PORT); + /* Set port side, inherit from the child module */ + module_manager.set_port_side( + tile_module, sink_tile_port_id, + module_manager.port_side(src_cb_module, src_cb_port_id)); VTR_LOGV(verbose, "Adding ports '%s' to tile as required by the connection " "block '%s'...\n", @@ -463,6 +471,158 @@ static int build_tile_module_port_and_nets_between_cb_and_pb( } } } + /* Iterate over the output pins of the Connection Block */ + std::vector cb_opin_sides = module_cb.get_cb_opin_sides(cb_type); + for (size_t iside = 0; iside < cb_opin_sides.size(); ++iside) { + enum e_side cb_opin_side = cb_opin_sides[iside]; + for (size_t inode = 0; + inode < module_cb.get_num_cb_opin_nodes(cb_type, cb_opin_side); + ++inode) { + /* Collect source-related information */ + RRNodeId module_opin_node = + module_cb.get_cb_opin_node(cb_type, cb_opin_side, inode); + vtr::Point cb_src_port_coord( + rr_graph.node_xlow(module_opin_node), + rr_graph.node_ylow(module_opin_node)); + std::string src_cb_port_name = generate_cb_module_grid_port_name( + cb_opin_side, grids, vpr_device_annotation, rr_graph, module_opin_node); + ModulePortId src_cb_port_id = + module_manager.find_module_port(src_cb_module, src_cb_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(src_cb_module, + src_cb_port_id)); + BasicPort src_cb_port = + module_manager.module_port(src_cb_module, src_cb_port_id); + + /* Collect sink-related information */ + /* Note that we use the instance cb pin here!!! + * because it has the correct coordinator for the grid!!! + */ + RRNodeId instance_opin_node = + rr_gsb.get_cb_opin_node(cb_type, cb_opin_side, inode); + vtr::Point grid_coordinate( + rr_graph.node_xlow(instance_opin_node), + rr_graph.node_ylow(instance_opin_node)); + std::string sink_grid_module_name = + generate_grid_block_module_name_in_top_module( + std::string(GRID_MODULE_NAME_PREFIX), grids, grid_coordinate); + ModuleId sink_grid_module = + module_manager.find_module(sink_grid_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(sink_grid_module)); + size_t sink_grid_pin_index = rr_graph.node_pin_num(instance_opin_node); + + t_physical_tile_type_ptr grid_type_descriptor = grids.get_physical_type( + t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); + size_t sink_grid_pin_width = + grid_type_descriptor->pin_width_offset[sink_grid_pin_index]; + size_t sink_grid_pin_height = + grid_type_descriptor->pin_height_offset[sink_grid_pin_index]; + BasicPort sink_grid_pin_info = + vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, + sink_grid_pin_index); + VTR_ASSERT(true == sink_grid_pin_info.is_valid()); + int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index( + grid_type_descriptor, sink_grid_pin_index); + VTR_ASSERT(OPEN != subtile_index && + subtile_index < grid_type_descriptor->capacity); + std::string sink_grid_port_name = generate_grid_port_name( + sink_grid_pin_width, sink_grid_pin_height, subtile_index, + get_rr_graph_single_node_side( + rr_graph, rr_gsb.get_cb_opin_node(cb_type, cb_opin_side, inode)), + sink_grid_pin_info); + ModulePortId sink_grid_port_id = + module_manager.find_module_port(sink_grid_module, sink_grid_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id( + sink_grid_module, sink_grid_port_id)); + BasicPort sink_grid_port = + module_manager.module_port(sink_grid_module, sink_grid_port_id); + + /* Check if the grid is inside the tile, if not, create ports */ + if (fabric_tile.pb_in_tile(fabric_tile_id, grid_coordinate)) { + if (!frame_view) { + size_t sink_grid_instance = + pb_instances[fabric_tile.find_pb_index_in_tile(fabric_tile_id, + grid_coordinate)]; + + /* Source and sink port should match in size */ + VTR_ASSERT(src_cb_port.get_width() == sink_grid_port.get_width()); + + /* Create a net for each pin. Note that the sink and source tags are + * reverted in the following code!!! */ + for (size_t pin_id = 0; pin_id < src_cb_port.pins().size(); + ++pin_id) { + ModuleNetId net = create_module_source_pin_net( + module_manager, tile_module, sink_grid_module, sink_grid_instance, + sink_grid_port_id, sink_grid_port.pins()[pin_id]); + /* Configure the net sink */ + module_manager.add_module_net_sink(tile_module, net, src_cb_module, + src_cb_instance, src_cb_port_id, + src_cb_port.pins()[pin_id]); + } + } + } else { + /* Special: No need to create a new port! Since we only support OPINs + * from Switch blocks. Walk through all the switch blocks and find the + * new port that it is created when connecting pb and sb */ + if (!frame_view) { + /* This is the source sb that is added to the top module */ + const RRGSB& module_sb = device_rr_gsb.get_gsb(module_gsb_coordinate); + vtr::Point module_sb_coordinate(module_sb.get_sb_x(), + module_sb.get_sb_y()); + + /* Collect sink-related information */ + std::string sink_sb_module_name = + generate_switch_block_module_name(module_sb_coordinate); + ModuleId sink_sb_module = + module_manager.find_module(sink_sb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(sink_sb_module)); + size_t isb = fabric_tile.find_sb_index_in_tile(fabric_tile_id, + module_sb_coordinate); + std::string temp_sb_module_name = generate_switch_block_module_name( + fabric_tile.sb_coordinates(fabric_tile_id)[isb]); + if (name_module_using_index) { + temp_sb_module_name = + generate_switch_block_module_name_using_index(isb); + } + /* FIXME: may find a way to determine the side. Currently using + * cb_opin_side is fine */ + vtr::Point sink_sb_port_coord( + rr_graph.node_xlow(module_sb.get_opin_node(cb_opin_side, inode)), + rr_graph.node_ylow(module_sb.get_opin_node(cb_opin_side, inode))); + std::string sink_sb_port_name = generate_sb_module_grid_port_name( + cb_opin_side, + get_rr_graph_single_node_side( + rr_graph, module_sb.get_opin_node(cb_opin_side, inode)), + grids, vpr_device_annotation, rr_graph, + module_sb.get_opin_node(cb_opin_side, inode)); + ModulePortId sink_sb_port_id = + module_manager.find_module_port(sink_sb_module, sink_sb_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id( + sink_sb_module, sink_sb_port_id)); + BasicPort sink_sb_port = + module_manager.module_port(sink_sb_module, sink_sb_port_id); + + sink_sb_port.set_name(generate_tile_module_port_name( + temp_sb_module_name, sink_sb_port.get_name())); + ModulePortId src_tile_port_id = module_manager.find_module_port( + tile_module, sink_sb_port.get_name()); + + /* Create a net for each pin */ + VTR_ASSERT(src_cb_port.pins().size() == sink_sb_port.pins().size()); + for (size_t pin_id = 0; pin_id < src_cb_port.pins().size(); + ++pin_id) { + ModuleNetId net = create_module_source_pin_net( + module_manager, tile_module, tile_module, 0, src_tile_port_id, + sink_sb_port.pins()[pin_id]); + /* Configure the net sink */ + module_manager.add_module_net_sink(tile_module, net, src_cb_module, + src_cb_instance, src_cb_port_id, + src_cb_port.pins()[pin_id]); + } + } + } + } + } + return CMD_EXEC_SUCCESS; } @@ -739,6 +899,10 @@ static int build_tile_module_port_and_nets_between_sb_and_cb( ModulePortId tile_chan_output_port_id = module_manager.add_port( tile_module, chan_output_port, ModuleManager::e_module_port_type::MODULE_OUTPUT_PORT); + /* Set port side, inherit from the child module */ + module_manager.set_port_side( + tile_module, tile_chan_output_port_id, + module_manager.port_side(sb_module_id, sb_chan_output_port_id)); VTR_LOGV( verbose, "Adding ports '%s' to tile as required by the switch block '%s'...\n", @@ -816,6 +980,10 @@ static int build_tile_module_one_port_from_cb( * avoid naming conflicts */ ModulePortId tile_module_port_id = module_manager.add_port(tile_module, tile_chan_port, chan_port_type); + /* Set port side, inherit from the child module */ + module_manager.set_port_side( + tile_module, tile_module_port_id, + module_manager.port_side(cb_module, chan_port_id)); if (!frame_view) { for (size_t pin_id = 0; pin_id < chan_port.pins().size(); ++pin_id) { @@ -1161,6 +1329,10 @@ static int build_tile_port_and_nets_from_pb( ModulePortId tile_module_port_id = module_manager.add_port( tile_module, pb_port, ModuleManager::e_module_port_type::MODULE_OUTPUT_PORT); + /* Set port side, inherit from the child module */ + module_manager.set_port_side( + tile_module, tile_module_port_id, + module_manager.port_side(pb_module, pb_module_port_id)); if (!frame_view) { ModuleNetId net = create_module_source_pin_net( module_manager, tile_module, pb_module, pb_instance, diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index 98b256fe0..84c901945 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -563,6 +563,90 @@ static void add_top_module_nets_connect_grids_and_cb( } } } + + /* Iterate over the input pins of the Connection Block */ + std::vector cb_opin_sides = module_cb.get_cb_opin_sides(cb_type); + for (size_t iside = 0; iside < cb_opin_sides.size(); ++iside) { + enum e_side cb_opin_side = cb_opin_sides[iside]; + for (size_t inode = 0; + inode < module_cb.get_num_cb_opin_nodes(cb_type, cb_opin_side); + ++inode) { + /* Collect source-related information */ + RRNodeId module_opin_node = + module_cb.get_cb_opin_node(cb_type, cb_opin_side, inode); + vtr::Point cb_src_port_coord( + rr_graph.node_xlow(module_opin_node), + rr_graph.node_ylow(module_opin_node)); + std::string src_cb_port_name = generate_cb_module_grid_port_name( + cb_opin_side, grids, vpr_device_annotation, rr_graph, module_opin_node); + ModulePortId src_cb_port_id = + module_manager.find_module_port(src_cb_module, src_cb_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(src_cb_module, + src_cb_port_id)); + BasicPort src_cb_port = + module_manager.module_port(src_cb_module, src_cb_port_id); + + /* Collect sink-related information */ + /* Note that we use the instance cb pin here!!! + * because it has the correct coordinator for the grid!!! + */ + RRNodeId instance_opin_node = + rr_gsb.get_cb_opin_node(cb_type, cb_opin_side, inode); + vtr::Point grid_coordinate( + rr_graph.node_xlow(instance_opin_node), + rr_graph.node_ylow(instance_opin_node)); + std::string sink_grid_module_name = + generate_grid_block_module_name_in_top_module( + std::string(GRID_MODULE_NAME_PREFIX), grids, grid_coordinate); + ModuleId sink_grid_module = + module_manager.find_module(sink_grid_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(sink_grid_module)); + size_t sink_grid_instance = + grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()]; + size_t sink_grid_pin_index = rr_graph.node_pin_num(instance_opin_node); + + t_physical_tile_type_ptr grid_type_descriptor = grids.get_physical_type( + t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); + size_t sink_grid_pin_width = + grid_type_descriptor->pin_width_offset[sink_grid_pin_index]; + size_t sink_grid_pin_height = + grid_type_descriptor->pin_height_offset[sink_grid_pin_index]; + BasicPort sink_grid_pin_info = + vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, + sink_grid_pin_index); + VTR_ASSERT(true == sink_grid_pin_info.is_valid()); + int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index( + grid_type_descriptor, sink_grid_pin_index); + VTR_ASSERT(OPEN != subtile_index && + subtile_index < grid_type_descriptor->capacity); + std::string sink_grid_port_name = generate_grid_port_name( + sink_grid_pin_width, sink_grid_pin_height, subtile_index, + get_rr_graph_single_node_side( + rr_graph, rr_gsb.get_cb_opin_node(cb_type, cb_opin_side, inode)), + sink_grid_pin_info); + ModulePortId sink_grid_port_id = + module_manager.find_module_port(sink_grid_module, sink_grid_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id( + sink_grid_module, sink_grid_port_id)); + BasicPort sink_grid_port = + module_manager.module_port(sink_grid_module, sink_grid_port_id); + + /* Source and sink port should match in size */ + VTR_ASSERT(src_cb_port.get_width() == sink_grid_port.get_width()); + + /* Create a net for each pin. Note that the src/sink tag is reverted in + * the following code. */ + for (size_t pin_id = 0; pin_id < src_cb_port.pins().size(); ++pin_id) { + ModuleNetId net = create_module_source_pin_net( + module_manager, top_module, sink_grid_module, sink_grid_instance, + sink_grid_port_id, sink_grid_port.pins()[pin_id]); + /* Configure the net sink */ + module_manager.add_module_net_sink(top_module, net, src_cb_module, + src_cb_instance, src_cb_port_id, + src_cb_port.pins()[pin_id]); + } + } + } } /******************************************************************** diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp index a7d137a5e..5dae3f0f4 100644 --- a/openfpga/src/fabric/build_top_module_memory.cpp +++ b/openfpga/src/fabric/build_top_module_memory.cpp @@ -1110,14 +1110,14 @@ static void add_top_module_nets_cmos_memory_bank_config_bus( /* Each memory bank has a unified number of BL/WLs */ size_t num_bls = 0; for (const auto& curr_config_bits : num_config_bits) { - num_bls = - std::max(num_bls, find_memory_decoder_data_size(curr_config_bits.first)); + num_bls = std::max( + num_bls, find_memory_decoder_data_size(curr_config_bits.first, 0, true)); } size_t num_wls = 0; for (const auto& curr_config_bits : num_config_bits) { - num_wls = - std::max(num_wls, find_memory_decoder_data_size(curr_config_bits.first)); + num_wls = std::max( + num_wls, find_memory_decoder_data_size(curr_config_bits.first, 0, false)); } /* Create separated memory bank circuitry, i.e., BL/WL decoders for each diff --git a/openfpga/src/fabric/fabric_hierarchy_writer.cpp b/openfpga/src/fabric/fabric_hierarchy_writer.cpp index 46daae954..6b24a4484 100644 --- a/openfpga/src/fabric/fabric_hierarchy_writer.cpp +++ b/openfpga/src/fabric/fabric_hierarchy_writer.cpp @@ -1,12 +1,14 @@ /*************************************************************************************** * Output internal structure of Module Graph hierarchy to file formats ***************************************************************************************/ +#include /* Headers from vtrutil library */ #include "vtr_assert.h" #include "vtr_log.h" #include "vtr_time.h" /* Headers from openfpgautil library */ +#include "command_exit_codes.h" #include "fabric_hierarchy_writer.h" #include "openfpga_digest.h" #include "openfpga_naming.h" @@ -14,6 +16,32 @@ /* begin namespace openfpga */ namespace openfpga { +/** Identify if the module has no child whose name matches the filter */ +static bool module_filter_all_children(const ModuleManager& module_manager, + const ModuleId& curr_module, + const ModuleNameMap& module_name_map, + const std::string& module_name_filter) { + for (const ModuleId& child_module : + module_manager.child_modules(curr_module)) { + /* Filter out the names which do not match the pattern */ + std::string child_module_name = module_manager.module_name(child_module); + if (module_name_map.name_exist(child_module_name)) { + child_module_name = module_name_map.name(child_module_name); + } + std::string pattern = module_name_filter; + std::regex star_replace("\\*"); + std::regex questionmark_replace("\\?"); + std::string wildcard_pattern = + std::regex_replace(std::regex_replace(pattern, star_replace, ".*"), + questionmark_replace, "."); + std::regex wildcard_regex(wildcard_pattern); + if (std::regex_match(child_module_name, wildcard_regex)) { + return false; + } + } + return true; +} + /*************************************************************************************** * Recursively output child module of the parent_module to a text file * We use Depth-First Search (DFS) here so that we can output a tree down to @@ -23,52 +51,88 @@ namespace openfpga { static int rec_output_module_hierarchy_to_text_file( std::fstream& fp, const size_t& hie_depth_to_stop, const size_t& current_hie_depth, const ModuleManager& module_manager, - const ModuleId& parent_module, const bool& verbose) { + const ModuleId& parent_module, const ModuleNameMap& module_name_map, + const std::string& module_name_filter, const bool& verbose) { /* Stop if hierarchy depth is beyond the stop line */ if (hie_depth_to_stop < current_hie_depth) { - return 0; + return CMD_EXEC_SUCCESS; } if (false == valid_file_stream(fp)) { - return 2; + return CMD_EXEC_FATAL_ERROR; } + /* Check if all the child module has not qualified grand-child, use leaf for + * this level */ + bool use_list = true; + for (const ModuleId& child_module : + module_manager.child_modules(parent_module)) { + if (!module_filter_all_children(module_manager, child_module, + module_name_map, module_name_filter)) { + use_list = false; + break; + } + } + /* For debug use only + VTR_LOGV(verbose, "Current depth: %lu, Target depth: %lu\n", + current_hie_depth, hie_depth_to_stop); + */ + std::string parent_module_name = module_manager.module_name(parent_module); + if (module_name_map.name_exist(parent_module_name)) { + parent_module_name = module_name_map.name(parent_module_name); + } + VTR_LOGV( + use_list && verbose, "Use list as module '%s' contains only leaf nodes\n", + module_name_map.name(module_manager.module_name(parent_module)).c_str()); + /* Iterate over all the child module */ for (const ModuleId& child_module : module_manager.child_modules(parent_module)) { - if (false == write_space_to_file(fp, current_hie_depth * 2)) { - return 2; - } - if (true != module_manager.valid_module_id(child_module)) { - VTR_LOGV_ERROR(verbose, "Unable to find the child module '%u'!\n", - size_t(child_module)); - return 1; + VTR_LOGV_ERROR( + verbose, + "Unable to find the child module '%s' under its parent '%s'!\n", + module_manager.module_name(child_module).c_str(), + module_manager.module_name(parent_module).c_str()); + return CMD_EXEC_FATAL_ERROR; } - fp << "- "; - fp << module_manager.module_name(child_module); - - /* If this is the leaf node, we leave a new line - * Otherwise, we will leave a ':' to be compatible to YAML file format - */ - if ((0 != module_manager.child_modules(child_module).size()) && - (hie_depth_to_stop >= current_hie_depth + 1)) { - fp << ":"; + /* Filter out the names which do not match the pattern */ + std::string child_module_name = module_manager.module_name(child_module); + if (module_name_map.name_exist(child_module_name)) { + child_module_name = module_name_map.name(child_module_name); + } + std::string pattern = module_name_filter; + std::regex star_replace("\\*"); + std::regex questionmark_replace("\\?"); + std::string wildcard_pattern = + std::regex_replace(std::regex_replace(pattern, star_replace, ".*"), + questionmark_replace, "."); + std::regex wildcard_regex(wildcard_pattern); + if (!std::regex_match(child_module_name, wildcard_regex)) { + continue; } - fp << "\n"; + if (false == write_space_to_file(fp, current_hie_depth * 2)) { + return CMD_EXEC_FATAL_ERROR; + } + if (hie_depth_to_stop == current_hie_depth || use_list) { + fp << "- " << child_module_name.c_str() << "\n"; + } else { + fp << child_module_name.c_str() << ":\n"; + } /* Go to next level */ int status = rec_output_module_hierarchy_to_text_file( fp, hie_depth_to_stop, current_hie_depth + 1, /* Increment the depth for the next level */ - module_manager, child_module, verbose); - if (0 != status) { + module_manager, child_module, module_name_map, module_name_filter, + verbose); + if (status != CMD_EXEC_SUCCESS) { return status; } } - return 0; + return CMD_EXEC_SUCCESS; } /*************************************************************************************** @@ -83,11 +147,11 @@ static int rec_output_module_hierarchy_to_text_file( * Return 1 if there are more serious bugs in the architecture * Return 2 if fail when creating files ***************************************************************************************/ -int write_fabric_hierarchy_to_text_file(const ModuleManager& module_manager, - const ModuleNameMap& module_name_map, - const std::string& fname, - const size_t& hie_depth_to_stop, - const bool& verbose) { +int write_fabric_hierarchy_to_text_file( + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const std::string& fname, const std::string& root_module_names, + const std::string& module_name_filter, const size_t& hie_depth_to_stop, + const bool& exclude_empty_modules, const bool& verbose) { std::string timer_message = std::string("Write fabric hierarchy to plain-text file '") + fname + std::string("'"); @@ -111,35 +175,61 @@ int write_fabric_hierarchy_to_text_file(const ModuleManager& module_manager, /* Validate the file stream */ check_file_stream(fname.c_str(), fp); - /* Find top-level module */ - std::string top_module_name = - module_name_map.name(generate_fpga_top_module_name()); - ModuleId top_module = module_manager.find_module(top_module_name); - if (true != module_manager.valid_module_id(top_module)) { - VTR_LOGV_ERROR(verbose, "Unable to find the top-level module '%s'!\n", - top_module_name.c_str()); - return 1; + size_t cnt = 0; + /* Use regular expression to capture the module whose name matches the pattern + */ + for (ModuleId curr_module : module_manager.modules()) { + std::string curr_module_name = module_manager.module_name(curr_module); + if (module_name_map.name_exist(curr_module_name)) { + curr_module_name = module_name_map.name(curr_module_name); + } + std::string pattern = root_module_names; + std::regex star_replace("\\*"); + std::regex questionmark_replace("\\?"); + std::string wildcard_pattern = + std::regex_replace(std::regex_replace(pattern, star_replace, ".*"), + questionmark_replace, "."); + std::regex wildcard_regex(wildcard_pattern); + if (!std::regex_match(curr_module_name, wildcard_regex)) { + continue; + } + /* Filter out module without children if required */ + if (exclude_empty_modules && + module_filter_all_children(module_manager, curr_module, module_name_map, + module_name_filter)) { + continue; + } + VTR_LOGV(verbose, "Select module '%s' as root\n", curr_module_name.c_str()); + /* Record current depth of module: top module is the root with 0 depth */ + size_t hie_depth = 0; + + fp << curr_module_name << ":" + << "\n"; + + /* Visit child module recursively and output the hierarchy */ + int err_code = rec_output_module_hierarchy_to_text_file( + fp, hie_depth_to_stop, hie_depth + 1, /* Start with level 1 */ + module_manager, curr_module, module_name_map, module_name_filter, + verbose); + /* Catch error code and exit if required */ + if (err_code == CMD_EXEC_FATAL_ERROR) { + return err_code; + } + cnt++; } - /* Record current depth of module: top module is the root with 0 depth */ - size_t hie_depth = 0; - - if (hie_depth_to_stop < hie_depth) { - return 0; + if (cnt == 0) { + VTR_LOG_ERROR( + "Unable to find any module matching the root module name pattern '%s'!\n", + root_module_names.c_str()); + return CMD_EXEC_FATAL_ERROR; } - - fp << top_module_name << ":" - << "\n"; - - /* Visit child module recursively and output the hierarchy */ - int err_code = rec_output_module_hierarchy_to_text_file( - fp, hie_depth_to_stop, hie_depth + 1, /* Start with level 1 */ - module_manager, top_module, verbose); + VTR_LOG("Outputted %lu modules as root\n", cnt); /* close a file */ fp.close(); - return err_code; + return CMD_EXEC_SUCCESS; } } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/fabric_hierarchy_writer.h b/openfpga/src/fabric/fabric_hierarchy_writer.h index 71fbea25b..c12d6af2f 100644 --- a/openfpga/src/fabric/fabric_hierarchy_writer.h +++ b/openfpga/src/fabric/fabric_hierarchy_writer.h @@ -14,11 +14,11 @@ /* begin namespace openfpga */ namespace openfpga { -int write_fabric_hierarchy_to_text_file(const ModuleManager& module_manager, - const ModuleNameMap& module_name_map, - const std::string& fname, - const size_t& hie_depth_to_stop, - const bool& verbose); +int write_fabric_hierarchy_to_text_file( + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const std::string& fname, const std::string& root_module_names, + const std::string& module_name_filter, const size_t& hie_depth_to_stop, + const bool& exclude_empty_modules, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/fabric_pin_physical_location_xml_constants.h b/openfpga/src/fabric/fabric_pin_physical_location_xml_constants.h new file mode 100644 index 000000000..70ff67a6d --- /dev/null +++ b/openfpga/src/fabric/fabric_pin_physical_location_xml_constants.h @@ -0,0 +1,13 @@ +#ifndef FABRIC_PIN_PHYSICAL_LOCATION_XML_CONSTANTS_H +#define FABRIC_PIN_PHYSICAL_LOCATION_XML_CONSTANTS_H + +/* Constants required by XML parser */ + +constexpr const char* XML_PINLOC_ROOT_NAME = "pin_location"; +constexpr const char* XML_MODULE_NODE_NAME = "module"; +constexpr const char* XML_MODULE_ATTRIBUTE_NAME = "name"; +constexpr const char* XML_MODULE_PINLOC_NODE_NAME = "loc"; +constexpr const char* XML_MODULE_PINLOC_ATTRIBUTE_PIN = "pin"; +constexpr const char* XML_MODULE_PINLOC_ATTRIBUTE_SIDE = "side"; + +#endif diff --git a/openfpga/src/fabric/module_manager.cpp b/openfpga/src/fabric/module_manager.cpp index 48d03095d..178a3b33f 100644 --- a/openfpga/src/fabric/module_manager.cpp +++ b/openfpga/src/fabric/module_manager.cpp @@ -304,6 +304,12 @@ std::vector ModuleManager::module_ports_by_type( return ports; } +e_side ModuleManager::port_side(const ModuleId& module_id, + const ModulePortId& port_id) const { + VTR_ASSERT(valid_module_port_id(module_id, port_id)); + return port_sides_[module_id][port_id]; +} + /* Find a list of port ids of a module by a given types */ std::vector ModuleManager::module_port_ids_by_type( const ModuleId& module_id, const enum e_module_port_type& port_type) const { @@ -746,6 +752,7 @@ ModuleId ModuleManager::add_module(const std::string& name) { port_is_wire_.emplace_back(); port_is_mappable_io_.emplace_back(); port_is_register_.emplace_back(); + port_sides_.emplace_back(); port_preproc_flags_.emplace_back(); num_nets_.emplace_back(0); @@ -789,6 +796,8 @@ ModulePortId ModuleManager::add_port(const ModuleId& module, port_ids_[module].push_back(port); ports_[module].push_back(port_info); port_types_[module].push_back(port_type); + /* Deposit invalid value for each side */ + port_sides_[module].push_back(NUM_SIDES); port_is_wire_[module].push_back(false); port_is_mappable_io_[module].push_back(false); port_is_register_[module].push_back(false); @@ -893,6 +902,15 @@ void ModuleManager::set_port_preproc_flag(const ModuleId& module, port_preproc_flags_[module][port] = preproc_flag; } +/* Set the side for a pin of a port port */ +void ModuleManager::set_port_side(const ModuleId& module, + const ModulePortId& port, + const e_side& pin_side) { + /* Must find something, otherwise drop an error */ + VTR_ASSERT(valid_module_port_id(module, port)); + port_sides_[module][port] = pin_side; +} + /* Add a child module to a parent module */ void ModuleManager::add_child_module(const ModuleId& parent_module, const ModuleId& child_module, diff --git a/openfpga/src/fabric/module_manager.h b/openfpga/src/fabric/module_manager.h index 235719cbc..6f9f2e267 100644 --- a/openfpga/src/fabric/module_manager.h +++ b/openfpga/src/fabric/module_manager.h @@ -9,6 +9,7 @@ #include "module_manager_fwd.h" #include "openfpga_port.h" +#include "physical_types.h" #include "vtr_geometry.h" #include "vtr_vector.h" @@ -273,6 +274,10 @@ class ModuleManager { /* Find the type of a port */ ModuleManager::e_module_port_type port_type(const ModuleId& module, const ModulePortId& port) const; + /* Get the physical side of a port. Note that not every pin has a valid side. + * An invalid value NUM_SIDES will be returned when the pin does not has a + * specific physical location */ + e_side port_side(const ModuleId& module, const ModulePortId& port) const; /* Find if a port is a wire connection */ bool port_is_wire(const ModuleId& module, const ModulePortId& port) const; /* Find if a port is mappable to an I/O from users' implementations */ @@ -369,6 +374,11 @@ class ModuleManager { /* Set the preprocessing flag for a port */ void set_port_preproc_flag(const ModuleId& module, const ModulePortId& port, const std::string& preproc_flag); + /* Set side to a given pin of a module port. Note that the pin id must be a + * valid one. Otherwise, abort and error out. The valid pin range can be get + * from module_port().pins() */ + void set_port_side(const ModuleId& module, const ModulePortId& port, + const e_side& pin_side); /** @brief Add a child module to a parent module. * By default, it considers the child module as an I/O child, and update the * children list of I/O modules inside It not needed, just turn it off. Then @@ -626,6 +636,8 @@ class ModuleManager { ports_; /* List of ports for each Module */ vtr::vector> port_types_; /* Type of ports */ + vtr::vector> + port_sides_; /* Type of ports */ vtr::vector> port_is_mappable_io_; /* If the port is mappable to an I/O for user's implementations */ diff --git a/openfpga/src/fabric/write_xml_fabric_pin_physical_location.cpp b/openfpga/src/fabric/write_xml_fabric_pin_physical_location.cpp new file mode 100644 index 000000000..959d7c252 --- /dev/null +++ b/openfpga/src/fabric/write_xml_fabric_pin_physical_location.cpp @@ -0,0 +1,192 @@ +/*************************************************************************************** + * Output internal structure of module graph to XML format + ***************************************************************************************/ +/* Headers from system goes first */ +#include +#include +#include +#include +#include + +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from openfpgautil library */ +#include "command_exit_codes.h" +#include "openfpga_digest.h" +#include "openfpga_side_manager.h" + +/* Headers from arch openfpga library */ +#include "fabric_pin_physical_location_xml_constants.h" +#include "write_xml_fabric_pin_physical_location.h" +#include "write_xml_utils.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * This function write header information to a pin location file + *******************************************************************/ +static void write_xml_fabric_pin_physical_location_file_head( + std::fstream& fp, const bool& include_time_stamp) { + valid_file_stream(fp); + + fp << "" << std::endl; + fp << std::endl; +} + +/******************************************************************** + * This function write header information to a pin location file + *******************************************************************/ +static int write_xml_fabric_module_pin_phy_loc( + std::fstream& fp, const ModuleManager& module_manager, + const ModuleId& curr_module, const bool& show_invalid_side, + const bool& verbose) { + valid_file_stream(fp); + + /* If show invalid side is off, we should check if there is any valid side. If + * there are not any, skip this module */ + bool skip_curr_module = true; + for (ModulePortId curr_port_id : module_manager.module_ports(curr_module)) { + SideManager side_mgr(module_manager.port_side(curr_module, curr_port_id)); + if (side_mgr.validate()) { + skip_curr_module = false; + break; + } + } + + if (!show_invalid_side && skip_curr_module) { + VTR_LOGV(verbose, "Skip module '%s' as it contains no valid sides\n", + module_manager.module_name(curr_module).c_str()); + return CMD_EXEC_SUCCESS; + } + /* Print a head */ + write_tab_to_file(fp, 1); + fp << "<" << XML_MODULE_NODE_NAME; + write_xml_attribute(fp, XML_MODULE_ATTRIBUTE_NAME, + module_manager.module_name(curr_module).c_str()); + fp << ">" + << "\n"; + + size_t cnt = 0; + for (ModulePortId curr_port_id : module_manager.module_ports(curr_module)) { + BasicPort curr_port = module_manager.module_port(curr_module, curr_port_id); + SideManager side_mgr(module_manager.port_side(curr_module, curr_port_id)); + if (!side_mgr.validate() && !show_invalid_side) { + continue; + } + for (int curr_pin_id : curr_port.pins()) { + BasicPort curr_pin(curr_port.get_name(), curr_pin_id, curr_pin_id); + std::string curr_port_str = generate_xml_port_name(curr_pin); + write_tab_to_file(fp, 2); + fp << "<" << XML_MODULE_PINLOC_NODE_NAME; + write_xml_attribute(fp, XML_MODULE_PINLOC_ATTRIBUTE_PIN, + curr_port_str.c_str()); + write_xml_attribute(fp, XML_MODULE_PINLOC_ATTRIBUTE_SIDE, + side_mgr.c_str()); + fp << "/>"; + fp << std::endl; + } + cnt++; + } + VTR_LOGV(verbose, "Output %lu ports with physical sides for module '%s'\n", + cnt, module_manager.module_name(curr_module).c_str()); + + /* Print a tail */ + write_tab_to_file(fp, 1); + fp << "" + << "\n"; + + return CMD_EXEC_SUCCESS; +} + +/******************************************************************** + * Top-level function + *******************************************************************/ +int write_xml_fabric_pin_physical_location(const char* fname, + const std::string& module_name, + const ModuleManager& module_manager, + const bool& show_invalid_side, + const bool& include_time_stamp, + const bool& verbose) { + vtr::ScopedStartFinishTimer timer("Write fabric pin physical location"); + + /* Create a file handler */ + std::fstream fp; + /* Open the file stream */ + fp.open(std::string(fname), std::fstream::out | std::fstream::trunc); + + /* Validate the file stream */ + openfpga::check_file_stream(fname, fp); + + write_xml_fabric_pin_physical_location_file_head(fp, include_time_stamp); + + /* Write the root node */ + fp << "<" << XML_PINLOC_ROOT_NAME; + fp << ">" + << "\n"; + + /* If module name is not specified, walk through all the modules and write + * physical pin location when any is specified */ + short cnt = 0; + /* Use regular expression to capture the module whose name matches the pattern + */ + for (ModuleId curr_module : module_manager.modules()) { + std::string curr_module_name = module_manager.module_name(curr_module); + std::string pattern = module_name; + std::regex star_replace("\\*"); + std::regex questionmark_replace("\\?"); + std::string wildcard_pattern = + std::regex_replace(std::regex_replace(pattern, star_replace, ".*"), + questionmark_replace, "."); + std::regex wildcard_regex(wildcard_pattern); + if (!std::regex_match(curr_module_name, wildcard_regex)) { + continue; + } + VTR_LOGV(verbose, "Outputted pin physical location of module '%s'.\n", + curr_module_name.c_str()); + /* Write the pin physical location for this module */ + int err_code = write_xml_fabric_module_pin_phy_loc( + fp, module_manager, curr_module, show_invalid_side, verbose); + if (err_code != CMD_EXEC_SUCCESS) { + return CMD_EXEC_FATAL_ERROR; + } + cnt++; + } + + /* Finish writing the root node */ + fp << "" + << "\n"; + + /* Close the file stream */ + fp.close(); + + /* If there is no match, error out! */ + if (cnt == 0) { + VTR_LOG_ERROR( + "Invalid regular expression for module name '%s' which does not match " + "any in current fabric!\n", + module_name.c_str()); + return CMD_EXEC_FATAL_ERROR; + } + + VTR_LOGV(verbose, "Outputted %lu modules with pin physical location.\n", cnt); + + return CMD_EXEC_SUCCESS; +} + +} /* end namespace openfpga */ diff --git a/openfpga/src/fabric/write_xml_fabric_pin_physical_location.h b/openfpga/src/fabric/write_xml_fabric_pin_physical_location.h new file mode 100644 index 000000000..6dd0ef214 --- /dev/null +++ b/openfpga/src/fabric/write_xml_fabric_pin_physical_location.h @@ -0,0 +1,27 @@ +#ifndef WRITE_XML_FABRIC_PIN_PHYSICAL_LOCATION_H +#define WRITE_XML_FABRIC_PIN_PHYSICAL_LOCATION_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include + +#include "module_manager.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +int write_xml_fabric_pin_physical_location(const char* fname, + const std::string& module_name, + const ModuleManager& module_manager, + const bool& show_invalid_side, + const bool& include_time_stamp, + const bool& verbose); + +} /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/fpga_bitstream/fabric_bitstream.h b/openfpga/src/fpga_bitstream/fabric_bitstream.h index 67e92f9f8..85a5054b8 100644 --- a/openfpga/src/fpga_bitstream/fabric_bitstream.h +++ b/openfpga/src/fpga_bitstream/fabric_bitstream.h @@ -30,6 +30,7 @@ #ifndef FABRIC_BITSTREAM_H #define FABRIC_BITSTREAM_H +#include #include #include #include diff --git a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp index 1f56da15e..1002da4b0 100644 --- a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp +++ b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp @@ -317,8 +317,9 @@ static void print_pnr_sdc_constrain_cb_mux_timing( /* Find the module port corresponding to the fan-in rr_nodes of the output * rr_node */ std::vector module_input_ports = - find_connection_block_module_input_ports( - module_manager, cb_module, rr_graph, rr_gsb, cb_type, input_rr_nodes); + find_connection_block_module_input_ports(module_manager, cb_module, grids, + device_annotation, rr_graph, + rr_gsb, cb_type, input_rr_nodes); /* Find timing constraints for each path (edge) */ std::map switch_delays; diff --git a/openfpga/src/fpga_verilog/verilog_constants.h b/openfpga/src/fpga_verilog/verilog_constants.h index da5370fd9..7b77f53bd 100644 --- a/openfpga/src/fpga_verilog/verilog_constants.h +++ b/openfpga/src/fpga_verilog/verilog_constants.h @@ -61,6 +61,11 @@ constexpr const char* FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME = constexpr const char* FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX = "_top_formal_verification_random_tb"; +constexpr const char* VERILOG_FSDB_PREPROC_FLAG = + "DUMP_FSDB"; // the flag to enable fsdb waveform output during compilation +constexpr const char* VERILOG_VCD_PREPROC_FLAG = + "DUMP_VCD"; // the flag to enable vcd waveform output during compilation + #define VERILOG_DEFAULT_SIGNAL_INIT_VALUE 0 #endif diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index e278ff9fa..5c1c703e2 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -490,6 +490,12 @@ int print_verilog_preconfig_top_module( module_manager, top_module, false); } + /* Add waveform output command, support both fsdb and vcd */ + if (true == options.dump_waveform()) { + print_verilog_testbench_dump_waveform( + fp, circuit_name, std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME)); + } + /* Testbench ends*/ print_verilog_module_end( fp, diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp index 6814a1d4e..55e758e34 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp @@ -31,6 +31,7 @@ VerilogTestbenchOption::VerilogTestbenchOption() { time_stamp_ = true; use_relative_path_ = false; simulator_type_ = e_simulator_type::IVERILOG; + dump_waveform_ = false; verbose_output_ = false; SIMULATOR_TYPE_STRING_ = {{"iverilog", "vcs"}}; @@ -87,6 +88,8 @@ bool VerilogTestbenchOption::include_signal_init() const { return include_signal_init_; } +bool VerilogTestbenchOption::dump_waveform() const { return dump_waveform_; } + bool VerilogTestbenchOption::no_self_checking() const { return reference_benchmark_file_path_.empty(); } @@ -206,6 +209,10 @@ void VerilogTestbenchOption::set_include_signal_init(const bool& enabled) { include_signal_init_ = enabled; } +void VerilogTestbenchOption::set_dump_waveform(const bool& enabled) { + dump_waveform_ = enabled; +} + void VerilogTestbenchOption::set_default_net_type( const std::string& default_net_type) { /* Decode from net type string */; diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.h b/openfpga/src/fpga_verilog/verilog_testbench_options.h index f00aac5b5..292fbd5d1 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_options.h +++ b/openfpga/src/fpga_verilog/verilog_testbench_options.h @@ -59,6 +59,7 @@ class VerilogTestbenchOption { std::string simulation_ini_path() const; bool explicit_port_mapping() const; bool include_signal_init() const; + bool dump_waveform() const; bool no_self_checking() const; e_verilog_default_net_type default_net_type() const; e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type() const; @@ -98,6 +99,7 @@ class VerilogTestbenchOption { void set_print_simulation_ini(const std::string& simulation_ini_path); void set_explicit_port_mapping(const bool& enabled); void set_include_signal_init(const bool& enabled); + void set_dump_waveform(const bool& enabled); void set_default_net_type(const std::string& default_net_type); void set_time_unit(const float& time_unit); void set_embedded_bitstream_hdl_type( @@ -132,6 +134,7 @@ class VerilogTestbenchOption { std::string simulation_ini_path_; bool explicit_port_mapping_; bool include_signal_init_; + bool dump_waveform_; e_verilog_default_net_type default_net_type_; e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type_; e_simulator_type simulator_type_; diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp index 4dbb879c9..02fc49737 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp @@ -1344,4 +1344,34 @@ void print_verilog_testbench_signal_initialization( } } +/******************************************************************** + * Print waveform output commands: support both VCD and FSDB + *******************************************************************/ +void print_verilog_testbench_dump_waveform(std::fstream& fp, + const std::string& circuit_name, + const std::string& uut_name) { + /* Validate the file stream */ + valid_file_stream(fp); + + print_verilog_comment( + fp, std::string("------ Use " + std::string(VERILOG_FSDB_PREPROC_FLAG) + + " to enable FSDB waveform output -----")); + print_verilog_preprocessing_flag(fp, std::string(VERILOG_FSDB_PREPROC_FLAG)); + fp << "initial begin\n"; + fp << "\t$fsdbDumpfile(\"" << circuit_name << ".fsdb\");\n"; + fp << "\t$fsdbDumpvars(0, \"" << uut_name << "\");\n"; + fp << "end\n"; + print_verilog_endif(fp); + + print_verilog_comment( + fp, std::string("------ Use " + std::string(VERILOG_VCD_PREPROC_FLAG) + + " to enable VCD waveform output -----")); + print_verilog_preprocessing_flag(fp, std::string(VERILOG_VCD_PREPROC_FLAG)); + fp << "initial begin\n"; + fp << "\t$dumpfile(\"" << circuit_name << ".vcd\");\n"; + fp << "\t$dumpvars(0, \"" << uut_name << "\");\n"; + fp << "end\n"; + print_verilog_endif(fp); +} + } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.h b/openfpga/src/fpga_verilog/verilog_testbench_utils.h index 243bd9904..b4b8bcac8 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.h +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.h @@ -135,6 +135,10 @@ void print_verilog_testbench_signal_initialization( const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, const ModuleId& top_module, const bool& deposit_random_values); +void print_verilog_testbench_dump_waveform(std::fstream& fp, + const std::string& circuit_name, + const std::string& uut_name); + } /* end namespace openfpga */ #endif diff --git a/openfpga/src/repack/build_physical_truth_table.cpp b/openfpga/src/repack/build_physical_truth_table.cpp index 86a2c7aa4..67f258c34 100644 --- a/openfpga/src/repack/build_physical_truth_table.cpp +++ b/openfpga/src/repack/build_physical_truth_table.cpp @@ -138,8 +138,13 @@ static void build_physical_pb_lut_truth_tables( size_t(lut_pb_id), output_pin->to_string().c_str()); VTR_LOGV(verbose, "Input nets:\n"); for (auto input_net : input_nets) { - VTR_LOGV(verbose, "\t%s\n", - atom_ctx.nlist.net_name(input_net).c_str()); + if (AtomNetId::INVALID() == input_net) { + VTR_LOGV(verbose, "\tunconn\n"); + } else { + VTR_ASSERT(AtomNetId::INVALID() != input_net); + VTR_LOGV(verbose, "\t%s\n", + atom_ctx.nlist.net_name(input_net).c_str()); + } } VTR_LOGV(verbose, "Output nets:\n"); VTR_LOGV(verbose, "\t%s\n", @@ -236,6 +241,10 @@ void build_physical_lut_truth_tables( for (auto blk_id : cluster_ctx.clb_nlist.blocks()) { PhysicalPb& physical_pb = cluster_annotation.mutable_physical_pb(blk_id); + VTR_LOGV( + verbose, + "Build truth tables for physical LUTs under clustered block '%s'...\n", + cluster_ctx.clb_nlist.block_name(blk_id).c_str()); /* Find the LUT physical pb id */ for (const PhysicalPbId& primitive_pb : physical_pb.primitive_pbs()) { CircuitModelId circuit_model = device_annotation.pb_type_circuit_model( diff --git a/openfpga/src/repack/lb_router_utils.cpp b/openfpga/src/repack/lb_router_utils.cpp index 45b1fce24..25c4399eb 100644 --- a/openfpga/src/repack/lb_router_utils.cpp +++ b/openfpga/src/repack/lb_router_utils.cpp @@ -92,10 +92,9 @@ void save_lb_router_results_to_physical_pb(PhysicalPb& phy_pb, const AtomNetId& atom_net = lb_router.net_atom_net_id(net); /* Print info to help debug */ - VTR_LOGV(verbose, "Save net '%s' to physical pb_graph_pin '%s.%s[%d]'\n", + VTR_LOGV(verbose, "Save net '%s' to physical pb_graph_pin '%s'\n", atom_netlist.net_name(atom_net).c_str(), - pb_graph_pin->parent_node->pb_type->name, - pb_graph_pin->port->name, pb_graph_pin->pin_number); + pb_graph_pin->to_string().c_str()); if (AtomNetId::INVALID() == phy_pb.pb_graph_pin_atom_net(pb_id, pb_graph_pin)) { diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp index 35f45d7a1..4f3dc460a 100644 --- a/openfpga/src/repack/repack.cpp +++ b/openfpga/src/repack/repack.cpp @@ -304,6 +304,33 @@ static std::vector find_pb_route_by_atom_net( return pb_route_indices; } +/*************************************************************************************** + * This function will find the actual routing traces of the demanded net + * There is a specific search space applied when searching the routing traces: + * - ONLY applicable to the pb_pin of top-level pb_graph_node + ***************************************************************************************/ +static std::vector find_pb_routes_by_atom_net_among_top_pb_pins( + const t_pb* pb, const AtomNetId& atom_net_id) { + std::vector pb_route_indices; + + std::vector candidate_pool; + for (int pin = 0; pin < pb->pb_graph_node->total_pb_pins; ++pin) { + /* Bypass unused pins */ + if ((0 == pb->pb_route.count(pin)) || + (AtomNetId::INVALID() == pb->pb_route.at(pin).atom_net_id)) { + continue; + } + /* Get the driver pb pin id, it must be valid */ + if (atom_net_id != pb->pb_route.at(pin).atom_net_id) { + continue; + } + if (pb->pb_route.at(pin).pb_graph_pin->parent_node->is_root()) { + candidate_pool.push_back(pin); + } + } + return candidate_pool; +} + /*************************************************************************************** * This function will find the actual routing traces of the demanded net * There is a specific search space applied when searching the routing traces: @@ -584,7 +611,6 @@ static void add_lb_router_nets( std::string(lb_type->pb_type->name), curr_pin))) { /* Find the net mapped to this pin in clustering results*/ AtomNetId atom_net_id = pb_pin_mapped_nets[source_pb_pin]; - std::vector pb_route_indices = find_pb_route_by_atom_net(pb, source_pb_pin, atom_net_id); VTR_ASSERT(1 == pb_route_indices.size()); @@ -640,9 +666,15 @@ static void add_lb_router_nets( BasicPort curr_pin(std::string(source_pb_pin->port->name), source_pb_pin->pin_number, source_pb_pin->pin_number); + /* Be very careful! There is only one routing trace for the net, it should + * never be ignored! */ if ((ignored_atom_nets[atom_net_id]) && + (find_pb_routes_by_atom_net_among_top_pb_pins(pb, atom_net_id).size() > + 1) && (options.is_pin_ignore_global_nets(std::string(lb_type->pb_type->name), curr_pin))) { + VTR_LOGV(verbose, "Skip net '%s' as it is global and set to be ignored\n", + atom_ctx.nlist.net_name(atom_net_id).c_str()); continue; } diff --git a/openfpga/src/tile_direct/build_tile_direct.cpp b/openfpga/src/tile_direct/build_tile_direct.cpp index 73b5fd77a..357c0a25c 100644 --- a/openfpga/src/tile_direct/build_tile_direct.cpp +++ b/openfpga/src/tile_direct/build_tile_direct.cpp @@ -197,7 +197,7 @@ static vtr::Point find_inter_direct_destination_coordinate( * Our search space will start from the next column * and ends at the RIGHT side of fabric */ - if (INTER_COLUMN == arch_direct.type(arch_direct_id)) { + if (e_direct_type::INTER_COLUMN == arch_direct.type(arch_direct_id)) { if (POSITIVE_DIR == arch_direct.x_dir(arch_direct_id)) { /* Our first search space will be in x-direction: * @@ -262,7 +262,7 @@ static vtr::Point find_inter_direct_destination_coordinate( * Our search space will start from the next column * and ends at the RIGHT side of fabric */ - if (INTER_ROW == arch_direct.type(arch_direct_id)) { + if (e_direct_type::INTER_ROW == arch_direct.type(arch_direct_id)) { if (POSITIVE_DIR == arch_direct.y_dir(arch_direct_id)) { /* Our first search space will be in y-direction: * @@ -326,10 +326,11 @@ static vtr::Point find_inter_direct_destination_coordinate( for (size_t ix : first_search_space) { std::vector> next_col_row_coords; for (size_t iy : second_search_space) { - if (INTER_COLUMN == arch_direct.type(arch_direct_id)) { + if (e_direct_type::INTER_COLUMN == arch_direct.type(arch_direct_id)) { next_col_row_coords.push_back(vtr::Point(ix, iy)); } else { - VTR_ASSERT(INTER_ROW == arch_direct.type(arch_direct_id)); + VTR_ASSERT(e_direct_type::INTER_ROW == + arch_direct.type(arch_direct_id)); /* For cross-row connection, our search space is flipped */ next_col_row_coords.push_back(vtr::Point(iy, ix)); } @@ -549,8 +550,8 @@ static void build_inter_column_row_tile_direct( /* Go through the direct connection list, see if we need intra-column/row * connection here */ - if ((INTER_COLUMN != arch_direct.type(arch_direct_id)) && - (INTER_ROW != arch_direct.type(arch_direct_id))) { + if ((e_direct_type::INTER_COLUMN != arch_direct.type(arch_direct_id)) && + (e_direct_type::INTER_ROW != arch_direct.type(arch_direct_id))) { return; } /* For cross-column connection, we will search the first valid grid in each @@ -568,7 +569,7 @@ static void build_inter_column_row_tile_direct( * +------+ * */ - if (INTER_COLUMN == arch_direct.type(arch_direct_id)) { + if (e_direct_type::INTER_COLUMN == arch_direct.type(arch_direct_id)) { for (size_t ix = 1; ix < device_ctx.grid.width() - 1; ++ix) { std::vector> next_col_src_grid_coords; /* For negative y- direction, we should start from y = ny */ @@ -671,7 +672,7 @@ static void build_inter_column_row_tile_direct( } /* Reach here, it must be a cross-row connection */ - VTR_ASSERT(INTER_ROW == arch_direct.type(arch_direct_id)); + VTR_ASSERT(e_direct_type::INTER_ROW == arch_direct.type(arch_direct_id)); /* For cross-row connection, we will search the first valid grid in each * column from x = 1 to x = nx * @@ -804,9 +805,14 @@ TileDirect build_device_tile_direct(const DeviceContext& device_ctx, exit(1); } /* Build from original VPR arch definition */ - build_inner_column_row_tile_direct(tile_direct, - device_ctx.arch->Directs[idirect], - device_ctx, arch_direct_id, verbose); + if (e_direct_type::INNER_COLUMN_OR_ROW == + arch_direct.type(arch_direct_id)) { + build_inner_column_row_tile_direct(tile_direct, + device_ctx.arch->Directs[idirect], + device_ctx, arch_direct_id, verbose); + /* Skip those direct connections which belong part of a connection block + */ + } /* Build from OpenFPGA arch definition */ build_inter_column_row_tile_direct( tile_direct, device_ctx.arch->Directs[idirect], device_ctx, arch_direct, diff --git a/openfpga/src/utils/decoder_library_utils.cpp b/openfpga/src/utils/decoder_library_utils.cpp index d3232b7ae..54135a4db 100644 --- a/openfpga/src/utils/decoder_library_utils.cpp +++ b/openfpga/src/utils/decoder_library_utils.cpp @@ -77,7 +77,7 @@ size_t find_mux_local_decoder_addr_size(const size_t& data_size) { ***************************************************************************************/ size_t find_memory_decoder_addr_size(const size_t& num_mems) { return find_mux_local_decoder_addr_size( - find_memory_decoder_data_size(num_mems)); + find_memory_decoder_data_size(num_mems, 0, false)); } /*************************************************************************************** @@ -86,8 +86,18 @@ size_t find_memory_decoder_addr_size(const size_t& num_mems) { *lines and word lines, the number of data lines will be a square root of the *number of memory cells. ***************************************************************************************/ -size_t find_memory_decoder_data_size(const size_t& num_mems) { - return (size_t)std::ceil(std::sqrt((float)num_mems)); +size_t find_memory_decoder_data_size(const size_t& num_mems, + const size_t& defined_num_wl, + const bool is_bl) { + if (defined_num_wl == 0) { + return (size_t)std::ceil(std::sqrt((float)num_mems)); + } else { + if (is_bl) { + return find_memory_wl_decoder_data_size(num_mems, defined_num_wl); + } else { + return defined_num_wl; + } + } } /*************************************************************************************** diff --git a/openfpga/src/utils/decoder_library_utils.h b/openfpga/src/utils/decoder_library_utils.h index 51d6da6dd..63aa501a9 100644 --- a/openfpga/src/utils/decoder_library_utils.h +++ b/openfpga/src/utils/decoder_library_utils.h @@ -15,7 +15,9 @@ size_t find_mux_local_decoder_addr_size(const size_t& data_size); size_t find_memory_decoder_addr_size(const size_t& num_mems); -size_t find_memory_decoder_data_size(const size_t& num_mems); +size_t find_memory_decoder_data_size(const size_t& num_mems, + const size_t& defined_num_wl, + const bool is_bl); size_t find_memory_wl_decoder_data_size(const size_t& num_mems, const size_t& num_bls); diff --git a/openfpga/src/utils/memory_utils.cpp b/openfpga/src/utils/memory_utils.cpp index 0abf95b07..9dc799949 100644 --- a/openfpga/src/utils/memory_utils.cpp +++ b/openfpga/src/utils/memory_utils.cpp @@ -436,7 +436,8 @@ size_t generate_sram_port_size(const e_config_protocol_type sram_orgz_type, * - QL Memory decoders: Apply square root as BL/WLs will be grouped ********************************************************************/ size_t generate_pb_sram_port_size(const e_config_protocol_type sram_orgz_type, - const size_t& num_config_bits) { + const size_t& num_config_bits, + const size_t& defined_num_wl) { size_t sram_port_size = num_config_bits; switch (sram_orgz_type) { @@ -447,7 +448,8 @@ size_t generate_pb_sram_port_size(const e_config_protocol_type sram_orgz_type, sram_port_size = 1; break; case CONFIG_MEM_QL_MEMORY_BANK: - sram_port_size = find_memory_decoder_data_size(num_config_bits); + sram_port_size = + find_memory_decoder_data_size(num_config_bits, defined_num_wl, true); break; case CONFIG_MEM_MEMORY_BANK: break; diff --git a/openfpga/src/utils/memory_utils.h b/openfpga/src/utils/memory_utils.h index 184d0be74..a619c07fb 100644 --- a/openfpga/src/utils/memory_utils.h +++ b/openfpga/src/utils/memory_utils.h @@ -42,7 +42,8 @@ size_t generate_sram_port_size(const e_config_protocol_type sram_orgz_type, const size_t& num_config_bits); size_t generate_pb_sram_port_size(const e_config_protocol_type sram_orgz_type, - const size_t& num_config_bits); + const size_t& num_config_bits, + const size_t& defined_num_wl); /** * @brief Compute the number of configurable children to be skipped for a given diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp index 70a62d148..4a52f46ff 100644 --- a/openfpga/src/utils/module_manager_utils.cpp +++ b/openfpga/src/utils/module_manager_utils.cpp @@ -419,11 +419,16 @@ void add_sram_ports_to_module_manager( void add_pb_sram_ports_to_module_manager( ModuleManager& module_manager, const ModuleId& module_id, const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, - const e_config_protocol_type sram_orgz_type, const size_t& num_config_bits) { + const e_config_protocol_type sram_orgz_type, const size_t& num_config_bits, + const uint32_t defined_num_wl) { + if (defined_num_wl) { + // Only support defined_num_wl if the configuration mode is QL Memory Bank + VTR_ASSERT(sram_orgz_type == CONFIG_MEM_QL_MEMORY_BANK); + } std::vector sram_port_names = generate_sram_port_names(circuit_lib, sram_model, sram_orgz_type); size_t sram_port_size = - generate_pb_sram_port_size(sram_orgz_type, num_config_bits); + generate_pb_sram_port_size(sram_orgz_type, num_config_bits, defined_num_wl); /* Add ports to the module manager */ switch (sram_orgz_type) { diff --git a/openfpga/src/utils/module_manager_utils.h b/openfpga/src/utils/module_manager_utils.h index f55f73402..0bcb59042 100644 --- a/openfpga/src/utils/module_manager_utils.h +++ b/openfpga/src/utils/module_manager_utils.h @@ -74,7 +74,8 @@ void add_sram_ports_to_module_manager( void add_pb_sram_ports_to_module_manager( ModuleManager& module_manager, const ModuleId& module_id, const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, - const e_config_protocol_type sram_orgz_type, const size_t& num_config_bits); + const e_config_protocol_type sram_orgz_type, const size_t& num_config_bits, + const uint32_t defined_num_wl = 0); void add_primitive_pb_type_ports_to_module_manager( ModuleManager& module_manager, const ModuleId& module_id, diff --git a/openfpga/src/utils/physical_pb_utils.cpp b/openfpga/src/utils/physical_pb_utils.cpp index 12d5572e3..ddb8c954f 100644 --- a/openfpga/src/utils/physical_pb_utils.cpp +++ b/openfpga/src/utils/physical_pb_utils.cpp @@ -131,7 +131,8 @@ void alloc_physical_pb_from_pb_graph( static void update_primitive_physical_pb_pin_atom_net( PhysicalPb& phy_pb, const PhysicalPbId& primitive_pb, const t_pb_graph_pin* pb_graph_pin, const t_pb_routes& pb_route, - const VprDeviceAnnotation& device_annotation) { + const VprDeviceAnnotation& device_annotation, const AtomNetlist& atom_nlist, + const bool& verbose) { int node_index = pb_graph_pin->pin_count_in_cluster; if (pb_route.count(node_index)) { /* The pin is mapped to a net, find the original pin in the atom netlist */ @@ -144,15 +145,11 @@ static void update_primitive_physical_pb_pin_atom_net( device_annotation.physical_pb_graph_pin(pb_graph_pin); VTR_ASSERT(nullptr != physical_pb_graph_pin); - /* Print info to help debug - bool verbose = true; - VTR_LOGV(verbose, - "\nSynchronize net '%lu' to physical pb_graph_pin '%s.%s[%d]'\n", - size_t(atom_net), - pb_graph_pin->parent_node->pb_type->name, - pb_graph_pin->port->name, - pb_graph_pin->pin_number); - */ + if (AtomNetId::INVALID() != atom_net) { + VTR_LOGV(verbose, "Synchronize net '%s' to physical pb_graph_pin '%s'\n", + atom_nlist.net_name(atom_net).c_str(), + pb_graph_pin->to_string().c_str()); + } /* Check if the pin has been mapped to a net. * If yes, the atom net must be the same @@ -165,6 +162,11 @@ static void update_primitive_physical_pb_pin_atom_net( VTR_ASSERT(atom_net == phy_pb.pb_graph_pin_atom_net( primitive_pb, physical_pb_graph_pin)); } + } else { + VTR_LOGV(verbose, + "Skip as no valid routing traces if found on physical " + "pb_graph_pin '%s'\n", + pb_graph_pin->to_string().c_str()); } } @@ -175,22 +177,39 @@ static void synchronize_primitive_physical_pb_atom_nets( PhysicalPb& phy_pb, const PhysicalPbId& primitive_pb, const t_pb_graph_node* pb_graph_node, const t_pb_routes& pb_route, const AtomContext& atom_ctx, const AtomBlockId& atom_blk, - const VprDeviceAnnotation& device_annotation) { + const VprDeviceAnnotation& device_annotation, const bool& verbose) { /* Iterate over all the ports: input, output and clock */ + VTR_LOGV(verbose, "Synchronizing atom nets on pb_graph_node '%s'...\n", + pb_graph_node->hierarchical_type_name().c_str()); for (int iport = 0; iport < pb_graph_node->num_input_ports; ++iport) { for (int ipin = 0; ipin < pb_graph_node->num_input_pins[iport]; ++ipin) { /* Port exists (some LUTs may have no input and hence no port in the atom * netlist) */ + VTR_LOGV(verbose, "Synchronizing atom nets on pb_graph_pin '%s'...\n", + pb_graph_node->input_pins[iport][ipin].to_string().c_str()); t_model_ports* model_port = pb_graph_node->input_pins[iport][ipin].port->model_port; + /* Special for LUTs, the model port is hidden under 1 level + * Do NOT do this. Net mapping on LUT inputs may be swapped during + * rerouting + * if (LUT_CLASS == pb_graph_node->pb_type->class_type) { + * VTR_ASSERT(pb_graph_node->pb_type->num_modes == 2); + * model_port = pb_graph_node->child_pb_graph_nodes[1][0][0] + * .input_pins[iport][ipin] + * .port->model_port; + * } + */ + /* It seems that LUT port are no longer built with an internal model */ if (nullptr == model_port) { + VTR_LOGV(verbose, "Skip due to empty model port\n"); continue; } AtomPortId atom_port = atom_ctx.nlist.find_atom_port(atom_blk, model_port); if (!atom_port) { + VTR_LOGV(verbose, "Skip due to invalid port\n"); continue; } /* Find the atom nets mapped to the pin @@ -199,7 +218,7 @@ static void synchronize_primitive_physical_pb_atom_nets( */ update_primitive_physical_pb_pin_atom_net( phy_pb, primitive_pb, &(pb_graph_node->input_pins[iport][ipin]), - pb_route, device_annotation); + pb_route, device_annotation, atom_ctx.nlist, verbose); } } @@ -207,15 +226,29 @@ static void synchronize_primitive_physical_pb_atom_nets( for (int ipin = 0; ipin < pb_graph_node->num_output_pins[iport]; ++ipin) { /* Port exists (some LUTs may have no input and hence no port in the atom * netlist) */ + VTR_LOGV(verbose, "Synchronizing atom nets on pb_graph_pin '%s'...\n", + pb_graph_node->output_pins[iport][ipin].to_string().c_str()); t_model_ports* model_port = pb_graph_node->output_pins[iport][ipin].port->model_port; + /* Special for LUTs, the model port is hidden under 1 level + * Do NOT do this. Net mapping on LUT inputs may be swapped during + * rerouting + * if (LUT_CLASS == pb_graph_node->pb_type->class_type) { + * VTR_ASSERT(pb_graph_node->pb_type->num_modes == 2); + * model_port = pb_graph_node->child_pb_graph_nodes[1][0][0] + * .output_pins[iport][ipin] + * .port->model_port; + * } + */ if (nullptr == model_port) { + VTR_LOGV(verbose, "Skip due to empty model port\n"); continue; } AtomPortId atom_port = atom_ctx.nlist.find_atom_port(atom_blk, model_port); if (!atom_port) { + VTR_LOGV(verbose, "Skip due to invalid port\n"); continue; } /* Find the atom nets mapped to the pin @@ -224,7 +257,7 @@ static void synchronize_primitive_physical_pb_atom_nets( */ update_primitive_physical_pb_pin_atom_net( phy_pb, primitive_pb, &(pb_graph_node->output_pins[iport][ipin]), - pb_route, device_annotation); + pb_route, device_annotation, atom_ctx.nlist, verbose); } } @@ -232,15 +265,19 @@ static void synchronize_primitive_physical_pb_atom_nets( for (int ipin = 0; ipin < pb_graph_node->num_clock_pins[iport]; ++ipin) { /* Port exists (some LUTs may have no input and hence no port in the atom * netlist) */ + VTR_LOGV(verbose, "Synchronizing atom nets on pb_graph_pin '%s'...\n", + pb_graph_node->clock_pins[iport][ipin].to_string().c_str()); t_model_ports* model_port = pb_graph_node->clock_pins[iport][ipin].port->model_port; if (nullptr == model_port) { + VTR_LOGV(verbose, "Skip due to empty model port\n"); continue; } AtomPortId atom_port = atom_ctx.nlist.find_atom_port(atom_blk, model_port); if (!atom_port) { + VTR_LOGV(verbose, "Skip due to invalid port\n"); continue; } /* Find the atom nets mapped to the pin @@ -249,7 +286,7 @@ static void synchronize_primitive_physical_pb_atom_nets( */ update_primitive_physical_pb_pin_atom_net( phy_pb, primitive_pb, &(pb_graph_node->clock_pins[iport][ipin]), - pb_route, device_annotation); + pb_route, device_annotation, atom_ctx.nlist, verbose); } } } @@ -280,10 +317,8 @@ static void mark_physical_pb_wired_lut_outputs( VTR_ASSERT(nullptr != physical_pb_graph_pin); /* Print debug info */ - VTR_LOGV( - verbose, "Mark physical pb_graph pin '%s.%s[%d]' as wire LUT output\n", - physical_pb_graph_pin->parent_node->pb_type->name, - physical_pb_graph_pin->port->name, physical_pb_graph_pin->pin_number); + VTR_LOGV(verbose, "Mark physical pb_graph pin '%s' as wire LUT output\n", + physical_pb_graph_pin->to_string().c_str()); /* Label the pins in physical_pb as driven by wired LUT*/ phy_pb.set_wire_lut_output(primitive_pb, physical_pb_graph_pin, true); @@ -318,6 +353,9 @@ void rec_update_physical_pb_from_operating_pb( VTR_ASSERT(atom_blk); phy_pb.add_atom_block(physical_pb, atom_blk); + VTR_LOGV(verbose, "Update physical pb '%s' using atom block '%s'\n", + physical_pb_graph_node->hierarchical_type_name().c_str(), + atom_ctx.nlist.block_name(atom_blk).c_str()); /* if the operating pb type has bitstream annotation, * bind the bitstream value from atom block to the physical pb @@ -400,7 +438,7 @@ void rec_update_physical_pb_from_operating_pb( /* Iterate over ports and annotate the atom pins */ synchronize_primitive_physical_pb_atom_nets( phy_pb, physical_pb, pb_graph_node, pb_route, atom_ctx, atom_blk, - device_annotation); + device_annotation, verbose); return; } diff --git a/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut_4bit/rst_on_lut_4bit.v b/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut_4bit/rst_on_lut_4bit.v new file mode 100644 index 000000000..33a8db5f3 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut_4bit/rst_on_lut_4bit.v @@ -0,0 +1,35 @@ +///////////////////////////////////////// +// Functionality: 4-bit version of A register driven by a combinational logic with reset signal +// Author: Xifan Tang +//////////////////////////////////////// +`timescale 1ns / 1ps + +module rst_on_lut_4bit(a, b0, b1, b2, b3, q, out0, out1, out2, out3, clk, rst); + +input wire rst; +input wire clk; +input wire a; +input wire b0; +input wire b1; +input wire b2; +input wire b3; +output reg q; +output wire out0; +output wire out1; +output wire out2; +output wire out3; + +always @(posedge rst or posedge clk) begin + if (rst) begin + q <= 0; + end else begin + q <= a; + end +end + +assign out0 = b0 & ~rst; +assign out1 = b1 & ~rst; +assign out2 = b2 & ~rst; +assign out3 = b3 & ~rst; + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut_8bit/rst_on_lut_8bit.v b/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut_8bit/rst_on_lut_8bit.v new file mode 100644 index 000000000..30c97205a --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut_8bit/rst_on_lut_8bit.v @@ -0,0 +1,47 @@ +///////////////////////////////////////// +// Functionality: 8-bit version of A register driven by a combinational logic with reset signal +// Author: Xifan Tang +//////////////////////////////////////// +`timescale 1ns / 1ps + +module rst_on_lut_8bit(a, b0, b1, b2, b3, b4, b5, b6, b7, q, out0, out1, out2, out3, out4, out5, out6, out7, clk, rst); + +input wire rst; +input wire clk; +input wire a; +input wire b0; +input wire b1; +input wire b2; +input wire b3; +input wire b4; +input wire b5; +input wire b6; +input wire b7; +output reg q; +output wire out0; +output wire out1; +output wire out2; +output wire out3; +output wire out4; +output wire out5; +output wire out6; +output wire out7; + +always @(posedge rst or posedge clk) begin + if (rst) begin + q <= 0; + end else begin + q <= a; + end +end + +assign out0 = b0 & ~rst; +assign out1 = b1 & ~rst; +assign out2 = b2 & ~rst; +assign out3 = b3 & ~rst; +assign out4 = b4 & ~rst; +assign out5 = b5 & ~rst; +assign out6 = b6 & ~rst; +assign out7 = b7 & ~rst; + +endmodule diff --git a/openfpga_flow/openfpga_arch/README.md b/openfpga_flow/openfpga_arch/README.md index b23e837ec..a2cc2f6ee 100644 --- a/openfpga_flow/openfpga_arch/README.md +++ b/openfpga_flow/openfpga_arch/README.md @@ -37,5 +37,6 @@ Note that an OpenFPGA architecture can be applied to multiple VPR architecture f * is the number of clocks * When specified, multiple clocks are in separated pins with different names - abspath: All the paths in the architecture file are absolute and hardcoded. +- ecb: *Enhanced Connection Block* where connection blocks includes feedback connections Other features are used in naming should be listed here. diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbankflatten_defined_wl_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbankflatten_defined_wl_openfpga.xml new file mode 100644 index 000000000..8fbf05b1f --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbankflatten_defined_wl_openfpga.xml @@ -0,0 +1,206 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_ecb_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_ecb_40nm_cc_openfpga.xml new file mode 100644 index 000000000..12842a05b --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_ecb_40nm_cc_openfpga.xml @@ -0,0 +1,253 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_abspath_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_abspath_openfpga.xml index 254f3fcac..a3b49f374 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_abspath_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_abspath_openfpga.xml @@ -210,7 +210,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml index 8cb766b67..51af075ea 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml @@ -210,7 +210,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml index aaddef305..32996800e 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml @@ -222,7 +222,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124X_L12Y_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124X_L12Y_40nm_frame_openfpga.xml index f489b97f5..6d3e3c45f 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124X_L12Y_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124X_L12Y_40nm_frame_openfpga.xml @@ -228,7 +228,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml index 444615016..b6752970f 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml @@ -226,7 +226,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml index 0fcbfba3f..203d8e179 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml @@ -232,7 +232,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index 81ae2b79d..50b4c6e6b 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -213,8 +213,8 @@ - - + + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml index c19f4c2cf..f4b3b0733 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml @@ -217,8 +217,8 @@ - - + + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index 86cf97c3c..bd122d3c9 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -215,7 +215,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index 0e503f00a..f889f2de6 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -230,7 +230,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index fa4ddb9be..8b89cf9a0 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -227,7 +227,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index 35ac32ced..7e659a631 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -235,7 +235,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index 3beae9929..b2d6da19d 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -236,7 +236,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml index be02a50e5..09dcb1b50 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml @@ -211,7 +211,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml index a64e19c82..1f7f137c3 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml @@ -233,7 +233,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml index 0812ecff9..831cf161e 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml @@ -234,7 +234,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml index 1997ab1f3..974a92928 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml @@ -237,7 +237,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml index 1d4a2cdb9..9cc2a0dfb 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml @@ -237,7 +237,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml index 1ac39cda0..d0567bb2f 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml @@ -223,7 +223,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml index 2ff4c6a0c..476850d6e 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml @@ -233,7 +233,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem1K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem1K_40nm_openfpga.xml index dfe1c060e..55237a608 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem1K_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem1K_40nm_openfpga.xml @@ -223,7 +223,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml index 3684157b6..50b7f9a34 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml @@ -211,8 +211,8 @@ - - + + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml index 44470f17b..dbb527899 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml @@ -216,9 +216,9 @@ - - - + + + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml index 624868489..21622bc56 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml @@ -217,7 +217,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml index 48f45f94c..440d0a2ae 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml @@ -232,7 +232,7 @@ - + diff --git a/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_fix_routeW_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_fix_routeW_example_script.openfpga new file mode 100644 index 000000000..85e9900e3 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_fix_routeW_example_script.openfpga @@ -0,0 +1,73 @@ +# Run VPR for the 'and' design +# When the global clock is defined as a port of a tile, clock routing in VPR should be skipped +# This is due to the Fc_in of clock port is set to 0 for global wiring +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/group_config_block_preconfig_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/group_config_block_preconfig_testbench_example_script.openfpga index cdb981da2..afe6032bd 100644 --- a/openfpga_flow/openfpga_shell_scripts/group_config_block_preconfig_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/group_config_block_preconfig_testbench_example_script.openfpga @@ -30,7 +30,8 @@ ${OPENFPGA_ADD_FPGA_CORE_MODULE} # Write the fabric hierarchy of module graph to a file # This is used by hierarchical PnR flows -write_fabric_hierarchy --file ./fabric_hierarchy.txt +write_fabric_hierarchy --file ./config_mem.yaml --depth 1 --module * --filter *config_group_mem* --verbose --exclude_empty_modules +write_fabric_hierarchy --file ./mux_modules.txt --depth 1 --module (grid|cbx|cby|sb)* --filter *mux*_size([0-9]+) --verbose --exclude_empty_modules # Repack the netlist to physical pbs # This must be done before bitstream generator and testbench generation diff --git a/openfpga_flow/openfpga_shell_scripts/group_tile_write_fabric_pin_phy_loc_preconfig_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/group_tile_write_fabric_pin_phy_loc_preconfig_testbench_example_script.openfpga new file mode 100644 index 000000000..fe95685a5 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/group_tile_write_fabric_pin_phy_loc_preconfig_testbench_example_script.openfpga @@ -0,0 +1,79 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal ${OPENFPGA_VPR_EXTRA_OPTIONS} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Optionally pb pin fixup +${OPENFPGA_PB_PIN_FIXUP_COMMAND} + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing --group_tile ${OPENFPGA_GROUP_TILE_CONFIG_FILE} #--verbose + +# Write fabric phyiscal pin location to file +write_fabric_pin_physical_location --file ${OPENFPGA_FABRIC_PIN_PHY_LOC_FILE} ${OPENFPGA_FABRIC_PIN_PHY_LOC_MODULE} --verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} + +# Write the SDC files for PnR backend +# - Turn on every options here +# FIXME: Not supported yet. +#write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +#write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +#write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga index ba0553733..990476956 100644 --- a/openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga @@ -27,11 +27,12 @@ build_fabric --compress_routing #--verbose # Write the fabric hierarchy of module graph to a file # This is used by hierarchical PnR flows -write_fabric_hierarchy --file ./fabric_hierarchy.txt +write_fabric_hierarchy --file ${OPENFPGA_OUTPUT_DIR}/mux_modules.yaml --depth 1 --module (grid|cbx|cby|sb)* --filter *mux*_size([0-9]+) --verbose --exclude_empty_modules # Write the fabric I/O attributes to a file # This is used by pin constraint files write_fabric_io_info --file ${OPENFPGA_OUTPUT_DIR}/fabric_io_location.xml --verbose --no_time_stamp +write_fabric_pin_physical_location --file ${OPENFPGA_OUTPUT_DIR}/fabric_pin_phy_loc.xml --verbose --no_time_stamp --module * # Write gsb to XML write_gsb_to_xml --file ${OPENFPGA_OUTPUT_DIR}/gsb_xml --verbose @@ -65,7 +66,7 @@ write_fabric_verilog --file ${OPENFPGA_OUTPUT_DIR} --explicit_port_mapping --inc # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ${OPENFPGA_OUTPUT_DIR} --explicit_port_mapping --no_time_stamp +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ${OPENFPGA_OUTPUT_DIR} --explicit_port_mapping --no_time_stamp ${OPENFPGA_PRECONFIG_FABRIC_WRAPPER_DUMP_WAVEFORM} write_preconfigured_testbench --file ${OPENFPGA_OUTPUT_DIR} --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --use_relative_path --explicit_port_mapping --no_time_stamp # Write the SDC files for PnR backend diff --git a/openfpga_flow/openfpga_shell_scripts/preload_rr_graph_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/preload_rr_graph_example_script.openfpga new file mode 100644 index 000000000..bf3d3b4e1 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/preload_rr_graph_example_script.openfpga @@ -0,0 +1,76 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr_standalone ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --pack --write_rr_graph ${OPENFPGA_VPR_RR_GRAPH_FILE} +# Do NOT know why! If we run full flow using vpr_standlone, running vpr full flow again will cause packing errors! Should fix this later!!! +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --place --route --read_rr_graph ${OPENFPGA_VPR_RR_GRAPH_FILE} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --time_unit ns --flatten_names --file ./SDC +write_pnr_sdc --time_unit ns --flatten_names --hierarchical --file ./SDC_leaf + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 08f3f86b0..c4b3ebcb8 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -2,7 +2,6 @@ set -e source openfpga.sh -PYTHON_EXEC=python3.8 ############################################### # OpenFPGA Shell with VPR8 ############################################## @@ -15,6 +14,10 @@ echo -e "Test source commands in openfpga shell" run-task basic_tests/source_command/source_string $@ run-task basic_tests/source_command/source_file $@ +echo -e "Testing preloading rr_graph" +run-task basic_tests/preload_rr_graph/preload_rr_graph_xml $@ +run-task basic_tests/preload_rr_graph/preload_rr_graph_bin $@ + echo -e "Testing testbenches using fpga core wrapper" run-task basic_tests/full_testbench/fpga_core_wrapper $@ run-task basic_tests/full_testbench/fpga_core_wrapper_naming_rules $@ @@ -78,6 +81,7 @@ run-task basic_tests/full_testbench/ql_memory_bank $@ run-task basic_tests/full_testbench/ql_memory_bank_use_wlr $@ run-task basic_tests/full_testbench/multi_region_ql_memory_bank $@ run-task basic_tests/full_testbench/ql_memory_bank_flatten $@ +run-task basic_tests/full_testbench/ql_memory_bank_flatten_defined_wl $@ run-task basic_tests/full_testbench/ql_memory_bank_flatten_use_wlr $@ run-task basic_tests/full_testbench/ql_memory_bank_shift_register $@ run-task basic_tests/full_testbench/ql_memory_bank_shift_register_use_wlr $@ @@ -171,6 +175,8 @@ echo -e "Testing K4N4 support clock generation by internal resources"; run-task basic_tests/k4_series/k4n4_clk_gen $@ echo -e "Testing K4N4 support reset generation by internal resources"; run-task basic_tests/k4_series/k4n4_rst_gen $@ +echo -e "Testing enhanced connection blocks" +run-task basic_tests/k4_series/k4n4_ecb $@ echo -e "Testing different tile organizations"; echo -e "Testing tiles with pins only on top and left sides"; @@ -195,6 +201,7 @@ run-task basic_tests/tile_organization/homo_fabric_tile_global_tile_clock $@ run-task basic_tests/tile_organization/homo_fabric_tile_adder_chain $@ run-task basic_tests/tile_organization/homo_fabric_tile_clkntwk $@ run-task basic_tests/tile_organization/hetero_fabric_tile $@ +run-task basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig $@ echo -e "Testing group config block"; run-task basic_tests/group_config_block/group_config_block_homo_full_testbench $@ @@ -252,6 +259,12 @@ run-task basic_tests/write_gsb/write_gsb_to_xml_compress_routing $@ run-task basic_tests/write_gsb/write_unique_gsb_to_xml $@ run-task basic_tests/write_gsb/write_unique_gsb_to_xml_compress_routing $@ +echo -e "Testing fabric pin physical location file" +run-task basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_default $@ +run-task basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles $@ +run-task basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_show_invalid_sides $@ +run-task basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_wildcards $@ + echo -e "Testing bus group features"; run-task basic_tests/bus_group/preconfig_testbench_explicit_mapping $@ run-task basic_tests/bus_group/preconfig_testbench_implicit_mapping $@ @@ -279,6 +292,7 @@ echo -e "Testing output files without time stamp"; run-task basic_tests/no_time_stamp/device_1x1 $@ run-task basic_tests/no_time_stamp/device_4x4 $@ run-task basic_tests/no_time_stamp/no_cout_in_gsb $@ +run-task basic_tests/no_time_stamp/dump_waveform $@ # Run git-diff to ensure no changes on the golden netlists # Switch to root path in case users are running the tests in another location cd ${OPENFPGA_PATH} diff --git a/openfpga_flow/regression_test_scripts/basic_reg_yosys_only_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_yosys_only_test.sh index 1396d27c2..920239641 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_yosys_only_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_yosys_only_test.sh @@ -2,7 +2,6 @@ set -e source openfpga.sh -PYTHON_EXEC=python3.8 ############################################### # OpenFPGA Shell with VPR8 ############################################## diff --git a/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh index 8d46be27f..174b4cabe 100755 --- a/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh @@ -2,7 +2,6 @@ set -e source openfpga.sh -PYTHON_EXEC=python3.8 ############################################### # OpenFPGA Shell with VPR8 ############################################## @@ -29,6 +28,7 @@ run-task fpga_bitstream/load_external_architecture_bitstream $@ echo -e "Testing repacker capability in identifying wire LUTs"; run-task fpga_bitstream/repack_wire_lut $@ run-task fpga_bitstream/repack_wire_lut_strong $@ +run-task fpga_bitstream/repack_ignore_nets $@ echo -e "Testing overloading default paths for programmable interconnect when generating bitstream"; run-task fpga_bitstream/overload_mux_default_path $@ diff --git a/openfpga_flow/regression_test_scripts/fpga_sdc_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_sdc_reg_test.sh index 084b0ea20..6760cf9fe 100755 --- a/openfpga_flow/regression_test_scripts/fpga_sdc_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/fpga_sdc_reg_test.sh @@ -2,7 +2,6 @@ set -e source openfpga.sh -PYTHON_EXEC=python3.8 ############################################### # OpenFPGA Shell with VPR8 ############################################## diff --git a/openfpga_flow/regression_test_scripts/fpga_spice_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_spice_reg_test.sh index c003f5d93..dee7d4f96 100755 --- a/openfpga_flow/regression_test_scripts/fpga_spice_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/fpga_spice_reg_test.sh @@ -2,7 +2,6 @@ set -e source openfpga.sh -PYTHON_EXEC=python3.8 ############################################### # OpenFPGA Shell with VPR8 ############################################## diff --git a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh index 46bf5cba9..c716757ab 100755 --- a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh @@ -2,7 +2,6 @@ set -e source openfpga.sh -PYTHON_EXEC=python3.8 ############################################### # OpenFPGA Shell with VPR8 ############################################## diff --git a/openfpga_flow/regression_test_scripts/iwls_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/iwls_benchmark_reg_test.sh index 4b37f6da7..ddbce4590 100755 --- a/openfpga_flow/regression_test_scripts/iwls_benchmark_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/iwls_benchmark_reg_test.sh @@ -2,7 +2,6 @@ set -e source openfpga.sh -PYTHON_EXEC=python3.8 ############################################### # OpenFPGA Shell with VPR8 ############################################## diff --git a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh index cb7b41252..b5903ed95 100755 --- a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh @@ -2,7 +2,6 @@ set -e source openfpga.sh -PYTHON_EXEC=python3.8 ############################################### # OpenFPGA Shell with VPR8 ############################################## diff --git a/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh b/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh index 2279a5c86..18eee18e2 100755 --- a/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh @@ -2,7 +2,6 @@ set -e source openfpga.sh -PYTHON_EXEC=python3.8 ############################################### # OpenFPGA Shell with VPR8 ############################################## diff --git a/openfpga_flow/regression_test_scripts/vtr_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/vtr_benchmark_reg_test.sh index 8bbc32436..99ca2c4c5 100755 --- a/openfpga_flow/regression_test_scripts/vtr_benchmark_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/vtr_benchmark_reg_test.sh @@ -2,7 +2,6 @@ set -e source openfpga.sh -PYTHON_EXEC=python3.8 ############################################### # OpenFPGA Shell with VPR8 ############################################## diff --git a/openfpga_flow/scripts/arch_file_updater.py b/openfpga_flow/scripts/arch_file_updater.py index 3538ec7f3..1ef9c3786 100644 --- a/openfpga_flow/scripts/arch_file_updater.py +++ b/openfpga_flow/scripts/arch_file_updater.py @@ -26,6 +26,7 @@ error_codes = {"SUCCESS": 0, "ERROR": 1, "OPTION_ERROR": 2, "FILE_ERROR": 3} ##################################################################### logging.basicConfig(format="%(levelname)s: %(message)s", level=logging.INFO) + ##################################################################### # Upgrade an architecture XML file from version 1.1 syntax to version 1.2 # Change rules: diff --git a/openfpga_flow/scripts/io_sequence_visualizer.py b/openfpga_flow/scripts/io_sequence_visualizer.py index d80acf1f2..cf435f217 100644 --- a/openfpga_flow/scripts/io_sequence_visualizer.py +++ b/openfpga_flow/scripts/io_sequence_visualizer.py @@ -13,6 +13,7 @@ This example demonstrates the ``OpenFPGA_Arch`` class which parses the Author: Ganesh Gore """ + import math import svgwrite from svgwrite.container import Group diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 3ad7bec8f..1cb3bc8a6 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -674,9 +674,11 @@ def create_yosys_params(): ys_params["READ_HDL_FILE"] += " ".join( [ "verific", - "-L " + ys_params["VERIFIC_SEARCH_LIB"] - if "VERIFIC_SEARCH_LIB" in ys_params - else "", + ( + "-L " + ys_params["VERIFIC_SEARCH_LIB"] + if "VERIFIC_SEARCH_LIB" in ys_params + else "" + ), standard, " ".join([shlex.quote(src) for src in sources]), "\n", diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_flatten_defined_wl/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_flatten_defined_wl/config/task.conf new file mode 100644 index 000000000..8e56d8437 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_flatten_defined_wl/config/task.conf @@ -0,0 +1,45 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbankflatten_defined_wl_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf index 8676f91ba..9e5d2f460 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf @@ -16,10 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_fix_routeW_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=auto +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=40 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile/config/task.conf index d75851ad9..d7f7a848c 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile/config/task.conf @@ -16,10 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_fix_routeW_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2_hybrid_io +openfpga_vpr_route_chan_width=60 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile_port_merge/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile_port_merge/config/task.conf index adbbaa2cb..062cdd91f 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile_port_merge/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile_port_merge/config/task.conf @@ -16,10 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_fix_routeW_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClkMergeSubtilePort_registerable_io_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2_hybrid_io +openfpga_vpr_route_chan_width=60 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_ecb/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_ecb/config/task.conf new file mode 100644 index 000000000..87f77596d --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_ecb/config/task.conf @@ -0,0 +1,37 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_pbPinFixup_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_ecb_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_device_layout=2x2 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBr_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/config/task.conf b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/config/task.conf index f1e22ed97..50daf4584 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/config/task.conf @@ -22,6 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio openfpga_vpr_device_layout = auto openfpga_vpr_route_chan_width = 26 openfpga_output_dir=${PATH:TASK_DIR}/golden_outputs_no_time_stamp +openfpga_preconfig_fabric_wrapper_dump_waveform= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v index c0daea5f7..6ed9c4edf 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v @@ -47,7 +47,7 @@ module and2_top_formal_verification_random_tb; initial begin clk[0] <= 1'b0; while(1) begin - #0.4628907144 + #0.4880859554 clk[0] <= !clk[0]; end end @@ -106,7 +106,7 @@ initial begin $timeformat(-9, 2, "ns", 20); $display("Simulation start"); // ----- Can be changed by the user for his/her need ------- - #6.480470181 + #6.833203316 if(nb_error == 0) begin $display("Simulation Succeed"); end else begin diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc index fa1a05891..8237fc2f9 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc @@ -9,14 +9,14 @@ ################################################## # Create clock ################################################## -create_clock clk[0] -period 9.25781396e-10 -waveform {0 4.62890698e-10} +create_clock clk[0] -period 9.761719211e-10 -waveform {0 4.880859605e-10} ################################################## # Create input and output delays for used I/Os ################################################## -set_input_delay -clock clk[0] -max 9.25781396e-10 gfpga_pad_GPIO_PAD[11] -set_input_delay -clock clk[0] -max 9.25781396e-10 gfpga_pad_GPIO_PAD[14] -set_output_delay -clock clk[0] -max 9.25781396e-10 gfpga_pad_GPIO_PAD[1] +set_input_delay -clock clk[0] -max 9.761719211e-10 gfpga_pad_GPIO_PAD[11] +set_input_delay -clock clk[0] -max 9.761719211e-10 gfpga_pad_GPIO_PAD[14] +set_output_delay -clock clk[0] -max 9.761719211e-10 gfpga_pad_GPIO_PAD[1] ################################################## # Disable timing for unused I/Os diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_pin_phy_loc.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_pin_phy_loc.xml new file mode 100644 index 000000000..603d120a5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_pin_phy_loc.xml @@ -0,0 +1,644 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/global_ports.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/global_ports.sdc index 0cf7373f8..f072bac09 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/global_ports.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/global_ports.sdc @@ -14,7 +14,7 @@ set_units -time s ################################################## # Create clock ################################################## -create_clock -name clk[0] -period 9.25781396e-10 -waveform {0 4.62890698e-10} [get_ports {clk[0]}] +create_clock -name clk[0] -period 9.761719211e-10 -waveform {0 4.880859605e-10} [get_ports {clk[0]}] ################################################## # Create programmable clock ################################################## diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml index 97758d454..6a92006a5 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml @@ -1,132 +1,132 @@ - - - + + + - - + + - - + + - - + + - - + + - - + + - - - + + + - - + + - - + + - + - + - + - - + + - - - + + + - - - + + + - - + + - - + + - - + + - - + + - - - + + + - - - + + + - - + + - + - + - + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml index 750160da5..24b0e8590 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml @@ -1,130 +1,130 @@ - - - + + + - - + + - - + + - - + + - - + + - - + + - - - + + + - - + + - - + + - + - + - + - - + + - - - + + + - - - + + + - - + + - - + + - - + + - - + + - - + + - - - + + + - - + + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml index 22e827258..10e1516e5 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml @@ -1,132 +1,132 @@ - - - + + + - - - + + + - - + + - - + + - - + + - - + + - - + + - - - + + + - - + + - + - + - + - + - - - + + + - - - + + + - - + + - - + + - - + + - - + + - - - + + + - - - + + + - - + + - + - + - + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml index 483099103..7725a1d9d 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml @@ -1,130 +1,130 @@ - - - + + + - - + + - - + + - - + + - - + + - - + + - - - + + + - - + + - - + + - + - + - + - - + + - - - + + + - - + + - - + + - - + + - - + + - - + + - - - + + + - - + + - - + + - + - + - + - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/mux_modules.yaml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/mux_modules.yaml new file mode 100644 index 000000000..5180e81ee --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/mux_modules.yaml @@ -0,0 +1,24 @@ +sb_0__0_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size3 + - mux_tree_tapbuf_size2 +sb_0__1_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size3 + - mux_tree_tapbuf_size2 +sb_1__0_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size3 + - mux_tree_tapbuf_size2 +sb_1__1_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size3 + - mux_tree_tapbuf_size2 +cbx_1__0_: + - mux_tree_tapbuf_size6 +cbx_1__1_: + - mux_tree_tapbuf_size6 +cby_0__1_: + - mux_tree_tapbuf_size6 +cby_1__1_: + - mux_tree_tapbuf_size6 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/config/task.conf b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/config/task.conf index 0a79fa359..8514c1877 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/config/task.conf @@ -22,6 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio openfpga_vpr_device_layout = 4x4 openfpga_vpr_route_chan_width = 20 openfpga_output_dir=${PATH:TASK_DIR}/golden_outputs_no_time_stamp +openfpga_preconfig_fabric_wrapper_dump_waveform= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v index 40a28f3da..5a6b6b31a 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v @@ -47,7 +47,7 @@ module and2_top_formal_verification_random_tb; initial begin clk[0] <= 1'b0; while(1) begin - #0.6573184729 + #0.8625563979 clk[0] <= !clk[0]; end end @@ -106,7 +106,7 @@ initial begin $timeformat(-9, 2, "ns", 20); $display("Simulation start"); // ----- Can be changed by the user for his/her need ------- - #9.202458382 + #12.07578945 if(nb_error == 0) begin $display("Simulation Succeed"); end else begin diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc index 7053e16d9..897ef728e 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc @@ -9,14 +9,14 @@ ################################################## # Create clock ################################################## -create_clock clk[0] -period 1.314636955e-09 -waveform {0 6.573184774e-10} +create_clock clk[0] -period 1.725112719e-09 -waveform {0 8.625563597e-10} ################################################## # Create input and output delays for used I/Os ################################################## -set_input_delay -clock clk[0] -max 1.314636955e-09 gfpga_pad_GPIO_PAD[38] -set_input_delay -clock clk[0] -max 1.314636955e-09 gfpga_pad_GPIO_PAD[58] -set_output_delay -clock clk[0] -max 1.314636955e-09 gfpga_pad_GPIO_PAD[17] +set_input_delay -clock clk[0] -max 1.725112719e-09 gfpga_pad_GPIO_PAD[38] +set_input_delay -clock clk[0] -max 1.725112719e-09 gfpga_pad_GPIO_PAD[58] +set_output_delay -clock clk[0] -max 1.725112719e-09 gfpga_pad_GPIO_PAD[17] ################################################## # Disable timing for unused I/Os diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_pin_phy_loc.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_pin_phy_loc.xml new file mode 100644 index 000000000..e30e971a2 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_pin_phy_loc.xml @@ -0,0 +1,1061 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/global_ports.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/global_ports.sdc index 0f5e878af..f87326299 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/global_ports.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/global_ports.sdc @@ -14,7 +14,7 @@ set_units -time s ################################################## # Create clock ################################################## -create_clock -name clk[0] -period 1.314636955e-09 -waveform {0 6.573184774e-10} [get_ports {clk[0]}] +create_clock -name clk[0] -period 1.725112719e-09 -waveform {0 8.625563597e-10} [get_ports {clk[0]}] ################################################## # Create programmable clock ################################################## diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml index 5b8aaa29e..2eb261e42 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml @@ -1,38 +1,38 @@ - + - + - + - + - + - + - + - + - + @@ -40,39 +40,39 @@ - + - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml index 0942b3fef..c3143bad3 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml @@ -1,8 +1,8 @@ - - - + + + @@ -20,9 +20,9 @@ - - - + + + @@ -39,9 +39,9 @@ - - - + + + @@ -53,12 +53,12 @@ - + - + @@ -102,9 +102,9 @@ - - - + + + @@ -122,9 +122,9 @@ - - - + + + @@ -141,9 +141,9 @@ - - - + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__2_.xml index f2d096157..71df950e0 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__2_.xml @@ -1,8 +1,8 @@ - - - + + + @@ -20,9 +20,9 @@ - - - + + + @@ -39,9 +39,9 @@ - - - + + + @@ -53,12 +53,12 @@ - + - + @@ -102,9 +102,9 @@ - - - + + + @@ -122,9 +122,9 @@ - - - + + + @@ -141,9 +141,9 @@ - - - + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__3_.xml index 8ff0435ff..651f17b42 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__3_.xml @@ -1,8 +1,8 @@ - - - + + + @@ -20,9 +20,9 @@ - - - + + + @@ -39,9 +39,9 @@ - - - + + + @@ -53,12 +53,12 @@ - + - + @@ -102,9 +102,9 @@ - - - + + + @@ -122,9 +122,9 @@ - - - + + + @@ -141,9 +141,9 @@ - - - + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__4_.xml index ed55dccd1..2c9833855 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_0__4_.xml @@ -1,38 +1,38 @@ - + - + - + - + - + - + - + - + - + @@ -40,39 +40,39 @@ - + - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml index 2c59dc413..1616d818a 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml @@ -1,13 +1,13 @@ - + - + @@ -45,9 +45,9 @@ - - - + + + @@ -66,9 +66,9 @@ - - - + + + @@ -85,9 +85,9 @@ - - - + + + @@ -102,9 +102,9 @@ - - - + + + @@ -121,9 +121,9 @@ - - - + + + @@ -140,9 +140,9 @@ - - - + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml index 1234f6b19..6db375e4b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml @@ -1,6 +1,6 @@ - + @@ -22,7 +22,7 @@ - + @@ -59,7 +59,7 @@ - + @@ -81,7 +81,7 @@ - + @@ -118,7 +118,7 @@ - + @@ -139,7 +139,7 @@ - + @@ -178,7 +178,7 @@ - + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__2_.xml index ea27be117..42aff2b61 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__2_.xml @@ -1,6 +1,6 @@ - + @@ -22,7 +22,7 @@ - + @@ -59,7 +59,7 @@ - + @@ -81,7 +81,7 @@ - + @@ -118,7 +118,7 @@ - + @@ -139,7 +139,7 @@ - + @@ -178,7 +178,7 @@ - + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__3_.xml index 07e35b230..9b60f95f5 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__3_.xml @@ -1,6 +1,6 @@ - + @@ -22,7 +22,7 @@ - + @@ -59,7 +59,7 @@ - + @@ -81,7 +81,7 @@ - + @@ -118,7 +118,7 @@ - + @@ -139,7 +139,7 @@ - + @@ -178,7 +178,7 @@ - + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__4_.xml index 81983daa6..bc2901f73 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_1__4_.xml @@ -1,8 +1,8 @@ - - - + + + @@ -20,9 +20,9 @@ - - - + + + @@ -40,9 +40,9 @@ - - - + + + @@ -53,12 +53,12 @@ - + - + @@ -101,9 +101,9 @@ - - - + + + @@ -121,9 +121,9 @@ - - - + + + @@ -140,9 +140,9 @@ - - - + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__0_.xml index ae777c8a1..bb04d7917 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__0_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__0_.xml @@ -1,13 +1,13 @@ - + - + @@ -45,9 +45,9 @@ - - - + + + @@ -66,9 +66,9 @@ - - - + + + @@ -85,9 +85,9 @@ - - - + + + @@ -102,9 +102,9 @@ - - - + + + @@ -121,9 +121,9 @@ - - - + + + @@ -140,9 +140,9 @@ - - - + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__1_.xml index 01a132814..8ec5b638b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__1_.xml @@ -1,6 +1,6 @@ - + @@ -22,7 +22,7 @@ - + @@ -59,7 +59,7 @@ - + @@ -81,7 +81,7 @@ - + @@ -118,7 +118,7 @@ - + @@ -139,7 +139,7 @@ - + @@ -178,7 +178,7 @@ - + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__2_.xml index e57c4777c..3c805285b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__2_.xml @@ -1,6 +1,6 @@ - + @@ -22,7 +22,7 @@ - + @@ -59,7 +59,7 @@ - + @@ -81,7 +81,7 @@ - + @@ -118,7 +118,7 @@ - + @@ -139,7 +139,7 @@ - + @@ -178,7 +178,7 @@ - + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__3_.xml index 42d409d65..e377195bc 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__3_.xml @@ -1,6 +1,6 @@ - + @@ -22,7 +22,7 @@ - + @@ -59,7 +59,7 @@ - + @@ -81,7 +81,7 @@ - + @@ -118,7 +118,7 @@ - + @@ -139,7 +139,7 @@ - + @@ -178,7 +178,7 @@ - + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__4_.xml index f7b656277..58a624fb3 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_2__4_.xml @@ -1,8 +1,8 @@ - - - + + + @@ -20,9 +20,9 @@ - - - + + + @@ -40,9 +40,9 @@ - - - + + + @@ -53,12 +53,12 @@ - + - + @@ -101,9 +101,9 @@ - - - + + + @@ -121,9 +121,9 @@ - - - + + + @@ -140,9 +140,9 @@ - - - + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__0_.xml index 0e15d91bf..e55a850e7 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__0_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__0_.xml @@ -1,13 +1,13 @@ - + - + @@ -45,9 +45,9 @@ - - - + + + @@ -66,9 +66,9 @@ - - - + + + @@ -85,9 +85,9 @@ - - - + + + @@ -102,9 +102,9 @@ - - - + + + @@ -121,9 +121,9 @@ - - - + + + @@ -140,9 +140,9 @@ - - - + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__1_.xml index 57ee9f1b3..afecf8514 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__1_.xml @@ -1,6 +1,6 @@ - + @@ -22,7 +22,7 @@ - + @@ -59,7 +59,7 @@ - + @@ -81,7 +81,7 @@ - + @@ -118,7 +118,7 @@ - + @@ -139,7 +139,7 @@ - + @@ -178,7 +178,7 @@ - + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__2_.xml index ed94af807..89b614956 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__2_.xml @@ -1,6 +1,6 @@ - + @@ -22,7 +22,7 @@ - + @@ -59,7 +59,7 @@ - + @@ -81,7 +81,7 @@ - + @@ -118,7 +118,7 @@ - + @@ -139,7 +139,7 @@ - + @@ -178,7 +178,7 @@ - + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__3_.xml index 233917eae..00f859e39 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__3_.xml @@ -1,6 +1,6 @@ - + @@ -22,7 +22,7 @@ - + @@ -59,7 +59,7 @@ - + @@ -81,7 +81,7 @@ - + @@ -118,7 +118,7 @@ - + @@ -139,7 +139,7 @@ - + @@ -178,7 +178,7 @@ - + @@ -199,7 +199,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__4_.xml index 784ab10d7..05eed197e 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_3__4_.xml @@ -1,8 +1,8 @@ - - - + + + @@ -20,9 +20,9 @@ - - - + + + @@ -40,9 +40,9 @@ - - - + + + @@ -53,12 +53,12 @@ - + - + @@ -101,9 +101,9 @@ - - - + + + @@ -121,9 +121,9 @@ - - - + + + @@ -140,9 +140,9 @@ - - - + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__0_.xml index bd9e172e7..962a9f6b9 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__0_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__0_.xml @@ -1,38 +1,38 @@ - + - + - + - + - + - + - + - + - + @@ -40,39 +40,39 @@ - + - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__1_.xml index 37b4d5474..bf33c82ca 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__1_.xml @@ -1,8 +1,8 @@ - - - + + + @@ -21,9 +21,9 @@ - - - + + + @@ -40,9 +40,9 @@ - - - + + + @@ -56,9 +56,9 @@ - - - + + + @@ -75,9 +75,9 @@ - - - + + + @@ -94,9 +94,9 @@ - - - + + + @@ -108,12 +108,12 @@ - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__2_.xml index f36ebf9dc..d19778757 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__2_.xml @@ -1,8 +1,8 @@ - - - + + + @@ -21,9 +21,9 @@ - - - + + + @@ -40,9 +40,9 @@ - - - + + + @@ -56,9 +56,9 @@ - - - + + + @@ -75,9 +75,9 @@ - - - + + + @@ -94,9 +94,9 @@ - - - + + + @@ -108,12 +108,12 @@ - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__3_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__3_.xml index 9d949aba7..ddda52b6e 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__3_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__3_.xml @@ -1,8 +1,8 @@ - - - + + + @@ -21,9 +21,9 @@ - - - + + + @@ -40,9 +40,9 @@ - - - + + + @@ -56,9 +56,9 @@ - - - + + + @@ -75,9 +75,9 @@ - - - + + + @@ -94,9 +94,9 @@ - - - + + + @@ -108,12 +108,12 @@ - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__4_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__4_.xml index 9ebabf7f5..6314d9a29 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__4_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/sb_4__4_.xml @@ -1,38 +1,38 @@ - + - + - + - + - + - + - + - + - + @@ -40,39 +40,39 @@ - + - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/mux_modules.yaml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/mux_modules.yaml new file mode 100644 index 000000000..2d7d586c9 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/mux_modules.yaml @@ -0,0 +1,55 @@ +sb_0__0_: + - mux_tree_tapbuf_size2 +sb_0__1_: + - mux_tree_tapbuf_size9 + - mux_tree_tapbuf_size8 + - mux_tree_tapbuf_size3 + - mux_tree_tapbuf_size2 +sb_0__4_: + - mux_tree_tapbuf_size2 +sb_1__0_: + - mux_tree_tapbuf_size5 + - mux_tree_tapbuf_size3 + - mux_tree_tapbuf_size2 + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size9 + - mux_tree_tapbuf_size8 + - mux_tree_tapbuf_size10 +sb_1__1_: + - mux_tree_tapbuf_size11 + - mux_tree_tapbuf_size9 + - mux_tree_tapbuf_size10 + - mux_tree_tapbuf_size8 +sb_1__4_: + - mux_tree_tapbuf_size9 + - mux_tree_tapbuf_size8 + - mux_tree_tapbuf_size3 + - mux_tree_tapbuf_size2 +sb_4__0_: + - mux_tree_tapbuf_size2 +sb_4__1_: + - mux_tree_tapbuf_size10 + - mux_tree_tapbuf_size8 + - mux_tree_tapbuf_size9 + - mux_tree_tapbuf_size3 + - mux_tree_tapbuf_size2 +sb_4__4_: + - mux_tree_tapbuf_size2 +cbx_1__0_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size2 +cbx_1__1_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size2 +cbx_1__4_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size2 +cby_0__1_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size2 +cby_1__1_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size2 +cby_4__1_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size2 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/config/task.conf b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/config/task.conf new file mode 100644 index 000000000..702110f40 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/config/task.conf @@ -0,0 +1,37 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_abspath_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout = auto +openfpga_vpr_route_chan_width = 26 +openfpga_output_dir=${PATH:TASK_DIR}/golden_outputs_no_time_stamp +openfpga_preconfig_fabric_wrapper_dump_waveform=--dump_waveform + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v new file mode 100644 index 000000000..6ed9c4edf --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v @@ -0,0 +1,120 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: FPGA Verilog Testbench for Formal Top-level netlist of Design: and2 +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +module and2_top_formal_verification_random_tb; +// ----- Default clock port is added here since benchmark does not contain one ------- + reg [0:0] clk; + +// ----- Shared inputs ------- + reg [0:0] a; + reg [0:0] b; + +// ----- FPGA fabric outputs ------- + wire [0:0] c_gfpga; + +// ----- Benchmark outputs ------- + wire [0:0] c_bench; + +// ----- Output vectors checking flags ------- + reg [0:0] c_flag; + +// ----- Error counter ------- + integer nb_error= 0; + +// ----- FPGA fabric instanciation ------- + and2_top_formal_verification FPGA_DUT( + .a(a), + .b(b), + .c(c_gfpga) + ); +// ----- End FPGA Fabric Instanication ------- + +// ----- Reference Benchmark Instanication ------- + and2 REF_DUT( + .a(a), + .b(b), + .c(c_bench) + ); +// ----- End reference Benchmark Instanication ------- + +// ----- Clock 'clk' Initialization ------- + initial begin + clk[0] <= 1'b0; + while(1) begin + #0.4880859554 + clk[0] <= !clk[0]; + end + end + +// ----- Begin reset signal generation ----- +// ----- End reset signal generation ----- + +// ----- Input Initialization ------- + initial begin + a <= 1'b0; + b <= 1'b0; + + c_flag[0] <= 1'b0; + end + +// ----- Input Stimulus ------- + always@(negedge clk[0]) begin + a <= $random; + b <= $random; + end + +// ----- Begin checking output vectors ------- +// ----- Skip the first falling edge of clock, it is for initialization ------- + reg [0:0] sim_start; + + always@(negedge clk[0]) begin + if (1'b1 == sim_start[0]) begin + sim_start[0] <= ~sim_start[0]; + end else +begin + if(!(c_gfpga === c_bench) && !(c_bench === 1'bx)) begin + c_flag <= 1'b1; + end else begin + c_flag<= 1'b0; + end + end + end + + always@(posedge c_flag) begin + if(c_flag) begin + nb_error = nb_error + 1; + $display("Mismatch on c_gfpga at time = %t", $realtime); + end + end + + +// ----- Begin output waveform to VCD file------- + initial begin + $dumpfile("and2_formal.vcd"); + $dumpvars(1, and2_top_formal_verification_random_tb); + end +// ----- END output waveform to VCD file ------- + +initial begin + sim_start[0] <= 1'b1; + $timeformat(-9, 2, "ns", 20); + $display("Simulation start"); +// ----- Can be changed by the user for his/her need ------- + #6.833203316 + if(nb_error == 0) begin + $display("Simulation Succeed"); + end else begin + $display("Simulation Failed with %d error(s)", nb_error); + end + $finish; +end + +endmodule +// ----- END Verilog module for and2_top_formal_verification_random_tb ----- + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc new file mode 100644 index 000000000..8237fc2f9 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc @@ -0,0 +1,1829 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain for Timing/Power analysis on the mapped FPGA +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +################################################## +# Create clock +################################################## +create_clock clk[0] -period 9.761719211e-10 -waveform {0 4.880859605e-10} + +################################################## +# Create input and output delays for used I/Os +################################################## +set_input_delay -clock clk[0] -max 9.761719211e-10 gfpga_pad_GPIO_PAD[11] +set_input_delay -clock clk[0] -max 9.761719211e-10 gfpga_pad_GPIO_PAD[14] +set_output_delay -clock clk[0] -max 9.761719211e-10 gfpga_pad_GPIO_PAD[1] + +################################################## +# Disable timing for unused I/Os +################################################## +set_disable_timing gfpga_pad_GPIO_PAD[0] +set_disable_timing gfpga_pad_GPIO_PAD[2] +set_disable_timing gfpga_pad_GPIO_PAD[3] +set_disable_timing gfpga_pad_GPIO_PAD[4] +set_disable_timing gfpga_pad_GPIO_PAD[5] +set_disable_timing gfpga_pad_GPIO_PAD[6] +set_disable_timing gfpga_pad_GPIO_PAD[7] +set_disable_timing gfpga_pad_GPIO_PAD[8] +set_disable_timing gfpga_pad_GPIO_PAD[9] +set_disable_timing gfpga_pad_GPIO_PAD[10] +set_disable_timing gfpga_pad_GPIO_PAD[12] +set_disable_timing gfpga_pad_GPIO_PAD[13] +set_disable_timing gfpga_pad_GPIO_PAD[15] +set_disable_timing gfpga_pad_GPIO_PAD[16] +set_disable_timing gfpga_pad_GPIO_PAD[17] +set_disable_timing gfpga_pad_GPIO_PAD[18] +set_disable_timing gfpga_pad_GPIO_PAD[19] +set_disable_timing gfpga_pad_GPIO_PAD[20] +set_disable_timing gfpga_pad_GPIO_PAD[21] +set_disable_timing gfpga_pad_GPIO_PAD[22] +set_disable_timing gfpga_pad_GPIO_PAD[23] +set_disable_timing gfpga_pad_GPIO_PAD[24] +set_disable_timing gfpga_pad_GPIO_PAD[25] +set_disable_timing gfpga_pad_GPIO_PAD[26] +set_disable_timing gfpga_pad_GPIO_PAD[27] +set_disable_timing gfpga_pad_GPIO_PAD[28] +set_disable_timing gfpga_pad_GPIO_PAD[29] +set_disable_timing gfpga_pad_GPIO_PAD[30] +set_disable_timing gfpga_pad_GPIO_PAD[31] + +################################################## +# Disable timing for global ports +################################################## +set_disable_timing set[0] +set_disable_timing reset[0] +set_disable_timing prog_clk[0] +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_mode_default__lut*_*/lut*_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_mode_default__lut*_*/lut*_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/mem_ble*_out_*/DFF_*_/Q +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/mem_ble*_out_*/DFF_*_/QN +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_*_in_*/DFF_*_/Q +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_*_in_*/DFF_*_/QN +################################################## +# Disable timing for Connection block cbx_1__0_ +################################################## +set_disable_timing cbx_1__0_/chanx_left_in[0] +set_disable_timing cbx_1__0_/chanx_right_in[0] +set_disable_timing cbx_1__0_/chanx_left_in[1] +set_disable_timing cbx_1__0_/chanx_right_in[1] +set_disable_timing cbx_1__0_/chanx_left_in[2] +set_disable_timing cbx_1__0_/chanx_right_in[2] +set_disable_timing cbx_1__0_/chanx_left_in[3] +set_disable_timing cbx_1__0_/chanx_right_in[3] +set_disable_timing cbx_1__0_/chanx_left_in[4] +set_disable_timing cbx_1__0_/chanx_right_in[4] +set_disable_timing cbx_1__0_/chanx_left_in[5] +set_disable_timing cbx_1__0_/chanx_right_in[5] +set_disable_timing cbx_1__0_/chanx_left_in[6] +set_disable_timing cbx_1__0_/chanx_right_in[6] +set_disable_timing cbx_1__0_/chanx_left_in[7] +set_disable_timing cbx_1__0_/chanx_right_in[7] +set_disable_timing cbx_1__0_/chanx_left_in[8] +set_disable_timing cbx_1__0_/chanx_right_in[8] +set_disable_timing cbx_1__0_/chanx_left_in[9] +set_disable_timing cbx_1__0_/chanx_right_in[9] +set_disable_timing cbx_1__0_/chanx_left_in[10] +set_disable_timing cbx_1__0_/chanx_right_in[10] +set_disable_timing cbx_1__0_/chanx_left_in[11] +set_disable_timing cbx_1__0_/chanx_right_in[11] +set_disable_timing cbx_1__0_/chanx_left_in[12] +set_disable_timing cbx_1__0_/chanx_right_in[12] +set_disable_timing cbx_1__0_/chanx_left_out[0] +set_disable_timing cbx_1__0_/chanx_right_out[0] +set_disable_timing cbx_1__0_/chanx_left_out[1] +set_disable_timing cbx_1__0_/chanx_right_out[1] +set_disable_timing cbx_1__0_/chanx_left_out[2] +set_disable_timing cbx_1__0_/chanx_right_out[2] +set_disable_timing cbx_1__0_/chanx_left_out[3] +set_disable_timing cbx_1__0_/chanx_right_out[3] +set_disable_timing cbx_1__0_/chanx_left_out[4] +set_disable_timing cbx_1__0_/chanx_right_out[4] +set_disable_timing cbx_1__0_/chanx_left_out[5] +set_disable_timing cbx_1__0_/chanx_right_out[5] +set_disable_timing cbx_1__0_/chanx_left_out[6] +set_disable_timing cbx_1__0_/chanx_right_out[6] +set_disable_timing cbx_1__0_/chanx_left_out[7] +set_disable_timing cbx_1__0_/chanx_right_out[7] +set_disable_timing cbx_1__0_/chanx_left_out[8] +set_disable_timing cbx_1__0_/chanx_right_out[8] +set_disable_timing cbx_1__0_/chanx_left_out[9] +set_disable_timing cbx_1__0_/chanx_right_out[9] +set_disable_timing cbx_1__0_/chanx_left_out[10] +set_disable_timing cbx_1__0_/chanx_right_out[10] +set_disable_timing cbx_1__0_/chanx_left_out[11] +set_disable_timing cbx_1__0_/chanx_right_out[11] +set_disable_timing cbx_1__0_/chanx_left_out[12] +set_disable_timing cbx_1__0_/chanx_right_out[12] +set_disable_timing cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] +set_disable_timing cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] +set_disable_timing cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] +set_disable_timing cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] +set_disable_timing cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] +set_disable_timing cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] +set_disable_timing cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] +set_disable_timing cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] +set_disable_timing cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] +set_disable_timing cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] +set_disable_timing cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] +set_disable_timing cbx_1__0_/mux_bottom_ipin_0/in[1] +set_disable_timing cbx_1__0_/mux_bottom_ipin_1/in[1] +set_disable_timing cbx_1__0_/mux_top_ipin_4/in[1] +set_disable_timing cbx_1__0_/mux_bottom_ipin_0/in[0] +set_disable_timing cbx_1__0_/mux_bottom_ipin_1/in[0] +set_disable_timing cbx_1__0_/mux_top_ipin_4/in[0] +set_disable_timing cbx_1__0_/mux_bottom_ipin_1/in[3] +set_disable_timing cbx_1__0_/mux_bottom_ipin_2/in[1] +set_disable_timing cbx_1__0_/mux_top_ipin_5/in[1] +set_disable_timing cbx_1__0_/mux_bottom_ipin_1/in[2] +set_disable_timing cbx_1__0_/mux_bottom_ipin_2/in[0] +set_disable_timing cbx_1__0_/mux_top_ipin_5/in[0] +set_disable_timing cbx_1__0_/mux_bottom_ipin_2/in[3] +set_disable_timing cbx_1__0_/mux_top_ipin_0/in[1] +set_disable_timing cbx_1__0_/mux_top_ipin_6/in[1] +set_disable_timing cbx_1__0_/mux_bottom_ipin_2/in[2] +set_disable_timing cbx_1__0_/mux_top_ipin_0/in[0] +set_disable_timing cbx_1__0_/mux_top_ipin_6/in[0] +set_disable_timing cbx_1__0_/mux_top_ipin_0/in[3] +set_disable_timing cbx_1__0_/mux_top_ipin_1/in[1] +set_disable_timing cbx_1__0_/mux_top_ipin_7/in[1] +set_disable_timing cbx_1__0_/mux_top_ipin_0/in[2] +set_disable_timing cbx_1__0_/mux_top_ipin_1/in[0] +set_disable_timing cbx_1__0_/mux_top_ipin_7/in[0] +set_disable_timing cbx_1__0_/mux_top_ipin_1/in[3] +set_disable_timing cbx_1__0_/mux_top_ipin_2/in[1] +set_disable_timing cbx_1__0_/mux_top_ipin_1/in[2] +set_disable_timing cbx_1__0_/mux_top_ipin_2/in[0] +set_disable_timing cbx_1__0_/mux_top_ipin_2/in[3] +set_disable_timing cbx_1__0_/mux_top_ipin_3/in[1] +set_disable_timing cbx_1__0_/mux_top_ipin_2/in[2] +set_disable_timing cbx_1__0_/mux_top_ipin_3/in[0] +set_disable_timing cbx_1__0_/mux_bottom_ipin_0/in[3] +set_disable_timing cbx_1__0_/mux_top_ipin_3/in[3] +set_disable_timing cbx_1__0_/mux_top_ipin_4/in[3] +set_disable_timing cbx_1__0_/mux_bottom_ipin_0/in[2] +set_disable_timing cbx_1__0_/mux_top_ipin_3/in[2] +set_disable_timing cbx_1__0_/mux_top_ipin_4/in[2] +set_disable_timing cbx_1__0_/mux_bottom_ipin_1/in[5] +set_disable_timing cbx_1__0_/mux_top_ipin_4/in[5] +set_disable_timing cbx_1__0_/mux_top_ipin_5/in[3] +set_disable_timing cbx_1__0_/mux_bottom_ipin_1/in[4] +set_disable_timing cbx_1__0_/mux_top_ipin_4/in[4] +set_disable_timing cbx_1__0_/mux_top_ipin_5/in[2] +set_disable_timing cbx_1__0_/mux_bottom_ipin_2/in[5] +set_disable_timing cbx_1__0_/mux_top_ipin_5/in[5] +set_disable_timing cbx_1__0_/mux_top_ipin_6/in[3] +set_disable_timing cbx_1__0_/mux_bottom_ipin_2/in[4] +set_disable_timing cbx_1__0_/mux_top_ipin_5/in[4] +set_disable_timing cbx_1__0_/mux_top_ipin_6/in[2] +set_disable_timing cbx_1__0_/mux_top_ipin_0/in[5] +set_disable_timing cbx_1__0_/mux_top_ipin_6/in[5] +set_disable_timing cbx_1__0_/mux_top_ipin_7/in[3] +set_disable_timing cbx_1__0_/mux_top_ipin_0/in[4] +set_disable_timing cbx_1__0_/mux_top_ipin_6/in[4] +set_disable_timing cbx_1__0_/mux_top_ipin_7/in[2] +set_disable_timing cbx_1__0_/mux_top_ipin_1/in[5] +set_disable_timing cbx_1__0_/mux_top_ipin_7/in[5] +set_disable_timing cbx_1__0_/mux_top_ipin_1/in[4] +set_disable_timing cbx_1__0_/mux_top_ipin_7/in[4] +set_disable_timing cbx_1__0_/mux_top_ipin_2/in[5] +set_disable_timing cbx_1__0_/mux_top_ipin_2/in[4] +set_disable_timing cbx_1__0_/mux_bottom_ipin_0/in[5] +set_disable_timing cbx_1__0_/mux_top_ipin_3/in[5] +set_disable_timing cbx_1__0_/mux_bottom_ipin_0/in[4] +set_disable_timing cbx_1__0_/mux_top_ipin_3/in[4] +################################################## +# Disable timing for Connection block cbx_1__1_ +################################################## +set_disable_timing cbx_1__1_/chanx_left_in[0] +set_disable_timing cbx_1__1_/chanx_right_in[0] +set_disable_timing cbx_1__1_/chanx_left_in[1] +set_disable_timing cbx_1__1_/chanx_left_in[2] +set_disable_timing cbx_1__1_/chanx_right_in[2] +set_disable_timing cbx_1__1_/chanx_left_in[3] +set_disable_timing cbx_1__1_/chanx_right_in[3] +set_disable_timing cbx_1__1_/chanx_left_in[4] +set_disable_timing cbx_1__1_/chanx_right_in[4] +set_disable_timing cbx_1__1_/chanx_left_in[5] +set_disable_timing cbx_1__1_/chanx_right_in[5] +set_disable_timing cbx_1__1_/chanx_left_in[6] +set_disable_timing cbx_1__1_/chanx_right_in[6] +set_disable_timing cbx_1__1_/chanx_left_in[7] +set_disable_timing cbx_1__1_/chanx_right_in[7] +set_disable_timing cbx_1__1_/chanx_left_in[8] +set_disable_timing cbx_1__1_/chanx_right_in[8] +set_disable_timing cbx_1__1_/chanx_left_in[9] +set_disable_timing cbx_1__1_/chanx_right_in[9] +set_disable_timing cbx_1__1_/chanx_left_in[10] +set_disable_timing cbx_1__1_/chanx_right_in[10] +set_disable_timing cbx_1__1_/chanx_left_in[11] +set_disable_timing cbx_1__1_/chanx_right_in[11] +set_disable_timing cbx_1__1_/chanx_left_in[12] +set_disable_timing cbx_1__1_/chanx_right_in[12] +set_disable_timing cbx_1__1_/chanx_left_out[0] +set_disable_timing cbx_1__1_/chanx_right_out[0] +set_disable_timing cbx_1__1_/chanx_left_out[1] +set_disable_timing cbx_1__1_/chanx_left_out[2] +set_disable_timing cbx_1__1_/chanx_right_out[2] +set_disable_timing cbx_1__1_/chanx_left_out[3] +set_disable_timing cbx_1__1_/chanx_right_out[3] +set_disable_timing cbx_1__1_/chanx_left_out[4] +set_disable_timing cbx_1__1_/chanx_right_out[4] +set_disable_timing cbx_1__1_/chanx_left_out[5] +set_disable_timing cbx_1__1_/chanx_right_out[5] +set_disable_timing cbx_1__1_/chanx_left_out[6] +set_disable_timing cbx_1__1_/chanx_right_out[6] +set_disable_timing cbx_1__1_/chanx_left_out[7] +set_disable_timing cbx_1__1_/chanx_right_out[7] +set_disable_timing cbx_1__1_/chanx_left_out[8] +set_disable_timing cbx_1__1_/chanx_right_out[8] +set_disable_timing cbx_1__1_/chanx_left_out[9] +set_disable_timing cbx_1__1_/chanx_right_out[9] +set_disable_timing cbx_1__1_/chanx_left_out[10] +set_disable_timing cbx_1__1_/chanx_right_out[10] +set_disable_timing cbx_1__1_/chanx_left_out[11] +set_disable_timing cbx_1__1_/chanx_right_out[11] +set_disable_timing cbx_1__1_/chanx_left_out[12] +set_disable_timing cbx_1__1_/chanx_right_out[12] +set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] +set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] +set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] +set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] +set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] +set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] +set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] +set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] +set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] +set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] +set_disable_timing cbx_1__1_/mux_bottom_ipin_0/in[1] +set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[1] +set_disable_timing cbx_1__1_/mux_bottom_ipin_7/in[1] +set_disable_timing cbx_1__1_/mux_bottom_ipin_0/in[0] +set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[0] +set_disable_timing cbx_1__1_/mux_bottom_ipin_7/in[0] +set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[3] +set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[1] +set_disable_timing cbx_1__1_/mux_top_ipin_0/in[1] +set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[0] +set_disable_timing cbx_1__1_/mux_top_ipin_0/in[0] +set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[3] +set_disable_timing cbx_1__1_/mux_bottom_ipin_3/in[1] +set_disable_timing cbx_1__1_/mux_top_ipin_1/in[1] +set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[2] +set_disable_timing cbx_1__1_/mux_bottom_ipin_3/in[0] +set_disable_timing cbx_1__1_/mux_top_ipin_1/in[0] +set_disable_timing cbx_1__1_/mux_bottom_ipin_3/in[3] +set_disable_timing cbx_1__1_/mux_bottom_ipin_4/in[1] +set_disable_timing cbx_1__1_/mux_top_ipin_2/in[1] +set_disable_timing cbx_1__1_/mux_bottom_ipin_3/in[2] +set_disable_timing cbx_1__1_/mux_bottom_ipin_4/in[0] +set_disable_timing cbx_1__1_/mux_top_ipin_2/in[0] +set_disable_timing cbx_1__1_/mux_bottom_ipin_4/in[3] +set_disable_timing cbx_1__1_/mux_bottom_ipin_5/in[1] +set_disable_timing cbx_1__1_/mux_bottom_ipin_4/in[2] +set_disable_timing cbx_1__1_/mux_bottom_ipin_5/in[0] +set_disable_timing cbx_1__1_/mux_bottom_ipin_5/in[3] +set_disable_timing cbx_1__1_/mux_bottom_ipin_6/in[1] +set_disable_timing cbx_1__1_/mux_bottom_ipin_5/in[2] +set_disable_timing cbx_1__1_/mux_bottom_ipin_6/in[0] +set_disable_timing cbx_1__1_/mux_bottom_ipin_0/in[3] +set_disable_timing cbx_1__1_/mux_bottom_ipin_6/in[3] +set_disable_timing cbx_1__1_/mux_bottom_ipin_7/in[3] +set_disable_timing cbx_1__1_/mux_bottom_ipin_0/in[2] +set_disable_timing cbx_1__1_/mux_bottom_ipin_6/in[2] +set_disable_timing cbx_1__1_/mux_bottom_ipin_7/in[2] +set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[5] +set_disable_timing cbx_1__1_/mux_bottom_ipin_7/in[5] +set_disable_timing cbx_1__1_/mux_top_ipin_0/in[3] +set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[4] +set_disable_timing cbx_1__1_/mux_bottom_ipin_7/in[4] +set_disable_timing cbx_1__1_/mux_top_ipin_0/in[2] +set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[5] +set_disable_timing cbx_1__1_/mux_top_ipin_0/in[5] +set_disable_timing cbx_1__1_/mux_top_ipin_1/in[3] +set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[4] +set_disable_timing cbx_1__1_/mux_top_ipin_0/in[4] +set_disable_timing cbx_1__1_/mux_top_ipin_1/in[2] +set_disable_timing cbx_1__1_/mux_bottom_ipin_3/in[5] +set_disable_timing cbx_1__1_/mux_top_ipin_1/in[5] +set_disable_timing cbx_1__1_/mux_top_ipin_2/in[3] +set_disable_timing cbx_1__1_/mux_bottom_ipin_3/in[4] +set_disable_timing cbx_1__1_/mux_top_ipin_1/in[4] +set_disable_timing cbx_1__1_/mux_top_ipin_2/in[2] +set_disable_timing cbx_1__1_/mux_bottom_ipin_4/in[5] +set_disable_timing cbx_1__1_/mux_top_ipin_2/in[5] +set_disable_timing cbx_1__1_/mux_bottom_ipin_4/in[4] +set_disable_timing cbx_1__1_/mux_top_ipin_2/in[4] +set_disable_timing cbx_1__1_/mux_bottom_ipin_5/in[5] +set_disable_timing cbx_1__1_/mux_bottom_ipin_5/in[4] +set_disable_timing cbx_1__1_/mux_bottom_ipin_0/in[5] +set_disable_timing cbx_1__1_/mux_bottom_ipin_6/in[5] +set_disable_timing cbx_1__1_/mux_bottom_ipin_0/in[4] +set_disable_timing cbx_1__1_/mux_bottom_ipin_6/in[4] +################################################## +# Disable timing for Connection block cby_0__1_ +################################################## +set_disable_timing cby_0__1_/chany_bottom_in[0] +set_disable_timing cby_0__1_/chany_top_in[0] +set_disable_timing cby_0__1_/chany_bottom_in[1] +set_disable_timing cby_0__1_/chany_top_in[1] +set_disable_timing cby_0__1_/chany_bottom_in[2] +set_disable_timing cby_0__1_/chany_top_in[2] +set_disable_timing cby_0__1_/chany_bottom_in[3] +set_disable_timing cby_0__1_/chany_top_in[3] +set_disable_timing cby_0__1_/chany_bottom_in[4] +set_disable_timing cby_0__1_/chany_top_in[4] +set_disable_timing cby_0__1_/chany_bottom_in[5] +set_disable_timing cby_0__1_/chany_top_in[5] +set_disable_timing cby_0__1_/chany_bottom_in[6] +set_disable_timing cby_0__1_/chany_top_in[6] +set_disable_timing cby_0__1_/chany_bottom_in[7] +set_disable_timing cby_0__1_/chany_top_in[7] +set_disable_timing cby_0__1_/chany_bottom_in[8] +set_disable_timing cby_0__1_/chany_top_in[8] +set_disable_timing cby_0__1_/chany_bottom_in[9] +set_disable_timing cby_0__1_/chany_top_in[9] +set_disable_timing cby_0__1_/chany_bottom_in[10] +set_disable_timing cby_0__1_/chany_top_in[10] +set_disable_timing cby_0__1_/chany_bottom_in[11] +set_disable_timing cby_0__1_/chany_top_in[11] +set_disable_timing cby_0__1_/chany_bottom_in[12] +set_disable_timing cby_0__1_/chany_top_in[12] +set_disable_timing cby_0__1_/chany_bottom_out[0] +set_disable_timing cby_0__1_/chany_top_out[0] +set_disable_timing cby_0__1_/chany_bottom_out[1] +set_disable_timing cby_0__1_/chany_top_out[1] +set_disable_timing cby_0__1_/chany_bottom_out[2] +set_disable_timing cby_0__1_/chany_top_out[2] +set_disable_timing cby_0__1_/chany_bottom_out[3] +set_disable_timing cby_0__1_/chany_top_out[3] +set_disable_timing cby_0__1_/chany_bottom_out[4] +set_disable_timing cby_0__1_/chany_top_out[4] +set_disable_timing cby_0__1_/chany_bottom_out[5] +set_disable_timing cby_0__1_/chany_top_out[5] +set_disable_timing cby_0__1_/chany_bottom_out[6] +set_disable_timing cby_0__1_/chany_top_out[6] +set_disable_timing cby_0__1_/chany_bottom_out[7] +set_disable_timing cby_0__1_/chany_top_out[7] +set_disable_timing cby_0__1_/chany_bottom_out[8] +set_disable_timing cby_0__1_/chany_top_out[8] +set_disable_timing cby_0__1_/chany_bottom_out[9] +set_disable_timing cby_0__1_/chany_top_out[9] +set_disable_timing cby_0__1_/chany_bottom_out[10] +set_disable_timing cby_0__1_/chany_top_out[10] +set_disable_timing cby_0__1_/chany_bottom_out[11] +set_disable_timing cby_0__1_/chany_top_out[11] +set_disable_timing cby_0__1_/chany_bottom_out[12] +set_disable_timing cby_0__1_/chany_top_out[12] +set_disable_timing cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] +set_disable_timing cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] +set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] +set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] +set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] +set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] +set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] +set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] +set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] +set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] +set_disable_timing cby_0__1_/mux_left_ipin_0/in[1] +set_disable_timing cby_0__1_/mux_left_ipin_1/in[1] +set_disable_timing cby_0__1_/mux_right_ipin_5/in[1] +set_disable_timing cby_0__1_/mux_left_ipin_0/in[0] +set_disable_timing cby_0__1_/mux_left_ipin_1/in[0] +set_disable_timing cby_0__1_/mux_right_ipin_5/in[0] +set_disable_timing cby_0__1_/mux_left_ipin_1/in[3] +set_disable_timing cby_0__1_/mux_right_ipin_0/in[1] +set_disable_timing cby_0__1_/mux_right_ipin_6/in[1] +set_disable_timing cby_0__1_/mux_left_ipin_1/in[2] +set_disable_timing cby_0__1_/mux_right_ipin_0/in[0] +set_disable_timing cby_0__1_/mux_right_ipin_6/in[0] +set_disable_timing cby_0__1_/mux_right_ipin_0/in[3] +set_disable_timing cby_0__1_/mux_right_ipin_1/in[1] +set_disable_timing cby_0__1_/mux_right_ipin_7/in[1] +set_disable_timing cby_0__1_/mux_right_ipin_0/in[2] +set_disable_timing cby_0__1_/mux_right_ipin_1/in[0] +set_disable_timing cby_0__1_/mux_right_ipin_7/in[0] +set_disable_timing cby_0__1_/mux_right_ipin_1/in[3] +set_disable_timing cby_0__1_/mux_right_ipin_2/in[1] +set_disable_timing cby_0__1_/mux_right_ipin_1/in[2] +set_disable_timing cby_0__1_/mux_right_ipin_2/in[0] +set_disable_timing cby_0__1_/mux_right_ipin_2/in[3] +set_disable_timing cby_0__1_/mux_right_ipin_3/in[1] +set_disable_timing cby_0__1_/mux_right_ipin_2/in[2] +set_disable_timing cby_0__1_/mux_right_ipin_3/in[0] +set_disable_timing cby_0__1_/mux_right_ipin_3/in[3] +set_disable_timing cby_0__1_/mux_right_ipin_4/in[1] +set_disable_timing cby_0__1_/mux_right_ipin_3/in[2] +set_disable_timing cby_0__1_/mux_right_ipin_4/in[0] +set_disable_timing cby_0__1_/mux_left_ipin_0/in[3] +set_disable_timing cby_0__1_/mux_right_ipin_4/in[3] +set_disable_timing cby_0__1_/mux_right_ipin_5/in[3] +set_disable_timing cby_0__1_/mux_left_ipin_0/in[2] +set_disable_timing cby_0__1_/mux_right_ipin_4/in[2] +set_disable_timing cby_0__1_/mux_right_ipin_5/in[2] +set_disable_timing cby_0__1_/mux_left_ipin_1/in[5] +set_disable_timing cby_0__1_/mux_right_ipin_5/in[5] +set_disable_timing cby_0__1_/mux_right_ipin_6/in[3] +set_disable_timing cby_0__1_/mux_left_ipin_1/in[4] +set_disable_timing cby_0__1_/mux_right_ipin_5/in[4] +set_disable_timing cby_0__1_/mux_right_ipin_6/in[2] +set_disable_timing cby_0__1_/mux_right_ipin_0/in[5] +set_disable_timing cby_0__1_/mux_right_ipin_6/in[5] +set_disable_timing cby_0__1_/mux_right_ipin_7/in[3] +set_disable_timing cby_0__1_/mux_right_ipin_0/in[4] +set_disable_timing cby_0__1_/mux_right_ipin_6/in[4] +set_disable_timing cby_0__1_/mux_right_ipin_7/in[2] +set_disable_timing cby_0__1_/mux_right_ipin_1/in[5] +set_disable_timing cby_0__1_/mux_right_ipin_7/in[5] +set_disable_timing cby_0__1_/mux_right_ipin_1/in[4] +set_disable_timing cby_0__1_/mux_right_ipin_7/in[4] +set_disable_timing cby_0__1_/mux_right_ipin_2/in[5] +set_disable_timing cby_0__1_/mux_right_ipin_2/in[4] +set_disable_timing cby_0__1_/mux_right_ipin_3/in[5] +set_disable_timing cby_0__1_/mux_right_ipin_3/in[4] +set_disable_timing cby_0__1_/mux_left_ipin_0/in[5] +set_disable_timing cby_0__1_/mux_right_ipin_4/in[5] +set_disable_timing cby_0__1_/mux_left_ipin_0/in[4] +set_disable_timing cby_0__1_/mux_right_ipin_4/in[4] +################################################## +# Disable timing for Connection block cby_1__1_ +################################################## +set_disable_timing cby_1__1_/chany_top_in[0] +set_disable_timing cby_1__1_/chany_bottom_in[1] +set_disable_timing cby_1__1_/chany_top_in[1] +set_disable_timing cby_1__1_/chany_bottom_in[2] +set_disable_timing cby_1__1_/chany_top_in[2] +set_disable_timing cby_1__1_/chany_bottom_in[3] +set_disable_timing cby_1__1_/chany_top_in[3] +set_disable_timing cby_1__1_/chany_bottom_in[4] +set_disable_timing cby_1__1_/chany_top_in[4] +set_disable_timing cby_1__1_/chany_bottom_in[5] +set_disable_timing cby_1__1_/chany_top_in[5] +set_disable_timing cby_1__1_/chany_bottom_in[6] +set_disable_timing cby_1__1_/chany_top_in[6] +set_disable_timing cby_1__1_/chany_top_in[7] +set_disable_timing cby_1__1_/chany_bottom_in[8] +set_disable_timing cby_1__1_/chany_top_in[8] +set_disable_timing cby_1__1_/chany_bottom_in[9] +set_disable_timing cby_1__1_/chany_top_in[9] +set_disable_timing cby_1__1_/chany_top_in[10] +set_disable_timing cby_1__1_/chany_bottom_in[11] +set_disable_timing cby_1__1_/chany_top_in[11] +set_disable_timing cby_1__1_/chany_bottom_in[12] +set_disable_timing cby_1__1_/chany_top_in[12] +set_disable_timing cby_1__1_/chany_top_out[0] +set_disable_timing cby_1__1_/chany_bottom_out[1] +set_disable_timing cby_1__1_/chany_top_out[1] +set_disable_timing cby_1__1_/chany_bottom_out[2] +set_disable_timing cby_1__1_/chany_top_out[2] +set_disable_timing cby_1__1_/chany_bottom_out[3] +set_disable_timing cby_1__1_/chany_top_out[3] +set_disable_timing cby_1__1_/chany_bottom_out[4] +set_disable_timing cby_1__1_/chany_top_out[4] +set_disable_timing cby_1__1_/chany_bottom_out[5] +set_disable_timing cby_1__1_/chany_top_out[5] +set_disable_timing cby_1__1_/chany_bottom_out[6] +set_disable_timing cby_1__1_/chany_top_out[6] +set_disable_timing cby_1__1_/chany_top_out[7] +set_disable_timing cby_1__1_/chany_bottom_out[8] +set_disable_timing cby_1__1_/chany_top_out[8] +set_disable_timing cby_1__1_/chany_bottom_out[9] +set_disable_timing cby_1__1_/chany_top_out[9] +set_disable_timing cby_1__1_/chany_top_out[10] +set_disable_timing cby_1__1_/chany_bottom_out[11] +set_disable_timing cby_1__1_/chany_top_out[11] +set_disable_timing cby_1__1_/chany_bottom_out[12] +set_disable_timing cby_1__1_/chany_top_out[12] +set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] +set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] +set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] +set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] +set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] +set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] +set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] +set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] +set_disable_timing cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] +set_disable_timing cby_1__1_/mux_left_ipin_0/in[1] +set_disable_timing cby_1__1_/mux_left_ipin_1/in[1] +set_disable_timing cby_1__1_/mux_left_ipin_7/in[1] +set_disable_timing cby_1__1_/mux_left_ipin_0/in[0] +set_disable_timing cby_1__1_/mux_left_ipin_1/in[0] +set_disable_timing cby_1__1_/mux_left_ipin_7/in[0] +set_disable_timing cby_1__1_/mux_left_ipin_1/in[3] +set_disable_timing cby_1__1_/mux_left_ipin_2/in[1] +set_disable_timing cby_1__1_/mux_right_ipin_0/in[1] +set_disable_timing cby_1__1_/mux_left_ipin_1/in[2] +set_disable_timing cby_1__1_/mux_left_ipin_2/in[0] +set_disable_timing cby_1__1_/mux_right_ipin_0/in[0] +set_disable_timing cby_1__1_/mux_left_ipin_2/in[3] +set_disable_timing cby_1__1_/mux_left_ipin_3/in[1] +set_disable_timing cby_1__1_/mux_right_ipin_1/in[1] +set_disable_timing cby_1__1_/mux_left_ipin_2/in[2] +set_disable_timing cby_1__1_/mux_left_ipin_3/in[0] +set_disable_timing cby_1__1_/mux_right_ipin_1/in[0] +set_disable_timing cby_1__1_/mux_left_ipin_3/in[3] +set_disable_timing cby_1__1_/mux_left_ipin_4/in[1] +set_disable_timing cby_1__1_/mux_right_ipin_2/in[1] +set_disable_timing cby_1__1_/mux_left_ipin_3/in[2] +set_disable_timing cby_1__1_/mux_left_ipin_4/in[0] +set_disable_timing cby_1__1_/mux_right_ipin_2/in[0] +set_disable_timing cby_1__1_/mux_left_ipin_4/in[3] +set_disable_timing cby_1__1_/mux_left_ipin_5/in[1] +set_disable_timing cby_1__1_/mux_left_ipin_4/in[2] +set_disable_timing cby_1__1_/mux_left_ipin_5/in[0] +set_disable_timing cby_1__1_/mux_left_ipin_5/in[3] +set_disable_timing cby_1__1_/mux_left_ipin_6/in[1] +set_disable_timing cby_1__1_/mux_left_ipin_5/in[2] +set_disable_timing cby_1__1_/mux_left_ipin_6/in[0] +set_disable_timing cby_1__1_/mux_left_ipin_0/in[3] +set_disable_timing cby_1__1_/mux_left_ipin_6/in[3] +set_disable_timing cby_1__1_/mux_left_ipin_7/in[3] +set_disable_timing cby_1__1_/mux_left_ipin_0/in[2] +set_disable_timing cby_1__1_/mux_left_ipin_6/in[2] +set_disable_timing cby_1__1_/mux_left_ipin_7/in[2] +set_disable_timing cby_1__1_/mux_left_ipin_1/in[5] +set_disable_timing cby_1__1_/mux_left_ipin_7/in[5] +set_disable_timing cby_1__1_/mux_left_ipin_1/in[4] +set_disable_timing cby_1__1_/mux_left_ipin_7/in[4] +set_disable_timing cby_1__1_/mux_right_ipin_0/in[2] +set_disable_timing cby_1__1_/mux_left_ipin_2/in[5] +set_disable_timing cby_1__1_/mux_right_ipin_0/in[5] +set_disable_timing cby_1__1_/mux_right_ipin_1/in[3] +set_disable_timing cby_1__1_/mux_left_ipin_2/in[4] +set_disable_timing cby_1__1_/mux_right_ipin_0/in[4] +set_disable_timing cby_1__1_/mux_right_ipin_1/in[2] +set_disable_timing cby_1__1_/mux_left_ipin_3/in[5] +set_disable_timing cby_1__1_/mux_right_ipin_1/in[5] +set_disable_timing cby_1__1_/mux_right_ipin_2/in[3] +set_disable_timing cby_1__1_/mux_left_ipin_3/in[4] +set_disable_timing cby_1__1_/mux_right_ipin_1/in[4] +set_disable_timing cby_1__1_/mux_right_ipin_2/in[2] +set_disable_timing cby_1__1_/mux_left_ipin_4/in[5] +set_disable_timing cby_1__1_/mux_left_ipin_4/in[4] +set_disable_timing cby_1__1_/mux_right_ipin_2/in[4] +set_disable_timing cby_1__1_/mux_left_ipin_5/in[5] +set_disable_timing cby_1__1_/mux_left_ipin_5/in[4] +set_disable_timing cby_1__1_/mux_left_ipin_0/in[5] +set_disable_timing cby_1__1_/mux_left_ipin_6/in[5] +set_disable_timing cby_1__1_/mux_left_ipin_0/in[4] +set_disable_timing cby_1__1_/mux_left_ipin_6/in[4] +################################################## +# Disable timing for Switch block sb_0__0_ +################################################## +set_disable_timing sb_0__0_/chany_top_out[0] +set_disable_timing sb_0__0_/chany_top_in[0] +set_disable_timing sb_0__0_/chany_top_out[1] +set_disable_timing sb_0__0_/chany_top_in[1] +set_disable_timing sb_0__0_/chany_top_out[2] +set_disable_timing sb_0__0_/chany_top_in[2] +set_disable_timing sb_0__0_/chany_top_out[3] +set_disable_timing sb_0__0_/chany_top_in[3] +set_disable_timing sb_0__0_/chany_top_out[4] +set_disable_timing sb_0__0_/chany_top_in[4] +set_disable_timing sb_0__0_/chany_top_out[5] +set_disable_timing sb_0__0_/chany_top_in[5] +set_disable_timing sb_0__0_/chany_top_out[6] +set_disable_timing sb_0__0_/chany_top_in[6] +set_disable_timing sb_0__0_/chany_top_out[7] +set_disable_timing sb_0__0_/chany_top_in[7] +set_disable_timing sb_0__0_/chany_top_out[8] +set_disable_timing sb_0__0_/chany_top_in[8] +set_disable_timing sb_0__0_/chany_top_out[9] +set_disable_timing sb_0__0_/chany_top_in[9] +set_disable_timing sb_0__0_/chany_top_out[10] +set_disable_timing sb_0__0_/chany_top_in[10] +set_disable_timing sb_0__0_/chany_top_out[11] +set_disable_timing sb_0__0_/chany_top_in[11] +set_disable_timing sb_0__0_/chany_top_out[12] +set_disable_timing sb_0__0_/chany_top_in[12] +set_disable_timing sb_0__0_/chanx_right_out[0] +set_disable_timing sb_0__0_/chanx_right_in[0] +set_disable_timing sb_0__0_/chanx_right_out[1] +set_disable_timing sb_0__0_/chanx_right_in[1] +set_disable_timing sb_0__0_/chanx_right_out[2] +set_disable_timing sb_0__0_/chanx_right_in[2] +set_disable_timing sb_0__0_/chanx_right_out[3] +set_disable_timing sb_0__0_/chanx_right_in[3] +set_disable_timing sb_0__0_/chanx_right_out[4] +set_disable_timing sb_0__0_/chanx_right_in[4] +set_disable_timing sb_0__0_/chanx_right_out[5] +set_disable_timing sb_0__0_/chanx_right_in[5] +set_disable_timing sb_0__0_/chanx_right_out[6] +set_disable_timing sb_0__0_/chanx_right_in[6] +set_disable_timing sb_0__0_/chanx_right_out[7] +set_disable_timing sb_0__0_/chanx_right_in[7] +set_disable_timing sb_0__0_/chanx_right_out[8] +set_disable_timing sb_0__0_/chanx_right_in[8] +set_disable_timing sb_0__0_/chanx_right_out[9] +set_disable_timing sb_0__0_/chanx_right_in[9] +set_disable_timing sb_0__0_/chanx_right_out[10] +set_disable_timing sb_0__0_/chanx_right_in[10] +set_disable_timing sb_0__0_/chanx_right_out[11] +set_disable_timing sb_0__0_/chanx_right_in[11] +set_disable_timing sb_0__0_/chanx_right_out[12] +set_disable_timing sb_0__0_/chanx_right_in[12] +set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] +set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] +set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] +set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] +set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] +set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] +set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] +set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] +set_disable_timing sb_0__0_/top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] +set_disable_timing sb_0__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] +set_disable_timing sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] +set_disable_timing sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] +set_disable_timing sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] +set_disable_timing sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] +set_disable_timing sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] +set_disable_timing sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] +set_disable_timing sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] +set_disable_timing sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] +set_disable_timing sb_0__0_/mux_top_track_0/in[0] +set_disable_timing sb_0__0_/mux_top_track_12/in[0] +set_disable_timing sb_0__0_/mux_top_track_24/in[0] +set_disable_timing sb_0__0_/mux_top_track_0/in[1] +set_disable_timing sb_0__0_/mux_top_track_2/in[0] +set_disable_timing sb_0__0_/mux_top_track_14/in[0] +set_disable_timing sb_0__0_/mux_top_track_2/in[1] +set_disable_timing sb_0__0_/mux_top_track_4/in[0] +set_disable_timing sb_0__0_/mux_top_track_16/in[0] +set_disable_timing sb_0__0_/mux_top_track_4/in[1] +set_disable_timing sb_0__0_/mux_top_track_6/in[0] +set_disable_timing sb_0__0_/mux_top_track_18/in[0] +set_disable_timing sb_0__0_/mux_top_track_6/in[1] +set_disable_timing sb_0__0_/mux_top_track_8/in[0] +set_disable_timing sb_0__0_/mux_top_track_20/in[0] +set_disable_timing sb_0__0_/mux_top_track_8/in[1] +set_disable_timing sb_0__0_/mux_top_track_10/in[0] +set_disable_timing sb_0__0_/mux_top_track_22/in[0] +set_disable_timing sb_0__0_/mux_top_track_10/in[1] +set_disable_timing sb_0__0_/mux_top_track_12/in[1] +set_disable_timing sb_0__0_/mux_top_track_24/in[1] +set_disable_timing sb_0__0_/mux_top_track_0/in[2] +set_disable_timing sb_0__0_/mux_top_track_12/in[2] +set_disable_timing sb_0__0_/mux_top_track_14/in[1] +set_disable_timing sb_0__0_/mux_top_track_16/in[1] +set_disable_timing sb_0__0_/mux_right_track_0/in[1] +set_disable_timing sb_0__0_/mux_right_track_12/in[1] +set_disable_timing sb_0__0_/mux_right_track_24/in[1] +set_disable_timing sb_0__0_/mux_right_track_0/in[2] +set_disable_timing sb_0__0_/mux_right_track_2/in[1] +set_disable_timing sb_0__0_/mux_right_track_14/in[1] +set_disable_timing sb_0__0_/mux_right_track_2/in[2] +set_disable_timing sb_0__0_/mux_right_track_4/in[1] +set_disable_timing sb_0__0_/mux_right_track_16/in[1] +set_disable_timing sb_0__0_/mux_right_track_4/in[2] +set_disable_timing sb_0__0_/mux_right_track_6/in[1] +set_disable_timing sb_0__0_/mux_right_track_18/in[1] +set_disable_timing sb_0__0_/mux_right_track_6/in[2] +set_disable_timing sb_0__0_/mux_right_track_8/in[1] +set_disable_timing sb_0__0_/mux_right_track_20/in[1] +set_disable_timing sb_0__0_/mux_right_track_8/in[2] +set_disable_timing sb_0__0_/mux_right_track_10/in[1] +set_disable_timing sb_0__0_/mux_right_track_22/in[1] +set_disable_timing sb_0__0_/mux_right_track_10/in[2] +set_disable_timing sb_0__0_/mux_right_track_12/in[2] +set_disable_timing sb_0__0_/mux_right_track_24/in[2] +set_disable_timing sb_0__0_/mux_right_track_0/in[3] +set_disable_timing sb_0__0_/mux_right_track_12/in[3] +set_disable_timing sb_0__0_/mux_right_track_14/in[2] +set_disable_timing sb_0__0_/mux_right_track_2/in[3] +set_disable_timing sb_0__0_/mux_right_track_14/in[3] +set_disable_timing sb_0__0_/mux_right_track_16/in[2] +set_disable_timing sb_0__0_/mux_right_track_2/in[0] +set_disable_timing sb_0__0_/mux_right_track_4/in[0] +set_disable_timing sb_0__0_/mux_right_track_6/in[0] +set_disable_timing sb_0__0_/mux_right_track_8/in[0] +set_disable_timing sb_0__0_/mux_right_track_10/in[0] +set_disable_timing sb_0__0_/mux_right_track_12/in[0] +set_disable_timing sb_0__0_/mux_right_track_14/in[0] +set_disable_timing sb_0__0_/mux_right_track_16/in[0] +set_disable_timing sb_0__0_/mux_right_track_18/in[0] +set_disable_timing sb_0__0_/mux_right_track_20/in[0] +set_disable_timing sb_0__0_/mux_right_track_22/in[0] +set_disable_timing sb_0__0_/mux_right_track_24/in[0] +set_disable_timing sb_0__0_/mux_right_track_0/in[0] +set_disable_timing sb_0__0_/mux_top_track_24/in[2] +set_disable_timing sb_0__0_/mux_top_track_0/in[3] +set_disable_timing sb_0__0_/mux_top_track_2/in[2] +set_disable_timing sb_0__0_/mux_top_track_4/in[2] +set_disable_timing sb_0__0_/mux_top_track_6/in[2] +set_disable_timing sb_0__0_/mux_top_track_8/in[2] +set_disable_timing sb_0__0_/mux_top_track_10/in[2] +set_disable_timing sb_0__0_/mux_top_track_12/in[3] +set_disable_timing sb_0__0_/mux_top_track_14/in[2] +set_disable_timing sb_0__0_/mux_top_track_16/in[2] +set_disable_timing sb_0__0_/mux_top_track_18/in[1] +set_disable_timing sb_0__0_/mux_top_track_20/in[1] +set_disable_timing sb_0__0_/mux_top_track_22/in[1] +################################################## +# Disable timing for Switch block sb_0__1_ +################################################## +set_disable_timing sb_0__1_/chanx_right_out[0] +set_disable_timing sb_0__1_/chanx_right_in[0] +set_disable_timing sb_0__1_/chanx_right_out[1] +set_disable_timing sb_0__1_/chanx_right_out[2] +set_disable_timing sb_0__1_/chanx_right_in[2] +set_disable_timing sb_0__1_/chanx_right_out[3] +set_disable_timing sb_0__1_/chanx_right_in[3] +set_disable_timing sb_0__1_/chanx_right_out[4] +set_disable_timing sb_0__1_/chanx_right_in[4] +set_disable_timing sb_0__1_/chanx_right_out[5] +set_disable_timing sb_0__1_/chanx_right_in[5] +set_disable_timing sb_0__1_/chanx_right_out[6] +set_disable_timing sb_0__1_/chanx_right_in[6] +set_disable_timing sb_0__1_/chanx_right_out[7] +set_disable_timing sb_0__1_/chanx_right_in[7] +set_disable_timing sb_0__1_/chanx_right_out[8] +set_disable_timing sb_0__1_/chanx_right_in[8] +set_disable_timing sb_0__1_/chanx_right_out[9] +set_disable_timing sb_0__1_/chanx_right_in[9] +set_disable_timing sb_0__1_/chanx_right_out[10] +set_disable_timing sb_0__1_/chanx_right_in[10] +set_disable_timing sb_0__1_/chanx_right_out[11] +set_disable_timing sb_0__1_/chanx_right_in[11] +set_disable_timing sb_0__1_/chanx_right_out[12] +set_disable_timing sb_0__1_/chanx_right_in[12] +set_disable_timing sb_0__1_/chany_bottom_in[0] +set_disable_timing sb_0__1_/chany_bottom_out[0] +set_disable_timing sb_0__1_/chany_bottom_in[1] +set_disable_timing sb_0__1_/chany_bottom_out[1] +set_disable_timing sb_0__1_/chany_bottom_in[2] +set_disable_timing sb_0__1_/chany_bottom_out[2] +set_disable_timing sb_0__1_/chany_bottom_in[3] +set_disable_timing sb_0__1_/chany_bottom_out[3] +set_disable_timing sb_0__1_/chany_bottom_in[4] +set_disable_timing sb_0__1_/chany_bottom_out[4] +set_disable_timing sb_0__1_/chany_bottom_in[5] +set_disable_timing sb_0__1_/chany_bottom_out[5] +set_disable_timing sb_0__1_/chany_bottom_in[6] +set_disable_timing sb_0__1_/chany_bottom_out[6] +set_disable_timing sb_0__1_/chany_bottom_in[7] +set_disable_timing sb_0__1_/chany_bottom_out[7] +set_disable_timing sb_0__1_/chany_bottom_in[8] +set_disable_timing sb_0__1_/chany_bottom_out[8] +set_disable_timing sb_0__1_/chany_bottom_in[9] +set_disable_timing sb_0__1_/chany_bottom_out[9] +set_disable_timing sb_0__1_/chany_bottom_in[10] +set_disable_timing sb_0__1_/chany_bottom_out[10] +set_disable_timing sb_0__1_/chany_bottom_in[11] +set_disable_timing sb_0__1_/chany_bottom_out[11] +set_disable_timing sb_0__1_/chany_bottom_in[12] +set_disable_timing sb_0__1_/chany_bottom_out[12] +set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] +set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] +set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] +set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] +set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] +set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] +set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] +set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] +set_disable_timing sb_0__1_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] +set_disable_timing sb_0__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] +set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] +set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] +set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] +set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] +set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] +set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] +set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] +set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] +set_disable_timing sb_0__1_/mux_right_track_0/in[0] +set_disable_timing sb_0__1_/mux_right_track_12/in[0] +set_disable_timing sb_0__1_/mux_right_track_24/in[0] +set_disable_timing sb_0__1_/mux_right_track_0/in[1] +set_disable_timing sb_0__1_/mux_right_track_2/in[0] +set_disable_timing sb_0__1_/mux_right_track_14/in[0] +set_disable_timing sb_0__1_/mux_right_track_2/in[1] +set_disable_timing sb_0__1_/mux_right_track_4/in[0] +set_disable_timing sb_0__1_/mux_right_track_16/in[0] +set_disable_timing sb_0__1_/mux_right_track_4/in[1] +set_disable_timing sb_0__1_/mux_right_track_6/in[0] +set_disable_timing sb_0__1_/mux_right_track_18/in[0] +set_disable_timing sb_0__1_/mux_right_track_6/in[1] +set_disable_timing sb_0__1_/mux_right_track_8/in[0] +set_disable_timing sb_0__1_/mux_right_track_20/in[0] +set_disable_timing sb_0__1_/mux_right_track_8/in[1] +set_disable_timing sb_0__1_/mux_right_track_10/in[0] +set_disable_timing sb_0__1_/mux_right_track_22/in[0] +set_disable_timing sb_0__1_/mux_right_track_10/in[1] +set_disable_timing sb_0__1_/mux_right_track_12/in[1] +set_disable_timing sb_0__1_/mux_right_track_24/in[1] +set_disable_timing sb_0__1_/mux_right_track_0/in[2] +set_disable_timing sb_0__1_/mux_right_track_12/in[2] +set_disable_timing sb_0__1_/mux_right_track_14/in[1] +set_disable_timing sb_0__1_/mux_right_track_16/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_1/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_1/in[2] +set_disable_timing sb_0__1_/mux_bottom_track_3/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_15/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_3/in[2] +set_disable_timing sb_0__1_/mux_bottom_track_5/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_17/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_5/in[2] +set_disable_timing sb_0__1_/mux_bottom_track_7/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_19/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_7/in[2] +set_disable_timing sb_0__1_/mux_bottom_track_9/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_21/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_9/in[2] +set_disable_timing sb_0__1_/mux_bottom_track_11/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_23/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_11/in[2] +set_disable_timing sb_0__1_/mux_bottom_track_13/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_25/in[1] +set_disable_timing sb_0__1_/mux_bottom_track_1/in[3] +set_disable_timing sb_0__1_/mux_bottom_track_13/in[2] +set_disable_timing sb_0__1_/mux_bottom_track_15/in[2] +set_disable_timing sb_0__1_/mux_bottom_track_3/in[3] +set_disable_timing sb_0__1_/mux_bottom_track_15/in[3] +set_disable_timing sb_0__1_/mux_bottom_track_17/in[2] +set_disable_timing sb_0__1_/mux_bottom_track_23/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_21/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_19/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_17/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_15/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_13/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_11/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_9/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_7/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_5/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_3/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_1/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_25/in[0] +set_disable_timing sb_0__1_/mux_right_track_22/in[1] +set_disable_timing sb_0__1_/mux_right_track_20/in[1] +set_disable_timing sb_0__1_/mux_right_track_18/in[1] +set_disable_timing sb_0__1_/mux_right_track_16/in[2] +set_disable_timing sb_0__1_/mux_right_track_14/in[2] +set_disable_timing sb_0__1_/mux_right_track_12/in[3] +set_disable_timing sb_0__1_/mux_right_track_10/in[2] +set_disable_timing sb_0__1_/mux_right_track_8/in[2] +set_disable_timing sb_0__1_/mux_right_track_6/in[2] +set_disable_timing sb_0__1_/mux_right_track_4/in[2] +set_disable_timing sb_0__1_/mux_right_track_2/in[2] +set_disable_timing sb_0__1_/mux_right_track_0/in[3] +set_disable_timing sb_0__1_/mux_right_track_24/in[2] +################################################## +# Disable timing for Switch block sb_1__0_ +################################################## +set_disable_timing sb_1__0_/chany_top_in[0] +set_disable_timing sb_1__0_/chany_top_out[1] +set_disable_timing sb_1__0_/chany_top_in[1] +set_disable_timing sb_1__0_/chany_top_out[2] +set_disable_timing sb_1__0_/chany_top_in[2] +set_disable_timing sb_1__0_/chany_top_out[3] +set_disable_timing sb_1__0_/chany_top_in[3] +set_disable_timing sb_1__0_/chany_top_out[4] +set_disable_timing sb_1__0_/chany_top_in[4] +set_disable_timing sb_1__0_/chany_top_out[5] +set_disable_timing sb_1__0_/chany_top_in[5] +set_disable_timing sb_1__0_/chany_top_out[6] +set_disable_timing sb_1__0_/chany_top_in[6] +set_disable_timing sb_1__0_/chany_top_in[7] +set_disable_timing sb_1__0_/chany_top_out[8] +set_disable_timing sb_1__0_/chany_top_in[8] +set_disable_timing sb_1__0_/chany_top_out[9] +set_disable_timing sb_1__0_/chany_top_in[9] +set_disable_timing sb_1__0_/chany_top_in[10] +set_disable_timing sb_1__0_/chany_top_out[11] +set_disable_timing sb_1__0_/chany_top_in[11] +set_disable_timing sb_1__0_/chany_top_out[12] +set_disable_timing sb_1__0_/chany_top_in[12] +set_disable_timing sb_1__0_/chanx_left_in[0] +set_disable_timing sb_1__0_/chanx_left_out[0] +set_disable_timing sb_1__0_/chanx_left_in[1] +set_disable_timing sb_1__0_/chanx_left_out[1] +set_disable_timing sb_1__0_/chanx_left_in[2] +set_disable_timing sb_1__0_/chanx_left_out[2] +set_disable_timing sb_1__0_/chanx_left_in[3] +set_disable_timing sb_1__0_/chanx_left_out[3] +set_disable_timing sb_1__0_/chanx_left_in[4] +set_disable_timing sb_1__0_/chanx_left_out[4] +set_disable_timing sb_1__0_/chanx_left_in[5] +set_disable_timing sb_1__0_/chanx_left_out[5] +set_disable_timing sb_1__0_/chanx_left_in[6] +set_disable_timing sb_1__0_/chanx_left_out[6] +set_disable_timing sb_1__0_/chanx_left_in[7] +set_disable_timing sb_1__0_/chanx_left_out[7] +set_disable_timing sb_1__0_/chanx_left_in[8] +set_disable_timing sb_1__0_/chanx_left_out[8] +set_disable_timing sb_1__0_/chanx_left_in[9] +set_disable_timing sb_1__0_/chanx_left_out[9] +set_disable_timing sb_1__0_/chanx_left_in[10] +set_disable_timing sb_1__0_/chanx_left_out[10] +set_disable_timing sb_1__0_/chanx_left_in[11] +set_disable_timing sb_1__0_/chanx_left_out[11] +set_disable_timing sb_1__0_/chanx_left_in[12] +set_disable_timing sb_1__0_/chanx_left_out[12] +set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] +set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] +set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] +set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] +set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] +set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] +set_disable_timing sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] +set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] +set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] +set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] +set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] +set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] +set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] +set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] +set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] +set_disable_timing sb_1__0_/mux_top_track_0/in[1] +set_disable_timing sb_1__0_/mux_top_track_2/in[0] +set_disable_timing sb_1__0_/mux_top_track_14/in[0] +set_disable_timing sb_1__0_/mux_top_track_2/in[1] +set_disable_timing sb_1__0_/mux_top_track_4/in[0] +set_disable_timing sb_1__0_/mux_top_track_16/in[0] +set_disable_timing sb_1__0_/mux_top_track_4/in[1] +set_disable_timing sb_1__0_/mux_top_track_6/in[0] +set_disable_timing sb_1__0_/mux_top_track_18/in[0] +set_disable_timing sb_1__0_/mux_top_track_6/in[1] +set_disable_timing sb_1__0_/mux_top_track_8/in[0] +set_disable_timing sb_1__0_/mux_top_track_8/in[1] +set_disable_timing sb_1__0_/mux_top_track_10/in[0] +set_disable_timing sb_1__0_/mux_top_track_22/in[0] +set_disable_timing sb_1__0_/mux_top_track_10/in[1] +set_disable_timing sb_1__0_/mux_top_track_12/in[0] +set_disable_timing sb_1__0_/mux_top_track_24/in[0] +set_disable_timing sb_1__0_/mux_top_track_0/in[2] +set_disable_timing sb_1__0_/mux_top_track_12/in[1] +set_disable_timing sb_1__0_/mux_top_track_2/in[2] +set_disable_timing sb_1__0_/mux_top_track_14/in[2] +set_disable_timing sb_1__0_/mux_top_track_16/in[1] +set_disable_timing sb_1__0_/mux_left_track_1/in[1] +set_disable_timing sb_1__0_/mux_left_track_13/in[1] +set_disable_timing sb_1__0_/mux_left_track_25/in[1] +set_disable_timing sb_1__0_/mux_left_track_1/in[2] +set_disable_timing sb_1__0_/mux_left_track_3/in[1] +set_disable_timing sb_1__0_/mux_left_track_15/in[1] +set_disable_timing sb_1__0_/mux_left_track_3/in[2] +set_disable_timing sb_1__0_/mux_left_track_5/in[1] +set_disable_timing sb_1__0_/mux_left_track_17/in[1] +set_disable_timing sb_1__0_/mux_left_track_5/in[2] +set_disable_timing sb_1__0_/mux_left_track_7/in[1] +set_disable_timing sb_1__0_/mux_left_track_19/in[1] +set_disable_timing sb_1__0_/mux_left_track_7/in[2] +set_disable_timing sb_1__0_/mux_left_track_9/in[1] +set_disable_timing sb_1__0_/mux_left_track_21/in[1] +set_disable_timing sb_1__0_/mux_left_track_9/in[2] +set_disable_timing sb_1__0_/mux_left_track_11/in[1] +set_disable_timing sb_1__0_/mux_left_track_23/in[1] +set_disable_timing sb_1__0_/mux_left_track_11/in[2] +set_disable_timing sb_1__0_/mux_left_track_13/in[2] +set_disable_timing sb_1__0_/mux_left_track_25/in[2] +set_disable_timing sb_1__0_/mux_left_track_1/in[3] +set_disable_timing sb_1__0_/mux_left_track_13/in[3] +set_disable_timing sb_1__0_/mux_left_track_15/in[2] +set_disable_timing sb_1__0_/mux_left_track_3/in[3] +set_disable_timing sb_1__0_/mux_left_track_15/in[3] +set_disable_timing sb_1__0_/mux_left_track_17/in[2] +set_disable_timing sb_1__0_/mux_left_track_1/in[0] +set_disable_timing sb_1__0_/mux_left_track_25/in[0] +set_disable_timing sb_1__0_/mux_left_track_23/in[0] +set_disable_timing sb_1__0_/mux_left_track_21/in[0] +set_disable_timing sb_1__0_/mux_left_track_19/in[0] +set_disable_timing sb_1__0_/mux_left_track_17/in[0] +set_disable_timing sb_1__0_/mux_left_track_15/in[0] +set_disable_timing sb_1__0_/mux_left_track_13/in[0] +set_disable_timing sb_1__0_/mux_left_track_11/in[0] +set_disable_timing sb_1__0_/mux_left_track_9/in[0] +set_disable_timing sb_1__0_/mux_left_track_7/in[0] +set_disable_timing sb_1__0_/mux_left_track_5/in[0] +set_disable_timing sb_1__0_/mux_left_track_3/in[0] +set_disable_timing sb_1__0_/mux_top_track_0/in[3] +set_disable_timing sb_1__0_/mux_top_track_24/in[1] +set_disable_timing sb_1__0_/mux_top_track_22/in[1] +set_disable_timing sb_1__0_/mux_top_track_20/in[1] +set_disable_timing sb_1__0_/mux_top_track_18/in[1] +set_disable_timing sb_1__0_/mux_top_track_16/in[2] +set_disable_timing sb_1__0_/mux_top_track_14/in[3] +set_disable_timing sb_1__0_/mux_top_track_12/in[2] +set_disable_timing sb_1__0_/mux_top_track_10/in[2] +set_disable_timing sb_1__0_/mux_top_track_8/in[2] +set_disable_timing sb_1__0_/mux_top_track_6/in[2] +set_disable_timing sb_1__0_/mux_top_track_4/in[2] +set_disable_timing sb_1__0_/mux_top_track_2/in[3] +################################################## +# Disable timing for Switch block sb_1__1_ +################################################## +set_disable_timing sb_1__1_/chany_bottom_out[0] +set_disable_timing sb_1__1_/chany_bottom_in[1] +set_disable_timing sb_1__1_/chany_bottom_out[1] +set_disable_timing sb_1__1_/chany_bottom_in[2] +set_disable_timing sb_1__1_/chany_bottom_out[2] +set_disable_timing sb_1__1_/chany_bottom_in[3] +set_disable_timing sb_1__1_/chany_bottom_out[3] +set_disable_timing sb_1__1_/chany_bottom_in[4] +set_disable_timing sb_1__1_/chany_bottom_out[4] +set_disable_timing sb_1__1_/chany_bottom_in[5] +set_disable_timing sb_1__1_/chany_bottom_out[5] +set_disable_timing sb_1__1_/chany_bottom_in[6] +set_disable_timing sb_1__1_/chany_bottom_out[6] +set_disable_timing sb_1__1_/chany_bottom_out[7] +set_disable_timing sb_1__1_/chany_bottom_in[8] +set_disable_timing sb_1__1_/chany_bottom_out[8] +set_disable_timing sb_1__1_/chany_bottom_in[9] +set_disable_timing sb_1__1_/chany_bottom_out[9] +set_disable_timing sb_1__1_/chany_bottom_out[10] +set_disable_timing sb_1__1_/chany_bottom_in[11] +set_disable_timing sb_1__1_/chany_bottom_out[11] +set_disable_timing sb_1__1_/chany_bottom_in[12] +set_disable_timing sb_1__1_/chany_bottom_out[12] +set_disable_timing sb_1__1_/chanx_left_in[0] +set_disable_timing sb_1__1_/chanx_left_out[0] +set_disable_timing sb_1__1_/chanx_left_in[1] +set_disable_timing sb_1__1_/chanx_left_in[2] +set_disable_timing sb_1__1_/chanx_left_out[2] +set_disable_timing sb_1__1_/chanx_left_in[3] +set_disable_timing sb_1__1_/chanx_left_out[3] +set_disable_timing sb_1__1_/chanx_left_in[4] +set_disable_timing sb_1__1_/chanx_left_out[4] +set_disable_timing sb_1__1_/chanx_left_in[5] +set_disable_timing sb_1__1_/chanx_left_out[5] +set_disable_timing sb_1__1_/chanx_left_in[6] +set_disable_timing sb_1__1_/chanx_left_out[6] +set_disable_timing sb_1__1_/chanx_left_in[7] +set_disable_timing sb_1__1_/chanx_left_out[7] +set_disable_timing sb_1__1_/chanx_left_in[8] +set_disable_timing sb_1__1_/chanx_left_out[8] +set_disable_timing sb_1__1_/chanx_left_in[9] +set_disable_timing sb_1__1_/chanx_left_out[9] +set_disable_timing sb_1__1_/chanx_left_in[10] +set_disable_timing sb_1__1_/chanx_left_out[10] +set_disable_timing sb_1__1_/chanx_left_in[11] +set_disable_timing sb_1__1_/chanx_left_out[11] +set_disable_timing sb_1__1_/chanx_left_in[12] +set_disable_timing sb_1__1_/chanx_left_out[12] +set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] +set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] +set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] +set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] +set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] +set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] +set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] +set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] +set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] +set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] +set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] +set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] +set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] +set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] +set_disable_timing sb_1__1_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] +set_disable_timing sb_1__1_/mux_bottom_track_1/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_13/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_25/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_1/in[1] +set_disable_timing sb_1__1_/mux_bottom_track_3/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_15/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_3/in[1] +set_disable_timing sb_1__1_/mux_bottom_track_5/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_17/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_5/in[1] +set_disable_timing sb_1__1_/mux_bottom_track_7/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_19/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_7/in[1] +set_disable_timing sb_1__1_/mux_bottom_track_9/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_21/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_9/in[1] +set_disable_timing sb_1__1_/mux_bottom_track_11/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_23/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_11/in[1] +set_disable_timing sb_1__1_/mux_bottom_track_13/in[1] +set_disable_timing sb_1__1_/mux_bottom_track_25/in[1] +set_disable_timing sb_1__1_/mux_bottom_track_1/in[2] +set_disable_timing sb_1__1_/mux_bottom_track_13/in[2] +set_disable_timing sb_1__1_/mux_bottom_track_15/in[1] +set_disable_timing sb_1__1_/mux_bottom_track_17/in[1] +set_disable_timing sb_1__1_/mux_left_track_1/in[1] +set_disable_timing sb_1__1_/mux_left_track_13/in[1] +set_disable_timing sb_1__1_/mux_left_track_25/in[1] +set_disable_timing sb_1__1_/mux_left_track_1/in[2] +set_disable_timing sb_1__1_/mux_left_track_3/in[1] +set_disable_timing sb_1__1_/mux_left_track_15/in[1] +set_disable_timing sb_1__1_/mux_left_track_3/in[2] +set_disable_timing sb_1__1_/mux_left_track_5/in[1] +set_disable_timing sb_1__1_/mux_left_track_17/in[1] +set_disable_timing sb_1__1_/mux_left_track_5/in[2] +set_disable_timing sb_1__1_/mux_left_track_7/in[1] +set_disable_timing sb_1__1_/mux_left_track_19/in[1] +set_disable_timing sb_1__1_/mux_left_track_7/in[2] +set_disable_timing sb_1__1_/mux_left_track_9/in[1] +set_disable_timing sb_1__1_/mux_left_track_21/in[1] +set_disable_timing sb_1__1_/mux_left_track_9/in[2] +set_disable_timing sb_1__1_/mux_left_track_11/in[1] +set_disable_timing sb_1__1_/mux_left_track_23/in[1] +set_disable_timing sb_1__1_/mux_left_track_11/in[2] +set_disable_timing sb_1__1_/mux_left_track_13/in[2] +set_disable_timing sb_1__1_/mux_left_track_25/in[2] +set_disable_timing sb_1__1_/mux_left_track_1/in[3] +set_disable_timing sb_1__1_/mux_left_track_13/in[3] +set_disable_timing sb_1__1_/mux_left_track_15/in[2] +set_disable_timing sb_1__1_/mux_left_track_17/in[2] +set_disable_timing sb_1__1_/mux_left_track_5/in[0] +set_disable_timing sb_1__1_/mux_left_track_7/in[0] +set_disable_timing sb_1__1_/mux_left_track_9/in[0] +set_disable_timing sb_1__1_/mux_left_track_11/in[0] +set_disable_timing sb_1__1_/mux_left_track_13/in[0] +set_disable_timing sb_1__1_/mux_left_track_15/in[0] +set_disable_timing sb_1__1_/mux_left_track_17/in[0] +set_disable_timing sb_1__1_/mux_left_track_19/in[0] +set_disable_timing sb_1__1_/mux_left_track_21/in[0] +set_disable_timing sb_1__1_/mux_left_track_23/in[0] +set_disable_timing sb_1__1_/mux_left_track_25/in[0] +set_disable_timing sb_1__1_/mux_left_track_1/in[0] +set_disable_timing sb_1__1_/mux_bottom_track_25/in[2] +set_disable_timing sb_1__1_/mux_bottom_track_1/in[3] +set_disable_timing sb_1__1_/mux_bottom_track_3/in[2] +set_disable_timing sb_1__1_/mux_bottom_track_5/in[2] +set_disable_timing sb_1__1_/mux_bottom_track_7/in[2] +set_disable_timing sb_1__1_/mux_bottom_track_9/in[2] +set_disable_timing sb_1__1_/mux_bottom_track_11/in[2] +set_disable_timing sb_1__1_/mux_bottom_track_13/in[3] +set_disable_timing sb_1__1_/mux_bottom_track_15/in[2] +set_disable_timing sb_1__1_/mux_bottom_track_17/in[2] +set_disable_timing sb_1__1_/mux_bottom_track_19/in[1] +set_disable_timing sb_1__1_/mux_bottom_track_21/in[1] +set_disable_timing sb_1__1_/mux_bottom_track_23/in[1] +####################################### +# Disable Timing for grid[1][1] +####################################### +####################################### +# Disable Timing for unused resources in grid[1][1][0] +####################################### +####################################### +# Disable unused pins for pb_graph_node clb[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[3] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[4] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[5] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[6] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[7] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[8] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_O[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_O[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_O[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_clk[0] +####################################### +# Disable unused mux_inputs for pb_graph_node clb[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[3] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[4] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[5] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[6] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[7] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[8] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[9] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//direct_interc_7_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[10] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[11] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[12] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[13] +####################################### +# Disable unused pins for pb_graph_node fle[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_clk[0] +####################################### +# Disable unused mux_inputs for pb_graph_node fle[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_1_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_2_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_3_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_4_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_5_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_0_/in[0] +####################################### +# Disable unused pins for pb_graph_node ble4[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[3] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0] +####################################### +# Disable unused mux_inputs for pb_graph_node ble4[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_0_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_3_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_4_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0] +####################################### +# Disable unused pins for pb_graph_node lut4[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[3] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0] +####################################### +# Disable unused pins for pb_graph_node ff[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0] +####################################### +# Disable unused pins for pb_graph_node fle[1] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_clk[0] +####################################### +# Disable unused mux_inputs for pb_graph_node fle[1] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_1_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_2_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_3_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_4_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_5_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_0_/in[0] +####################################### +# Disable unused pins for pb_graph_node ble4[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[3] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0] +####################################### +# Disable unused mux_inputs for pb_graph_node ble4[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_0_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_3_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_4_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0] +####################################### +# Disable unused pins for pb_graph_node lut4[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[3] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0] +####################################### +# Disable unused pins for pb_graph_node ff[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0] +####################################### +# Disable unused pins for pb_graph_node fle[2] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_clk[0] +####################################### +# Disable unused mux_inputs for pb_graph_node fle[2] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_1_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_2_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_3_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_4_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_5_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_0_/in[0] +####################################### +# Disable unused pins for pb_graph_node ble4[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[3] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0] +####################################### +# Disable unused mux_inputs for pb_graph_node ble4[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_0_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_3_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_4_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0] +####################################### +# Disable unused pins for pb_graph_node lut4[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[3] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0] +####################################### +# Disable unused pins for pb_graph_node ff[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0] +####################################### +# Disable unused pins for pb_graph_node fle[3] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_clk[0] +####################################### +# Disable unused mux_inputs for pb_graph_node fle[3] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_2_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_3_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_5_/in[0] +####################################### +# Disable unused pins for pb_graph_node ble4[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0] +####################################### +# Disable unused mux_inputs for pb_graph_node ble4[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0] +####################################### +# Disable unused pins for pb_graph_node lut4[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2] +####################################### +# Disable unused pins for pb_graph_node ff[0] +####################################### +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0] +####################################### +# Disable Timing for grid[1][2] +####################################### +####################################### +# Disable Timing for unused grid[1][2][0] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__0/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused resources in grid[1][2][1] +####################################### +####################################### +# Disable unused pins for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/io_inpad[0] +####################################### +# Disable unused mux_inputs for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1//direct_interc_0_/in[0] +####################################### +# Disable unused pins for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0] +####################################### +# Disable Timing for unused grid[1][2][2] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__2/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][2][3] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__3/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][2][4] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__4/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][2][5] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__5/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][2][6] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__6/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][2][7] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__7/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for grid[2][1] +####################################### +####################################### +# Disable Timing for unused grid[2][1][0] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__0/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[2][1][1] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__1/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[2][1][2] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__2/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused resources in grid[2][1][3] +####################################### +####################################### +# Disable unused pins for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/io_outpad[0] +####################################### +# Disable unused mux_inputs for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3//direct_interc_1_/in[0] +####################################### +# Disable unused pins for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] +####################################### +# Disable Timing for unused grid[2][1][4] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[2][1][5] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__5/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused resources in grid[2][1][6] +####################################### +####################################### +# Disable unused pins for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__6/io_outpad[0] +####################################### +# Disable unused mux_inputs for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__6//direct_interc_1_/in[0] +####################################### +# Disable unused pins for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] +####################################### +# Disable Timing for unused grid[2][1][7] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for grid[1][0] +####################################### +####################################### +# Disable Timing for unused grid[1][0][0] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__0/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][0][1] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__1/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][0][2] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__2/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][0][3] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__3/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][0][4] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__4/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][0][5] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__5/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][0][6] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__6/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[1][0][7] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__7/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for grid[0][1] +####################################### +####################################### +# Disable Timing for unused grid[0][1][0] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__0/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[0][1][1] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[0][1][2] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[0][1][3] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[0][1][4] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__4/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[0][1][5] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__5/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[0][1][6] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__6/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[0][1][7] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__7/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/* diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_include_netlists.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_include_netlists.v new file mode 100644 index 000000000..69009dff8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_include_netlists.v @@ -0,0 +1,16 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include fabric top-level netlists ----- +`include "fabric_netlists.v" + +`include "and2_output_verilog.v" + +`include "and2_top_formal_verification.v" +`include "and2_formal_random_top_tb.v" diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_top_formal_verification.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_top_formal_verification.v new file mode 100644 index 000000000..7fe4b4b38 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_top_formal_verification.v @@ -0,0 +1,513 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog netlist for pre-configured FPGA fabric by design: and2 +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +module and2_top_formal_verification ( +input [0:0] a, +input [0:0] b, +output [0:0] c); + +// ----- Local wires for FPGA fabric ----- +wire [0:31] gfpga_pad_GPIO_PAD_fm; +wire [0:0] ccff_head_fm; +wire [0:0] ccff_tail_fm; +wire [0:0] prog_clk_fm; +wire [0:0] set_fm; +wire [0:0] reset_fm; +wire [0:0] clk_fm; + +// ----- FPGA top-level module to be capsulated ----- + fpga_top U0_formal_verification ( + .prog_clk(prog_clk_fm[0]), + .set(set_fm[0]), + .reset(reset_fm[0]), + .clk(clk_fm[0]), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD_fm[0:31]), + .ccff_head(ccff_head_fm[0]), + .ccff_tail(ccff_tail_fm[0])); + +// ----- Begin Connect Global ports of FPGA top module ----- + assign set_fm[0] = 1'b0; + assign reset_fm[0] = 1'b0; + assign clk_fm[0] = 1'b0; + assign prog_clk_fm[0] = 1'b0; +// ----- End Connect Global ports of FPGA top module ----- + +// ----- Link BLIF Benchmark I/Os to FPGA I/Os ----- +// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[11] ----- + assign gfpga_pad_GPIO_PAD_fm[11] = a[0]; + +// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[14] ----- + assign gfpga_pad_GPIO_PAD_fm[14] = b[0]; + +// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[1] ----- + assign c[0] = gfpga_pad_GPIO_PAD_fm[1]; + +// ----- Wire unused FPGA I/Os to constants ----- + assign gfpga_pad_GPIO_PAD_fm[0] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[2] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[3] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[4] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[5] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[6] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[7] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[8] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[9] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[10] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[12] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[13] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[15] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[16] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[17] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[18] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[19] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[20] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[21] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[22] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[23] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[24] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[25] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[26] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[27] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[28] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[29] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[30] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[31] = 1'b0; + +// ----- Begin load bitstream to configuration memories ----- +// ----- Begin assign bitstream to configuration memories ----- +initial begin + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = 16'b1010101000000000; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = 16'b0101010111111111; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = 2'b01; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = 2'b10; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_1.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_2.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_3.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_0.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_1.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_2.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_3.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_0.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_1.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = 4'b0110; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = 4'b1001; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = 4'b0111; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b1000; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_12.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_12.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_14.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_14.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_16.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_16.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_18.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_18.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_20.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_20.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_22.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_22.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_24.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_24.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_0.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_4.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_4.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_6.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_6.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_8.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_8.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_10.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_10.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_12.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_12.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_0.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_2.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_2.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_4.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_4.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_6.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_6.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_8.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_8.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_10.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_10.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_14.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_14.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_18.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_20.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_22.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_22.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_24.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_right_track_24.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_7.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_7.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_11.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_11.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_13.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_23.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_23.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_12.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_12.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_14.mem_out[0:2] = 3'b011; + force U0_formal_verification.sb_1__0_.mem_top_track_14.mem_outb[0:2] = 3'b100; + force U0_formal_verification.sb_1__0_.mem_top_track_16.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_16.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_18.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_18.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_20.mem_out[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_20.mem_outb[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_22.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_22.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_24.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_24.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_1.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_3.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_3.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_5.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_7.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_9.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_11.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_13.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_13.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_15.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_15.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_17.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_17.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_19.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_19.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_21.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_21.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_23.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_23.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_left_track_25.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_left_track_25.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_5.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_7.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_7.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_9.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_11.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_11.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_13.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_13.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_15.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_15.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_23.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_23.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_25.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_bottom_track_25.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_1.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_out[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_outb[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_11.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_13.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_13.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_15.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_15.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_19.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_19.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_21.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_21.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_23.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_23.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_25.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_25.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_2.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_3.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_3.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_4.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_4.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_5.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_5.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_6.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_6.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_7.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__0_.mem_top_ipin_7.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:2] = 3'b001; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_outb[0:2] = 3'b110; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_4.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_4.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_5.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_5.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_1.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_2.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_3.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_3.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_4.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_4.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_5.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_5.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_6.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_6.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_7.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_0__1_.mem_right_ipin_7.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_0.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_1.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_7.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_7.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_out[0:2] = 3'b101; + force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_outb[0:2] = 3'b010; + force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_out[0:2] = 3'b110; + force U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_outb[0:2] = 3'b001; +end +// ----- End assign bitstream to configuration memories ----- +// ----- End load bitstream to configuration memories ----- +// ------ Use DUMP_FSDB to enable FSDB waveform output ----- +`ifdef DUMP_FSDB +initial begin + $fsdbDumpfile("and2.fsdb"); + $fsdbDumpvars(0, "U0_formal_verification"); +end +`endif +// ------ Use DUMP_VCD to enable VCD waveform output ----- +`ifdef DUMP_VCD +initial begin + $dumpfile("and2.vcd"); + $dumpvars(0, "U0_formal_verification"); +end +`endif +endmodule +// ----- END Verilog module for and2_top_formal_verification ----- + +//----- Default net type ----- +`default_nettype wire + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/bitstream_distribution.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/bitstream_distribution.xml new file mode 100644 index 000000000..34701b8fb --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/bitstream_distribution.xml @@ -0,0 +1,40 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/cbx_1__0_.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/cbx_1__0_.sdc new file mode 100644 index 000000000..01be1d8ca --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/cbx_1__0_.sdc @@ -0,0 +1,105 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Connection Block cbx_1__0_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/chanx_left_out[0] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/chanx_right_out[0] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/chanx_left_out[1] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/chanx_right_out[1] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/chanx_left_out[2] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/chanx_right_out[2] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/chanx_left_out[3] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/chanx_right_out[3] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/chanx_left_out[4] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/chanx_right_out[4] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/chanx_left_out[5] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/chanx_right_out[5] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/chanx_left_out[6] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/chanx_right_out[6] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/chanx_left_out[7] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/chanx_right_out[7] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/chanx_left_out[8] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/chanx_right_out[8] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/chanx_left_out[9] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/chanx_right_out[9] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/chanx_left_out[10] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/chanx_right_out[10] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/chanx_left_out[11] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/chanx_right_out[11] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/chanx_left_out[12] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/chanx_right_out[12] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/cbx_1__1_.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/cbx_1__1_.sdc new file mode 100644 index 000000000..414bba436 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/cbx_1__1_.sdc @@ -0,0 +1,105 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Connection Block cbx_1__1_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/chanx_left_out[0] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/chanx_right_out[0] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/chanx_left_out[1] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/chanx_right_out[1] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/chanx_left_out[2] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/chanx_right_out[2] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/chanx_left_out[3] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/chanx_right_out[3] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/chanx_left_out[4] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/chanx_right_out[4] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/chanx_left_out[5] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/chanx_right_out[5] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/chanx_left_out[6] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/chanx_right_out[6] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/chanx_left_out[7] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/chanx_right_out[7] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/chanx_left_out[8] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/chanx_right_out[8] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/chanx_left_out[9] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/chanx_right_out[9] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/chanx_left_out[10] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/chanx_right_out[10] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/chanx_left_out[11] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/chanx_right_out[11] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/chanx_left_out[12] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/chanx_right_out[12] 2.272500113e-12 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/cby_0__1_.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/cby_0__1_.sdc new file mode 100644 index 000000000..c5f0741b7 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/cby_0__1_.sdc @@ -0,0 +1,99 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Connection Block cby_0__1_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/chany_bottom_out[0] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/chany_top_out[0] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/chany_bottom_out[1] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/chany_top_out[1] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/chany_bottom_out[2] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/chany_top_out[2] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/chany_bottom_out[3] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/chany_top_out[3] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/chany_bottom_out[4] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/chany_top_out[4] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/chany_bottom_out[5] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/chany_top_out[5] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/chany_bottom_out[6] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/chany_top_out[6] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/chany_bottom_out[7] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/chany_top_out[7] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/chany_bottom_out[8] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/chany_top_out[8] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/chany_bottom_out[9] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/chany_top_out[9] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[10] -to fpga_top/cby_0__1_/chany_bottom_out[10] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[10] -to fpga_top/cby_0__1_/chany_top_out[10] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[11] -to fpga_top/cby_0__1_/chany_bottom_out[11] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[11] -to fpga_top/cby_0__1_/chany_top_out[11] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/chany_bottom_out[12] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/chany_top_out[12] 2.272500113e-12 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[10] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[10] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[11] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[11] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/cby_1__1_.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/cby_1__1_.sdc new file mode 100644 index 000000000..c033fd624 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/cby_1__1_.sdc @@ -0,0 +1,105 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Connection Block cby_1__1_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/chany_bottom_out[0] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/chany_top_out[0] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/chany_bottom_out[1] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/chany_top_out[1] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/chany_bottom_out[2] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/chany_top_out[2] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/chany_bottom_out[3] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/chany_top_out[3] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/chany_bottom_out[4] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/chany_top_out[4] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/chany_bottom_out[5] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/chany_top_out[5] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/chany_bottom_out[6] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/chany_top_out[6] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/chany_bottom_out[7] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/chany_top_out[7] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/chany_bottom_out[8] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/chany_top_out[8] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/chany_bottom_out[9] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/chany_top_out[9] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/chany_bottom_out[10] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/chany_top_out[10] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/chany_bottom_out[11] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/chany_top_out[11] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/chany_bottom_out[12] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/chany_top_out[12] 2.272500113e-12 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11 +set_max_delay -from fpga_top/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/ccff_timing.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/ccff_timing.sdc new file mode 100644 index 000000000..df2b04e23 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/ccff_timing.sdc @@ -0,0 +1,1065 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Timing constraints for configurable chains used in PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time ns + +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__0_/mem_top_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_0__0_/mem_top_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_4/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_4/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_4/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_4/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_6/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_6/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_6/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_6/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_12/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_12/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_12/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_12/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_12/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_12/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_12/DFF_2_/Q -to fpga_top/sb_0__0_/mem_top_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_12/DFF_2_/Q -to fpga_top/sb_0__0_/mem_top_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_14/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_14/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_14/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_14/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_18/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_18/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_18/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_18/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_20/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_20/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_20/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_20/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_20/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_20/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_20/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_22/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_20/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_22/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_22/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_22/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_22/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_22/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_22/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_24/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_22/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_24/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_24/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_24/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_24/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_24/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_top_track_24/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_top_track_24/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__0_/mem_right_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__0_/mem_right_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_2/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_2/DFF_2_/Q -to fpga_top/sb_0__0_/mem_right_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_2/DFF_2_/Q -to fpga_top/sb_0__0_/mem_right_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_12/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_12/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__0_/mem_right_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__0_/mem_right_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_14/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_14/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_14/DFF_2_/Q -to fpga_top/sb_0__0_/mem_right_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_14/DFF_2_/Q -to fpga_top/sb_0__0_/mem_right_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_18/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_18/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_18/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_18/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_20/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_20/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_20/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_20/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_22/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_22/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_22/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_22/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__0_/mem_top_track_2/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_2_/Q -to fpga_top/sb_1__0_/mem_top_track_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_2/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_2/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_2/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_2/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_2/DFF_2_/Q -to fpga_top/sb_1__0_/mem_top_track_4/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_2/DFF_2_/Q -to fpga_top/sb_1__0_/mem_top_track_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_4/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_4/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_4/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_4/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_6/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_4/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_6/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_6/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_6/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_6/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_8/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_6/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_8/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_8/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_8/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_8/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_10/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_8/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_10/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_10/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_10/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_10/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_12/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_10/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_12/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_12/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_12/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_12/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_12/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_12/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_14/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_12/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_14/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_14/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_14/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_14/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_14/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_14/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_14/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_14/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_14/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_14/DFF_2_/Q -to fpga_top/sb_1__0_/mem_top_track_16/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_14/DFF_2_/Q -to fpga_top/sb_1__0_/mem_top_track_16/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_16/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_16/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_16/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_18/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_16/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_18/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_18/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_18/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_18/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_20/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_18/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_20/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_20/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_20/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_20/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_20/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_20/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_22/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_20/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_22/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_22/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_22/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_22/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_22/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_22/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_24/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_22/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_24/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_24/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_24/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_24/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_24/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_top_track_24/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_1/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_top_track_24/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_1/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_1/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__0_/mem_left_track_3/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__0_/mem_left_track_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_3/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_3/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_3/DFF_2_/Q -to fpga_top/sb_1__0_/mem_left_track_5/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_3/DFF_2_/Q -to fpga_top/sb_1__0_/mem_left_track_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_5/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_7/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_7/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_9/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_9/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_9/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_9/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_11/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_11/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_11/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_11/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_13/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_13/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_13/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_13/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_13/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_13/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__0_/mem_left_track_15/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__0_/mem_left_track_15/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_15/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_15/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_15/DFF_2_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_15/DFF_2_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_15/DFF_2_/Q -to fpga_top/sb_1__0_/mem_left_track_17/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_15/DFF_2_/Q -to fpga_top/sb_1__0_/mem_left_track_17/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_17/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_17/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_19/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_19/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_19/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_19/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_21/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_21/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_21/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_21/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_23/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_23/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_23/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_23/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_25/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__0_/mem_left_track_25/DFF_0_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_25/DFF_1_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__0_/mem_left_track_25/DFF_1_/D 2.5 +set_max_delay -from fpga_top/sb_1__0_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/sb_1__0_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_bottom_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_2/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_2/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_2/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_2/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_2/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_3/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_2/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_3/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_3/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_3/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_3/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_3/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_3/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_3/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_4/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_3/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_4/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_4/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_4/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_4/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_4/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_4/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_4/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_4/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_4/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_4/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_5/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_4/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_5/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_5/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_5/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_5/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_5/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_5/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_5/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_5/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_5/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_5/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_6/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_5/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_6/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_6/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_6/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_6/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_6/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_6/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_6/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_6/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_6/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_6/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_7/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_6/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_7/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_7/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_7/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_7/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_7/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_7/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_7/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_7/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_7/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_right_ipin_0/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_right_ipin_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_right_ipin_0/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_right_ipin_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_1__1_/mem_right_ipin_0/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_1__1_/mem_right_ipin_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_1__1_/mem_right_ipin_1/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_1__1_/mem_right_ipin_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_1__1_/mem_right_ipin_1/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_1__1_/mem_right_ipin_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_1__1_/mem_right_ipin_1/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_1__1_/mem_right_ipin_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_1__1_/mem_right_ipin_2/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_1__1_/mem_right_ipin_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_1__1_/mem_right_ipin_2/DFF_1_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_1__1_/mem_right_ipin_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_1__1_/mem_right_ipin_2/DFF_2_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_1__1_/mem_right_ipin_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/cby_1__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/cby_1__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_4_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_5_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_6_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_7_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_8_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_9_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_10_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_11_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_12_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_13_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_14_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_DFF_mem/DFF_15_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/mem_ble4_out_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_0/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_1/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_2/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_0_in_3/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_0/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_1/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_2/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_1_in_3/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_0/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_1/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_2/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_2_in_3/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_0/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_1/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_3_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_0_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_2/DFF_3_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_0_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_0_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_1_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/D 2.5 +set_max_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 5 +set_min_delay -from fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_2_/Q -to fpga_top/grid_clb_1__1_/logical_tile_clb_mode_clb__0/mem_fle_3_in_3/DFF_3_/D 2.5 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc new file mode 100644 index 000000000..022a20fcf --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc @@ -0,0 +1,86 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Disable configurable memory outputs for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q +set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q +set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_mode_default__lut*_*/lut*_DFF_mem/DFF_*_/Q +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_mode_default__lut*_*/lut*_DFF_mem/DFF_*_/QN +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/mem_ble*_out_*/DFF_*_/Q +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/mem_ble*_out_*/DFF_*_/QN +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_*_in_*/DFF_*_/Q +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_*_in_*/DFF_*_/QN diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_configure_ports.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_configure_ports.sdc new file mode 100644 index 000000000..8b39a842d --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_configure_ports.sdc @@ -0,0 +1,82 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Disable configuration outputs of all the programmable cells for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_mode_default__lut*_*/lut*_*_/sram +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_mode_default__lut*_*/lut*_*_/sram_inv +set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/sram +set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/sram +set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/sram +set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/sram +set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/sram +set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/sram +set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/sram +set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/sram +set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/sram_inv +set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/sram_inv +set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/sram_inv +set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/sram_inv +set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/sram_inv +set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/sram_inv +set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/sram_inv +set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/mux_ble*_out_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/mux_ble*_out_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mux_fle_*_in_*/sram +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mux_fle_*_in_*/sram_inv +set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_*_/DIR +set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_*_/DIR +set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_*_/DIR +set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_*_/DIR diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_routing_multiplexer_outputs.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_routing_multiplexer_outputs.sdc new file mode 100644 index 000000000..b8ed3a616 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_routing_multiplexer_outputs.sdc @@ -0,0 +1,42 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Disable routing multiplexer outputs for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/out +set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/out +set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/out +set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/out +set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/out +set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/out +set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/out +set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/out +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/mux_ble*_out_*/out +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mux_fle_*_in_*/out diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_sb_outputs.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_sb_outputs.sdc new file mode 100644 index 000000000..f8c3c394f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_sb_outputs.sdc @@ -0,0 +1,32 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Disable Switch Block outputs for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +set_disable_timing fpga_top/sb_*__*_/chany_top_out + +set_disable_timing fpga_top/sb_*__*_/chanx_right_out + +set_disable_timing fpga_top/sb_*__*_/ccff_tail + +set_disable_timing fpga_top/sb_*__*_/chanx_right_out + +set_disable_timing fpga_top/sb_*__*_/chany_bottom_out + +set_disable_timing fpga_top/sb_*__*_/ccff_tail + +set_disable_timing fpga_top/sb_*__*_/chany_top_out + +set_disable_timing fpga_top/sb_*__*_/chanx_left_out + +set_disable_timing fpga_top/sb_*__*_/ccff_tail + +set_disable_timing fpga_top/sb_*__*_/chany_bottom_out + +set_disable_timing fpga_top/sb_*__*_/chanx_left_out + +set_disable_timing fpga_top/sb_*__*_/ccff_tail + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.bit b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.bit new file mode 100644 index 000000000..3387708eb --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.bit @@ -0,0 +1,530 @@ +// Fabric bitstream +// Bitstream length: 527 +// Bitstream width (LSB -> MSB): 1 +1 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +0 +1 +0 +1 +0 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +0 +0 +0 +1 +0 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +0 +0 +0 +0 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +1 +1 +1 +1 +0 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.xml new file mode 100644 index 000000000..4edf9cf2b --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.xml @@ -0,0 +1,1064 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_io_location.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_io_location.xml new file mode 100644 index 000000000..e7000bde6 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_io_location.xml @@ -0,0 +1,39 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_netlists.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_netlists.v new file mode 100644 index 000000000..053caefe2 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_netlists.v @@ -0,0 +1,52 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Fabric Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +// ------ Include defines: preproc flags ----- +`include "fpga_defines.v" + +// ------ Include user-defined netlists ----- +`include "openfpga_flow/openfpga_cell_library/verilog/dff.v" +`include "openfpga_flow/openfpga_cell_library/verilog/gpio.v" +// ------ Include primitive module netlists ----- +`include "sub_module/inv_buf_passgate.v" +`include "sub_module/arch_encoder.v" +`include "sub_module/local_encoder.v" +`include "sub_module/mux_primitives.v" +`include "sub_module/muxes.v" +`include "sub_module/luts.v" +`include "sub_module/wires.v" +`include "sub_module/memories.v" +`include "sub_module/shift_register_banks.v" + +// ------ Include logic block netlists ----- +`include "lb/logical_tile_io_mode_physical__iopad.v" +`include "lb/logical_tile_io_mode_io_.v" +`include "lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v" +`include "lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v" +`include "lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v" +`include "lb/logical_tile_clb_mode_default__fle.v" +`include "lb/logical_tile_clb_mode_clb_.v" +`include "lb/grid_io_top.v" +`include "lb/grid_io_right.v" +`include "lb/grid_io_bottom.v" +`include "lb/grid_io_left.v" +`include "lb/grid_clb.v" + +// ------ Include routing module netlists ----- +`include "routing/sb_0__0_.v" +`include "routing/sb_0__1_.v" +`include "routing/sb_1__0_.v" +`include "routing/sb_1__1_.v" +`include "routing/cbx_1__0_.v" +`include "routing/cbx_1__1_.v" +`include "routing/cby_0__1_.v" +`include "routing/cby_1__1_.v" + +// ------ Include tile module netlists ----- + +// ------ Include fabric top-level netlists ----- +`include "fpga_top.v" + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_pin_phy_loc.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_pin_phy_loc.xml new file mode 100644 index 000000000..603d120a5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_pin_phy_loc.xml @@ -0,0 +1,644 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fpga_defines.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fpga_defines.v new file mode 100644 index 000000000..82aab8ef1 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fpga_defines.v @@ -0,0 +1,8 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Preprocessing flags to enable/disable features in FPGA Verilog modules +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +`define ENABLE_TIMING 1 + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fpga_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fpga_top.v new file mode 100644 index 000000000..c8c3d7300 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fpga_top.v @@ -0,0 +1,460 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Top-level Verilog module for FPGA +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for fpga_top ----- +module fpga_top(prog_clk, + set, + reset, + clk, + gfpga_pad_GPIO_PAD, + ccff_head, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- GLOBAL PORTS ----- +input [0:0] set; +//----- GLOBAL PORTS ----- +input [0:0] reset; +//----- GLOBAL PORTS ----- +input [0:0] clk; +//----- GPIO PORTS ----- +inout [0:31] gfpga_pad_GPIO_PAD; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_; +wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_; +wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_; +wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_; +wire [0:0] cbx_1__0__0_ccff_tail; +wire [0:12] cbx_1__0__0_chanx_left_out; +wire [0:12] cbx_1__0__0_chanx_right_out; +wire [0:0] cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_; +wire [0:0] cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_; +wire [0:0] cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_; +wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_; +wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_; +wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_; +wire [0:0] cbx_1__1__0_ccff_tail; +wire [0:12] cbx_1__1__0_chanx_left_out; +wire [0:12] cbx_1__1__0_chanx_right_out; +wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_; +wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_; +wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_; +wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_; +wire [0:0] cby_0__1__0_ccff_tail; +wire [0:12] cby_0__1__0_chany_bottom_out; +wire [0:12] cby_0__1__0_chany_top_out; +wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_; +wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_; +wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_; +wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_; +wire [0:0] cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_; +wire [0:0] cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_7_; +wire [0:0] cby_1__1__0_ccff_tail; +wire [0:12] cby_1__1__0_chany_bottom_out; +wire [0:12] cby_1__1__0_chany_top_out; +wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_1_; +wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_5_; +wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_9_; +wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; +wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; +wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; +wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; +wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_; +wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_; +wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_; +wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_; +wire [0:0] grid_clb_0_bottom_width_0_height_0_subtile_0__pin_O_0_; +wire [0:0] grid_clb_0_left_width_0_height_0_subtile_0__pin_O_1_; +wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_3_; +wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_; +wire [0:0] grid_io_bottom_0_ccff_tail; +wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_; +wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_; +wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_; +wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_; +wire [0:0] grid_io_left_0_ccff_tail; +wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_4__pin_inpad_0_; +wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_; +wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_; +wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_; +wire [0:0] grid_io_right_0_ccff_tail; +wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_; +wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_; +wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_; +wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_; +wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_; +wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_; +wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_; +wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_; +wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_; +wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_; +wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_; +wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_; +wire [0:0] grid_io_top_0_ccff_tail; +wire [0:0] sb_0__0__0_ccff_tail; +wire [0:12] sb_0__0__0_chanx_right_out; +wire [0:12] sb_0__0__0_chany_top_out; +wire [0:0] sb_0__1__0_ccff_tail; +wire [0:12] sb_0__1__0_chanx_right_out; +wire [0:12] sb_0__1__0_chany_bottom_out; +wire [0:0] sb_1__0__0_ccff_tail; +wire [0:12] sb_1__0__0_chanx_left_out; +wire [0:12] sb_1__0__0_chany_top_out; +wire [0:0] sb_1__1__0_ccff_tail; +wire [0:12] sb_1__1__0_chanx_left_out; +wire [0:12] sb_1__1__0_chany_bottom_out; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + grid_io_top grid_io_top_1__2_ ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0:7]), + .bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_), + .bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), + .bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), + .bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), + .ccff_head(cbx_1__1__0_ccff_tail), + .bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_), + .bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_), + .bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_), + .bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_), + .ccff_tail(grid_io_top_0_ccff_tail)); + + grid_io_right grid_io_right_2__1_ ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[8:15]), + .left_width_0_height_0_subtile_0__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .left_width_0_height_0_subtile_1__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .left_width_0_height_0_subtile_2__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .left_width_0_height_0_subtile_3__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .left_width_0_height_0_subtile_4__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_), + .left_width_0_height_0_subtile_5__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_), + .left_width_0_height_0_subtile_6__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_), + .left_width_0_height_0_subtile_7__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_), + .ccff_head(grid_io_bottom_0_ccff_tail), + .left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_), + .left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_), + .left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_), + .left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_), + .left_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_), + .left_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_), + .left_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_), + .left_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_), + .ccff_tail(grid_io_right_0_ccff_tail)); + + grid_io_bottom grid_io_bottom_1__0_ ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[16:23]), + .top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .top_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_), + .top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), + .top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), + .top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), + .ccff_head(ccff_head), + .top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), + .top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), + .top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), + .top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_), + .top_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_), + .top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_), + .top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_), + .top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_), + .ccff_tail(grid_io_bottom_0_ccff_tail)); + + grid_io_left grid_io_left_0__1_ ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[24:31]), + .right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .right_width_0_height_0_subtile_4__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_), + .right_width_0_height_0_subtile_5__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_), + .right_width_0_height_0_subtile_6__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_), + .right_width_0_height_0_subtile_7__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_), + .ccff_head(cby_0__1__0_ccff_tail), + .right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_), + .right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_), + .right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_), + .right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_), + .right_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_4__pin_inpad_0_), + .right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_), + .right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_), + .right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_), + .ccff_tail(grid_io_left_0_ccff_tail)); + + grid_clb grid_clb_1__1_ ( + .prog_clk(prog_clk), + .set(set), + .reset(reset), + .clk(clk), + .top_width_0_height_0_subtile_0__pin_I_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_), + .top_width_0_height_0_subtile_0__pin_I_4_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_), + .top_width_0_height_0_subtile_0__pin_I_8_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_), + .right_width_0_height_0_subtile_0__pin_I_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_1_), + .right_width_0_height_0_subtile_0__pin_I_5_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_5_), + .right_width_0_height_0_subtile_0__pin_I_9_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_9_), + .bottom_width_0_height_0_subtile_0__pin_I_2_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_), + .bottom_width_0_height_0_subtile_0__pin_I_6_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_), + .bottom_width_0_height_0_subtile_0__pin_clk_0_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_), + .left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), + .left_width_0_height_0_subtile_0__pin_I_7_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_7_), + .ccff_head(cby_1__1__0_ccff_tail), + .top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), + .right_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_3_), + .bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_bottom_width_0_height_0_subtile_0__pin_O_0_), + .left_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_left_width_0_height_0_subtile_0__pin_O_1_), + .ccff_tail(ccff_tail)); + + sb_0__0_ sb_0__0_ ( + .prog_clk(prog_clk), + .chany_top_in(cby_0__1__0_chany_bottom_out[0:12]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_4__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_), + .top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_left_width_0_height_0_subtile_0__pin_O_1_), + .chanx_right_in(cbx_1__0__0_chanx_left_out[0:12]), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_bottom_width_0_height_0_subtile_0__pin_O_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_), + .ccff_head(sb_0__1__0_ccff_tail), + .chany_top_out(sb_0__0__0_chany_top_out[0:12]), + .chanx_right_out(sb_0__0__0_chanx_right_out[0:12]), + .ccff_tail(sb_0__0__0_ccff_tail)); + + sb_0__1_ sb_0__1_ ( + .prog_clk(prog_clk), + .chanx_right_in(cbx_1__1__0_chanx_left_out[0:12]), + .right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_), + .right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_), + .right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), + .chany_bottom_in(cby_0__1__0_chany_top_out[0:12]), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_left_width_0_height_0_subtile_0__pin_O_1_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_4__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_), + .ccff_head(grid_io_top_0_ccff_tail), + .chanx_right_out(sb_0__1__0_chanx_right_out[0:12]), + .chany_bottom_out(sb_0__1__0_chany_bottom_out[0:12]), + .ccff_tail(sb_0__1__0_ccff_tail)); + + sb_1__0_ sb_1__0_ ( + .prog_clk(prog_clk), + .chany_top_in(cby_1__1__0_chany_bottom_out[0:12]), + .top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_3_), + .top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_), + .top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_), + .chanx_left_in(cbx_1__0__0_chanx_right_out[0:12]), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_bottom_width_0_height_0_subtile_0__pin_O_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_), + .ccff_head(grid_io_left_0_ccff_tail), + .chany_top_out(sb_1__0__0_chany_top_out[0:12]), + .chanx_left_out(sb_1__0__0_chanx_left_out[0:12]), + .ccff_tail(sb_1__0__0_ccff_tail)); + + sb_1__1_ sb_1__1_ ( + .prog_clk(prog_clk), + .chany_bottom_in(cby_1__1__0_chany_top_out[0:12]), + .bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_), + .bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_), + .bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_3_), + .chanx_left_in(cbx_1__1__0_chanx_right_out[0:12]), + .left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_), + .left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_), + .left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_), + .ccff_head(grid_io_right_0_ccff_tail), + .chany_bottom_out(sb_1__1__0_chany_bottom_out[0:12]), + .chanx_left_out(sb_1__1__0_chanx_left_out[0:12]), + .ccff_tail(sb_1__1__0_ccff_tail)); + + cbx_1__0_ cbx_1__0_ ( + .prog_clk(prog_clk), + .chanx_left_in(sb_0__0__0_chanx_right_out[0:12]), + .chanx_right_in(sb_1__0__0_chanx_left_out[0:12]), + .ccff_head(sb_1__0__0_ccff_tail), + .chanx_left_out(cbx_1__0__0_chanx_left_out[0:12]), + .chanx_right_out(cbx_1__0__0_chanx_right_out[0:12]), + .top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_), + .top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_), + .top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_), + .ccff_tail(cbx_1__0__0_ccff_tail)); + + cbx_1__1_ cbx_1__1_ ( + .prog_clk(prog_clk), + .chanx_left_in(sb_0__1__0_chanx_right_out[0:12]), + .chanx_right_in(sb_1__1__0_chanx_left_out[0:12]), + .ccff_head(sb_1__1__0_ccff_tail), + .chanx_left_out(cbx_1__1__0_chanx_left_out[0:12]), + .chanx_right_out(cbx_1__1__0_chanx_right_out[0:12]), + .top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_), + .top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_), + .bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_), + .ccff_tail(cbx_1__1__0_ccff_tail)); + + cby_0__1_ cby_0__1_ ( + .prog_clk(prog_clk), + .chany_bottom_in(sb_0__0__0_chany_top_out[0:12]), + .chany_top_in(sb_0__1__0_chany_bottom_out[0:12]), + .ccff_head(sb_0__0__0_ccff_tail), + .chany_bottom_out(cby_0__1__0_chany_bottom_out[0:12]), + .chany_top_out(cby_0__1__0_chany_top_out[0:12]), + .right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_), + .right_grid_left_width_0_height_0_subtile_0__pin_I_7_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_7_), + .left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_), + .ccff_tail(cby_0__1__0_ccff_tail)); + + cby_1__1_ cby_1__1_ ( + .prog_clk(prog_clk), + .chany_bottom_in(sb_1__0__0_chany_top_out[0:12]), + .chany_top_in(sb_1__1__0_chany_bottom_out[0:12]), + .ccff_head(cbx_1__0__0_ccff_tail), + .chany_bottom_out(cby_1__1__0_chany_bottom_out[0:12]), + .chany_top_out(cby_1__1__0_chany_top_out[0:12]), + .right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_), + .right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_), + .left_grid_right_width_0_height_0_subtile_0__pin_I_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_1_), + .left_grid_right_width_0_height_0_subtile_0__pin_I_5_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_5_), + .left_grid_right_width_0_height_0_subtile_0__pin_I_9_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_9_), + .ccff_tail(cby_1__1__0_ccff_tail)); + +endmodule +// ----- END Verilog module for fpga_top ----- + +//----- Default net type ----- +`default_nettype wire + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/global_ports.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/global_ports.sdc new file mode 100644 index 000000000..f072bac09 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/global_ports.sdc @@ -0,0 +1,21 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Clock contraints for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +################################################## +# Create clock +################################################## +create_clock -name clk[0] -period 9.761719211e-10 -waveform {0 4.880859605e-10} [get_ports {clk[0]}] +################################################## +# Create programmable clock +################################################## +create_clock -name prog_clk[0] -period 9.999999939e-09 -waveform {0 4.99999997e-09} [get_ports {prog_clk[0]}] diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cbx_0__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cbx_0__0_.xml new file mode 100644 index 000000000..88ecd4adb --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cbx_0__0_.xml @@ -0,0 +1,2 @@ + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cbx_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cbx_0__1_.xml new file mode 100644 index 000000000..e65930df0 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cbx_0__1_.xml @@ -0,0 +1,2 @@ + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cbx_1__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cbx_1__0_.xml new file mode 100644 index 000000000..39781ad36 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cbx_1__0_.xml @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cbx_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cbx_1__1_.xml new file mode 100644 index 000000000..660956573 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cbx_1__1_.xml @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml new file mode 100644 index 000000000..99aadddf5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml @@ -0,0 +1,82 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml new file mode 100644 index 000000000..f0437dd4b --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml @@ -0,0 +1,2 @@ + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml new file mode 100644 index 000000000..eefaf5cd9 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml new file mode 100644 index 000000000..fe935ebef --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml @@ -0,0 +1,2 @@ + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml new file mode 100644 index 000000000..6a92006a5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml @@ -0,0 +1,132 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml new file mode 100644 index 000000000..24b0e8590 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml @@ -0,0 +1,130 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml new file mode 100644 index 000000000..10e1516e5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml @@ -0,0 +1,132 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml new file mode 100644 index 000000000..7725a1d9d --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml @@ -0,0 +1,130 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_0__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_0__0_.xml new file mode 100644 index 000000000..88ecd4adb --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_0__0_.xml @@ -0,0 +1,2 @@ + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_0__1_.xml new file mode 100644 index 000000000..e65930df0 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_0__1_.xml @@ -0,0 +1,2 @@ + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_1__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_1__0_.xml new file mode 100644 index 000000000..1bb2753a1 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_1__0_.xml @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_1__1_.xml new file mode 100644 index 000000000..aa95d1a45 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_1__1_.xml @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml new file mode 100644 index 000000000..5ecb11950 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml @@ -0,0 +1,82 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml new file mode 100644 index 000000000..f0437dd4b --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml @@ -0,0 +1,2 @@ + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml new file mode 100644 index 000000000..edec22d72 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml new file mode 100644 index 000000000..fe935ebef --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml @@ -0,0 +1,2 @@ + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_0__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_0__0_.xml new file mode 100644 index 000000000..e1012a9b1 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_0__0_.xml @@ -0,0 +1,132 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_0__1_.xml new file mode 100644 index 000000000..18eb5f107 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_0__1_.xml @@ -0,0 +1,130 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_1__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_1__0_.xml new file mode 100644 index 000000000..fcf4a8552 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_1__0_.xml @@ -0,0 +1,132 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_1__1_.xml new file mode 100644 index 000000000..86d1919ea --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_1__1_.xml @@ -0,0 +1,130 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_clb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_clb.v new file mode 100644 index 000000000..d7433dd3f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_clb.v @@ -0,0 +1,110 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for physical tile: clb] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +// ----- BEGIN Grid Verilog module: grid_clb ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for grid_clb ----- +module grid_clb(prog_clk, + set, + reset, + clk, + top_width_0_height_0_subtile_0__pin_I_0_, + top_width_0_height_0_subtile_0__pin_I_4_, + top_width_0_height_0_subtile_0__pin_I_8_, + right_width_0_height_0_subtile_0__pin_I_1_, + right_width_0_height_0_subtile_0__pin_I_5_, + right_width_0_height_0_subtile_0__pin_I_9_, + bottom_width_0_height_0_subtile_0__pin_I_2_, + bottom_width_0_height_0_subtile_0__pin_I_6_, + bottom_width_0_height_0_subtile_0__pin_clk_0_, + left_width_0_height_0_subtile_0__pin_I_3_, + left_width_0_height_0_subtile_0__pin_I_7_, + ccff_head, + top_width_0_height_0_subtile_0__pin_O_2_, + right_width_0_height_0_subtile_0__pin_O_3_, + bottom_width_0_height_0_subtile_0__pin_O_0_, + left_width_0_height_0_subtile_0__pin_O_1_, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- GLOBAL PORTS ----- +input [0:0] set; +//----- GLOBAL PORTS ----- +input [0:0] reset; +//----- GLOBAL PORTS ----- +input [0:0] clk; +//----- INPUT PORTS ----- +input [0:0] top_width_0_height_0_subtile_0__pin_I_0_; +//----- INPUT PORTS ----- +input [0:0] top_width_0_height_0_subtile_0__pin_I_4_; +//----- INPUT PORTS ----- +input [0:0] top_width_0_height_0_subtile_0__pin_I_8_; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_0__pin_I_1_; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_0__pin_I_5_; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_0__pin_I_9_; +//----- INPUT PORTS ----- +input [0:0] bottom_width_0_height_0_subtile_0__pin_I_2_; +//----- INPUT PORTS ----- +input [0:0] bottom_width_0_height_0_subtile_0__pin_I_6_; +//----- INPUT PORTS ----- +input [0:0] bottom_width_0_height_0_subtile_0__pin_clk_0_; +//----- INPUT PORTS ----- +input [0:0] left_width_0_height_0_subtile_0__pin_I_3_; +//----- INPUT PORTS ----- +input [0:0] left_width_0_height_0_subtile_0__pin_I_7_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] top_width_0_height_0_subtile_0__pin_O_2_; +//----- OUTPUT PORTS ----- +output [0:0] right_width_0_height_0_subtile_0__pin_O_3_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_width_0_height_0_subtile_0__pin_O_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_width_0_height_0_subtile_0__pin_O_1_; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( + .prog_clk(prog_clk), + .set(set), + .reset(reset), + .clk(clk), + .clb_I({top_width_0_height_0_subtile_0__pin_I_0_, right_width_0_height_0_subtile_0__pin_I_1_, bottom_width_0_height_0_subtile_0__pin_I_2_, left_width_0_height_0_subtile_0__pin_I_3_, top_width_0_height_0_subtile_0__pin_I_4_, right_width_0_height_0_subtile_0__pin_I_5_, bottom_width_0_height_0_subtile_0__pin_I_6_, left_width_0_height_0_subtile_0__pin_I_7_, top_width_0_height_0_subtile_0__pin_I_8_, right_width_0_height_0_subtile_0__pin_I_9_}), + .clb_clk(bottom_width_0_height_0_subtile_0__pin_clk_0_), + .ccff_head(ccff_head), + .clb_O({bottom_width_0_height_0_subtile_0__pin_O_0_, left_width_0_height_0_subtile_0__pin_O_1_, top_width_0_height_0_subtile_0__pin_O_2_, right_width_0_height_0_subtile_0__pin_O_3_}), + .ccff_tail(ccff_tail)); + +endmodule +// ----- END Verilog module for grid_clb ----- + +//----- Default net type ----- +`default_nettype wire + + + +// ----- END Grid Verilog module: grid_clb ----- + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_io_bottom.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_io_bottom.v new file mode 100644 index 000000000..9ff8b229f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_io_bottom.v @@ -0,0 +1,167 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for physical tile: io] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +// ----- BEGIN Grid Verilog module: grid_io_bottom ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for grid_io_bottom ----- +module grid_io_bottom(prog_clk, + gfpga_pad_GPIO_PAD, + top_width_0_height_0_subtile_0__pin_outpad_0_, + top_width_0_height_0_subtile_1__pin_outpad_0_, + top_width_0_height_0_subtile_2__pin_outpad_0_, + top_width_0_height_0_subtile_3__pin_outpad_0_, + top_width_0_height_0_subtile_4__pin_outpad_0_, + top_width_0_height_0_subtile_5__pin_outpad_0_, + top_width_0_height_0_subtile_6__pin_outpad_0_, + top_width_0_height_0_subtile_7__pin_outpad_0_, + ccff_head, + top_width_0_height_0_subtile_0__pin_inpad_0_, + top_width_0_height_0_subtile_1__pin_inpad_0_, + top_width_0_height_0_subtile_2__pin_inpad_0_, + top_width_0_height_0_subtile_3__pin_inpad_0_, + top_width_0_height_0_subtile_4__pin_inpad_0_, + top_width_0_height_0_subtile_5__pin_inpad_0_, + top_width_0_height_0_subtile_6__pin_inpad_0_, + top_width_0_height_0_subtile_7__pin_inpad_0_, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- GPIO PORTS ----- +inout [0:7] gfpga_pad_GPIO_PAD; +//----- INPUT PORTS ----- +input [0:0] top_width_0_height_0_subtile_0__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_width_0_height_0_subtile_1__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_width_0_height_0_subtile_2__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_width_0_height_0_subtile_3__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_width_0_height_0_subtile_4__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_width_0_height_0_subtile_5__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_width_0_height_0_subtile_6__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_width_0_height_0_subtile_7__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] top_width_0_height_0_subtile_0__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_width_0_height_0_subtile_1__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_width_0_height_0_subtile_2__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_width_0_height_0_subtile_3__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_width_0_height_0_subtile_4__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_width_0_height_0_subtile_5__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_width_0_height_0_subtile_6__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_width_0_height_0_subtile_7__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] logical_tile_io_mode_io__0_ccff_tail; +wire [0:0] logical_tile_io_mode_io__1_ccff_tail; +wire [0:0] logical_tile_io_mode_io__2_ccff_tail; +wire [0:0] logical_tile_io_mode_io__3_ccff_tail; +wire [0:0] logical_tile_io_mode_io__4_ccff_tail; +wire [0:0] logical_tile_io_mode_io__5_ccff_tail; +wire [0:0] logical_tile_io_mode_io__6_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]), + .io_outpad(top_width_0_height_0_subtile_0__pin_outpad_0_), + .ccff_head(ccff_head), + .io_inpad(top_width_0_height_0_subtile_0__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__0_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__1 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]), + .io_outpad(top_width_0_height_0_subtile_1__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__0_ccff_tail), + .io_inpad(top_width_0_height_0_subtile_1__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__1_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__2 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]), + .io_outpad(top_width_0_height_0_subtile_2__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__1_ccff_tail), + .io_inpad(top_width_0_height_0_subtile_2__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__2_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__3 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]), + .io_outpad(top_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__2_ccff_tail), + .io_inpad(top_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__3_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__4 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]), + .io_outpad(top_width_0_height_0_subtile_4__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__3_ccff_tail), + .io_inpad(top_width_0_height_0_subtile_4__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__4_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]), + .io_outpad(top_width_0_height_0_subtile_5__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__4_ccff_tail), + .io_inpad(top_width_0_height_0_subtile_5__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__5_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__6 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]), + .io_outpad(top_width_0_height_0_subtile_6__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__5_ccff_tail), + .io_inpad(top_width_0_height_0_subtile_6__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__6_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__7 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]), + .io_outpad(top_width_0_height_0_subtile_7__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__6_ccff_tail), + .io_inpad(top_width_0_height_0_subtile_7__pin_inpad_0_), + .ccff_tail(ccff_tail)); + +endmodule +// ----- END Verilog module for grid_io_bottom ----- + +//----- Default net type ----- +`default_nettype wire + + + +// ----- END Grid Verilog module: grid_io_bottom ----- + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_io_left.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_io_left.v new file mode 100644 index 000000000..f93e0c6ea --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_io_left.v @@ -0,0 +1,167 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for physical tile: io] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +// ----- BEGIN Grid Verilog module: grid_io_left ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for grid_io_left ----- +module grid_io_left(prog_clk, + gfpga_pad_GPIO_PAD, + right_width_0_height_0_subtile_0__pin_outpad_0_, + right_width_0_height_0_subtile_1__pin_outpad_0_, + right_width_0_height_0_subtile_2__pin_outpad_0_, + right_width_0_height_0_subtile_3__pin_outpad_0_, + right_width_0_height_0_subtile_4__pin_outpad_0_, + right_width_0_height_0_subtile_5__pin_outpad_0_, + right_width_0_height_0_subtile_6__pin_outpad_0_, + right_width_0_height_0_subtile_7__pin_outpad_0_, + ccff_head, + right_width_0_height_0_subtile_0__pin_inpad_0_, + right_width_0_height_0_subtile_1__pin_inpad_0_, + right_width_0_height_0_subtile_2__pin_inpad_0_, + right_width_0_height_0_subtile_3__pin_inpad_0_, + right_width_0_height_0_subtile_4__pin_inpad_0_, + right_width_0_height_0_subtile_5__pin_inpad_0_, + right_width_0_height_0_subtile_6__pin_inpad_0_, + right_width_0_height_0_subtile_7__pin_inpad_0_, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- GPIO PORTS ----- +inout [0:7] gfpga_pad_GPIO_PAD; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_0__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_1__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_2__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_3__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_4__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_5__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_6__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_width_0_height_0_subtile_7__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] right_width_0_height_0_subtile_0__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_width_0_height_0_subtile_1__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_width_0_height_0_subtile_2__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_width_0_height_0_subtile_3__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_width_0_height_0_subtile_4__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_width_0_height_0_subtile_5__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_width_0_height_0_subtile_6__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_width_0_height_0_subtile_7__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] logical_tile_io_mode_io__0_ccff_tail; +wire [0:0] logical_tile_io_mode_io__1_ccff_tail; +wire [0:0] logical_tile_io_mode_io__2_ccff_tail; +wire [0:0] logical_tile_io_mode_io__3_ccff_tail; +wire [0:0] logical_tile_io_mode_io__4_ccff_tail; +wire [0:0] logical_tile_io_mode_io__5_ccff_tail; +wire [0:0] logical_tile_io_mode_io__6_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]), + .io_outpad(right_width_0_height_0_subtile_0__pin_outpad_0_), + .ccff_head(ccff_head), + .io_inpad(right_width_0_height_0_subtile_0__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__0_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__1 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]), + .io_outpad(right_width_0_height_0_subtile_1__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__0_ccff_tail), + .io_inpad(right_width_0_height_0_subtile_1__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__1_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__2 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]), + .io_outpad(right_width_0_height_0_subtile_2__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__1_ccff_tail), + .io_inpad(right_width_0_height_0_subtile_2__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__2_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__3 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]), + .io_outpad(right_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__2_ccff_tail), + .io_inpad(right_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__3_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__4 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]), + .io_outpad(right_width_0_height_0_subtile_4__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__3_ccff_tail), + .io_inpad(right_width_0_height_0_subtile_4__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__4_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]), + .io_outpad(right_width_0_height_0_subtile_5__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__4_ccff_tail), + .io_inpad(right_width_0_height_0_subtile_5__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__5_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__6 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]), + .io_outpad(right_width_0_height_0_subtile_6__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__5_ccff_tail), + .io_inpad(right_width_0_height_0_subtile_6__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__6_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__7 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]), + .io_outpad(right_width_0_height_0_subtile_7__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__6_ccff_tail), + .io_inpad(right_width_0_height_0_subtile_7__pin_inpad_0_), + .ccff_tail(ccff_tail)); + +endmodule +// ----- END Verilog module for grid_io_left ----- + +//----- Default net type ----- +`default_nettype wire + + + +// ----- END Grid Verilog module: grid_io_left ----- + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_io_right.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_io_right.v new file mode 100644 index 000000000..9d0a0f05f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_io_right.v @@ -0,0 +1,167 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for physical tile: io] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +// ----- BEGIN Grid Verilog module: grid_io_right ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for grid_io_right ----- +module grid_io_right(prog_clk, + gfpga_pad_GPIO_PAD, + left_width_0_height_0_subtile_0__pin_outpad_0_, + left_width_0_height_0_subtile_1__pin_outpad_0_, + left_width_0_height_0_subtile_2__pin_outpad_0_, + left_width_0_height_0_subtile_3__pin_outpad_0_, + left_width_0_height_0_subtile_4__pin_outpad_0_, + left_width_0_height_0_subtile_5__pin_outpad_0_, + left_width_0_height_0_subtile_6__pin_outpad_0_, + left_width_0_height_0_subtile_7__pin_outpad_0_, + ccff_head, + left_width_0_height_0_subtile_0__pin_inpad_0_, + left_width_0_height_0_subtile_1__pin_inpad_0_, + left_width_0_height_0_subtile_2__pin_inpad_0_, + left_width_0_height_0_subtile_3__pin_inpad_0_, + left_width_0_height_0_subtile_4__pin_inpad_0_, + left_width_0_height_0_subtile_5__pin_inpad_0_, + left_width_0_height_0_subtile_6__pin_inpad_0_, + left_width_0_height_0_subtile_7__pin_inpad_0_, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- GPIO PORTS ----- +inout [0:7] gfpga_pad_GPIO_PAD; +//----- INPUT PORTS ----- +input [0:0] left_width_0_height_0_subtile_0__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_width_0_height_0_subtile_1__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_width_0_height_0_subtile_2__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_width_0_height_0_subtile_3__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_width_0_height_0_subtile_4__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_width_0_height_0_subtile_5__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_width_0_height_0_subtile_6__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_width_0_height_0_subtile_7__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] left_width_0_height_0_subtile_0__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_width_0_height_0_subtile_1__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_width_0_height_0_subtile_2__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_width_0_height_0_subtile_3__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_width_0_height_0_subtile_4__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_width_0_height_0_subtile_5__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_width_0_height_0_subtile_6__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_width_0_height_0_subtile_7__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] logical_tile_io_mode_io__0_ccff_tail; +wire [0:0] logical_tile_io_mode_io__1_ccff_tail; +wire [0:0] logical_tile_io_mode_io__2_ccff_tail; +wire [0:0] logical_tile_io_mode_io__3_ccff_tail; +wire [0:0] logical_tile_io_mode_io__4_ccff_tail; +wire [0:0] logical_tile_io_mode_io__5_ccff_tail; +wire [0:0] logical_tile_io_mode_io__6_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]), + .io_outpad(left_width_0_height_0_subtile_0__pin_outpad_0_), + .ccff_head(ccff_head), + .io_inpad(left_width_0_height_0_subtile_0__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__0_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__1 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]), + .io_outpad(left_width_0_height_0_subtile_1__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__0_ccff_tail), + .io_inpad(left_width_0_height_0_subtile_1__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__1_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__2 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]), + .io_outpad(left_width_0_height_0_subtile_2__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__1_ccff_tail), + .io_inpad(left_width_0_height_0_subtile_2__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__2_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__3 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]), + .io_outpad(left_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__2_ccff_tail), + .io_inpad(left_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__3_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__4 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]), + .io_outpad(left_width_0_height_0_subtile_4__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__3_ccff_tail), + .io_inpad(left_width_0_height_0_subtile_4__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__4_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]), + .io_outpad(left_width_0_height_0_subtile_5__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__4_ccff_tail), + .io_inpad(left_width_0_height_0_subtile_5__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__5_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__6 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]), + .io_outpad(left_width_0_height_0_subtile_6__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__5_ccff_tail), + .io_inpad(left_width_0_height_0_subtile_6__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__6_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__7 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]), + .io_outpad(left_width_0_height_0_subtile_7__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__6_ccff_tail), + .io_inpad(left_width_0_height_0_subtile_7__pin_inpad_0_), + .ccff_tail(ccff_tail)); + +endmodule +// ----- END Verilog module for grid_io_right ----- + +//----- Default net type ----- +`default_nettype wire + + + +// ----- END Grid Verilog module: grid_io_right ----- + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_io_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_io_top.v new file mode 100644 index 000000000..af8760fc5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/grid_io_top.v @@ -0,0 +1,167 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for physical tile: io] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +// ----- BEGIN Grid Verilog module: grid_io_top ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for grid_io_top ----- +module grid_io_top(prog_clk, + gfpga_pad_GPIO_PAD, + bottom_width_0_height_0_subtile_0__pin_outpad_0_, + bottom_width_0_height_0_subtile_1__pin_outpad_0_, + bottom_width_0_height_0_subtile_2__pin_outpad_0_, + bottom_width_0_height_0_subtile_3__pin_outpad_0_, + bottom_width_0_height_0_subtile_4__pin_outpad_0_, + bottom_width_0_height_0_subtile_5__pin_outpad_0_, + bottom_width_0_height_0_subtile_6__pin_outpad_0_, + bottom_width_0_height_0_subtile_7__pin_outpad_0_, + ccff_head, + bottom_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_width_0_height_0_subtile_3__pin_inpad_0_, + bottom_width_0_height_0_subtile_4__pin_inpad_0_, + bottom_width_0_height_0_subtile_5__pin_inpad_0_, + bottom_width_0_height_0_subtile_6__pin_inpad_0_, + bottom_width_0_height_0_subtile_7__pin_inpad_0_, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- GPIO PORTS ----- +inout [0:7] gfpga_pad_GPIO_PAD; +//----- INPUT PORTS ----- +input [0:0] bottom_width_0_height_0_subtile_0__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_width_0_height_0_subtile_1__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_width_0_height_0_subtile_2__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_width_0_height_0_subtile_3__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_width_0_height_0_subtile_4__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_width_0_height_0_subtile_5__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_width_0_height_0_subtile_6__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_width_0_height_0_subtile_7__pin_outpad_0_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] bottom_width_0_height_0_subtile_0__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_width_0_height_0_subtile_1__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_width_0_height_0_subtile_2__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_width_0_height_0_subtile_3__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_width_0_height_0_subtile_4__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_width_0_height_0_subtile_5__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_width_0_height_0_subtile_6__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_width_0_height_0_subtile_7__pin_inpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] logical_tile_io_mode_io__0_ccff_tail; +wire [0:0] logical_tile_io_mode_io__1_ccff_tail; +wire [0:0] logical_tile_io_mode_io__2_ccff_tail; +wire [0:0] logical_tile_io_mode_io__3_ccff_tail; +wire [0:0] logical_tile_io_mode_io__4_ccff_tail; +wire [0:0] logical_tile_io_mode_io__5_ccff_tail; +wire [0:0] logical_tile_io_mode_io__6_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]), + .io_outpad(bottom_width_0_height_0_subtile_0__pin_outpad_0_), + .ccff_head(ccff_head), + .io_inpad(bottom_width_0_height_0_subtile_0__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__0_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__1 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]), + .io_outpad(bottom_width_0_height_0_subtile_1__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__0_ccff_tail), + .io_inpad(bottom_width_0_height_0_subtile_1__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__1_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__2 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]), + .io_outpad(bottom_width_0_height_0_subtile_2__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__1_ccff_tail), + .io_inpad(bottom_width_0_height_0_subtile_2__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__2_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__3 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]), + .io_outpad(bottom_width_0_height_0_subtile_3__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__2_ccff_tail), + .io_inpad(bottom_width_0_height_0_subtile_3__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__3_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__4 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]), + .io_outpad(bottom_width_0_height_0_subtile_4__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__3_ccff_tail), + .io_inpad(bottom_width_0_height_0_subtile_4__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__4_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]), + .io_outpad(bottom_width_0_height_0_subtile_5__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__4_ccff_tail), + .io_inpad(bottom_width_0_height_0_subtile_5__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__5_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__6 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]), + .io_outpad(bottom_width_0_height_0_subtile_6__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__5_ccff_tail), + .io_inpad(bottom_width_0_height_0_subtile_6__pin_inpad_0_), + .ccff_tail(logical_tile_io_mode_io__6_ccff_tail)); + + logical_tile_io_mode_io_ logical_tile_io_mode_io__7 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]), + .io_outpad(bottom_width_0_height_0_subtile_7__pin_outpad_0_), + .ccff_head(logical_tile_io_mode_io__6_ccff_tail), + .io_inpad(bottom_width_0_height_0_subtile_7__pin_inpad_0_), + .ccff_tail(ccff_tail)); + +endmodule +// ----- END Verilog module for grid_io_top ----- + +//----- Default net type ----- +`default_nettype wire + + + +// ----- END Grid Verilog module: grid_io_top ----- + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v new file mode 100644 index 000000000..796a7b82a --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v @@ -0,0 +1,424 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for pb_type: clb +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +// ----- BEGIN Physical programmable logic block Verilog module: clb ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for logical_tile_clb_mode_clb_ ----- +module logical_tile_clb_mode_clb_(prog_clk, + set, + reset, + clk, + clb_I, + clb_clk, + ccff_head, + clb_O, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- GLOBAL PORTS ----- +input [0:0] set; +//----- GLOBAL PORTS ----- +input [0:0] reset; +//----- GLOBAL PORTS ----- +input [0:0] clk; +//----- INPUT PORTS ----- +input [0:9] clb_I; +//----- INPUT PORTS ----- +input [0:0] clb_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:3] clb_O; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +wire [0:9] clb_I; +wire [0:0] clb_clk; +wire [0:3] clb_O; +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] direct_interc_4_out; +wire [0:0] direct_interc_5_out; +wire [0:0] direct_interc_6_out; +wire [0:0] direct_interc_7_out; +wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail; +wire [0:0] logical_tile_clb_mode_default__fle_0_fle_out; +wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail; +wire [0:0] logical_tile_clb_mode_default__fle_1_fle_out; +wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail; +wire [0:0] logical_tile_clb_mode_default__fle_2_fle_out; +wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail; +wire [0:0] logical_tile_clb_mode_default__fle_3_fle_out; +wire [0:0] mux_tree_size14_0_out; +wire [0:3] mux_tree_size14_0_sram; +wire [0:3] mux_tree_size14_0_sram_inv; +wire [0:0] mux_tree_size14_10_out; +wire [0:3] mux_tree_size14_10_sram; +wire [0:3] mux_tree_size14_10_sram_inv; +wire [0:0] mux_tree_size14_11_out; +wire [0:3] mux_tree_size14_11_sram; +wire [0:3] mux_tree_size14_11_sram_inv; +wire [0:0] mux_tree_size14_12_out; +wire [0:3] mux_tree_size14_12_sram; +wire [0:3] mux_tree_size14_12_sram_inv; +wire [0:0] mux_tree_size14_13_out; +wire [0:3] mux_tree_size14_13_sram; +wire [0:3] mux_tree_size14_13_sram_inv; +wire [0:0] mux_tree_size14_14_out; +wire [0:3] mux_tree_size14_14_sram; +wire [0:3] mux_tree_size14_14_sram_inv; +wire [0:0] mux_tree_size14_15_out; +wire [0:3] mux_tree_size14_15_sram; +wire [0:3] mux_tree_size14_15_sram_inv; +wire [0:0] mux_tree_size14_1_out; +wire [0:3] mux_tree_size14_1_sram; +wire [0:3] mux_tree_size14_1_sram_inv; +wire [0:0] mux_tree_size14_2_out; +wire [0:3] mux_tree_size14_2_sram; +wire [0:3] mux_tree_size14_2_sram_inv; +wire [0:0] mux_tree_size14_3_out; +wire [0:3] mux_tree_size14_3_sram; +wire [0:3] mux_tree_size14_3_sram_inv; +wire [0:0] mux_tree_size14_4_out; +wire [0:3] mux_tree_size14_4_sram; +wire [0:3] mux_tree_size14_4_sram_inv; +wire [0:0] mux_tree_size14_5_out; +wire [0:3] mux_tree_size14_5_sram; +wire [0:3] mux_tree_size14_5_sram_inv; +wire [0:0] mux_tree_size14_6_out; +wire [0:3] mux_tree_size14_6_sram; +wire [0:3] mux_tree_size14_6_sram_inv; +wire [0:0] mux_tree_size14_7_out; +wire [0:3] mux_tree_size14_7_sram; +wire [0:3] mux_tree_size14_7_sram_inv; +wire [0:0] mux_tree_size14_8_out; +wire [0:3] mux_tree_size14_8_sram; +wire [0:3] mux_tree_size14_8_sram_inv; +wire [0:0] mux_tree_size14_9_out; +wire [0:3] mux_tree_size14_9_sram; +wire [0:3] mux_tree_size14_9_sram_inv; +wire [0:0] mux_tree_size14_mem_0_ccff_tail; +wire [0:0] mux_tree_size14_mem_10_ccff_tail; +wire [0:0] mux_tree_size14_mem_11_ccff_tail; +wire [0:0] mux_tree_size14_mem_12_ccff_tail; +wire [0:0] mux_tree_size14_mem_13_ccff_tail; +wire [0:0] mux_tree_size14_mem_14_ccff_tail; +wire [0:0] mux_tree_size14_mem_1_ccff_tail; +wire [0:0] mux_tree_size14_mem_2_ccff_tail; +wire [0:0] mux_tree_size14_mem_3_ccff_tail; +wire [0:0] mux_tree_size14_mem_4_ccff_tail; +wire [0:0] mux_tree_size14_mem_5_ccff_tail; +wire [0:0] mux_tree_size14_mem_6_ccff_tail; +wire [0:0] mux_tree_size14_mem_7_ccff_tail; +wire [0:0] mux_tree_size14_mem_8_ccff_tail; +wire [0:0] mux_tree_size14_mem_9_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0 ( + .prog_clk(prog_clk), + .set(set), + .reset(reset), + .clk(clk), + .fle_in({mux_tree_size14_0_out, mux_tree_size14_1_out, mux_tree_size14_2_out, mux_tree_size14_3_out}), + .fle_clk(direct_interc_4_out), + .ccff_head(ccff_head), + .fle_out(logical_tile_clb_mode_default__fle_0_fle_out), + .ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail)); + + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1 ( + .prog_clk(prog_clk), + .set(set), + .reset(reset), + .clk(clk), + .fle_in({mux_tree_size14_4_out, mux_tree_size14_5_out, mux_tree_size14_6_out, mux_tree_size14_7_out}), + .fle_clk(direct_interc_5_out), + .ccff_head(logical_tile_clb_mode_default__fle_0_ccff_tail), + .fle_out(logical_tile_clb_mode_default__fle_1_fle_out), + .ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail)); + + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2 ( + .prog_clk(prog_clk), + .set(set), + .reset(reset), + .clk(clk), + .fle_in({mux_tree_size14_8_out, mux_tree_size14_9_out, mux_tree_size14_10_out, mux_tree_size14_11_out}), + .fle_clk(direct_interc_6_out), + .ccff_head(logical_tile_clb_mode_default__fle_1_ccff_tail), + .fle_out(logical_tile_clb_mode_default__fle_2_fle_out), + .ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail)); + + logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3 ( + .prog_clk(prog_clk), + .set(set), + .reset(reset), + .clk(clk), + .fle_in({mux_tree_size14_12_out, mux_tree_size14_13_out, mux_tree_size14_14_out, mux_tree_size14_15_out}), + .fle_clk(direct_interc_7_out), + .ccff_head(logical_tile_clb_mode_default__fle_2_ccff_tail), + .fle_out(logical_tile_clb_mode_default__fle_3_fle_out), + .ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail)); + + direct_interc direct_interc_0_ ( + .in(logical_tile_clb_mode_default__fle_0_fle_out), + .out(clb_O[0])); + + direct_interc direct_interc_1_ ( + .in(logical_tile_clb_mode_default__fle_1_fle_out), + .out(clb_O[1])); + + direct_interc direct_interc_2_ ( + .in(logical_tile_clb_mode_default__fle_2_fle_out), + .out(clb_O[2])); + + direct_interc direct_interc_3_ ( + .in(logical_tile_clb_mode_default__fle_3_fle_out), + .out(clb_O[3])); + + direct_interc direct_interc_4_ ( + .in(clb_clk), + .out(direct_interc_4_out)); + + direct_interc direct_interc_5_ ( + .in(clb_clk), + .out(direct_interc_5_out)); + + direct_interc direct_interc_6_ ( + .in(clb_clk), + .out(direct_interc_6_out)); + + direct_interc direct_interc_7_ ( + .in(clb_clk), + .out(direct_interc_7_out)); + + mux_tree_size14 mux_fle_0_in_0 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_0_sram[0:3]), + .sram_inv(mux_tree_size14_0_sram_inv[0:3]), + .out(mux_tree_size14_0_out)); + + mux_tree_size14 mux_fle_0_in_1 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_1_sram[0:3]), + .sram_inv(mux_tree_size14_1_sram_inv[0:3]), + .out(mux_tree_size14_1_out)); + + mux_tree_size14 mux_fle_0_in_2 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_2_sram[0:3]), + .sram_inv(mux_tree_size14_2_sram_inv[0:3]), + .out(mux_tree_size14_2_out)); + + mux_tree_size14 mux_fle_0_in_3 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_3_sram[0:3]), + .sram_inv(mux_tree_size14_3_sram_inv[0:3]), + .out(mux_tree_size14_3_out)); + + mux_tree_size14 mux_fle_1_in_0 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_4_sram[0:3]), + .sram_inv(mux_tree_size14_4_sram_inv[0:3]), + .out(mux_tree_size14_4_out)); + + mux_tree_size14 mux_fle_1_in_1 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_5_sram[0:3]), + .sram_inv(mux_tree_size14_5_sram_inv[0:3]), + .out(mux_tree_size14_5_out)); + + mux_tree_size14 mux_fle_1_in_2 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_6_sram[0:3]), + .sram_inv(mux_tree_size14_6_sram_inv[0:3]), + .out(mux_tree_size14_6_out)); + + mux_tree_size14 mux_fle_1_in_3 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_7_sram[0:3]), + .sram_inv(mux_tree_size14_7_sram_inv[0:3]), + .out(mux_tree_size14_7_out)); + + mux_tree_size14 mux_fle_2_in_0 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_8_sram[0:3]), + .sram_inv(mux_tree_size14_8_sram_inv[0:3]), + .out(mux_tree_size14_8_out)); + + mux_tree_size14 mux_fle_2_in_1 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_9_sram[0:3]), + .sram_inv(mux_tree_size14_9_sram_inv[0:3]), + .out(mux_tree_size14_9_out)); + + mux_tree_size14 mux_fle_2_in_2 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_10_sram[0:3]), + .sram_inv(mux_tree_size14_10_sram_inv[0:3]), + .out(mux_tree_size14_10_out)); + + mux_tree_size14 mux_fle_2_in_3 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_11_sram[0:3]), + .sram_inv(mux_tree_size14_11_sram_inv[0:3]), + .out(mux_tree_size14_11_out)); + + mux_tree_size14 mux_fle_3_in_0 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_12_sram[0:3]), + .sram_inv(mux_tree_size14_12_sram_inv[0:3]), + .out(mux_tree_size14_12_out)); + + mux_tree_size14 mux_fle_3_in_1 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_13_sram[0:3]), + .sram_inv(mux_tree_size14_13_sram_inv[0:3]), + .out(mux_tree_size14_13_out)); + + mux_tree_size14 mux_fle_3_in_2 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_14_sram[0:3]), + .sram_inv(mux_tree_size14_14_sram_inv[0:3]), + .out(mux_tree_size14_14_out)); + + mux_tree_size14 mux_fle_3_in_3 ( + .in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}), + .sram(mux_tree_size14_15_sram[0:3]), + .sram_inv(mux_tree_size14_15_sram_inv[0:3]), + .out(mux_tree_size14_15_out)); + + mux_tree_size14_mem mem_fle_0_in_0 ( + .prog_clk(prog_clk), + .ccff_head(logical_tile_clb_mode_default__fle_3_ccff_tail), + .ccff_tail(mux_tree_size14_mem_0_ccff_tail), + .mem_out(mux_tree_size14_0_sram[0:3]), + .mem_outb(mux_tree_size14_0_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_0_in_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_0_ccff_tail), + .ccff_tail(mux_tree_size14_mem_1_ccff_tail), + .mem_out(mux_tree_size14_1_sram[0:3]), + .mem_outb(mux_tree_size14_1_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_0_in_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_1_ccff_tail), + .ccff_tail(mux_tree_size14_mem_2_ccff_tail), + .mem_out(mux_tree_size14_2_sram[0:3]), + .mem_outb(mux_tree_size14_2_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_0_in_3 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_2_ccff_tail), + .ccff_tail(mux_tree_size14_mem_3_ccff_tail), + .mem_out(mux_tree_size14_3_sram[0:3]), + .mem_outb(mux_tree_size14_3_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_1_in_0 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_3_ccff_tail), + .ccff_tail(mux_tree_size14_mem_4_ccff_tail), + .mem_out(mux_tree_size14_4_sram[0:3]), + .mem_outb(mux_tree_size14_4_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_1_in_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_4_ccff_tail), + .ccff_tail(mux_tree_size14_mem_5_ccff_tail), + .mem_out(mux_tree_size14_5_sram[0:3]), + .mem_outb(mux_tree_size14_5_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_1_in_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_5_ccff_tail), + .ccff_tail(mux_tree_size14_mem_6_ccff_tail), + .mem_out(mux_tree_size14_6_sram[0:3]), + .mem_outb(mux_tree_size14_6_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_1_in_3 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_6_ccff_tail), + .ccff_tail(mux_tree_size14_mem_7_ccff_tail), + .mem_out(mux_tree_size14_7_sram[0:3]), + .mem_outb(mux_tree_size14_7_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_2_in_0 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_7_ccff_tail), + .ccff_tail(mux_tree_size14_mem_8_ccff_tail), + .mem_out(mux_tree_size14_8_sram[0:3]), + .mem_outb(mux_tree_size14_8_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_2_in_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_8_ccff_tail), + .ccff_tail(mux_tree_size14_mem_9_ccff_tail), + .mem_out(mux_tree_size14_9_sram[0:3]), + .mem_outb(mux_tree_size14_9_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_2_in_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_9_ccff_tail), + .ccff_tail(mux_tree_size14_mem_10_ccff_tail), + .mem_out(mux_tree_size14_10_sram[0:3]), + .mem_outb(mux_tree_size14_10_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_2_in_3 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_10_ccff_tail), + .ccff_tail(mux_tree_size14_mem_11_ccff_tail), + .mem_out(mux_tree_size14_11_sram[0:3]), + .mem_outb(mux_tree_size14_11_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_3_in_0 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_11_ccff_tail), + .ccff_tail(mux_tree_size14_mem_12_ccff_tail), + .mem_out(mux_tree_size14_12_sram[0:3]), + .mem_outb(mux_tree_size14_12_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_3_in_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_12_ccff_tail), + .ccff_tail(mux_tree_size14_mem_13_ccff_tail), + .mem_out(mux_tree_size14_13_sram[0:3]), + .mem_outb(mux_tree_size14_13_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_3_in_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_13_ccff_tail), + .ccff_tail(mux_tree_size14_mem_14_ccff_tail), + .mem_out(mux_tree_size14_14_sram[0:3]), + .mem_outb(mux_tree_size14_14_sram_inv[0:3])); + + mux_tree_size14_mem mem_fle_3_in_3 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_size14_mem_14_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_size14_15_sram[0:3]), + .mem_outb(mux_tree_size14_15_sram_inv[0:3])); + +endmodule +// ----- END Verilog module for logical_tile_clb_mode_clb_ ----- + +//----- Default net type ----- +`default_nettype wire + + + +// ----- END Physical programmable logic block Verilog module: clb ----- diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v new file mode 100644 index 000000000..555071020 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v @@ -0,0 +1,106 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for pb_type: fle +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +// ----- BEGIN Physical programmable logic block Verilog module: fle ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for logical_tile_clb_mode_default__fle ----- +module logical_tile_clb_mode_default__fle(prog_clk, + set, + reset, + clk, + fle_in, + fle_clk, + ccff_head, + fle_out, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- GLOBAL PORTS ----- +input [0:0] set; +//----- GLOBAL PORTS ----- +input [0:0] reset; +//----- GLOBAL PORTS ----- +input [0:0] clk; +//----- INPUT PORTS ----- +input [0:3] fle_in; +//----- INPUT PORTS ----- +input [0:0] fle_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] fle_out; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +wire [0:3] fle_in; +wire [0:0] fle_clk; +wire [0:0] fle_out; +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] direct_interc_1_out; +wire [0:0] direct_interc_2_out; +wire [0:0] direct_interc_3_out; +wire [0:0] direct_interc_4_out; +wire [0:0] direct_interc_5_out; +wire [0:0] logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0_ble4_out; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4 logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0 ( + .prog_clk(prog_clk), + .set(set), + .reset(reset), + .clk(clk), + .ble4_in({direct_interc_1_out, direct_interc_2_out, direct_interc_3_out, direct_interc_4_out}), + .ble4_clk(direct_interc_5_out), + .ccff_head(ccff_head), + .ble4_out(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0_ble4_out), + .ccff_tail(ccff_tail)); + + direct_interc direct_interc_0_ ( + .in(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0_ble4_out), + .out(fle_out)); + + direct_interc direct_interc_1_ ( + .in(fle_in[0]), + .out(direct_interc_1_out)); + + direct_interc direct_interc_2_ ( + .in(fle_in[1]), + .out(direct_interc_2_out)); + + direct_interc direct_interc_3_ ( + .in(fle_in[2]), + .out(direct_interc_3_out)); + + direct_interc direct_interc_4_ ( + .in(fle_in[3]), + .out(direct_interc_4_out)); + + direct_interc direct_interc_5_ ( + .in(fle_clk), + .out(direct_interc_5_out)); + +endmodule +// ----- END Verilog module for logical_tile_clb_mode_default__fle ----- + +//----- Default net type ----- +`default_nettype wire + + + +// ----- END Physical programmable logic block Verilog module: fle ----- diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v new file mode 100644 index 000000000..aab763fac --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v @@ -0,0 +1,128 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for pb_type: ble4 +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +// ----- BEGIN Physical programmable logic block Verilog module: ble4 ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4 ----- +module logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4(prog_clk, + set, + reset, + clk, + ble4_in, + ble4_clk, + ccff_head, + ble4_out, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- GLOBAL PORTS ----- +input [0:0] set; +//----- GLOBAL PORTS ----- +input [0:0] reset; +//----- GLOBAL PORTS ----- +input [0:0] clk; +//----- INPUT PORTS ----- +input [0:3] ble4_in; +//----- INPUT PORTS ----- +input [0:0] ble4_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ble4_out; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +wire [0:3] ble4_in; +wire [0:0] ble4_clk; +wire [0:0] ble4_out; +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] direct_interc_0_out; +wire [0:0] direct_interc_1_out; +wire [0:0] direct_interc_2_out; +wire [0:0] direct_interc_3_out; +wire [0:0] direct_interc_4_out; +wire [0:0] direct_interc_5_out; +wire [0:0] logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0_ff_Q; +wire [0:0] logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_ccff_tail; +wire [0:0] logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_lut4_out; +wire [0:1] mux_tree_tapbuf_size2_0_sram; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4 logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0 ( + .prog_clk(prog_clk), + .lut4_in({direct_interc_0_out, direct_interc_1_out, direct_interc_2_out, direct_interc_3_out}), + .ccff_head(ccff_head), + .lut4_out(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_lut4_out), + .ccff_tail(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_ccff_tail)); + + logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0 ( + .set(set), + .reset(reset), + .clk(clk), + .ff_D(direct_interc_4_out), + .ff_Q(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0_ff_Q), + .ff_clk(direct_interc_5_out)); + + mux_tree_tapbuf_size2 mux_ble4_out_0 ( + .in({logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0_ff_Q, logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_lut4_out}), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(ble4_out)); + + mux_tree_tapbuf_size2_mem mem_ble4_out_0 ( + .prog_clk(prog_clk), + .ccff_head(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); + + direct_interc direct_interc_0_ ( + .in(ble4_in[0]), + .out(direct_interc_0_out)); + + direct_interc direct_interc_1_ ( + .in(ble4_in[1]), + .out(direct_interc_1_out)); + + direct_interc direct_interc_2_ ( + .in(ble4_in[2]), + .out(direct_interc_2_out)); + + direct_interc direct_interc_3_ ( + .in(ble4_in[3]), + .out(direct_interc_3_out)); + + direct_interc direct_interc_4_ ( + .in(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_lut4_out), + .out(direct_interc_4_out)); + + direct_interc direct_interc_5_ ( + .in(ble4_clk), + .out(direct_interc_5_out)); + +endmodule +// ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4 ----- + +//----- Default net type ----- +`default_nettype wire + + + +// ----- END Physical programmable logic block Verilog module: ble4 ----- diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v new file mode 100644 index 000000000..fe3b6bc84 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v @@ -0,0 +1,61 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for primitive pb_type: ff +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff ----- +module logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff(set, + reset, + clk, + ff_D, + ff_Q, + ff_clk); +//----- GLOBAL PORTS ----- +input [0:0] set; +//----- GLOBAL PORTS ----- +input [0:0] reset; +//----- GLOBAL PORTS ----- +input [0:0] clk; +//----- INPUT PORTS ----- +input [0:0] ff_D; +//----- OUTPUT PORTS ----- +output [0:0] ff_Q; +//----- CLOCK PORTS ----- +input [0:0] ff_clk; + +//----- BEGIN wire-connection ports ----- +wire [0:0] ff_D; +wire [0:0] ff_Q; +wire [0:0] ff_clk; +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + DFFSRQ DFFSRQ_0_ ( + .SET(set), + .RST(reset), + .CK(clk), + .D(ff_D), + .Q(ff_Q)); + +endmodule +// ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff ----- + +//----- Default net type ----- +`default_nettype wire + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v new file mode 100644 index 000000000..ae00bb2cc --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v @@ -0,0 +1,65 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for primitive pb_type: lut4 +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4 ----- +module logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4(prog_clk, + lut4_in, + ccff_head, + lut4_out, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:3] lut4_in; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] lut4_out; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +wire [0:3] lut4_in; +wire [0:0] lut4_out; +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:15] lut4_0_sram; +wire [0:15] lut4_0_sram_inv; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + lut4 lut4_0_ ( + .in(lut4_in[0:3]), + .sram(lut4_0_sram[0:15]), + .sram_inv(lut4_0_sram_inv[0:15]), + .out(lut4_out)); + + lut4_DFF_mem lut4_DFF_mem ( + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(ccff_tail), + .mem_out(lut4_0_sram[0:15]), + .mem_outb(lut4_0_sram_inv[0:15])); + +endmodule +// ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4 ----- + +//----- Default net type ----- +`default_nettype wire + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v new file mode 100644 index 000000000..c1298dab4 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v @@ -0,0 +1,73 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for pb_type: io +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +// ----- BEGIN Physical programmable logic block Verilog module: io ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for logical_tile_io_mode_io_ ----- +module logical_tile_io_mode_io_(prog_clk, + gfpga_pad_GPIO_PAD, + io_outpad, + ccff_head, + io_inpad, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- GPIO PORTS ----- +inout [0:0] gfpga_pad_GPIO_PAD; +//----- INPUT PORTS ----- +input [0:0] io_outpad; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] io_inpad; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +wire [0:0] io_outpad; +wire [0:0] io_inpad; +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] direct_interc_1_out; +wire [0:0] logical_tile_io_mode_physical__iopad_0_iopad_inpad; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .prog_clk(prog_clk), + .gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD), + .iopad_outpad(direct_interc_1_out), + .ccff_head(ccff_head), + .iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad), + .ccff_tail(ccff_tail)); + + direct_interc direct_interc_0_ ( + .in(logical_tile_io_mode_physical__iopad_0_iopad_inpad), + .out(io_inpad)); + + direct_interc direct_interc_1_ ( + .in(io_outpad), + .out(direct_interc_1_out)); + +endmodule +// ----- END Verilog module for logical_tile_io_mode_io_ ----- + +//----- Default net type ----- +`default_nettype wire + + + +// ----- END Physical programmable logic block Verilog module: io ----- diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v new file mode 100644 index 000000000..3fe49ce2f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v @@ -0,0 +1,68 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for primitive pb_type: iopad +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for logical_tile_io_mode_physical__iopad ----- +module logical_tile_io_mode_physical__iopad(prog_clk, + gfpga_pad_GPIO_PAD, + iopad_outpad, + ccff_head, + iopad_inpad, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- GPIO PORTS ----- +inout [0:0] gfpga_pad_GPIO_PAD; +//----- INPUT PORTS ----- +input [0:0] iopad_outpad; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] iopad_inpad; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +wire [0:0] iopad_outpad; +wire [0:0] iopad_inpad; +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] GPIO_0_DIR; +wire [0:0] GPIO_DFF_mem_undriven_mem_outb; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + GPIO GPIO_0_ ( + .PAD(gfpga_pad_GPIO_PAD), + .A(iopad_outpad), + .DIR(GPIO_0_DIR), + .Y(iopad_inpad)); + + GPIO_DFF_mem GPIO_DFF_mem ( + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(ccff_tail), + .mem_out(GPIO_0_DIR), + .mem_outb(GPIO_DFF_mem_undriven_mem_outb)); + +endmodule +// ----- END Verilog module for logical_tile_io_mode_physical__iopad ----- + +//----- Default net type ----- +`default_nettype wire + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_clb_.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_clb_.sdc new file mode 100644 index 000000000..926bf0463 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_clb_.sdc @@ -0,0 +1,237 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Timing constraints for Grid logical_tile_clb_mode_clb_ in PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[0] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[4] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[5] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[6] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[7] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[8] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/clb_I[9] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 9.500000092e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 7.499999927e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[3] 7.499999927e-11 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_default__fle.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_default__fle.sdc new file mode 100644 index 000000000..985595883 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_default__fle.sdc @@ -0,0 +1,13 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle in PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.sdc new file mode 100644 index 000000000..c960efbee --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.sdc @@ -0,0 +1,15 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4 in PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0] 4.500000025e-11 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0] 2.500000033e-11 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.sdc new file mode 100644 index 000000000..c83672cad --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.sdc @@ -0,0 +1,13 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff in PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.sdc new file mode 100644 index 000000000..fd273c6be --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.sdc @@ -0,0 +1,21 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4 in PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_out[0] 2.609999994e-10 +set_min_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_out[0] 2.609999994e-10 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_in[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_out[0] 2.609999994e-10 +set_min_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_in[1] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_out[0] 2.609999994e-10 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_in[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_out[0] 2.609999994e-10 +set_min_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_in[2] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_out[0] 2.609999994e-10 +set_max_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_in[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_out[0] 2.609999994e-10 +set_min_delay -from fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_in[3] -to fpga_top/grid_clb/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4/lut4_out[0] 2.609999994e-10 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_io_mode_io_.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_io_mode_io_.sdc new file mode 100644 index 000000000..891a7bfef --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/logical_tile_io_mode_io_.sdc @@ -0,0 +1,15 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Timing constraints for Grid logical_tile_io_mode_io_ in PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_top/grid_io_left/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0] -to fpga_top/grid_io_left/logical_tile_io_mode_io__0/io_inpad[0] 4.243000049e-11 +set_max_delay -from fpga_top/grid_io_left/logical_tile_io_mode_io__0/io_outpad[0] -to fpga_top/grid_io_left/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] 1.39400002e-11 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/mux_modules.yaml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/mux_modules.yaml new file mode 100644 index 000000000..5180e81ee --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/mux_modules.yaml @@ -0,0 +1,24 @@ +sb_0__0_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size3 + - mux_tree_tapbuf_size2 +sb_0__1_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size3 + - mux_tree_tapbuf_size2 +sb_1__0_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size3 + - mux_tree_tapbuf_size2 +sb_1__1_: + - mux_tree_tapbuf_size4 + - mux_tree_tapbuf_size3 + - mux_tree_tapbuf_size2 +cbx_1__0_: + - mux_tree_tapbuf_size6 +cbx_1__1_: + - mux_tree_tapbuf_size6 +cby_0__1_: + - mux_tree_tapbuf_size6 +cby_1__1_: + - mux_tree_tapbuf_size6 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/pin_mapping.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/pin_mapping.xml new file mode 100644 index 000000000..89523007a --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/pin_mapping.xml @@ -0,0 +1,9 @@ + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/cbx_1__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/cbx_1__0_.v new file mode 100644 index 000000000..9090e22db --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/cbx_1__0_.v @@ -0,0 +1,367 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Connection Blocks[1][0] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for cbx_1__0_ ----- +module cbx_1__0_(prog_clk, + chanx_left_in, + chanx_right_in, + ccff_head, + chanx_left_out, + chanx_right_out, + top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_, + top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_, + top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:12] chanx_left_in; +//----- INPUT PORTS ----- +input [0:12] chanx_right_in; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:12] chanx_left_out; +//----- OUTPUT PORTS ----- +output [0:12] chanx_right_out; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:2] mux_tree_tapbuf_size6_0_sram; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_10_sram; +wire [0:2] mux_tree_tapbuf_size6_10_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_1_sram; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_2_sram; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_3_sram; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_4_sram; +wire [0:2] mux_tree_tapbuf_size6_4_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_5_sram; +wire [0:2] mux_tree_tapbuf_size6_5_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_6_sram; +wire [0:2] mux_tree_tapbuf_size6_6_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_7_sram; +wire [0:2] mux_tree_tapbuf_size6_7_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_8_sram; +wire [0:2] mux_tree_tapbuf_size6_8_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_9_sram; +wire [0:2] mux_tree_tapbuf_size6_9_sram_inv; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_9_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- Local connection due to Wire 0 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[0] = chanx_left_in[0]; +// ----- Local connection due to Wire 1 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[1] = chanx_left_in[1]; +// ----- Local connection due to Wire 2 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[2] = chanx_left_in[2]; +// ----- Local connection due to Wire 3 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[3] = chanx_left_in[3]; +// ----- Local connection due to Wire 4 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[4] = chanx_left_in[4]; +// ----- Local connection due to Wire 5 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[5] = chanx_left_in[5]; +// ----- Local connection due to Wire 6 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[6] = chanx_left_in[6]; +// ----- Local connection due to Wire 7 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[7] = chanx_left_in[7]; +// ----- Local connection due to Wire 8 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[8] = chanx_left_in[8]; +// ----- Local connection due to Wire 9 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[9] = chanx_left_in[9]; +// ----- Local connection due to Wire 10 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[10] = chanx_left_in[10]; +// ----- Local connection due to Wire 11 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[11] = chanx_left_in[11]; +// ----- Local connection due to Wire 12 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[12] = chanx_left_in[12]; +// ----- Local connection due to Wire 13 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[0] = chanx_right_in[0]; +// ----- Local connection due to Wire 14 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[1] = chanx_right_in[1]; +// ----- Local connection due to Wire 15 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[2] = chanx_right_in[2]; +// ----- Local connection due to Wire 16 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[3] = chanx_right_in[3]; +// ----- Local connection due to Wire 17 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[4] = chanx_right_in[4]; +// ----- Local connection due to Wire 18 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[5] = chanx_right_in[5]; +// ----- Local connection due to Wire 19 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[6] = chanx_right_in[6]; +// ----- Local connection due to Wire 20 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[7] = chanx_right_in[7]; +// ----- Local connection due to Wire 21 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[8] = chanx_right_in[8]; +// ----- Local connection due to Wire 22 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[9] = chanx_right_in[9]; +// ----- Local connection due to Wire 23 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[10] = chanx_right_in[10]; +// ----- Local connection due to Wire 24 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[11] = chanx_right_in[11]; +// ----- Local connection due to Wire 25 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[12] = chanx_right_in[12]; +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size6 mux_bottom_ipin_0 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12]}), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_)); + + mux_tree_tapbuf_size6 mux_bottom_ipin_1 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[7], chanx_right_in[7]}), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_)); + + mux_tree_tapbuf_size6 mux_bottom_ipin_2 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8]}), + .sram(mux_tree_tapbuf_size6_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), + .out(top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_)); + + mux_tree_tapbuf_size6 mux_top_ipin_0 ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9]}), + .sram(mux_tree_tapbuf_size6_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_top_ipin_1 ( + .in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10]}), + .sram(mux_tree_tapbuf_size6_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]), + .out(bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_top_ipin_2 ( + .in({chanx_left_in[4], chanx_right_in[4], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11]}), + .sram(mux_tree_tapbuf_size6_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_5_sram_inv[0:2]), + .out(bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_top_ipin_3 ( + .in({chanx_left_in[5], chanx_right_in[5], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12]}), + .sram(mux_tree_tapbuf_size6_6_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_6_sram_inv[0:2]), + .out(bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_top_ipin_4 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[6], chanx_right_in[6], chanx_left_in[7], chanx_right_in[7]}), + .sram(mux_tree_tapbuf_size6_7_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_7_sram_inv[0:2]), + .out(bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_top_ipin_5 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[7], chanx_right_in[7], chanx_left_in[8], chanx_right_in[8]}), + .sram(mux_tree_tapbuf_size6_8_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_8_sram_inv[0:2]), + .out(bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_top_ipin_6 ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[9], chanx_right_in[9]}), + .sram(mux_tree_tapbuf_size6_9_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_9_sram_inv[0:2]), + .out(bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_top_ipin_7 ( + .in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[10], chanx_right_in[10]}), + .sram(mux_tree_tapbuf_size6_10_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_10_sram_inv[0:2]), + .out(bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_)); + + mux_tree_tapbuf_size6_mem mem_bottom_ipin_0 ( + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_ipin_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_ipin_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_ipin_0 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_ipin_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_ipin_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_5_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_ipin_3 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_6_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_ipin_4 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_7_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_7_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_ipin_5 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_8_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_8_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_ipin_6 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_9_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_9_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_ipin_7 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size6_10_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_10_sram_inv[0:2])); + +endmodule +// ----- END Verilog module for cbx_1__0_ ----- + +//----- Default net type ----- +`default_nettype wire + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/cbx_1__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/cbx_1__1_.v new file mode 100644 index 000000000..3e96c8986 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/cbx_1__1_.v @@ -0,0 +1,367 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Connection Blocks[1][1] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for cbx_1__1_ ----- +module cbx_1__1_(prog_clk, + chanx_left_in, + chanx_right_in, + ccff_head, + chanx_left_out, + chanx_right_out, + top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_, + top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_, + bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:12] chanx_left_in; +//----- INPUT PORTS ----- +input [0:12] chanx_right_in; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:12] chanx_left_out; +//----- OUTPUT PORTS ----- +output [0:12] chanx_right_out; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_; +//----- OUTPUT PORTS ----- +output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:2] mux_tree_tapbuf_size6_0_sram; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_10_sram; +wire [0:2] mux_tree_tapbuf_size6_10_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_1_sram; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_2_sram; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_3_sram; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_4_sram; +wire [0:2] mux_tree_tapbuf_size6_4_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_5_sram; +wire [0:2] mux_tree_tapbuf_size6_5_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_6_sram; +wire [0:2] mux_tree_tapbuf_size6_6_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_7_sram; +wire [0:2] mux_tree_tapbuf_size6_7_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_8_sram; +wire [0:2] mux_tree_tapbuf_size6_8_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_9_sram; +wire [0:2] mux_tree_tapbuf_size6_9_sram_inv; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_9_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- Local connection due to Wire 0 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[0] = chanx_left_in[0]; +// ----- Local connection due to Wire 1 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[1] = chanx_left_in[1]; +// ----- Local connection due to Wire 2 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[2] = chanx_left_in[2]; +// ----- Local connection due to Wire 3 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[3] = chanx_left_in[3]; +// ----- Local connection due to Wire 4 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[4] = chanx_left_in[4]; +// ----- Local connection due to Wire 5 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[5] = chanx_left_in[5]; +// ----- Local connection due to Wire 6 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[6] = chanx_left_in[6]; +// ----- Local connection due to Wire 7 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[7] = chanx_left_in[7]; +// ----- Local connection due to Wire 8 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[8] = chanx_left_in[8]; +// ----- Local connection due to Wire 9 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[9] = chanx_left_in[9]; +// ----- Local connection due to Wire 10 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[10] = chanx_left_in[10]; +// ----- Local connection due to Wire 11 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[11] = chanx_left_in[11]; +// ----- Local connection due to Wire 12 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_right_out[12] = chanx_left_in[12]; +// ----- Local connection due to Wire 13 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[0] = chanx_right_in[0]; +// ----- Local connection due to Wire 14 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[1] = chanx_right_in[1]; +// ----- Local connection due to Wire 15 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[2] = chanx_right_in[2]; +// ----- Local connection due to Wire 16 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[3] = chanx_right_in[3]; +// ----- Local connection due to Wire 17 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[4] = chanx_right_in[4]; +// ----- Local connection due to Wire 18 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[5] = chanx_right_in[5]; +// ----- Local connection due to Wire 19 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[6] = chanx_right_in[6]; +// ----- Local connection due to Wire 20 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[7] = chanx_right_in[7]; +// ----- Local connection due to Wire 21 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[8] = chanx_right_in[8]; +// ----- Local connection due to Wire 22 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[9] = chanx_right_in[9]; +// ----- Local connection due to Wire 23 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[10] = chanx_right_in[10]; +// ----- Local connection due to Wire 24 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[11] = chanx_right_in[11]; +// ----- Local connection due to Wire 25 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chanx_left_out[12] = chanx_right_in[12]; +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size6 mux_bottom_ipin_0 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12]}), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_bottom_ipin_1 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[7], chanx_right_in[7]}), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_bottom_ipin_2 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8]}), + .sram(mux_tree_tapbuf_size6_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), + .out(top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_bottom_ipin_3 ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9]}), + .sram(mux_tree_tapbuf_size6_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]), + .out(top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_bottom_ipin_4 ( + .in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10]}), + .sram(mux_tree_tapbuf_size6_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]), + .out(top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_bottom_ipin_5 ( + .in({chanx_left_in[4], chanx_right_in[4], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11]}), + .sram(mux_tree_tapbuf_size6_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_5_sram_inv[0:2]), + .out(top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_bottom_ipin_6 ( + .in({chanx_left_in[5], chanx_right_in[5], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12]}), + .sram(mux_tree_tapbuf_size6_6_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_6_sram_inv[0:2]), + .out(top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_bottom_ipin_7 ( + .in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[6], chanx_right_in[6], chanx_left_in[7], chanx_right_in[7]}), + .sram(mux_tree_tapbuf_size6_7_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_7_sram_inv[0:2]), + .out(top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_top_ipin_0 ( + .in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[7], chanx_right_in[7], chanx_left_in[8], chanx_right_in[8]}), + .sram(mux_tree_tapbuf_size6_8_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_8_sram_inv[0:2]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_)); + + mux_tree_tapbuf_size6 mux_top_ipin_1 ( + .in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[9], chanx_right_in[9]}), + .sram(mux_tree_tapbuf_size6_9_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_9_sram_inv[0:2]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_)); + + mux_tree_tapbuf_size6 mux_top_ipin_2 ( + .in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[10], chanx_right_in[10]}), + .sram(mux_tree_tapbuf_size6_10_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_10_sram_inv[0:2]), + .out(bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_)); + + mux_tree_tapbuf_size6_mem mem_bottom_ipin_0 ( + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_ipin_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_ipin_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_ipin_3 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_ipin_4 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_ipin_5 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_5_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_ipin_6 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_6_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_bottom_ipin_7 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_7_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_7_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_ipin_0 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_8_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_8_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_ipin_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_9_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_9_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_top_ipin_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size6_10_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_10_sram_inv[0:2])); + +endmodule +// ----- END Verilog module for cbx_1__1_ ----- + +//----- Default net type ----- +`default_nettype wire + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/cby_0__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/cby_0__1_.v new file mode 100644 index 000000000..67f8756a9 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/cby_0__1_.v @@ -0,0 +1,348 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Connection Blocks[0][1] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for cby_0__1_ ----- +module cby_0__1_(prog_clk, + chany_bottom_in, + chany_top_in, + ccff_head, + chany_bottom_out, + chany_top_out, + right_grid_left_width_0_height_0_subtile_0__pin_I_3_, + right_grid_left_width_0_height_0_subtile_0__pin_I_7_, + left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:12] chany_bottom_in; +//----- INPUT PORTS ----- +input [0:12] chany_top_in; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:12] chany_bottom_out; +//----- OUTPUT PORTS ----- +output [0:12] chany_top_out; +//----- OUTPUT PORTS ----- +output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_I_3_; +//----- OUTPUT PORTS ----- +output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_I_7_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:2] mux_tree_tapbuf_size6_0_sram; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_1_sram; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_2_sram; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_3_sram; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_4_sram; +wire [0:2] mux_tree_tapbuf_size6_4_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_5_sram; +wire [0:2] mux_tree_tapbuf_size6_5_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_6_sram; +wire [0:2] mux_tree_tapbuf_size6_6_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_7_sram; +wire [0:2] mux_tree_tapbuf_size6_7_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_8_sram; +wire [0:2] mux_tree_tapbuf_size6_8_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_9_sram; +wire [0:2] mux_tree_tapbuf_size6_9_sram_inv; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- Local connection due to Wire 0 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[0] = chany_bottom_in[0]; +// ----- Local connection due to Wire 1 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[1] = chany_bottom_in[1]; +// ----- Local connection due to Wire 2 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[2] = chany_bottom_in[2]; +// ----- Local connection due to Wire 3 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[3] = chany_bottom_in[3]; +// ----- Local connection due to Wire 4 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[4] = chany_bottom_in[4]; +// ----- Local connection due to Wire 5 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[5] = chany_bottom_in[5]; +// ----- Local connection due to Wire 6 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[6] = chany_bottom_in[6]; +// ----- Local connection due to Wire 7 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[7] = chany_bottom_in[7]; +// ----- Local connection due to Wire 8 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[8] = chany_bottom_in[8]; +// ----- Local connection due to Wire 9 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[9] = chany_bottom_in[9]; +// ----- Local connection due to Wire 10 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[10] = chany_bottom_in[10]; +// ----- Local connection due to Wire 11 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[11] = chany_bottom_in[11]; +// ----- Local connection due to Wire 12 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[12] = chany_bottom_in[12]; +// ----- Local connection due to Wire 13 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[0] = chany_top_in[0]; +// ----- Local connection due to Wire 14 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[1] = chany_top_in[1]; +// ----- Local connection due to Wire 15 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[2] = chany_top_in[2]; +// ----- Local connection due to Wire 16 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[3] = chany_top_in[3]; +// ----- Local connection due to Wire 17 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[4] = chany_top_in[4]; +// ----- Local connection due to Wire 18 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[5] = chany_top_in[5]; +// ----- Local connection due to Wire 19 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[6] = chany_top_in[6]; +// ----- Local connection due to Wire 20 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[7] = chany_top_in[7]; +// ----- Local connection due to Wire 21 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[8] = chany_top_in[8]; +// ----- Local connection due to Wire 22 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[9] = chany_top_in[9]; +// ----- Local connection due to Wire 23 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[10] = chany_top_in[10]; +// ----- Local connection due to Wire 24 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[11] = chany_top_in[11]; +// ----- Local connection due to Wire 25 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[12] = chany_top_in[12]; +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size6 mux_left_ipin_0 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12]}), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(right_grid_left_width_0_height_0_subtile_0__pin_I_3_)); + + mux_tree_tapbuf_size6 mux_left_ipin_1 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[7], chany_top_in[7]}), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(right_grid_left_width_0_height_0_subtile_0__pin_I_7_)); + + mux_tree_tapbuf_size6 mux_right_ipin_0 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8]}), + .sram(mux_tree_tapbuf_size6_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_right_ipin_1 ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9]}), + .sram(mux_tree_tapbuf_size6_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]), + .out(left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_right_ipin_2 ( + .in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10]}), + .sram(mux_tree_tapbuf_size6_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]), + .out(left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_right_ipin_3 ( + .in({chany_bottom_in[4], chany_top_in[4], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11]}), + .sram(mux_tree_tapbuf_size6_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_5_sram_inv[0:2]), + .out(left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_right_ipin_4 ( + .in({chany_bottom_in[5], chany_top_in[5], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12]}), + .sram(mux_tree_tapbuf_size6_6_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_6_sram_inv[0:2]), + .out(left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_right_ipin_5 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[7], chany_top_in[7]}), + .sram(mux_tree_tapbuf_size6_7_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_7_sram_inv[0:2]), + .out(left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_right_ipin_6 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[8], chany_top_in[8]}), + .sram(mux_tree_tapbuf_size6_8_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_8_sram_inv[0:2]), + .out(left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_right_ipin_7 ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[9], chany_top_in[9]}), + .sram(mux_tree_tapbuf_size6_9_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_9_sram_inv[0:2]), + .out(left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_)); + + mux_tree_tapbuf_size6_mem mem_left_ipin_0 ( + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_ipin_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_ipin_0 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_ipin_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_ipin_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_ipin_3 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_5_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_ipin_4 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_6_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_ipin_5 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_7_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_7_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_ipin_6 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_8_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_8_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_ipin_7 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size6_9_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_9_sram_inv[0:2])); + +endmodule +// ----- END Verilog module for cby_0__1_ ----- + +//----- Default net type ----- +`default_nettype wire + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/cby_1__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/cby_1__1_.v new file mode 100644 index 000000000..5a9c566f8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/cby_1__1_.v @@ -0,0 +1,367 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Connection Blocks[1][1] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for cby_1__1_ ----- +module cby_1__1_(prog_clk, + chany_bottom_in, + chany_top_in, + ccff_head, + chany_bottom_out, + chany_top_out, + right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_, + right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_, + left_grid_right_width_0_height_0_subtile_0__pin_I_1_, + left_grid_right_width_0_height_0_subtile_0__pin_I_5_, + left_grid_right_width_0_height_0_subtile_0__pin_I_9_, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:12] chany_bottom_in; +//----- INPUT PORTS ----- +input [0:12] chany_top_in; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:12] chany_bottom_out; +//----- OUTPUT PORTS ----- +output [0:12] chany_top_out; +//----- OUTPUT PORTS ----- +output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_1_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_5_; +//----- OUTPUT PORTS ----- +output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_9_; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:2] mux_tree_tapbuf_size6_0_sram; +wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_10_sram; +wire [0:2] mux_tree_tapbuf_size6_10_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_1_sram; +wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_2_sram; +wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_3_sram; +wire [0:2] mux_tree_tapbuf_size6_3_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_4_sram; +wire [0:2] mux_tree_tapbuf_size6_4_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_5_sram; +wire [0:2] mux_tree_tapbuf_size6_5_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_6_sram; +wire [0:2] mux_tree_tapbuf_size6_6_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_7_sram; +wire [0:2] mux_tree_tapbuf_size6_7_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_8_sram; +wire [0:2] mux_tree_tapbuf_size6_8_sram_inv; +wire [0:2] mux_tree_tapbuf_size6_9_sram; +wire [0:2] mux_tree_tapbuf_size6_9_sram_inv; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size6_mem_9_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- Local connection due to Wire 0 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[0] = chany_bottom_in[0]; +// ----- Local connection due to Wire 1 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[1] = chany_bottom_in[1]; +// ----- Local connection due to Wire 2 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[2] = chany_bottom_in[2]; +// ----- Local connection due to Wire 3 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[3] = chany_bottom_in[3]; +// ----- Local connection due to Wire 4 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[4] = chany_bottom_in[4]; +// ----- Local connection due to Wire 5 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[5] = chany_bottom_in[5]; +// ----- Local connection due to Wire 6 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[6] = chany_bottom_in[6]; +// ----- Local connection due to Wire 7 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[7] = chany_bottom_in[7]; +// ----- Local connection due to Wire 8 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[8] = chany_bottom_in[8]; +// ----- Local connection due to Wire 9 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[9] = chany_bottom_in[9]; +// ----- Local connection due to Wire 10 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[10] = chany_bottom_in[10]; +// ----- Local connection due to Wire 11 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[11] = chany_bottom_in[11]; +// ----- Local connection due to Wire 12 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_top_out[12] = chany_bottom_in[12]; +// ----- Local connection due to Wire 13 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[0] = chany_top_in[0]; +// ----- Local connection due to Wire 14 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[1] = chany_top_in[1]; +// ----- Local connection due to Wire 15 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[2] = chany_top_in[2]; +// ----- Local connection due to Wire 16 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[3] = chany_top_in[3]; +// ----- Local connection due to Wire 17 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[4] = chany_top_in[4]; +// ----- Local connection due to Wire 18 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[5] = chany_top_in[5]; +// ----- Local connection due to Wire 19 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[6] = chany_top_in[6]; +// ----- Local connection due to Wire 20 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[7] = chany_top_in[7]; +// ----- Local connection due to Wire 21 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[8] = chany_top_in[8]; +// ----- Local connection due to Wire 22 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[9] = chany_top_in[9]; +// ----- Local connection due to Wire 23 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[10] = chany_top_in[10]; +// ----- Local connection due to Wire 24 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[11] = chany_top_in[11]; +// ----- Local connection due to Wire 25 ----- +// ----- Net source id 0 ----- +// ----- Net sink id 0 ----- + assign chany_bottom_out[12] = chany_top_in[12]; +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size6 mux_left_ipin_0 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12]}), + .sram(mux_tree_tapbuf_size6_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .out(right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_left_ipin_1 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[7], chany_top_in[7]}), + .sram(mux_tree_tapbuf_size6_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .out(right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_left_ipin_2 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8]}), + .sram(mux_tree_tapbuf_size6_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), + .out(right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_left_ipin_3 ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9]}), + .sram(mux_tree_tapbuf_size6_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]), + .out(right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_left_ipin_4 ( + .in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10]}), + .sram(mux_tree_tapbuf_size6_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]), + .out(right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_left_ipin_5 ( + .in({chany_bottom_in[4], chany_top_in[4], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11]}), + .sram(mux_tree_tapbuf_size6_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_5_sram_inv[0:2]), + .out(right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_left_ipin_6 ( + .in({chany_bottom_in[5], chany_top_in[5], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12]}), + .sram(mux_tree_tapbuf_size6_6_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_6_sram_inv[0:2]), + .out(right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_left_ipin_7 ( + .in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[7], chany_top_in[7]}), + .sram(mux_tree_tapbuf_size6_7_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_7_sram_inv[0:2]), + .out(right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_)); + + mux_tree_tapbuf_size6 mux_right_ipin_0 ( + .in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[8], chany_top_in[8]}), + .sram(mux_tree_tapbuf_size6_8_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_8_sram_inv[0:2]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I_1_)); + + mux_tree_tapbuf_size6 mux_right_ipin_1 ( + .in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[9], chany_top_in[9]}), + .sram(mux_tree_tapbuf_size6_9_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_9_sram_inv[0:2]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I_5_)); + + mux_tree_tapbuf_size6 mux_right_ipin_2 ( + .in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[10], chany_top_in[10]}), + .sram(mux_tree_tapbuf_size6_10_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size6_10_sram_inv[0:2]), + .out(left_grid_right_width_0_height_0_subtile_0__pin_I_9_)); + + mux_tree_tapbuf_size6_mem mem_left_ipin_0 ( + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_ipin_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_ipin_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_ipin_3 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_ipin_4 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_ipin_5 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_5_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_ipin_6 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_6_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_6_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_left_ipin_7 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_7_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_7_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_ipin_0 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_8_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_8_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_ipin_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size6_9_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_9_sram_inv[0:2])); + + mux_tree_tapbuf_size6_mem mem_right_ipin_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size6_10_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size6_10_sram_inv[0:2])); + +endmodule +// ----- END Verilog module for cby_1__1_ ----- + +//----- Default net type ----- +`default_nettype wire + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/sb_0__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/sb_0__0_.v new file mode 100644 index 000000000..6e5f094d9 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/sb_0__0_.v @@ -0,0 +1,523 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Switch Blocks[0][0] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for sb_0__0_ ----- +module sb_0__0_(prog_clk, + chany_top_in, + top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_, + top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_, + chanx_right_in, + right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_, + ccff_head, + chany_top_out, + chanx_right_out, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:12] chany_top_in; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_; +//----- INPUT PORTS ----- +input [0:12] chanx_right_in; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:12] chany_top_out; +//----- OUTPUT PORTS ----- +output [0:12] chanx_right_out; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:1] mux_tree_tapbuf_size2_0_sram; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_1_sram; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_2_sram; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_3_sram; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_4_sram; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_5_sram; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; +wire [0:1] mux_tree_tapbuf_size3_0_sram; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_10_sram; +wire [0:1] mux_tree_tapbuf_size3_10_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_11_sram; +wire [0:1] mux_tree_tapbuf_size3_11_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_12_sram; +wire [0:1] mux_tree_tapbuf_size3_12_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_13_sram; +wire [0:1] mux_tree_tapbuf_size3_13_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_1_sram; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_2_sram; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_3_sram; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_4_sram; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_5_sram; +wire [0:1] mux_tree_tapbuf_size3_5_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_6_sram; +wire [0:1] mux_tree_tapbuf_size3_6_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_7_sram; +wire [0:1] mux_tree_tapbuf_size3_7_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_8_sram; +wire [0:1] mux_tree_tapbuf_size3_8_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_9_sram; +wire [0:1] mux_tree_tapbuf_size3_9_sram_inv; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_11_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_12_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_9_ccff_tail; +wire [0:2] mux_tree_tapbuf_size4_0_sram; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_1_sram; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_2_sram; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_3_sram; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_4_sram; +wire [0:2] mux_tree_tapbuf_size4_4_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_5_sram; +wire [0:2] mux_tree_tapbuf_size4_5_sram_inv; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size4 mux_top_track_0 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_, chanx_right_in[1]}), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .out(chany_top_out[0])); + + mux_tree_tapbuf_size4 mux_top_track_12 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_, chanx_right_in[7]}), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .out(chany_top_out[6])); + + mux_tree_tapbuf_size4 mux_right_track_0 ( + .in({chany_top_in[12], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .out(chanx_right_out[0])); + + mux_tree_tapbuf_size4 mux_right_track_2 ( + .in({chany_top_in[0], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), + .out(chanx_right_out[1])); + + mux_tree_tapbuf_size4 mux_right_track_12 ( + .in({chany_top_in[5], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_4_sram_inv[0:2]), + .out(chanx_right_out[6])); + + mux_tree_tapbuf_size4 mux_right_track_14 ( + .in({chany_top_in[6], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_5_sram_inv[0:2]), + .out(chanx_right_out[7])); + + mux_tree_tapbuf_size4_mem mem_top_track_0 ( + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_top_track_12 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_right_track_0 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_right_track_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_right_track_12 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_4_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_right_track_14 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_5_sram_inv[0:2])); + + mux_tree_tapbuf_size3 mux_top_track_2 ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[2]}), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chany_top_out[1])); + + mux_tree_tapbuf_size3 mux_top_track_4 ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[3]}), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chany_top_out[2])); + + mux_tree_tapbuf_size3 mux_top_track_6 ( + .in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, chanx_right_in[4]}), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .out(chany_top_out[3])); + + mux_tree_tapbuf_size3 mux_top_track_8 ( + .in({top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_, chanx_right_in[5]}), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), + .out(chany_top_out[4])); + + mux_tree_tapbuf_size3 mux_top_track_10 ( + .in({top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_, chanx_right_in[6]}), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), + .out(chany_top_out[5])); + + mux_tree_tapbuf_size3 mux_top_track_14 ( + .in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_, chanx_right_in[8]}), + .sram(mux_tree_tapbuf_size3_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]), + .out(chany_top_out[7])); + + mux_tree_tapbuf_size3 mux_top_track_16 ( + .in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_, chanx_right_in[9]}), + .sram(mux_tree_tapbuf_size3_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]), + .out(chany_top_out[8])); + + mux_tree_tapbuf_size3 mux_top_track_24 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_, chanx_right_in[0]}), + .sram(mux_tree_tapbuf_size3_7_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_7_sram_inv[0:1]), + .out(chany_top_out[12])); + + mux_tree_tapbuf_size3 mux_right_track_4 ( + .in({chany_top_in[1], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_8_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_8_sram_inv[0:1]), + .out(chanx_right_out[2])); + + mux_tree_tapbuf_size3 mux_right_track_6 ( + .in({chany_top_in[2], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_9_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_9_sram_inv[0:1]), + .out(chanx_right_out[3])); + + mux_tree_tapbuf_size3 mux_right_track_8 ( + .in({chany_top_in[3], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_10_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_10_sram_inv[0:1]), + .out(chanx_right_out[4])); + + mux_tree_tapbuf_size3 mux_right_track_10 ( + .in({chany_top_in[4], right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_11_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_11_sram_inv[0:1]), + .out(chanx_right_out[5])); + + mux_tree_tapbuf_size3 mux_right_track_16 ( + .in({chany_top_in[7], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_12_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_12_sram_inv[0:1]), + .out(chanx_right_out[8])); + + mux_tree_tapbuf_size3 mux_right_track_24 ( + .in({chany_top_in[11], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_13_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_13_sram_inv[0:1]), + .out(chanx_right_out[12])); + + mux_tree_tapbuf_size3_mem mem_top_track_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_4 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_6 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_8 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_10 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_14 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_16 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_24 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_7_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_4 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_8_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_8_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_6 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_9_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_9_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_8 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_10_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_10_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_10 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_11_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_11_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_16 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_12_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_12_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_24 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size3_13_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_13_sram_inv[0:1])); + + mux_tree_tapbuf_size2 mux_top_track_18 ( + .in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[10]}), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chany_top_out[9])); + + mux_tree_tapbuf_size2 mux_top_track_20 ( + .in({top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, chanx_right_in[11]}), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chany_top_out[10])); + + mux_tree_tapbuf_size2 mux_top_track_22 ( + .in({top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_, chanx_right_in[12]}), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chany_top_out[11])); + + mux_tree_tapbuf_size2 mux_right_track_18 ( + .in({chany_top_in[8], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chanx_right_out[9])); + + mux_tree_tapbuf_size2 mux_right_track_20 ( + .in({chany_top_in[9], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chanx_right_out[10])); + + mux_tree_tapbuf_size2 mux_right_track_22 ( + .in({chany_top_in[10], right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .out(chanx_right_out[11])); + + mux_tree_tapbuf_size2_mem mem_top_track_18 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_20 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_22 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_18 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_20 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_22 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])); + +endmodule +// ----- END Verilog module for sb_0__0_ ----- + +//----- Default net type ----- +`default_nettype wire + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/sb_0__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/sb_0__1_.v new file mode 100644 index 000000000..221ac87b1 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/sb_0__1_.v @@ -0,0 +1,523 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Switch Blocks[0][1] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for sb_0__1_ ----- +module sb_0__1_(prog_clk, + chanx_right_in, + right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, + right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, + right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + chany_bottom_in, + bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_, + ccff_head, + chanx_right_out, + chany_bottom_out, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:12] chanx_right_in; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; +//----- INPUT PORTS ----- +input [0:12] chany_bottom_in; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:12] chanx_right_out; +//----- OUTPUT PORTS ----- +output [0:12] chany_bottom_out; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:1] mux_tree_tapbuf_size2_0_sram; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_1_sram; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_2_sram; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_3_sram; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_4_sram; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_5_sram; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_6_sram; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; +wire [0:1] mux_tree_tapbuf_size3_0_sram; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_10_sram; +wire [0:1] mux_tree_tapbuf_size3_10_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_11_sram; +wire [0:1] mux_tree_tapbuf_size3_11_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_12_sram; +wire [0:1] mux_tree_tapbuf_size3_12_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_13_sram; +wire [0:1] mux_tree_tapbuf_size3_13_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_1_sram; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_2_sram; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_3_sram; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_4_sram; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_5_sram; +wire [0:1] mux_tree_tapbuf_size3_5_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_6_sram; +wire [0:1] mux_tree_tapbuf_size3_6_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_7_sram; +wire [0:1] mux_tree_tapbuf_size3_7_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_8_sram; +wire [0:1] mux_tree_tapbuf_size3_8_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_9_sram; +wire [0:1] mux_tree_tapbuf_size3_9_sram_inv; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_11_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_12_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_13_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_9_ccff_tail; +wire [0:2] mux_tree_tapbuf_size4_0_sram; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_1_sram; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_2_sram; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_3_sram; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_4_sram; +wire [0:2] mux_tree_tapbuf_size4_4_sram_inv; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size4 mux_right_track_0 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, chany_bottom_in[11]}), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .out(chanx_right_out[0])); + + mux_tree_tapbuf_size4 mux_right_track_12 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, chany_bottom_in[5]}), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .out(chanx_right_out[6])); + + mux_tree_tapbuf_size4 mux_bottom_track_1 ( + .in({chanx_right_in[11], bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .out(chany_bottom_out[0])); + + mux_tree_tapbuf_size4 mux_bottom_track_3 ( + .in({chanx_right_in[10], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), + .out(chany_bottom_out[1])); + + mux_tree_tapbuf_size4 mux_bottom_track_15 ( + .in({chanx_right_in[4], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_4_sram_inv[0:2]), + .out(chany_bottom_out[7])); + + mux_tree_tapbuf_size4_mem mem_right_track_0 ( + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_right_track_12 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_bottom_track_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_bottom_track_3 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_bottom_track_15 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_4_sram_inv[0:2])); + + mux_tree_tapbuf_size3 mux_right_track_2 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, chany_bottom_in[10]}), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chanx_right_out[1])); + + mux_tree_tapbuf_size3 mux_right_track_4 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[9]}), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chanx_right_out[2])); + + mux_tree_tapbuf_size3 mux_right_track_6 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, chany_bottom_in[8]}), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .out(chanx_right_out[3])); + + mux_tree_tapbuf_size3 mux_right_track_8 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, chany_bottom_in[7]}), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), + .out(chanx_right_out[4])); + + mux_tree_tapbuf_size3 mux_right_track_10 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, chany_bottom_in[6]}), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), + .out(chanx_right_out[5])); + + mux_tree_tapbuf_size3 mux_right_track_14 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, chany_bottom_in[4]}), + .sram(mux_tree_tapbuf_size3_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]), + .out(chanx_right_out[7])); + + mux_tree_tapbuf_size3 mux_right_track_16 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[3]}), + .sram(mux_tree_tapbuf_size3_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]), + .out(chanx_right_out[8])); + + mux_tree_tapbuf_size3 mux_right_track_24 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, chany_bottom_in[12]}), + .sram(mux_tree_tapbuf_size3_7_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_7_sram_inv[0:1]), + .out(chanx_right_out[12])); + + mux_tree_tapbuf_size3 mux_bottom_track_5 ( + .in({chanx_right_in[9], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_8_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_8_sram_inv[0:1]), + .out(chany_bottom_out[2])); + + mux_tree_tapbuf_size3 mux_bottom_track_7 ( + .in({chanx_right_in[8], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_9_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_9_sram_inv[0:1]), + .out(chany_bottom_out[3])); + + mux_tree_tapbuf_size3 mux_bottom_track_9 ( + .in({chanx_right_in[7], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_10_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_10_sram_inv[0:1]), + .out(chany_bottom_out[4])); + + mux_tree_tapbuf_size3 mux_bottom_track_11 ( + .in({chanx_right_in[6], bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_11_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_11_sram_inv[0:1]), + .out(chany_bottom_out[5])); + + mux_tree_tapbuf_size3 mux_bottom_track_13 ( + .in({chanx_right_in[5], bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_12_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_12_sram_inv[0:1]), + .out(chany_bottom_out[6])); + + mux_tree_tapbuf_size3 mux_bottom_track_17 ( + .in({chanx_right_in[3], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_13_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_13_sram_inv[0:1]), + .out(chany_bottom_out[8])); + + mux_tree_tapbuf_size3_mem mem_right_track_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_4 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_6 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_8 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_10 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_14 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_16 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_right_track_24 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_7_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_5 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_8_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_8_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_7 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_9_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_9_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_9 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_10_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_10_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_11 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_11_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_11_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_13 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_12_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_12_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_17 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_13_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_13_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_13_sram_inv[0:1])); + + mux_tree_tapbuf_size2 mux_right_track_18 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[2]}), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chanx_right_out[9])); + + mux_tree_tapbuf_size2 mux_right_track_20 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, chany_bottom_in[1]}), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chanx_right_out[10])); + + mux_tree_tapbuf_size2 mux_right_track_22 ( + .in({right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, chany_bottom_in[0]}), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chanx_right_out[11])); + + mux_tree_tapbuf_size2 mux_bottom_track_19 ( + .in({chanx_right_in[2], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chany_bottom_out[9])); + + mux_tree_tapbuf_size2 mux_bottom_track_21 ( + .in({chanx_right_in[1], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chany_bottom_out[10])); + + mux_tree_tapbuf_size2 mux_bottom_track_23 ( + .in({chanx_right_in[0], bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .out(chany_bottom_out[11])); + + mux_tree_tapbuf_size2 mux_bottom_track_25 ( + .in({chanx_right_in[12], bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), + .out(chany_bottom_out[12])); + + mux_tree_tapbuf_size2_mem mem_right_track_18 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_20 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_right_track_22 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_19 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_13_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_21 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_23 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_25 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])); + +endmodule +// ----- END Verilog module for sb_0__1_ ----- + +//----- Default net type ----- +`default_nettype wire + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/sb_1__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/sb_1__0_.v new file mode 100644 index 000000000..b9385b247 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/sb_1__0_.v @@ -0,0 +1,523 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Switch Blocks[1][0] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for sb_1__0_ ----- +module sb_1__0_(prog_clk, + chany_top_in, + top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, + top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, + top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, + chanx_left_in, + left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_, + ccff_head, + chany_top_out, + chanx_left_out, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:12] chany_top_in; +//----- INPUT PORTS ----- +input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:12] chanx_left_in; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:12] chany_top_out; +//----- OUTPUT PORTS ----- +output [0:12] chanx_left_out; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:1] mux_tree_tapbuf_size2_0_sram; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_1_sram; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_2_sram; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_3_sram; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_4_sram; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_5_sram; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_6_sram; +wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; +wire [0:1] mux_tree_tapbuf_size3_0_sram; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_10_sram; +wire [0:1] mux_tree_tapbuf_size3_10_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_11_sram; +wire [0:1] mux_tree_tapbuf_size3_11_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_1_sram; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_2_sram; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_3_sram; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_4_sram; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_5_sram; +wire [0:1] mux_tree_tapbuf_size3_5_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_6_sram; +wire [0:1] mux_tree_tapbuf_size3_6_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_7_sram; +wire [0:1] mux_tree_tapbuf_size3_7_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_8_sram; +wire [0:1] mux_tree_tapbuf_size3_8_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_9_sram; +wire [0:1] mux_tree_tapbuf_size3_9_sram_inv; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_9_ccff_tail; +wire [0:2] mux_tree_tapbuf_size4_0_sram; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_1_sram; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_2_sram; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_3_sram; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_4_sram; +wire [0:2] mux_tree_tapbuf_size4_4_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_5_sram; +wire [0:2] mux_tree_tapbuf_size4_5_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_6_sram; +wire [0:2] mux_tree_tapbuf_size4_6_sram_inv; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size4 mux_top_track_0 ( + .in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[0]}), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .out(chany_top_out[0])); + + mux_tree_tapbuf_size4 mux_top_track_2 ( + .in({top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[12]}), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .out(chany_top_out[1])); + + mux_tree_tapbuf_size4 mux_top_track_14 ( + .in({top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[6]}), + .sram(mux_tree_tapbuf_size4_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .out(chany_top_out[7])); + + mux_tree_tapbuf_size4 mux_left_track_1 ( + .in({chany_top_in[0], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), + .out(chanx_left_out[0])); + + mux_tree_tapbuf_size4 mux_left_track_3 ( + .in({chany_top_in[12], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_4_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_4_sram_inv[0:2]), + .out(chanx_left_out[1])); + + mux_tree_tapbuf_size4 mux_left_track_13 ( + .in({chany_top_in[7], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_5_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_5_sram_inv[0:2]), + .out(chanx_left_out[6])); + + mux_tree_tapbuf_size4 mux_left_track_15 ( + .in({chany_top_in[6], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_6_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_6_sram_inv[0:2]), + .out(chanx_left_out[7])); + + mux_tree_tapbuf_size4_mem mem_top_track_0 ( + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_top_track_2 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_top_track_14 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_left_track_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_left_track_3 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_4_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_4_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_left_track_13 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_5_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_5_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_left_track_15 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_6_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_6_sram_inv[0:2])); + + mux_tree_tapbuf_size3 mux_top_track_4 ( + .in({top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[11]}), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chany_top_out[2])); + + mux_tree_tapbuf_size3 mux_top_track_6 ( + .in({top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chany_top_out[3])); + + mux_tree_tapbuf_size3 mux_top_track_8 ( + .in({top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[9]}), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .out(chany_top_out[4])); + + mux_tree_tapbuf_size3 mux_top_track_10 ( + .in({top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[8]}), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), + .out(chany_top_out[5])); + + mux_tree_tapbuf_size3 mux_top_track_12 ( + .in({top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[7]}), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), + .out(chany_top_out[6])); + + mux_tree_tapbuf_size3 mux_top_track_16 ( + .in({top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[5]}), + .sram(mux_tree_tapbuf_size3_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]), + .out(chany_top_out[8])); + + mux_tree_tapbuf_size3 mux_left_track_5 ( + .in({chany_top_in[11], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]), + .out(chanx_left_out[2])); + + mux_tree_tapbuf_size3 mux_left_track_7 ( + .in({chany_top_in[10], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_7_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_7_sram_inv[0:1]), + .out(chanx_left_out[3])); + + mux_tree_tapbuf_size3 mux_left_track_9 ( + .in({chany_top_in[9], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_8_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_8_sram_inv[0:1]), + .out(chanx_left_out[4])); + + mux_tree_tapbuf_size3 mux_left_track_11 ( + .in({chany_top_in[8], left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_9_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_9_sram_inv[0:1]), + .out(chanx_left_out[5])); + + mux_tree_tapbuf_size3 mux_left_track_17 ( + .in({chany_top_in[5], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_10_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_10_sram_inv[0:1]), + .out(chanx_left_out[8])); + + mux_tree_tapbuf_size3 mux_left_track_25 ( + .in({chany_top_in[1], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_11_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_11_sram_inv[0:1]), + .out(chanx_left_out[12])); + + mux_tree_tapbuf_size3_mem mem_top_track_4 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_6 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_8 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_10 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_12 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_top_track_16 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_5 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_7 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_7_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_9 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_8_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_8_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_11 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_9_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_9_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_17 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_10_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_10_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_25 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size3_11_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_11_sram_inv[0:1])); + + mux_tree_tapbuf_size2 mux_top_track_18 ( + .in({top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[4]}), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chany_top_out[9])); + + mux_tree_tapbuf_size2 mux_top_track_20 ( + .in({top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[3]}), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chany_top_out[10])); + + mux_tree_tapbuf_size2 mux_top_track_22 ( + .in({top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[2]}), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chany_top_out[11])); + + mux_tree_tapbuf_size2 mux_top_track_24 ( + .in({top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[1]}), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chany_top_out[12])); + + mux_tree_tapbuf_size2 mux_left_track_19 ( + .in({chany_top_in[4], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chanx_left_out[9])); + + mux_tree_tapbuf_size2 mux_left_track_21 ( + .in({chany_top_in[3], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .out(chanx_left_out[10])); + + mux_tree_tapbuf_size2 mux_left_track_23 ( + .in({chany_top_in[2], left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), + .out(chanx_left_out[11])); + + mux_tree_tapbuf_size2_mem mem_top_track_18 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_20 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_22 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_top_track_24 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_19 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_21 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_23 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1])); + +endmodule +// ----- END Verilog module for sb_1__0_ ----- + +//----- Default net type ----- +`default_nettype wire + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/sb_1__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/sb_1__1_.v new file mode 100644 index 000000000..f8bcc9d61 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/routing/sb_1__1_.v @@ -0,0 +1,523 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Verilog modules for Unique Switch Blocks[1][1] +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for sb_1__1_ ----- +module sb_1__1_(prog_clk, + chany_bottom_in, + bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, + bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, + bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, + chanx_left_in, + left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, + left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, + left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, + ccff_head, + chany_bottom_out, + chanx_left_out, + ccff_tail); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:12] chany_bottom_in; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_; +//----- INPUT PORTS ----- +input [0:12] chanx_left_in; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_; +//----- INPUT PORTS ----- +input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:12] chany_bottom_out; +//----- OUTPUT PORTS ----- +output [0:12] chanx_left_out; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:1] mux_tree_tapbuf_size2_0_sram; +wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_1_sram; +wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_2_sram; +wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_3_sram; +wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_4_sram; +wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; +wire [0:1] mux_tree_tapbuf_size2_5_sram; +wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; +wire [0:1] mux_tree_tapbuf_size3_0_sram; +wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_10_sram; +wire [0:1] mux_tree_tapbuf_size3_10_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_11_sram; +wire [0:1] mux_tree_tapbuf_size3_11_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_12_sram; +wire [0:1] mux_tree_tapbuf_size3_12_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_13_sram; +wire [0:1] mux_tree_tapbuf_size3_13_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_14_sram; +wire [0:1] mux_tree_tapbuf_size3_14_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_15_sram; +wire [0:1] mux_tree_tapbuf_size3_15_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_1_sram; +wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_2_sram; +wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_3_sram; +wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_4_sram; +wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_5_sram; +wire [0:1] mux_tree_tapbuf_size3_5_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_6_sram; +wire [0:1] mux_tree_tapbuf_size3_6_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_7_sram; +wire [0:1] mux_tree_tapbuf_size3_7_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_8_sram; +wire [0:1] mux_tree_tapbuf_size3_8_sram_inv; +wire [0:1] mux_tree_tapbuf_size3_9_sram; +wire [0:1] mux_tree_tapbuf_size3_9_sram_inv; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_10_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_11_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_12_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_13_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_14_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail; +wire [0:0] mux_tree_tapbuf_size3_mem_9_ccff_tail; +wire [0:2] mux_tree_tapbuf_size4_0_sram; +wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_1_sram; +wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_2_sram; +wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; +wire [0:2] mux_tree_tapbuf_size4_3_sram; +wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + mux_tree_tapbuf_size4 mux_bottom_track_1 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[1]}), + .sram(mux_tree_tapbuf_size4_0_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .out(chany_bottom_out[0])); + + mux_tree_tapbuf_size4 mux_bottom_track_13 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[7]}), + .sram(mux_tree_tapbuf_size4_1_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .out(chany_bottom_out[6])); + + mux_tree_tapbuf_size4 mux_left_track_1 ( + .in({chany_bottom_in[12], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_2_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .out(chanx_left_out[0])); + + mux_tree_tapbuf_size4 mux_left_track_13 ( + .in({chany_bottom_in[5], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size4_3_sram[0:2]), + .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), + .out(chanx_left_out[6])); + + mux_tree_tapbuf_size4_mem mem_bottom_track_1 ( + .prog_clk(prog_clk), + .ccff_head(ccff_head), + .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_bottom_track_13 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_left_track_1 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2])); + + mux_tree_tapbuf_size4_mem mem_left_track_13 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), + .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2])); + + mux_tree_tapbuf_size3 mux_bottom_track_3 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[2]}), + .sram(mux_tree_tapbuf_size3_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .out(chany_bottom_out[1])); + + mux_tree_tapbuf_size3 mux_bottom_track_5 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[3]}), + .sram(mux_tree_tapbuf_size3_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .out(chany_bottom_out[2])); + + mux_tree_tapbuf_size3 mux_bottom_track_7 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[4]}), + .sram(mux_tree_tapbuf_size3_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .out(chany_bottom_out[3])); + + mux_tree_tapbuf_size3 mux_bottom_track_9 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[5]}), + .sram(mux_tree_tapbuf_size3_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), + .out(chany_bottom_out[4])); + + mux_tree_tapbuf_size3 mux_bottom_track_11 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[6]}), + .sram(mux_tree_tapbuf_size3_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), + .out(chany_bottom_out[5])); + + mux_tree_tapbuf_size3 mux_bottom_track_15 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[8]}), + .sram(mux_tree_tapbuf_size3_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]), + .out(chany_bottom_out[7])); + + mux_tree_tapbuf_size3 mux_bottom_track_17 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, chanx_left_in[9]}), + .sram(mux_tree_tapbuf_size3_6_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]), + .out(chany_bottom_out[8])); + + mux_tree_tapbuf_size3 mux_bottom_track_25 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[0]}), + .sram(mux_tree_tapbuf_size3_7_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_7_sram_inv[0:1]), + .out(chany_bottom_out[12])); + + mux_tree_tapbuf_size3 mux_left_track_3 ( + .in({chany_bottom_in[0], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_8_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_8_sram_inv[0:1]), + .out(chanx_left_out[1])); + + mux_tree_tapbuf_size3 mux_left_track_5 ( + .in({chany_bottom_in[1], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_9_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_9_sram_inv[0:1]), + .out(chanx_left_out[2])); + + mux_tree_tapbuf_size3 mux_left_track_7 ( + .in({chany_bottom_in[2], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_10_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_10_sram_inv[0:1]), + .out(chanx_left_out[3])); + + mux_tree_tapbuf_size3 mux_left_track_9 ( + .in({chany_bottom_in[3], left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_11_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_11_sram_inv[0:1]), + .out(chanx_left_out[4])); + + mux_tree_tapbuf_size3 mux_left_track_11 ( + .in({chany_bottom_in[4], left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_12_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_12_sram_inv[0:1]), + .out(chanx_left_out[5])); + + mux_tree_tapbuf_size3 mux_left_track_15 ( + .in({chany_bottom_in[6], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_13_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_13_sram_inv[0:1]), + .out(chanx_left_out[7])); + + mux_tree_tapbuf_size3 mux_left_track_17 ( + .in({chany_bottom_in[7], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}), + .sram(mux_tree_tapbuf_size3_14_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_14_sram_inv[0:1]), + .out(chanx_left_out[8])); + + mux_tree_tapbuf_size3 mux_left_track_25 ( + .in({chany_bottom_in[11], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size3_15_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size3_15_sram_inv[0:1]), + .out(chanx_left_out[12])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_3 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_5 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_7 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_9 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_11 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_15 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_17 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_6_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_bottom_track_25 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_7_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_7_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_3 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_8_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_8_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_5 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_9_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_9_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_7 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_10_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_10_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_9 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_11_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_11_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_11 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_12_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_12_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_15 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_13_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_13_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_13_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_17 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_13_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size3_mem_14_ccff_tail), + .mem_out(mux_tree_tapbuf_size3_14_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_14_sram_inv[0:1])); + + mux_tree_tapbuf_size3_mem mem_left_track_25 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .ccff_tail(ccff_tail), + .mem_out(mux_tree_tapbuf_size3_15_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size3_15_sram_inv[0:1])); + + mux_tree_tapbuf_size2 mux_bottom_track_19 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[10]}), + .sram(mux_tree_tapbuf_size2_0_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .out(chany_bottom_out[9])); + + mux_tree_tapbuf_size2 mux_bottom_track_21 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[11]}), + .sram(mux_tree_tapbuf_size2_1_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .out(chany_bottom_out[10])); + + mux_tree_tapbuf_size2 mux_bottom_track_23 ( + .in({bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[12]}), + .sram(mux_tree_tapbuf_size2_2_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .out(chany_bottom_out[11])); + + mux_tree_tapbuf_size2 mux_left_track_19 ( + .in({chany_bottom_in[8], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_3_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .out(chanx_left_out[9])); + + mux_tree_tapbuf_size2 mux_left_track_21 ( + .in({chany_bottom_in[9], left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_4_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .out(chanx_left_out[10])); + + mux_tree_tapbuf_size2 mux_left_track_23 ( + .in({chany_bottom_in[10], left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_}), + .sram(mux_tree_tapbuf_size2_5_sram[0:1]), + .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .out(chanx_left_out[11])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_19 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_21 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_bottom_track_23 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_19 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size3_mem_14_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_21 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1])); + + mux_tree_tapbuf_size2_mem mem_left_track_23 ( + .prog_clk(prog_clk), + .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail), + .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail), + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), + .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1])); + +endmodule +// ----- END Verilog module for sb_1__1_ ----- + +//----- Default net type ----- +`default_nettype wire + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sb_0__0_.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sb_0__0_.sdc new file mode 100644 index 000000000..1eb6d3aae --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sb_0__0_.sdc @@ -0,0 +1,91 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Switch Block sb_0__0_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[1] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[2] -to fpga_top/sb_0__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[3] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[4] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[5] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[6] -to fpga_top/sb_0__0_/chany_top_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[7] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[8] -to fpga_top/sb_0__0_/chany_top_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] -to fpga_top/sb_0__0_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[9] -to fpga_top/sb_0__0_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[10] -to fpga_top/sb_0__0_/chany_top_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[11] -to fpga_top/sb_0__0_/chany_top_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[12] -to fpga_top/sb_0__0_/chany_top_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chanx_right_in[0] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[12] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[1] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[2] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[3] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[4] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[5] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[6] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[7] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[8] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[9] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[10] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__0_/chany_top_in[11] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sb_0__1_.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sb_0__1_.sdc new file mode 100644 index 000000000..8f37af1eb --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sb_0__1_.sdc @@ -0,0 +1,89 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Switch Block sb_0__1_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[11] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[9] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[7] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[5] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[4] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[3] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[2] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[1] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[0] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_bottom_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_bottom_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_bottom_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sb_1__0_.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sb_1__0_.sdc new file mode 100644 index 000000000..b17c6e0c0 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sb_1__0_.sdc @@ -0,0 +1,91 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Switch Block sb_1__0_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_top/sb_1__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[11] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[9] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[7] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[5] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[4] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[3] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[2] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chanx_left_in[1] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_left_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_left_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_left_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_left_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_left_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_left_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sb_1__1_.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sb_1__1_.sdc new file mode 100644 index 000000000..d70811c44 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sb_1__1_.sdc @@ -0,0 +1,89 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Switch Block sb_1__1_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_left_out[5] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_left_out[6] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_left_out[7] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_left_out[9] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_left_out[10] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_left_out[11] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_top/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/arch_encoder.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/arch_encoder.v new file mode 100644 index 000000000..3a42c112a --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/arch_encoder.v @@ -0,0 +1,6 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Decoders for fabric configuration protocol +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v new file mode 100644 index 000000000..9c69ae47b --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v @@ -0,0 +1,193 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Essential gates +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for const0 ----- +module const0(const0); +//----- OUTPUT PORTS ----- +output [0:0] const0; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + assign const0[0] = 1'b0; +endmodule +// ----- END Verilog module for const0 ----- + +//----- Default net type ----- +`default_nettype wire + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for const1 ----- +module const1(const1); +//----- OUTPUT PORTS ----- +output [0:0] const1; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + assign const1[0] = 1'b1; +endmodule +// ----- END Verilog module for const1 ----- + +//----- Default net type ----- +`default_nettype wire + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for INVTX1 ----- +module INVTX1(in, + out); +//----- INPUT PORTS ----- +input [0:0] in; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + +// ----- Verilog codes of a regular inverter ----- + assign out = (in === 1'bz)? $random : ~in; + +`ifdef ENABLE_TIMING +// ------ BEGIN Pin-to-pin Timing constraints ----- + specify + (in => out) = (0.01, 0.01); + endspecify +// ------ END Pin-to-pin Timing constraints ----- +`endif +endmodule +// ----- END Verilog module for INVTX1 ----- + +//----- Default net type ----- +`default_nettype wire + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for buf4 ----- +module buf4(in, + out); +//----- INPUT PORTS ----- +input [0:0] in; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + +// ----- Verilog codes of a regular inverter ----- + assign out = (in === 1'bz)? $random : in; + +`ifdef ENABLE_TIMING +// ------ BEGIN Pin-to-pin Timing constraints ----- + specify + (in => out) = (0.01, 0.01); + endspecify +// ------ END Pin-to-pin Timing constraints ----- +`endif +endmodule +// ----- END Verilog module for buf4 ----- + +//----- Default net type ----- +`default_nettype wire + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for tap_buf4 ----- +module tap_buf4(in, + out); +//----- INPUT PORTS ----- +input [0:0] in; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + +// ----- Verilog codes of a regular inverter ----- + assign out = (in === 1'bz)? $random : ~in; + +`ifdef ENABLE_TIMING +// ------ BEGIN Pin-to-pin Timing constraints ----- + specify + (in => out) = (0.01, 0.01); + endspecify +// ------ END Pin-to-pin Timing constraints ----- +`endif +endmodule +// ----- END Verilog module for tap_buf4 ----- + +//----- Default net type ----- +`default_nettype wire + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for TGATE ----- +module TGATE(in, + sel, + selb, + out); +//----- INPUT PORTS ----- +input [0:0] in; +//----- INPUT PORTS ----- +input [0:0] sel; +//----- INPUT PORTS ----- +input [0:0] selb; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + assign out = sel ? in : 1'bz; + +`ifdef ENABLE_TIMING +// ------ BEGIN Pin-to-pin Timing constraints ----- + specify + (in => out) = (0.01, 0.01); + (sel => out) = (0.005, 0.005); + (selb => out) = (0.005, 0.005); + endspecify +// ------ END Pin-to-pin Timing constraints ----- +`endif +endmodule +// ----- END Verilog module for TGATE ----- + +//----- Default net type ----- +`default_nettype wire + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/local_encoder.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/local_encoder.v new file mode 100644 index 000000000..49e4ef736 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/local_encoder.v @@ -0,0 +1,6 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Local Decoders for Multiplexers +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/luts.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/luts.v new file mode 100644 index 000000000..8e2d5245f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/luts.v @@ -0,0 +1,93 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Look-Up Tables +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for lut4 ----- +module lut4(in, + sram, + sram_inv, + out); +//----- INPUT PORTS ----- +input [0:3] in; +//----- INPUT PORTS ----- +input [0:15] sram; +//----- INPUT PORTS ----- +input [0:15] sram_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +wire [0:3] in; +wire [0:0] out; +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] INVTX1_0_out; +wire [0:0] INVTX1_1_out; +wire [0:0] INVTX1_2_out; +wire [0:0] INVTX1_3_out; +wire [0:0] buf4_0_out; +wire [0:0] buf4_1_out; +wire [0:0] buf4_2_out; +wire [0:0] buf4_3_out; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + INVTX1 INVTX1_0_ ( + .in(in[0]), + .out(INVTX1_0_out)); + + INVTX1 INVTX1_1_ ( + .in(in[1]), + .out(INVTX1_1_out)); + + INVTX1 INVTX1_2_ ( + .in(in[2]), + .out(INVTX1_2_out)); + + INVTX1 INVTX1_3_ ( + .in(in[3]), + .out(INVTX1_3_out)); + + buf4 buf4_0_ ( + .in(in[0]), + .out(buf4_0_out)); + + buf4 buf4_1_ ( + .in(in[1]), + .out(buf4_1_out)); + + buf4 buf4_2_ ( + .in(in[2]), + .out(buf4_2_out)); + + buf4 buf4_3_ ( + .in(in[3]), + .out(buf4_3_out)); + + lut4_mux lut4_mux_0_ ( + .in(sram[0:15]), + .sram({buf4_0_out, buf4_1_out, buf4_2_out, buf4_3_out}), + .sram_inv({INVTX1_0_out, INVTX1_1_out, INVTX1_2_out, INVTX1_3_out}), + .out(out)); + +endmodule +// ----- END Verilog module for lut4 ----- + +//----- Default net type ----- +`default_nettype wire + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/memories.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/memories.v new file mode 100644 index 000000000..6e40f5ac9 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/memories.v @@ -0,0 +1,500 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Memories used in FPGA +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size6_mem ----- +module mux_tree_tapbuf_size6_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; +//----- OUTPUT PORTS ----- +output [0:2] mem_out; +//----- OUTPUT PORTS ----- +output [0:2] mem_outb; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- + assign ccff_tail[0] = mem_out[2]; +// ----- END Local output short connections ----- + + DFF DFF_0_ ( + .CK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]), + .QN(mem_outb[0])); + + DFF DFF_1_ ( + .CK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]), + .QN(mem_outb[1])); + + DFF DFF_2_ ( + .CK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]), + .QN(mem_outb[2])); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size6_mem ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size4_mem ----- +module mux_tree_tapbuf_size4_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; +//----- OUTPUT PORTS ----- +output [0:2] mem_out; +//----- OUTPUT PORTS ----- +output [0:2] mem_outb; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- + assign ccff_tail[0] = mem_out[2]; +// ----- END Local output short connections ----- + + DFF DFF_0_ ( + .CK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]), + .QN(mem_outb[0])); + + DFF DFF_1_ ( + .CK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]), + .QN(mem_outb[1])); + + DFF DFF_2_ ( + .CK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]), + .QN(mem_outb[2])); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size4_mem ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size3_mem ----- +module mux_tree_tapbuf_size3_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; +//----- OUTPUT PORTS ----- +output [0:1] mem_out; +//----- OUTPUT PORTS ----- +output [0:1] mem_outb; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- + assign ccff_tail[0] = mem_out[1]; +// ----- END Local output short connections ----- + + DFF DFF_0_ ( + .CK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]), + .QN(mem_outb[0])); + + DFF DFF_1_ ( + .CK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]), + .QN(mem_outb[1])); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size3_mem ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size2_mem ----- +module mux_tree_tapbuf_size2_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; +//----- OUTPUT PORTS ----- +output [0:1] mem_out; +//----- OUTPUT PORTS ----- +output [0:1] mem_outb; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- + assign ccff_tail[0] = mem_out[1]; +// ----- END Local output short connections ----- + + DFF DFF_0_ ( + .CK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]), + .QN(mem_outb[0])); + + DFF DFF_1_ ( + .CK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]), + .QN(mem_outb[1])); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size2_mem ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_size14_mem ----- +module mux_tree_size14_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; +//----- OUTPUT PORTS ----- +output [0:3] mem_out; +//----- OUTPUT PORTS ----- +output [0:3] mem_outb; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- + assign ccff_tail[0] = mem_out[3]; +// ----- END Local output short connections ----- + + DFF DFF_0_ ( + .CK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]), + .QN(mem_outb[0])); + + DFF DFF_1_ ( + .CK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]), + .QN(mem_outb[1])); + + DFF DFF_2_ ( + .CK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]), + .QN(mem_outb[2])); + + DFF DFF_3_ ( + .CK(prog_clk), + .D(mem_out[2]), + .Q(mem_out[3]), + .QN(mem_outb[3])); + +endmodule +// ----- END Verilog module for mux_tree_size14_mem ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for lut4_DFF_mem ----- +module lut4_DFF_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; +//----- OUTPUT PORTS ----- +output [0:15] mem_out; +//----- OUTPUT PORTS ----- +output [0:15] mem_outb; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- + assign ccff_tail[0] = mem_out[15]; +// ----- END Local output short connections ----- + + DFF DFF_0_ ( + .CK(prog_clk), + .D(ccff_head), + .Q(mem_out[0]), + .QN(mem_outb[0])); + + DFF DFF_1_ ( + .CK(prog_clk), + .D(mem_out[0]), + .Q(mem_out[1]), + .QN(mem_outb[1])); + + DFF DFF_2_ ( + .CK(prog_clk), + .D(mem_out[1]), + .Q(mem_out[2]), + .QN(mem_outb[2])); + + DFF DFF_3_ ( + .CK(prog_clk), + .D(mem_out[2]), + .Q(mem_out[3]), + .QN(mem_outb[3])); + + DFF DFF_4_ ( + .CK(prog_clk), + .D(mem_out[3]), + .Q(mem_out[4]), + .QN(mem_outb[4])); + + DFF DFF_5_ ( + .CK(prog_clk), + .D(mem_out[4]), + .Q(mem_out[5]), + .QN(mem_outb[5])); + + DFF DFF_6_ ( + .CK(prog_clk), + .D(mem_out[5]), + .Q(mem_out[6]), + .QN(mem_outb[6])); + + DFF DFF_7_ ( + .CK(prog_clk), + .D(mem_out[6]), + .Q(mem_out[7]), + .QN(mem_outb[7])); + + DFF DFF_8_ ( + .CK(prog_clk), + .D(mem_out[7]), + .Q(mem_out[8]), + .QN(mem_outb[8])); + + DFF DFF_9_ ( + .CK(prog_clk), + .D(mem_out[8]), + .Q(mem_out[9]), + .QN(mem_outb[9])); + + DFF DFF_10_ ( + .CK(prog_clk), + .D(mem_out[9]), + .Q(mem_out[10]), + .QN(mem_outb[10])); + + DFF DFF_11_ ( + .CK(prog_clk), + .D(mem_out[10]), + .Q(mem_out[11]), + .QN(mem_outb[11])); + + DFF DFF_12_ ( + .CK(prog_clk), + .D(mem_out[11]), + .Q(mem_out[12]), + .QN(mem_outb[12])); + + DFF DFF_13_ ( + .CK(prog_clk), + .D(mem_out[12]), + .Q(mem_out[13]), + .QN(mem_outb[13])); + + DFF DFF_14_ ( + .CK(prog_clk), + .D(mem_out[13]), + .Q(mem_out[14]), + .QN(mem_outb[14])); + + DFF DFF_15_ ( + .CK(prog_clk), + .D(mem_out[14]), + .Q(mem_out[15]), + .QN(mem_outb[15])); + +endmodule +// ----- END Verilog module for lut4_DFF_mem ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for GPIO_DFF_mem ----- +module GPIO_DFF_mem(prog_clk, + ccff_head, + ccff_tail, + mem_out, + mem_outb); +//----- GLOBAL PORTS ----- +input [0:0] prog_clk; +//----- INPUT PORTS ----- +input [0:0] ccff_head; +//----- OUTPUT PORTS ----- +output [0:0] ccff_tail; +//----- OUTPUT PORTS ----- +output [0:0] mem_out; +//----- OUTPUT PORTS ----- +output [0:0] mem_outb; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- + assign ccff_tail[0] = mem_out[0]; +// ----- END Local output short connections ----- + + DFF DFF_0_ ( + .CK(prog_clk), + .D(ccff_head), + .Q(mem_out), + .QN(mem_outb)); + +endmodule +// ----- END Verilog module for GPIO_DFF_mem ----- + +//----- Default net type ----- +`default_nettype wire + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/mux_primitives.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/mux_primitives.v new file mode 100644 index 000000000..afcf99cac --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/mux_primitives.v @@ -0,0 +1,162 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Multiplexer primitives +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_basis_input2_mem1 ----- +module mux_tree_tapbuf_basis_input2_mem1(in, + mem, + mem_inv, + out); +//----- INPUT PORTS ----- +input [0:1] in; +//----- INPUT PORTS ----- +input [0:0] mem; +//----- INPUT PORTS ----- +input [0:0] mem_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + TGATE TGATE_0_ ( + .in(in[0]), + .sel(mem), + .selb(mem_inv), + .out(out)); + + TGATE TGATE_1_ ( + .in(in[1]), + .sel(mem_inv), + .selb(mem), + .out(out)); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_basis_input2_mem1 ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_basis_input2_mem1 ----- +module mux_tree_basis_input2_mem1(in, + mem, + mem_inv, + out); +//----- INPUT PORTS ----- +input [0:1] in; +//----- INPUT PORTS ----- +input [0:0] mem; +//----- INPUT PORTS ----- +input [0:0] mem_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + TGATE TGATE_0_ ( + .in(in[0]), + .sel(mem), + .selb(mem_inv), + .out(out)); + + TGATE TGATE_1_ ( + .in(in[1]), + .sel(mem_inv), + .selb(mem), + .out(out)); + +endmodule +// ----- END Verilog module for mux_tree_basis_input2_mem1 ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for lut4_mux_basis_input2_mem1 ----- +module lut4_mux_basis_input2_mem1(in, + mem, + mem_inv, + out); +//----- INPUT PORTS ----- +input [0:1] in; +//----- INPUT PORTS ----- +input [0:0] mem; +//----- INPUT PORTS ----- +input [0:0] mem_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + TGATE TGATE_0_ ( + .in(in[0]), + .sel(mem), + .selb(mem_inv), + .out(out)); + + TGATE TGATE_1_ ( + .in(in[1]), + .sel(mem_inv), + .selb(mem), + .out(out)); + +endmodule +// ----- END Verilog module for lut4_mux_basis_input2_mem1 ----- + +//----- Default net type ----- +`default_nettype wire + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/muxes.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/muxes.v new file mode 100644 index 000000000..9676a06d6 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/muxes.v @@ -0,0 +1,823 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Multiplexers +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size6 ----- +module mux_tree_tapbuf_size6(in, + sram, + sram_inv, + out); +//----- INPUT PORTS ----- +input [0:5] in; +//----- INPUT PORTS ----- +input [0:2] sram; +//----- INPUT PORTS ----- +input [0:2] sram_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] INVTX1_0_out; +wire [0:0] INVTX1_1_out; +wire [0:0] INVTX1_2_out; +wire [0:0] INVTX1_3_out; +wire [0:0] INVTX1_4_out; +wire [0:0] INVTX1_5_out; +wire [0:0] const1_0_const1; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_0_out; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_1_out; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_2_out; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_3_out; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_4_out; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_5_out; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + INVTX1 INVTX1_0_ ( + .in(in[0]), + .out(INVTX1_0_out)); + + INVTX1 INVTX1_1_ ( + .in(in[1]), + .out(INVTX1_1_out)); + + INVTX1 INVTX1_2_ ( + .in(in[2]), + .out(INVTX1_2_out)); + + INVTX1 INVTX1_3_ ( + .in(in[3]), + .out(INVTX1_3_out)); + + INVTX1 INVTX1_4_ ( + .in(in[4]), + .out(INVTX1_4_out)); + + INVTX1 INVTX1_5_ ( + .in(in[5]), + .out(INVTX1_5_out)); + + const1 const1_0_ ( + .const1(const1_0_const1)); + + tap_buf4 tap_buf4_0_ ( + .in(mux_tree_tapbuf_basis_input2_mem1_5_out), + .out(out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_0_ ( + .in({INVTX1_0_out, INVTX1_1_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_tapbuf_basis_input2_mem1_0_out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_1_ ( + .in({INVTX1_2_out, INVTX1_3_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_tapbuf_basis_input2_mem1_1_out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_2_ ( + .in({INVTX1_4_out, INVTX1_5_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_tapbuf_basis_input2_mem1_2_out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( + .in({mux_tree_tapbuf_basis_input2_mem1_0_out, mux_tree_tapbuf_basis_input2_mem1_1_out}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(mux_tree_tapbuf_basis_input2_mem1_3_out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l2_in_1_ ( + .in({mux_tree_tapbuf_basis_input2_mem1_2_out, const1_0_const1}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(mux_tree_tapbuf_basis_input2_mem1_4_out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l3_in_0_ ( + .in({mux_tree_tapbuf_basis_input2_mem1_3_out, mux_tree_tapbuf_basis_input2_mem1_4_out}), + .mem(sram[2]), + .mem_inv(sram_inv[2]), + .out(mux_tree_tapbuf_basis_input2_mem1_5_out)); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size6 ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size4 ----- +module mux_tree_tapbuf_size4(in, + sram, + sram_inv, + out); +//----- INPUT PORTS ----- +input [0:3] in; +//----- INPUT PORTS ----- +input [0:2] sram; +//----- INPUT PORTS ----- +input [0:2] sram_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] INVTX1_0_out; +wire [0:0] INVTX1_1_out; +wire [0:0] INVTX1_2_out; +wire [0:0] INVTX1_3_out; +wire [0:0] const1_0_const1; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_0_out; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_1_out; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_2_out; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_3_out; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + INVTX1 INVTX1_0_ ( + .in(in[0]), + .out(INVTX1_0_out)); + + INVTX1 INVTX1_1_ ( + .in(in[1]), + .out(INVTX1_1_out)); + + INVTX1 INVTX1_2_ ( + .in(in[2]), + .out(INVTX1_2_out)); + + INVTX1 INVTX1_3_ ( + .in(in[3]), + .out(INVTX1_3_out)); + + const1 const1_0_ ( + .const1(const1_0_const1)); + + tap_buf4 tap_buf4_0_ ( + .in(mux_tree_tapbuf_basis_input2_mem1_3_out), + .out(out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_0_ ( + .in({INVTX1_0_out, INVTX1_1_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_tapbuf_basis_input2_mem1_0_out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( + .in({mux_tree_tapbuf_basis_input2_mem1_0_out, INVTX1_2_out}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(mux_tree_tapbuf_basis_input2_mem1_1_out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l2_in_1_ ( + .in({INVTX1_3_out, const1_0_const1}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(mux_tree_tapbuf_basis_input2_mem1_2_out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l3_in_0_ ( + .in({mux_tree_tapbuf_basis_input2_mem1_1_out, mux_tree_tapbuf_basis_input2_mem1_2_out}), + .mem(sram[2]), + .mem_inv(sram_inv[2]), + .out(mux_tree_tapbuf_basis_input2_mem1_3_out)); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size4 ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size3 ----- +module mux_tree_tapbuf_size3(in, + sram, + sram_inv, + out); +//----- INPUT PORTS ----- +input [0:2] in; +//----- INPUT PORTS ----- +input [0:1] sram; +//----- INPUT PORTS ----- +input [0:1] sram_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] INVTX1_0_out; +wire [0:0] INVTX1_1_out; +wire [0:0] INVTX1_2_out; +wire [0:0] const1_0_const1; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_0_out; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_1_out; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_2_out; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + INVTX1 INVTX1_0_ ( + .in(in[0]), + .out(INVTX1_0_out)); + + INVTX1 INVTX1_1_ ( + .in(in[1]), + .out(INVTX1_1_out)); + + INVTX1 INVTX1_2_ ( + .in(in[2]), + .out(INVTX1_2_out)); + + const1 const1_0_ ( + .const1(const1_0_const1)); + + tap_buf4 tap_buf4_0_ ( + .in(mux_tree_tapbuf_basis_input2_mem1_2_out), + .out(out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_0_ ( + .in({INVTX1_0_out, INVTX1_1_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_tapbuf_basis_input2_mem1_0_out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_1_ ( + .in({INVTX1_2_out, const1_0_const1}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_tapbuf_basis_input2_mem1_1_out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( + .in({mux_tree_tapbuf_basis_input2_mem1_0_out, mux_tree_tapbuf_basis_input2_mem1_1_out}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(mux_tree_tapbuf_basis_input2_mem1_2_out)); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size3 ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_tapbuf_size2 ----- +module mux_tree_tapbuf_size2(in, + sram, + sram_inv, + out); +//----- INPUT PORTS ----- +input [0:1] in; +//----- INPUT PORTS ----- +input [0:1] sram; +//----- INPUT PORTS ----- +input [0:1] sram_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] INVTX1_0_out; +wire [0:0] INVTX1_1_out; +wire [0:0] const1_0_const1; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_0_out; +wire [0:0] mux_tree_tapbuf_basis_input2_mem1_1_out; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + INVTX1 INVTX1_0_ ( + .in(in[0]), + .out(INVTX1_0_out)); + + INVTX1 INVTX1_1_ ( + .in(in[1]), + .out(INVTX1_1_out)); + + const1 const1_0_ ( + .const1(const1_0_const1)); + + tap_buf4 tap_buf4_0_ ( + .in(mux_tree_tapbuf_basis_input2_mem1_1_out), + .out(out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_0_ ( + .in({INVTX1_0_out, INVTX1_1_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_tapbuf_basis_input2_mem1_0_out)); + + mux_tree_tapbuf_basis_input2_mem1 mux_l2_in_0_ ( + .in({mux_tree_tapbuf_basis_input2_mem1_0_out, const1_0_const1}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(mux_tree_tapbuf_basis_input2_mem1_1_out)); + +endmodule +// ----- END Verilog module for mux_tree_tapbuf_size2 ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for mux_tree_size14 ----- +module mux_tree_size14(in, + sram, + sram_inv, + out); +//----- INPUT PORTS ----- +input [0:13] in; +//----- INPUT PORTS ----- +input [0:3] sram; +//----- INPUT PORTS ----- +input [0:3] sram_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] INVTX1_0_out; +wire [0:0] INVTX1_10_out; +wire [0:0] INVTX1_11_out; +wire [0:0] INVTX1_12_out; +wire [0:0] INVTX1_13_out; +wire [0:0] INVTX1_1_out; +wire [0:0] INVTX1_2_out; +wire [0:0] INVTX1_3_out; +wire [0:0] INVTX1_4_out; +wire [0:0] INVTX1_5_out; +wire [0:0] INVTX1_6_out; +wire [0:0] INVTX1_7_out; +wire [0:0] INVTX1_8_out; +wire [0:0] INVTX1_9_out; +wire [0:0] const1_0_const1; +wire [0:0] mux_tree_basis_input2_mem1_0_out; +wire [0:0] mux_tree_basis_input2_mem1_10_out; +wire [0:0] mux_tree_basis_input2_mem1_11_out; +wire [0:0] mux_tree_basis_input2_mem1_12_out; +wire [0:0] mux_tree_basis_input2_mem1_13_out; +wire [0:0] mux_tree_basis_input2_mem1_1_out; +wire [0:0] mux_tree_basis_input2_mem1_2_out; +wire [0:0] mux_tree_basis_input2_mem1_3_out; +wire [0:0] mux_tree_basis_input2_mem1_4_out; +wire [0:0] mux_tree_basis_input2_mem1_5_out; +wire [0:0] mux_tree_basis_input2_mem1_6_out; +wire [0:0] mux_tree_basis_input2_mem1_7_out; +wire [0:0] mux_tree_basis_input2_mem1_8_out; +wire [0:0] mux_tree_basis_input2_mem1_9_out; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + INVTX1 INVTX1_0_ ( + .in(in[0]), + .out(INVTX1_0_out)); + + INVTX1 INVTX1_1_ ( + .in(in[1]), + .out(INVTX1_1_out)); + + INVTX1 INVTX1_2_ ( + .in(in[2]), + .out(INVTX1_2_out)); + + INVTX1 INVTX1_3_ ( + .in(in[3]), + .out(INVTX1_3_out)); + + INVTX1 INVTX1_4_ ( + .in(in[4]), + .out(INVTX1_4_out)); + + INVTX1 INVTX1_5_ ( + .in(in[5]), + .out(INVTX1_5_out)); + + INVTX1 INVTX1_6_ ( + .in(in[6]), + .out(INVTX1_6_out)); + + INVTX1 INVTX1_7_ ( + .in(in[7]), + .out(INVTX1_7_out)); + + INVTX1 INVTX1_8_ ( + .in(in[8]), + .out(INVTX1_8_out)); + + INVTX1 INVTX1_9_ ( + .in(in[9]), + .out(INVTX1_9_out)); + + INVTX1 INVTX1_10_ ( + .in(in[10]), + .out(INVTX1_10_out)); + + INVTX1 INVTX1_11_ ( + .in(in[11]), + .out(INVTX1_11_out)); + + INVTX1 INVTX1_12_ ( + .in(in[12]), + .out(INVTX1_12_out)); + + INVTX1 INVTX1_13_ ( + .in(in[13]), + .out(INVTX1_13_out)); + + INVTX1 INVTX1_14_ ( + .in(mux_tree_basis_input2_mem1_13_out), + .out(out)); + + const1 const1_0_ ( + .const1(const1_0_const1)); + + mux_tree_basis_input2_mem1 mux_l1_in_0_ ( + .in({INVTX1_0_out, INVTX1_1_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_basis_input2_mem1_0_out)); + + mux_tree_basis_input2_mem1 mux_l1_in_1_ ( + .in({INVTX1_2_out, INVTX1_3_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_basis_input2_mem1_1_out)); + + mux_tree_basis_input2_mem1 mux_l1_in_2_ ( + .in({INVTX1_4_out, INVTX1_5_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_basis_input2_mem1_2_out)); + + mux_tree_basis_input2_mem1 mux_l1_in_3_ ( + .in({INVTX1_6_out, INVTX1_7_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_basis_input2_mem1_3_out)); + + mux_tree_basis_input2_mem1 mux_l1_in_4_ ( + .in({INVTX1_8_out, INVTX1_9_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_basis_input2_mem1_4_out)); + + mux_tree_basis_input2_mem1 mux_l1_in_5_ ( + .in({INVTX1_10_out, INVTX1_11_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_basis_input2_mem1_5_out)); + + mux_tree_basis_input2_mem1 mux_l1_in_6_ ( + .in({INVTX1_12_out, INVTX1_13_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(mux_tree_basis_input2_mem1_6_out)); + + mux_tree_basis_input2_mem1 mux_l2_in_0_ ( + .in({mux_tree_basis_input2_mem1_0_out, mux_tree_basis_input2_mem1_1_out}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(mux_tree_basis_input2_mem1_7_out)); + + mux_tree_basis_input2_mem1 mux_l2_in_1_ ( + .in({mux_tree_basis_input2_mem1_2_out, mux_tree_basis_input2_mem1_3_out}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(mux_tree_basis_input2_mem1_8_out)); + + mux_tree_basis_input2_mem1 mux_l2_in_2_ ( + .in({mux_tree_basis_input2_mem1_4_out, mux_tree_basis_input2_mem1_5_out}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(mux_tree_basis_input2_mem1_9_out)); + + mux_tree_basis_input2_mem1 mux_l2_in_3_ ( + .in({mux_tree_basis_input2_mem1_6_out, const1_0_const1}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(mux_tree_basis_input2_mem1_10_out)); + + mux_tree_basis_input2_mem1 mux_l3_in_0_ ( + .in({mux_tree_basis_input2_mem1_7_out, mux_tree_basis_input2_mem1_8_out}), + .mem(sram[2]), + .mem_inv(sram_inv[2]), + .out(mux_tree_basis_input2_mem1_11_out)); + + mux_tree_basis_input2_mem1 mux_l3_in_1_ ( + .in({mux_tree_basis_input2_mem1_9_out, mux_tree_basis_input2_mem1_10_out}), + .mem(sram[2]), + .mem_inv(sram_inv[2]), + .out(mux_tree_basis_input2_mem1_12_out)); + + mux_tree_basis_input2_mem1 mux_l4_in_0_ ( + .in({mux_tree_basis_input2_mem1_11_out, mux_tree_basis_input2_mem1_12_out}), + .mem(sram[3]), + .mem_inv(sram_inv[3]), + .out(mux_tree_basis_input2_mem1_13_out)); + +endmodule +// ----- END Verilog module for mux_tree_size14 ----- + +//----- Default net type ----- +`default_nettype wire + + + + +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for lut4_mux ----- +module lut4_mux(in, + sram, + sram_inv, + out); +//----- INPUT PORTS ----- +input [0:15] in; +//----- INPUT PORTS ----- +input [0:3] sram; +//----- INPUT PORTS ----- +input [0:3] sram_inv; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + + +wire [0:0] INVTX1_0_out; +wire [0:0] INVTX1_10_out; +wire [0:0] INVTX1_11_out; +wire [0:0] INVTX1_12_out; +wire [0:0] INVTX1_13_out; +wire [0:0] INVTX1_14_out; +wire [0:0] INVTX1_15_out; +wire [0:0] INVTX1_1_out; +wire [0:0] INVTX1_2_out; +wire [0:0] INVTX1_3_out; +wire [0:0] INVTX1_4_out; +wire [0:0] INVTX1_5_out; +wire [0:0] INVTX1_6_out; +wire [0:0] INVTX1_7_out; +wire [0:0] INVTX1_8_out; +wire [0:0] INVTX1_9_out; +wire [0:0] lut4_mux_basis_input2_mem1_0_out; +wire [0:0] lut4_mux_basis_input2_mem1_10_out; +wire [0:0] lut4_mux_basis_input2_mem1_11_out; +wire [0:0] lut4_mux_basis_input2_mem1_12_out; +wire [0:0] lut4_mux_basis_input2_mem1_13_out; +wire [0:0] lut4_mux_basis_input2_mem1_14_out; +wire [0:0] lut4_mux_basis_input2_mem1_1_out; +wire [0:0] lut4_mux_basis_input2_mem1_2_out; +wire [0:0] lut4_mux_basis_input2_mem1_3_out; +wire [0:0] lut4_mux_basis_input2_mem1_4_out; +wire [0:0] lut4_mux_basis_input2_mem1_5_out; +wire [0:0] lut4_mux_basis_input2_mem1_6_out; +wire [0:0] lut4_mux_basis_input2_mem1_7_out; +wire [0:0] lut4_mux_basis_input2_mem1_8_out; +wire [0:0] lut4_mux_basis_input2_mem1_9_out; + +// ----- BEGIN Local short connections ----- +// ----- END Local short connections ----- +// ----- BEGIN Local output short connections ----- +// ----- END Local output short connections ----- + + INVTX1 INVTX1_0_ ( + .in(in[0]), + .out(INVTX1_0_out)); + + INVTX1 INVTX1_1_ ( + .in(in[1]), + .out(INVTX1_1_out)); + + INVTX1 INVTX1_2_ ( + .in(in[2]), + .out(INVTX1_2_out)); + + INVTX1 INVTX1_3_ ( + .in(in[3]), + .out(INVTX1_3_out)); + + INVTX1 INVTX1_4_ ( + .in(in[4]), + .out(INVTX1_4_out)); + + INVTX1 INVTX1_5_ ( + .in(in[5]), + .out(INVTX1_5_out)); + + INVTX1 INVTX1_6_ ( + .in(in[6]), + .out(INVTX1_6_out)); + + INVTX1 INVTX1_7_ ( + .in(in[7]), + .out(INVTX1_7_out)); + + INVTX1 INVTX1_8_ ( + .in(in[8]), + .out(INVTX1_8_out)); + + INVTX1 INVTX1_9_ ( + .in(in[9]), + .out(INVTX1_9_out)); + + INVTX1 INVTX1_10_ ( + .in(in[10]), + .out(INVTX1_10_out)); + + INVTX1 INVTX1_11_ ( + .in(in[11]), + .out(INVTX1_11_out)); + + INVTX1 INVTX1_12_ ( + .in(in[12]), + .out(INVTX1_12_out)); + + INVTX1 INVTX1_13_ ( + .in(in[13]), + .out(INVTX1_13_out)); + + INVTX1 INVTX1_14_ ( + .in(in[14]), + .out(INVTX1_14_out)); + + INVTX1 INVTX1_15_ ( + .in(in[15]), + .out(INVTX1_15_out)); + + INVTX1 INVTX1_16_ ( + .in(lut4_mux_basis_input2_mem1_14_out), + .out(out)); + + lut4_mux_basis_input2_mem1 mux_l1_in_0_ ( + .in({INVTX1_0_out, INVTX1_1_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(lut4_mux_basis_input2_mem1_0_out)); + + lut4_mux_basis_input2_mem1 mux_l1_in_1_ ( + .in({INVTX1_2_out, INVTX1_3_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(lut4_mux_basis_input2_mem1_1_out)); + + lut4_mux_basis_input2_mem1 mux_l1_in_2_ ( + .in({INVTX1_4_out, INVTX1_5_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(lut4_mux_basis_input2_mem1_2_out)); + + lut4_mux_basis_input2_mem1 mux_l1_in_3_ ( + .in({INVTX1_6_out, INVTX1_7_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(lut4_mux_basis_input2_mem1_3_out)); + + lut4_mux_basis_input2_mem1 mux_l1_in_4_ ( + .in({INVTX1_8_out, INVTX1_9_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(lut4_mux_basis_input2_mem1_4_out)); + + lut4_mux_basis_input2_mem1 mux_l1_in_5_ ( + .in({INVTX1_10_out, INVTX1_11_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(lut4_mux_basis_input2_mem1_5_out)); + + lut4_mux_basis_input2_mem1 mux_l1_in_6_ ( + .in({INVTX1_12_out, INVTX1_13_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(lut4_mux_basis_input2_mem1_6_out)); + + lut4_mux_basis_input2_mem1 mux_l1_in_7_ ( + .in({INVTX1_14_out, INVTX1_15_out}), + .mem(sram[0]), + .mem_inv(sram_inv[0]), + .out(lut4_mux_basis_input2_mem1_7_out)); + + lut4_mux_basis_input2_mem1 mux_l2_in_0_ ( + .in({lut4_mux_basis_input2_mem1_0_out, lut4_mux_basis_input2_mem1_1_out}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(lut4_mux_basis_input2_mem1_8_out)); + + lut4_mux_basis_input2_mem1 mux_l2_in_1_ ( + .in({lut4_mux_basis_input2_mem1_2_out, lut4_mux_basis_input2_mem1_3_out}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(lut4_mux_basis_input2_mem1_9_out)); + + lut4_mux_basis_input2_mem1 mux_l2_in_2_ ( + .in({lut4_mux_basis_input2_mem1_4_out, lut4_mux_basis_input2_mem1_5_out}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(lut4_mux_basis_input2_mem1_10_out)); + + lut4_mux_basis_input2_mem1 mux_l2_in_3_ ( + .in({lut4_mux_basis_input2_mem1_6_out, lut4_mux_basis_input2_mem1_7_out}), + .mem(sram[1]), + .mem_inv(sram_inv[1]), + .out(lut4_mux_basis_input2_mem1_11_out)); + + lut4_mux_basis_input2_mem1 mux_l3_in_0_ ( + .in({lut4_mux_basis_input2_mem1_8_out, lut4_mux_basis_input2_mem1_9_out}), + .mem(sram[2]), + .mem_inv(sram_inv[2]), + .out(lut4_mux_basis_input2_mem1_12_out)); + + lut4_mux_basis_input2_mem1 mux_l3_in_1_ ( + .in({lut4_mux_basis_input2_mem1_10_out, lut4_mux_basis_input2_mem1_11_out}), + .mem(sram[2]), + .mem_inv(sram_inv[2]), + .out(lut4_mux_basis_input2_mem1_13_out)); + + lut4_mux_basis_input2_mem1 mux_l4_in_0_ ( + .in({lut4_mux_basis_input2_mem1_12_out, lut4_mux_basis_input2_mem1_13_out}), + .mem(sram[3]), + .mem_inv(sram_inv[3]), + .out(lut4_mux_basis_input2_mem1_14_out)); + +endmodule +// ----- END Verilog module for lut4_mux ----- + +//----- Default net type ----- +`default_nettype wire + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v new file mode 100644 index 000000000..59d6aa2b8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v @@ -0,0 +1,6 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Shift register banks used in FPGA +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v new file mode 100644 index 000000000..1d5542b75 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v @@ -0,0 +1,117 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Template for user-defined Verilog modules +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +// ----- Template Verilog module for DFFSRQ ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for DFFSRQ ----- +module DFFSRQ(SET, + RST, + CK, + D, + Q); +//----- GLOBAL PORTS ----- +input [0:0] SET; +//----- GLOBAL PORTS ----- +input [0:0] RST; +//----- GLOBAL PORTS ----- +input [0:0] CK; +//----- INPUT PORTS ----- +input [0:0] D; +//----- OUTPUT PORTS ----- +output [0:0] Q; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + +// ----- Internal logic should start here ----- + + +// ----- Internal logic should end here ----- +endmodule +// ----- END Verilog module for DFFSRQ ----- + +//----- Default net type ----- +`default_nettype wire + + +// ----- Template Verilog module for DFF ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for DFF ----- +module DFF(CK, + D, + Q, + QN); +//----- GLOBAL PORTS ----- +input [0:0] CK; +//----- INPUT PORTS ----- +input [0:0] D; +//----- OUTPUT PORTS ----- +output [0:0] Q; +//----- OUTPUT PORTS ----- +output [0:0] QN; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + +// ----- Internal logic should start here ----- + + +// ----- Internal logic should end here ----- +endmodule +// ----- END Verilog module for DFF ----- + +//----- Default net type ----- +`default_nettype wire + + +// ----- Template Verilog module for GPIO ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for GPIO ----- +module GPIO(PAD, + A, + DIR, + Y); +//----- GPIO PORTS ----- +inout [0:0] PAD; +//----- INPUT PORTS ----- +input [0:0] A; +//----- INPUT PORTS ----- +input [0:0] DIR; +//----- OUTPUT PORTS ----- +output [0:0] Y; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + +// ----- Internal logic should start here ----- + + +// ----- Internal logic should end here ----- +endmodule +// ----- END Verilog module for GPIO ----- + +//----- Default net type ----- +`default_nettype wire + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/wires.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/wires.v new file mode 100644 index 000000000..ab3ee5445 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/sub_module/wires.v @@ -0,0 +1,36 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Wires +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +// ----- BEGIN Verilog modules for regular wires ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for direct_interc ----- +module direct_interc(in, + out); +//----- INPUT PORTS ----- +input [0:0] in; +//----- OUTPUT PORTS ----- +output [0:0] out; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + +wire [0:0] in; +wire [0:0] out; + assign out[0] = in[0]; +endmodule +// ----- END Verilog module for direct_interc ----- + +//----- Default net type ----- +`default_nettype wire + + +// ----- END Verilog modules for regular wires ----- diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/config/task.conf b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/config/task.conf index 60c164b4d..7ea074a5f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/config/task.conf @@ -22,6 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio openfpga_vpr_device_layout = 2x2 openfpga_vpr_route_chan_width = 20 openfpga_output_dir=${PATH:TASK_DIR}/golden_outputs_no_time_stamp +openfpga_preconfig_fabric_wrapper_dump_waveform= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v index e9c8f977d..8321cad47 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v @@ -47,7 +47,7 @@ module and2_top_formal_verification_random_tb; initial begin clk[0] <= 1'b0; while(1) begin - #0.4866067469 + #0.5400847197 clk[0] <= !clk[0]; end end @@ -106,7 +106,7 @@ initial begin $timeformat(-9, 2, "ns", 20); $display("Simulation start"); // ----- Can be changed by the user for his/her need ------- - #6.812494755 + #7.561185837 if(nb_error == 0) begin $display("Simulation Succeed"); end else begin diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc index 73d00c19f..a45d6aa34 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc @@ -9,14 +9,14 @@ ################################################## # Create clock ################################################## -create_clock clk[0] -period 9.732135098e-10 -waveform {0 4.866067549e-10} +create_clock clk[0] -period 1.080169398e-09 -waveform {0 5.400846992e-10} ################################################## # Create input and output delays for used I/Os ################################################## -set_input_delay -clock clk[0] -max 9.732135098e-10 gfpga_pad_GPIO_PAD[22] -set_input_delay -clock clk[0] -max 9.732135098e-10 gfpga_pad_GPIO_PAD[26] -set_output_delay -clock clk[0] -max 9.732135098e-10 gfpga_pad_GPIO_PAD[9] +set_input_delay -clock clk[0] -max 1.080169398e-09 gfpga_pad_GPIO_PAD[22] +set_input_delay -clock clk[0] -max 1.080169398e-09 gfpga_pad_GPIO_PAD[26] +set_output_delay -clock clk[0] -max 1.080169398e-09 gfpga_pad_GPIO_PAD[9] ################################################## # Disable timing for unused I/Os diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_pin_phy_loc.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_pin_phy_loc.xml new file mode 100644 index 000000000..124109017 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_pin_phy_loc.xml @@ -0,0 +1,1105 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/global_ports.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/global_ports.sdc index f0d0e3c9b..610adfd62 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/global_ports.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/global_ports.sdc @@ -14,7 +14,7 @@ set_units -time s ################################################## # Create clock ################################################## -create_clock -name clk[0] -period 9.732135098e-10 -waveform {0 4.866067549e-10} [get_ports {clk[0]}] +create_clock -name clk[0] -period 1.080169398e-09 -waveform {0 5.400846992e-10} [get_ports {clk[0]}] ################################################## # Create programmable clock ################################################## diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml index 6b76a5c9a..8cee42a6f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml @@ -1,34 +1,34 @@ - + - + - + - + - + - + - + - + @@ -39,44 +39,44 @@ - - + + - - + + - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml index a44b3a915..b92fd2831 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml @@ -1,8 +1,8 @@ - - - + + + @@ -20,9 +20,9 @@ - - - + + + @@ -39,8 +39,8 @@ - - + + @@ -53,25 +53,25 @@ - + - + - + - + @@ -103,9 +103,9 @@ - - - + + + @@ -123,9 +123,9 @@ - - - + + + @@ -142,8 +142,8 @@ - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_0__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_0__2_.xml index e9a236355..40001d7a5 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_0__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_0__2_.xml @@ -1,34 +1,34 @@ - + - + - + - + - + - + - + - + @@ -39,35 +39,35 @@ - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml index 5852252cc..20c1fff92 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml @@ -1,24 +1,24 @@ - + - + - + - + @@ -48,10 +48,10 @@ - - - - + + + + @@ -70,10 +70,10 @@ - - - - + + + + @@ -90,10 +90,10 @@ - - - - + + + + @@ -108,10 +108,10 @@ - - - - + + + + @@ -128,10 +128,10 @@ - - - - + + + + @@ -148,10 +148,10 @@ - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml index c8a81010f..5f6ce3d54 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml @@ -1,7 +1,7 @@ - - + + @@ -24,7 +24,7 @@ - + @@ -44,7 +44,7 @@ - + @@ -62,8 +62,8 @@ - - + + @@ -85,7 +85,7 @@ - + @@ -105,7 +105,7 @@ - + @@ -123,8 +123,8 @@ - - + + @@ -145,7 +145,7 @@ - + @@ -165,7 +165,7 @@ - + @@ -185,8 +185,8 @@ - - + + @@ -206,7 +206,7 @@ - + @@ -226,7 +226,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_1__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_1__2_.xml index 6c03f3109..d5a883d4b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_1__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_1__2_.xml @@ -1,8 +1,8 @@ - - - + + + @@ -20,9 +20,9 @@ - - - + + + @@ -40,8 +40,8 @@ - - + + @@ -53,24 +53,24 @@ - + - + - + - + @@ -102,9 +102,9 @@ - - - + + + @@ -122,9 +122,9 @@ - - - + + + @@ -141,8 +141,8 @@ - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_2__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_2__0_.xml index 520bdb20f..0eb3629ba 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_2__0_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_2__0_.xml @@ -1,86 +1,86 @@ - - + + - - + + - + - + - + - + - + - + - + - + - - + + - - + + - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_2__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_2__1_.xml index fa68d4ad3..07cd62c33 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_2__1_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_2__1_.xml @@ -1,9 +1,9 @@ - - - - + + + + @@ -22,10 +22,10 @@ - - - - + + + + @@ -42,10 +42,10 @@ - - - - + + + + @@ -59,10 +59,10 @@ - - - - + + + + @@ -79,10 +79,10 @@ - - - - + + + + @@ -99,10 +99,10 @@ - - - - + + + + @@ -115,25 +115,25 @@ - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_2__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_2__2_.xml index 4a8ca3efe..09fbf2ac6 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_2__2_.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/sb_2__2_.xml @@ -1,77 +1,77 @@ - - + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/mux_modules.yaml b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/mux_modules.yaml new file mode 100644 index 000000000..8ee171e0a --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/mux_modules.yaml @@ -0,0 +1,54 @@ +sb_0__0_: + - mux_2level_tapbuf_size2 + - mux_2level_tapbuf_size3 +sb_0__1_: + - mux_2level_tapbuf_size9 + - mux_2level_tapbuf_size8 + - mux_2level_tapbuf_size3 + - mux_2level_tapbuf_size4 + - mux_2level_tapbuf_size2 + - mux_2level_tapbuf_size7 +sb_0__2_: + - mux_2level_tapbuf_size2 +sb_1__0_: + - mux_2level_tapbuf_size5 + - mux_2level_tapbuf_size4 + - mux_2level_tapbuf_size3 + - mux_2level_tapbuf_size2 + - mux_2level_tapbuf_size10 + - mux_2level_tapbuf_size9 + - mux_2level_tapbuf_size11 +sb_1__1_: + - mux_2level_tapbuf_size13 + - mux_2level_tapbuf_size9 +sb_1__2_: + - mux_2level_tapbuf_size9 + - mux_2level_tapbuf_size7 + - mux_2level_tapbuf_size4 + - mux_2level_tapbuf_size3 + - mux_2level_tapbuf_size2 +sb_2__0_: + - mux_2level_tapbuf_size3 + - mux_2level_tapbuf_size2 +sb_2__1_: + - mux_2level_tapbuf_size11 + - mux_2level_tapbuf_size9 + - mux_2level_tapbuf_size10 + - mux_2level_tapbuf_size4 + - mux_2level_tapbuf_size2 +sb_2__2_: + - mux_2level_tapbuf_size3 + - mux_2level_tapbuf_size2 +cbx_1__0_: + - mux_2level_tapbuf_size2 + - mux_2level_tapbuf_size4 +cbx_1__1_: + - mux_2level_tapbuf_size2 +cbx_1__2_: + - mux_2level_tapbuf_size4 +cby_0__1_: + - mux_2level_tapbuf_size4 +cby_1__1_: + - mux_2level_tapbuf_size4 +cby_2__1_: + - mux_2level_tapbuf_size4 diff --git a/openfpga_flow/tasks/basic_tests/preload_rr_graph/preload_rr_graph_bin/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_rr_graph/preload_rr_graph_bin/config/task.conf new file mode 100644 index 000000000..99dc26c0c --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_rr_graph/preload_rr_graph_bin/config/task.conf @@ -0,0 +1,39 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/preload_rr_graph_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124X_L12Y_40nm_frame_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=4x4 +openfpga_vpr_route_chan_width=60 +openfpga_vpr_rr_graph_file=rr_graph.bin + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124X_L12Y_ChanWidth0p8_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/preload_rr_graph/preload_rr_graph_xml/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_rr_graph/preload_rr_graph_xml/config/task.conf new file mode 100644 index 000000000..856d7a45c --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_rr_graph/preload_rr_graph_xml/config/task.conf @@ -0,0 +1,39 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/preload_rr_graph_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124X_L12Y_40nm_frame_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=4x4 +openfpga_vpr_route_chan_width=60 +openfpga_vpr_rr_graph_file=rr_graph.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124X_L12Y_ChanWidth0p8_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/task.conf new file mode 100644 index 000000000..8f1b5aa53 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/task.conf @@ -0,0 +1,41 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_ecb_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options=--skip_sync_clustering_and_routing_results on +openfpga_pb_pin_fixup_command=pb_pin_fixup +openfpga_vpr_device=2x2 +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBr_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_default/config/task.conf b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_default/config/task.conf new file mode 100644 index 000000000..094b80b88 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_default/config/task.conf @@ -0,0 +1,43 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_write_fabric_pin_phy_loc_preconfig_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=auto +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping +openfpga_fabric_pin_phy_loc_file=fabric_pin_phy_loc.xml +openfpga_fabric_pin_phy_loc_module= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_default/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_default/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_default/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles/config/task.conf b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles/config/task.conf new file mode 100644 index 000000000..a8fcda0db --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles/config/task.conf @@ -0,0 +1,43 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_write_fabric_pin_phy_loc_preconfig_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=auto +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping +openfpga_fabric_pin_phy_loc_file=fabric_pin_phy_loc.xml +openfpga_fabric_pin_phy_loc_module=--module tile* + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_show_invalid_sides/config/task.conf b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_show_invalid_sides/config/task.conf new file mode 100644 index 000000000..a6abb1e92 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_show_invalid_sides/config/task.conf @@ -0,0 +1,43 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_write_fabric_pin_phy_loc_preconfig_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=auto +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping +openfpga_fabric_pin_phy_loc_file=fabric_pin_phy_loc.xml +openfpga_fabric_pin_phy_loc_module=--module tile* --show_invalid_side + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_show_invalid_sides/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_show_invalid_sides/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_show_invalid_sides/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_wildcards/config/task.conf b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_wildcards/config/task.conf new file mode 100644 index 000000000..1382ad6f0 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_wildcards/config/task.conf @@ -0,0 +1,43 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_write_fabric_pin_phy_loc_preconfig_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=auto +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping +openfpga_fabric_pin_phy_loc_file=fabric_pin_phy_loc.xml +openfpga_fabric_pin_phy_loc_module=--module * + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_wildcards/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_wildcards/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_wildcards/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_repack_dc.xml b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_repack_dc.xml index 71153e425..748e23269 100644 --- a/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_repack_dc.xml +++ b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_repack_dc.xml @@ -2,7 +2,7 @@ - + diff --git a/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/task.conf index 63ffd257c..6076c364f 100644 --- a/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/task.conf +++ b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/task.conf @@ -28,6 +28,8 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_lo [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/two_dff_inv_rst/two_dff_inv_rst.v bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut_4bit/rst_on_lut_4bit.v +bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut_8bit/rst_on_lut_8bit.v [SYNTHESIS_PARAM] # Yosys script parameters @@ -45,6 +47,14 @@ bench1_top = rst_on_lut bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/rst_on_lut_pc.xml bench1_openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/rst_on_lut_repack_dc.xml +bench2_top = rst_on_lut_4bit +bench2_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/rst_on_lut_pc.xml +bench2_openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/rst_on_lut_repack_dc.xml + +bench3_top = rst_on_lut_8bit +bench3_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/rst_on_lut_pc.xml +bench3_openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/rst_on_lut_repack_dc.xml + [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/vpr_arch/README.md b/openfpga_flow/vpr_arch/README.md index 65f3c3d55..7f8a000b5 100644 --- a/openfpga_flow/vpr_arch/README.md +++ b/openfpga_flow/vpr_arch/README.md @@ -33,6 +33,7 @@ Please reveal the following architecture features in the names to help quickly s * Top-right (Tr): the pins of a tile are placed on the top side and right side only * Bottom-right (Br): the pins of a tile are placed on the bottom side and right side only - GlobalTileClk: How many clocks are defined through global ports from physical tiles. is the number of clocks +- ecb: *Enhanced Connection Block* where connection blocks includes feedback connections Other features are used in naming should be listed here. diff --git a/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBr_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBr_40nm.xml new file mode 100644 index 000000000..4597207bb --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBr_40nm.xml @@ -0,0 +1,373 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + clb.clk + clb.I2[0:3] clb.I3[0:3] clb.O[2:3] + + clb.I0[0:3] clb.I1[0:3] clb.O[0:1] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124X_L12Y_ChanWidth0p8_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124X_L12Y_ChanWidth0p8_40nm.xml index 095a82096..038161627 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124X_L12Y_ChanWidth0p8_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124X_L12Y_ChanWidth0p8_40nm.xml @@ -136,7 +136,7 @@ - + diff --git a/requirements.txt b/requirements.txt index 889fe9159..502bfc8e0 100644 --- a/requirements.txt +++ b/requirements.txt @@ -5,5 +5,5 @@ pyverilog # Python linter and formatter click==8.0.2 # Our version of black needs an older version of click (https://stackoverflow.com/questions/71673404/importerror-cannot-import-name-unicodefun-from-click) -black==20.8b1 +black==24.3.0 pylint==2.7.4 diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index eb9722851..6e8ac62b7 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit eb9722851bd3de03df7fb9ace5bdfb9cb078ca83 +Subproject commit 6e8ac62b77bcfb30897b63a797d0726927bf2a21 diff --git a/yosys b/yosys index e9cd6ca9e..74a1dd99a 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit e9cd6ca9e8f9c8c729044e83811762ce13e84a12 +Subproject commit 74a1dd99ac0bc7355b5d8913bc4b7bb0160ddb1d