[Arch] Reduce the size of DPRAM in example architecture to accelerate testing
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tangxifan
parent
5c729657ef
commit
be98775ae5
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@ -1,279 +0,0 @@
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<!-- Architecture annotation for OpenFPGA framework
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This annotation supports the k6_N10_40nm.xml
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- General purpose logic block
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- K = 6, N = 10, I = 40
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- Single mode
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- Routing architecture
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- L = 4, fc_in = 0.15, fc_out = 0.1
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-->
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<openfpga_architecture>
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<technology_library>
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<device_library>
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<device_model name="logic" type="transistor">
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<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="0.9" pn_ratio="2"/>
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<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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</device_model>
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<device_model name="io" type="transistor">
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<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="2.5" pn_ratio="3"/>
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<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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</device_model>
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</device_library>
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<variation_library>
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<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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</variation_library>
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</technology_library>
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<circuit_library>
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<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
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<design_technology type="cmos" topology="inverter" size="1"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
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<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
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<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
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<design_technology type="cmos" topology="OR"/>
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<device_technology device_model_name="logic"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="a" size="1"/>
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<port type="input" prefix="b" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="a b" out_port="out">
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10e-12 5e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="a b" out_port="out">
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10e-12 5e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
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<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
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<device_technology device_model_name="logic"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="input" prefix="sel" size="1"/>
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<port type="input" prefix="selb" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in sel selb" out_port="out">
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10e-12 5e-12 5e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in sel selb" out_port="out">
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10e-12 5e-12 5e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
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</circuit_model>
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<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
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</circuit_model>
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<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
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<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
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<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="tap_buf4"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
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<design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="tap_buf4"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
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<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="D" size="1"/>
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<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
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<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="clock" prefix="clk" lib_name="CK" size="1"/>
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</circuit_model>
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<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
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<design_technology type="cmos" fracturable_lut="true"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
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<lut_input_buffer exist="true" circuit_model_name="buf4"/>
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<lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
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<port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
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<port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
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<port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
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<port type="sram" prefix="sram" size="64"/>
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<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
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</circuit_model>
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<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
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<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
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<port type="input" prefix="D" size="1"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="output" prefix="QN" size="1"/>
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<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
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</circuit_model>
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<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
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<port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
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<port type="input" prefix="outpad" lib_name="A" size="1"/>
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<port type="output" prefix="inpad" lib_name="Y" size="1"/>
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</circuit_model>
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<circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/adder.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="a" lib_name="A" size="1"/>
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<port type="input" prefix="b" lib_name="B" size="1"/>
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<port type="input" prefix="cin" lib_name="CI" size="1"/>
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<port type="output" prefix="sumout" lib_name="SUM" size="1"/>
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<port type="output" prefix="cout" lib_name="CO" size="1"/>
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</circuit_model>
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<circuit_model type="hard_logic" name="dpram_2048x8" prefix="dpram_2048x8" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dpram_2048x8.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="waddr" size="11"/>
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<port type="input" prefix="raddr" size="11"/>
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<port type="input" prefix="data_in" size="8"/>
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<port type="input" prefix="wen" size="1"/>
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<port type="input" prefix="ren" size="1"/>
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<port type="output" prefix="data_out" size="8"/>
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<port type="clock" prefix="clk" size="1"/>
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</circuit_model>
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</circuit_library>
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<configuration_protocol>
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<organization type="scan_chain" circuit_model_name="DFFR"/>
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</configuration_protocol>
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<connection_block>
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<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
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</connection_block>
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<switch_block>
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<switch name="0" circuit_model_name="mux_2level_tapbuf"/>
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</switch_block>
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<routing_segment>
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<segment name="L4" circuit_model_name="chan_segment"/>
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</routing_segment>
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<direct_connection>
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<direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
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</direct_connection>
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<tile_annotations>
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<global_port name="clk" is_clock="true" default_val="0">
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<tile name="clb" port="clk"/>
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<tile name="memory" port="clk"/>
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</global_port>
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</tile_annotations>
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<pb_type_annotations>
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<!-- physical pb_type binding in complex block IO -->
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<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
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<pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>
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<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
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<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
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<!-- End physical pb_type binding in complex block IO -->
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<!-- physical pb_type binding in complex block CLB -->
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<!-- physical mode will be the default mode if not specified -->
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<pb_type name="clb">
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<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
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<interconnect name="crossbar" circuit_model_name="mux_2level"/>
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</pb_type>
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<pb_type name="clb.fle" physical_mode_name="physical"/>
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<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
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<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
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<pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="ADDF"/>
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<!-- Binding operating pb_type to physical pb_type -->
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<!-- Binding operating pb_types in mode 'n2_lut5' -->
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<pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
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<!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
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<port name="in" physical_mode_port="in[0:4]"/>
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<port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
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</pb_type>
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<pb_type name="clb.fle[n2_lut5].ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
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<!-- Binding operating pb_types in mode 'arithmetic' -->
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<pb_type name="clb.fle[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
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<!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
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<port name="in" physical_mode_port="in[0:3]"/>
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<port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
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</pb_type>
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<pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
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<pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
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<!-- Binding operating pb_types in mode 'ble6' -->
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<pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="00">
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<!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
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<port name="in" physical_mode_port="in[0:5]"/>
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<port name="out" physical_mode_port="lut6_out"/>
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</pb_type>
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<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
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<!-- End physical pb_type binding in complex block clb -->
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<!-- physical pb_type binding in complex block memory -->
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<pb_type name="memory[mem_2048x8_dp].mem_2048x8_dp" circuit_model_name="dpram_2048x8"/>
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<!-- END physical pb_type binding in complex block memory -->
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</pb_type_annotations>
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</openfpga_architecture>
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@ -118,7 +118,7 @@
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<port name="lut6_out"/>
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</output_ports>
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</model>
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<model name="dpram_2048x8">
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<model name="dpram_128x8">
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<input_ports>
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<!-- write address lines -->
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<port name="waddr" clock="clk"/>
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@ -181,8 +181,8 @@
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<equivalent_sites>
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<site pb_type="memory"/>
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</equivalent_sites>
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<input name="waddr" num_pins="11"/>
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<input name="raddr" num_pins="11"/>
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<input name="waddr" num_pins="7"/>
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<input name="raddr" num_pins="7"/>
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<input name="data_in" num_pins="8"/>
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<input name="wen" num_pins="1"/>
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<input name="ren" num_pins="1"/>
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@ -194,9 +194,9 @@
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<pinlocations pattern="custom">
|
||||
<loc side="left" yoffset="0">memory.clk</loc>
|
||||
<loc side="top" yoffset="1"></loc>
|
||||
<loc side="right" yoffset="0">memory.wen memory.waddr[0:3] memory.raddr[0:3] memory.data_in[0:2] memory.data_out[0:2]</loc>
|
||||
<loc side="right" yoffset="1">memory.ren memory.waddr[4:7] memory.raddr[4:7] memory.data_in[3:5] memory.data_out[3:5]</loc>
|
||||
<loc side="bottom" yoffset="0">memory.waddr[8:10] memory.raddr[8:10] memory.data_in[6:7] memory.data_out[6:7]</loc>
|
||||
<loc side="right" yoffset="0">memory.wen memory.waddr[0:2] memory.raddr[0:2] memory.data_in[0:2] memory.data_out[0:2]</loc>
|
||||
<loc side="right" yoffset="1">memory.ren memory.waddr[3:5] memory.raddr[3:5] memory.data_in[3:5] memory.data_out[3:5]</loc>
|
||||
<loc side="bottom" yoffset="0">memory.waddr[6:6] memory.raddr[6:6] memory.data_in[6:7] memory.data_out[6:7]</loc>
|
||||
</pinlocations>
|
||||
</tile>
|
||||
</tiles>
|
||||
|
|
@ -691,57 +691,57 @@
|
|||
<!-- Define general purpose logic block (CLB) ends -->
|
||||
<!-- Define single-mode dual-port memory begin -->
|
||||
<pb_type name="memory">
|
||||
<input name="waddr" num_pins="11"/>
|
||||
<input name="raddr" num_pins="11"/>
|
||||
<input name="waddr" num_pins="7"/>
|
||||
<input name="raddr" num_pins="7"/>
|
||||
<input name="data_in" num_pins="8"/>
|
||||
<input name="wen" num_pins="1"/>
|
||||
<input name="ren" num_pins="1"/>
|
||||
<output name="data_out" num_pins="8"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Specify the 2048x8=16Kbit memory block
|
||||
<!-- Specify the 128x8=16Kbit memory block
|
||||
Note: the delay numbers are extracted from VPR flagship XML without modification
|
||||
Should align to the process technology we using to create the 16K dual-port RAM
|
||||
-->
|
||||
<mode name="mem_2048x8_dp">
|
||||
<pb_type name="mem_2048x8_dp" blif_model=".subckt dpram_2048x8" num_pb="1">
|
||||
<input name="waddr" num_pins="11" port_class="address1"/>
|
||||
<input name="raddr" num_pins="11" port_class="address2"/>
|
||||
<mode name="mem_128x8_dp">
|
||||
<pb_type name="mem_128x8_dp" blif_model=".subckt dpram_128x8" num_pb="1">
|
||||
<input name="waddr" num_pins="7" port_class="address1"/>
|
||||
<input name="raddr" num_pins="7" port_class="address2"/>
|
||||
<input name="data_in" num_pins="8" port_class="data_in1"/>
|
||||
<input name="wen" num_pins="1" port_class="write_en1"/>
|
||||
<input name="ren" num_pins="1" port_class="write_en2"/>
|
||||
<output name="data_out" num_pins="8" port_class="data_out1"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="509e-12" port="mem_2048x8_dp.waddr" clock="clk"/>
|
||||
<T_setup value="509e-12" port="mem_2048x8_dp.raddr" clock="clk"/>
|
||||
<T_setup value="509e-12" port="mem_2048x8_dp.data_in" clock="clk"/>
|
||||
<T_setup value="509e-12" port="mem_2048x8_dp.wen" clock="clk"/>
|
||||
<T_setup value="509e-12" port="mem_2048x8_dp.ren" clock="clk"/>
|
||||
<T_clock_to_Q max="1.234e-9" port="mem_2048x8_dp.data_out" clock="clk"/>
|
||||
<T_setup value="509e-12" port="mem_128x8_dp.waddr" clock="clk"/>
|
||||
<T_setup value="509e-12" port="mem_128x8_dp.raddr" clock="clk"/>
|
||||
<T_setup value="509e-12" port="mem_128x8_dp.data_in" clock="clk"/>
|
||||
<T_setup value="509e-12" port="mem_128x8_dp.wen" clock="clk"/>
|
||||
<T_setup value="509e-12" port="mem_128x8_dp.ren" clock="clk"/>
|
||||
<T_clock_to_Q max="1.234e-9" port="mem_128x8_dp.data_out" clock="clk"/>
|
||||
<power method="pin-toggle">
|
||||
<port name="clk" energy_per_toggle="17.9e-12"/>
|
||||
<static_power power_per_instance="0.0"/>
|
||||
</power>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="waddress" input="memory.waddr" output="mem_2048x8_dp.waddr">
|
||||
<delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_2048x8_dp.waddr"/>
|
||||
<direct name="waddress" input="memory.waddr" output="mem_128x8_dp.waddr">
|
||||
<delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_128x8_dp.waddr"/>
|
||||
</direct>
|
||||
<direct name="raddress" input="memory.raddr" output="mem_2048x8_dp.raddr">
|
||||
<delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_2048x8_dp.raddr"/>
|
||||
<direct name="raddress" input="memory.raddr" output="mem_128x8_dp.raddr">
|
||||
<delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_128x8_dp.raddr"/>
|
||||
</direct>
|
||||
<direct name="data_input" input="memory.data_in" output="mem_2048x8_dp.data_in">
|
||||
<delay_constant max="132e-12" in_port="memory.data_in" out_port="mem_2048x8_dp.data_in"/>
|
||||
<direct name="data_input" input="memory.data_in" output="mem_128x8_dp.data_in">
|
||||
<delay_constant max="132e-12" in_port="memory.data_in" out_port="mem_128x8_dp.data_in"/>
|
||||
</direct>
|
||||
<direct name="writeen" input="memory.wen" output="mem_2048x8_dp.wen">
|
||||
<delay_constant max="132e-12" in_port="memory.wen" out_port="mem_2048x8_dp.wen"/>
|
||||
<direct name="writeen" input="memory.wen" output="mem_128x8_dp.wen">
|
||||
<delay_constant max="132e-12" in_port="memory.wen" out_port="mem_128x8_dp.wen"/>
|
||||
</direct>
|
||||
<direct name="readen" input="memory.ren" output="mem_2048x8_dp.ren">
|
||||
<delay_constant max="132e-12" in_port="memory.ren" out_port="mem_2048x8_dp.ren"/>
|
||||
<direct name="readen" input="memory.ren" output="mem_128x8_dp.ren">
|
||||
<delay_constant max="132e-12" in_port="memory.ren" out_port="mem_128x8_dp.ren"/>
|
||||
</direct>
|
||||
<direct name="dataout" input="mem_2048x8_dp.data_out" output="memory.data_out">
|
||||
<delay_constant max="40e-12" in_port="mem_2048x8_dp.data_out" out_port="memory.data_out"/>
|
||||
<direct name="dataout" input="mem_128x8_dp.data_out" output="memory.data_out">
|
||||
<delay_constant max="40e-12" in_port="mem_128x8_dp.data_out" out_port="memory.data_out"/>
|
||||
</direct>
|
||||
<direct name="clk" input="memory.clk" output="mem_2048x8_dp.clk">
|
||||
<direct name="clk" input="memory.clk" output="mem_128x8_dp.clk">
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
|
|
@ -118,7 +118,7 @@
|
|||
<port name="lut6_out"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<model name="dpram_2048x8">
|
||||
<model name="dpram_128x8">
|
||||
<input_ports>
|
||||
<!-- write address lines -->
|
||||
<port name="waddr" clock="clk"/>
|
||||
|
|
@ -181,8 +181,8 @@
|
|||
<equivalent_sites>
|
||||
<site pb_type="memory"/>
|
||||
</equivalent_sites>
|
||||
<input name="waddr" num_pins="11"/>
|
||||
<input name="raddr" num_pins="11"/>
|
||||
<input name="waddr" num_pins="7"/>
|
||||
<input name="raddr" num_pins="7"/>
|
||||
<input name="data_in" num_pins="8"/>
|
||||
<input name="wen" num_pins="1"/>
|
||||
<input name="ren" num_pins="1"/>
|
||||
|
|
@ -192,13 +192,13 @@
|
|||
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
|
||||
</fc>
|
||||
<pinlocations pattern="custom">
|
||||
<loc side="left" yoffset="0">memory.clk memory.waddr[0:1] memory.raddr[0:1] memory.data_in[0:0] memory.data_out[0:0]</loc>
|
||||
<loc side="left" yoffset="1">memory.waddr[2:3] memory.raddr[2:3] memory.data_in[1:1] memory.data_out[1:1]</loc>
|
||||
<loc side="top" xoffset="0" yoffset="1">memory.waddr[4:5] memory.raddr[4:5] memory.data_in[2:2] memory.data_out[2:2]</loc>
|
||||
<loc side="top" xoffset="1" yoffset="1">memory.waddr[6:7] memory.raddr[6:7] memory.data_in[3:3] memory.data_out[3:3]</loc>
|
||||
<loc side="right" xoffset="1" yoffset="0">memory.waddr[8:8] memory.raddr[8:8] memory.data_in[4:4] memory.data_out[4:4]</loc>
|
||||
<loc side="right" xoffset="1" yoffset="1">memory.waddr[9:9] memory.raddr[9:9] memory.data_in[5:5] memory.data_out[5:5]</loc>
|
||||
<loc side="bottom" xoffset="0">memory.wen memory.waddr[10:10] memory.raddr[10:10] memory.data_in[6:6] memory.data_out[6:6]</loc>
|
||||
<loc side="left" yoffset="0">memory.clk memory.waddr[0:0] memory.raddr[0:0] memory.data_in[0:0] memory.data_out[0:0]</loc>
|
||||
<loc side="left" yoffset="1">memory.waddr[1:1] memory.raddr[1:1] memory.data_in[1:1] memory.data_out[1:1]</loc>
|
||||
<loc side="top" xoffset="0" yoffset="1">memory.waddr[2:2] memory.raddr[2:2] memory.data_in[2:2] memory.data_out[2:2]</loc>
|
||||
<loc side="top" xoffset="1" yoffset="1">memory.waddr[3:3] memory.raddr[3:3] memory.data_in[3:3] memory.data_out[3:3]</loc>
|
||||
<loc side="right" xoffset="1" yoffset="0">memory.waddr[4:4] memory.raddr[4:4] memory.data_in[4:4] memory.data_out[4:4]</loc>
|
||||
<loc side="right" xoffset="1" yoffset="1">memory.waddr[5:5] memory.raddr[5:5] memory.data_in[5:5] memory.data_out[5:5]</loc>
|
||||
<loc side="bottom" xoffset="0">memory.wen memory.waddr[5:5] memory.raddr[5:5] memory.data_in[6:6] memory.data_out[6:6]</loc>
|
||||
<loc side="bottom" xoffset="1">memory.ren memory.data_in[7:7] memory.data_out[7:7]</loc>
|
||||
</pinlocations>
|
||||
</tile>
|
||||
|
|
@ -694,57 +694,57 @@
|
|||
<!-- Define general purpose logic block (CLB) ends -->
|
||||
<!-- Define single-mode dual-port memory begin -->
|
||||
<pb_type name="memory">
|
||||
<input name="waddr" num_pins="11"/>
|
||||
<input name="raddr" num_pins="11"/>
|
||||
<input name="waddr" num_pins="7"/>
|
||||
<input name="raddr" num_pins="7"/>
|
||||
<input name="data_in" num_pins="8"/>
|
||||
<input name="wen" num_pins="1"/>
|
||||
<input name="ren" num_pins="1"/>
|
||||
<output name="data_out" num_pins="8"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Specify the 2048x8=16Kbit memory block
|
||||
<!-- Specify the 128x8=16Kbit memory block
|
||||
Note: the delay numbers are extracted from VPR flagship XML without modification
|
||||
Should align to the process technology we using to create the 16K dual-port RAM
|
||||
-->
|
||||
<mode name="mem_2048x8_dp">
|
||||
<pb_type name="mem_2048x8_dp" blif_model=".subckt dpram_2048x8" num_pb="1">
|
||||
<input name="waddr" num_pins="11" port_class="address1"/>
|
||||
<input name="raddr" num_pins="11" port_class="address2"/>
|
||||
<mode name="mem_128x8_dp">
|
||||
<pb_type name="mem_128x8_dp" blif_model=".subckt dpram_128x8" num_pb="1">
|
||||
<input name="waddr" num_pins="7" port_class="address1"/>
|
||||
<input name="raddr" num_pins="7" port_class="address2"/>
|
||||
<input name="data_in" num_pins="8" port_class="data_in1"/>
|
||||
<input name="wen" num_pins="1" port_class="write_en1"/>
|
||||
<input name="ren" num_pins="1" port_class="write_en2"/>
|
||||
<output name="data_out" num_pins="8" port_class="data_out1"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="509e-12" port="mem_2048x8_dp.waddr" clock="clk"/>
|
||||
<T_setup value="509e-12" port="mem_2048x8_dp.raddr" clock="clk"/>
|
||||
<T_setup value="509e-12" port="mem_2048x8_dp.data_in" clock="clk"/>
|
||||
<T_setup value="509e-12" port="mem_2048x8_dp.wen" clock="clk"/>
|
||||
<T_setup value="509e-12" port="mem_2048x8_dp.ren" clock="clk"/>
|
||||
<T_clock_to_Q max="1.234e-9" port="mem_2048x8_dp.data_out" clock="clk"/>
|
||||
<T_setup value="509e-12" port="mem_128x8_dp.waddr" clock="clk"/>
|
||||
<T_setup value="509e-12" port="mem_128x8_dp.raddr" clock="clk"/>
|
||||
<T_setup value="509e-12" port="mem_128x8_dp.data_in" clock="clk"/>
|
||||
<T_setup value="509e-12" port="mem_128x8_dp.wen" clock="clk"/>
|
||||
<T_setup value="509e-12" port="mem_128x8_dp.ren" clock="clk"/>
|
||||
<T_clock_to_Q max="1.234e-9" port="mem_128x8_dp.data_out" clock="clk"/>
|
||||
<power method="pin-toggle">
|
||||
<port name="clk" energy_per_toggle="17.9e-12"/>
|
||||
<static_power power_per_instance="0.0"/>
|
||||
</power>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="waddress" input="memory.waddr" output="mem_2048x8_dp.waddr">
|
||||
<delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_2048x8_dp.waddr"/>
|
||||
<direct name="waddress" input="memory.waddr" output="mem_128x8_dp.waddr">
|
||||
<delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_128x8_dp.waddr"/>
|
||||
</direct>
|
||||
<direct name="raddress" input="memory.raddr" output="mem_2048x8_dp.raddr">
|
||||
<delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_2048x8_dp.raddr"/>
|
||||
<direct name="raddress" input="memory.raddr" output="mem_128x8_dp.raddr">
|
||||
<delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_128x8_dp.raddr"/>
|
||||
</direct>
|
||||
<direct name="data_input" input="memory.data_in" output="mem_2048x8_dp.data_in">
|
||||
<delay_constant max="132e-12" in_port="memory.data_in" out_port="mem_2048x8_dp.data_in"/>
|
||||
<direct name="data_input" input="memory.data_in" output="mem_128x8_dp.data_in">
|
||||
<delay_constant max="132e-12" in_port="memory.data_in" out_port="mem_128x8_dp.data_in"/>
|
||||
</direct>
|
||||
<direct name="writeen" input="memory.wen" output="mem_2048x8_dp.wen">
|
||||
<delay_constant max="132e-12" in_port="memory.wen" out_port="mem_2048x8_dp.wen"/>
|
||||
<direct name="writeen" input="memory.wen" output="mem_128x8_dp.wen">
|
||||
<delay_constant max="132e-12" in_port="memory.wen" out_port="mem_128x8_dp.wen"/>
|
||||
</direct>
|
||||
<direct name="readen" input="memory.ren" output="mem_2048x8_dp.ren">
|
||||
<delay_constant max="132e-12" in_port="memory.ren" out_port="mem_2048x8_dp.ren"/>
|
||||
<direct name="readen" input="memory.ren" output="mem_128x8_dp.ren">
|
||||
<delay_constant max="132e-12" in_port="memory.ren" out_port="mem_128x8_dp.ren"/>
|
||||
</direct>
|
||||
<direct name="dataout" input="mem_2048x8_dp.data_out" output="memory.data_out">
|
||||
<delay_constant max="40e-12" in_port="mem_2048x8_dp.data_out" out_port="memory.data_out"/>
|
||||
<direct name="dataout" input="mem_128x8_dp.data_out" output="memory.data_out">
|
||||
<delay_constant max="40e-12" in_port="mem_128x8_dp.data_out" out_port="memory.data_out"/>
|
||||
</direct>
|
||||
<direct name="clk" input="memory.clk" output="mem_2048x8_dp.clk">
|
||||
<direct name="clk" input="memory.clk" output="mem_128x8_dp.clk">
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
Loading…
Reference in New Issue