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[FPGA-Verilog] Fix a bug on the polarity of reset signals that drive FPGA instances

This commit is contained in:
tangxifan 2022-02-14 17:16:26 -08:00
parent d3f68db228
commit be8f18310d
1 changed files with 6 additions and 1 deletions
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7
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
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@ -408,9 +408,14 @@ void print_verilog_top_testbench_global_reset_ports_stimuli(std::fstream& fp,
if ( (false == pin_constraints.unconstrained_net(constrained_net_name)) if ( (false == pin_constraints.unconstrained_net(constrained_net_name))
&& (false == pin_constraints.unmapped_net(constrained_net_name))) { && (false == pin_constraints.unmapped_net(constrained_net_name))) {
BasicPort benchmark_pin(constrained_net_name + std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX), 1); BasicPort benchmark_pin(constrained_net_name + std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX), 1);
/* Polarity of some input may have to be inverted, as defined in pin constraints
* For example, the reset signal of the benchmark is active low
* while the reset signal of the FPGA fabric is active high (inside FPGA, the reset signal will be inverted)
* However, to ensure correct stimuli to the benchmark, we have to invert the signal
*/
print_verilog_wire_connection(fp, module_global_pin, print_verilog_wire_connection(fp, module_global_pin,
benchmark_pin, benchmark_pin,
false); PinConstraints::LOGIC_HIGH == pin_constraints.net_default_value(constrained_net_name));
continue; /* Finish the net assignment for this reset pin */ continue; /* Finish the net assignment for this reset pin */
} }
} }