Merge pull request #660 from lnis-uofu/version

Now Version is in a separated file `VERSION.md`

.github/workflows/patch_updater.yml

@@ -6,6 +6,7 @@ on:
 
 env:
   TAG_COMMIT: 781ea3f..
+  VERSION_FILE: VERSION.md
   BRANCH_NAME: patch_update
 
 jobs:
@@ -28,10 +29,10 @@ jobs:
       - name: Insert Patch Count
         if: "!contains(steps.log.outputs.message, 'Updated Patch Count') && contains(steps.repo.outputs.message, 'lnis-uofu/OpenFPGA')"
         run: |
-          sed -i "/^set(OPENFPGA_VERSION_PATCH /s/[0-9]*)/`git log ${TAG_COMMIT}  --oneline | wc -l`)/" CMakeLists.txt
+          sed -i "s/[0-9]*$/`git log ${TAG_COMMIT}  --oneline | wc -l`/" ${VERSION_FILE}
           git config --local user.email "41898282+github-actions[bot]@users.noreply.github.com"
           git config --local user.name "github-actions[bot]"
-          git add CMakeLists.txt
+          git add ${VERSION_FILE}
           git commit -m "Updated Patch Count"
 
       - name: Push changes # push the output folder to your repo

CMakeLists.txt

@@ -51,9 +51,11 @@ set(VPR_USE_EZGL "auto" CACHE STRING "Specify whether vpr uses the graphics libr
 set_property(CACHE VPR_USE_EZGL PROPERTY STRINGS auto off on)
 
 # Version number
-set(OPENFPGA_VERSION_MAJOR 1)
-set(OPENFPGA_VERSION_MINOR 1)
-set(OPENFPGA_VERSION_PATCH 215)
+file (STRINGS "VERSION.md" VERSION_NUMBER)
+string (REPLACE "." ";" VERSION_LIST ${VERSION_NUMBER})
+list(GET VERSION_LIST 0 OPENFPGA_VERSION_MAJOR)
+list(GET VERSION_LIST 1 OPENFPGA_VERSION_MINOR)
+list(GET VERSION_LIST 2 OPENFPGA_VERSION_PATCH)
 set(OPENFPGA_VERSION_PRERELEASE "dev")
 
 # Include user-defined functions

README.md

@@ -3,6 +3,8 @@
 [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master)
 [![Binder](https://mybinder.org/badge_logo.svg)](https://mybinder.org/v2/gh/lnis-uofu/OpenFPGA/master?urlpath=vscode)
 
+Version: see [`VERSION.md`](VERSION.md)
+
 ## Introduction
 
 The award-winning OpenFPGA framework is the **first open-source FPGA IP generator** supporting highly-customizable homogeneous FPGA architectures. OpenFPGA provides complete EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers.

VERSION.md

@@ -0,0 +1 @@
+1.1.215

docs/source/VERSION.md

@@ -0,0 +1 @@
+../../VERSION.md

docs/source/conf.py

@@ -37,10 +37,10 @@ copyright = u'2018, Xifan Tang'
 author = u'Xifan Tang'
 
 # The short X.Y version
-version = u''
-# The full version, including alpha/beta/rc tags
-release = u'1.0'
-
+with open("VERSION.md") as ver_f:
+  version = ver_f.readline().rstrip()
+  # The full version, including alpha/beta/rc tags
+  release = version
 
 # -- General configuration ---------------------------------------------------