From be4643b8a6e8f7f2895aedf9b3cb874abbe23ff5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 10 May 2019 10:21:06 -0600 Subject: [PATCH] updated Verilog generator to use compact CBs and SBs. SPICE generator to be updated --- .../fpga_x2p/base/fpga_x2p_pbtypes_utils.h | 4 - .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 3 +- .../verilog/verilog_compact_netlist.c | 319 +++++++++++++++++- .../verilog/verilog_compact_netlist.h | 1 + .../SRC/fpga_x2p/verilog/verilog_routing.c | 70 ++-- .../SRC/fpga_x2p/verilog/verilog_routing.h | 9 +- 6 files changed, 377 insertions(+), 29 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h index 67f6ac6ef..05bcd003b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h @@ -113,8 +113,6 @@ t_pb* get_child_pb_for_phy_pb_graph_node(t_pb* cur_pb, int ipb, int jpb); t_phy_pb* get_phy_child_pb_for_phy_pb_graph_node(t_phy_pb* cur_phy_pb, int ipb, int jpb); -enum e_interconnect find_pb_graph_pin_in_edges_interc_type(t_pb_graph_pin pb_graph_pin) ; - t_spice_model* find_pb_graph_pin_in_edges_interc_model(t_pb_graph_pin pb_graph_pin) ; void find_interc_fan_in_des_pb_graph_pin(t_pb_graph_pin* des_pb_graph_pin, @@ -210,8 +208,6 @@ t_phy_pb* rec_get_phy_pb_by_name(t_phy_pb* cur_phy_pb, int get_pb_graph_node_wired_lut_logical_block_index(t_pb_graph_node* cur_pb_graph_node, t_rr_node* op_pb_rr_graph); -void rec_reset_pb_graph_node_rr_node_index_physical_pb(t_pb_graph_node* cur_pb_graph_node); - void sync_wired_lut_to_one_phy_pb(t_pb_graph_node* cur_pb_graph_node, t_phy_pb* cur_phy_pb, t_rr_node* op_pb_rr_graph); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index fd6641a1e..1d970690b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -253,7 +253,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, /* Dump routing resources: switch blocks, connection blocks and channel tracks */ dump_verilog_routing_resources(sram_verilog_orgz_info, src_dir_path, rr_dir_path, Arch, &vpr_setup.RoutingArch, num_rr_nodes, rr_node, rr_node_indices, rr_indexed_data, - vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts); + vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy); /* Dump logic blocks * Branches to go: @@ -274,6 +274,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, num_rr_nodes, rr_node, rr_node_indices, num_clocks, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, + vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy, *(Arch.spice)); /* Dump SDC constraints */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 5430be339..00aaa61f2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -35,6 +35,7 @@ #include "verilog_utils.h" #include "verilog_primitives.h" #include "verilog_pbtypes.h" +#include "verilog_routing.h" #include "verilog_top_netlist_utils.h" /* ONLY for compact Verilog netlists: @@ -739,6 +740,311 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info, return; } +/* Call the defined switch box sub-circuit + * TODO: This function is also copied from + * spice_routing.c : dump_verilog_routing_switch_box_subckt + */ +static +void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info, + FILE* fp, + t_sb cur_sb_info) { + int ix, iy, side, itrack, x, y, inode; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > cur_sb_info.x))&&(!(cur_sb_info.x > (nx + 1)))); + assert((!(0 > cur_sb_info.y))&&(!(cur_sb_info.y > (ny + 1)))); + + x = cur_sb_info.x; + y = cur_sb_info.y; + + /* Comment lines */ + fprintf(fp, "//----- BEGIN call module Switch blocks [%d][%d] -----\n", + cur_sb_info.x, cur_sb_info.y); + /* Print module*/ + + /* If we have an mirror SB, we should the module name of the mirror !!! */ + if (NULL != cur_sb_info.mirror) { + fprintf(fp, "%s ", gen_verilog_one_sb_module_name(cur_sb_info.mirror)); + } else { + fprintf(fp, "%s ", gen_verilog_one_sb_module_name(&cur_sb_info)); + } + + fprintf(fp, "%s ", gen_verilog_one_sb_instance_name(&cur_sb_info)); + fprintf(fp, "("); + + fprintf(fp, "\n"); + /* dump global ports */ + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + fprintf(fp, ",\n"); + } + + for (side = 0; side < cur_sb_info.num_sides; side++) { + determine_sb_port_coordinator(cur_sb_info, side, &ix, &iy); + + fprintf(fp, "//----- %s side channel ports-----\n", convert_side_index_to_string(side)); + for (itrack = 0; itrack < cur_sb_info.chan_width[side]; itrack++) { + fprintf(fp, "%s,\n", + gen_verilog_routing_channel_one_pin_name(cur_sb_info.chan_rr_node[side][itrack], + ix, iy, itrack, + cur_sb_info.chan_rr_node_direction[side][itrack])); + } + fprintf(fp, "//----- %s side inputs: CLB output pins -----\n", convert_side_index_to_string(side)); + /* Dump OPINs of adjacent CLBs */ + for (inode = 0; inode < cur_sb_info.num_opin_rr_nodes[side]; inode++) { + dump_verilog_grid_side_pin_with_given_index(fp, IPIN, + cur_sb_info.opin_rr_node[side][inode]->ptc_num, + cur_sb_info.opin_rr_node_grid_side[side][inode], + cur_sb_info.opin_rr_node[side][inode]->xlow, + cur_sb_info.opin_rr_node[side][inode]->ylow, + FALSE); /* Do not specify the direction of port */ + fprintf(fp, ", "); + } + fprintf(fp, "\n"); + } + + /* Configuration ports */ + /* output of each configuration bit */ + /* Reserved sram ports */ + if (0 < (cur_sb_info.num_reserved_conf_bits)) { + dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info, + 0, cur_sb_info.num_reserved_conf_bits - 1, + VERILOG_PORT_CONKT); + fprintf(fp, ",\n"); + } + /* Normal sram ports */ + if (0 < (cur_sb_info.conf_bits_msb - cur_sb_info.conf_bits_lsb)) { + dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, + cur_sb_info.conf_bits_lsb, + cur_sb_info.conf_bits_msb - 1, + VERILOG_PORT_CONKT); + } + + /* Dump ports only visible during formal verification*/ + if (0 < (cur_sb_info.conf_bits_msb - 1 - cur_sb_info.conf_bits_lsb)) { + fprintf(fp, "\n"); + fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag); + fprintf(fp, ",\n"); + dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, + cur_sb_info.conf_bits_lsb, + cur_sb_info.conf_bits_msb - 1, + VERILOG_PORT_CONKT); + fprintf(fp, "\n"); + fprintf(fp, "`endif\n"); + } + fprintf(fp, ");\n"); + + /* Comment lines */ + fprintf(fp, "//----- END call module Switch blocks [%d][%d] -----\n\n", x, y); + + /* Free */ + + return; +} + + +void dump_compact_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_info, + FILE* fp) { + int ix, iy; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 0; iy < (ny + 1); iy++) { + dump_compact_verilog_defined_one_switch_box(cur_sram_orgz_info, fp, sb_info[ix][iy]); + } + } + + return; +} + +/* Call the defined sub-circuit of connection box + * TODO: actually most of this function is copied from + * spice_routing.c : dump_verilog_conneciton_box_interc + * Should be more clever to use the original function + */ +static +void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_info, + FILE* fp, + t_cb cur_cb_info) { + int itrack, inode, side, x, y; + int side_cnt = 0; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert((!(0 > cur_cb_info.x))&&(!(cur_cb_info.x > (nx + 1)))); + assert((!(0 > cur_cb_info.y))&&(!(cur_cb_info.y > (ny + 1)))); + + x = cur_cb_info.x; + y = cur_cb_info.y; + + /* Comment lines */ + fprintf(fp, + "//----- BEGIN Call Connection Box for %s direction [%d][%d] module -----\n", + convert_chan_type_to_string(cur_cb_info.type), + x, y); + + /* Print module */ + /* If we have an mirror SB, we should the module name of the mirror !!! */ + if (NULL != cur_cb_info.mirror) { + fprintf(fp, "%s ", gen_verilog_one_cb_module_name(cur_cb_info.mirror)); + } else { + fprintf(fp, "%s ", gen_verilog_one_cb_module_name(&cur_cb_info)); + } + + fprintf(fp, "%s ", gen_verilog_one_cb_instance_name(&cur_cb_info)); + + fprintf(fp, "("); + fprintf(fp, "\n"); + /* dump global ports */ + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + fprintf(fp, ",\n"); + } + + /* Print the ports of channels*/ + /* connect to the mid point of a track*/ + side_cnt = 0; + for (side = 0; side < cur_cb_info.num_sides; side++) { + /* Bypass side with zero channel width */ + if (0 == cur_cb_info.chan_width[side]) { + continue; + } + assert (0 < cur_cb_info.chan_width[side]); + side_cnt++; + fprintf(fp, "//----- %s side inputs: channel track middle outputs -----\n", convert_side_index_to_string(side)); + for (itrack = 0; itrack < cur_cb_info.chan_width[side]; itrack++) { + fprintf(fp, "%s, ", + gen_verilog_routing_channel_one_midout_name(&cur_cb_info, itrack)); + fprintf(fp, "\n"); + } + } + /*check side_cnt */ + assert(1 == side_cnt); + + side_cnt = 0; + /* Print the ports of grids*/ + for (side = 0; side < cur_cb_info.num_sides; side++) { + /* Bypass side with zero IPINs*/ + if (0 == cur_cb_info.num_ipin_rr_nodes[side]) { + continue; + } + side_cnt++; + assert(0 < cur_cb_info.num_ipin_rr_nodes[side]); + assert(NULL != cur_cb_info.ipin_rr_node[side]); + fprintf(fp, "//----- %s side outputs: CLB input pins -----\n", convert_side_index_to_string(side)); + for (inode = 0; inode < cur_cb_info.num_ipin_rr_nodes[side]; inode++) { + /* Print each INPUT Pins of a grid */ + dump_verilog_grid_side_pin_with_given_index(fp, OPIN, + cur_cb_info.ipin_rr_node[side][inode]->ptc_num, + cur_cb_info.ipin_rr_node_grid_side[side][inode], + cur_cb_info.ipin_rr_node[side][inode]->xlow, + cur_cb_info.ipin_rr_node[side][inode]->ylow, + FALSE); /* Do not specify direction of port */ + fprintf(fp, ", \n"); + } + } + /* Make sure only 2 sides of IPINs are printed */ + assert((1 == side_cnt)||(2 == side_cnt)); + + /* Configuration ports */ + /* Reserved sram ports */ + if (0 < (cur_cb_info.num_reserved_conf_bits)) { + dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info, + 0, cur_cb_info.num_reserved_conf_bits - 1, + VERILOG_PORT_CONKT); + fprintf(fp, ",\n"); + } + /* Normal sram ports */ + if (0 < (cur_cb_info.conf_bits_msb - cur_cb_info.conf_bits_lsb)) { + dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, + cur_cb_info.conf_bits_lsb, cur_cb_info.conf_bits_msb - 1, + VERILOG_PORT_CONKT); + } + /* Dump ports only visible during formal verification*/ + if (0 < (cur_cb_info.conf_bits_msb - 1 - cur_cb_info.conf_bits_lsb)) { + fprintf(fp, "\n"); + fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag); + fprintf(fp, ",\n"); + dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, + cur_cb_info.conf_bits_lsb, + cur_cb_info.conf_bits_msb - 1, + VERILOG_PORT_CONKT); + fprintf(fp, "\n"); + fprintf(fp, "`endif\n"); + } + fprintf(fp, ");\n"); + + /* Comment lines */ + switch(cur_cb_info.type) { + case CHANX: + fprintf(fp, "//----- END call Connection Box-X direction [%d][%d] module -----\n\n", x, y); + break; + case CHANY: + fprintf(fp, "//----- END call Connection Box-Y direction [%d][%d] module -----\n\n", x, y); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((1 == side_cnt)||(2 == side_cnt)); + + return; +} + +/* Call the sub-circuits for connection boxes */ +void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info, + FILE* fp) { + int ix, iy; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* X - channels [1...nx][0..ny]*/ + for (iy = 0; iy < (ny + 1); iy++) { + for (ix = 1; ix < (nx + 1); ix++) { + if ((TRUE == is_cb_exist(CHANX, ix, iy)) + &&(0 < count_cb_info_num_ipin_rr_nodes(cbx_info[ix][iy]))) { + dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, cbx_info[ix][iy]); + } + } + } + /* Y - channels [1...ny][0..nx]*/ + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + if ((TRUE == is_cb_exist(CHANY, ix, iy)) + &&(0 < count_cb_info_num_ipin_rr_nodes(cby_info[ix][iy]))) { + dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, cby_info[ix][iy]); + } + } + } + + return; +} + + + /** Print Top-level SPICE netlist in a compact way * Instance unique submodules (I/O, CLB, Heterogeneous block) for the full grids */ @@ -754,6 +1060,7 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, t_ivec*** LL_rr_node_indices, int num_clock, t_syn_verilog_opts fpga_verilog_opts, + boolean compact_routing_hierarchy, t_spice verilog) { FILE* fp = NULL; char* formatted_dir_path = NULL; @@ -809,10 +1116,18 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_defined_channels(fp, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); /* Quote Routing structures: Switch Boxes */ - dump_verilog_defined_switch_boxes(cur_sram_orgz_info, fp); + if (TRUE == compact_routing_hierarchy ) { + dump_compact_verilog_defined_switch_boxes(cur_sram_orgz_info, fp); + } else { + dump_verilog_defined_switch_boxes(cur_sram_orgz_info, fp); + } /* Quote Routing structures: Connection Boxes */ - dump_verilog_defined_connection_boxes(cur_sram_orgz_info, fp); + if (TRUE == compact_routing_hierarchy ) { + dump_compact_verilog_defined_connection_boxes(cur_sram_orgz_info, fp); + } else { + dump_verilog_defined_connection_boxes(cur_sram_orgz_info, fp); + } /* Quote defined Logic blocks subckts (Grids) */ dump_compact_verilog_defined_grids(cur_sram_orgz_info, fp); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h index e74cd8432..34d63b540 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h @@ -24,5 +24,6 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, t_ivec*** LL_rr_node_indices, int num_clock, t_syn_verilog_opts fpga_verilog_opts, + boolean compact_routing_hierarchy, t_spice verilog); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index c51e8ebaa..e198d751a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -1107,7 +1107,8 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info t_sb* cur_sb_info, int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, - t_syn_verilog_opts fpga_verilog_opts) { + t_syn_verilog_opts fpga_verilog_opts, + boolean compact_routing_hierarchy) { int itrack, inode, side, ix, iy, x, y; int cur_num_sram, num_conf_bits, num_reserved_conf_bits, esti_sram_cnt; FILE* fp = NULL; @@ -1131,6 +1132,20 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info cur_sb_info->num_reserved_conf_bits = num_reserved_conf_bits; cur_sb_info->conf_bits_lsb = cur_num_sram; cur_sb_info->conf_bits_msb = cur_num_sram + num_conf_bits; + + /* Handle mirror switch blocks: + * For mirrors, no need to output a file + * Just update the counter + */ + if ( (TRUE == compact_routing_hierarchy) + && (NULL != cur_sb_info->mirror) ) { + /* Again ensure the conf_bits should match !!! */ + /* Count the number of configuration bits of the mirror */ + int mirror_num_conf_bits = count_verilog_switch_box_conf_bits(cur_sram_orgz_info, cur_sb_info->mirror); + assert( mirror_num_conf_bits == num_conf_bits ); + /* return directly */ + return; + } /* Create file handler */ fp = verilog_create_one_subckt_file(subckt_dir, "Switch Block ", sb_verilog_file_name_prefix, cur_sb_info->x, cur_sb_info->y, &fname); @@ -1755,7 +1770,8 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ t_cb* cur_cb_info, int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, - t_syn_verilog_opts fpga_verilog_opts) { + t_syn_verilog_opts fpga_verilog_opts, + boolean compact_routing_hierarchy) { int itrack, inode, side, x, y; int side_cnt = 0; FILE* fp = NULL; @@ -1768,7 +1784,34 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ x= cur_cb_info->x; y= cur_cb_info->y; - + + /* Count the number of configuration bits */ + /* Count the number of configuration bits to be consumed by this Switch block */ + num_conf_bits = count_verilog_connection_box_conf_bits(cur_sram_orgz_info, cur_cb_info); + /* Count the number of reserved configuration bits to be consumed by this Switch block */ + num_reserved_conf_bits = count_verilog_connection_box_reserved_conf_bits(cur_sram_orgz_info, cur_cb_info); + /* Estimate the sram_verilog_model->cnt */ + cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); + esti_sram_cnt = cur_num_sram + num_conf_bits; + /* Record index */ + cur_cb_info->num_reserved_conf_bits = num_reserved_conf_bits; + cur_cb_info->conf_bits_lsb = cur_num_sram; + cur_cb_info->conf_bits_msb = cur_num_sram + num_conf_bits; + + /* Handle mirror switch blocks: + * For mirrors, no need to output a file + * Just update the counter + */ + if ( (TRUE == compact_routing_hierarchy) + && (NULL != cur_cb_info->mirror) ) { + /* Again ensure the conf_bits should match !!! */ + /* Count the number of configuration bits of the mirror */ + int mirror_num_conf_bits = count_verilog_connection_box_conf_bits(cur_sram_orgz_info, cur_cb_info->mirror); + assert( mirror_num_conf_bits == num_conf_bits ); + /* return directly */ + return; + } + /* Print the definition of subckt*/ /* Identify the type of connection box */ switch(cur_cb_info->type) { @@ -1850,18 +1893,6 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ /* Make sure only 2 sides of IPINs are printed */ assert((1 == side_cnt)||(2 == side_cnt)); - /* Count the number of configuration bits */ - /* Count the number of configuration bits to be consumed by this Switch block */ - num_conf_bits = count_verilog_connection_box_conf_bits(cur_sram_orgz_info, cur_cb_info); - /* Count the number of reserved configuration bits to be consumed by this Switch block */ - num_reserved_conf_bits = count_verilog_connection_box_reserved_conf_bits(cur_sram_orgz_info, cur_cb_info); - /* Estimate the sram_verilog_model->cnt */ - cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); - esti_sram_cnt = cur_num_sram + num_conf_bits; - /* Record index */ - cur_cb_info->num_reserved_conf_bits = num_reserved_conf_bits; - cur_cb_info->conf_bits_lsb = cur_num_sram; - cur_cb_info->conf_bits_msb = cur_num_sram + num_conf_bits; /* Put down configuration port */ /* output of each configuration bit */ @@ -1956,7 +1987,8 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, t_rr_indexed_data* LL_rr_indexed_data, - t_syn_verilog_opts fpga_verilog_opts) { + t_syn_verilog_opts fpga_verilog_opts, + boolean compact_routing_hierarchy) { int ix, iy; assert(UNI_DIRECTIONAL == routing_arch->directionality); @@ -2005,7 +2037,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, update_spice_models_routing_index_low(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models); dump_verilog_routing_switch_box_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, &(sb_info[ix][iy]), LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, - fpga_verilog_opts); + fpga_verilog_opts, compact_routing_hierarchy); update_spice_models_routing_index_high(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models); } } @@ -2020,7 +2052,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, &&(0 < count_cb_info_num_ipin_rr_nodes(cbx_info[ix][iy]))) { dump_verilog_routing_connection_box_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, &(cbx_info[ix][iy]), LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, - fpga_verilog_opts); + fpga_verilog_opts, compact_routing_hierarchy); } update_spice_models_routing_index_high(ix, iy, CHANX, arch.spice->num_spice_model, arch.spice->spice_models); } @@ -2034,7 +2066,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, &&(0 < count_cb_info_num_ipin_rr_nodes(cby_info[ix][iy]))) { dump_verilog_routing_connection_box_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, &(cby_info[ix][iy]), LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, - fpga_verilog_opts); + fpga_verilog_opts, compact_routing_hierarchy); } update_spice_models_routing_index_high(ix, iy, CHANY, arch.spice->num_spice_model, arch.spice->spice_models); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h index 6f02a5f88..d72953085 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h @@ -67,7 +67,8 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info t_sb* cur_sb_info, int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, - t_syn_verilog_opts fpga_verilog_opts); + t_syn_verilog_opts fpga_verilog_opts, + boolean compact_routing_hierarchy); void dump_verilog_connection_box_short_interc(t_sram_orgz_info* cur_sram_orgz_info, @@ -111,7 +112,8 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ t_cb* cur_cb_info, int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, - t_syn_verilog_opts fpga_verilog_opts); + t_syn_verilog_opts fpga_verilog_opts, + boolean compact_routing_hierarchy); void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, @@ -122,5 +124,6 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, t_rr_indexed_data* LL_rr_indexed_data, - t_syn_verilog_opts fpga_verilog_opts); + t_syn_verilog_opts fpga_verilog_opts, + boolean compact_routing_hierarchy);