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[core] format

This commit is contained in:
tangxifan 2023-06-18 21:18:35 -07:00
parent cef573529d
commit bdda695cc0
3 changed files with 12 additions and 11 deletions
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7
openfpga/src/fpga_verilog/verilog_top_module.cpp
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@ -32,7 +32,8 @@ void print_verilog_core_module(NetlistManager& netlist_manager,
*/
std::string core_module_name = generate_fpga_core_module_name();
ModuleId core_module = module_manager.find_module(core_module_name);
/* It could happen that the module does not exist, just return with no errors */
/* It could happen that the module does not exist, just return with no errors
*/
if (!module_manager.valid_module_id(core_module)) {
return;
}
@ -52,8 +53,8 @@ void print_verilog_core_module(NetlistManager& netlist_manager,
check_file_stream(verilog_fpath.c_str(), fp);
print_verilog_file_header(
fp, std::string("Wrapper Verilog module for FPGA"), options.time_stamp());
print_verilog_file_header(fp, std::string("Wrapper Verilog module for FPGA"),
options.time_stamp());
/* Write the module content in Verilog format */
write_verilog_module_to_file(fp, module_manager, core_module,