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bug fix in top-level testbench for frame-based decoders

This commit is contained in:
tangxifan 2020-05-28 18:34:18 -06:00
parent 986956e474
commit bdc9efb38f
1 changed files with 2 additions and 2 deletions
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4
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
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@ -598,7 +598,7 @@ void print_verilog_top_testbench_load_bitstream_task_frame_decoder(std::fstream&
/* Add an empty line as splitter */ /* Add an empty line as splitter */
fp << std::endl; fp << std::endl;
/* Feed the address and data input at each rising edge of programming clock /* Feed the address and data input at each falling edge of programming clock
* As the enable signal is wired to the programming clock, we should synchronize * As the enable signal is wired to the programming clock, we should synchronize
* address and data with the enable signal * address and data with the enable signal
*/ */
@ -607,7 +607,7 @@ void print_verilog_top_testbench_load_bitstream_task_frame_decoder(std::fstream&
fp << generate_verilog_port(VERILOG_PORT_INPUT, addr_value) << ";" << std::endl; fp << generate_verilog_port(VERILOG_PORT_INPUT, addr_value) << ";" << std::endl;
fp << generate_verilog_port(VERILOG_PORT_INPUT, din_value) << ";" << std::endl; fp << generate_verilog_port(VERILOG_PORT_INPUT, din_value) << ";" << std::endl;
fp << "\tbegin" << std::endl; fp << "\tbegin" << std::endl;
fp << "\t\t@(posedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl; fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
fp << "\t\t\t"; fp << "\t\t\t";
fp << generate_verilog_port(VERILOG_PORT_CONKT, addr_port); fp << generate_verilog_port(VERILOG_PORT_CONKT, addr_port);