riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[arch] update arch files

This commit is contained in:
tangxifan 2022-08-22 18:24:37 -07:00
parent 6c44f321e5
commit bdb051f787
55 changed files with 29354 additions and 29409 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
openfpga_flow/vpr_arch/k4_N4_tileableIO_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Architecture with no fracturable LUTs
- 40 nm technology
@ -12,8 +12,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -35,7 +34,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -46,8 +45,8 @@
<loc side="top">io.outpad</loc>
<loc side="right">io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -56,7 +55,7 @@
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

13
openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Architecture with no fracturable LUTs
- 40 nm technology
@ -12,8 +12,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -35,7 +34,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -48,8 +47,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -58,7 +57,7 @@
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

13
openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Architecture with no fracturable LUTs
- 40 nm technology
@ -13,8 +13,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -36,7 +35,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -49,8 +48,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -61,7 +60,7 @@
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
</fc>
<pinlocations pattern="spread"/>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

13
openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile8Clk_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Architecture with no fracturable LUTs
- 40 nm technology
@ -13,8 +13,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -36,7 +35,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -49,8 +48,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -61,7 +60,7 @@
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
</fc>
<pinlocations pattern="spread"/>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

13
openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Architecture with no fracturable LUTs
- 40 nm technology
@ -12,8 +12,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -35,7 +34,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -48,8 +47,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -60,7 +59,7 @@
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
</fc>
<pinlocations pattern="spread"/>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

13
openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Architecture with no fracturable LUTs
- 40 nm technology
@ -12,8 +12,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -35,7 +34,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -51,8 +50,8 @@
<loc side="right">io.outpad io.inpad io.clk</loc>
<loc side="bottom">io.outpad io.inpad io.clk</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -63,7 +62,7 @@
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
</fc>
<pinlocations pattern="spread"/>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

17
openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzBr_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Architecture with no fracturable LUTs
- 40 nm technology
@ -12,8 +12,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -35,7 +34,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -48,8 +47,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -58,12 +57,12 @@
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="left"></loc>
<loc side="top"></loc>
<loc side="left"/>
<loc side="top"/>
<loc side="right">clb.I[5:9] clb.O[2:3]</loc>
<loc side="bottom">clb.clk clb.I[0:4] clb.O[0:1]</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

17
openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Architecture with no fracturable LUTs
- 40 nm technology
@ -12,8 +12,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -35,7 +34,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -48,8 +47,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -60,10 +59,10 @@
<pinlocations pattern="custom">
<loc side="top">clb.clk clb.I[0:4] clb.O[0:1]</loc>
<loc side="left">clb.I[5:9] clb.O[2:3]</loc>
<loc side="right"></loc>
<loc side="bottom"></loc>
<loc side="right"/>
<loc side="bottom"/>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

17
openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTr_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Architecture with no fracturable LUTs
- 40 nm technology
@ -12,8 +12,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -35,7 +34,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -48,8 +47,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -58,12 +57,12 @@
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="left"></loc>
<loc side="left"/>
<loc side="top">clb.clk clb.I[0:4] clb.O[0:1]</loc>
<loc side="right">clb.I[5:9] clb.O[2:3]</loc>
<loc side="bottom"></loc>
<loc side="bottom"/>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

19
openfpga_flow/vpr_arch/k4_N4_tileable_dsp8reg_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Architecture with no fracturable LUTs
- 40 nm technology
@ -15,8 +15,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -47,7 +46,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -60,8 +59,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -70,8 +69,8 @@
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
</tile>
<tile name="mult_8" height="2" area="396000">
</sub_tile> </tile>
<tile name="mult_8" height="2" area="396000"> <sub_tile name="mult_8">
<equivalent_sites>
<site pb_type="mult_8" pin_mapping="direct"/>
</equivalent_sites>
@ -86,9 +85,9 @@
<loc side="left">mult_8.a[0:3] mult_8.b[0:3] mult_8.out[0:7]</loc>
<loc side="top">mult_8.clk</loc>
<loc side="right">mult_8.a[4:7] mult_8.b[4:7] mult_8.out[8:15]</loc>
<loc side="bottom"></loc>
<loc side="bottom"/>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

13
openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Architecture with no fracturable LUTs
- 40 nm technology
@ -13,8 +13,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -36,7 +35,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -49,8 +48,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -59,7 +58,7 @@
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

13
openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Architecture with no fracturable LUTs
- 40 nm technology
@ -13,8 +13,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -36,7 +35,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -49,8 +48,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -62,7 +61,7 @@
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

13
openfpga_flow/vpr_arch/k4_N5_tileable_pattern_local_routing_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Architecture with no fracturable LUTs
- 40 nm technology
@ -12,8 +12,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -35,7 +34,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -48,8 +47,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -58,7 +57,7 @@
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

13
openfpga_flow/vpr_arch/k4_fracNative_N4_tileable_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
- 40 nm technology
@ -12,8 +12,7 @@
Based on flagship k4_frac_N4_mem32K_40nm.xml architecture.
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -49,7 +48,7 @@
If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end
-->
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -62,8 +61,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -72,7 +71,7 @@
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

13
openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
- 40 nm technology
@ -12,8 +12,7 @@
Based on flagship k4_frac_N4_mem32K_40nm.xml architecture.
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -49,7 +48,7 @@
If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end
-->
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -62,8 +61,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -72,7 +71,7 @@
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

13
openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
- 40 nm technology
@ -12,8 +12,7 @@
Based on flagship k4_frac_N4_mem32K_40nm.xml architecture.
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -49,7 +48,7 @@
If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end
-->
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -62,8 +61,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -72,7 +71,7 @@
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

13
openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
- 40 nm technology
@ -12,8 +12,7 @@
Based on flagship k4_frac_N4_mem32K_40nm.xml architecture.
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -60,7 +59,7 @@
If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end
-->
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -73,8 +72,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -94,7 +93,7 @@
<loc side="right">clb.O[3:0] clb.I[5:0]</loc>
<loc side="bottom">clb.cout clb.O[7:4] clb.I[11:6]</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

17
openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
- 40 nm technology
@ -12,8 +12,7 @@
Based on flagship k4_frac_N4_mem32K_40nm.xml architecture.
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -80,7 +79,7 @@
If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end
-->
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -93,8 +92,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -114,8 +113,8 @@
<loc side="right">clb.O[3:0] clb.I[5:0]</loc>
<loc side="bottom">clb.cout clb.O[7:4] clb.I[11:6]</loc>
</pinlocations>
</tile>
<tile name="memory" height="2" area="548000">
</sub_tile> </tile>
<tile name="memory" height="2" area="548000"> <sub_tile name="memory">
<equivalent_sites>
<site pb_type="memory"/>
</equivalent_sites>
@ -128,7 +127,7 @@
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

17
openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
- 40 nm technology
@ -15,8 +15,7 @@
Based on flagship k4_frac_N4_mem32K_40nm.xml architecture.
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -83,7 +82,7 @@
If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end
-->
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -96,8 +95,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -117,8 +116,8 @@
<loc side="right">clb.O[3:0] clb.I[5:0]</loc>
<loc side="bottom">clb.cout clb.O[7:4] clb.I[11:6]</loc>
</pinlocations>
</tile>
<tile name="memory" height="2" area="548000">
</sub_tile> </tile>
<tile name="memory" height="2" area="548000"> <sub_tile name="memory">
<equivalent_sites>
<site pb_type="memory"/>
</equivalent_sites>
@ -131,7 +130,7 @@
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.25" out_type="frac" out_val="0.20"/>
<pinlocations pattern="spread"/>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

21
openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_frac_dsp32_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
- 40 nm technology
@ -17,8 +17,7 @@
Based on flagship k4_frac_N4_mem32K_40nm.xml architecture.
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -94,7 +93,7 @@
If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end
-->
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -107,8 +106,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -128,8 +127,8 @@
<loc side="right">clb.O[3:0] clb.I[5:0]</loc>
<loc side="bottom">clb.cout clb.O[7:4] clb.I[11:6]</loc>
</pinlocations>
</tile>
<tile name="memory" height="2" area="548000">
</sub_tile> </tile>
<tile name="memory" height="2" area="548000"> <sub_tile name="memory">
<equivalent_sites>
<site pb_type="memory"/>
</equivalent_sites>
@ -142,8 +141,8 @@
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
</tile>
<tile name="mult_32" height="4" area="396000">
</sub_tile> </tile>
<tile name="mult_32" height="4" area="396000"> <sub_tile name="mult_32">
<equivalent_sites>
<site pb_type="mult_32" pin_mapping="direct"/>
</equivalent_sites>
@ -159,7 +158,7 @@
<loc side="right">mult_32.a[0:15] mult_32.b[0:15] mult_32.out[0:31]</loc>
<loc side="bottom">mult_32.a[16:31] mult_32.b[16:31] mult_32.out[32:63]</loc>
</pinlocations-->
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

13
openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff2edge_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
- 40 nm technology
@ -8,8 +8,7 @@
- Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
Authors: Xifan Tang
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -109,7 +108,7 @@
If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end
-->
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -122,8 +121,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -136,7 +135,7 @@
<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
</fc>
<pinlocations pattern="spread"/>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

13
openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
- 40 nm technology
@ -8,8 +8,7 @@
- Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
Authors: Xifan Tang
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -77,7 +76,7 @@
If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end
-->
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -90,8 +89,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -104,7 +103,7 @@
<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
</fc>
<pinlocations pattern="spread"/>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

15
openfpga_flow/vpr_arch/k4_frac_N4_tileable_lutram_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
- 40 nm technology
@ -13,8 +13,7 @@
Based on flagship k4_frac_N4_mem32K_40nm.xml architecture.
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -61,7 +60,7 @@
If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end
-->
<tile name="io" capacity="1" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -74,8 +73,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -86,11 +85,11 @@
<!--pinlocations pattern="spread"/-->
<pinlocations pattern="custom">
<loc side="left">clb.clk</loc>
<loc side="top"></loc>
<loc side="top"/>
<loc side="right">clb.O[3:0] clb.I[5:0]</loc>
<loc side="bottom">clb.O[7:4] clb.I[11:6]</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

25
openfpga_flow/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Low-cost homogeneous FPGA Architecture.
- Skywater 130 nm technology
@ -12,8 +12,7 @@
- 100 routing tracks per channel
Authors: Xifan Tang
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -61,7 +60,7 @@
These clocks can be handled in back-end
-->
<!-- Top-side has 1 I/O per tile -->
<tile name="io_top" capacity="1" area="0">
<tile name="io_top" area="0"> <sub_tile name="io_top" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -71,9 +70,9 @@
<pinlocations pattern="custom">
<loc side="bottom">io_top.outpad io_top.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- Right-side has 1 I/O per tile -->
<tile name="io_right" capacity="1" area="0">
<tile name="io_right" area="0"> <sub_tile name="io_right" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -83,9 +82,9 @@
<pinlocations pattern="custom">
<loc side="left">io_right.outpad io_right.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- Bottom-side has 6 I/O per tile -->
<tile name="io_bottom" capacity="6" area="0">
<tile name="io_bottom" area="0"> <sub_tile name="io_bottom" capacity="6">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -95,9 +94,9 @@
<pinlocations pattern="custom">
<loc side="top">io_bottom.outpad io_bottom.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- Left-side has 1 I/O per tile -->
<tile name="io_left" capacity="1" area="0">
<tile name="io_left" area="0"> <sub_tile name="io_left" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -107,9 +106,9 @@
<pinlocations pattern="custom">
<loc side="right">io_left.outpad io_left.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- CLB has most pins on the top and right sides -->
<tile name="clb" area="53894">
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -148,7 +147,7 @@
<loc side="right">clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc>
<loc side="bottom">clb.regout clb.scout </loc>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

17
openfpga_flow/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Low-cost homogeneous FPGA Architecture.
- Skywater 130 nm technology
@ -12,8 +12,7 @@
- 100 routing tracks per channel
Authors: Xifan Tang
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -51,7 +50,7 @@
If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end
-->
<tile name="gp_inpad" capacity="8" area="0">
<tile name="gp_inpad" area="0"> <sub_tile name="gp_inpad" capacity="8">
<equivalent_sites>
<site pb_type="gp_inpad"/>
</equivalent_sites>
@ -63,8 +62,8 @@
<loc side="right">gp_inpad.inpad</loc>
<loc side="bottom">gp_inpad.inpad</loc>
</pinlocations>
</tile>
<tile name="gp_outpad" capacity="8" area="0">
</sub_tile> </tile>
<tile name="gp_outpad" area="0"> <sub_tile name="gp_outpad" capacity="8">
<equivalent_sites>
<site pb_type="gp_outpad"/>
</equivalent_sites>
@ -76,8 +75,8 @@
<loc side="right">gp_outpad.outpad</loc>
<loc side="bottom">gp_outpad.outpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -116,7 +115,7 @@
<loc side="right">clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i </loc>
<loc side="bottom">clb.regout clb.scout clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

25
openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Low-cost homogeneous FPGA Architecture.
- Skywater 130 nm technology
@ -12,8 +12,7 @@
- 100 routing tracks per channel
Authors: Xifan Tang
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -62,7 +61,7 @@
These clocks can be handled in back-end
-->
<!-- Top-side has 1 I/O per tile -->
<tile name="io_top" capacity="1" area="0">
<tile name="io_top" area="0"> <sub_tile name="io_top" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -72,9 +71,9 @@
<pinlocations pattern="custom">
<loc side="bottom">io_top.outpad io_top.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- Right-side has 1 I/O per tile -->
<tile name="io_right" capacity="1" area="0">
<tile name="io_right" area="0"> <sub_tile name="io_right" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -84,9 +83,9 @@
<pinlocations pattern="custom">
<loc side="left">io_right.outpad io_right.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- Bottom-side has 9 I/O per tile -->
<tile name="io_bottom" capacity="9" area="0">
<tile name="io_bottom" area="0"> <sub_tile name="io_bottom" capacity="9">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -96,9 +95,9 @@
<pinlocations pattern="custom">
<loc side="top">io_bottom.outpad io_bottom.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- Left-side has 1 I/O per tile -->
<tile name="io_left" capacity="1" area="0">
<tile name="io_left" area="0"> <sub_tile name="io_left" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -108,9 +107,9 @@
<pinlocations pattern="custom">
<loc side="right">io_left.outpad io_left.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- CLB has most pins on the top and right sides -->
<tile name="clb" area="53894">
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -152,7 +151,7 @@
<loc side="right">clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc>
<loc side="bottom">clb.reg_out clb.sc_out</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

25
openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Low-cost homogeneous FPGA Architecture.
- Skywater 130 nm technology
@ -12,8 +12,7 @@
- 100 routing tracks per channel
Authors: Xifan Tang
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -73,7 +72,7 @@
These clocks can be handled in back-end
-->
<!-- Top-side has 1 I/O per tile -->
<tile name="io_top" capacity="1" area="0">
<tile name="io_top" area="0"> <sub_tile name="io_top" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -83,9 +82,9 @@
<pinlocations pattern="custom">
<loc side="bottom">io_top.outpad io_top.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- Right-side has 1 I/O per tile -->
<tile name="io_right" capacity="1" area="0">
<tile name="io_right" area="0"> <sub_tile name="io_right" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -95,9 +94,9 @@
<pinlocations pattern="custom">
<loc side="left">io_right.outpad io_right.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- Bottom-side has 9 I/O per tile -->
<tile name="io_bottom" capacity="9" area="0">
<tile name="io_bottom" area="0"> <sub_tile name="io_bottom" capacity="9">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -107,9 +106,9 @@
<pinlocations pattern="custom">
<loc side="top">io_bottom.outpad io_bottom.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- Left-side has 1 I/O per tile -->
<tile name="io_left" capacity="1" area="0">
<tile name="io_left" area="0"> <sub_tile name="io_left" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -119,9 +118,9 @@
<pinlocations pattern="custom">
<loc side="right">io_left.outpad io_left.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- CLB has most pins on the top and right sides -->
<tile name="clb" area="53894">
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -167,7 +166,7 @@
<loc side="right">clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc>
<loc side="bottom">clb.reg_out clb.sc_out clb.cout</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

33
openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Low-cost homogeneous FPGA Architecture.
- Skywater 130 nm technology
@ -14,8 +14,7 @@
- 100 routing tracks per channel
Authors: Xifan Tang
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -102,7 +101,7 @@
These clocks can be handled in back-end
-->
<!-- Top-side has 1 I/O per tile -->
<tile name="io_top" capacity="1" area="0">
<tile name="io_top" area="0"> <sub_tile name="io_top" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -112,9 +111,9 @@
<pinlocations pattern="custom">
<loc side="bottom">io_top.outpad io_top.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- Right-side has 1 I/O per tile -->
<tile name="io_right" capacity="1" area="0">
<tile name="io_right" area="0"> <sub_tile name="io_right" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -124,9 +123,9 @@
<pinlocations pattern="custom">
<loc side="left">io_right.outpad io_right.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- Bottom-side has 9 I/O per tile -->
<tile name="io_bottom" capacity="9" area="0">
<tile name="io_bottom" area="0"> <sub_tile name="io_bottom" capacity="9">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -136,9 +135,9 @@
<pinlocations pattern="custom">
<loc side="top">io_bottom.outpad io_bottom.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- Left-side has 1 I/O per tile -->
<tile name="io_left" capacity="1" area="0">
<tile name="io_left" area="0"> <sub_tile name="io_left" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -148,9 +147,9 @@
<pinlocations pattern="custom">
<loc side="right">io_left.outpad io_left.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- CLB has most pins on the top and right sides -->
<tile name="clb" area="53894">
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -196,8 +195,8 @@
<loc side="right">clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc>
<loc side="bottom">clb.reg_out clb.sc_out clb.cout</loc>
</pinlocations>
</tile>
<tile name="mult_8" height="2" area="396000">
</sub_tile> </tile>
<tile name="mult_8" height="2" area="396000"> <sub_tile name="mult_8">
<equivalent_sites>
<site pb_type="mult_8" pin_mapping="direct"/>
</equivalent_sites>
@ -208,13 +207,13 @@
<!-- Highly recommand to customize pin location when direct connection is used!!! -->
<!--pinlocations pattern="spread"/-->
<pinlocations pattern="custom">
<loc side="left"></loc>
<loc side="top"></loc>
<loc side="left"/>
<loc side="top"/>
<loc side="right" yoffset="0">mult_8.a[0:2] mult_8.b[0:2] mult_8.out[0:5]</loc>
<loc side="right" yoffset="1">mult_8.a[3:5] mult_8.b[3:5] mult_8.out[6:10]</loc>
<loc side="bottom">mult_8.a[6:7] mult_8.b[6:7] mult_8.out[11:15]</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

29
openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Low-cost homogeneous FPGA Architecture.
- Skywater 130 nm technology
@ -14,8 +14,7 @@
- 100 routing tracks per channel
Authors: Xifan Tang
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -111,7 +110,7 @@
These clocks can be handled in back-end
-->
<!-- Top-side has 1 I/O per tile -->
<tile name="io_top" capacity="9" area="0">
<tile name="io_top" area="0"> <sub_tile name="io_top" capacity="9">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -121,9 +120,9 @@
<pinlocations pattern="custom">
<loc side="bottom">io_top.outpad io_top.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- Right-side has 1 I/O per tile -->
<tile name="io_right" capacity="9" area="0">
<tile name="io_right" area="0"> <sub_tile name="io_right" capacity="9">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -133,9 +132,9 @@
<pinlocations pattern="custom">
<loc side="left">io_right.outpad io_right.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- Bottom-side has 9 I/O per tile -->
<tile name="io_bottom" capacity="9" area="0">
<tile name="io_bottom" area="0"> <sub_tile name="io_bottom" capacity="9">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -145,9 +144,9 @@
<pinlocations pattern="custom">
<loc side="top">io_bottom.outpad io_bottom.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- Left-side has 1 I/O per tile -->
<tile name="io_left" capacity="9" area="0">
<tile name="io_left" area="0"> <sub_tile name="io_left" capacity="9">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -157,9 +156,9 @@
<pinlocations pattern="custom">
<loc side="right">io_left.outpad io_left.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- CLB has most pins on the top and right sides -->
<tile name="clb" area="53894">
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -205,8 +204,8 @@
<loc side="right">clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc>
<loc side="bottom">clb.reg_out clb.sc_out clb.cout</loc>
</pinlocations>
</tile>
<tile name="mult_16" height="2" area="396000">
</sub_tile> </tile>
<tile name="mult_16" height="2" area="396000"> <sub_tile name="mult_16">
<equivalent_sites>
<site pb_type="mult_16" pin_mapping="direct"/>
</equivalent_sites>
@ -224,7 +223,7 @@
<loc side="right" yoffset="1">mult_16.a[11:13] mult_16.b[11:13] mult_16.out[22:26]</loc>
<loc side="bottom">mult_16.a[14:15] mult_16.b[14:15] mult_16.out[27:31]</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

25
openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Low-cost homogeneous FPGA Architecture.
- Skywater 130 nm technology
@ -12,8 +12,7 @@
- 100 routing tracks per channel
Authors: Xifan Tang
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -91,7 +90,7 @@
These clocks can be handled in back-end
-->
<!-- Top-side has 1 I/O per tile -->
<tile name="io_top" capacity="1" area="0">
<tile name="io_top" area="0"> <sub_tile name="io_top" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -101,9 +100,9 @@
<pinlocations pattern="custom">
<loc side="bottom">io_top.outpad io_top.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- Right-side has 1 I/O per tile -->
<tile name="io_right" capacity="1" area="0">
<tile name="io_right" area="0"> <sub_tile name="io_right" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -113,9 +112,9 @@
<pinlocations pattern="custom">
<loc side="left">io_right.outpad io_right.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- Bottom-side has 9 I/O per tile -->
<tile name="io_bottom" capacity="9" area="0">
<tile name="io_bottom" area="0"> <sub_tile name="io_bottom" capacity="9">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -125,9 +124,9 @@
<pinlocations pattern="custom">
<loc side="top">io_bottom.outpad io_bottom.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- Left-side has 1 I/O per tile -->
<tile name="io_left" capacity="1" area="0">
<tile name="io_left" area="0"> <sub_tile name="io_left" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -137,9 +136,9 @@
<pinlocations pattern="custom">
<loc side="right">io_left.outpad io_left.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- CLB has most pins on the top and right sides -->
<tile name="clb" area="53894">
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -185,7 +184,7 @@
<loc side="right">clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc>
<loc side="bottom">clb.reg_out clb.sc_out clb.cout</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

29
openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_wide_frac_dsp16_nonLR_caravel_io_skywater130nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Low-cost homogeneous FPGA Architecture.
- Skywater 130 nm technology
@ -14,8 +14,7 @@
- 100 routing tracks per channel
Authors: Xifan Tang
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -111,7 +110,7 @@
These clocks can be handled in back-end
-->
<!-- Top-side has 1 I/O per tile -->
<tile name="io_top" capacity="9" area="0">
<tile name="io_top" area="0"> <sub_tile name="io_top" capacity="9">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -121,9 +120,9 @@
<pinlocations pattern="custom">
<loc side="bottom">io_top.outpad io_top.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- Right-side has 1 I/O per tile -->
<tile name="io_right" capacity="9" area="0">
<tile name="io_right" area="0"> <sub_tile name="io_right" capacity="9">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -133,9 +132,9 @@
<pinlocations pattern="custom">
<loc side="left">io_right.outpad io_right.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- Bottom-side has 9 I/O per tile -->
<tile name="io_bottom" capacity="9" area="0">
<tile name="io_bottom" area="0"> <sub_tile name="io_bottom" capacity="9">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -145,9 +144,9 @@
<pinlocations pattern="custom">
<loc side="top">io_bottom.outpad io_bottom.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- Left-side has 1 I/O per tile -->
<tile name="io_left" capacity="9" area="0">
<tile name="io_left" area="0"> <sub_tile name="io_left" capacity="9">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -157,9 +156,9 @@
<pinlocations pattern="custom">
<loc side="right">io_left.outpad io_left.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- CLB has most pins on the top and right sides -->
<tile name="clb" area="53894">
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -205,8 +204,8 @@
<loc side="right">clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc>
<loc side="bottom">clb.reg_out clb.sc_out clb.cout</loc>
</pinlocations>
</tile>
<tile name="mult_16" height="2" width="2" area="396000">
</sub_tile> </tile>
<tile name="mult_16" height="2" width="2" area="396000"> <sub_tile name="mult_16">
<equivalent_sites>
<site pb_type="mult_16" pin_mapping="direct"/>
</equivalent_sites>
@ -226,7 +225,7 @@
<loc side="bottom" xoffset="0">mult_16.a[12:13] mult_16.b[12:13] mult_16.out[24:27]</loc>
<loc side="bottom" xoffset="1">mult_16.a[14:15] mult_16.b[14:15] mult_16.out[28:31]</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

13
openfpga_flow/vpr_arch/k6_N10_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Architecture with no fracturable LUTs
- 40 nm technology
@ -12,8 +12,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -35,7 +34,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -48,8 +47,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -58,7 +57,7 @@
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

13
openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Architecture with no fracturable LUTs
- 40 nm technology
@ -12,8 +12,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -35,7 +34,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -48,8 +47,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -58,7 +57,7 @@
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

13
openfpga_flow/vpr_arch/k6_frac_N10_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
- 40 nm technology
@ -12,8 +12,7 @@
Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -49,7 +48,7 @@
If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end
-->
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -62,8 +61,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -72,7 +71,7 @@
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

13
openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
- 40 nm technology
@ -75,8 +75,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -120,7 +119,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -133,8 +132,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -155,7 +154,7 @@
<loc side="right">clb.O[9:0] clb.I[19:0]</loc>
<loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

19
openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
- 40 nm technology
@ -75,8 +75,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -140,7 +139,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -153,8 +152,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -175,8 +174,8 @@
<loc side="right">clb.O[9:0] clb.I[19:0]</loc>
<loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
</pinlocations>
</tile>
<tile name="memory" height="2" area="548000">
</sub_tile> </tile>
<tile name="memory" height="2" area="548000"> <sub_tile name="memory">
<equivalent_sites>
<site pb_type="memory"/>
</equivalent_sites>
@ -190,12 +189,12 @@
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="left" yoffset="0">memory.clk</loc>
<loc side="top" yoffset="1"></loc>
<loc side="top" yoffset="1"/>
<loc side="right" yoffset="0">memory.wen memory.waddr[0:3] memory.raddr[0:3] memory.data_in[0:2] memory.data_out[0:2]</loc>
<loc side="right" yoffset="1">memory.ren memory.waddr[4:7] memory.raddr[4:7] memory.data_in[3:5] memory.data_out[3:5]</loc>
<loc side="bottom" yoffset="0">memory.waddr[8:11] memory.raddr[8:11] memory.data_in[6:7] memory.data_out[6:7]</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

13
openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
- 40 nm technology
@ -12,8 +12,7 @@
Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -49,7 +48,7 @@
If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end
-->
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -62,8 +61,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -72,7 +71,7 @@
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

13
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
- 40 nm technology
@ -75,8 +75,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -120,7 +119,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -133,8 +132,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -155,7 +154,7 @@
<loc side="right">clb.O[9:0] clb.I[19:0]</loc>
<loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

27
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
- 40 nm technology
@ -75,8 +75,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -149,7 +148,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -162,8 +161,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -184,8 +183,8 @@
<loc side="right">clb.O[9:0] clb.I[19:0]</loc>
<loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
</pinlocations>
</tile>
<tile name="memory" height="2" area="548000">
</sub_tile> </tile>
<tile name="memory" height="2" area="548000"> <sub_tile name="memory">
<equivalent_sites>
<site pb_type="memory"/>
</equivalent_sites>
@ -200,12 +199,12 @@
<!--pinlocations pattern="spread"/-->
<pinlocations pattern="custom">
<loc side="left">memory.clk</loc>
<loc side="top"></loc>
<loc side="top"/>
<loc side="right">memory.waddr[4:0] memory.raddr[4:0] memory.data_in[3:0] memory.wen memory.data_out[3:0]</loc>
<loc side="bottom">memory.waddr[9:5] memory.raddr[9:5] memory.data_in[7:4] memory.ren memory.data_out[7:4]</loc>
</pinlocations>
</tile>
<tile name="mult_36" height="6" area="396000">
</sub_tile> </tile>
<tile name="mult_36" height="6" area="396000"> <sub_tile name="mult_36">
<equivalent_sites>
<site pb_type="mult_36" pin_mapping="direct"/>
</equivalent_sites>
@ -217,11 +216,11 @@
<!-- pinlocations are designed to spread pin on 4 sides evenly -->
<pinlocations pattern="custom">
<loc side="left">mult_36.b[0:9] mult_36.b[10:35] mult_36.out[36:71]</loc>
<loc side="top"></loc>
<loc side="top"/>
<loc side="right">mult_36.a[0:9] mult_36.a[10:35] mult_36.out[0:35]</loc>
<loc side="bottom"></loc>
<loc side="bottom"/>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

27
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
- 40 nm technology
@ -75,8 +75,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -210,7 +209,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -223,8 +222,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -250,8 +249,8 @@
<loc side="right">clb.O[9:0] clb.I[19:0]</loc>
<loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
</pinlocations>
</tile>
<tile name="memory" height="2" area="548000">
</sub_tile> </tile>
<tile name="memory" height="2" area="548000"> <sub_tile name="memory">
<equivalent_sites>
<site pb_type="memory"/>
</equivalent_sites>
@ -268,12 +267,12 @@
<!--pinlocations pattern="spread"/-->
<pinlocations pattern="custom">
<loc side="left">memory.clk</loc>
<loc side="top"></loc>
<loc side="top"/>
<loc side="right">memory.waddr[4:0] memory.raddr[4:0] memory.data_in[3:0] memory.wen memory.data_out[3:0]</loc>
<loc side="bottom">memory.waddr[9:5] memory.raddr[9:5] memory.data_in[7:4] memory.ren memory.data_out[7:4]</loc>
</pinlocations>
</tile>
<tile name="mult_36" height="6" area="396000">
</sub_tile> </tile>
<tile name="mult_36" height="6" area="396000"> <sub_tile name="mult_36">
<equivalent_sites>
<site pb_type="mult_36" pin_mapping="direct"/>
</equivalent_sites>
@ -285,11 +284,11 @@
<!-- pinlocations are designed to spread pin on 4 sides evenly -->
<pinlocations pattern="custom">
<loc side="left">mult_36.b[0:9] mult_36.b[10:35] mult_36.out[36:71]</loc>
<loc side="top"></loc>
<loc side="top"/>
<loc side="right">mult_36.a[0:9] mult_36.a[10:35] mult_36.out[0:35]</loc>
<loc side="bottom"></loc>
<loc side="bottom"/>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

27
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
- 40 nm technology
@ -84,8 +84,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -179,7 +178,7 @@
</models>
<tiles>
<!-- The original XML does have a default capacity (=1). Set 8 here for best architecture evaluation -->
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io" pin_mapping="direct"/>
</equivalent_sites>
@ -192,8 +191,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb" pin_mapping="direct"/>
</equivalent_sites>
@ -214,8 +213,8 @@
<loc side="right">clb.O[9:0] clb.I[19:0]</loc>
<loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
</pinlocations>
</tile>
<tile name="mult_36" height="4" area="396000">
</sub_tile> </tile>
<tile name="mult_36" height="4" area="396000"> <sub_tile name="mult_36">
<equivalent_sites>
<site pb_type="mult_36" pin_mapping="direct"/>
</equivalent_sites>
@ -226,13 +225,13 @@
<!-- Highly recommand to customize pin location when direct connection is used!!! -->
<!--pinlocations pattern="spread"/-->
<pinlocations pattern="custom">
<loc side="left"></loc>
<loc side="top"></loc>
<loc side="left"/>
<loc side="top"/>
<loc side="right">mult_36.a[0:17] mult_36.b[0:17] mult_36.out[0:35]</loc>
<loc side="bottom">mult_36.a[18:35] mult_36.b[18:35] mult_36.out[36:71]</loc>
</pinlocations>
</tile>
<tile name="memory" height="6" area="548000">
</sub_tile> </tile>
<tile name="memory" height="6" area="548000"> <sub_tile name="memory">
<equivalent_sites>
<site pb_type="memory" pin_mapping="direct"/>
</equivalent_sites>
@ -247,12 +246,12 @@
<!-- Highly recommand to customize pin location when direct connection is used!!! -->
<!--pinlocations pattern="spread"/-->
<pinlocations pattern="custom">
<loc side="left"></loc>
<loc side="left"/>
<loc side="top">memory.clk</loc>
<loc side="right">memory.addr1[0:14] memory.data[0:31] memory.we1 memory.out[0:31]</loc>
<loc side="bottom">memory.addr2[0:14] memory.data[32:63] memory.we2 memory.out[32:63]</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

27
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_GlobalTile8Clk_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
- 40 nm technology
@ -84,8 +84,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -179,7 +178,7 @@
</models>
<tiles>
<!-- The original XML does have a default capacity (=1). Set 8 here for best architecture evaluation -->
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io" pin_mapping="direct"/>
</equivalent_sites>
@ -192,8 +191,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb" pin_mapping="direct"/>
</equivalent_sites>
@ -215,8 +214,8 @@
<loc side="right">clb.O[9:0] clb.I[19:0]</loc>
<loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
</pinlocations>
</tile>
<tile name="mult_36" height="4" area="396000">
</sub_tile> </tile>
<tile name="mult_36" height="4" area="396000"> <sub_tile name="mult_36">
<equivalent_sites>
<site pb_type="mult_36" pin_mapping="direct"/>
</equivalent_sites>
@ -227,13 +226,13 @@
<!-- Highly recommand to customize pin location when direct connection is used!!! -->
<!--pinlocations pattern="spread"/-->
<pinlocations pattern="custom">
<loc side="left"></loc>
<loc side="top"></loc>
<loc side="left"/>
<loc side="top"/>
<loc side="right">mult_36.a[0:17] mult_36.b[0:17] mult_36.out[0:35]</loc>
<loc side="bottom">mult_36.a[18:35] mult_36.b[18:35] mult_36.out[36:71]</loc>
</pinlocations>
</tile>
<tile name="memory" height="6" area="548000">
</sub_tile> </tile>
<tile name="memory" height="6" area="548000"> <sub_tile name="memory">
<equivalent_sites>
<site pb_type="memory" pin_mapping="direct"/>
</equivalent_sites>
@ -250,12 +249,12 @@
<!-- Highly recommand to customize pin location when direct connection is used!!! -->
<!--pinlocations pattern="spread"/-->
<pinlocations pattern="custom">
<loc side="left"></loc>
<loc side="left"/>
<loc side="top">memory.clk</loc>
<loc side="right">memory.addr1[0:14] memory.data[0:31] memory.we1 memory.out[0:31]</loc>
<loc side="bottom">memory.addr2[0:14] memory.data[32:63] memory.we2 memory.out[32:63]</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

21
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
- 40 nm technology
@ -75,8 +75,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -152,7 +151,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -165,13 +164,13 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- A mini AIB interface to be located at the right side of the FPGA
All the port will be accessible to the left side of the tile
TODO: add full control signals
TODO: add analog bus ports to the right side which should be GPIOs
-->
<tile name="aib" width="1" height="4" area="0">
<tile name="aib" width="1" height="4" area="0"> <sub_tile name="aib">
<equivalent_sites>
<site pb_type="aib"/>
</equivalent_sites>
@ -183,8 +182,8 @@
<pinlocations pattern="custom">
<loc side="left">aib.tx_clk aib.tx_data aib.rx_clk aib.rx_data</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -205,8 +204,8 @@
<loc side="right">clb.O[9:0] clb.I[19:0]</loc>
<loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
</pinlocations>
</tile>
<tile name="memory" height="2" area="548000">
</sub_tile> </tile>
<tile name="memory" height="2" area="548000"> <sub_tile name="memory">
<equivalent_sites>
<site pb_type="memory"/>
</equivalent_sites>
@ -219,7 +218,7 @@
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

29
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
- 40 nm technology
@ -75,8 +75,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -140,7 +139,7 @@
</model>
</models>
<tiles>
<tile name="io_top" capacity="3" area="0">
<tile name="io_top" area="0"> <sub_tile name="io_top" capacity="3">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -150,8 +149,8 @@
<pinlocations pattern="custom">
<loc side="bottom">io_top.outpad io_top.inpad</loc>
</pinlocations>
</tile>
<tile name="io_right" capacity="2" area="0">
</sub_tile> </tile>
<tile name="io_right" area="0"> <sub_tile name="io_right" capacity="2">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -161,8 +160,8 @@
<pinlocations pattern="custom">
<loc side="left">io_right.outpad io_right.inpad</loc>
</pinlocations>
</tile>
<tile name="io_bottom" capacity="1" area="0">
</sub_tile> </tile>
<tile name="io_bottom" area="0"> <sub_tile name="io_bottom" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -172,8 +171,8 @@
<pinlocations pattern="custom">
<loc side="top">io_bottom.outpad io_bottom.inpad</loc>
</pinlocations>
</tile>
<tile name="io_left" capacity="4" area="0">
</sub_tile> </tile>
<tile name="io_left" area="0"> <sub_tile name="io_left" capacity="4">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -183,9 +182,9 @@
<pinlocations pattern="custom">
<loc side="right">io_left.outpad io_left.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<tile name="clb" area="53894">
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -206,8 +205,8 @@
<loc side="right">clb.O[9:0] clb.I[19:0]</loc>
<loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
</pinlocations>
</tile>
<tile name="memory" height="2" area="548000">
</sub_tile> </tile>
<tile name="memory" height="2" area="548000"> <sub_tile name="memory">
<equivalent_sites>
<site pb_type="memory"/>
</equivalent_sites>
@ -220,7 +219,7 @@
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

17
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
- 40 nm technology
@ -75,8 +75,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -140,7 +139,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -153,8 +152,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -175,8 +174,8 @@
<loc side="right">clb.O[9:0] clb.I[19:0]</loc>
<loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
</pinlocations>
</tile>
<tile name="memory" height="2" area="548000">
</sub_tile> </tile>
<tile name="memory" height="2" area="548000"> <sub_tile name="memory">
<equivalent_sites>
<site pb_type="memory"/>
</equivalent_sites>
@ -189,7 +188,7 @@
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

19
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem1K_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
- 40 nm technology
@ -75,8 +75,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -140,7 +139,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -153,8 +152,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -176,8 +175,8 @@
<loc side="right">clb.O[9:0] clb.I[19:0]</loc>
<loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
</pinlocations>
</tile>
<tile name="memory" height="2" area="548000">
</sub_tile> </tile>
<tile name="memory" height="2" area="548000"> <sub_tile name="memory">
<equivalent_sites>
<site pb_type="memory"/>
</equivalent_sites>
@ -193,12 +192,12 @@
</fc>
<pinlocations pattern="custom">
<loc side="left" yoffset="0">memory.clk</loc>
<loc side="top" yoffset="1"></loc>
<loc side="top" yoffset="1"/>
<loc side="right" yoffset="0">memory.wen memory.waddr[0:2] memory.raddr[0:2] memory.data_in[0:2] memory.data_out[0:2]</loc>
<loc side="right" yoffset="1">memory.ren memory.waddr[3:5] memory.raddr[3:5] memory.data_in[3:5] memory.data_out[3:5]</loc>
<loc side="bottom" yoffset="0">memory.waddr[6:6] memory.raddr[6:6] memory.data_in[6:7] memory.data_out[6:7]</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

17
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem1K_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
- 40 nm technology
@ -75,8 +75,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -140,7 +139,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -153,8 +152,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -176,8 +175,8 @@
<loc side="right">clb.O[9:0] clb.I[19:0]</loc>
<loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
</pinlocations>
</tile>
<tile name="memory" height="2" width="2" area="548000">
</sub_tile> </tile>
<tile name="memory" height="2" width="2" area="548000"> <sub_tile name="memory">
<equivalent_sites>
<site pb_type="memory"/>
</equivalent_sites>
@ -201,7 +200,7 @@
<loc side="bottom" xoffset="0">memory.wen memory.waddr[6:6] memory.raddr[6:6] memory.data_in[6:6] memory.data_out[6:6]</loc>
<loc side="bottom" xoffset="1">memory.ren memory.data_in[7:7] memory.data_out[7:7]</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

13
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
- 40 nm technology
@ -75,8 +75,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -120,7 +119,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -133,8 +132,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -159,7 +158,7 @@
<loc side="right">clb.O[9:0] clb.I[19:0]</loc>
<loc side="bottom">clb.cout clb.regout clb.O[19:10] clb.I[39:20]</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

13
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
- 40 nm technology
@ -75,8 +75,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -131,7 +130,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -144,8 +143,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -174,7 +173,7 @@
<loc side="right">clb.O[9:0] clb.I[19:0]</loc>
<loc side="bottom">clb.cout clb.regout clb.scout clb.O[19:10] clb.I[39:20]</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

15
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
View File

@ -1,11 +1,10 @@
<!-- Homogeneous FPGA Architecture with Carry Chain for VPR8
<?xml version="1.0" ?><!-- Homogeneous FPGA Architecture with Carry Chain for VPR8
- The chip layout is organized with a 2x2 array of Configurable Logic Blocks (CLBs)
surrounded by a ring of I/Os
- [TODO] Delay numbers are extracted from a 12 nm technology
Author: Xifan Tang, Aurelien Alacchi and Ganesh Gore
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -73,7 +72,7 @@
make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-->
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -89,12 +88,12 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- Each CLB tile includes a Configurable Logic Block (CLB)
Each input of the tile can be driven by 15% of routing tracks
Each output of the tile can drive 10% of routing tracks
-->
<tile name="clb" area="53894">
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -129,12 +128,12 @@
Top side pins are mainly for direct connections
-->
<pinlocations pattern="custom">
<loc side="left"></loc>
<loc side="left"/>
<loc side="top">clb.sc_in clb.cin clb.cin_trick clb.regin clb.clk</loc>
<loc side="right">clb.I0[9:0] clb.I1[9:0] clb.O[9:0]</loc>
<loc side="bottom">clb.cout clb.cout_copy clb.sc_out clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10]</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

21
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml
View File

@ -1,11 +1,10 @@
<!-- Homogeneous FPGA Architecture with Carry Chain for VPR8
<?xml version="1.0" ?><!-- Homogeneous FPGA Architecture with Carry Chain for VPR8
- The chip layout is organized with a 2x2 array of Configurable Logic Blocks (CLBs)
surrounded by a ring of I/Os
- [TODO] Delay numbers are extracted from a 12 nm technology
Author: Xifan Tang, Aurelien Alacchi and Ganesh Gore
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -73,7 +72,7 @@
make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-->
<tile name="io" capacity="1" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -89,12 +88,12 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- Each CLB tile includes a Configurable Logic Block (CLB)
Each input of the tile can be driven by 15% of routing tracks
Each output of the tile can drive 10% of routing tracks
-->
<tile name="clb" area="53894">
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -129,17 +128,17 @@
Top side pins are mainly for direct connections
-->
<pinlocations pattern="custom">
<loc side="left"></loc>
<loc side="left"/>
<loc side="top">clb.sc_in clb.cin clb.cin_trick clb.regin clb.clk</loc>
<loc side="right">clb.I0[9:0] clb.I1[9:0] clb.O[9:0]</loc>
<loc side="bottom">clb.cout clb.cout_copy clb.sc_out clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10]</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- Each CLB tile with spypads includes a Configurable Logic Block (CLB) with spypads
Each input of the tile can be driven by 15% of routing tracks
Each output of the tile can drive 10% of routing tracks
-->
<tile name="clb_spypad" area="53894">
<tile name="clb_spypad" area="53894"> <sub_tile name="clb_spypad">
<equivalent_sites>
<site pb_type="clb_spypad"/>
</equivalent_sites>
@ -174,12 +173,12 @@
Top side pins are mainly for direct connections
-->
<pinlocations pattern="custom">
<loc side="left"></loc>
<loc side="left"/>
<loc side="top">clb_spypad.sc_in clb_spypad.cin clb_spypad.cin_trick clb_spypad.regin clb_spypad.clk</loc>
<loc side="right">clb_spypad.I0[9:0] clb_spypad.I1[9:0] clb_spypad.O[9:0]</loc>
<loc side="bottom">clb_spypad.cout clb_spypad.cout_copy clb_spypad.sc_out clb_spypad.regout clb_spypad.I2[9:0] clb_spypad.I3[9:0] clb_spypad.O[19:10]</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

21
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml
View File

@ -1,4 +1,4 @@
<!-- Heterogeneous FPGA Architecture with Carry Chain for VPR8
<?xml version="1.0" ?><!-- Heterogeneous FPGA Architecture with Carry Chain for VPR8
- The chip layout is organized with a 32x32 array of Configurable Logic Blocks (CLBs)
surrounded by a ring of I/Os
@ -7,8 +7,7 @@
Process corner: TT 0.8V
Author: Xifan Tang, Aurelien Alacchi and Ganesh Gore
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -96,7 +95,7 @@
make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-->
<tile name="io" capacity="1" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="1">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -112,12 +111,12 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
<!-- Each CLB tile includes a Configurable Logic Block (CLB)
Each input of the tile can be driven by 15% of routing tracks
Each output of the tile can drive 10% of routing tracks
-->
<tile name="clb" area="53894">
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -152,13 +151,13 @@
Top side pins are mainly for direct connections
-->
<pinlocations pattern="custom">
<loc side="left"></loc>
<loc side="left"/>
<loc side="top">clb.sc_in clb.cin clb.cin_trick clb.regin clb.clk</loc>
<loc side="right">clb.I0[9:0] clb.I1[9:0] clb.O[9:0]</loc>
<loc side="bottom">clb.cout clb.cout_copy clb.sc_out clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10]</loc>
</pinlocations>
</tile>
<tile name="memory" height="2" area="548000">
</sub_tile> </tile>
<tile name="memory" height="2" area="548000"> <sub_tile name="memory">
<equivalent_sites>
<site pb_type="memory"/>
</equivalent_sites>
@ -171,12 +170,12 @@
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="left"></loc>
<loc side="left"/>
<loc side="top">memory.clk</loc>
<loc side="right">memory.waddr memory.d_in[15:0] memory.wen memory.d_out[15:0]</loc>
<loc side="bottom">memory.raddr memory.d_in[31:16] memory.ren memory.d_out[31:16]</loc>
</pinlocations>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

17
openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
- 40 nm technology
@ -75,8 +75,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -140,7 +139,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -153,8 +152,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -175,8 +174,8 @@
<loc side="right">clb.O[9:0] clb.I[19:0]</loc>
<loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
</pinlocations>
</tile>
<tile name="memory" height="2" area="548000">
</sub_tile> </tile>
<tile name="memory" height="2" area="548000"> <sub_tile name="memory">
<equivalent_sites>
<site pb_type="memory"/>
</equivalent_sites>
@ -196,7 +195,7 @@
<loc side="right" yoffset="1">memory.raddr[0:4] memory.d_out[0:15]</loc>
<loc side="bottom">memory.waddr[5:9] memory.raddr[5:9] memory.d_in[16:31] memory.ren memory.d_out[16:31]</loc>
</pinlocations-->
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

17
openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_wide_mem16K_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
- 40 nm technology
@ -75,8 +75,7 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -140,7 +139,7 @@
</model>
</models>
<tiles>
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -153,8 +152,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -175,8 +174,8 @@
<loc side="right">clb.O[9:0] clb.I[19:0]</loc>
<loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
</pinlocations>
</tile>
<tile name="memory" width="2" height="2" area="548000">
</sub_tile> </tile>
<tile name="memory" width="2" height="2" area="548000"> <sub_tile name="memory">
<equivalent_sites>
<site pb_type="memory"/>
</equivalent_sites>
@ -189,7 +188,7 @@
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="perimeter"/>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->

13
openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml
View File

@ -1,4 +1,4 @@
<!--
<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
- 40 nm technology
@ -12,8 +12,7 @@
Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
@ -49,7 +48,7 @@
If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end
-->
<tile name="io" capacity="8" area="0">
<tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
@ -62,8 +61,8 @@
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
</tile>
<tile name="clb" area="53894">
</sub_tile> </tile>
<tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
@ -72,7 +71,7 @@
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
</tile>
</sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->