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[arch] update arch files

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tangxifan 2022-08-22 18:24:37 -07:00
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openfpga_flow/vpr_arch/k4_N4_tileableIO_40nm.xml
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@ -1,4 +1,4 @@
<!-- <?xml version="1.0" ?><!--
Architecture with no fracturable LUTs Architecture with no fracturable LUTs
- 40 nm technology - 40 nm technology
@ -12,9 +12,8 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--> --><architecture>
<architecture> <!--
<!--
ODIN II specific config begins ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports. ".model [type_of_block]") that this architecture supports.
@ -22,64 +21,64 @@
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch) already special structures in blif (.names, .input, .output, and .latch)
that describe them. that describe them.
--> -->
<models> <models>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io"> <model name="io">
<input_ports> <input_ports>
<port name="outpad"/> <port name="outpad"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="inpad"/> <port name="inpad"/>
</output_ports> </output_ports>
</model> </model>
</models> </models>
<tiles> <tiles>
<tile name="io" capacity="8" area="0"> <tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="top">io.outpad</loc> <loc side="top">io.outpad</loc>
<loc side="right">io.inpad</loc> <loc side="right">io.inpad</loc>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
<tile name="clb" area="53894"> <tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites> <equivalent_sites>
<site pb_type="clb"/> <site pb_type="clb"/>
</equivalent_sites> </equivalent_sites>
<input name="I" num_pins="10" equivalent="full"/> <input name="I" num_pins="10" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/> <output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/> <pinlocations pattern="spread"/>
</tile> </sub_tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
<!-- Physical descriptions begin --> <!-- Physical descriptions begin -->
<layout tileable="true"> <layout tileable="true">
<auto_layout aspect_ratio="1.0"> <auto_layout aspect_ratio="1.0">
<!-- Perimeter of 'EMPTY' blocks --> <!-- Perimeter of 'EMPTY' blocks -->
<perimeter type="EMPTY" priority="100"/> <perimeter type="EMPTY" priority="100"/>
<!--Fill with 'io'--> <!--Fill with 'io'-->
<fill type="io" priority="10"/> <fill type="io" priority="10"/>
<!-- Build an inner region of clbs --> <!-- Build an inner region of clbs -->
<region type="clb" startx="2" endx="W-3" starty="2" endy="H-3" priority="101"/> <region type="clb" startx="2" endx="W-3" starty="2" endy="H-3" priority="101"/>
</auto_layout> </auto_layout>
<fixed_layout name="2x2" width="6" height="6"> <fixed_layout name="2x2" width="6" height="6">
<!-- Perimeter of 'EMPTY' blocks --> <!-- Perimeter of 'EMPTY' blocks -->
<perimeter type="EMPTY" priority="100"/> <perimeter type="EMPTY" priority="100"/>
<!--Fill with 'io'--> <!--Fill with 'io'-->
<fill type="io" priority="10"/> <fill type="io" priority="10"/>
<!-- Build an inner region of clbs --> <!-- Build an inner region of clbs -->
<region type="clb" startx="2" endx="W-3" starty="2" endy="H-3" priority="101"/> <region type="clb" startx="2" endx="W-3" starty="2" endy="H-3" priority="101"/>
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
@ -93,21 +92,21 @@
The delay values are lined up with Stratix IV, which has an architecture similar to this The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. --> 4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
--> -->
<area grid_logic_tile_area="0"/> <area grid_logic_tile_area="0"/>
<chan_width_distr> <chan_width_distr>
<x distr="uniform" peak="1.000000"/> <x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/> <y distr="uniform" peak="1.000000"/>
</chan_width_distr> </chan_width_distr>
<switch_block type="wilton" fs="3"/> <switch_block type="wilton" fs="3"/>
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength. book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
@ -119,81 +118,81 @@
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables. 2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. --> This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/> <mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
</segment> </segment>
</segmentlist> </segmentlist>
<complexblocklist> <complexblocklist>
<!-- Define I/O pads begin --> <!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA --> <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. --> <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io"> <pb_type name="io">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- IOs can operate as either inputs or outputs. <!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them. today and that is when you timing analyze them.
--> -->
<mode name="inpad"> <mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<mode name="outpad"> <mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1"> <pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- IOs go on the periphery of the FPGA, for consistency, <!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed. make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
--> -->
<!-- Place I/Os on the sides of the FPGA --> <!-- Place I/Os on the sides of the FPGA -->
<power method="ignore"/> <power method="ignore"/>
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin --> <!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs. area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic This means that only 37% of our area is in the general routing, and 63% is inside the logic
@ -201,69 +200,69 @@
area in this analysis. That is a lower proportion of of routing area than most academics area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range. routing area up significantly, we estimate into the ~70% range.
--> -->
<pb_type name="clb"> <pb_type name="clb">
<input name="I" num_pins="10" equivalent="full"/> <input name="I" num_pins="10" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/> <output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Describe basic logic element. <!-- Describe basic logic element.
Each basic logic element has a 4-LUT that can be optionally registered Each basic logic element has a 4-LUT that can be optionally registered
--> -->
<pb_type name="fle" num_pb="4"> <pb_type name="fle" num_pb="4">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- 4-LUT mode definition begin --> <!-- 4-LUT mode definition begin -->
<mode name="n1_lut4"> <mode name="n1_lut4">
<!-- Define 4-LUT mode --> <!-- Define 4-LUT mode -->
<pb_type name="ble4" num_pb="1"> <pb_type name="ble4" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/> <input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out"> <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/> <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D"> <direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/> <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/> <direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out"> <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/> <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/> <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="ble4.in"/> <direct name="direct1" input="fle.in" output="ble4.in"/>
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/> <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble4.clk"/> <direct name="direct3" input="fle.clk" output="ble4.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- 6-LUT mode definition end --> <!-- 6-LUT mode definition end -->
</pb_type> </pb_type>
<interconnect> <interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB <!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining delay on the connection block input mux (modeled by Ian Kuon), so the remaining
@ -271,23 +270,23 @@
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT. The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. --> to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in"> <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/> <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
</complete> </complete>
<complete name="clks" input="clb.clk" output="fle[3:0].clk"> <complete name="clks" input="clb.clk" output="fle[3:0].clk">
</complete> </complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins. <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification). naive specification).
--> -->
<direct name="clbouts1" input="fle[3:0].out" output="clb.O"/> <direct name="clbouts1" input="fle[3:0].out" output="clb.O"/>
</interconnect> </interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- Place this general purpose logic block in any unspecified column --> <!-- Place this general purpose logic block in any unspecified column -->
</pb_type> </pb_type>
<!-- Define general purpose logic block (CLB) ends --> <!-- Define general purpose logic block (CLB) ends -->
</complexblocklist> </complexblocklist>
</architecture> </architecture>

479
openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
View File

@ -1,4 +1,4 @@
<!-- <?xml version="1.0" ?><!--
Architecture with no fracturable LUTs Architecture with no fracturable LUTs
- 40 nm technology - 40 nm technology
@ -12,9 +12,8 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--> --><architecture>
<architecture> <!--
<!--
ODIN II specific config begins ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports. ".model [type_of_block]") that this architecture supports.
@ -22,85 +21,85 @@
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch) already special structures in blif (.names, .input, .output, and .latch)
that describe them. that describe them.
--> -->
<models> <models>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io"> <model name="io">
<input_ports> <input_ports>
<port name="outpad"/> <port name="outpad"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="inpad"/> <port name="inpad"/>
</output_ports> </output_ports>
</model> </model>
</models> </models>
<tiles> <tiles>
<tile name="io" capacity="8" area="0"> <tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc> <loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc> <loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc> <loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc> <loc side="bottom">io.outpad io.inpad</loc>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
<tile name="clb" area="53894"> <tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites> <equivalent_sites>
<site pb_type="clb"/> <site pb_type="clb"/>
</equivalent_sites> </equivalent_sites>
<input name="I" num_pins="10" equivalent="full"/> <input name="I" num_pins="10" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/> <output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/> <pinlocations pattern="spread"/>
</tile> </sub_tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
<!-- Physical descriptions begin --> <!-- Physical descriptions begin -->
<layout tileable="true"> <layout tileable="true">
<auto_layout aspect_ratio="1.0"> <auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</auto_layout> </auto_layout>
<fixed_layout name="2x2" width="4" height="4"> <fixed_layout name="2x2" width="4" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
<fixed_layout name="4x4" width="6" height="6"> <fixed_layout name="4x4" width="6" height="6">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
<fixed_layout name="48x48" width="50" height="50"> <fixed_layout name="48x48" width="50" height="50">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
<fixed_layout name="96x96" width="98" height="98"> <fixed_layout name="96x96" width="98" height="98">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
@ -114,21 +113,21 @@
The delay values are lined up with Stratix IV, which has an architecture similar to this The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. --> 4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
--> -->
<area grid_logic_tile_area="0"/> <area grid_logic_tile_area="0"/>
<chan_width_distr> <chan_width_distr>
<x distr="uniform" peak="1.000000"/> <x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/> <y distr="uniform" peak="1.000000"/>
</chan_width_distr> </chan_width_distr>
<switch_block type="wilton" fs="3"/> <switch_block type="wilton" fs="3"/>
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength. book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
@ -140,81 +139,81 @@
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables. 2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. --> This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/> <mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
</segment> </segment>
</segmentlist> </segmentlist>
<complexblocklist> <complexblocklist>
<!-- Define I/O pads begin --> <!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA --> <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. --> <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io"> <pb_type name="io">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- IOs can operate as either inputs or outputs. <!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them. today and that is when you timing analyze them.
--> -->
<mode name="inpad"> <mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<mode name="outpad"> <mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1"> <pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- IOs go on the periphery of the FPGA, for consistency, <!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed. make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
--> -->
<!-- Place I/Os on the sides of the FPGA --> <!-- Place I/Os on the sides of the FPGA -->
<power method="ignore"/> <power method="ignore"/>
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin --> <!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs. area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic This means that only 37% of our area is in the general routing, and 63% is inside the logic
@ -222,69 +221,69 @@
area in this analysis. That is a lower proportion of of routing area than most academics area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range. routing area up significantly, we estimate into the ~70% range.
--> -->
<pb_type name="clb"> <pb_type name="clb">
<input name="I" num_pins="10" equivalent="full"/> <input name="I" num_pins="10" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/> <output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Describe basic logic element. <!-- Describe basic logic element.
Each basic logic element has a 4-LUT that can be optionally registered Each basic logic element has a 4-LUT that can be optionally registered
--> -->
<pb_type name="fle" num_pb="4"> <pb_type name="fle" num_pb="4">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- 4-LUT mode definition begin --> <!-- 4-LUT mode definition begin -->
<mode name="n1_lut4"> <mode name="n1_lut4">
<!-- Define 4-LUT mode --> <!-- Define 4-LUT mode -->
<pb_type name="ble4" num_pb="1"> <pb_type name="ble4" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/> <input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out"> <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/> <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D"> <direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/> <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/> <direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out"> <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/> <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/> <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="ble4.in"/> <direct name="direct1" input="fle.in" output="ble4.in"/>
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/> <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble4.clk"/> <direct name="direct3" input="fle.clk" output="ble4.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- 6-LUT mode definition end --> <!-- 6-LUT mode definition end -->
</pb_type> </pb_type>
<interconnect> <interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB <!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining delay on the connection block input mux (modeled by Ian Kuon), so the remaining
@ -292,23 +291,23 @@
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT. The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. --> to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in"> <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/> <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
</complete> </complete>
<complete name="clks" input="clb.clk" output="fle[3:0].clk"> <complete name="clks" input="clb.clk" output="fle[3:0].clk">
</complete> </complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins. <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification). naive specification).
--> -->
<direct name="clbouts1" input="fle[3:0].out" output="clb.O"/> <direct name="clbouts1" input="fle[3:0].out" output="clb.O"/>
</interconnect> </interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- Place this general purpose logic block in any unspecified column --> <!-- Place this general purpose logic block in any unspecified column -->
</pb_type> </pb_type>
<!-- Define general purpose logic block (CLB) ends --> <!-- Define general purpose logic block (CLB) ends -->
</complexblocklist> </complexblocklist>
</architecture> </architecture>

441
openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml
View File

@ -1,4 +1,4 @@
<!-- <?xml version="1.0" ?><!--
Architecture with no fracturable LUTs Architecture with no fracturable LUTs
- 40 nm technology - 40 nm technology
@ -13,9 +13,8 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--> --><architecture>
<architecture> <!--
<!--
ODIN II specific config begins ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports. ".model [type_of_block]") that this architecture supports.
@ -23,66 +22,66 @@
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch) already special structures in blif (.names, .input, .output, and .latch)
that describe them. that describe them.
--> -->
<models> <models>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io"> <model name="io">
<input_ports> <input_ports>
<port name="outpad"/> <port name="outpad"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="inpad"/> <port name="inpad"/>
</output_ports> </output_ports>
</model> </model>
</models> </models>
<tiles> <tiles>
<tile name="io" capacity="8" area="0"> <tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc> <loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc> <loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc> <loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc> <loc side="bottom">io.outpad io.inpad</loc>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
<tile name="clb" area="53894"> <tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites> <equivalent_sites>
<site pb_type="clb"/> <site pb_type="clb"/>
</equivalent_sites> </equivalent_sites>
<input name="I" num_pins="10" equivalent="full"/> <input name="I" num_pins="10" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/> <output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="4"/> <clock name="clk" num_pins="4"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="clk" fc_type="frac" fc_val="0"/> <fc_override port_name="clk" fc_type="frac" fc_val="0"/>
</fc> </fc>
<pinlocations pattern="spread"/> <pinlocations pattern="spread"/>
</tile> </sub_tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
<!-- Physical descriptions begin --> <!-- Physical descriptions begin -->
<layout tileable="true"> <layout tileable="true">
<auto_layout aspect_ratio="1.0"> <auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</auto_layout> </auto_layout>
<fixed_layout name="2x2" width="4" height="4"> <fixed_layout name="2x2" width="4" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
@ -96,21 +95,21 @@
The delay values are lined up with Stratix IV, which has an architecture similar to this The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. --> 4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
--> -->
<area grid_logic_tile_area="0"/> <area grid_logic_tile_area="0"/>
<chan_width_distr> <chan_width_distr>
<x distr="uniform" peak="1.000000"/> <x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/> <y distr="uniform" peak="1.000000"/>
</chan_width_distr> </chan_width_distr>
<switch_block type="wilton" fs="3"/> <switch_block type="wilton" fs="3"/>
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength. book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
@ -122,81 +121,81 @@
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables. 2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. --> This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/> <mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
</segment> </segment>
</segmentlist> </segmentlist>
<complexblocklist> <complexblocklist>
<!-- Define I/O pads begin --> <!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA --> <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. --> <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io"> <pb_type name="io">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- IOs can operate as either inputs or outputs. <!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them. today and that is when you timing analyze them.
--> -->
<mode name="inpad"> <mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<mode name="outpad"> <mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1"> <pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- IOs go on the periphery of the FPGA, for consistency, <!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed. make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
--> -->
<!-- Place I/Os on the sides of the FPGA --> <!-- Place I/Os on the sides of the FPGA -->
<power method="ignore"/> <power method="ignore"/>
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin --> <!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs. area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic This means that only 37% of our area is in the general routing, and 63% is inside the logic
@ -204,69 +203,69 @@
area in this analysis. That is a lower proportion of of routing area than most academics area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range. routing area up significantly, we estimate into the ~70% range.
--> -->
<pb_type name="clb"> <pb_type name="clb">
<input name="I" num_pins="10" equivalent="full"/> <input name="I" num_pins="10" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/> <output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="4"/> <clock name="clk" num_pins="4"/>
<!-- Describe basic logic element. <!-- Describe basic logic element.
Each basic logic element has a 4-LUT that can be optionally registered Each basic logic element has a 4-LUT that can be optionally registered
--> -->
<pb_type name="fle" num_pb="4"> <pb_type name="fle" num_pb="4">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- 4-LUT mode definition begin --> <!-- 4-LUT mode definition begin -->
<mode name="n1_lut4"> <mode name="n1_lut4">
<!-- Define 4-LUT mode --> <!-- Define 4-LUT mode -->
<pb_type name="ble4" num_pb="1"> <pb_type name="ble4" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/> <input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out"> <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/> <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D"> <direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/> <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/> <direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out"> <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/> <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/> <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="ble4.in"/> <direct name="direct1" input="fle.in" output="ble4.in"/>
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/> <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble4.clk"/> <direct name="direct3" input="fle.clk" output="ble4.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- 6-LUT mode definition end --> <!-- 6-LUT mode definition end -->
</pb_type> </pb_type>
<interconnect> <interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB <!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining delay on the connection block input mux (modeled by Ian Kuon), so the remaining
@ -274,23 +273,23 @@
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT. The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. --> to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in"> <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/> <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
</complete> </complete>
<complete name="clks" input="clb.clk" output="fle[3:0].clk"> <complete name="clks" input="clb.clk" output="fle[3:0].clk">
</complete> </complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins. <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification). naive specification).
--> -->
<direct name="clbouts1" input="fle[3:0].out" output="clb.O"/> <direct name="clbouts1" input="fle[3:0].out" output="clb.O"/>
</interconnect> </interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- Place this general purpose logic block in any unspecified column --> <!-- Place this general purpose logic block in any unspecified column -->
</pb_type> </pb_type>
<!-- Define general purpose logic block (CLB) ends --> <!-- Define general purpose logic block (CLB) ends -->
</complexblocklist> </complexblocklist>
</architecture> </architecture>

441
openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile8Clk_40nm.xml
View File

@ -1,4 +1,4 @@
<!-- <?xml version="1.0" ?><!--
Architecture with no fracturable LUTs Architecture with no fracturable LUTs
- 40 nm technology - 40 nm technology
@ -13,9 +13,8 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--> --><architecture>
<architecture> <!--
<!--
ODIN II specific config begins ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports. ".model [type_of_block]") that this architecture supports.
@ -23,66 +22,66 @@
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch) already special structures in blif (.names, .input, .output, and .latch)
that describe them. that describe them.
--> -->
<models> <models>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io"> <model name="io">
<input_ports> <input_ports>
<port name="outpad"/> <port name="outpad"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="inpad"/> <port name="inpad"/>
</output_ports> </output_ports>
</model> </model>
</models> </models>
<tiles> <tiles>
<tile name="io" capacity="8" area="0"> <tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc> <loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc> <loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc> <loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc> <loc side="bottom">io.outpad io.inpad</loc>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
<tile name="clb" area="53894"> <tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites> <equivalent_sites>
<site pb_type="clb"/> <site pb_type="clb"/>
</equivalent_sites> </equivalent_sites>
<input name="I" num_pins="10" equivalent="full"/> <input name="I" num_pins="10" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/> <output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="8"/> <clock name="clk" num_pins="8"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="clk" fc_type="frac" fc_val="0"/> <fc_override port_name="clk" fc_type="frac" fc_val="0"/>
</fc> </fc>
<pinlocations pattern="spread"/> <pinlocations pattern="spread"/>
</tile> </sub_tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
<!-- Physical descriptions begin --> <!-- Physical descriptions begin -->
<layout tileable="true"> <layout tileable="true">
<auto_layout aspect_ratio="1.0"> <auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</auto_layout> </auto_layout>
<fixed_layout name="2x2" width="4" height="4"> <fixed_layout name="2x2" width="4" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
@ -96,21 +95,21 @@
The delay values are lined up with Stratix IV, which has an architecture similar to this The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. --> 4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
--> -->
<area grid_logic_tile_area="0"/> <area grid_logic_tile_area="0"/>
<chan_width_distr> <chan_width_distr>
<x distr="uniform" peak="1.000000"/> <x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/> <y distr="uniform" peak="1.000000"/>
</chan_width_distr> </chan_width_distr>
<switch_block type="wilton" fs="3"/> <switch_block type="wilton" fs="3"/>
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength. book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
@ -122,81 +121,81 @@
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables. 2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. --> This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/> <mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
</segment> </segment>
</segmentlist> </segmentlist>
<complexblocklist> <complexblocklist>
<!-- Define I/O pads begin --> <!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA --> <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. --> <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io"> <pb_type name="io">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- IOs can operate as either inputs or outputs. <!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them. today and that is when you timing analyze them.
--> -->
<mode name="inpad"> <mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<mode name="outpad"> <mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1"> <pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- IOs go on the periphery of the FPGA, for consistency, <!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed. make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
--> -->
<!-- Place I/Os on the sides of the FPGA --> <!-- Place I/Os on the sides of the FPGA -->
<power method="ignore"/> <power method="ignore"/>
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin --> <!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs. area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic This means that only 37% of our area is in the general routing, and 63% is inside the logic
@ -204,69 +203,69 @@
area in this analysis. That is a lower proportion of of routing area than most academics area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range. routing area up significantly, we estimate into the ~70% range.
--> -->
<pb_type name="clb"> <pb_type name="clb">
<input name="I" num_pins="10" equivalent="full"/> <input name="I" num_pins="10" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/> <output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="8"/> <clock name="clk" num_pins="8"/>
<!-- Describe basic logic element. <!-- Describe basic logic element.
Each basic logic element has a 4-LUT that can be optionally registered Each basic logic element has a 4-LUT that can be optionally registered
--> -->
<pb_type name="fle" num_pb="4"> <pb_type name="fle" num_pb="4">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- 4-LUT mode definition begin --> <!-- 4-LUT mode definition begin -->
<mode name="n1_lut4"> <mode name="n1_lut4">
<!-- Define 4-LUT mode --> <!-- Define 4-LUT mode -->
<pb_type name="ble4" num_pb="1"> <pb_type name="ble4" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/> <input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out"> <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/> <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D"> <direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/> <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/> <direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out"> <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/> <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/> <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="ble4.in"/> <direct name="direct1" input="fle.in" output="ble4.in"/>
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/> <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble4.clk"/> <direct name="direct3" input="fle.clk" output="ble4.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- 6-LUT mode definition end --> <!-- 6-LUT mode definition end -->
</pb_type> </pb_type>
<interconnect> <interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB <!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining delay on the connection block input mux (modeled by Ian Kuon), so the remaining
@ -274,23 +273,23 @@
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT. The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. --> to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in"> <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/> <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
</complete> </complete>
<complete name="clks" input="clb.clk" output="fle[3:0].clk"> <complete name="clks" input="clb.clk" output="fle[3:0].clk">
</complete> </complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins. <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification). naive specification).
--> -->
<direct name="clbouts1" input="fle[3:0].out" output="clb.O"/> <direct name="clbouts1" input="fle[3:0].out" output="clb.O"/>
</interconnect> </interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- Place this general purpose logic block in any unspecified column --> <!-- Place this general purpose logic block in any unspecified column -->
</pb_type> </pb_type>
<!-- Define general purpose logic block (CLB) ends --> <!-- Define general purpose logic block (CLB) ends -->
</complexblocklist> </complexblocklist>
</architecture> </architecture>

441
openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_40nm.xml
View File

@ -1,4 +1,4 @@
<!-- <?xml version="1.0" ?><!--
Architecture with no fracturable LUTs Architecture with no fracturable LUTs
- 40 nm technology - 40 nm technology
@ -12,9 +12,8 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--> --><architecture>
<architecture> <!--
<!--
ODIN II specific config begins ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports. ".model [type_of_block]") that this architecture supports.
@ -22,66 +21,66 @@
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch) already special structures in blif (.names, .input, .output, and .latch)
that describe them. that describe them.
--> -->
<models> <models>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io"> <model name="io">
<input_ports> <input_ports>
<port name="outpad"/> <port name="outpad"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="inpad"/> <port name="inpad"/>
</output_ports> </output_ports>
</model> </model>
</models> </models>
<tiles> <tiles>
<tile name="io" capacity="8" area="0"> <tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc> <loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc> <loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc> <loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc> <loc side="bottom">io.outpad io.inpad</loc>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
<tile name="clb" area="53894"> <tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites> <equivalent_sites>
<site pb_type="clb"/> <site pb_type="clb"/>
</equivalent_sites> </equivalent_sites>
<input name="I" num_pins="10" equivalent="full"/> <input name="I" num_pins="10" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/> <output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="clk" fc_type="frac" fc_val="0"/> <fc_override port_name="clk" fc_type="frac" fc_val="0"/>
</fc> </fc>
<pinlocations pattern="spread"/> <pinlocations pattern="spread"/>
</tile> </sub_tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
<!-- Physical descriptions begin --> <!-- Physical descriptions begin -->
<layout tileable="true"> <layout tileable="true">
<auto_layout aspect_ratio="1.0"> <auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</auto_layout> </auto_layout>
<fixed_layout name="2x2" width="4" height="4"> <fixed_layout name="2x2" width="4" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
@ -95,21 +94,21 @@
The delay values are lined up with Stratix IV, which has an architecture similar to this The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. --> 4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
--> -->
<area grid_logic_tile_area="0"/> <area grid_logic_tile_area="0"/>
<chan_width_distr> <chan_width_distr>
<x distr="uniform" peak="1.000000"/> <x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/> <y distr="uniform" peak="1.000000"/>
</chan_width_distr> </chan_width_distr>
<switch_block type="wilton" fs="3"/> <switch_block type="wilton" fs="3"/>
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength. book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
@ -121,81 +120,81 @@
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables. 2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. --> This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/> <mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
</segment> </segment>
</segmentlist> </segmentlist>
<complexblocklist> <complexblocklist>
<!-- Define I/O pads begin --> <!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA --> <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. --> <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io"> <pb_type name="io">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- IOs can operate as either inputs or outputs. <!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them. today and that is when you timing analyze them.
--> -->
<mode name="inpad"> <mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<mode name="outpad"> <mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1"> <pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- IOs go on the periphery of the FPGA, for consistency, <!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed. make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
--> -->
<!-- Place I/Os on the sides of the FPGA --> <!-- Place I/Os on the sides of the FPGA -->
<power method="ignore"/> <power method="ignore"/>
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin --> <!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs. area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic This means that only 37% of our area is in the general routing, and 63% is inside the logic
@ -203,69 +202,69 @@
area in this analysis. That is a lower proportion of of routing area than most academics area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range. routing area up significantly, we estimate into the ~70% range.
--> -->
<pb_type name="clb"> <pb_type name="clb">
<input name="I" num_pins="10" equivalent="full"/> <input name="I" num_pins="10" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/> <output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Describe basic logic element. <!-- Describe basic logic element.
Each basic logic element has a 4-LUT that can be optionally registered Each basic logic element has a 4-LUT that can be optionally registered
--> -->
<pb_type name="fle" num_pb="4"> <pb_type name="fle" num_pb="4">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- 4-LUT mode definition begin --> <!-- 4-LUT mode definition begin -->
<mode name="n1_lut4"> <mode name="n1_lut4">
<!-- Define 4-LUT mode --> <!-- Define 4-LUT mode -->
<pb_type name="ble4" num_pb="1"> <pb_type name="ble4" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/> <input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out"> <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/> <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D"> <direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/> <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/> <direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out"> <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/> <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/> <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="ble4.in"/> <direct name="direct1" input="fle.in" output="ble4.in"/>
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/> <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble4.clk"/> <direct name="direct3" input="fle.clk" output="ble4.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- 6-LUT mode definition end --> <!-- 6-LUT mode definition end -->
</pb_type> </pb_type>
<interconnect> <interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB <!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining delay on the connection block input mux (modeled by Ian Kuon), so the remaining
@ -273,23 +272,23 @@
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT. The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. --> to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in"> <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/> <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
</complete> </complete>
<complete name="clks" input="clb.clk" output="fle[3:0].clk"> <complete name="clks" input="clb.clk" output="fle[3:0].clk">
</complete> </complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins. <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification). naive specification).
--> -->
<direct name="clbouts1" input="fle[3:0].out" output="clb.O"/> <direct name="clbouts1" input="fle[3:0].out" output="clb.O"/>
</interconnect> </interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- Place this general purpose logic block in any unspecified column --> <!-- Place this general purpose logic block in any unspecified column -->
</pb_type> </pb_type>
<!-- Define general purpose logic block (CLB) ends --> <!-- Define general purpose logic block (CLB) ends -->
</complexblocklist> </complexblocklist>
</architecture> </architecture>

509
openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml
View File

@ -1,4 +1,4 @@
<!-- <?xml version="1.0" ?><!--
Architecture with no fracturable LUTs Architecture with no fracturable LUTs
- 40 nm technology - 40 nm technology
@ -12,9 +12,8 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--> --><architecture>
<architecture> <!--
<!--
ODIN II specific config begins ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports. ".model [type_of_block]") that this architecture supports.
@ -22,69 +21,69 @@
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch) already special structures in blif (.names, .input, .output, and .latch)
that describe them. that describe them.
--> -->
<models> <models>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io"> <model name="io">
<input_ports> <input_ports>
<port name="outpad"/> <port name="outpad"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="inpad"/> <port name="inpad"/>
</output_ports> </output_ports>
</model> </model>
</models> </models>
<tiles> <tiles>
<tile name="io" capacity="8" area="0"> <tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="clk" fc_type="frac" fc_val="0"/> <fc_override port_name="clk" fc_type="frac" fc_val="0"/>
</fc> </fc>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad io.clk</loc> <loc side="left">io.outpad io.inpad io.clk</loc>
<loc side="top">io.outpad io.inpad io.clk</loc> <loc side="top">io.outpad io.inpad io.clk</loc>
<loc side="right">io.outpad io.inpad io.clk</loc> <loc side="right">io.outpad io.inpad io.clk</loc>
<loc side="bottom">io.outpad io.inpad io.clk</loc> <loc side="bottom">io.outpad io.inpad io.clk</loc>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
<tile name="clb" area="53894"> <tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites> <equivalent_sites>
<site pb_type="clb"/> <site pb_type="clb"/>
</equivalent_sites> </equivalent_sites>
<input name="I" num_pins="10" equivalent="full"/> <input name="I" num_pins="10" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/> <output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="clk" fc_type="frac" fc_val="0"/> <fc_override port_name="clk" fc_type="frac" fc_val="0"/>
</fc> </fc>
<pinlocations pattern="spread"/> <pinlocations pattern="spread"/>
</tile> </sub_tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
<!-- Physical descriptions begin --> <!-- Physical descriptions begin -->
<layout tileable="true"> <layout tileable="true">
<auto_layout aspect_ratio="1.0"> <auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</auto_layout> </auto_layout>
<fixed_layout name="2x2" width="4" height="4"> <fixed_layout name="2x2" width="4" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
@ -98,21 +97,21 @@
The delay values are lined up with Stratix IV, which has an architecture similar to this The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. --> 4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
--> -->
<area grid_logic_tile_area="0"/> <area grid_logic_tile_area="0"/>
<chan_width_distr> <chan_width_distr>
<x distr="uniform" peak="1.000000"/> <x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/> <y distr="uniform" peak="1.000000"/>
</chan_width_distr> </chan_width_distr>
<switch_block type="wilton" fs="3"/> <switch_block type="wilton" fs="3"/>
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength. book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
@ -124,112 +123,112 @@
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables. 2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. --> This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/> <mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
</segment> </segment>
</segmentlist> </segmentlist>
<complexblocklist> <complexblocklist>
<!-- Define I/O pads begin --> <!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA --> <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. --> <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io"> <pb_type name="io">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="clk" input="io.clk" output="ff.clk"/> <direct name="clk" input="io.clk" output="ff.clk"/>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<!-- Create a selector between registered/combinational I/O --> <!-- Create a selector between registered/combinational I/O -->
<direct name="inpad" input="iopad.inpad" output="ff.D"/> <direct name="inpad" input="iopad.inpad" output="ff.D"/>
<mux name="mux1" input="iopad.inpad ff.Q" output="io.inpad"> <mux name="mux1" input="iopad.inpad ff.Q" output="io.inpad">
<delay_constant max="4.5e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="4.5e-11" in_port="iopad.inpad" out_port="io.inpad"/>
<delay_constant max="4.243e-11" in_port="ff.Q" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="ff.Q" out_port="io.inpad"/>
</mux> </mux>
</interconnect> </interconnect>
</mode> </mode>
<!-- IOs can operate as either inputs or outputs. <!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them. today and that is when you timing analyze them.
--> -->
<mode name="inpad"> <mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<mode name="inpad_registered"> <mode name="inpad_registered">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="clk" input="io.clk" output="ff.clk"/> <direct name="clk" input="io.clk" output="ff.clk"/>
<direct name="inpad" input="inpad.inpad" output="ff.D"> <direct name="inpad" input="inpad.inpad" output="ff.D">
<pack_pattern name="registered_io" in_port="inpad.inpad" out_port="ff.D"/> <pack_pattern name="registered_io" in_port="inpad.inpad" out_port="ff.D"/>
</direct> </direct>
<direct name="ff2inpad" input="ff.Q" output="io.inpad"/> <direct name="ff2inpad" input="ff.Q" output="io.inpad"/>
</interconnect> </interconnect>
</mode> </mode>
<mode name="outpad"> <mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1"> <pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- IOs go on the periphery of the FPGA, for consistency, <!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed. make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
--> -->
<!-- Place I/Os on the sides of the FPGA --> <!-- Place I/Os on the sides of the FPGA -->
<power method="ignore"/> <power method="ignore"/>
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin --> <!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs. area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic This means that only 37% of our area is in the general routing, and 63% is inside the logic
@ -237,69 +236,69 @@
area in this analysis. That is a lower proportion of of routing area than most academics area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range. routing area up significantly, we estimate into the ~70% range.
--> -->
<pb_type name="clb"> <pb_type name="clb">
<input name="I" num_pins="10" equivalent="full"/> <input name="I" num_pins="10" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/> <output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Describe basic logic element. <!-- Describe basic logic element.
Each basic logic element has a 4-LUT that can be optionally registered Each basic logic element has a 4-LUT that can be optionally registered
--> -->
<pb_type name="fle" num_pb="4"> <pb_type name="fle" num_pb="4">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- 4-LUT mode definition begin --> <!-- 4-LUT mode definition begin -->
<mode name="n1_lut4"> <mode name="n1_lut4">
<!-- Define 4-LUT mode --> <!-- Define 4-LUT mode -->
<pb_type name="ble4" num_pb="1"> <pb_type name="ble4" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/> <input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out"> <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/> <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D"> <direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/> <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/> <direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out"> <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/> <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/> <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="ble4.in"/> <direct name="direct1" input="fle.in" output="ble4.in"/>
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/> <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble4.clk"/> <direct name="direct3" input="fle.clk" output="ble4.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- 6-LUT mode definition end --> <!-- 6-LUT mode definition end -->
</pb_type> </pb_type>
<interconnect> <interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB <!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining delay on the connection block input mux (modeled by Ian Kuon), so the remaining
@ -307,23 +306,23 @@
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT. The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. --> to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in"> <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/> <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
</complete> </complete>
<complete name="clks" input="clb.clk" output="fle[3:0].clk"> <complete name="clks" input="clb.clk" output="fle[3:0].clk">
</complete> </complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins. <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification). naive specification).
--> -->
<direct name="clbouts1" input="fle[3:0].out" output="clb.O"/> <direct name="clbouts1" input="fle[3:0].out" output="clb.O"/>
</interconnect> </interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- Place this general purpose logic block in any unspecified column --> <!-- Place this general purpose logic block in any unspecified column -->
</pb_type> </pb_type>
<!-- Define general purpose logic block (CLB) ends --> <!-- Define general purpose logic block (CLB) ends -->
</complexblocklist> </complexblocklist>
</architecture> </architecture>

447
openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzBr_40nm.xml
View File

@ -1,4 +1,4 @@
<!-- <?xml version="1.0" ?><!--
Architecture with no fracturable LUTs Architecture with no fracturable LUTs
- 40 nm technology - 40 nm technology
@ -12,9 +12,8 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--> --><architecture>
<architecture> <!--
<!--
ODIN II specific config begins ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports. ".model [type_of_block]") that this architecture supports.
@ -22,69 +21,69 @@
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch) already special structures in blif (.names, .input, .output, and .latch)
that describe them. that describe them.
--> -->
<models> <models>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io"> <model name="io">
<input_ports> <input_ports>
<port name="outpad"/> <port name="outpad"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="inpad"/> <port name="inpad"/>
</output_ports> </output_ports>
</model> </model>
</models> </models>
<tiles> <tiles>
<tile name="io" capacity="8" area="0"> <tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc> <loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc> <loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc> <loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc> <loc side="bottom">io.outpad io.inpad</loc>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
<tile name="clb" area="53894"> <tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites> <equivalent_sites>
<site pb_type="clb"/> <site pb_type="clb"/>
</equivalent_sites> </equivalent_sites>
<input name="I" num_pins="10" equivalent="full"/> <input name="I" num_pins="10" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/> <output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left"></loc> <loc side="left"/>
<loc side="top"></loc> <loc side="top"/>
<loc side="right">clb.I[5:9] clb.O[2:3]</loc> <loc side="right">clb.I[5:9] clb.O[2:3]</loc>
<loc side="bottom">clb.clk clb.I[0:4] clb.O[0:1]</loc> <loc side="bottom">clb.clk clb.I[0:4] clb.O[0:1]</loc>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
<!-- Physical descriptions begin --> <!-- Physical descriptions begin -->
<layout tileable="true"> <layout tileable="true">
<auto_layout aspect_ratio="1.0"> <auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</auto_layout> </auto_layout>
<fixed_layout name="2x2" width="4" height="4"> <fixed_layout name="2x2" width="4" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
@ -98,21 +97,21 @@
The delay values are lined up with Stratix IV, which has an architecture similar to this The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. --> 4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
--> -->
<area grid_logic_tile_area="0"/> <area grid_logic_tile_area="0"/>
<chan_width_distr> <chan_width_distr>
<x distr="uniform" peak="1.000000"/> <x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/> <y distr="uniform" peak="1.000000"/>
</chan_width_distr> </chan_width_distr>
<switch_block type="wilton" fs="3"/> <switch_block type="wilton" fs="3"/>
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength. book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
@ -124,81 +123,81 @@
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables. 2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. --> This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/> <mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
</segment> </segment>
</segmentlist> </segmentlist>
<complexblocklist> <complexblocklist>
<!-- Define I/O pads begin --> <!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA --> <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. --> <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io"> <pb_type name="io">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- IOs can operate as either inputs or outputs. <!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them. today and that is when you timing analyze them.
--> -->
<mode name="inpad"> <mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<mode name="outpad"> <mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1"> <pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- IOs go on the periphery of the FPGA, for consistency, <!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed. make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
--> -->
<!-- Place I/Os on the sides of the FPGA --> <!-- Place I/Os on the sides of the FPGA -->
<power method="ignore"/> <power method="ignore"/>
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin --> <!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs. area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic This means that only 37% of our area is in the general routing, and 63% is inside the logic
@ -206,69 +205,69 @@
area in this analysis. That is a lower proportion of of routing area than most academics area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range. routing area up significantly, we estimate into the ~70% range.
--> -->
<pb_type name="clb"> <pb_type name="clb">
<input name="I" num_pins="10" equivalent="full"/> <input name="I" num_pins="10" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/> <output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Describe basic logic element. <!-- Describe basic logic element.
Each basic logic element has a 4-LUT that can be optionally registered Each basic logic element has a 4-LUT that can be optionally registered
--> -->
<pb_type name="fle" num_pb="4"> <pb_type name="fle" num_pb="4">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- 4-LUT mode definition begin --> <!-- 4-LUT mode definition begin -->
<mode name="n1_lut4"> <mode name="n1_lut4">
<!-- Define 4-LUT mode --> <!-- Define 4-LUT mode -->
<pb_type name="ble4" num_pb="1"> <pb_type name="ble4" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/> <input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out"> <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/> <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D"> <direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/> <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/> <direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out"> <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/> <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/> <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="ble4.in"/> <direct name="direct1" input="fle.in" output="ble4.in"/>
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/> <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble4.clk"/> <direct name="direct3" input="fle.clk" output="ble4.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- 6-LUT mode definition end --> <!-- 6-LUT mode definition end -->
</pb_type> </pb_type>
<interconnect> <interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB <!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining delay on the connection block input mux (modeled by Ian Kuon), so the remaining
@ -276,23 +275,23 @@
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT. The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. --> to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in"> <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/> <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
</complete> </complete>
<complete name="clks" input="clb.clk" output="fle[3:0].clk"> <complete name="clks" input="clb.clk" output="fle[3:0].clk">
</complete> </complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins. <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification). naive specification).
--> -->
<direct name="clbouts1" input="fle[3:0].out" output="clb.O"/> <direct name="clbouts1" input="fle[3:0].out" output="clb.O"/>
</interconnect> </interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- Place this general purpose logic block in any unspecified column --> <!-- Place this general purpose logic block in any unspecified column -->
</pb_type> </pb_type>
<!-- Define general purpose logic block (CLB) ends --> <!-- Define general purpose logic block (CLB) ends -->
</complexblocklist> </complexblocklist>
</architecture> </architecture>

447
openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml
View File

@ -1,4 +1,4 @@
<!-- <?xml version="1.0" ?><!--
Architecture with no fracturable LUTs Architecture with no fracturable LUTs
- 40 nm technology - 40 nm technology
@ -12,9 +12,8 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--> --><architecture>
<architecture> <!--
<!--
ODIN II specific config begins ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports. ".model [type_of_block]") that this architecture supports.
@ -22,69 +21,69 @@
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch) already special structures in blif (.names, .input, .output, and .latch)
that describe them. that describe them.
--> -->
<models> <models>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io"> <model name="io">
<input_ports> <input_ports>
<port name="outpad"/> <port name="outpad"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="inpad"/> <port name="inpad"/>
</output_ports> </output_ports>
</model> </model>
</models> </models>
<tiles> <tiles>
<tile name="io" capacity="8" area="0"> <tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc> <loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc> <loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc> <loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc> <loc side="bottom">io.outpad io.inpad</loc>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
<tile name="clb" area="53894"> <tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites> <equivalent_sites>
<site pb_type="clb"/> <site pb_type="clb"/>
</equivalent_sites> </equivalent_sites>
<input name="I" num_pins="10" equivalent="full"/> <input name="I" num_pins="10" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/> <output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="top">clb.clk clb.I[0:4] clb.O[0:1]</loc> <loc side="top">clb.clk clb.I[0:4] clb.O[0:1]</loc>
<loc side="left">clb.I[5:9] clb.O[2:3]</loc> <loc side="left">clb.I[5:9] clb.O[2:3]</loc>
<loc side="right"></loc> <loc side="right"/>
<loc side="bottom"></loc> <loc side="bottom"/>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
<!-- Physical descriptions begin --> <!-- Physical descriptions begin -->
<layout tileable="true"> <layout tileable="true">
<auto_layout aspect_ratio="1.0"> <auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</auto_layout> </auto_layout>
<fixed_layout name="2x2" width="4" height="4"> <fixed_layout name="2x2" width="4" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
@ -98,21 +97,21 @@
The delay values are lined up with Stratix IV, which has an architecture similar to this The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. --> 4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
--> -->
<area grid_logic_tile_area="0"/> <area grid_logic_tile_area="0"/>
<chan_width_distr> <chan_width_distr>
<x distr="uniform" peak="1.000000"/> <x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/> <y distr="uniform" peak="1.000000"/>
</chan_width_distr> </chan_width_distr>
<switch_block type="wilton" fs="3"/> <switch_block type="wilton" fs="3"/>
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength. book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
@ -124,81 +123,81 @@
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables. 2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. --> This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/> <mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
</segment> </segment>
</segmentlist> </segmentlist>
<complexblocklist> <complexblocklist>
<!-- Define I/O pads begin --> <!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA --> <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. --> <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io"> <pb_type name="io">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- IOs can operate as either inputs or outputs. <!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them. today and that is when you timing analyze them.
--> -->
<mode name="inpad"> <mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<mode name="outpad"> <mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1"> <pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- IOs go on the periphery of the FPGA, for consistency, <!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed. make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
--> -->
<!-- Place I/Os on the sides of the FPGA --> <!-- Place I/Os on the sides of the FPGA -->
<power method="ignore"/> <power method="ignore"/>
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin --> <!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs. area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic This means that only 37% of our area is in the general routing, and 63% is inside the logic
@ -206,69 +205,69 @@
area in this analysis. That is a lower proportion of of routing area than most academics area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range. routing area up significantly, we estimate into the ~70% range.
--> -->
<pb_type name="clb"> <pb_type name="clb">
<input name="I" num_pins="10" equivalent="full"/> <input name="I" num_pins="10" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/> <output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Describe basic logic element. <!-- Describe basic logic element.
Each basic logic element has a 4-LUT that can be optionally registered Each basic logic element has a 4-LUT that can be optionally registered
--> -->
<pb_type name="fle" num_pb="4"> <pb_type name="fle" num_pb="4">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- 4-LUT mode definition begin --> <!-- 4-LUT mode definition begin -->
<mode name="n1_lut4"> <mode name="n1_lut4">
<!-- Define 4-LUT mode --> <!-- Define 4-LUT mode -->
<pb_type name="ble4" num_pb="1"> <pb_type name="ble4" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/> <input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out"> <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/> <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D"> <direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/> <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/> <direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out"> <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/> <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/> <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="ble4.in"/> <direct name="direct1" input="fle.in" output="ble4.in"/>
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/> <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble4.clk"/> <direct name="direct3" input="fle.clk" output="ble4.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- 6-LUT mode definition end --> <!-- 6-LUT mode definition end -->
</pb_type> </pb_type>
<interconnect> <interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB <!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining delay on the connection block input mux (modeled by Ian Kuon), so the remaining
@ -276,23 +275,23 @@
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT. The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. --> to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in"> <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/> <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
</complete> </complete>
<complete name="clks" input="clb.clk" output="fle[3:0].clk"> <complete name="clks" input="clb.clk" output="fle[3:0].clk">
</complete> </complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins. <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification). naive specification).
--> -->
<direct name="clbouts1" input="fle[3:0].out" output="clb.O"/> <direct name="clbouts1" input="fle[3:0].out" output="clb.O"/>
</interconnect> </interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- Place this general purpose logic block in any unspecified column --> <!-- Place this general purpose logic block in any unspecified column -->
</pb_type> </pb_type>
<!-- Define general purpose logic block (CLB) ends --> <!-- Define general purpose logic block (CLB) ends -->
</complexblocklist> </complexblocklist>
</architecture> </architecture>

447
openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTr_40nm.xml
View File

@ -1,4 +1,4 @@
<!-- <?xml version="1.0" ?><!--
Architecture with no fracturable LUTs Architecture with no fracturable LUTs
- 40 nm technology - 40 nm technology
@ -12,9 +12,8 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--> --><architecture>
<architecture> <!--
<!--
ODIN II specific config begins ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports. ".model [type_of_block]") that this architecture supports.
@ -22,69 +21,69 @@
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch) already special structures in blif (.names, .input, .output, and .latch)
that describe them. that describe them.
--> -->
<models> <models>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io"> <model name="io">
<input_ports> <input_ports>
<port name="outpad"/> <port name="outpad"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="inpad"/> <port name="inpad"/>
</output_ports> </output_ports>
</model> </model>
</models> </models>
<tiles> <tiles>
<tile name="io" capacity="8" area="0"> <tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc> <loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc> <loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc> <loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc> <loc side="bottom">io.outpad io.inpad</loc>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
<tile name="clb" area="53894"> <tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites> <equivalent_sites>
<site pb_type="clb"/> <site pb_type="clb"/>
</equivalent_sites> </equivalent_sites>
<input name="I" num_pins="10" equivalent="full"/> <input name="I" num_pins="10" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/> <output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left"></loc> <loc side="left"/>
<loc side="top">clb.clk clb.I[0:4] clb.O[0:1]</loc> <loc side="top">clb.clk clb.I[0:4] clb.O[0:1]</loc>
<loc side="right">clb.I[5:9] clb.O[2:3]</loc> <loc side="right">clb.I[5:9] clb.O[2:3]</loc>
<loc side="bottom"></loc> <loc side="bottom"/>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
<!-- Physical descriptions begin --> <!-- Physical descriptions begin -->
<layout tileable="true"> <layout tileable="true">
<auto_layout aspect_ratio="1.0"> <auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</auto_layout> </auto_layout>
<fixed_layout name="2x2" width="4" height="4"> <fixed_layout name="2x2" width="4" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
@ -98,21 +97,21 @@
The delay values are lined up with Stratix IV, which has an architecture similar to this The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. --> 4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
--> -->
<area grid_logic_tile_area="0"/> <area grid_logic_tile_area="0"/>
<chan_width_distr> <chan_width_distr>
<x distr="uniform" peak="1.000000"/> <x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/> <y distr="uniform" peak="1.000000"/>
</chan_width_distr> </chan_width_distr>
<switch_block type="wilton" fs="3"/> <switch_block type="wilton" fs="3"/>
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength. book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
@ -124,81 +123,81 @@
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables. 2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. --> This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/> <mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
</segment> </segment>
</segmentlist> </segmentlist>
<complexblocklist> <complexblocklist>
<!-- Define I/O pads begin --> <!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA --> <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. --> <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io"> <pb_type name="io">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- IOs can operate as either inputs or outputs. <!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them. today and that is when you timing analyze them.
--> -->
<mode name="inpad"> <mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<mode name="outpad"> <mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1"> <pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- IOs go on the periphery of the FPGA, for consistency, <!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed. make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
--> -->
<!-- Place I/Os on the sides of the FPGA --> <!-- Place I/Os on the sides of the FPGA -->
<power method="ignore"/> <power method="ignore"/>
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin --> <!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs. area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic This means that only 37% of our area is in the general routing, and 63% is inside the logic
@ -206,69 +205,69 @@
area in this analysis. That is a lower proportion of of routing area than most academics area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range. routing area up significantly, we estimate into the ~70% range.
--> -->
<pb_type name="clb"> <pb_type name="clb">
<input name="I" num_pins="10" equivalent="full"/> <input name="I" num_pins="10" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/> <output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Describe basic logic element. <!-- Describe basic logic element.
Each basic logic element has a 4-LUT that can be optionally registered Each basic logic element has a 4-LUT that can be optionally registered
--> -->
<pb_type name="fle" num_pb="4"> <pb_type name="fle" num_pb="4">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- 4-LUT mode definition begin --> <!-- 4-LUT mode definition begin -->
<mode name="n1_lut4"> <mode name="n1_lut4">
<!-- Define 4-LUT mode --> <!-- Define 4-LUT mode -->
<pb_type name="ble4" num_pb="1"> <pb_type name="ble4" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/> <input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out"> <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/> <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D"> <direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/> <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/> <direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out"> <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/> <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/> <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="ble4.in"/> <direct name="direct1" input="fle.in" output="ble4.in"/>
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/> <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble4.clk"/> <direct name="direct3" input="fle.clk" output="ble4.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- 6-LUT mode definition end --> <!-- 6-LUT mode definition end -->
</pb_type> </pb_type>
<interconnect> <interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB <!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining delay on the connection block input mux (modeled by Ian Kuon), so the remaining
@ -276,23 +275,23 @@
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT. The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. --> to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in"> <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/> <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
</complete> </complete>
<complete name="clks" input="clb.clk" output="fle[3:0].clk"> <complete name="clks" input="clb.clk" output="fle[3:0].clk">
</complete> </complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins. <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification). naive specification).
--> -->
<direct name="clbouts1" input="fle[3:0].out" output="clb.O"/> <direct name="clbouts1" input="fle[3:0].out" output="clb.O"/>
</interconnect> </interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- Place this general purpose logic block in any unspecified column --> <!-- Place this general purpose logic block in any unspecified column -->
</pb_type> </pb_type>
<!-- Define general purpose logic block (CLB) ends --> <!-- Define general purpose logic block (CLB) ends -->
</complexblocklist> </complexblocklist>
</architecture> </architecture>

721
openfpga_flow/vpr_arch/k4_N4_tileable_dsp8reg_40nm.xml
View File

@ -1,4 +1,4 @@
<!-- <?xml version="1.0" ?><!--
Architecture with no fracturable LUTs Architecture with no fracturable LUTs
- 40 nm technology - 40 nm technology
@ -15,9 +15,8 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--> --><architecture>
<architecture> <!--
<!--
ODIN II specific config begins ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports. ".model [type_of_block]") that this architecture supports.
@ -25,101 +24,101 @@
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch) already special structures in blif (.names, .input, .output, and .latch)
that describe them. that describe them.
--> -->
<models> <models>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io"> <model name="io">
<input_ports> <input_ports>
<port name="outpad"/> <port name="outpad"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="inpad"/> <port name="inpad"/>
</output_ports> </output_ports>
</model> </model>
<model name="mult_8"> <model name="mult_8">
<input_ports> <input_ports>
<port name="A" combinational_sink_ports="Y"/> <port name="A" combinational_sink_ports="Y"/>
<port name="B" combinational_sink_ports="Y"/> <port name="B" combinational_sink_ports="Y"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="Y"/> <port name="Y"/>
</output_ports> </output_ports>
</model> </model>
</models> </models>
<tiles> <tiles>
<tile name="io" capacity="8" area="0"> <tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc> <loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc> <loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc> <loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc> <loc side="bottom">io.outpad io.inpad</loc>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
<tile name="clb" area="53894"> <tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites> <equivalent_sites>
<site pb_type="clb"/> <site pb_type="clb"/>
</equivalent_sites> </equivalent_sites>
<input name="I" num_pins="10" equivalent="full"/> <input name="I" num_pins="10" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/> <output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/> <pinlocations pattern="spread"/>
</tile> </sub_tile> </tile>
<tile name="mult_8" height="2" area="396000"> <tile name="mult_8" height="2" area="396000"> <sub_tile name="mult_8">
<equivalent_sites> <equivalent_sites>
<site pb_type="mult_8" pin_mapping="direct"/> <site pb_type="mult_8" pin_mapping="direct"/>
</equivalent_sites> </equivalent_sites>
<input name="a" num_pins="8"/> <input name="a" num_pins="8"/>
<input name="b" num_pins="8"/> <input name="b" num_pins="8"/>
<output name="out" num_pins="16"/> <output name="out" num_pins="16"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<!-- Highly recommand to customize pin location when direct connection is used!!! --> <!-- Highly recommand to customize pin location when direct connection is used!!! -->
<!-- pinlocations are designed to spread pin on 4 sides evenly --> <!-- pinlocations are designed to spread pin on 4 sides evenly -->
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">mult_8.a[0:3] mult_8.b[0:3] mult_8.out[0:7]</loc> <loc side="left">mult_8.a[0:3] mult_8.b[0:3] mult_8.out[0:7]</loc>
<loc side="top">mult_8.clk</loc> <loc side="top">mult_8.clk</loc>
<loc side="right">mult_8.a[4:7] mult_8.b[4:7] mult_8.out[8:15]</loc> <loc side="right">mult_8.a[4:7] mult_8.b[4:7] mult_8.out[8:15]</loc>
<loc side="bottom"></loc> <loc side="bottom"/>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
<!-- Physical descriptions begin --> <!-- Physical descriptions begin -->
<layout tileable="true"> <layout tileable="true">
<auto_layout aspect_ratio="1.0"> <auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</auto_layout> </auto_layout>
<fixed_layout name="2x2" width="4" height="4"> <fixed_layout name="2x2" width="4" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
<fixed_layout name="3x2" width="5" height="4"> <fixed_layout name="3x2" width="5" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
<!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.--> <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
<col type="mult_8" startx="2" starty="1" repeatx="8" priority="20"/> <col type="mult_8" startx="2" starty="1" repeatx="8" priority="20"/>
<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/> <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
@ -133,21 +132,21 @@
The delay values are lined up with Stratix IV, which has an architecture similar to this The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. --> 4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
--> -->
<area grid_logic_tile_area="0"/> <area grid_logic_tile_area="0"/>
<chan_width_distr> <chan_width_distr>
<x distr="uniform" peak="1.000000"/> <x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/> <y distr="uniform" peak="1.000000"/>
</chan_width_distr> </chan_width_distr>
<switch_block type="wilton" fs="3"/> <switch_block type="wilton" fs="3"/>
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength. book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
@ -159,81 +158,81 @@
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables. 2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. --> This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/> <mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
</segment> </segment>
</segmentlist> </segmentlist>
<complexblocklist> <complexblocklist>
<!-- Define I/O pads begin --> <!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA --> <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. --> <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io"> <pb_type name="io">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- IOs can operate as either inputs or outputs. <!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them. today and that is when you timing analyze them.
--> -->
<mode name="inpad"> <mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<mode name="outpad"> <mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1"> <pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- IOs go on the periphery of the FPGA, for consistency, <!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed. make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
--> -->
<!-- Place I/Os on the sides of the FPGA --> <!-- Place I/Os on the sides of the FPGA -->
<power method="ignore"/> <power method="ignore"/>
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin --> <!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs. area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic This means that only 37% of our area is in the general routing, and 63% is inside the logic
@ -241,69 +240,69 @@
area in this analysis. That is a lower proportion of of routing area than most academics area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range. routing area up significantly, we estimate into the ~70% range.
--> -->
<pb_type name="clb"> <pb_type name="clb">
<input name="I" num_pins="10" equivalent="full"/> <input name="I" num_pins="10" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/> <output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Describe basic logic element. <!-- Describe basic logic element.
Each basic logic element has a 4-LUT that can be optionally registered Each basic logic element has a 4-LUT that can be optionally registered
--> -->
<pb_type name="fle" num_pb="4"> <pb_type name="fle" num_pb="4">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- 4-LUT mode definition begin --> <!-- 4-LUT mode definition begin -->
<mode name="n1_lut4"> <mode name="n1_lut4">
<!-- Define 4-LUT mode --> <!-- Define 4-LUT mode -->
<pb_type name="ble4" num_pb="1"> <pb_type name="ble4" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/> <input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out"> <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/> <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D"> <direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/> <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/> <direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out"> <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/> <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/> <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="ble4.in"/> <direct name="direct1" input="fle.in" output="ble4.in"/>
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/> <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble4.clk"/> <direct name="direct3" input="fle.clk" output="ble4.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- 6-LUT mode definition end --> <!-- 6-LUT mode definition end -->
</pb_type> </pb_type>
<interconnect> <interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB <!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining delay on the connection block input mux (modeled by Ian Kuon), so the remaining
@ -311,132 +310,132 @@
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT. The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. --> to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in"> <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/> <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
</complete> </complete>
<complete name="clks" input="clb.clk" output="fle[3:0].clk"> <complete name="clks" input="clb.clk" output="fle[3:0].clk">
</complete> </complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins. <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification). naive specification).
--> -->
<direct name="clbouts1" input="fle[3:0].out" output="clb.O"/> <direct name="clbouts1" input="fle[3:0].out" output="clb.O"/>
</interconnect> </interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- Place this general purpose logic block in any unspecified column --> <!-- Place this general purpose logic block in any unspecified column -->
</pb_type> </pb_type>
<!-- Define general purpose logic block (CLB) ends --> <!-- Define general purpose logic block (CLB) ends -->
<!-- Define 8-bit multiplier with input and output registers begin --> <!-- Define 8-bit multiplier with input and output registers begin -->
<pb_type name="mult_8"> <pb_type name="mult_8">
<input name="a" num_pins="8"/> <input name="a" num_pins="8"/>
<input name="b" num_pins="8"/> <input name="b" num_pins="8"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<output name="out" num_pins="16"/> <output name="out" num_pins="16"/>
<mode name="mult_8x8"> <mode name="mult_8x8">
<pb_type name="mult_8x8_slice" num_pb="1"> <pb_type name="mult_8x8_slice" num_pb="1">
<input name="A_cfg" num_pins="8"/> <input name="A_cfg" num_pins="8"/>
<input name="B_cfg" num_pins="8"/> <input name="B_cfg" num_pins="8"/>
<output name="OUT_cfg" num_pins="16"/> <output name="OUT_cfg" num_pins="16"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<pb_type name="mult_8x8" blif_model=".subckt mult_8" num_pb="1"> <pb_type name="mult_8x8" blif_model=".subckt mult_8" num_pb="1">
<input name="A" num_pins="8"/> <input name="A" num_pins="8"/>
<input name="B" num_pins="8"/> <input name="B" num_pins="8"/>
<output name="Y" num_pins="16"/> <output name="Y" num_pins="16"/>
<delay_constant max="1.523e-9" min="0.776e-9" in_port="mult_8x8.A" out_port="mult_8x8.Y"/> <delay_constant max="1.523e-9" min="0.776e-9" in_port="mult_8x8.A" out_port="mult_8x8.Y"/>
<delay_constant max="1.523e-9" min="0.776e-9" in_port="mult_8x8.B" out_port="mult_8x8.Y"/> <delay_constant max="1.523e-9" min="0.776e-9" in_port="mult_8x8.B" out_port="mult_8x8.Y"/>
</pb_type> </pb_type>
<pb_type name="ff_A" blif_model=".latch" num_pb="8" class="flipflop"> <pb_type name="ff_A" blif_model=".latch" num_pb="8" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff_A.D" clock="clk"/> <T_setup value="66e-12" port="ff_A.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff_A.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff_A.Q" clock="clk"/>
</pb_type> </pb_type>
<pb_type name="ff_B" blif_model=".latch" num_pb="8" class="flipflop"> <pb_type name="ff_B" blif_model=".latch" num_pb="8" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff_B.D" clock="clk"/> <T_setup value="66e-12" port="ff_B.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff_B.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff_B.Q" clock="clk"/>
</pb_type> </pb_type>
<pb_type name="ff_Y" blif_model=".latch" num_pb="16" class="flipflop"> <pb_type name="ff_Y" blif_model=".latch" num_pb="16" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff_Y.D" clock="clk"/> <T_setup value="66e-12" port="ff_Y.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff_Y.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff_Y.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<mux name="a2a0" input="mult_8x8_slice.A_cfg[0] ff_A[0].Q" output="mult_8x8.A[0]"/> <mux name="a2a0" input="mult_8x8_slice.A_cfg[0] ff_A[0].Q" output="mult_8x8.A[0]"/>
<mux name="a2a1" input="mult_8x8_slice.A_cfg[1] ff_A[1].Q" output="mult_8x8.A[1]"/> <mux name="a2a1" input="mult_8x8_slice.A_cfg[1] ff_A[1].Q" output="mult_8x8.A[1]"/>
<mux name="a2a2" input="mult_8x8_slice.A_cfg[2] ff_A[2].Q" output="mult_8x8.A[2]"/> <mux name="a2a2" input="mult_8x8_slice.A_cfg[2] ff_A[2].Q" output="mult_8x8.A[2]"/>
<mux name="a2a3" input="mult_8x8_slice.A_cfg[3] ff_A[3].Q" output="mult_8x8.A[3]"/> <mux name="a2a3" input="mult_8x8_slice.A_cfg[3] ff_A[3].Q" output="mult_8x8.A[3]"/>
<mux name="a2a4" input="mult_8x8_slice.A_cfg[4] ff_A[4].Q" output="mult_8x8.A[4]"/> <mux name="a2a4" input="mult_8x8_slice.A_cfg[4] ff_A[4].Q" output="mult_8x8.A[4]"/>
<mux name="a2a5" input="mult_8x8_slice.A_cfg[5] ff_A[5].Q" output="mult_8x8.A[5]"/> <mux name="a2a5" input="mult_8x8_slice.A_cfg[5] ff_A[5].Q" output="mult_8x8.A[5]"/>
<mux name="a2a6" input="mult_8x8_slice.A_cfg[6] ff_A[6].Q" output="mult_8x8.A[6]"/> <mux name="a2a6" input="mult_8x8_slice.A_cfg[6] ff_A[6].Q" output="mult_8x8.A[6]"/>
<mux name="a2a7" input="mult_8x8_slice.A_cfg[7] ff_A[7].Q" output="mult_8x8.A[7]"/> <mux name="a2a7" input="mult_8x8_slice.A_cfg[7] ff_A[7].Q" output="mult_8x8.A[7]"/>
<direct name="a2ff" input="mult_8x8_slice.A_cfg[7:0]" output="ff_A[7:0].D"/> <direct name="a2ff" input="mult_8x8_slice.A_cfg[7:0]" output="ff_A[7:0].D"/>
<mux name="b2b0" input="mult_8x8_slice.B_cfg[0] ff_B[0].Q" output="mult_8x8.B[0]"/> <mux name="b2b0" input="mult_8x8_slice.B_cfg[0] ff_B[0].Q" output="mult_8x8.B[0]"/>
<mux name="b2b1" input="mult_8x8_slice.B_cfg[1] ff_B[1].Q" output="mult_8x8.B[1]"/> <mux name="b2b1" input="mult_8x8_slice.B_cfg[1] ff_B[1].Q" output="mult_8x8.B[1]"/>
<mux name="b2b2" input="mult_8x8_slice.B_cfg[2] ff_B[2].Q" output="mult_8x8.B[2]"/> <mux name="b2b2" input="mult_8x8_slice.B_cfg[2] ff_B[2].Q" output="mult_8x8.B[2]"/>
<mux name="b2b3" input="mult_8x8_slice.B_cfg[3] ff_B[3].Q" output="mult_8x8.B[3]"/> <mux name="b2b3" input="mult_8x8_slice.B_cfg[3] ff_B[3].Q" output="mult_8x8.B[3]"/>
<mux name="b2b4" input="mult_8x8_slice.B_cfg[4] ff_B[4].Q" output="mult_8x8.B[4]"/> <mux name="b2b4" input="mult_8x8_slice.B_cfg[4] ff_B[4].Q" output="mult_8x8.B[4]"/>
<mux name="b2b5" input="mult_8x8_slice.B_cfg[5] ff_B[5].Q" output="mult_8x8.B[5]"/> <mux name="b2b5" input="mult_8x8_slice.B_cfg[5] ff_B[5].Q" output="mult_8x8.B[5]"/>
<mux name="b2b6" input="mult_8x8_slice.B_cfg[6] ff_B[6].Q" output="mult_8x8.B[6]"/> <mux name="b2b6" input="mult_8x8_slice.B_cfg[6] ff_B[6].Q" output="mult_8x8.B[6]"/>
<mux name="b2b7" input="mult_8x8_slice.B_cfg[7] ff_B[7].Q" output="mult_8x8.B[7]"/> <mux name="b2b7" input="mult_8x8_slice.B_cfg[7] ff_B[7].Q" output="mult_8x8.B[7]"/>
<direct name="b2ff" input="mult_8x8_slice.B_cfg[7:0]" output="ff_B[7:0].D"/> <direct name="b2ff" input="mult_8x8_slice.B_cfg[7:0]" output="ff_B[7:0].D"/>
<mux name="out2out0" input="mult_8x8.Y[0] ff_Y[0].Q" output="mult_8x8_slice.OUT_cfg[0]"/> <mux name="out2out0" input="mult_8x8.Y[0] ff_Y[0].Q" output="mult_8x8_slice.OUT_cfg[0]"/>
<mux name="out2out1" input="mult_8x8.Y[1] ff_Y[1].Q" output="mult_8x8_slice.OUT_cfg[1]"/> <mux name="out2out1" input="mult_8x8.Y[1] ff_Y[1].Q" output="mult_8x8_slice.OUT_cfg[1]"/>
<mux name="out2out2" input="mult_8x8.Y[2] ff_Y[2].Q" output="mult_8x8_slice.OUT_cfg[2]"/> <mux name="out2out2" input="mult_8x8.Y[2] ff_Y[2].Q" output="mult_8x8_slice.OUT_cfg[2]"/>
<mux name="out2out3" input="mult_8x8.Y[3] ff_Y[3].Q" output="mult_8x8_slice.OUT_cfg[3]"/> <mux name="out2out3" input="mult_8x8.Y[3] ff_Y[3].Q" output="mult_8x8_slice.OUT_cfg[3]"/>
<mux name="out2out4" input="mult_8x8.Y[4] ff_Y[4].Q" output="mult_8x8_slice.OUT_cfg[4]"/> <mux name="out2out4" input="mult_8x8.Y[4] ff_Y[4].Q" output="mult_8x8_slice.OUT_cfg[4]"/>
<mux name="out2out5" input="mult_8x8.Y[5] ff_Y[5].Q" output="mult_8x8_slice.OUT_cfg[5]"/> <mux name="out2out5" input="mult_8x8.Y[5] ff_Y[5].Q" output="mult_8x8_slice.OUT_cfg[5]"/>
<mux name="out2out6" input="mult_8x8.Y[6] ff_Y[6].Q" output="mult_8x8_slice.OUT_cfg[6]"/> <mux name="out2out6" input="mult_8x8.Y[6] ff_Y[6].Q" output="mult_8x8_slice.OUT_cfg[6]"/>
<mux name="out2out7" input="mult_8x8.Y[7] ff_Y[7].Q" output="mult_8x8_slice.OUT_cfg[7]"/> <mux name="out2out7" input="mult_8x8.Y[7] ff_Y[7].Q" output="mult_8x8_slice.OUT_cfg[7]"/>
<mux name="out2out8" input="mult_8x8.Y[8] ff_Y[8].Q" output="mult_8x8_slice.OUT_cfg[8]"/> <mux name="out2out8" input="mult_8x8.Y[8] ff_Y[8].Q" output="mult_8x8_slice.OUT_cfg[8]"/>
<mux name="out2out9" input="mult_8x8.Y[9] ff_Y[9].Q" output="mult_8x8_slice.OUT_cfg[9]"/> <mux name="out2out9" input="mult_8x8.Y[9] ff_Y[9].Q" output="mult_8x8_slice.OUT_cfg[9]"/>
<mux name="out2out10" input="mult_8x8.Y[10] ff_Y[10].Q" output="mult_8x8_slice.OUT_cfg[10]"/> <mux name="out2out10" input="mult_8x8.Y[10] ff_Y[10].Q" output="mult_8x8_slice.OUT_cfg[10]"/>
<mux name="out2out11" input="mult_8x8.Y[11] ff_Y[11].Q" output="mult_8x8_slice.OUT_cfg[11]"/> <mux name="out2out11" input="mult_8x8.Y[11] ff_Y[11].Q" output="mult_8x8_slice.OUT_cfg[11]"/>
<mux name="out2out12" input="mult_8x8.Y[12] ff_Y[12].Q" output="mult_8x8_slice.OUT_cfg[12]"/> <mux name="out2out12" input="mult_8x8.Y[12] ff_Y[12].Q" output="mult_8x8_slice.OUT_cfg[12]"/>
<mux name="out2out13" input="mult_8x8.Y[13] ff_Y[13].Q" output="mult_8x8_slice.OUT_cfg[13]"/> <mux name="out2out13" input="mult_8x8.Y[13] ff_Y[13].Q" output="mult_8x8_slice.OUT_cfg[13]"/>
<mux name="out2out14" input="mult_8x8.Y[14] ff_Y[14].Q" output="mult_8x8_slice.OUT_cfg[14]"/> <mux name="out2out14" input="mult_8x8.Y[14] ff_Y[14].Q" output="mult_8x8_slice.OUT_cfg[14]"/>
<mux name="out2out15" input="mult_8x8.Y[15] ff_Y[15].Q" output="mult_8x8_slice.OUT_cfg[15]"/> <mux name="out2out15" input="mult_8x8.Y[15] ff_Y[15].Q" output="mult_8x8_slice.OUT_cfg[15]"/>
<direct name="out2ff" input="mult_8x8.Y[15:0]" output="ff_Y[15:0].D"/> <direct name="out2ff" input="mult_8x8.Y[15:0]" output="ff_Y[15:0].D"/>
<complete name="clk_ff_A" input="mult_8x8_slice.clk" output="ff_A.clk"/> <complete name="clk_ff_A" input="mult_8x8_slice.clk" output="ff_A.clk"/>
<complete name="clk_ff_B" input="mult_8x8_slice.clk" output="ff_B.clk"/> <complete name="clk_ff_B" input="mult_8x8_slice.clk" output="ff_B.clk"/>
<complete name="clk_ff_Y" input="mult_8x8_slice.clk" output="ff_Y.clk"/> <complete name="clk_ff_Y" input="mult_8x8_slice.clk" output="ff_Y.clk"/>
</interconnect> </interconnect>
<power method="pin-toggle"> <power method="pin-toggle">
<port name="A_cfg" energy_per_toggle="2.13e-12"/> <port name="A_cfg" energy_per_toggle="2.13e-12"/>
<port name="B_cfg" energy_per_toggle="2.13e-12"/> <port name="B_cfg" energy_per_toggle="2.13e-12"/>
<static_power power_per_instance="0.0"/> <static_power power_per_instance="0.0"/>
</power> </power>
</pb_type> </pb_type>
<interconnect> <interconnect>
<!-- Stratix IV input delay of 207ps is conservative for this architecture because this architecture does not have an input crossbar in the multiplier. <!-- Stratix IV input delay of 207ps is conservative for this architecture because this architecture does not have an input crossbar in the multiplier.
Subtract 72.5 ps delay, which is already in the connection block input mux, leading Subtract 72.5 ps delay, which is already in the connection block input mux, leading
to a 134 ps delay. to a 134 ps delay.
The interconnect difference for DSP blocks is 0.5523, which leads to a minimum delay of 74 ps The interconnect difference for DSP blocks is 0.5523, which leads to a minimum delay of 74 ps
--> -->
<direct name="a2a" input="mult_8.a" output="mult_8x8_slice.A_cfg"> <direct name="a2a" input="mult_8.a" output="mult_8x8_slice.A_cfg">
<delay_constant max="134e-12" min="74e-12" in_port="mult_8.a" out_port="mult_8x8_slice.A_cfg"/> <delay_constant max="134e-12" min="74e-12" in_port="mult_8.a" out_port="mult_8x8_slice.A_cfg"/>
</direct> </direct>
<direct name="b2b" input="mult_8.b" output="mult_8x8_slice.B_cfg"> <direct name="b2b" input="mult_8.b" output="mult_8x8_slice.B_cfg">
<delay_constant max="134e-12" min="74e-12" in_port="mult_8.b" out_port="mult_8x8_slice.B_cfg"/> <delay_constant max="134e-12" min="74e-12" in_port="mult_8.b" out_port="mult_8x8_slice.B_cfg"/>
</direct> </direct>
<direct name="out2out" input="mult_8x8_slice.OUT_cfg" output="mult_8.out"> <direct name="out2out" input="mult_8x8_slice.OUT_cfg" output="mult_8.out">
<delay_constant max="1.93e-9" min="74e-12" in_port="mult_8x8_slice.OUT_cfg" out_port="mult_8.out"/> <delay_constant max="1.93e-9" min="74e-12" in_port="mult_8x8_slice.OUT_cfg" out_port="mult_8.out"/>
</direct> </direct>
<complete name="clk" input="mult_8.clk" output="mult_8x8_slice.clk"/> <complete name="clk" input="mult_8.clk" output="mult_8x8_slice.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- Place this multiplier block every 8 columns from (and including) the sixth column --> <!-- Place this multiplier block every 8 columns from (and including) the sixth column -->
<power method="sum-of-children"/> <power method="sum-of-children"/>
</pb_type> </pb_type>
<!-- Define fracturable multiplier end --> <!-- Define fracturable multiplier end -->
</complexblocklist> </complexblocklist>
</architecture> </architecture>

441
openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml
View File

@ -1,4 +1,4 @@
<!-- <?xml version="1.0" ?><!--
Architecture with no fracturable LUTs Architecture with no fracturable LUTs
- 40 nm technology - 40 nm technology
@ -13,9 +13,8 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--> --><architecture>
<architecture> <!--
<!--
ODIN II specific config begins ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports. ".model [type_of_block]") that this architecture supports.
@ -23,64 +22,64 @@
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch) already special structures in blif (.names, .input, .output, and .latch)
that describe them. that describe them.
--> -->
<models> <models>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io"> <model name="io">
<input_ports> <input_ports>
<port name="outpad"/> <port name="outpad"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="inpad"/> <port name="inpad"/>
</output_ports> </output_ports>
</model> </model>
</models> </models>
<tiles> <tiles>
<tile name="io" capacity="8" area="0"> <tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc> <loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc> <loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc> <loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc> <loc side="bottom">io.outpad io.inpad</loc>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
<tile name="clb" area="53894"> <tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites> <equivalent_sites>
<site pb_type="clb"/> <site pb_type="clb"/>
</equivalent_sites> </equivalent_sites>
<input name="I" num_pins="10" equivalent="full"/> <input name="I" num_pins="10" equivalent="full"/>
<output name="O" num_pins="4" equivalent="full"/> <output name="O" num_pins="4" equivalent="full"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/> <pinlocations pattern="spread"/>
</tile> </sub_tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
<!-- Physical descriptions begin --> <!-- Physical descriptions begin -->
<layout tileable="true"> <layout tileable="true">
<auto_layout aspect_ratio="1.0"> <auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</auto_layout> </auto_layout>
<fixed_layout name="2x2" width="4" height="4"> <fixed_layout name="2x2" width="4" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
@ -94,21 +93,21 @@
The delay values are lined up with Stratix IV, which has an architecture similar to this The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. --> 4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
--> -->
<area grid_logic_tile_area="0"/> <area grid_logic_tile_area="0"/>
<chan_width_distr> <chan_width_distr>
<x distr="uniform" peak="1.000000"/> <x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/> <y distr="uniform" peak="1.000000"/>
</chan_width_distr> </chan_width_distr>
<switch_block type="wilton" fs="3"/> <switch_block type="wilton" fs="3"/>
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength. book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
@ -120,81 +119,81 @@
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables. 2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. --> This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/> <mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
</segment> </segment>
</segmentlist> </segmentlist>
<complexblocklist> <complexblocklist>
<!-- Define I/O pads begin --> <!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA --> <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. --> <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io"> <pb_type name="io">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- IOs can operate as either inputs or outputs. <!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them. today and that is when you timing analyze them.
--> -->
<mode name="inpad"> <mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<mode name="outpad"> <mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1"> <pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- IOs go on the periphery of the FPGA, for consistency, <!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed. make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
--> -->
<!-- Place I/Os on the sides of the FPGA --> <!-- Place I/Os on the sides of the FPGA -->
<power method="ignore"/> <power method="ignore"/>
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin --> <!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs. area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic This means that only 37% of our area is in the general routing, and 63% is inside the logic
@ -202,69 +201,69 @@
area in this analysis. That is a lower proportion of of routing area than most academics area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range. routing area up significantly, we estimate into the ~70% range.
--> -->
<pb_type name="clb"> <pb_type name="clb">
<input name="I" num_pins="10" equivalent="full"/> <input name="I" num_pins="10" equivalent="full"/>
<output name="O" num_pins="4" equivalent="full"/> <output name="O" num_pins="4" equivalent="full"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Describe basic logic element. <!-- Describe basic logic element.
Each basic logic element has a 4-LUT that can be optionally registered Each basic logic element has a 4-LUT that can be optionally registered
--> -->
<pb_type name="fle" num_pb="4"> <pb_type name="fle" num_pb="4">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- 4-LUT mode definition begin --> <!-- 4-LUT mode definition begin -->
<mode name="n1_lut4"> <mode name="n1_lut4">
<!-- Define 4-LUT mode --> <!-- Define 4-LUT mode -->
<pb_type name="ble4" num_pb="1"> <pb_type name="ble4" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/> <input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out"> <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/> <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D"> <direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/> <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/> <direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out"> <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/> <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/> <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="ble4.in"/> <direct name="direct1" input="fle.in" output="ble4.in"/>
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/> <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble4.clk"/> <direct name="direct3" input="fle.clk" output="ble4.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- 6-LUT mode definition end --> <!-- 6-LUT mode definition end -->
</pb_type> </pb_type>
<interconnect> <interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB <!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining delay on the connection block input mux (modeled by Ian Kuon), so the remaining
@ -272,25 +271,25 @@
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT. The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. --> to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in"> <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/> <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
</complete> </complete>
<complete name="clks" input="clb.clk" output="fle[3:0].clk"> <complete name="clks" input="clb.clk" output="fle[3:0].clk">
</complete> </complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins. <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification). naive specification).
--> -->
<complete name="output_crossbar" input="fle[3:0].out" output="clb.O"> <complete name="output_crossbar" input="fle[3:0].out" output="clb.O">
<delay_constant max="45e-12" in_port="fle[3:0].out" out_port="clb.O"/> <delay_constant max="45e-12" in_port="fle[3:0].out" out_port="clb.O"/>
</complete> </complete>
</interconnect> </interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- Place this general purpose logic block in any unspecified column --> <!-- Place this general purpose logic block in any unspecified column -->
</pb_type> </pb_type>
<!-- Define general purpose logic block (CLB) ends --> <!-- Define general purpose logic block (CLB) ends -->
</complexblocklist> </complexblocklist>
</architecture> </architecture>

449
openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
View File

@ -1,4 +1,4 @@
<!-- <?xml version="1.0" ?><!--
Architecture with no fracturable LUTs Architecture with no fracturable LUTs
- 40 nm technology - 40 nm technology
@ -13,9 +13,8 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--> --><architecture>
<architecture> <!--
<!--
ODIN II specific config begins ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports. ".model [type_of_block]") that this architecture supports.
@ -23,67 +22,67 @@
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch) already special structures in blif (.names, .input, .output, and .latch)
that describe them. that describe them.
--> -->
<models> <models>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io"> <model name="io">
<input_ports> <input_ports>
<port name="outpad"/> <port name="outpad"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="inpad"/> <port name="inpad"/>
</output_ports> </output_ports>
</model> </model>
</models> </models>
<tiles> <tiles>
<tile name="io" capacity="8" area="0"> <tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc> <loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc> <loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc> <loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc> <loc side="bottom">io.outpad io.inpad</loc>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
<tile name="clb" area="53894"> <tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites> <equivalent_sites>
<site pb_type="clb"/> <site pb_type="clb"/>
</equivalent_sites> </equivalent_sites>
<input name="I0" num_pins="4" equivalent="full"/> <input name="I0" num_pins="4" equivalent="full"/>
<input name="I1" num_pins="4" equivalent="full"/> <input name="I1" num_pins="4" equivalent="full"/>
<input name="I2" num_pins="4" equivalent="full"/> <input name="I2" num_pins="4" equivalent="full"/>
<input name="I3" num_pins="4" equivalent="full"/> <input name="I3" num_pins="4" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/> <output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/> <pinlocations pattern="spread"/>
</tile> </sub_tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
<!-- Physical descriptions begin --> <!-- Physical descriptions begin -->
<layout tileable="true"> <layout tileable="true">
<auto_layout aspect_ratio="1.0"> <auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</auto_layout> </auto_layout>
<fixed_layout name="2x2" width="4" height="4"> <fixed_layout name="2x2" width="4" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
@ -97,21 +96,21 @@
The delay values are lined up with Stratix IV, which has an architecture similar to this The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. --> 4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
--> -->
<area grid_logic_tile_area="0"/> <area grid_logic_tile_area="0"/>
<chan_width_distr> <chan_width_distr>
<x distr="uniform" peak="1.000000"/> <x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/> <y distr="uniform" peak="1.000000"/>
</chan_width_distr> </chan_width_distr>
<switch_block type="wilton" fs="3"/> <switch_block type="wilton" fs="3"/>
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength. book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
@ -123,81 +122,81 @@
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables. 2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. --> This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/> <mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
</segment> </segment>
</segmentlist> </segmentlist>
<complexblocklist> <complexblocklist>
<!-- Define I/O pads begin --> <!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA --> <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. --> <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io"> <pb_type name="io">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- IOs can operate as either inputs or outputs. <!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them. today and that is when you timing analyze them.
--> -->
<mode name="inpad"> <mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<mode name="outpad"> <mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1"> <pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- IOs go on the periphery of the FPGA, for consistency, <!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed. make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
--> -->
<!-- Place I/Os on the sides of the FPGA --> <!-- Place I/Os on the sides of the FPGA -->
<power method="ignore"/> <power method="ignore"/>
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin --> <!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs. area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic This means that only 37% of our area is in the general routing, and 63% is inside the logic
@ -205,91 +204,91 @@
area in this analysis. That is a lower proportion of of routing area than most academics area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range. routing area up significantly, we estimate into the ~70% range.
--> -->
<pb_type name="clb"> <pb_type name="clb">
<!-- FIXME These inputs should be logic equivalent <!-- FIXME These inputs should be logic equivalent
However, current annotation engine does not support this However, current annotation engine does not support this
The feature should be enabled after patching The feature should be enabled after patching
--> -->
<input name="I0" num_pins="4" equivalent="full"/> <input name="I0" num_pins="4" equivalent="full"/>
<input name="I1" num_pins="4" equivalent="full"/> <input name="I1" num_pins="4" equivalent="full"/>
<input name="I2" num_pins="4" equivalent="full"/> <input name="I2" num_pins="4" equivalent="full"/>
<input name="I3" num_pins="4" equivalent="full"/> <input name="I3" num_pins="4" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/> <output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Describe basic logic element. <!-- Describe basic logic element.
Each basic logic element has a 4-LUT that can be optionally registered Each basic logic element has a 4-LUT that can be optionally registered
--> -->
<pb_type name="fle" num_pb="4"> <pb_type name="fle" num_pb="4">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- 4-LUT mode definition begin --> <!-- 4-LUT mode definition begin -->
<mode name="n1_lut4"> <mode name="n1_lut4">
<!-- Define 4-LUT mode --> <!-- Define 4-LUT mode -->
<pb_type name="ble4" num_pb="1"> <pb_type name="ble4" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/> <input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out"> <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/> <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D"> <direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/> <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/> <direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out"> <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/> <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/> <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="ble4.in"/> <direct name="direct1" input="fle.in" output="ble4.in"/>
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/> <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble4.clk"/> <direct name="direct3" input="fle.clk" output="ble4.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- 6-LUT mode definition end --> <!-- 6-LUT mode definition end -->
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="crossbar0" input="clb.I0" output="fle[0:0].in"/> <direct name="crossbar0" input="clb.I0" output="fle[0:0].in"/>
<direct name="crossbar1" input="clb.I1" output="fle[1:1].in"/> <direct name="crossbar1" input="clb.I1" output="fle[1:1].in"/>
<direct name="crossbar2" input="clb.I2" output="fle[2:2].in"/> <direct name="crossbar2" input="clb.I2" output="fle[2:2].in"/>
<direct name="crossbar3" input="clb.I3" output="fle[3:3].in"/> <direct name="crossbar3" input="clb.I3" output="fle[3:3].in"/>
<complete name="clks" input="clb.clk" output="fle[3:0].clk"> <complete name="clks" input="clb.clk" output="fle[3:0].clk">
</complete> </complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins. <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification). naive specification).
--> -->
<direct name="output_crossbar" input="fle[3:0].out" output="clb.O"/> <direct name="output_crossbar" input="fle[3:0].out" output="clb.O"/>
</interconnect> </interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- Place this general purpose logic block in any unspecified column --> <!-- Place this general purpose logic block in any unspecified column -->
</pb_type> </pb_type>
<!-- Define general purpose logic block (CLB) ends --> <!-- Define general purpose logic block (CLB) ends -->
</complexblocklist> </complexblocklist>
</architecture> </architecture>

561
openfpga_flow/vpr_arch/k4_N5_tileable_pattern_local_routing_40nm.xml
View File

@ -1,4 +1,4 @@
<!-- <?xml version="1.0" ?><!--
Architecture with no fracturable LUTs Architecture with no fracturable LUTs
- 40 nm technology - 40 nm technology
@ -12,9 +12,8 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--> --><architecture>
<architecture> <!--
<!--
ODIN II specific config begins ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports. ".model [type_of_block]") that this architecture supports.
@ -22,64 +21,64 @@
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch) already special structures in blif (.names, .input, .output, and .latch)
that describe them. that describe them.
--> -->
<models> <models>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io"> <model name="io">
<input_ports> <input_ports>
<port name="outpad"/> <port name="outpad"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="inpad"/> <port name="inpad"/>
</output_ports> </output_ports>
</model> </model>
</models> </models>
<tiles> <tiles>
<tile name="io" capacity="8" area="0"> <tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc> <loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc> <loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc> <loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc> <loc side="bottom">io.outpad io.inpad</loc>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
<tile name="clb" area="53894"> <tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites> <equivalent_sites>
<site pb_type="clb"/> <site pb_type="clb"/>
</equivalent_sites> </equivalent_sites>
<input name="I" num_pins="12" equivalent="full"/> <input name="I" num_pins="12" equivalent="full"/>
<output name="O" num_pins="5" equivalent="none"/> <output name="O" num_pins="5" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/> <pinlocations pattern="spread"/>
</tile> </sub_tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
<!-- Physical descriptions begin --> <!-- Physical descriptions begin -->
<layout tileable="true"> <layout tileable="true">
<auto_layout aspect_ratio="1.0"> <auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</auto_layout> </auto_layout>
<fixed_layout name="2x2" width="4" height="4"> <fixed_layout name="2x2" width="4" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
@ -93,21 +92,21 @@
The delay values are lined up with Stratix IV, which has an architecture similar to this The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. --> 4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
--> -->
<area grid_logic_tile_area="0"/> <area grid_logic_tile_area="0"/>
<chan_width_distr> <chan_width_distr>
<x distr="uniform" peak="1.000000"/> <x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/> <y distr="uniform" peak="1.000000"/>
</chan_width_distr> </chan_width_distr>
<switch_block type="wilton" fs="3"/> <switch_block type="wilton" fs="3"/>
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength. book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
@ -119,81 +118,81 @@
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables. 2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. --> This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/> <mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
</segment> </segment>
</segmentlist> </segmentlist>
<complexblocklist> <complexblocklist>
<!-- Define I/O pads begin --> <!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA --> <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. --> <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io"> <pb_type name="io">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- IOs can operate as either inputs or outputs. <!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them. today and that is when you timing analyze them.
--> -->
<mode name="inpad"> <mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<mode name="outpad"> <mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1"> <pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- IOs go on the periphery of the FPGA, for consistency, <!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed. make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
--> -->
<!-- Place I/Os on the sides of the FPGA --> <!-- Place I/Os on the sides of the FPGA -->
<power method="ignore"/> <power method="ignore"/>
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin --> <!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs. area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic This means that only 37% of our area is in the general routing, and 63% is inside the logic
@ -201,73 +200,73 @@
area in this analysis. That is a lower proportion of of routing area than most academics area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range. routing area up significantly, we estimate into the ~70% range.
--> -->
<pb_type name="clb"> <pb_type name="clb">
<input name="I" num_pins="12" equivalent="full"/> <input name="I" num_pins="12" equivalent="full"/>
<output name="O" num_pins="5" equivalent="none"/> <output name="O" num_pins="5" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Describe basic logic element. <!-- Describe basic logic element.
Each basic logic element has a 4-LUT that can be optionally registered Each basic logic element has a 4-LUT that can be optionally registered
--> -->
<pb_type name="fle" num_pb="5"> <pb_type name="fle" num_pb="5">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<output name="lut_out" num_pins="1"/> <output name="lut_out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- 4-LUT mode definition begin --> <!-- 4-LUT mode definition begin -->
<mode name="n1_lut4"> <mode name="n1_lut4">
<!-- Define 4-LUT mode --> <!-- Define 4-LUT mode -->
<pb_type name="ble4" num_pb="1"> <pb_type name="ble4" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="lut_out" num_pins="1"/> <output name="lut_out" num_pins="1"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/> <input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out"> <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/> <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D"> <direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/> <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="lut4.out" output="ble4.lut_out"/> <direct name="direct3" input="lut4.out" output="ble4.lut_out"/>
<direct name="direct4" input="ble4.clk" output="ff.clk"/> <direct name="direct4" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out"> <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/> <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/> <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="ble4.in"/> <direct name="direct1" input="fle.in" output="ble4.in"/>
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/> <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
<direct name="direct3" input="ble4.lut_out" output="fle.lut_out[0:0]"/> <direct name="direct3" input="ble4.lut_out" output="fle.lut_out[0:0]"/>
<direct name="direct4" input="fle.clk" output="ble4.clk"/> <direct name="direct4" input="fle.clk" output="ble4.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- 6-LUT mode definition end --> <!-- 6-LUT mode definition end -->
</pb_type> </pb_type>
<interconnect> <interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB <!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining delay on the connection block input mux (modeled by Ian Kuon), so the remaining
@ -275,81 +274,81 @@
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT. The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. --> to get the part that should be marked on the crossbar. -->
<!-- Local routing for FLE[0] inputs --> <!-- Local routing for FLE[0] inputs -->
<complete name="crossbar_fle0" input="clb.I fle[4:0].out" output="fle[0:0].in"> <complete name="crossbar_fle0" input="clb.I fle[4:0].out" output="fle[0:0].in">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[0:0].in"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[0:0].in"/>
<delay_constant max="75e-12" in_port="fle[4:0].out" out_port="fle[0:0].in"/> <delay_constant max="75e-12" in_port="fle[4:0].out" out_port="fle[0:0].in"/>
</complete> </complete>
<!-- Local routing for FLE[1] inputs --> <!-- Local routing for FLE[1] inputs -->
<complete name="crossbar_fle1_in0" input="clb.I fle[4:0].out fle[0:0].lut_out" output="fle[1:1].in[0]"> <complete name="crossbar_fle1_in0" input="clb.I fle[4:0].out fle[0:0].lut_out" output="fle[1:1].in[0]">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[1:1].in[0]"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[1:1].in[0]"/>
<delay_constant max="75e-12" in_port="fle[4:0].out fle[0:0].lut_out" out_port="fle[1:1].in[0]"/> <delay_constant max="75e-12" in_port="fle[4:0].out fle[0:0].lut_out" out_port="fle[1:1].in[0]"/>
</complete> </complete>
<complete name="crossbar_fle1" input="clb.I fle[4:0].out" output="fle[1:1].in[1:3]"> <complete name="crossbar_fle1" input="clb.I fle[4:0].out" output="fle[1:1].in[1:3]">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[1:1].in[1:3]"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[1:1].in[1:3]"/>
<delay_constant max="75e-12" in_port="fle[4:0].out" out_port="fle[1:1].in[1:3]"/> <delay_constant max="75e-12" in_port="fle[4:0].out" out_port="fle[1:1].in[1:3]"/>
</complete> </complete>
<!-- Local routing for FLE[2] inputs --> <!-- Local routing for FLE[2] inputs -->
<complete name="crossbar_fle2_in0" input="clb.I fle[4:0].out fle[0:0].lut_out" output="fle[2:2].in[0]"> <complete name="crossbar_fle2_in0" input="clb.I fle[4:0].out fle[0:0].lut_out" output="fle[2:2].in[0]">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[2:2].in[0]"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[2:2].in[0]"/>
<delay_constant max="75e-12" in_port="fle[4:0].out fle[0:0].lut_out" out_port="fle[2:2].in[0]"/> <delay_constant max="75e-12" in_port="fle[4:0].out fle[0:0].lut_out" out_port="fle[2:2].in[0]"/>
</complete> </complete>
<complete name="crossbar_fle2_in1" input="clb.I fle[4:0].out fle[1:1].lut_out" output="fle[2:2].in[1]"> <complete name="crossbar_fle2_in1" input="clb.I fle[4:0].out fle[1:1].lut_out" output="fle[2:2].in[1]">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[2:2].in[1]"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[2:2].in[1]"/>
<delay_constant max="75e-12" in_port="fle[4:0].out fle[1:1].lut_out" out_port="fle[2:2].in[1]"/> <delay_constant max="75e-12" in_port="fle[4:0].out fle[1:1].lut_out" out_port="fle[2:2].in[1]"/>
</complete> </complete>
<complete name="crossbar_fle2" input="clb.I fle[4:0].out" output="fle[2:2].in[2:3]"> <complete name="crossbar_fle2" input="clb.I fle[4:0].out" output="fle[2:2].in[2:3]">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[2:2].in[2:3]"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[2:2].in[2:3]"/>
<delay_constant max="75e-12" in_port="fle[4:0].out" out_port="fle[2:2].in[2:3]"/> <delay_constant max="75e-12" in_port="fle[4:0].out" out_port="fle[2:2].in[2:3]"/>
</complete> </complete>
<!-- Local routing for FLE[3] inputs --> <!-- Local routing for FLE[3] inputs -->
<complete name="crossbar_fle3_in0" input="clb.I fle[4:0].out fle[0:0].lut_out" output="fle[3:3].in[0]"> <complete name="crossbar_fle3_in0" input="clb.I fle[4:0].out fle[0:0].lut_out" output="fle[3:3].in[0]">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:3].in[0]"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:3].in[0]"/>
<delay_constant max="75e-12" in_port="fle[4:0].out fle[0:0].lut_out" out_port="fle[3:3].in[0]"/> <delay_constant max="75e-12" in_port="fle[4:0].out fle[0:0].lut_out" out_port="fle[3:3].in[0]"/>
</complete> </complete>
<complete name="crossbar_fle3_in1" input="clb.I fle[4:0].out fle[1:1].lut_out" output="fle[3:3].in[1]"> <complete name="crossbar_fle3_in1" input="clb.I fle[4:0].out fle[1:1].lut_out" output="fle[3:3].in[1]">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:3].in[1]"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:3].in[1]"/>
<delay_constant max="75e-12" in_port="fle[4:0].out fle[1:1].lut_out" out_port="fle[3:3].in[1]"/> <delay_constant max="75e-12" in_port="fle[4:0].out fle[1:1].lut_out" out_port="fle[3:3].in[1]"/>
</complete> </complete>
<complete name="crossbar_fle3_in2" input="clb.I fle[4:0].out fle[2:2].lut_out" output="fle[3:3].in[2]"> <complete name="crossbar_fle3_in2" input="clb.I fle[4:0].out fle[2:2].lut_out" output="fle[3:3].in[2]">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:3].in[2]"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:3].in[2]"/>
<delay_constant max="75e-12" in_port="fle[4:0].out fle[2:2].lut_out" out_port="fle[3:3].in[2]"/> <delay_constant max="75e-12" in_port="fle[4:0].out fle[2:2].lut_out" out_port="fle[3:3].in[2]"/>
</complete> </complete>
<complete name="crossbar_fle3" input="clb.I fle[4:0].out" output="fle[3:3].in[3:3]"> <complete name="crossbar_fle3" input="clb.I fle[4:0].out" output="fle[3:3].in[3:3]">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:3].in[3:3]"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:3].in[3:3]"/>
<delay_constant max="75e-12" in_port="fle[4:0].out" out_port="fle[3:3].in[3:3]"/> <delay_constant max="75e-12" in_port="fle[4:0].out" out_port="fle[3:3].in[3:3]"/>
</complete> </complete>
<!-- Local routing for FLE[4] inputs --> <!-- Local routing for FLE[4] inputs -->
<complete name="crossbar_fle4_in0" input="clb.I fle[4:0].out fle[0:0].lut_out" output="fle[4:4].in[0]"> <complete name="crossbar_fle4_in0" input="clb.I fle[4:0].out fle[0:0].lut_out" output="fle[4:4].in[0]">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[4:4].in[0]"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[4:4].in[0]"/>
<delay_constant max="75e-12" in_port="fle[4:0].out fle[0:0].lut_out" out_port="fle[4:4].in[0]"/> <delay_constant max="75e-12" in_port="fle[4:0].out fle[0:0].lut_out" out_port="fle[4:4].in[0]"/>
</complete> </complete>
<complete name="crossbar_fle4_in1" input="clb.I fle[4:0].out fle[1:1].lut_out" output="fle[4:4].in[1]"> <complete name="crossbar_fle4_in1" input="clb.I fle[4:0].out fle[1:1].lut_out" output="fle[4:4].in[1]">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[4:4].in[1]"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[4:4].in[1]"/>
<delay_constant max="75e-12" in_port="fle[4:0].out fle[1:1].lut_out" out_port="fle[4:4].in[1]"/> <delay_constant max="75e-12" in_port="fle[4:0].out fle[1:1].lut_out" out_port="fle[4:4].in[1]"/>
</complete> </complete>
<complete name="crossbar_fle4_in2" input="clb.I fle[4:0].out fle[2:2].lut_out" output="fle[4:4].in[2]"> <complete name="crossbar_fle4_in2" input="clb.I fle[4:0].out fle[2:2].lut_out" output="fle[4:4].in[2]">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[4:4].in[2]"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[4:4].in[2]"/>
<delay_constant max="75e-12" in_port="fle[4:0].out fle[2:2].lut_out" out_port="fle[4:4].in[2]"/> <delay_constant max="75e-12" in_port="fle[4:0].out fle[2:2].lut_out" out_port="fle[4:4].in[2]"/>
</complete> </complete>
<complete name="crossbar_fle4_in3" input="clb.I fle[4:0].out fle[3:3].lut_out" output="fle[4:4].in[3]"> <complete name="crossbar_fle4_in3" input="clb.I fle[4:0].out fle[3:3].lut_out" output="fle[4:4].in[3]">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[4:4].in[3]"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[4:4].in[3]"/>
<delay_constant max="75e-12" in_port="fle[4:0].out fle[3:3].lut_out" out_port="fle[4:4].in[3]"/> <delay_constant max="75e-12" in_port="fle[4:0].out fle[3:3].lut_out" out_port="fle[4:4].in[3]"/>
</complete> </complete>
<!-- Local clock connections --> <!-- Local clock connections -->
<complete name="clks" input="clb.clk" output="fle[4:0].clk"> <complete name="clks" input="clb.clk" output="fle[4:0].clk">
</complete> </complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins. <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification). naive specification).
--> -->
<direct name="clbouts1" input="fle[4:0].out" output="clb.O"/> <direct name="clbouts1" input="fle[4:0].out" output="clb.O"/>
</interconnect> </interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- Place this general purpose logic block in any unspecified column --> <!-- Place this general purpose logic block in any unspecified column -->
</pb_type> </pb_type>
<!-- Define general purpose logic block (CLB) ends --> <!-- Define general purpose logic block (CLB) ends -->
</complexblocklist> </complexblocklist>
</architecture> </architecture>

661
openfpga_flow/vpr_arch/k4_fracNative_N4_tileable_40nm.xml
View File

@ -1,4 +1,4 @@
<!-- <?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0. Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
- 40 nm technology - 40 nm technology
@ -12,9 +12,8 @@
Based on flagship k4_frac_N4_mem32K_40nm.xml architecture. Based on flagship k4_frac_N4_mem32K_40nm.xml architecture.
Authors: Jason Luu, Jeff Goeders, Vaughn Betz Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--> --><architecture>
<architecture> <!--
<!--
ODIN II specific config begins ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports. ".model [type_of_block]") that this architecture supports.
@ -22,85 +21,85 @@
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch) already special structures in blif (.names, .input, .output, and .latch)
that describe them. that describe them.
--> -->
<models> <models>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io"> <model name="io">
<input_ports> <input_ports>
<port name="outpad"/> <port name="outpad"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="inpad"/> <port name="inpad"/>
</output_ports> </output_ports>
</model> </model>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="frac_lut4"> <model name="frac_lut4">
<input_ports> <input_ports>
<port name="in"/> <port name="in"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="lut3_out"/> <port name="lut3_out"/>
<port name="lut4_out"/> <port name="lut4_out"/>
</output_ports> </output_ports>
</model> </model>
</models> </models>
<tiles> <tiles>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
If you need to register the I/O, define clocks in the circuit models If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end These clocks can be handled in back-end
--> -->
<tile name="io" capacity="8" area="0"> <tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc> <loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc> <loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc> <loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc> <loc side="bottom">io.outpad io.inpad</loc>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
<tile name="clb" area="53894"> <tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites> <equivalent_sites>
<site pb_type="clb"/> <site pb_type="clb"/>
</equivalent_sites> </equivalent_sites>
<input name="I" num_pins="12" equivalent="full"/> <input name="I" num_pins="12" equivalent="full"/>
<output name="O" num_pins="8" equivalent="none"/> <output name="O" num_pins="8" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/> <pinlocations pattern="spread"/>
</tile> </sub_tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
<!-- Physical descriptions begin --> <!-- Physical descriptions begin -->
<layout tileable="true"> <layout tileable="true">
<auto_layout aspect_ratio="1.0"> <auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</auto_layout> </auto_layout>
<fixed_layout name="2x2" width="4" height="4"> <fixed_layout name="2x2" width="4" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
<fixed_layout name="4x4" width="6" height="6"> <fixed_layout name="4x4" width="6" height="6">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
@ -114,21 +113,21 @@
The delay values are lined up with Stratix IV, which has an architecture similar to this The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. --> 4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
--> -->
<area grid_logic_tile_area="0"/> <area grid_logic_tile_area="0"/>
<chan_width_distr> <chan_width_distr>
<x distr="uniform" peak="1.000000"/> <x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/> <y distr="uniform" peak="1.000000"/>
</chan_width_distr> </chan_width_distr>
<switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/> <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength. book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
@ -140,87 +139,87 @@
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables. 2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. --> This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! --> <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/> <mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
</segment> </segment>
</segmentlist> </segmentlist>
<complexblocklist> <complexblocklist>
<!-- Define I/O pads begin --> <!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA --> <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. --> <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io"> <pb_type name="io">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
If you need to register the I/O, define clocks in the circuit models If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end These clocks can be handled in back-end
--> -->
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- IOs can operate as either inputs or outputs. <!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them. today and that is when you timing analyze them.
--> -->
<mode name="inpad"> <mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<mode name="outpad"> <mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1"> <pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- IOs go on the periphery of the FPGA, for consistency, <!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed. make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
--> -->
<!-- Place I/Os on the sides of the FPGA --> <!-- Place I/Os on the sides of the FPGA -->
<power method="ignore"/> <power method="ignore"/>
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin --> <!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs. area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic This means that only 37% of our area is in the general routing, and 63% is inside the logic
@ -228,168 +227,168 @@
area in this analysis. That is a lower proportion of of routing area than most academics area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range. routing area up significantly, we estimate into the ~70% range.
--> -->
<pb_type name="clb"> <pb_type name="clb">
<input name="I" num_pins="12" equivalent="full"/> <input name="I" num_pins="12" equivalent="full"/>
<output name="O" num_pins="8" equivalent="none"/> <output name="O" num_pins="8" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Describe fracturable logic element. <!-- Describe fracturable logic element.
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
The outputs of the fracturable logic element can be optionally registered The outputs of the fracturable logic element can be optionally registered
--> -->
<pb_type name="fle" num_pb="4"> <pb_type name="fle" num_pb="4">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<pb_type name="frac_logic" num_pb="1"> <pb_type name="frac_logic" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<!-- Define a native (no mode switch) 4-input fracturable LUT <!-- Define a native (no mode switch) 4-input fracturable LUT
Different from standard fracturable LUT4 whose input can be tri-stated Different from standard fracturable LUT4 whose input can be tri-stated
to enable fracturable output, to enable fracturable output,
The native fracturable LUT4 has a LUT3 output without any switches The native fracturable LUT4 has a LUT3 output without any switches
to enable it. Therefore, none of its inputs will be tri-stated to enable it. Therefore, none of its inputs will be tri-stated
The LUT3 output is directly wired to an internal point of LUT4 The LUT3 output is directly wired to an internal point of LUT4
which can be considered a spy output which can be considered a spy output
--> -->
<pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1"> <pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="lut3_out" num_pins="1"/> <output name="lut3_out" num_pins="1"/>
<output name="lut4_out" num_pins="1"/> <output name="lut4_out" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="frac_logic.in" output="frac_lut4.in"/> <direct name="direct1" input="frac_logic.in" output="frac_lut4.in"/>
<direct name="direct2" input="frac_lut4.lut3_out[0]" output="frac_logic.out[0]"/> <direct name="direct2" input="frac_lut4.lut3_out[0]" output="frac_logic.out[0]"/>
<direct name="direct3" input="frac_lut4.lut4_out[0]" output="frac_logic.out[1]"/> <direct name="direct3" input="frac_lut4.lut4_out[0]" output="frac_logic.out[1]"/>
</interconnect> </interconnect>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/> <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
<direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/> <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
<complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/> <complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]"> <mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/> <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/> <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux> </mux>
<mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]"> <mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/> <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/> <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="fabric.in"/> <direct name="direct1" input="fle.in" output="fabric.in"/>
<direct name="direct2" input="fabric.out" output="fle.out"/> <direct name="direct2" input="fabric.out" output="fle.out"/>
<direct name="direct3" input="fle.clk" output="fabric.clk"/> <direct name="direct3" input="fle.clk" output="fabric.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- Physical mode definition end (physical implementation of the fle) --> <!-- Physical mode definition end (physical implementation of the fle) -->
<!-- 3-LUT + LUT4 with shared inputs mode definition begin --> <!-- 3-LUT + LUT4 with shared inputs mode definition begin -->
<mode name="shared_lut3_lut4"> <mode name="shared_lut3_lut4">
<pb_type name="ble3" num_pb="1"> <pb_type name="ble3" num_pb="1">
<input name="in" num_pins="3"/> <input name="in" num_pins="3"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define LUT3 --> <!-- Define LUT3 -->
<pb_type name="lut3" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut3" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="3" port_class="lut_in"/> <input name="in" num_pins="3" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<delay_matrix type="max" in_port="lut3.in" out_port="lut3.out"> <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
235e-12 235e-12
235e-12 235e-12
235e-12 235e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define the flip-flop --> <!-- Define the flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/> <direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
<direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D"> <direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/> <pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
</direct> </direct>
<direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/> <direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
<mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]"> <mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/> <delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/> <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<pb_type name="ble4" num_pb="1"> <pb_type name="ble4" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define LUT4 --> <!-- Define LUT4 -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/> <input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out"> <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define the flip-flop --> <!-- Define the flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble4.in[3:0]" output="lut4[0:0].in[3:0]"/> <direct name="direct1" input="ble4.in[3:0]" output="lut4[0:0].in[3:0]"/>
<direct name="direct2" input="lut4[0:0].out" output="ff[0:0].D"> <direct name="direct2" input="lut4[0:0].out" output="ff[0:0].D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4[0:0].out" out_port="ff[0:0].D"/> <pack_pattern name="ble4" in_port="lut4[0:0].out" out_port="ff[0:0].D"/>
</direct> </direct>
<direct name="direct3" input="ble4.clk" output="ff[0:0].clk"/> <direct name="direct3" input="ble4.clk" output="ff[0:0].clk"/>
<mux name="mux1" input="ff[0:0].Q lut4.out[0:0]" output="ble4.out[0:0]"> <mux name="mux1" input="ff[0:0].Q lut4.out[0:0]" output="ble4.out[0:0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out[0:0]" out_port="ble4.out[0:0]"/> <delay_constant max="25e-12" in_port="lut4.out[0:0]" out_port="ble4.out[0:0]"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble4.out[0:0]"/> <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble4.out[0:0]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in[2:0]" output="ble3.in"/> <direct name="direct1" input="fle.in[2:0]" output="ble3.in"/>
<direct name="direct2" input="fle.in[3:0]" output="ble4.in"/> <direct name="direct2" input="fle.in[3:0]" output="ble4.in"/>
<direct name="direct3" input="ble3.out" output="fle.out[0:0]"/> <direct name="direct3" input="ble3.out" output="fle.out[0:0]"/>
<direct name="direct4" input="ble4.out" output="fle.out[1:1]"/> <direct name="direct4" input="ble4.out" output="fle.out[1:1]"/>
<direct name="direct5" input="fle.clk" output="ble3.clk"/> <direct name="direct5" input="fle.clk" output="ble3.clk"/>
<direct name="direct6" input="fle.clk" output="ble4.clk"/> <direct name="direct6" input="fle.clk" output="ble4.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- Dual 3-LUT mode definition end --> <!-- Dual 3-LUT mode definition end -->
</pb_type> </pb_type>
<interconnect> <interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB <!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining delay on the connection block input mux (modeled by Ian Kuon), so the remaining
@ -397,24 +396,24 @@
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT. The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. --> to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in"> <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/> <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
</complete> </complete>
<complete name="clks" input="clb.clk" output="fle[3:0].clk"> <complete name="clks" input="clb.clk" output="fle[3:0].clk">
</complete> </complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins. <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification). naive specification).
--> -->
<direct name="clbouts1" input="fle[3:0].out[0:0]" output="clb.O[3:0]"/> <direct name="clbouts1" input="fle[3:0].out[0:0]" output="clb.O[3:0]"/>
<direct name="clbouts2" input="fle[3:0].out[1:1]" output="clb.O[7:4]"/> <direct name="clbouts2" input="fle[3:0].out[1:1]" output="clb.O[7:4]"/>
</interconnect> </interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- Place this general purpose logic block in any unspecified column --> <!-- Place this general purpose logic block in any unspecified column -->
</pb_type> </pb_type>
<!-- Define general purpose logic block (CLB) ends --> <!-- Define general purpose logic block (CLB) ends -->
</complexblocklist> </complexblocklist>
</architecture> </architecture>

705
openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml
View File

@ -1,4 +1,4 @@
<!-- <?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0. Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
- 40 nm technology - 40 nm technology
@ -12,9 +12,8 @@
Based on flagship k4_frac_N4_mem32K_40nm.xml architecture. Based on flagship k4_frac_N4_mem32K_40nm.xml architecture.
Authors: Jason Luu, Jeff Goeders, Vaughn Betz Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--> --><architecture>
<architecture> <!--
<!--
ODIN II specific config begins ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports. ".model [type_of_block]") that this architecture supports.
@ -22,85 +21,85 @@
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch) already special structures in blif (.names, .input, .output, and .latch)
that describe them. that describe them.
--> -->
<models> <models>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io"> <model name="io">
<input_ports> <input_ports>
<port name="outpad"/> <port name="outpad"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="inpad"/> <port name="inpad"/>
</output_ports> </output_ports>
</model> </model>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="frac_lut4"> <model name="frac_lut4">
<input_ports> <input_ports>
<port name="in"/> <port name="in"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="lut3_out"/> <port name="lut3_out"/>
<port name="lut4_out"/> <port name="lut4_out"/>
</output_ports> </output_ports>
</model> </model>
</models> </models>
<tiles> <tiles>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
If you need to register the I/O, define clocks in the circuit models If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end These clocks can be handled in back-end
--> -->
<tile name="io" capacity="8" area="0"> <tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc> <loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc> <loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc> <loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc> <loc side="bottom">io.outpad io.inpad</loc>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
<tile name="clb" area="53894"> <tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites> <equivalent_sites>
<site pb_type="clb"/> <site pb_type="clb"/>
</equivalent_sites> </equivalent_sites>
<input name="I" num_pins="12" equivalent="full"/> <input name="I" num_pins="12" equivalent="full"/>
<output name="O" num_pins="8" equivalent="none"/> <output name="O" num_pins="8" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/> <pinlocations pattern="spread"/>
</tile> </sub_tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
<!-- Physical descriptions begin --> <!-- Physical descriptions begin -->
<layout tileable="false"> <layout tileable="false">
<auto_layout aspect_ratio="1.0"> <auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</auto_layout> </auto_layout>
<fixed_layout name="2x2" width="4" height="4"> <fixed_layout name="2x2" width="4" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
<fixed_layout name="4x4" width="6" height="6"> <fixed_layout name="4x4" width="6" height="6">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
@ -114,21 +113,21 @@
The delay values are lined up with Stratix IV, which has an architecture similar to this The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. --> 4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
--> -->
<area grid_logic_tile_area="0"/> <area grid_logic_tile_area="0"/>
<chan_width_distr> <chan_width_distr>
<x distr="uniform" peak="1.000000"/> <x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/> <y distr="uniform" peak="1.000000"/>
</chan_width_distr> </chan_width_distr>
<switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/> <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength. book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
@ -140,87 +139,87 @@
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables. 2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. --> This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! --> <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/> <mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
</segment> </segment>
</segmentlist> </segmentlist>
<complexblocklist> <complexblocklist>
<!-- Define I/O pads begin --> <!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA --> <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. --> <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io"> <pb_type name="io">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
If you need to register the I/O, define clocks in the circuit models If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end These clocks can be handled in back-end
--> -->
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- IOs can operate as either inputs or outputs. <!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them. today and that is when you timing analyze them.
--> -->
<mode name="inpad"> <mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<mode name="outpad"> <mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1"> <pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- IOs go on the periphery of the FPGA, for consistency, <!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed. make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
--> -->
<!-- Place I/Os on the sides of the FPGA --> <!-- Place I/Os on the sides of the FPGA -->
<power method="ignore"/> <power method="ignore"/>
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin --> <!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs. area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic This means that only 37% of our area is in the general routing, and 63% is inside the logic
@ -228,150 +227,150 @@
area in this analysis. That is a lower proportion of of routing area than most academics area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range. routing area up significantly, we estimate into the ~70% range.
--> -->
<pb_type name="clb"> <pb_type name="clb">
<input name="I" num_pins="12" equivalent="full"/> <input name="I" num_pins="12" equivalent="full"/>
<output name="O" num_pins="8" equivalent="none"/> <output name="O" num_pins="8" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Describe fracturable logic element. <!-- Describe fracturable logic element.
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
The outputs of the fracturable logic element can be optionally registered The outputs of the fracturable logic element can be optionally registered
--> -->
<pb_type name="fle" num_pb="4"> <pb_type name="fle" num_pb="4">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<pb_type name="frac_logic" num_pb="1"> <pb_type name="frac_logic" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1"> <pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="lut3_out" num_pins="2"/> <output name="lut3_out" num_pins="2"/>
<output name="lut4_out" num_pins="1"/> <output name="lut4_out" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="frac_logic.in" output="frac_lut4.in"/> <direct name="direct1" input="frac_logic.in" output="frac_lut4.in"/>
<direct name="direct2" input="frac_lut4.lut3_out[1]" output="frac_logic.out[1]"/> <direct name="direct2" input="frac_lut4.lut3_out[1]" output="frac_logic.out[1]"/>
<!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] --> <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
<mux name="mux1" input="frac_lut4.lut4_out frac_lut4.lut3_out[0]" output="frac_logic.out[0]"/> <mux name="mux1" input="frac_lut4.lut4_out frac_lut4.lut3_out[0]" output="frac_logic.out[0]"/>
</interconnect> </interconnect>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/> <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
<direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/> <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
<complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/> <complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]"> <mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/> <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/> <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux> </mux>
<mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]"> <mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/> <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/> <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="fabric.in"/> <direct name="direct1" input="fle.in" output="fabric.in"/>
<direct name="direct2" input="fabric.out" output="fle.out"/> <direct name="direct2" input="fabric.out" output="fle.out"/>
<direct name="direct3" input="fle.clk" output="fabric.clk"/> <direct name="direct3" input="fle.clk" output="fabric.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- Physical mode definition end (physical implementation of the fle) --> <!-- Physical mode definition end (physical implementation of the fle) -->
<!-- Dual 3-LUT mode definition begin --> <!-- Dual 3-LUT mode definition begin -->
<mode name="n2_lut3"> <mode name="n2_lut3">
<pb_type name="lut3inter" num_pb="1"> <pb_type name="lut3inter" num_pb="1">
<input name="in" num_pins="3"/> <input name="in" num_pins="3"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<pb_type name="ble3" num_pb="2"> <pb_type name="ble3" num_pb="2">
<input name="in" num_pins="3"/> <input name="in" num_pins="3"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define the LUT --> <!-- Define the LUT -->
<pb_type name="lut3" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut3" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="3" port_class="lut_in"/> <input name="in" num_pins="3" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing, <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results we instead take the average of these numbers to get more stable results
82e-12 82e-12
173e-12 173e-12
261e-12 261e-12
263e-12 263e-12
398e-12 398e-12
--> -->
<delay_matrix type="max" in_port="lut3.in" out_port="lut3.out"> <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
235e-12 235e-12
235e-12 235e-12
235e-12 235e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define the flip-flop --> <!-- Define the flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/> <direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
<direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D"> <direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/> <pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
</direct> </direct>
<direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/> <direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
<mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]"> <mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/> <delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/> <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="lut3inter.in" output="ble3[0:0].in"/> <direct name="direct1" input="lut3inter.in" output="ble3[0:0].in"/>
<direct name="direct2" input="lut3inter.in" output="ble3[1:1].in"/> <direct name="direct2" input="lut3inter.in" output="ble3[1:1].in"/>
<direct name="direct3" input="ble3[1:0].out" output="lut3inter.out"/> <direct name="direct3" input="ble3[1:0].out" output="lut3inter.out"/>
<complete name="complete1" input="lut3inter.clk" output="ble3[1:0].clk"/> <complete name="complete1" input="lut3inter.clk" output="ble3[1:0].clk"/>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in[2:0]" output="lut3inter.in"/> <direct name="direct1" input="fle.in[2:0]" output="lut3inter.in"/>
<direct name="direct2" input="lut3inter.out" output="fle.out"/> <direct name="direct2" input="lut3inter.out" output="fle.out"/>
<direct name="direct3" input="fle.clk" output="lut3inter.clk"/> <direct name="direct3" input="fle.clk" output="lut3inter.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- Dual 3-LUT mode definition end --> <!-- Dual 3-LUT mode definition end -->
<!-- 4-LUT mode definition begin --> <!-- 4-LUT mode definition begin -->
<mode name="n1_lut4"> <mode name="n1_lut4">
<!-- Define 4-LUT mode --> <!-- Define 4-LUT mode -->
<pb_type name="ble4" num_pb="1"> <pb_type name="ble4" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/> <input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing, <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results we instead take the average of these numbers to get more stable results
82e-12 82e-12
173e-12 173e-12
@ -379,46 +378,46 @@
263e-12 263e-12
398e-12 398e-12
397e-12 397e-12
--> -->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out"> <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/> <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D"> <direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/> <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/> <direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out"> <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/> <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/> <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="ble4.in"/> <direct name="direct1" input="fle.in" output="ble4.in"/>
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/> <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble4.clk"/> <direct name="direct3" input="fle.clk" output="ble4.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- 6-LUT mode definition end --> <!-- 6-LUT mode definition end -->
</pb_type> </pb_type>
<interconnect> <interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB <!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining delay on the connection block input mux (modeled by Ian Kuon), so the remaining
@ -426,24 +425,24 @@
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT. The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. --> to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in"> <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/> <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
</complete> </complete>
<complete name="clks" input="clb.clk" output="fle[3:0].clk"> <complete name="clks" input="clb.clk" output="fle[3:0].clk">
</complete> </complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins. <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification). naive specification).
--> -->
<direct name="clbouts1" input="fle[3:0].out[0:0]" output="clb.O[3:0]"/> <direct name="clbouts1" input="fle[3:0].out[0:0]" output="clb.O[3:0]"/>
<direct name="clbouts2" input="fle[3:0].out[1:1]" output="clb.O[7:4]"/> <direct name="clbouts2" input="fle[3:0].out[1:1]" output="clb.O[7:4]"/>
</interconnect> </interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- Place this general purpose logic block in any unspecified column --> <!-- Place this general purpose logic block in any unspecified column -->
</pb_type> </pb_type>
<!-- Define general purpose logic block (CLB) ends --> <!-- Define general purpose logic block (CLB) ends -->
</complexblocklist> </complexblocklist>
</architecture> </architecture>

705
openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml
View File

@ -1,4 +1,4 @@
<!-- <?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0. Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
- 40 nm technology - 40 nm technology
@ -12,9 +12,8 @@
Based on flagship k4_frac_N4_mem32K_40nm.xml architecture. Based on flagship k4_frac_N4_mem32K_40nm.xml architecture.
Authors: Jason Luu, Jeff Goeders, Vaughn Betz Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--> --><architecture>
<architecture> <!--
<!--
ODIN II specific config begins ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports. ".model [type_of_block]") that this architecture supports.
@ -22,85 +21,85 @@
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch) already special structures in blif (.names, .input, .output, and .latch)
that describe them. that describe them.
--> -->
<models> <models>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io"> <model name="io">
<input_ports> <input_ports>
<port name="outpad"/> <port name="outpad"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="inpad"/> <port name="inpad"/>
</output_ports> </output_ports>
</model> </model>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="frac_lut4"> <model name="frac_lut4">
<input_ports> <input_ports>
<port name="in"/> <port name="in"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="lut3_out"/> <port name="lut3_out"/>
<port name="lut4_out"/> <port name="lut4_out"/>
</output_ports> </output_ports>
</model> </model>
</models> </models>
<tiles> <tiles>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
If you need to register the I/O, define clocks in the circuit models If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end These clocks can be handled in back-end
--> -->
<tile name="io" capacity="8" area="0"> <tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc> <loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc> <loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc> <loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc> <loc side="bottom">io.outpad io.inpad</loc>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
<tile name="clb" area="53894"> <tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites> <equivalent_sites>
<site pb_type="clb"/> <site pb_type="clb"/>
</equivalent_sites> </equivalent_sites>
<input name="I" num_pins="12" equivalent="full"/> <input name="I" num_pins="12" equivalent="full"/>
<output name="O" num_pins="8" equivalent="none"/> <output name="O" num_pins="8" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/> <pinlocations pattern="spread"/>
</tile> </sub_tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
<!-- Physical descriptions begin --> <!-- Physical descriptions begin -->
<layout tileable="true"> <layout tileable="true">
<auto_layout aspect_ratio="1.0"> <auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</auto_layout> </auto_layout>
<fixed_layout name="2x2" width="4" height="4"> <fixed_layout name="2x2" width="4" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
<fixed_layout name="4x4" width="6" height="6"> <fixed_layout name="4x4" width="6" height="6">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
@ -114,21 +113,21 @@
The delay values are lined up with Stratix IV, which has an architecture similar to this The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. --> 4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
--> -->
<area grid_logic_tile_area="0"/> <area grid_logic_tile_area="0"/>
<chan_width_distr> <chan_width_distr>
<x distr="uniform" peak="1.000000"/> <x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/> <y distr="uniform" peak="1.000000"/>
</chan_width_distr> </chan_width_distr>
<switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/> <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength. book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
@ -140,87 +139,87 @@
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables. 2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. --> This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! --> <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/> <mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
</segment> </segment>
</segmentlist> </segmentlist>
<complexblocklist> <complexblocklist>
<!-- Define I/O pads begin --> <!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA --> <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. --> <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io"> <pb_type name="io">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
If you need to register the I/O, define clocks in the circuit models If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end These clocks can be handled in back-end
--> -->
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- IOs can operate as either inputs or outputs. <!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them. today and that is when you timing analyze them.
--> -->
<mode name="inpad"> <mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<mode name="outpad"> <mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1"> <pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- IOs go on the periphery of the FPGA, for consistency, <!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed. make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
--> -->
<!-- Place I/Os on the sides of the FPGA --> <!-- Place I/Os on the sides of the FPGA -->
<power method="ignore"/> <power method="ignore"/>
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin --> <!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs. area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic This means that only 37% of our area is in the general routing, and 63% is inside the logic
@ -228,150 +227,150 @@
area in this analysis. That is a lower proportion of of routing area than most academics area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range. routing area up significantly, we estimate into the ~70% range.
--> -->
<pb_type name="clb"> <pb_type name="clb">
<input name="I" num_pins="12" equivalent="full"/> <input name="I" num_pins="12" equivalent="full"/>
<output name="O" num_pins="8" equivalent="none"/> <output name="O" num_pins="8" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Describe fracturable logic element. <!-- Describe fracturable logic element.
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
The outputs of the fracturable logic element can be optionally registered The outputs of the fracturable logic element can be optionally registered
--> -->
<pb_type name="fle" num_pb="4"> <pb_type name="fle" num_pb="4">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<pb_type name="frac_logic" num_pb="1"> <pb_type name="frac_logic" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1"> <pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="lut3_out" num_pins="2"/> <output name="lut3_out" num_pins="2"/>
<output name="lut4_out" num_pins="1"/> <output name="lut4_out" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="frac_logic.in" output="frac_lut4.in"/> <direct name="direct1" input="frac_logic.in" output="frac_lut4.in"/>
<direct name="direct2" input="frac_lut4.lut3_out[1]" output="frac_logic.out[1]"/> <direct name="direct2" input="frac_lut4.lut3_out[1]" output="frac_logic.out[1]"/>
<!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] --> <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
<mux name="mux1" input="frac_lut4.lut4_out frac_lut4.lut3_out[0]" output="frac_logic.out[0]"/> <mux name="mux1" input="frac_lut4.lut4_out frac_lut4.lut3_out[0]" output="frac_logic.out[0]"/>
</interconnect> </interconnect>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/> <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
<direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/> <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
<complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/> <complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]"> <mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/> <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/> <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux> </mux>
<mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]"> <mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/> <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/> <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="fabric.in"/> <direct name="direct1" input="fle.in" output="fabric.in"/>
<direct name="direct2" input="fabric.out" output="fle.out"/> <direct name="direct2" input="fabric.out" output="fle.out"/>
<direct name="direct3" input="fle.clk" output="fabric.clk"/> <direct name="direct3" input="fle.clk" output="fabric.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- Physical mode definition end (physical implementation of the fle) --> <!-- Physical mode definition end (physical implementation of the fle) -->
<!-- Dual 3-LUT mode definition begin --> <!-- Dual 3-LUT mode definition begin -->
<mode name="n2_lut3"> <mode name="n2_lut3">
<pb_type name="lut3inter" num_pb="1"> <pb_type name="lut3inter" num_pb="1">
<input name="in" num_pins="3"/> <input name="in" num_pins="3"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<pb_type name="ble3" num_pb="2"> <pb_type name="ble3" num_pb="2">
<input name="in" num_pins="3"/> <input name="in" num_pins="3"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define the LUT --> <!-- Define the LUT -->
<pb_type name="lut3" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut3" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="3" port_class="lut_in"/> <input name="in" num_pins="3" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing, <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results we instead take the average of these numbers to get more stable results
82e-12 82e-12
173e-12 173e-12
261e-12 261e-12
263e-12 263e-12
398e-12 398e-12
--> -->
<delay_matrix type="max" in_port="lut3.in" out_port="lut3.out"> <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
235e-12 235e-12
235e-12 235e-12
235e-12 235e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define the flip-flop --> <!-- Define the flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/> <direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
<direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D"> <direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/> <pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
</direct> </direct>
<direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/> <direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
<mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]"> <mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/> <delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/> <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="lut3inter.in" output="ble3[0:0].in"/> <direct name="direct1" input="lut3inter.in" output="ble3[0:0].in"/>
<direct name="direct2" input="lut3inter.in" output="ble3[1:1].in"/> <direct name="direct2" input="lut3inter.in" output="ble3[1:1].in"/>
<direct name="direct3" input="ble3[1:0].out" output="lut3inter.out"/> <direct name="direct3" input="ble3[1:0].out" output="lut3inter.out"/>
<complete name="complete1" input="lut3inter.clk" output="ble3[1:0].clk"/> <complete name="complete1" input="lut3inter.clk" output="ble3[1:0].clk"/>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in[2:0]" output="lut3inter.in"/> <direct name="direct1" input="fle.in[2:0]" output="lut3inter.in"/>
<direct name="direct2" input="lut3inter.out" output="fle.out"/> <direct name="direct2" input="lut3inter.out" output="fle.out"/>
<direct name="direct3" input="fle.clk" output="lut3inter.clk"/> <direct name="direct3" input="fle.clk" output="lut3inter.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- Dual 3-LUT mode definition end --> <!-- Dual 3-LUT mode definition end -->
<!-- 4-LUT mode definition begin --> <!-- 4-LUT mode definition begin -->
<mode name="n1_lut4"> <mode name="n1_lut4">
<!-- Define 4-LUT mode --> <!-- Define 4-LUT mode -->
<pb_type name="ble4" num_pb="1"> <pb_type name="ble4" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/> <input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing, <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results we instead take the average of these numbers to get more stable results
82e-12 82e-12
173e-12 173e-12
@ -379,46 +378,46 @@
263e-12 263e-12
398e-12 398e-12
397e-12 397e-12
--> -->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out"> <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/> <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D"> <direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/> <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/> <direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out"> <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/> <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/> <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="ble4.in"/> <direct name="direct1" input="fle.in" output="ble4.in"/>
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/> <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble4.clk"/> <direct name="direct3" input="fle.clk" output="ble4.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- 6-LUT mode definition end --> <!-- 6-LUT mode definition end -->
</pb_type> </pb_type>
<interconnect> <interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB <!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining delay on the connection block input mux (modeled by Ian Kuon), so the remaining
@ -426,24 +425,24 @@
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT. The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. --> to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in"> <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/> <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
</complete> </complete>
<complete name="clks" input="clb.clk" output="fle[3:0].clk"> <complete name="clks" input="clb.clk" output="fle[3:0].clk">
</complete> </complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins. <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification). naive specification).
--> -->
<direct name="clbouts1" input="fle[3:0].out[0:0]" output="clb.O[3:0]"/> <direct name="clbouts1" input="fle[3:0].out[0:0]" output="clb.O[3:0]"/>
<direct name="clbouts2" input="fle[3:0].out[1:1]" output="clb.O[7:4]"/> <direct name="clbouts2" input="fle[3:0].out[1:1]" output="clb.O[7:4]"/>
</interconnect> </interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- Place this general purpose logic block in any unspecified column --> <!-- Place this general purpose logic block in any unspecified column -->
</pb_type> </pb_type>
<!-- Define general purpose logic block (CLB) ends --> <!-- Define general purpose logic block (CLB) ends -->
</complexblocklist> </complexblocklist>
</architecture> </architecture>

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@ -1,4 +1,4 @@
<!-- <?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0. Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
- 40 nm technology - 40 nm technology
@ -13,9 +13,8 @@
Based on flagship k4_frac_N4_mem32K_40nm.xml architecture. Based on flagship k4_frac_N4_mem32K_40nm.xml architecture.
Authors: Jason Luu, Jeff Goeders, Vaughn Betz Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--> --><architecture>
<architecture> <!--
<!--
ODIN II specific config begins ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports. ".model [type_of_block]") that this architecture supports.
@ -23,102 +22,102 @@
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch) already special structures in blif (.names, .input, .output, and .latch)
that describe them. that describe them.
--> -->
<models> <models>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io"> <model name="io">
<input_ports> <input_ports>
<port name="outpad"/> <port name="outpad"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="inpad"/> <port name="inpad"/>
</output_ports> </output_ports>
</model> </model>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="frac_lut4"> <model name="frac_lut4">
<input_ports> <input_ports>
<port name="in"/> <port name="in"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="lut3_out"/> <port name="lut3_out"/>
<port name="lut4_out"/> <port name="lut4_out"/>
</output_ports> </output_ports>
</model> </model>
<model name="spram_4x1"> <model name="spram_4x1">
<input_ports> <input_ports>
<port name="wr_en" clock="clk"/> <port name="wr_en" clock="clk"/>
<port name="addr" clock="clk"/> <port name="addr" clock="clk"/>
<port name="d_in" clock="clk"/> <port name="d_in" clock="clk"/>
<port name="clk" is_clock="1"/> <port name="clk" is_clock="1"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="d_out" clock="clk"/> <port name="d_out" clock="clk"/>
</output_ports> </output_ports>
</model> </model>
</models> </models>
<tiles> <tiles>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
If you need to register the I/O, define clocks in the circuit models If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end These clocks can be handled in back-end
--> -->
<tile name="io" capacity="1" area="0"> <tile name="io" area="0"> <sub_tile name="io" capacity="1">
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc> <loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc> <loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc> <loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc> <loc side="bottom">io.outpad io.inpad</loc>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
<tile name="clb" area="53894"> <tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites> <equivalent_sites>
<site pb_type="clb"/> <site pb_type="clb"/>
</equivalent_sites> </equivalent_sites>
<input name="I" num_pins="12" equivalent="full"/> <input name="I" num_pins="12" equivalent="full"/>
<output name="O" num_pins="8" equivalent="none"/> <output name="O" num_pins="8" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<!--pinlocations pattern="spread"/--> <!--pinlocations pattern="spread"/-->
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">clb.clk</loc> <loc side="left">clb.clk</loc>
<loc side="top"></loc> <loc side="top"/>
<loc side="right">clb.O[3:0] clb.I[5:0]</loc> <loc side="right">clb.O[3:0] clb.I[5:0]</loc>
<loc side="bottom">clb.O[7:4] clb.I[11:6]</loc> <loc side="bottom">clb.O[7:4] clb.I[11:6]</loc>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
<!-- Physical descriptions begin --> <!-- Physical descriptions begin -->
<layout tileable="true"> <layout tileable="true">
<auto_layout aspect_ratio="1.0"> <auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</auto_layout> </auto_layout>
<fixed_layout name="2x2" width="4" height="4"> <fixed_layout name="2x2" width="4" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
<fixed_layout name="4x4" width="6" height="6"> <fixed_layout name="4x4" width="6" height="6">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
@ -132,21 +131,21 @@
The delay values are lined up with Stratix IV, which has an architecture similar to this The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. --> 4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
--> -->
<area grid_logic_tile_area="0"/> <area grid_logic_tile_area="0"/>
<chan_width_distr> <chan_width_distr>
<x distr="uniform" peak="1.000000"/> <x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/> <y distr="uniform" peak="1.000000"/>
</chan_width_distr> </chan_width_distr>
<switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/> <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength. book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
@ -158,87 +157,87 @@
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables. 2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. --> This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! --> <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/> <mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
</segment> </segment>
</segmentlist> </segmentlist>
<complexblocklist> <complexblocklist>
<!-- Define I/O pads begin --> <!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA --> <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. --> <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io"> <pb_type name="io">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
If you need to register the I/O, define clocks in the circuit models If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end These clocks can be handled in back-end
--> -->
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- IOs can operate as either inputs or outputs. <!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them. today and that is when you timing analyze them.
--> -->
<mode name="inpad"> <mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<mode name="outpad"> <mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1"> <pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- IOs go on the periphery of the FPGA, for consistency, <!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed. make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
--> -->
<!-- Place I/Os on the sides of the FPGA --> <!-- Place I/Os on the sides of the FPGA -->
<power method="ignore"/> <power method="ignore"/>
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin --> <!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs. area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic This means that only 37% of our area is in the general routing, and 63% is inside the logic
@ -246,222 +245,222 @@
area in this analysis. That is a lower proportion of of routing area than most academics area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range. routing area up significantly, we estimate into the ~70% range.
--> -->
<pb_type name="clb"> <pb_type name="clb">
<input name="I" num_pins="12" equivalent="full"/> <input name="I" num_pins="12" equivalent="full"/>
<output name="O" num_pins="8" equivalent="none"/> <output name="O" num_pins="8" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Describe fracturable logic element. <!-- Describe fracturable logic element.
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
The outputs of the fracturable logic element can be optionally registered The outputs of the fracturable logic element can be optionally registered
--> -->
<pb_type name="fle" num_pb="4"> <pb_type name="fle" num_pb="4">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<pb_type name="frac_logic" num_pb="1"> <pb_type name="frac_logic" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1"> <pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="lut3_out" num_pins="2"/> <output name="lut3_out" num_pins="2"/>
<output name="lut4_out" num_pins="1"/> <output name="lut4_out" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="frac_logic.in" output="frac_lut4.in"/> <direct name="direct1" input="frac_logic.in" output="frac_lut4.in"/>
<direct name="direct2" input="frac_lut4.lut3_out[1]" output="frac_logic.out[1]"/> <direct name="direct2" input="frac_lut4.lut3_out[1]" output="frac_logic.out[1]"/>
<!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] --> <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
<mux name="mux1" input="frac_lut4.lut4_out frac_lut4.lut3_out[0]" output="frac_logic.out[0]"/> <mux name="mux1" input="frac_lut4.lut4_out frac_lut4.lut3_out[0]" output="frac_logic.out[0]"/>
</interconnect> </interconnect>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<!-- Define spram_4x1 --> <!-- Define spram_4x1 -->
<pb_type name="spram_4x1" blif_model=".subckt spram_4x1" num_pb="1"> <pb_type name="spram_4x1" blif_model=".subckt spram_4x1" num_pb="1">
<input name="wr_en" num_pins="1"/> <input name="wr_en" num_pins="1"/>
<input name="addr" num_pins="2"/> <input name="addr" num_pins="2"/>
<input name="d_in" num_pins="1"/> <input name="d_in" num_pins="1"/>
<output name="d_out" num_pins="1"/> <output name="d_out" num_pins="1"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="509e-12" port="spram_4x1.wr_en" clock="clk"/> <T_setup value="509e-12" port="spram_4x1.wr_en" clock="clk"/>
<T_setup value="509e-12" port="spram_4x1.addr" clock="clk"/> <T_setup value="509e-12" port="spram_4x1.addr" clock="clk"/>
<T_setup value="509e-12" port="spram_4x1.d_in" clock="clk"/> <T_setup value="509e-12" port="spram_4x1.d_in" clock="clk"/>
<T_clock_to_Q max="1.234e-9" port="spram_4x1.d_out" clock="clk"/> <T_clock_to_Q max="1.234e-9" port="spram_4x1.d_out" clock="clk"/>
<power method="pin-toggle"> <power method="pin-toggle">
<port name="clk" energy_per_toggle="17.9e-12"/> <port name="clk" energy_per_toggle="17.9e-12"/>
<static_power power_per_instance="0.0"/> <static_power power_per_instance="0.0"/>
</power> </power>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/> <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
<direct name="direct_mem_en" input="fabric.in[0]" output="spram_4x1.wr_en"/> <direct name="direct_mem_en" input="fabric.in[0]" output="spram_4x1.wr_en"/>
<direct name="direct_mem_in" input="fabric.in[3]" output="spram_4x1.d_in"/> <direct name="direct_mem_in" input="fabric.in[3]" output="spram_4x1.d_in"/>
<direct name="direct_mem_addr" input="fabric.in[2:1]" output="spram_4x1.addr"/> <direct name="direct_mem_addr" input="fabric.in[2:1]" output="spram_4x1.addr"/>
<complete name="direct6" input="fabric.clk" output="ff[1:0].clk"/> <complete name="direct6" input="fabric.clk" output="ff[1:0].clk"/>
<complete name="direct_mem_clk" input="fabric.clk" output="spram_4x1.clk"/> <complete name="direct_mem_clk" input="fabric.clk" output="spram_4x1.clk"/>
<mux name="mux1" input="frac_logic.out[0:0] spram_4x1.d_out" output="ff[0:0].D"> <mux name="mux1" input="frac_logic.out[0:0] spram_4x1.d_out" output="ff[0:0].D">
<delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/> <delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
<delay_constant max="45e-12" in_port="spram_4x1.d_out" out_port="ff[0:0].D"/> <delay_constant max="45e-12" in_port="spram_4x1.d_out" out_port="ff[0:0].D"/>
</mux> </mux>
<mux name="mux2" input="frac_logic.out[1:1] spram_4x1.d_out" output="ff[1:1].D"> <mux name="mux2" input="frac_logic.out[1:1] spram_4x1.d_out" output="ff[1:1].D">
<delay_constant max="25e-12" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/> <delay_constant max="25e-12" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
<delay_constant max="45e-12" in_port="spram_4x1.d_out" out_port="ff[1:1].D"/> <delay_constant max="45e-12" in_port="spram_4x1.d_out" out_port="ff[1:1].D"/>
</mux> </mux>
<mux name="mux3" input="spram_4x1.d_out ff[0].Q frac_logic.out[0]" output="fabric.out[0]"> <mux name="mux3" input="spram_4x1.d_out ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/> <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux> </mux>
<mux name="mux4" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]"> <mux name="mux4" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/> <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="fabric.in"/> <direct name="direct1" input="fle.in" output="fabric.in"/>
<direct name="direct3" input="fabric.out" output="fle.out"/> <direct name="direct3" input="fabric.out" output="fle.out"/>
<direct name="direct5" input="fle.clk" output="fabric.clk"/> <direct name="direct5" input="fle.clk" output="fabric.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- Physical mode definition end (physical implementation of the fle) --> <!-- Physical mode definition end (physical implementation of the fle) -->
<!-- Dual 3-LUT mode definition begin --> <!-- Dual 3-LUT mode definition begin -->
<mode name="n2_lut3"> <mode name="n2_lut3">
<pb_type name="lut3inter" num_pb="1"> <pb_type name="lut3inter" num_pb="1">
<input name="in" num_pins="3"/> <input name="in" num_pins="3"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<pb_type name="ble3" num_pb="2"> <pb_type name="ble3" num_pb="2">
<input name="in" num_pins="3"/> <input name="in" num_pins="3"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define the LUT --> <!-- Define the LUT -->
<pb_type name="lut3" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut3" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="3" port_class="lut_in"/> <input name="in" num_pins="3" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing, <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results we instead take the average of these numbers to get more stable results
82e-12 82e-12
173e-12 173e-12
261e-12 261e-12
263e-12 263e-12
398e-12 398e-12
--> -->
<delay_matrix type="max" in_port="lut3.in" out_port="lut3.out"> <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
235e-12 235e-12
235e-12 235e-12
235e-12 235e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define the flip-flop --> <!-- Define the flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/> <direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
<direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D"> <direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/> <pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
</direct> </direct>
<direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/> <direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
<mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]"> <mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/> <delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/> <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="lut3inter.in" output="ble3[0:0].in"/> <direct name="direct1" input="lut3inter.in" output="ble3[0:0].in"/>
<direct name="direct2" input="lut3inter.in" output="ble3[1:1].in"/> <direct name="direct2" input="lut3inter.in" output="ble3[1:1].in"/>
<direct name="direct3" input="ble3[1:0].out" output="lut3inter.out"/> <direct name="direct3" input="ble3[1:0].out" output="lut3inter.out"/>
<complete name="complete1" input="lut3inter.clk" output="ble3[1:0].clk"/> <complete name="complete1" input="lut3inter.clk" output="ble3[1:0].clk"/>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in[2:0]" output="lut3inter.in"/> <direct name="direct1" input="fle.in[2:0]" output="lut3inter.in"/>
<direct name="direct2" input="lut3inter.out" output="fle.out"/> <direct name="direct2" input="lut3inter.out" output="fle.out"/>
<direct name="direct3" input="fle.clk" output="lut3inter.clk"/> <direct name="direct3" input="fle.clk" output="lut3inter.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- Dual 3-LUT mode definition end --> <!-- Dual 3-LUT mode definition end -->
<!-- BEGIN lutram mode --> <!-- BEGIN lutram mode -->
<mode name="lutram"> <mode name="lutram">
<pb_type name="lutram" num_pb="1"> <pb_type name="lutram" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<pb_type name="spram_4x1" blif_model=".subckt spram_4x1" num_pb="1"> <pb_type name="spram_4x1" blif_model=".subckt spram_4x1" num_pb="1">
<input name="wr_en" num_pins="1"/> <input name="wr_en" num_pins="1"/>
<input name="addr" num_pins="2"/> <input name="addr" num_pins="2"/>
<input name="d_in" num_pins="1"/> <input name="d_in" num_pins="1"/>
<output name="d_out" num_pins="1"/> <output name="d_out" num_pins="1"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="509e-12" port="spram_4x1.wr_en" clock="clk"/> <T_setup value="509e-12" port="spram_4x1.wr_en" clock="clk"/>
<T_setup value="509e-12" port="spram_4x1.addr" clock="clk"/> <T_setup value="509e-12" port="spram_4x1.addr" clock="clk"/>
<T_setup value="509e-12" port="spram_4x1.d_in" clock="clk"/> <T_setup value="509e-12" port="spram_4x1.d_in" clock="clk"/>
<T_clock_to_Q max="1.234e-9" port="spram_4x1.d_out" clock="clk"/> <T_clock_to_Q max="1.234e-9" port="spram_4x1.d_out" clock="clk"/>
</pb_type> </pb_type>
<pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="clock_mem" input="lutram.clk" output="spram_4x1.clk"/> <direct name="clock_mem" input="lutram.clk" output="spram_4x1.clk"/>
<direct name="mem_wr_en" input="lutram.in[0]" output="spram_4x1.wr_en"/> <direct name="mem_wr_en" input="lutram.in[0]" output="spram_4x1.wr_en"/>
<direct name="mem_addr" input="lutram.in[2:1]" output="spram_4x1.addr"/> <direct name="mem_addr" input="lutram.in[2:1]" output="spram_4x1.addr"/>
<direct name="mem_d_in" input="lutram.in[3]" output="spram_4x1.d_in"/> <direct name="mem_d_in" input="lutram.in[3]" output="spram_4x1.d_in"/>
<complete name="ff_d" input="spram_4x1.d_out" output="ff.D"/> <complete name="ff_d" input="spram_4x1.d_out" output="ff.D"/>
<complete name="clock_ff" input="lutram.clk" output="ff.clk"/> <complete name="clock_ff" input="lutram.clk" output="ff.clk"/>
<mux name="mem_out_0" input="ff[0].Q spram_4x1.d_out" output="lutram.out[0]"> <mux name="mem_out_0" input="ff[0].Q spram_4x1.d_out" output="lutram.out[0]">
<delay_constant max="25e-12" in_port="spram_4x1.d_out" out_port="lutram.out[0]"/> <delay_constant max="25e-12" in_port="spram_4x1.d_out" out_port="lutram.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="lutram.out"/> <delay_constant max="45e-12" in_port="ff[0].Q" out_port="lutram.out"/>
</mux> </mux>
<mux name="mem_out_1" input="ff[1].Q spram_4x1.d_out" output="lutram.out[1]"> <mux name="mem_out_1" input="ff[1].Q spram_4x1.d_out" output="lutram.out[1]">
<delay_constant max="25e-12" in_port="spram_4x1.d_out" out_port="lutram.out[1]"/> <delay_constant max="25e-12" in_port="spram_4x1.d_out" out_port="lutram.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="lutram.out"/> <delay_constant max="45e-12" in_port="ff[1].Q" out_port="lutram.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in[3:0]" output="lutram.in"/> <direct name="direct1" input="fle.in[3:0]" output="lutram.in"/>
<direct name="direct3" input="fle.clk" output="lutram.clk"/> <direct name="direct3" input="fle.clk" output="lutram.clk"/>
<direct name="direct4" input="lutram.out" output="fle.out"/> <direct name="direct4" input="lutram.out" output="fle.out"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- 4-LUT mode definition begin --> <!-- 4-LUT mode definition begin -->
<mode name="n1_lut4"> <mode name="n1_lut4">
<!-- Define 4-LUT mode --> <!-- Define 4-LUT mode -->
<pb_type name="ble4" num_pb="1"> <pb_type name="ble4" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/> <input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing, <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results we instead take the average of these numbers to get more stable results
82e-12 82e-12
173e-12 173e-12
@ -469,46 +468,46 @@
263e-12 263e-12
398e-12 398e-12
397e-12 397e-12
--> -->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out"> <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/> <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D"> <direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/> <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/> <direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out"> <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/> <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/> <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="ble4.in"/> <direct name="direct1" input="fle.in" output="ble4.in"/>
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/> <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble4.clk"/> <direct name="direct3" input="fle.clk" output="ble4.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- 4-LUT mode definition end --> <!-- 4-LUT mode definition end -->
</pb_type> </pb_type>
<interconnect> <interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB <!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining delay on the connection block input mux (modeled by Ian Kuon), so the remaining
@ -516,24 +515,24 @@
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT. The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. --> to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in"> <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/> <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
</complete> </complete>
<complete name="clks" input="clb.clk" output="fle[3:0].clk"> <complete name="clks" input="clb.clk" output="fle[3:0].clk">
</complete> </complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins. <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification). naive specification).
--> -->
<direct name="clbouts1" input="fle[3:0].out[0:0]" output="clb.O[3:0]"/> <direct name="clbouts1" input="fle[3:0].out[0:0]" output="clb.O[3:0]"/>
<direct name="clbouts2" input="fle[3:0].out[1:1]" output="clb.O[7:4]"/> <direct name="clbouts2" input="fle[3:0].out[1:1]" output="clb.O[7:4]"/>
</interconnect> </interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- Place this general purpose logic block in any unspecified column --> <!-- Place this general purpose logic block in any unspecified column -->
</pb_type> </pb_type>
<!-- Define general purpose logic block (CLB) ends --> <!-- Define general purpose logic block (CLB) ends -->
</complexblocklist> </complexblocklist>
</architecture> </architecture>

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@ -1,4 +1,4 @@
<!-- <?xml version="1.0" ?><!--
Architecture with no fracturable LUTs Architecture with no fracturable LUTs
- 40 nm technology - 40 nm technology
@ -12,9 +12,8 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--> --><architecture>
<architecture> <!--
<!--
ODIN II specific config begins ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports. ".model [type_of_block]") that this architecture supports.
@ -22,57 +21,57 @@
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch) already special structures in blif (.names, .input, .output, and .latch)
that describe them. that describe them.
--> -->
<models> <models>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io"> <model name="io">
<input_ports> <input_ports>
<port name="outpad"/> <port name="outpad"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="inpad"/> <port name="inpad"/>
</output_ports> </output_ports>
</model> </model>
</models> </models>
<tiles> <tiles>
<tile name="io" capacity="8" area="0"> <tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc> <loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc> <loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc> <loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc> <loc side="bottom">io.outpad io.inpad</loc>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
<tile name="clb" area="53894"> <tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites> <equivalent_sites>
<site pb_type="clb"/> <site pb_type="clb"/>
</equivalent_sites> </equivalent_sites>
<input name="I" num_pins="40" equivalent="full"/> <input name="I" num_pins="40" equivalent="full"/>
<output name="O" num_pins="10" equivalent="none"/> <output name="O" num_pins="10" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/> <pinlocations pattern="spread"/>
</tile> </sub_tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
<!-- Physical descriptions begin --> <!-- Physical descriptions begin -->
<layout tileable="false"> <layout tileable="false">
<auto_layout aspect_ratio="1.0"> <auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</auto_layout> </auto_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
@ -86,21 +85,21 @@
The delay values are lined up with Stratix IV, which has an architecture similar to this The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. --> 4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
--> -->
<area grid_logic_tile_area="0"/> <area grid_logic_tile_area="0"/>
<chan_width_distr> <chan_width_distr>
<x distr="uniform" peak="1.000000"/> <x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/> <y distr="uniform" peak="1.000000"/>
</chan_width_distr> </chan_width_distr>
<switch_block type="wilton" fs="3"/> <switch_block type="wilton" fs="3"/>
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength. book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
@ -112,81 +111,81 @@
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables. 2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. --> This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/> <mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
</segment> </segment>
</segmentlist> </segmentlist>
<complexblocklist> <complexblocklist>
<!-- Define I/O pads begin --> <!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA --> <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. --> <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io"> <pb_type name="io">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- IOs can operate as either inputs or outputs. <!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them. today and that is when you timing analyze them.
--> -->
<mode name="inpad"> <mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<mode name="outpad"> <mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1"> <pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- IOs go on the periphery of the FPGA, for consistency, <!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed. make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
--> -->
<!-- Place I/Os on the sides of the FPGA --> <!-- Place I/Os on the sides of the FPGA -->
<power method="ignore"/> <power method="ignore"/>
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin --> <!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs. area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic This means that only 37% of our area is in the general routing, and 63% is inside the logic
@ -194,31 +193,31 @@
area in this analysis. That is a lower proportion of of routing area than most academics area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range. routing area up significantly, we estimate into the ~70% range.
--> -->
<pb_type name="clb"> <pb_type name="clb">
<input name="I" num_pins="40" equivalent="full"/> <input name="I" num_pins="40" equivalent="full"/>
<output name="O" num_pins="10" equivalent="none"/> <output name="O" num_pins="10" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Describe basic logic element. <!-- Describe basic logic element.
Each basic logic element has a 6-LUT that can be optionally registered Each basic logic element has a 6-LUT that can be optionally registered
--> -->
<pb_type name="fle" num_pb="10"> <pb_type name="fle" num_pb="10">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- 6-LUT mode definition begin --> <!-- 6-LUT mode definition begin -->
<mode name="n1_lut6"> <mode name="n1_lut6">
<!-- Define 6-LUT mode --> <!-- Define 6-LUT mode -->
<pb_type name="ble6" num_pb="1"> <pb_type name="ble6" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="6" port_class="lut_in"/> <input name="in" num_pins="6" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing, <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results we instead take the average of these numbers to get more stable results
82e-12 82e-12
173e-12 173e-12
@ -226,48 +225,48 @@
263e-12 263e-12
398e-12 398e-12
397e-12 397e-12
--> -->
<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out"> <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/> <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
<direct name="direct2" input="lut6.out" output="ff.D"> <direct name="direct2" input="lut6.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/> <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble6.clk" output="ff.clk"/> <direct name="direct3" input="ble6.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut6.out" output="ble6.out"> <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/> <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/> <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="ble6.in"/> <direct name="direct1" input="fle.in" output="ble6.in"/>
<direct name="direct2" input="ble6.out" output="fle.out[0:0]"/> <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble6.clk"/> <direct name="direct3" input="fle.clk" output="ble6.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- 6-LUT mode definition end --> <!-- 6-LUT mode definition end -->
</pb_type> </pb_type>
<interconnect> <interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB <!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining delay on the connection block input mux (modeled by Ian Kuon), so the remaining
@ -275,23 +274,23 @@
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT. The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. --> to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in"> <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
<delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/> <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
</complete> </complete>
<complete name="clks" input="clb.clk" output="fle[9:0].clk"> <complete name="clks" input="clb.clk" output="fle[9:0].clk">
</complete> </complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins. <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification). naive specification).
--> -->
<direct name="clbouts1" input="fle[9:0].out" output="clb.O"/> <direct name="clbouts1" input="fle[9:0].out" output="clb.O"/>
</interconnect> </interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- Place this general purpose logic block in any unspecified column --> <!-- Place this general purpose logic block in any unspecified column -->
</pb_type> </pb_type>
<!-- Define general purpose logic block (CLB) ends --> <!-- Define general purpose logic block (CLB) ends -->
</complexblocklist> </complexblocklist>
</architecture> </architecture>

427
openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml
View File

@ -1,4 +1,4 @@
<!-- <?xml version="1.0" ?><!--
Architecture with no fracturable LUTs Architecture with no fracturable LUTs
- 40 nm technology - 40 nm technology
@ -12,9 +12,8 @@
Authors: Jason Luu, Jeff Goeders, Vaughn Betz Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--> --><architecture>
<architecture> <!--
<!--
ODIN II specific config begins ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports. ".model [type_of_block]") that this architecture supports.
@ -22,57 +21,57 @@
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch) already special structures in blif (.names, .input, .output, and .latch)
that describe them. that describe them.
--> -->
<models> <models>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io"> <model name="io">
<input_ports> <input_ports>
<port name="outpad"/> <port name="outpad"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="inpad"/> <port name="inpad"/>
</output_ports> </output_ports>
</model> </model>
</models> </models>
<tiles> <tiles>
<tile name="io" capacity="8" area="0"> <tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc> <loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc> <loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc> <loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc> <loc side="bottom">io.outpad io.inpad</loc>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
<tile name="clb" area="53894"> <tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites> <equivalent_sites>
<site pb_type="clb"/> <site pb_type="clb"/>
</equivalent_sites> </equivalent_sites>
<input name="I" num_pins="40" equivalent="full"/> <input name="I" num_pins="40" equivalent="full"/>
<output name="O" num_pins="10" equivalent="none"/> <output name="O" num_pins="10" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/> <pinlocations pattern="spread"/>
</tile> </sub_tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
<!-- Physical descriptions begin --> <!-- Physical descriptions begin -->
<layout tileable="true"> <layout tileable="true">
<auto_layout aspect_ratio="1.0"> <auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</auto_layout> </auto_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
@ -86,21 +85,21 @@
The delay values are lined up with Stratix IV, which has an architecture similar to this The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. --> 4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
--> -->
<area grid_logic_tile_area="0"/> <area grid_logic_tile_area="0"/>
<chan_width_distr> <chan_width_distr>
<x distr="uniform" peak="1.000000"/> <x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/> <y distr="uniform" peak="1.000000"/>
</chan_width_distr> </chan_width_distr>
<switch_block type="wilton" fs="3"/> <switch_block type="wilton" fs="3"/>
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength. book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
@ -112,81 +111,81 @@
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables. 2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. --> This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/> <mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
</segment> </segment>
</segmentlist> </segmentlist>
<complexblocklist> <complexblocklist>
<!-- Define I/O pads begin --> <!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA --> <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. --> <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io"> <pb_type name="io">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- IOs can operate as either inputs or outputs. <!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them. today and that is when you timing analyze them.
--> -->
<mode name="inpad"> <mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<mode name="outpad"> <mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1"> <pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- IOs go on the periphery of the FPGA, for consistency, <!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed. make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
--> -->
<!-- Place I/Os on the sides of the FPGA --> <!-- Place I/Os on the sides of the FPGA -->
<power method="ignore"/> <power method="ignore"/>
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin --> <!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs. area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic This means that only 37% of our area is in the general routing, and 63% is inside the logic
@ -194,31 +193,31 @@
area in this analysis. That is a lower proportion of of routing area than most academics area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range. routing area up significantly, we estimate into the ~70% range.
--> -->
<pb_type name="clb"> <pb_type name="clb">
<input name="I" num_pins="40" equivalent="full"/> <input name="I" num_pins="40" equivalent="full"/>
<output name="O" num_pins="10" equivalent="none"/> <output name="O" num_pins="10" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Describe basic logic element. <!-- Describe basic logic element.
Each basic logic element has a 6-LUT that can be optionally registered Each basic logic element has a 6-LUT that can be optionally registered
--> -->
<pb_type name="fle" num_pb="10"> <pb_type name="fle" num_pb="10">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- 6-LUT mode definition begin --> <!-- 6-LUT mode definition begin -->
<mode name="n1_lut6"> <mode name="n1_lut6">
<!-- Define 6-LUT mode --> <!-- Define 6-LUT mode -->
<pb_type name="ble6" num_pb="1"> <pb_type name="ble6" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="6" port_class="lut_in"/> <input name="in" num_pins="6" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing, <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results we instead take the average of these numbers to get more stable results
82e-12 82e-12
173e-12 173e-12
@ -226,48 +225,48 @@
263e-12 263e-12
398e-12 398e-12
397e-12 397e-12
--> -->
<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out"> <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/> <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
<direct name="direct2" input="lut6.out" output="ff.D"> <direct name="direct2" input="lut6.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/> <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble6.clk" output="ff.clk"/> <direct name="direct3" input="ble6.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut6.out" output="ble6.out"> <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/> <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/> <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="ble6.in"/> <direct name="direct1" input="fle.in" output="ble6.in"/>
<direct name="direct2" input="ble6.out" output="fle.out[0:0]"/> <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble6.clk"/> <direct name="direct3" input="fle.clk" output="ble6.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- 6-LUT mode definition end --> <!-- 6-LUT mode definition end -->
</pb_type> </pb_type>
<interconnect> <interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB <!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining delay on the connection block input mux (modeled by Ian Kuon), so the remaining
@ -275,23 +274,23 @@
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT. The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. --> to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in"> <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
<delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/> <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
</complete> </complete>
<complete name="clks" input="clb.clk" output="fle[9:0].clk"> <complete name="clks" input="clb.clk" output="fle[9:0].clk">
</complete> </complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins. <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification). naive specification).
--> -->
<direct name="clbouts1" input="fle[9:0].out" output="clb.O"/> <direct name="clbouts1" input="fle[9:0].out" output="clb.O"/>
</interconnect> </interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- Place this general purpose logic block in any unspecified column --> <!-- Place this general purpose logic block in any unspecified column -->
</pb_type> </pb_type>
<!-- Define general purpose logic block (CLB) ends --> <!-- Define general purpose logic block (CLB) ends -->
</complexblocklist> </complexblocklist>
</architecture> </architecture>

691
openfpga_flow/vpr_arch/k6_frac_N10_40nm.xml
View File

@ -1,4 +1,4 @@
<!-- <?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0. Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
- 40 nm technology - 40 nm technology
@ -12,9 +12,8 @@
Based on flagship k6_frac_N10_mem32K_40nm.xml architecture. Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.
Authors: Jason Luu, Jeff Goeders, Vaughn Betz Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--> --><architecture>
<architecture> <!--
<!--
ODIN II specific config begins ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports. ".model [type_of_block]") that this architecture supports.
@ -22,78 +21,78 @@
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch) already special structures in blif (.names, .input, .output, and .latch)
that describe them. that describe them.
--> -->
<models> <models>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io"> <model name="io">
<input_ports> <input_ports>
<port name="outpad"/> <port name="outpad"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="inpad"/> <port name="inpad"/>
</output_ports> </output_ports>
</model> </model>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="frac_lut6"> <model name="frac_lut6">
<input_ports> <input_ports>
<port name="in"/> <port name="in"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="lut5_out"/> <port name="lut5_out"/>
<port name="lut6_out"/> <port name="lut6_out"/>
</output_ports> </output_ports>
</model> </model>
</models> </models>
<tiles> <tiles>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
If you need to register the I/O, define clocks in the circuit models If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end These clocks can be handled in back-end
--> -->
<tile name="io" capacity="8" area="0"> <tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc> <loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc> <loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc> <loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc> <loc side="bottom">io.outpad io.inpad</loc>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
<tile name="clb" area="53894"> <tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites> <equivalent_sites>
<site pb_type="clb"/> <site pb_type="clb"/>
</equivalent_sites> </equivalent_sites>
<input name="I" num_pins="40" equivalent="full"/> <input name="I" num_pins="40" equivalent="full"/>
<output name="O" num_pins="20" equivalent="none"/> <output name="O" num_pins="20" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/> <pinlocations pattern="spread"/>
</tile> </sub_tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
<!-- Physical descriptions begin --> <!-- Physical descriptions begin -->
<layout tileable="false"> <layout tileable="false">
<auto_layout aspect_ratio="1.0"> <auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</auto_layout> </auto_layout>
<fixed_layout name="2x2" width="4" height="4"> <fixed_layout name="2x2" width="4" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
@ -107,21 +106,21 @@
The delay values are lined up with Stratix IV, which has an architecture similar to this The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. --> 4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
--> -->
<area grid_logic_tile_area="0"/> <area grid_logic_tile_area="0"/>
<chan_width_distr> <chan_width_distr>
<x distr="uniform" peak="1.000000"/> <x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/> <y distr="uniform" peak="1.000000"/>
</chan_width_distr> </chan_width_distr>
<switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/> <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength. book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
@ -133,87 +132,87 @@
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables. 2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. --> This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! --> <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/> <mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
</segment> </segment>
</segmentlist> </segmentlist>
<complexblocklist> <complexblocklist>
<!-- Define I/O pads begin --> <!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA --> <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. --> <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io"> <pb_type name="io">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
If you need to register the I/O, define clocks in the circuit models If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end These clocks can be handled in back-end
--> -->
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- IOs can operate as either inputs or outputs. <!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them. today and that is when you timing analyze them.
--> -->
<mode name="inpad"> <mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<mode name="outpad"> <mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1"> <pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- IOs go on the periphery of the FPGA, for consistency, <!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed. make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
--> -->
<!-- Place I/Os on the sides of the FPGA --> <!-- Place I/Os on the sides of the FPGA -->
<power method="ignore"/> <power method="ignore"/>
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin --> <!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs. area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic This means that only 37% of our area is in the general routing, and 63% is inside the logic
@ -221,152 +220,152 @@
area in this analysis. That is a lower proportion of of routing area than most academics area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range. routing area up significantly, we estimate into the ~70% range.
--> -->
<pb_type name="clb"> <pb_type name="clb">
<input name="I" num_pins="40" equivalent="full"/> <input name="I" num_pins="40" equivalent="full"/>
<output name="O" num_pins="20" equivalent="none"/> <output name="O" num_pins="20" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Describe fracturable logic element. <!-- Describe fracturable logic element.
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
The outputs of the fracturable logic element can be optionally registered The outputs of the fracturable logic element can be optionally registered
--> -->
<pb_type name="fle" num_pb="10"> <pb_type name="fle" num_pb="10">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<pb_type name="frac_logic" num_pb="1"> <pb_type name="frac_logic" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1"> <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<output name="lut5_out" num_pins="2"/> <output name="lut5_out" num_pins="2"/>
<output name="lut6_out" num_pins="1"/> <output name="lut6_out" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/> <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
<direct name="direct2" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/> <direct name="direct2" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
<!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] --> <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
<mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/> <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
</interconnect> </interconnect>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/> <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
<direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/> <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
<complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/> <complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]"> <mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/> <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/> <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux> </mux>
<mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]"> <mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/> <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/> <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="fabric.in"/> <direct name="direct1" input="fle.in" output="fabric.in"/>
<direct name="direct2" input="fabric.out" output="fle.out"/> <direct name="direct2" input="fabric.out" output="fle.out"/>
<direct name="direct3" input="fle.clk" output="fabric.clk"/> <direct name="direct3" input="fle.clk" output="fabric.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- Physical mode definition end (physical implementation of the fle) --> <!-- Physical mode definition end (physical implementation of the fle) -->
<!-- Dual 5-LUT mode definition begin --> <!-- Dual 5-LUT mode definition begin -->
<mode name="n2_lut5"> <mode name="n2_lut5">
<pb_type name="lut5inter" num_pb="1"> <pb_type name="lut5inter" num_pb="1">
<input name="in" num_pins="5"/> <input name="in" num_pins="5"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<pb_type name="ble5" num_pb="2"> <pb_type name="ble5" num_pb="2">
<input name="in" num_pins="5"/> <input name="in" num_pins="5"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define the LUT --> <!-- Define the LUT -->
<pb_type name="lut5" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="5" port_class="lut_in"/> <input name="in" num_pins="5" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing, <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results we instead take the average of these numbers to get more stable results
82e-12 82e-12
173e-12 173e-12
261e-12 261e-12
263e-12 263e-12
398e-12 398e-12
--> -->
<delay_matrix type="max" in_port="lut5.in" out_port="lut5.out"> <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
235e-12 235e-12
235e-12 235e-12
235e-12 235e-12
235e-12 235e-12
235e-12 235e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define the flip-flop --> <!-- Define the flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble5.in[4:0]" output="lut5[0:0].in[4:0]"/> <direct name="direct1" input="ble5.in[4:0]" output="lut5[0:0].in[4:0]"/>
<direct name="direct2" input="lut5[0:0].out" output="ff[0:0].D"> <direct name="direct2" input="lut5[0:0].out" output="ff[0:0].D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble5" in_port="lut5[0:0].out" out_port="ff[0:0].D"/> <pack_pattern name="ble5" in_port="lut5[0:0].out" out_port="ff[0:0].D"/>
</direct> </direct>
<direct name="direct3" input="ble5.clk" output="ff[0:0].clk"/> <direct name="direct3" input="ble5.clk" output="ff[0:0].clk"/>
<mux name="mux1" input="ff[0:0].Q lut5.out[0:0]" output="ble5.out[0:0]"> <mux name="mux1" input="ff[0:0].Q lut5.out[0:0]" output="ble5.out[0:0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut5.out[0:0]" out_port="ble5.out[0:0]"/> <delay_constant max="25e-12" in_port="lut5.out[0:0]" out_port="ble5.out[0:0]"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble5.out[0:0]"/> <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble5.out[0:0]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/> <direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
<direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/> <direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
<direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/> <direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
<complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/> <complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/> <direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
<direct name="direct2" input="lut5inter.out" output="fle.out"/> <direct name="direct2" input="lut5inter.out" output="fle.out"/>
<direct name="direct3" input="fle.clk" output="lut5inter.clk"/> <direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- Dual 5-LUT mode definition end --> <!-- Dual 5-LUT mode definition end -->
<!-- 6-LUT mode definition begin --> <!-- 6-LUT mode definition begin -->
<mode name="n1_lut6"> <mode name="n1_lut6">
<!-- Define 6-LUT mode --> <!-- Define 6-LUT mode -->
<pb_type name="ble6" num_pb="1"> <pb_type name="ble6" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="6" port_class="lut_in"/> <input name="in" num_pins="6" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing, <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results we instead take the average of these numbers to get more stable results
82e-12 82e-12
173e-12 173e-12
@ -374,48 +373,48 @@
263e-12 263e-12
398e-12 398e-12
397e-12 397e-12
--> -->
<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out"> <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/> <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
<direct name="direct2" input="lut6.out" output="ff.D"> <direct name="direct2" input="lut6.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/> <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble6.clk" output="ff.clk"/> <direct name="direct3" input="ble6.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut6.out" output="ble6.out"> <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/> <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/> <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="ble6.in"/> <direct name="direct1" input="fle.in" output="ble6.in"/>
<direct name="direct2" input="ble6.out" output="fle.out[0:0]"/> <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble6.clk"/> <direct name="direct3" input="fle.clk" output="ble6.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- 6-LUT mode definition end --> <!-- 6-LUT mode definition end -->
</pb_type> </pb_type>
<interconnect> <interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB <!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining delay on the connection block input mux (modeled by Ian Kuon), so the remaining
@ -423,24 +422,24 @@
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT. The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. --> to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in"> <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
<delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/> <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
</complete> </complete>
<complete name="clks" input="clb.clk" output="fle[9:0].clk"> <complete name="clks" input="clb.clk" output="fle[9:0].clk">
</complete> </complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins. <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification). naive specification).
--> -->
<direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/> <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
<direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/> <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
</interconnect> </interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- Place this general purpose logic block in any unspecified column --> <!-- Place this general purpose logic block in any unspecified column -->
</pb_type> </pb_type>
<!-- Define general purpose logic block (CLB) ends --> <!-- Define general purpose logic block (CLB) ends -->
</complexblocklist> </complexblocklist>
</architecture> </architecture>

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openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_40nm.xml
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openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
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openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
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@ -1,4 +1,4 @@
<!-- <?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0. Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
- 40 nm technology - 40 nm technology
@ -12,9 +12,8 @@
Based on flagship k6_frac_N10_mem32K_40nm.xml architecture. Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.
Authors: Jason Luu, Jeff Goeders, Vaughn Betz Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--> --><architecture>
<architecture> <!--
<!--
ODIN II specific config begins ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports. ".model [type_of_block]") that this architecture supports.
@ -22,78 +21,78 @@
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch) already special structures in blif (.names, .input, .output, and .latch)
that describe them. that describe them.
--> -->
<models> <models>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io"> <model name="io">
<input_ports> <input_ports>
<port name="outpad"/> <port name="outpad"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="inpad"/> <port name="inpad"/>
</output_ports> </output_ports>
</model> </model>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="frac_lut6"> <model name="frac_lut6">
<input_ports> <input_ports>
<port name="in"/> <port name="in"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="lut5_out"/> <port name="lut5_out"/>
<port name="lut6_out"/> <port name="lut6_out"/>
</output_ports> </output_ports>
</model> </model>
</models> </models>
<tiles> <tiles>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
If you need to register the I/O, define clocks in the circuit models If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end These clocks can be handled in back-end
--> -->
<tile name="io" capacity="8" area="0"> <tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc> <loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc> <loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc> <loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc> <loc side="bottom">io.outpad io.inpad</loc>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
<tile name="clb" area="53894"> <tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites> <equivalent_sites>
<site pb_type="clb"/> <site pb_type="clb"/>
</equivalent_sites> </equivalent_sites>
<input name="I" num_pins="40" equivalent="full"/> <input name="I" num_pins="40" equivalent="full"/>
<output name="O" num_pins="20" equivalent="none"/> <output name="O" num_pins="20" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/> <pinlocations pattern="spread"/>
</tile> </sub_tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
<!-- Physical descriptions begin --> <!-- Physical descriptions begin -->
<layout tileable="true"> <layout tileable="true">
<auto_layout aspect_ratio="1.0"> <auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</auto_layout> </auto_layout>
<fixed_layout name="2x2" width="4" height="4"> <fixed_layout name="2x2" width="4" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
@ -107,21 +106,21 @@
The delay values are lined up with Stratix IV, which has an architecture similar to this The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. --> 4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
--> -->
<area grid_logic_tile_area="0"/> <area grid_logic_tile_area="0"/>
<chan_width_distr> <chan_width_distr>
<x distr="uniform" peak="1.000000"/> <x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/> <y distr="uniform" peak="1.000000"/>
</chan_width_distr> </chan_width_distr>
<switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/> <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength. book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
@ -133,87 +132,87 @@
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables. 2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. --> This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! --> <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/> <mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
</segment> </segment>
</segmentlist> </segmentlist>
<complexblocklist> <complexblocklist>
<!-- Define I/O pads begin --> <!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA --> <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. --> <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io"> <pb_type name="io">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
If you need to register the I/O, define clocks in the circuit models If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end These clocks can be handled in back-end
--> -->
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- IOs can operate as either inputs or outputs. <!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them. today and that is when you timing analyze them.
--> -->
<mode name="inpad"> <mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<mode name="outpad"> <mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1"> <pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- IOs go on the periphery of the FPGA, for consistency, <!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed. make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
--> -->
<!-- Place I/Os on the sides of the FPGA --> <!-- Place I/Os on the sides of the FPGA -->
<power method="ignore"/> <power method="ignore"/>
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin --> <!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs. area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic This means that only 37% of our area is in the general routing, and 63% is inside the logic
@ -221,152 +220,152 @@
area in this analysis. That is a lower proportion of of routing area than most academics area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range. routing area up significantly, we estimate into the ~70% range.
--> -->
<pb_type name="clb"> <pb_type name="clb">
<input name="I" num_pins="40" equivalent="full"/> <input name="I" num_pins="40" equivalent="full"/>
<output name="O" num_pins="20" equivalent="none"/> <output name="O" num_pins="20" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Describe fracturable logic element. <!-- Describe fracturable logic element.
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
The outputs of the fracturable logic element can be optionally registered The outputs of the fracturable logic element can be optionally registered
--> -->
<pb_type name="fle" num_pb="10"> <pb_type name="fle" num_pb="10">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<pb_type name="frac_logic" num_pb="1"> <pb_type name="frac_logic" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1"> <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<output name="lut5_out" num_pins="2"/> <output name="lut5_out" num_pins="2"/>
<output name="lut6_out" num_pins="1"/> <output name="lut6_out" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/> <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
<direct name="direct2" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/> <direct name="direct2" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
<!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] --> <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
<mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/> <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
</interconnect> </interconnect>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/> <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
<direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/> <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
<complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/> <complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]"> <mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/> <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/> <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux> </mux>
<mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]"> <mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/> <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/> <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="fabric.in"/> <direct name="direct1" input="fle.in" output="fabric.in"/>
<direct name="direct2" input="fabric.out" output="fle.out"/> <direct name="direct2" input="fabric.out" output="fle.out"/>
<direct name="direct3" input="fle.clk" output="fabric.clk"/> <direct name="direct3" input="fle.clk" output="fabric.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- Physical mode definition end (physical implementation of the fle) --> <!-- Physical mode definition end (physical implementation of the fle) -->
<!-- Dual 5-LUT mode definition begin --> <!-- Dual 5-LUT mode definition begin -->
<mode name="n2_lut5"> <mode name="n2_lut5">
<pb_type name="lut5inter" num_pb="1"> <pb_type name="lut5inter" num_pb="1">
<input name="in" num_pins="5"/> <input name="in" num_pins="5"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<pb_type name="ble5" num_pb="2"> <pb_type name="ble5" num_pb="2">
<input name="in" num_pins="5"/> <input name="in" num_pins="5"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define the LUT --> <!-- Define the LUT -->
<pb_type name="lut5" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="5" port_class="lut_in"/> <input name="in" num_pins="5" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing, <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results we instead take the average of these numbers to get more stable results
82e-12 82e-12
173e-12 173e-12
261e-12 261e-12
263e-12 263e-12
398e-12 398e-12
--> -->
<delay_matrix type="max" in_port="lut5.in" out_port="lut5.out"> <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
235e-12 235e-12
235e-12 235e-12
235e-12 235e-12
235e-12 235e-12
235e-12 235e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define the flip-flop --> <!-- Define the flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble5.in[4:0]" output="lut5[0:0].in[4:0]"/> <direct name="direct1" input="ble5.in[4:0]" output="lut5[0:0].in[4:0]"/>
<direct name="direct2" input="lut5[0:0].out" output="ff[0:0].D"> <direct name="direct2" input="lut5[0:0].out" output="ff[0:0].D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble5" in_port="lut5[0:0].out" out_port="ff[0:0].D"/> <pack_pattern name="ble5" in_port="lut5[0:0].out" out_port="ff[0:0].D"/>
</direct> </direct>
<direct name="direct3" input="ble5.clk" output="ff[0:0].clk"/> <direct name="direct3" input="ble5.clk" output="ff[0:0].clk"/>
<mux name="mux1" input="ff[0:0].Q lut5.out[0:0]" output="ble5.out[0:0]"> <mux name="mux1" input="ff[0:0].Q lut5.out[0:0]" output="ble5.out[0:0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut5.out[0:0]" out_port="ble5.out[0:0]"/> <delay_constant max="25e-12" in_port="lut5.out[0:0]" out_port="ble5.out[0:0]"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble5.out[0:0]"/> <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble5.out[0:0]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/> <direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
<direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/> <direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
<direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/> <direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
<complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/> <complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/> <direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
<direct name="direct2" input="lut5inter.out" output="fle.out"/> <direct name="direct2" input="lut5inter.out" output="fle.out"/>
<direct name="direct3" input="fle.clk" output="lut5inter.clk"/> <direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- Dual 5-LUT mode definition end --> <!-- Dual 5-LUT mode definition end -->
<!-- 6-LUT mode definition begin --> <!-- 6-LUT mode definition begin -->
<mode name="n1_lut6"> <mode name="n1_lut6">
<!-- Define 6-LUT mode --> <!-- Define 6-LUT mode -->
<pb_type name="ble6" num_pb="1"> <pb_type name="ble6" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="6" port_class="lut_in"/> <input name="in" num_pins="6" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing, <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results we instead take the average of these numbers to get more stable results
82e-12 82e-12
173e-12 173e-12
@ -374,48 +373,48 @@
263e-12 263e-12
398e-12 398e-12
397e-12 397e-12
--> -->
<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out"> <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/> <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
<direct name="direct2" input="lut6.out" output="ff.D"> <direct name="direct2" input="lut6.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/> <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble6.clk" output="ff.clk"/> <direct name="direct3" input="ble6.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut6.out" output="ble6.out"> <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/> <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/> <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="ble6.in"/> <direct name="direct1" input="fle.in" output="ble6.in"/>
<direct name="direct2" input="ble6.out" output="fle.out[0:0]"/> <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble6.clk"/> <direct name="direct3" input="fle.clk" output="ble6.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- 6-LUT mode definition end --> <!-- 6-LUT mode definition end -->
</pb_type> </pb_type>
<interconnect> <interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB <!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining delay on the connection block input mux (modeled by Ian Kuon), so the remaining
@ -423,24 +422,24 @@
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT. The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. --> to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in"> <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
<delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/> <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
</complete> </complete>
<complete name="clks" input="clb.clk" output="fle[9:0].clk"> <complete name="clks" input="clb.clk" output="fle[9:0].clk">
</complete> </complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins. <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification). naive specification).
--> -->
<direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/> <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
<direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/> <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
</interconnect> </interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- Place this general purpose logic block in any unspecified column --> <!-- Place this general purpose logic block in any unspecified column -->
</pb_type> </pb_type>
<!-- Define general purpose logic block (CLB) ends --> <!-- Define general purpose logic block (CLB) ends -->
</complexblocklist> </complexblocklist>
</architecture> </architecture>

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@ -1,4 +1,4 @@
<!-- <?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0. Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
- 40 nm technology - 40 nm technology
@ -12,9 +12,8 @@
Based on flagship k6_frac_N10_mem32K_40nm.xml architecture. Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.
Authors: Jason Luu, Jeff Goeders, Vaughn Betz Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--> --><architecture>
<architecture> <!--
<!--
ODIN II specific config begins ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports. ".model [type_of_block]") that this architecture supports.
@ -22,78 +21,78 @@
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch) already special structures in blif (.names, .input, .output, and .latch)
that describe them. that describe them.
--> -->
<models> <models>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io"> <model name="io">
<input_ports> <input_ports>
<port name="outpad"/> <port name="outpad"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="inpad"/> <port name="inpad"/>
</output_ports> </output_ports>
</model> </model>
<!-- A virtual model for I/O to be used in the physical mode of io block --> <!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="frac_lut6"> <model name="frac_lut6">
<input_ports> <input_ports>
<port name="in"/> <port name="in"/>
</input_ports> </input_ports>
<output_ports> <output_ports>
<port name="lut5_out"/> <port name="lut5_out"/>
<port name="lut6_out"/> <port name="lut6_out"/>
</output_ports> </output_ports>
</model> </model>
</models> </models>
<tiles> <tiles>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
If you need to register the I/O, define clocks in the circuit models If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end These clocks can be handled in back-end
--> -->
<tile name="io" capacity="8" area="0"> <tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc> <loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc> <loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc> <loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc> <loc side="bottom">io.outpad io.inpad</loc>
</pinlocations> </pinlocations>
</tile> </sub_tile> </tile>
<tile name="clb" area="53894"> <tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites> <equivalent_sites>
<site pb_type="clb"/> <site pb_type="clb"/>
</equivalent_sites> </equivalent_sites>
<input name="I" num_pins="32" equivalent="full"/> <input name="I" num_pins="32" equivalent="full"/>
<output name="O" num_pins="16" equivalent="none"/> <output name="O" num_pins="16" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/> <pinlocations pattern="spread"/>
</tile> </sub_tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
<!-- Physical descriptions begin --> <!-- Physical descriptions begin -->
<layout tileable="true"> <layout tileable="true">
<auto_layout aspect_ratio="1.0"> <auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</auto_layout> </auto_layout>
<fixed_layout name="2x2" width="4" height="4"> <fixed_layout name="2x2" width="4" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
</layout> </layout>
<device> <device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
@ -107,21 +106,21 @@
The delay values are lined up with Stratix IV, which has an architecture similar to this The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. --> 4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/> <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing) <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file. area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
--> -->
<area grid_logic_tile_area="0"/> <area grid_logic_tile_area="0"/>
<chan_width_distr> <chan_width_distr>
<x distr="uniform" peak="1.000000"/> <x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/> <y distr="uniform" peak="1.000000"/>
</chan_width_distr> </chan_width_distr>
<switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/> <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
<connection_block input_switch_name="ipin_cblock"/> <connection_block input_switch_name="ipin_cblock"/>
</device> </device>
<switchlist> <switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength. book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
@ -133,87 +132,87 @@
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables. 2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. --> This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/> <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer--> <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/> <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
</switchlist> </switchlist>
<segmentlist> <segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space. <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! --> <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15"> <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<mux name="0"/> <mux name="0"/>
<sb type="pattern">1 1 1 1 1</sb> <sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb> <cb type="pattern">1 1 1 1</cb>
</segment> </segment>
</segmentlist> </segmentlist>
<complexblocklist> <complexblocklist>
<!-- Define I/O pads begin --> <!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA --> <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. --> <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io"> <pb_type name="io">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
If you need to register the I/O, define clocks in the circuit models If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end These clocks can be handled in back-end
--> -->
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad"> <direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct> </direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad"> <direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- IOs can operate as either inputs or outputs. <!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them. today and that is when you timing analyze them.
--> -->
<mode name="inpad"> <mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<mode name="outpad"> <mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1"> <pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- IOs go on the periphery of the FPGA, for consistency, <!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed. make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
--> -->
<!-- Place I/Os on the sides of the FPGA --> <!-- Place I/Os on the sides of the FPGA -->
<power method="ignore"/> <power method="ignore"/>
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin --> <!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs. area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic This means that only 37% of our area is in the general routing, and 63% is inside the logic
@ -221,152 +220,152 @@
area in this analysis. That is a lower proportion of of routing area than most academics area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range. routing area up significantly, we estimate into the ~70% range.
--> -->
<pb_type name="clb"> <pb_type name="clb">
<input name="I" num_pins="32" equivalent="full"/> <input name="I" num_pins="32" equivalent="full"/>
<output name="O" num_pins="16" equivalent="none"/> <output name="O" num_pins="16" equivalent="none"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Describe fracturable logic element. <!-- Describe fracturable logic element.
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
The outputs of the fracturable logic element can be optionally registered The outputs of the fracturable logic element can be optionally registered
--> -->
<pb_type name="fle" num_pb="8"> <pb_type name="fle" num_pb="8">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disable_packing="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<pb_type name="frac_logic" num_pb="1"> <pb_type name="frac_logic" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1"> <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<output name="lut5_out" num_pins="2"/> <output name="lut5_out" num_pins="2"/>
<output name="lut6_out" num_pins="1"/> <output name="lut6_out" num_pins="1"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/> <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
<direct name="direct2" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/> <direct name="direct2" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
<!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] --> <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
<mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/> <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
</interconnect> </interconnect>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/> <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
<direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/> <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
<complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/> <complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]"> <mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/> <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/> <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
</mux> </mux>
<mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]"> <mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/> <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/> <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="fabric.in"/> <direct name="direct1" input="fle.in" output="fabric.in"/>
<direct name="direct2" input="fabric.out" output="fle.out"/> <direct name="direct2" input="fabric.out" output="fle.out"/>
<direct name="direct3" input="fle.clk" output="fabric.clk"/> <direct name="direct3" input="fle.clk" output="fabric.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- Physical mode definition end (physical implementation of the fle) --> <!-- Physical mode definition end (physical implementation of the fle) -->
<!-- Dual 5-LUT mode definition begin --> <!-- Dual 5-LUT mode definition begin -->
<mode name="n2_lut5"> <mode name="n2_lut5">
<pb_type name="lut5inter" num_pb="1"> <pb_type name="lut5inter" num_pb="1">
<input name="in" num_pins="5"/> <input name="in" num_pins="5"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<pb_type name="ble5" num_pb="2"> <pb_type name="ble5" num_pb="2">
<input name="in" num_pins="5"/> <input name="in" num_pins="5"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define the LUT --> <!-- Define the LUT -->
<pb_type name="lut5" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="5" port_class="lut_in"/> <input name="in" num_pins="5" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing, <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results we instead take the average of these numbers to get more stable results
82e-12 82e-12
173e-12 173e-12
261e-12 261e-12
263e-12 263e-12
398e-12 398e-12
--> -->
<delay_matrix type="max" in_port="lut5.in" out_port="lut5.out"> <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
235e-12 235e-12
235e-12 235e-12
235e-12 235e-12
235e-12 235e-12
235e-12 235e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define the flip-flop --> <!-- Define the flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble5.in[4:0]" output="lut5[0:0].in[4:0]"/> <direct name="direct1" input="ble5.in[4:0]" output="lut5[0:0].in[4:0]"/>
<direct name="direct2" input="lut5[0:0].out" output="ff[0:0].D"> <direct name="direct2" input="lut5[0:0].out" output="ff[0:0].D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble5" in_port="lut5[0:0].out" out_port="ff[0:0].D"/> <pack_pattern name="ble5" in_port="lut5[0:0].out" out_port="ff[0:0].D"/>
</direct> </direct>
<direct name="direct3" input="ble5.clk" output="ff[0:0].clk"/> <direct name="direct3" input="ble5.clk" output="ff[0:0].clk"/>
<mux name="mux1" input="ff[0:0].Q lut5.out[0:0]" output="ble5.out[0:0]"> <mux name="mux1" input="ff[0:0].Q lut5.out[0:0]" output="ble5.out[0:0]">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut5.out[0:0]" out_port="ble5.out[0:0]"/> <delay_constant max="25e-12" in_port="lut5.out[0:0]" out_port="ble5.out[0:0]"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble5.out[0:0]"/> <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble5.out[0:0]"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/> <direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
<direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/> <direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
<direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/> <direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
<complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/> <complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/> <direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
<direct name="direct2" input="lut5inter.out" output="fle.out"/> <direct name="direct2" input="lut5inter.out" output="fle.out"/>
<direct name="direct3" input="fle.clk" output="lut5inter.clk"/> <direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- Dual 5-LUT mode definition end --> <!-- Dual 5-LUT mode definition end -->
<!-- 6-LUT mode definition begin --> <!-- 6-LUT mode definition begin -->
<mode name="n1_lut6"> <mode name="n1_lut6">
<!-- Define 6-LUT mode --> <!-- Define 6-LUT mode -->
<pb_type name="ble6" num_pb="1"> <pb_type name="ble6" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Define LUT --> <!-- Define LUT -->
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut"> <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
<input name="in" num_pins="6" port_class="lut_in"/> <input name="in" num_pins="6" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/> <output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix --> <!-- LUT timing using delay matrix -->
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing, <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
we instead take the average of these numbers to get more stable results we instead take the average of these numbers to get more stable results
82e-12 82e-12
173e-12 173e-12
@ -374,48 +373,48 @@
263e-12 263e-12
398e-12 398e-12
397e-12 397e-12
--> -->
<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out"> <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
261e-12 261e-12
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/> <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
<direct name="direct2" input="lut6.out" output="ff.D"> <direct name="direct2" input="lut6.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist --> <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/> <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
</direct> </direct>
<direct name="direct3" input="ble6.clk" output="ff.clk"/> <direct name="direct3" input="ble6.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut6.out" output="ble6.out"> <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
<!-- LUT to output is faster than FF to output on a Stratix IV --> <!-- LUT to output is faster than FF to output on a Stratix IV -->
<delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/> <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/> <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="fle.in" output="ble6.in"/> <direct name="direct1" input="fle.in" output="ble6.in"/>
<direct name="direct2" input="ble6.out" output="fle.out[0:0]"/> <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble6.clk"/> <direct name="direct3" input="fle.clk" output="ble6.clk"/>
</interconnect> </interconnect>
</mode> </mode>
<!-- 6-LUT mode definition end --> <!-- 6-LUT mode definition end -->
</pb_type> </pb_type>
<interconnect> <interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB <!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining delay on the connection block input mux (modeled by Ian Kuon), so the remaining
@ -423,24 +422,24 @@
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT. The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. --> to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[7:0].out" output="fle[7:0].in"> <complete name="crossbar" input="clb.I fle[7:0].out" output="fle[7:0].in">
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[7:0].in"/> <delay_constant max="95e-12" in_port="clb.I" out_port="fle[7:0].in"/>
<delay_constant max="75e-12" in_port="fle[7:0].out" out_port="fle[7:0].in"/> <delay_constant max="75e-12" in_port="fle[7:0].out" out_port="fle[7:0].in"/>
</complete> </complete>
<complete name="clks" input="clb.clk" output="fle[7:0].clk"> <complete name="clks" input="clb.clk" output="fle[7:0].clk">
</complete> </complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins. <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification). naive specification).
--> -->
<direct name="clbouts1" input="fle[7:0].out[0:0]" output="clb.O[7:0]"/> <direct name="clbouts1" input="fle[7:0].out[0:0]" output="clb.O[7:0]"/>
<direct name="clbouts2" input="fle[7:0].out[1:1]" output="clb.O[15:8]"/> <direct name="clbouts2" input="fle[7:0].out[1:1]" output="clb.O[15:8]"/>
</interconnect> </interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel --> <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<!-- Place this general purpose logic block in any unspecified column --> <!-- Place this general purpose logic block in any unspecified column -->
</pb_type> </pb_type>
<!-- Define general purpose logic block (CLB) ends --> <!-- Define general purpose logic block (CLB) ends -->
</complexblocklist> </complexblocklist>
</architecture> </architecture>