From bd158311c55e733cc5c726c9b095b92d979ebb07 Mon Sep 17 00:00:00 2001
From: Aram Kostanyan <aram@rapidsilicon.com>
Date: Tue, 18 Jan 2022 14:07:41 +0500
Subject: [PATCH] Fixed typo in documentation and updated
 'benchmark_sweep/iwls2005' task to use list of HDL files for
 'iwls2005/ethernet' benchmark.

---
 docs/source/manual/openfpga_flow/run_fpga_task.rst            | 3 +--
 openfpga_flow/tasks/benchmark_sweep/iwls2005/config/task.conf | 2 +-
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/docs/source/manual/openfpga_flow/run_fpga_task.rst b/docs/source/manual/openfpga_flow/run_fpga_task.rst
index 9540a7082..e47a021cc 100644
--- a/docs/source/manual/openfpga_flow/run_fpga_task.rst
+++ b/docs/source/manual/openfpga_flow/run_fpga_task.rst
@@ -212,8 +212,7 @@ Benchmarks Sections
 .. option:: bench<bench_label>=<list_of_files_in_benchmark>
 
     The ``bench_label`` variable can be any number of string without
-    white-spaces. ``xml_architecture_file_path`` is path to the actual XML
-    architecture file
+    white-spaces. ``list_of_files_in_benchmark`` is a list of benchmark HDL files paths.
 
     For Example following code shows how to define a benchmarks,
     with a single file, multiple files and files added from a specific directory.
diff --git a/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/task.conf
index 0af8166ca..823da5aac 100644
--- a/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/task.conf
+++ b/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/task.conf
@@ -37,7 +37,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_ch
 # RTL netlists from IWLS 2005 benchmark release
 # Comment out it requires falling edge latches which are not supported yet
 #bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/*.v
-bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/*.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_clockgen.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_crc.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_defines.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_fifo.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_maccontrol.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_macstatus.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_miim.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_outputcontrol.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_random.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_receivecontrol.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_register.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_registers.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_rxaddrcheck.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_rxcounters.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_rxethmac.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_rxstatem.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_shiftreg.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_spram_256x32.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_top.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_transmitcontrol.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_txcounters.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_txethmac.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_txstatem.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_wishbone.v,${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/timescale.v
 bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/*.v
 bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/simple_spi/rtl/*.v
 # Comment out due to VHDL is not supported by Yosys without Verific