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[Tool] Add new option 'testbench_type' so that simulation task can write different information for different testbenches

This commit is contained in:
tangxifan 2021-06-25 10:10:16 -06:00
parent 91a2dc4fd7
commit bcc16d732c
5 changed files with 60 additions and 8 deletions
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23
openfpga/src/base/openfpga_verilog.cpp
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@ -219,6 +219,7 @@ int write_simulation_task_info(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_file = cmd.option("file");
CommandOptionId opt_hdl_dir = cmd.option("hdl_dir");
CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path");
CommandOptionId opt_tb_type = cmd.option("testbench_type");
CommandOptionId opt_verbose = cmd.option("verbose");
/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
@ -230,6 +231,28 @@ int write_simulation_task_info(const OpenfpgaContext& openfpga_ctx,
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_print_simulation_ini(cmd_context.option_value(cmd, opt_file));
/* Identify testbench type */
std::string full_tb_tag("full_testbench");
std::string preconfig_tb_tag("preconfigured_testbench");
if (true == cmd_context.option_enable(cmd, opt_tb_type)) {
if (std::string("preconfigured_testbench") == cmd_context.option_value(cmd, opt_tb_type)) {
options.set_print_preconfig_top_testbench(true);
} else if (std::string("full_testbench") == cmd_context.option_value(cmd, opt_tb_type)) {
options.set_print_preconfig_top_testbench(false);
options.set_print_top_testbench(true);
} else {
/* Invalid option, error out */
VTR_LOG_ERROR("Invalid option value for testbench type: '%s'! Should be either '%s' or '%s'\n",
cmd_context.option_value(cmd, opt_tb_type).c_str(),
full_tb_tag.c_str(),
preconfig_tb_tag.c_str());
return CMD_EXEC_FATAL_ERROR;
}
} else {
/* Deposit default type which is the preconfigured testbench */
options.set_print_preconfig_top_testbench(true);
}
return fpga_verilog_simulation_task_info(openfpga_ctx.module_graph(),
openfpga_ctx.bitstream_manager(),
g_vpr_ctx.atom(),

4
openfpga/src/base/openfpga_verilog_command.cpp
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@ -243,6 +243,10 @@ ShellCommandId add_openfpga_write_simulation_task_info_command(openfpga::Shell<O
CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", true, "Specify the file path to the reference Verilog netlist");
shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING);
/* Add an option '--testbench_type'*/
CommandOptionId tb_type_opt = shell_cmd.add_option("testbench_type", false, "Specify the type of testbenches to be considered. Different testbenches have different simulation parameters.");
shell_cmd.set_option_require_value(tb_type_opt, openfpga::OPT_STRING);
/* Add an option '--verbose' */
shell_cmd.add_option("verbose", false, "Enable verbose output");

1
openfpga/src/fpga_verilog/verilog_api.cpp
View File

@ -323,6 +323,7 @@ int fpga_verilog_simulation_task_info(const ModuleManager &module_manager,
std::string simulation_ini_file_name = options.simulation_ini_path();
VTR_ASSERT(true != options.simulation_ini_path().empty());
print_verilog_simulation_info(simulation_ini_file_name,
options,
netlist_name,
src_dir_path,
atom_ctx, place_ctx, io_location_map,

38
openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp
View File

@ -31,6 +31,7 @@ namespace openfpga {
* information, in order to interface different Verilog simulators
********************************************************************/
void print_verilog_simulation_info(const std::string& ini_fname,
const VerilogTestbenchOption& options,
const std::string& circuit_name,
const std::string& src_dir,
const AtomContext& atom_ctx,
@ -61,22 +62,43 @@ void print_verilog_simulation_info(const std::string& ini_fname,
// units_map['s']=1; // units_map['ms']=1E-3; // units_map['us']=1E-6;
// units_map['ns']=1E-9; // units_map['ps']=1E-12; // units_map['fs']=1E-15;
/* Compute simulation time period */
float simulation_time_period = find_simulation_time_period(1E-3,
num_program_clock_cycles,
1. / prog_clock_freq,
num_operating_clock_cycles,
1. / op_clock_freq);
/* Compute simulation time period: full testbench and pre-configured testbench has different length
* Currently, we only support the two types. And one of them must be enabled when outputting this file
*/
float simulation_time_period = 0.;
if (options.print_top_testbench()) {
simulation_time_period = find_simulation_time_period(1E-3,
num_program_clock_cycles,
1. / prog_clock_freq,
num_operating_clock_cycles,
1. / op_clock_freq);
} else {
VTR_ASSERT(options.print_preconfig_top_testbench());
/* Added 2 additional clock cycles due to reset/set cycles */
simulation_time_period = find_operating_phase_simulation_time(1.,
num_operating_clock_cycles + 2,
1. / op_clock_freq,
1E-3);
}
/* Identify the testbench file name depending on the type */
std::string top_tb_name;
if (options.print_top_testbench()) {
top_tb_name = circuit_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX);
} else {
VTR_ASSERT(options.print_preconfig_top_testbench());
top_tb_name = circuit_name + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX);
}
/* Basic information */
ini["SIMULATION_DECK"]["PROJECTNAME "] = "ModelSimProject";
ini["SIMULATION_DECK"]["BENCHMARK "] = circuit_name;
ini["SIMULATION_DECK"]["TOP_TB"] = circuit_name + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX);
ini["SIMULATION_DECK"]["TOP_TB"] = top_tb_name;
ini["SIMULATION_DECK"]["SIMTIME "] = std::to_string(simulation_time_period);
ini["SIMULATION_DECK"]["UNIT "] = "ms";
ini["SIMULATION_DECK"]["VERILOG_PATH "] = std::string(src_dir);
ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(DEFINES_VERILOG_FILE_NAME);
ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME);
ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX));
ini["SIMULATION_DECK"]["CONFIG_PROTOCOL"] = std::string(CONFIG_PROTOCOL_TYPE_STRING[config_protocol_type]);

2
openfpga/src/fpga_verilog/verilog_simulation_info_writer.h
View File

@ -9,6 +9,7 @@
#include "config_protocol.h"
#include "vpr_context.h"
#include "io_location_map.h"
#include "verilog_testbench_options.h"
/********************************************************************
* Function declaration
@ -18,6 +19,7 @@
namespace openfpga {
void print_verilog_simulation_info(const std::string& ini_fname,
const VerilogTestbenchOption& options,
const std::string& circuit_name,
const std::string& src_dir,
const AtomContext& atom_ctx,