From bcb86801faf0ac0022b0d5fa7dbf564217d8defa Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 5 Apr 2020 17:26:44 -0600 Subject: [PATCH] bug fixed in gpio naming for module manager ports --- openfpga/src/base/openfpga_naming.cpp | 5 +- openfpga/src/base/openfpga_naming.h | 3 +- openfpga/src/fabric/build_grid_modules.cpp | 68 ++++++++++++++++--- openfpga/src/utils/module_manager_utils.cpp | 2 +- .../k6_frac_N10_spyio_40nm_openfpga.xml | 2 +- 5 files changed, 65 insertions(+), 15 deletions(-) diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp index 530db8cc6..99d59afdb 100644 --- a/openfpga/src/base/openfpga_naming.cpp +++ b/openfpga/src/base/openfpga_naming.cpp @@ -1339,10 +1339,13 @@ std::string generate_pb_type_port_name(t_port* pb_type_port) { ********************************************************************/ std::string generate_fpga_global_io_port_name(const std::string& prefix, const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model) { + const CircuitModelId& circuit_model, + const CircuitPortId& circuit_port) { std::string port_name(prefix); port_name += circuit_lib.model_name(circuit_model); + port_name += std::string("_"); + port_name += circuit_lib.port_prefix(circuit_port); return port_name; } diff --git a/openfpga/src/base/openfpga_naming.h b/openfpga/src/base/openfpga_naming.h index e4f1ee8f8..40d7f05e9 100644 --- a/openfpga/src/base/openfpga_naming.h +++ b/openfpga/src/base/openfpga_naming.h @@ -242,7 +242,8 @@ std::string generate_pb_type_port_name(t_port* pb_type_port); std::string generate_fpga_global_io_port_name(const std::string& prefix, const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model); + const CircuitModelId& circuit_model, + const CircuitPortId& circuit_port); std::string generate_fpga_top_module_name(); diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp index e55640834..741632d1c 100644 --- a/openfpga/src/fabric/build_grid_modules.cpp +++ b/openfpga/src/fabric/build_grid_modules.cpp @@ -144,6 +144,38 @@ void add_grid_module_nets_connect_pb_type_ports(ModuleManager& module_manager, } } +/******************************************************************** + *******************************************************************/ +static +void add_primitive_module_fpga_global_io_port(ModuleManager& module_manager, + const ModuleId& primitive_module, + const ModuleId& logic_module, + const size_t& logic_instance_id, + const ModuleManager::e_module_port_type& module_io_port_type, + const CircuitLibrary& circuit_lib, + const CircuitModelId& primitive_model, + const CircuitPortId& circuit_port) { + BasicPort module_port(generate_fpga_global_io_port_name(std::string(GIO_INOUT_PREFIX), circuit_lib, primitive_model, circuit_port), circuit_lib.port_size(circuit_port)); + ModulePortId primitive_io_port_id = module_manager.add_port(primitive_module, module_port, module_io_port_type); + ModulePortId logic_io_port_id = module_manager.find_module_port(logic_module, circuit_lib.port_prefix(circuit_port)); + BasicPort logic_io_port = module_manager.module_port(logic_module, logic_io_port_id); + VTR_ASSERT(logic_io_port.get_width() == module_port.get_width()); + + /* Wire the GPIO port form primitive_module to the logic module!*/ + for (size_t pin_id = 0; pin_id < module_port.pins().size(); ++pin_id) { + ModuleNetId net = module_manager.create_module_net(primitive_module); + if ( (ModuleManager::MODULE_GPIO_PORT == module_io_port_type) + || (ModuleManager::MODULE_GPIN_PORT == module_io_port_type) ) { + module_manager.add_module_net_source(primitive_module, net, primitive_module, 0, primitive_io_port_id, module_port.pins()[pin_id]); + module_manager.add_module_net_sink(primitive_module, net, logic_module, logic_instance_id, logic_io_port_id, logic_io_port.pins()[pin_id]); + } else { + VTR_ASSERT(ModuleManager::MODULE_GPOUT_PORT == module_io_port_type); + module_manager.add_module_net_source(primitive_module, net, logic_module, logic_instance_id, logic_io_port_id, logic_io_port.pins()[pin_id]); + module_manager.add_module_net_sink(primitive_module, net, primitive_module, 0, primitive_io_port_id, module_port.pins()[pin_id]); + } + } +} + /******************************************************************** * Print Verilog modules of a primitive node in the pb_graph_node graph * This generic function can support all the different types of primitive nodes @@ -275,18 +307,32 @@ void build_primitive_block_module(ModuleManager& module_manager, if (CIRCUIT_MODEL_IOPAD == circuit_lib.model_type(primitive_model)) { std::vector primitive_model_inout_ports = circuit_lib.model_ports_by_type(primitive_model, CIRCUIT_MODEL_PORT_INOUT); for (auto port : primitive_model_inout_ports) { - BasicPort module_port(generate_fpga_global_io_port_name(std::string(GIO_INOUT_PREFIX), circuit_lib, primitive_model), circuit_lib.port_size(port)); - ModulePortId primitive_gpio_port_id = module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_GPIO_PORT); - ModulePortId logic_gpio_port_id = module_manager.find_module_port(logic_module, circuit_lib.port_prefix(port)); - BasicPort logic_gpio_port = module_manager.module_port(logic_module, logic_gpio_port_id); - VTR_ASSERT(logic_gpio_port.get_width() == module_port.get_width()); + add_primitive_module_fpga_global_io_port(module_manager, primitive_module, + logic_module, logic_instance_id, + ModuleManager::MODULE_GPIO_PORT, + circuit_lib, + primitive_model, + port); + } + } - /* Wire the GPIO port form primitive_module to the logic module!*/ - for (size_t pin_id = 0; pin_id < module_port.pins().size(); ++pin_id) { - ModuleNetId net = module_manager.create_module_net(primitive_module); - module_manager.add_module_net_source(primitive_module, net, primitive_module, 0, primitive_gpio_port_id, module_port.pins()[pin_id]); - module_manager.add_module_net_sink(primitive_module, net, logic_module, logic_instance_id, logic_gpio_port_id, logic_gpio_port.pins()[pin_id]); - } + /* Find the other i/o ports required by the primitive node, and add them to the module */ + for (const auto& port : circuit_lib.model_global_ports(primitive_model, false)) { + if ( (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(port)) + && (true == circuit_lib.port_is_io(port)) ) { + add_primitive_module_fpga_global_io_port(module_manager, primitive_module, + logic_module, logic_instance_id, + ModuleManager::MODULE_GPIN_PORT, + circuit_lib, + primitive_model, + port); + } else if (CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib.port_type(port)) { + add_primitive_module_fpga_global_io_port(module_manager, primitive_module, + logic_module, logic_instance_id, + ModuleManager::MODULE_GPOUT_PORT, + circuit_lib, + primitive_model, + port); } } diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp index 3c1ef2de2..64bef2e88 100644 --- a/openfpga/src/utils/module_manager_utils.cpp +++ b/openfpga/src/utils/module_manager_utils.cpp @@ -48,7 +48,7 @@ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, } else if (CIRCUIT_MODEL_PORT_CLOCK == circuit_lib.port_type(port)) { module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT); } else if ( (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(port)) - && (false == circuit_lib.port_is_io(port)) ) { + && (true == circuit_lib.port_is_io(port)) ) { module_manager.add_port(module, port_info, ModuleManager::MODULE_GPIN_PORT); } else { VTR_ASSERT(CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib.port_type(port)); diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml index b8f5fc249..2b432ce86 100644 --- a/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml +++ b/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml @@ -181,7 +181,7 @@ - +