[core] code complete for rename modules

libs/libnamemanager/src/base/module_name_map.cpp

@@ -54,6 +54,11 @@ int ModuleNameMap::set_tag_to_name_pair(const std::string& tag, const std::strin
   name2tags_[name] = tag;
   tag2names_[tag] = name;
   return CMD_EXEC_SUCCESS;
+} 
+
+void ModuleNameMap::clear() {
+  tag2names_.clear();
+  name2tags_.clear();
 }
 
 } /* end namespace openfpga */

libs/libnamemanager/src/base/module_name_map.h

@@ -24,6 +24,8 @@ class ModuleNameMap {
  public: /* Public mutators */
   /** @brief Create the one-on-one mapping between an built-in name and a customized name. Return 0 for success, return 1 for fail */
   int set_tag_to_name_pair(const std::string& tag, const std::string& name);
+  /** @brief Reset to empty status. Clear all the storage */
+  void clear();
  private: /* Internal Data */
   /* built-in name -> customized_name
    * Create a double link to check any customized name is mapped to more than 1 built-in name!

openfpga/src/base/openfpga_build_fabric_template.h

@@ -22,6 +22,7 @@
 #include "read_xml_tile_config.h"
 #include "vtr_log.h"
 #include "vtr_time.h"
+#include "rename_modules.h"
 
 /* begin namespace openfpga */
 namespace openfpga {

openfpga/src/base/openfpga_naming.cpp

@@ -503,6 +503,15 @@ std::string generate_switch_block_module_name(
                      std::string("_"));
 }
 
+/*********************************************************************
+ * Generate the module name for a switch block with a given index
+ *********************************************************************/
+std::string generate_switch_block_module_name_using_index(
+  const size_t& index) {
+  return std::string("sb_" + std::to_string(index) +
+                     std::string("_"));
+}
+
 /*********************************************************************
  * Generate the module name for a tile module with a given coordinate
  *********************************************************************/
@@ -511,6 +520,13 @@ std::string generate_tile_module_name(const vtr::Point<size_t>& tile_coord) {
                      std::to_string(tile_coord.y()) + "_");
 }
 
+/*********************************************************************
+ * Generate the module name for a tile module with a given index
+ *********************************************************************/
+std::string generate_tile_module_name_using_index(const size_t& index) {
+  return std::string("tile_" + std::to_string(index) + "_");
+}
+
 /*********************************************************************
  * Generate the port name for a tile. Note that use the index to make the tile
  *port name unique!
@@ -560,6 +576,28 @@ std::string generate_connection_block_module_name(
                      std::string("_"));
 }
 
+/*********************************************************************
+ * Generate the module name for a connection block with a given index
+ *********************************************************************/
+std::string generate_connection_block_module_name_using_index(
+  const t_rr_type& cb_type, const size_t& index) {
+  std::string prefix("cb");
+  switch (cb_type) {
+    case CHANX:
+      prefix += std::string("x_");
+      break;
+    case CHANY:
+      prefix += std::string("y_");
+      break;
+    default:
+      VTR_LOG_ERROR("Invalid type of connection block!\n");
+      exit(1);
+  }
+
+  return std::string(prefix + std::to_string(index) +
+                     std::string("_"));
+}
+
 /*********************************************************************
  * Generate the port name for a grid in top-level netlists, i.e., full FPGA
  *fabric This function will generate a full port name including coordinates so

openfpga/src/base/openfpga_naming.h

@@ -108,11 +108,19 @@ std::string generate_routing_track_middle_output_port_name(
 std::string generate_switch_block_module_name(
   const vtr::Point<size_t>& coordinate);
 
+std::string generate_switch_block_module_name_using_index(
+  const size_t& index);
+
 std::string generate_connection_block_module_name(
   const t_rr_type& cb_type, const vtr::Point<size_t>& coordinate);
 
+std::string generate_connection_block_module_name_using_index(
+  const t_rr_type& cb_type, const size_t& index);
+
 std::string generate_tile_module_name(const vtr::Point<size_t>& tile_coord);
 
+std::string generate_tile_module_name_using_index(const size_t& index);
+
 std::string generate_tile_module_port_name(const std::string& prefix,
                                            const std::string& port_name);
 

openfpga/src/fabric/build_device_module.cpp

@@ -23,6 +23,7 @@
 #include "build_wire_modules.h"
 #include "command_exit_codes.h"
 #include "openfpga_naming.h"
+#include "rename_modules.h"
 
 /* begin namespace openfpga */
 namespace openfpga {
@@ -155,13 +156,13 @@ int build_device_module_graph(
                                      openfpga_ctx.arch().circuit_lib);
 
   /* Collect module names and initialize module name mapping */
-  status = init_fabric_module_map_name(module_manager, module_name_map);
+  status = init_fabric_module_name_map(module_name_map, module_manager, verbose);
   if (CMD_EXEC_FATAL_ERROR == status) {
     return status;
   }
   if (name_module_using_index) {
     /* Update module name data */
-    status = update_module_map_name_with_indexing_names(module_name_map, device_rr_gsb, fabric_tile);
+    status = update_module_map_name_with_indexing_names(module_name_map, device_rr_gsb, fabric_tile, verbose);
     if (CMD_EXEC_FATAL_ERROR == status) {
       return status;
     }

openfpga/src/fabric/rename_modules.cpp

@@ -0,0 +1,93 @@
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+#include "vtr_time.h"
+
+#include "command_exit_codes.h"
+#include "openfpga_naming.h"
+#include "rename_modules.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/** @brief Initialize a module name map with the existing module names from a module manager. In this case, all the built-in names are the same as customized names */
+int init_fabric_module_name_map(
+  ModuleNameMap& module_name_map,
+  const ModuleManager& module_manager, 
+  const bool& verbose) {
+  int status = CMD_EXEC_SUCCESS;
+  /* the module name map should be empty! */
+  module_name_map.clear();
+  size_t cnt = 0;
+  for (ModuleId curr_module : module_manager.modules()) {
+    status = module_name_map.set_tag_to_name_pair(module_manager.module_name(curr_module), module_manager.module_name(curr_module));
+    if (status != CMD_EXEC_SUCCESS) {
+      return CMD_EXEC_SUCCESS;
+    }
+    cnt++;
+  }
+  VTR_LOGV(verbose, "Initialized module name map for '%lu' modules\n", cnt);
+  return CMD_EXEC_SUCCESS;
+}
+
+int update_module_map_name_with_indexing_names(ModuleNameMap& module_name_map, const DeviceRRGSB& device_rr_gsb, const FabricTile& fabric_tile, const bool& verbose) {
+  int status = CMD_EXEC_SUCCESS;
+  /* Walk through the device rr gsb on the unique routing modules */
+  for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
+    const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb);
+    vtr::Point<size_t> gsb_coordinate(unique_mirror.get_sb_x(), unique_mirror.get_sb_y());
+    std::string name_using_coord = generate_switch_block_module_name(gsb_coordinate);
+    std::string name_using_index = generate_switch_block_module_name_using_index(isb);
+    status = module_name_map.set_tag_to_name_pair(name_using_coord, name_using_index);
+    if (status != CMD_EXEC_SUCCESS) {
+      return CMD_EXEC_SUCCESS;
+    }
+    VTR_LOGV(verbose, "Now use indexing name for module '%s' (was '%s')\n", name_using_index.c_str(), name_using_coord.c_str());
+  }
+  for (t_rr_type cb_type : {CHANX, CHANY}) {
+    for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(cb_type);
+         ++icb) {
+      const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, icb);
+      vtr::Point<size_t> gsb_coordinate(unique_mirror.get_cb_x(cb_type),
+                                        unique_mirror.get_cb_y(cb_type));
+      std::string name_using_coord = generate_connection_block_module_name(cb_type, gsb_coordinate);
+      std::string name_using_index = generate_connection_block_module_name_using_index(cb_type, icb);
+      status = module_name_map.set_tag_to_name_pair(name_using_coord, name_using_index);
+      if (status != CMD_EXEC_SUCCESS) {
+        return CMD_EXEC_SUCCESS;
+      }
+      VTR_LOGV(verbose, "Now use indexing name for module '%s' (was '%s')\n", name_using_index.c_str(), name_using_coord.c_str());
+    }
+  }
+  /* Walk through the fabric tile on the unique routing modules */
+  for (size_t itile = 0; itile < fabric_tile.unique_tiles().size(); ++itile) {
+    FabricTileId fabric_tile_id = fabric_tile.unique_tiles()[itile];
+    vtr::Point<size_t> tile_coord = fabric_tile.tile_coordinate(fabric_tile_id);
+    std::string name_using_coord = generate_tile_module_name(tile_coord);
+    std::string name_using_index = generate_tile_module_name_using_index(tile_coord, itile);
+    status = module_name_map.set_tag_to_name_pair(name_using_coord, name_using_index);
+    if (status != CMD_EXEC_SUCCESS) {
+      return CMD_EXEC_SUCCESS;
+    }
+    VTR_LOGV(verbose, "Now use indexing name for module '%s' (was '%s')\n", name_using_index.c_str(), name_using_coord.c_str());
+  }
+  return CMD_EXEC_SUCCESS;
+}
+
+int rename_fabric_modules(ModuleManager& module_manager, const ModuleNameMap& module_name_map, const bool& verbose) {
+  int status = CMD_EXEC_SUCCESS;
+  size_t cnt = 0;
+  for (ModuleId curr_module : module_manager.modules()) {
+    std::string new_name = module_name_map.name(module_manager.module_name(curr_module));
+    if (new_name != module_manager.module_name()) {
+      VTR_LOGV(verbose, "Rename module '%s' to its new name '%s'\n", module_manager.module_name(curr_module).c_str(), new_name.c_str());
+      module_manager.set_module_name(curr_module, new_name);
+    }
+    cnt++;
+  }
+  VTR_LOG("Renamed %lu modules\n", cnt);
+  return status;
+} 
+
+
+} /* end namespace openfpga */

openfpga/src/fabric/rename_modules.h

@@ -0,0 +1,30 @@
+#ifndef RENAME_MODULES_H
+#define RENAME_MODULES_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "fabric_tile.h"
+#include "device_rr_gsb.h"
+#include "module_name_map.h"
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+int init_fabric_module_name_map(
+  ModuleNameMap& module_name_map,
+  const ModuleManager& module_manager,
+  const bool& verbose);
+
+int update_module_map_name_with_indexing_names(ModuleNameMap& module_name_map, const DeviceRRGSB& device_rr_gsb, const FabricTile& fabric_tile, const bool& verbose);
+
+int rename_fabric_modules(ModuleManager& module_manager, const ModuleNameMap& module_name_map, const bool& verbose); 
+
+} /* end namespace openfpga */
+
+#endif