diff --git a/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf
index 02e08dff4..7004582ed 100644
--- a/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf
+++ b/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf
@@ -12,7 +12,7 @@ power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
 power_analysis = false
 spice_output=false
 verilog_output=true
-timeout_each_job = 20*60
+timeout_each_job = 2*60
 # Due to the limitation in ACE2 which cannot output .blif files 
 # with correct multi-clock assignments to .latch lines
 # We have to use the vpr_blif flow where the .blif is modified
diff --git a/openfpga_flow/tasks/quicklogic_tests/sdc_controller_test/config/pin_constraints.xml b/openfpga_flow/tasks/quicklogic_tests/sdc_controller_test/config/pin_constraints.xml
new file mode 100644
index 000000000..8206e8ee5
--- /dev/null
+++ b/openfpga_flow/tasks/quicklogic_tests/sdc_controller_test/config/pin_constraints.xml
@@ -0,0 +1,9 @@
+<pin_constraints>
+  <!-- For a given .blif file, we want to assign 
+       - the clk0 signal to the clk[0] port of the FPGA fabric
+       - the clk1 signal to the clk[1] port of the FPGA fabric
+    -->
+  <set_io pin="clk[0]" net="wb_clk_i"/>
+  <set_io pin="clk[1]" net="sd_clk_i_pad"/>
+</pin_constraints>
+
diff --git a/openfpga_flow/tasks/quicklogic_tests/sdc_controller_test/config/repack_pin_constraints.xml b/openfpga_flow/tasks/quicklogic_tests/sdc_controller_test/config/repack_pin_constraints.xml
new file mode 100644
index 000000000..2e1bcb7c2
--- /dev/null
+++ b/openfpga_flow/tasks/quicklogic_tests/sdc_controller_test/config/repack_pin_constraints.xml
@@ -0,0 +1,18 @@
+<repack_design_constraints>
+  <!-- For a given .blif file, we want to assign 
+       - the clk0 signal to the clk[0] port of all the clb tiles available in the FPGA fabric
+       - the clk1 signal to the clk[1] port of all the clb tiles available in the FPGA fabric
+       and ensure no signals could be mapped to 
+       - the clk[2] port of all the clb tiles available in the FPGA fabric
+       - the clk[3] port of all the clb tiles available in the FPGA fabric
+    -->
+  <pin_constraint pb_type="clb" pin="clk[0]" net="wb_clk_i"/>
+  <pin_constraint pb_type="clb" pin="clk[1]" net="sd_clk_i_pad"/>
+  <pin_constraint pb_type="clb" pin="clk[2]" net="OPEN"/>
+  <pin_constraint pb_type="clb" pin="clk[3]" net="OPEN"/>
+  <pin_constraint pb_type="clb" pin="clk[4]" net="OPEN"/>
+  <pin_constraint pb_type="clb" pin="clk[5]" net="OPEN"/>
+  <pin_constraint pb_type="clb" pin="clk[6]" net="OPEN"/>
+  <pin_constraint pb_type="clb" pin="clk[7]" net="OPEN"/>
+</repack_design_constraints>
+
diff --git a/openfpga_flow/tasks/quicklogic_tests/sdc_controller_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/sdc_controller_test/config/task.conf
new file mode 100644
index 000000000..9d8c4a7ff
--- /dev/null
+++ b/openfpga_flow/tasks/quicklogic_tests/sdc_controller_test/config/task.conf
@@ -0,0 +1,40 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 2*60
+# Due to the limitation in ACE2 which cannot output .blif files 
+# with correct multi-clock assignments to .latch lines
+# We have to use the vpr_blif flow where the .blif is modified
+# based on yosys outputs with correct clock assignment!
+# TODO: This limitation should be removed and we should use yosys_vpr flow!!!
+#fpga_flow=vpr_blif
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_global_tile_multiclock_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTile8Clk_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_8clock_sim_openfpga.xml
+openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/sdc_controller_test/config/repack_pin_constraints.xml
+openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/sdc_controller_test/config/pin_constraints.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile8Clk_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sdc_controller/rtl/*.v
+
+[SYNTHESIS_PARAM]
+bench0_top = sdc_controller
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]