diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml
index 90109d00b..66aa9b4b3 100644
--- a/openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml
@@ -173,8 +173,8 @@
     <segment name="L4" circuit_model_name="chan_segment"/>
   </routing_segment>
   <tile_annotations>
-    <global_port name="clk" is_clock="true" clock_arch_tree_name="clk_tree_2lvl" default_val="0">
-      <tile name="clb" port="clk[0:1]"/>
+    <global_port name="clk[0:1]" is_clock="true" clock_arch_tree_name="clk_tree_2lvl" default_val="0">
+      <tile name="clb" port="clk[0:0]"/>
     </global_port>
   </tile_annotations>
   <pb_type_annotations>
diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml
index 98e91d27a..ff5734d10 100644
--- a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml
@@ -11,8 +11,8 @@
     <spine name="rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
     <spine name="rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
     <taps>
-      <all from_pin="clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
-      <all from_pin="clk[1:1]" to_pin="clb[0:0].clk[1:1]"/>
+      <all from_pin="clk[0:0]" to_pin="clb[0:0].clk[0:1]"/>
+      <all from_pin="clk[1:1]" to_pin="clb[0:0].clk[0:1]"/>
     </taps>
   </clock_network>  
 </clock_networks> 
diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk2clk2lvl_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk2clk2lvl_40nm.xml
index f4e40b275..231aef08b 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk2clk2lvl_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk2clk2lvl_40nm.xml
@@ -59,7 +59,7 @@
         </equivalent_sites>
         <input name="I" num_pins="10" equivalent="full"/>
         <output name="O" num_pins="4" equivalent="none"/>
-        <clock name="clk" num_pins="2"/>
+        <clock name="clk" num_pins="1"/>
         <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
           <fc_override port_name="clk" fc_type="frac" fc_val="0"/>
         </fc>
@@ -250,7 +250,7 @@
     <pb_type name="clb">
       <input name="I" num_pins="10" equivalent="full"/>
       <output name="O" num_pins="4" equivalent="none"/>
-      <clock name="clk" num_pins="2"/>
+      <clock name="clk" num_pins="1"/>
       <!-- Describe basic logic element.  
              Each basic logic element has a 4-LUT that can be optionally registered
         -->