From bb2a02c9ad46cf2e3fa1b270a542dbd69cc22374 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 11 Mar 2021 15:23:14 -0700 Subject: [PATCH] [HDL] Patch the superLUT HDL code to be consistent with (qlf_k4n8_sim.v)[https://github.com/lnsharma/yosys/blob/add_qlf_k4n8_dev/techlibs/quicklogic/qlf_k4n8_cells_sim.v] --- openfpga_flow/openfpga_cell_library/verilog/frac_lut4_arith.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/openfpga_cell_library/verilog/frac_lut4_arith.v b/openfpga_flow/openfpga_cell_library/verilog/frac_lut4_arith.v index 0b5461615..d5410b5bf 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/frac_lut4_arith.v +++ b/openfpga_flow/openfpga_cell_library/verilog/frac_lut4_arith.v @@ -63,7 +63,7 @@ wire [0:0] sky130_fd_sc_hd__or2_1_0_X; .A(in[1]), .Y(sky130_fd_sc_hd__inv_1_1_Y[0])); - assign arith_in2 = mode[0] ? in[2] : cin; + assign arith_in2 = mode[0] ? cin : in[2]; sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A(arith_in2), @@ -82,7 +82,7 @@ wire [0:0] sky130_fd_sc_hd__or2_1_0_X; .X(sky130_fd_sc_hd__buf_2_1_X[0])); sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( - .A(in[2]), + .A(arith_in2), .X(sky130_fd_sc_hd__buf_2_2_X[0])); sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ (