start developing XML parser for pb_type annotation
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tangxifan
parent
b6f96e5a8f
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bafd866cfc
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@ -268,7 +268,7 @@
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<direct_connection>
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<direct name="adder" circuit_model_name="direct_interc"/>
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</direct_connection>
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<complex_blocks>
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<pb_type_annotations>
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<!-- physical pb_type binding in complex block IO -->
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<pb_type name="io" physical_mode_name="io_phy"/>
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<pb_type name="io[io_phy].iopad" circuit_model_name="iopad" mode_bits="1"/>
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@ -293,26 +293,26 @@
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<pb_type name="clb.fle[fle_phy].frac_logic.ff_phy" circuit_model_name="static_dff"/>
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<pb_type name="clb.fle[n2_lut5].lut5_inter.ble5[blut5].flut5.lut5" mode_bits="01" physical_pb_type_name="clb.fle[fle_phy].frac_logic.frac_lut6" physical_pb_type_index_factor="0.5">
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<!-- If not specified, we by default assume the physical mode pin share the same name -->
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<input name="in" physical_mode_pin="in[4:0]"/>
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<output name="out" physical_mode_pin="lut5_out" physical_mode_pin_rotate_offset="1"/>
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<port name="in" physical_mode_pin="in[4:0]"/>
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<port name="out" physical_mode_pin="lut5_out" physical_mode_pin_rotate_offset="1"/>
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</pb_type>
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<pb_type name="clb.fle[n2_lut5].lut5_inter.ble5[blut5].flut5.ff" physical_pb_type_name="clb.fle[fle_phy].frac_logic.ff_phy"/>
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<pb_type name="clb.fle[n2_lut5].lut5_inter.ble5[arithmetic].arithemetic.lut4" mode_bits="11" physical_pb_type_name="clb.fle[fle_phy].frac_logic.frac_lut6">
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<!-- If not specified, we by default assume the physical mode pin share the same name -->
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<input name="in" physical_mode_pin="in[3:0]"/>
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<output name="out" physical_mode_pin="lut4_out" physical_mode_pin_rotate_offset="1"/>
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<port name="in" physical_mode_pin="in[3:0]"/>
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<port name="out" physical_mode_pin="lut4_out" physical_mode_pin_rotate_offset="1"/>
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</pb_type>
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<pb_type name="clb.fle[n2_lut5].lut5_inter.ble5[arithmetic].arithemetic.adder" physical_pb_type_name="clb.fle[fle_phy].frac_logic.adder_phy"/>
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<pb_type name="clb.fle[n2_lut5].lut5_inter.ble5[arithmetic].arithemetic.ff" physical_pb_type_name="clb.fle[fle_phy].frac_logic.ff_phy"/>
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<pb_type name="clb.fle[n1_lut6].ble6.lut6" mode_bits="00" physical_pb_type_name="clb.fle[fle_phy].frac_logic.frac_lut6">
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<!-- If not specified, we by default assume the physical mode pin share the same name -->
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<input name="in" physical_mode_pin="in[5:0]"/>
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<output name="out" physical_mode_pin="lut6_out"/>
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<port name="in" physical_mode_pin="in[5:0]"/>
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<port name="out" physical_mode_pin="lut6_out"/>
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</pb_type>
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<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[fle_phy].frac_logic.ff_phy" physical_pb_type_index_factor="2" physical_pb_type_index_offset="1"/>
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<pb_type name="clb.fle[shift_register].ble6_shift.ff" physical_pb_type_name="clb.fle[fle_phy].frac_logic.ff_phy"/>
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<!-- End physical pb_type binding in complex block IO -->
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</complex_blocks>
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</pb_type_annotations>
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</openfpga_architecture>
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<openfpga_simulation_setting>
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<clock_setting>
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@ -1,12 +1,14 @@
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#ifndef OPENFPGA_ARCH_H
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#define OPENFPGA_ARCH_H
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#include <vector>
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#include <map>
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#include "circuit_library.h"
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#include "technology_library.h"
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#include "simulation_setting.h"
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#include "config_protocol.h"
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#include "pb_type_annotation.h"
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/* namespace openfpga begins */
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namespace openfpga {
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@ -47,6 +49,12 @@ struct Arch {
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* to circuit models in circuit library
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*/
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std::map<std::string, CircuitModelId> direct2circuit;
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/* Pb type annotations
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* Bind from operating to physical
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* Bind from physical to circuit model
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*/
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std::vector<PbTypeAnnotation> pb_type_annotations;
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};
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} /* namespace openfpga ends */
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@ -21,6 +21,7 @@
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#include "read_xml_simulation_setting.h"
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#include "read_xml_config_protocol.h"
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#include "read_xml_routing_circuit.h"
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#include "read_xml_pb_type_annotation.h"
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#include "read_xml_openfpga_arch.h"
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#include "openfpga_arch_linker.h"
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@ -85,10 +86,13 @@ openfpga::Arch read_xml_openfpga_arch(const char* arch_file_name) {
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openfpga_arch.routing_seg2circuit = read_xml_routing_segment_circuit(xml_openfpga_arch, loc_data,
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openfpga_arch.circuit_lib);
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/* Parse the routing segment circuit definition */
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/* Parse the direct circuit definition */
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openfpga_arch.direct2circuit = read_xml_direct_circuit(xml_openfpga_arch, loc_data,
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openfpga_arch.circuit_lib);
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/* Parse the pb_type annotation */
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openfpga_arch.pb_type_annotations = read_xml_pb_type_annotations(xml_openfpga_arch, loc_data);
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/* Second node should be <openfpga_simulation_setting> */
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auto xml_simulation_settings = get_single_child(doc, "openfpga_simulation_setting", loc_data);
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@ -0,0 +1,74 @@
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/********************************************************************
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* This file includes the top-level function of this library
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* which reads an XML modeling OpenFPGA architecture to the associated
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* data structures
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*******************************************************************/
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#include <string>
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/* Headers from pugi XML library */
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#include "pugixml.hpp"
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#include "pugixml_util.hpp"
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/* Headers from vtr util library */
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#include "vtr_assert.h"
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/* Headers from libarchfpga */
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#include "arch_error.h"
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#include "read_xml_util.h"
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#include "read_xml_pb_type_annotation.h"
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/********************************************************************
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* Parse XML description for a pb_type annotation under a <pb_type> XML node
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*******************************************************************/
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static
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void read_xml_pb_type_annotation(pugi::xml_node& xml_pb_type,
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const pugiutil::loc_data& loc_data,
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std::vector<openfpga::PbTypeAnnotation>& pb_type_annotations) {
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openfpga::PbTypeAnnotation pb_type_annotation;
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/* Find the name of pb_type */
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const std::string& name_attr = get_attribute(xml_pb_type, "name", loc_data).as_string();
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const std::string& physical_name_attr = get_attribute(xml_pb_type, "physical_pb_type_name", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string();
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/* If both names are not empty, this is a operating pb_type */
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if ( (false == name_attr.empty())
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&& (false == physical_name_attr.empty()) ) {
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/* Parse the attributes for operating pb_type */
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pb_type_annotation.set_operating_pb_type_name(name_attr);
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pb_type_annotation.set_physical_pb_type_name(physical_name_attr);
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}
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/* If there is only a name, this is a physical pb_type */
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if ( (false == name_attr.empty())
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&& (true == physical_name_attr.empty()) ) {
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pb_type_annotation.set_physical_pb_type_name(name_attr);
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}
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/* Finish parsing and add it to the vector */
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pb_type_annotations.push_back(pb_type_annotation);
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}
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/********************************************************************
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* Top function to parse XML description about pb_type annotation
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*******************************************************************/
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std::vector<openfpga::PbTypeAnnotation> read_xml_pb_type_annotations(pugi::xml_node& Node,
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const pugiutil::loc_data& loc_data) {
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std::vector<openfpga::PbTypeAnnotation> pb_type_annotations;
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/* Parse configuration protocol root node */
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pugi::xml_node xml_annotations = get_single_child(Node, "pb_type_annotations", loc_data);
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/* Iterate over the children under this node,
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* each child should be named after <pb_type>
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*/
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for (pugi::xml_node xml_pb_type : xml_annotations.children()) {
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/* Error out if the XML child has an invalid name! */
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if (xml_pb_type.name() != std::string("pb_type")) {
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bad_tag(xml_pb_type, loc_data, xml_annotations, {"pb_type"});
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}
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read_xml_pb_type_annotation(xml_pb_type, loc_data, pb_type_annotations);
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}
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return pb_type_annotations;
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}
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@ -0,0 +1,17 @@
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#ifndef READ_XML_PB_TYPE_ANNOTATION_H
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#define READ_XML_PB_TYPE_ANNOTATION_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include "pugixml_util.hpp"
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#include "pugixml.hpp"
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#include "pb_type_annotation.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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std::vector<openfpga::PbTypeAnnotation> read_xml_pb_type_annotations(pugi::xml_node& Node,
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const pugiutil::loc_data& loc_data);
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#endif
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