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[core] code format

This commit is contained in:
tangxifan 2023-12-08 13:41:41 -08:00
parent 5e181cbe72
commit bacd845139
4 changed files with 38 additions and 27 deletions
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3
openfpga/src/base/openfpga_verilog_template.h
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@ -135,8 +135,7 @@ int write_full_testbench_template(const T& openfpga_ctx, const Command& cmd,
/* Configure the simulator */ /* Configure the simulator */
if (true == cmd_context.option_enable(cmd, opt_sim)) { if (true == cmd_context.option_enable(cmd, opt_sim)) {
options.set_simulator_type( options.set_simulator_type(cmd_context.option_value(cmd, opt_sim));
cmd_context.option_value(cmd, opt_sim));
} }
return fpga_verilog_full_testbench( return fpga_verilog_full_testbench(

24
openfpga/src/fpga_verilog/verilog_testbench_options.cpp
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@ -110,7 +110,10 @@ bool VerilogTestbenchOption::use_relative_path() const {
bool VerilogTestbenchOption::verbose_output() const { return verbose_output_; } bool VerilogTestbenchOption::verbose_output() const { return verbose_output_; }
VerilogTestbenchOption::e_simulator_type VerilogTestbenchOption::simulator_type() const { return simulator_type_; } VerilogTestbenchOption::e_simulator_type
VerilogTestbenchOption::simulator_type() const {
return simulator_type_;
}
/****************************************************************************** /******************************************************************************
* Private Mutators * Private Mutators
@ -265,14 +268,15 @@ void VerilogTestbenchOption::set_verbose_output(const bool& enabled) {
} }
int VerilogTestbenchOption::set_simulator_type(const std::string& value) { int VerilogTestbenchOption::set_simulator_type(const std::string& value) {
simulator_type_ = str2simulator_type(value); simulator_type_ = str2simulator_type(value);
return valid_simulator_type(simulator_type_); return valid_simulator_type(simulator_type_);
} }
std::string VerilogTestbenchOption::simulator_type_all2str() const { std::string VerilogTestbenchOption::simulator_type_all2str() const {
std::string full_types = "["; std::string full_types = "[";
for (int itype = size_t(VerilogTestbenchOption::e_simulator_type::IVERILOG); for (int itype = size_t(VerilogTestbenchOption::e_simulator_type::IVERILOG);
itype != size_t(VerilogTestbenchOption::e_simulator_type::NUM_TYPES); ++itype) { itype != size_t(VerilogTestbenchOption::e_simulator_type::NUM_TYPES);
++itype) {
full_types += std::string(SIMULATOR_TYPE_STRING_[itype]) + std::string("|"); full_types += std::string(SIMULATOR_TYPE_STRING_[itype]) + std::string("|");
} }
full_types.pop_back(); full_types.pop_back();
@ -280,9 +284,12 @@ std::string VerilogTestbenchOption::simulator_type_all2str() const {
return full_types; return full_types;
} }
VerilogTestbenchOption::e_simulator_type VerilogTestbenchOption::str2simulator_type(const std::string& type_str, const bool& verbose) const { VerilogTestbenchOption::e_simulator_type
VerilogTestbenchOption::str2simulator_type(const std::string& type_str,
const bool& verbose) const {
for (int itype = size_t(VerilogTestbenchOption::e_simulator_type::IVERILOG); for (int itype = size_t(VerilogTestbenchOption::e_simulator_type::IVERILOG);
itype != size_t(VerilogTestbenchOption::e_simulator_type::NUM_TYPES); ++itype) { itype != size_t(VerilogTestbenchOption::e_simulator_type::NUM_TYPES);
++itype) {
if (type_str == std::string(SIMULATOR_TYPE_STRING_[itype])) { if (type_str == std::string(SIMULATOR_TYPE_STRING_[itype])) {
return static_cast<VerilogTestbenchOption::e_simulator_type>(itype); return static_cast<VerilogTestbenchOption::e_simulator_type>(itype);
} }
@ -292,7 +299,9 @@ VerilogTestbenchOption::e_simulator_type VerilogTestbenchOption::str2simulator_t
return VerilogTestbenchOption::e_simulator_type::NUM_TYPES; return VerilogTestbenchOption::e_simulator_type::NUM_TYPES;
} }
std::string VerilogTestbenchOption::simulator_type2str(const VerilogTestbenchOption::e_simulator_type& sim_type, const bool& verbose) const { std::string VerilogTestbenchOption::simulator_type2str(
const VerilogTestbenchOption::e_simulator_type& sim_type,
const bool& verbose) const {
if (!valid_simulator_type(sim_type)) { if (!valid_simulator_type(sim_type)) {
VTR_LOGV_ERROR(verbose, "Invalid type for simulator! Expect %s\n", VTR_LOGV_ERROR(verbose, "Invalid type for simulator! Expect %s\n",
simulator_type_all2str().c_str()); simulator_type_all2str().c_str());
@ -301,7 +310,8 @@ std::string VerilogTestbenchOption::simulator_type2str(const VerilogTestbenchOpt
return std::string(SIMULATOR_TYPE_STRING_[size_t(sim_type)]); return std::string(SIMULATOR_TYPE_STRING_[size_t(sim_type)]);
} }
bool VerilogTestbenchOption::valid_simulator_type(const VerilogTestbenchOption::e_simulator_type& sim_type) const { bool VerilogTestbenchOption::valid_simulator_type(
const VerilogTestbenchOption::e_simulator_type& sim_type) const {
return sim_type != VerilogTestbenchOption::e_simulator_type::NUM_TYPES; return sim_type != VerilogTestbenchOption::e_simulator_type::NUM_TYPES;
} }

29
openfpga/src/fpga_verilog/verilog_testbench_options.h
View File

@ -32,18 +32,15 @@ constexpr std::array<const char*, NUM_EMBEDDED_BITSTREAM_HDL_TYPES + 1>
*******************************************************************/ *******************************************************************/
class VerilogTestbenchOption { class VerilogTestbenchOption {
/* Public types */ /* Public types */
public: public:
/* Embedded bitstream code style */ /* Embedded bitstream code style */
enum class e_simulator_type { enum class e_simulator_type { IVERILOG = 0, VCS, NUM_TYPES };
IVERILOG = 0,
VCS,
NUM_TYPES
};
/* Constants */ /* Constants */
private: private:
/* String version of simulator types. Used for debugging/error messages */ /* String version of simulator types. Used for debugging/error messages */
std::array<const char*, size_t(e_simulator_type::NUM_TYPES)> std::array<const char*, size_t(e_simulator_type::NUM_TYPES)>
SIMULATOR_TYPE_STRING_; SIMULATOR_TYPE_STRING_;
public: /* Public constructor */ public: /* Public constructor */
/* Set default options */ /* Set default options */
VerilogTestbenchOption(); VerilogTestbenchOption();
@ -109,12 +106,15 @@ class VerilogTestbenchOption {
void set_use_relative_path(const bool& enabled); void set_use_relative_path(const bool& enabled);
void set_verbose_output(const bool& enabled); void set_verbose_output(const bool& enabled);
/* @brief Create the simulator type by parsing a given string. Return error when failed */ /* @brief Create the simulator type by parsing a given string. Return error
* when failed */
int set_simulator_type(const std::string& value); int set_simulator_type(const std::string& value);
private: /* Private utility and validators */ private: /* Private utility and validators */
e_simulator_type str2simulator_type(const std::string& value, const bool& verbose = false) const; e_simulator_type str2simulator_type(const std::string& value,
std::string simulator_type2str(const e_simulator_type& sim_type, const bool& verbose = false) const; const bool& verbose = false) const;
std::string simulator_type2str(const e_simulator_type& sim_type,
const bool& verbose = false) const;
std::string simulator_type_all2str() const; std::string simulator_type_all2str() const;
bool valid_simulator_type(const e_simulator_type& sim_type) const; bool valid_simulator_type(const e_simulator_type& sim_type) const;
@ -139,7 +139,6 @@ class VerilogTestbenchOption {
bool time_stamp_; bool time_stamp_;
bool use_relative_path_; bool use_relative_path_;
bool verbose_output_; bool verbose_output_;
}; };
} /* End namespace openfpga*/ } /* End namespace openfpga*/

9
openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp
View File

@ -346,7 +346,8 @@ print_verilog_full_testbench_ql_memory_bank_shift_register_virtual_clock_generat
fp << "end"; fp << "end";
fp << std::endl; fp << std::endl;
// The following code does not work when using Synopsys VCS. Comment them out. See if iverilog is fine or not // The following code does not work when using Synopsys VCS. Comment them out.
// See if iverilog is fine or not
if (sim_type == VerilogTestbenchOption::e_simulator_type::IVERILOG) { if (sim_type == VerilogTestbenchOption::e_simulator_type::IVERILOG) {
fp << "\t"; fp << "\t";
fp << generate_verilog_port_constant_values( fp << generate_verilog_port_constant_values(
@ -536,7 +537,8 @@ int print_verilog_top_testbench_configuration_protocol_ql_memory_bank_stimulus(
print_verilog_comment( print_verilog_comment(
fp, "----- BL Shift register virtual clock generator -----"); fp, "----- BL Shift register virtual clock generator -----");
print_verilog_full_testbench_ql_memory_bank_shift_register_virtual_clock_generator( print_verilog_full_testbench_ql_memory_bank_shift_register_virtual_clock_generator(
fp, start_bl_sr_port, virtual_bl_sr_clock_port, bl_sr_clock_period, sim_type); fp, start_bl_sr_port, virtual_bl_sr_clock_port, bl_sr_clock_period,
sim_type);
print_verilog_comment(fp, print_verilog_comment(fp,
"----- BL Shift register clock generator -----"); "----- BL Shift register clock generator -----");
@ -548,7 +550,8 @@ int print_verilog_top_testbench_configuration_protocol_ql_memory_bank_stimulus(
print_verilog_comment( print_verilog_comment(
fp, "----- WL Shift register virtual clock generator -----"); fp, "----- WL Shift register virtual clock generator -----");
print_verilog_full_testbench_ql_memory_bank_shift_register_virtual_clock_generator( print_verilog_full_testbench_ql_memory_bank_shift_register_virtual_clock_generator(
fp, start_wl_sr_port, virtual_wl_sr_clock_port, wl_sr_clock_period, sim_type); fp, start_wl_sr_port, virtual_wl_sr_clock_port, wl_sr_clock_period,
sim_type);
print_verilog_comment(fp, print_verilog_comment(fp,
"----- WL Shift register clock generator -----"); "----- WL Shift register clock generator -----");
print_verilog_full_testbench_ql_memory_bank_shift_register_clock_generator( print_verilog_full_testbench_ql_memory_bank_shift_register_clock_generator(