diff --git a/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga
index d331b4283..ccd7e2efe 100644
--- a/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga
@@ -1,5 +1,5 @@
 # Convert .pcf to a .place file that VPR can accept
-pcf2place --pcf ${OPENFPGA_PCF} --blif ${VPR_TESTBENCH_BLIF} --pin_table ${OPENFPGA_PIN_TABLE} --fpga_io_map ${OPENFPGA_IO_MAP_FILE} --fpga_fix_pins ${OPENFPGA_VPR_FIX_PINS_FILE} --skip_sync_clustering_and_routing_results on
+pcf2place --pcf ${OPENFPGA_PCF} --blif ${VPR_TESTBENCH_BLIF} --pin_table ${OPENFPGA_PIN_TABLE} --fpga_io_map ${OPENFPGA_IO_MAP_FILE} --fpga_fix_clusters ${OPENFPGA_VPR_FIX_PINS_FILE} --skip_sync_clustering_and_routing_results on
 
 # Run VPR for the 'and' design
 #--write_rr_graph example_rr_graph.xml