From fc523bed32986e06d17d81421e9c87e5e0685df3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Aug 2023 21:04:37 -0700 Subject: [PATCH 1/7] [core] fixed some bugs in spotting the correct pin index of given subtiles --- .../build_top_module_child_tile_instance.cpp | 5 ++- openfpga/src/utils/check_tile_annotation.cpp | 45 +++++++++---------- 2 files changed, 25 insertions(+), 25 deletions(-) diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp index 9b190c646..88c0e0731 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp @@ -1341,8 +1341,8 @@ static int build_top_module_global_net_for_given_tile_module( return CMD_EXEC_FATAL_ERROR; } grid_pin_start_index = - (subtile_index - sub_tile.capacity.low) * sub_tile_num_pins + - tile_port.absolute_first_pin_index; + sub_tile.sub_tile_to_tile_pin_indices[(subtile_index - sub_tile.capacity.low) * sub_tile_num_pins + + tile_port.absolute_first_pin_index]; physical_tile_port = tile_port; break; } @@ -1386,6 +1386,7 @@ static int build_top_module_global_net_for_given_tile_module( generate_tile_module_port_name(grid_instance_name, grid_port_name); ModulePortId tile_grid_port_id = module_manager.find_module_port(tile_module, tile_grid_port_name); + VTR_LOG("Finding global port '%s' from grid '%s'\n", tile_grid_port_name.c_str(), tile_module_name.c_str()); VTR_ASSERT(true == module_manager.valid_module_port_id( tile_module, tile_grid_port_id)); diff --git a/openfpga/src/utils/check_tile_annotation.cpp b/openfpga/src/utils/check_tile_annotation.cpp index 6117e3109..68097d2af 100644 --- a/openfpga/src/utils/check_tile_annotation.cpp +++ b/openfpga/src/utils/check_tile_annotation.cpp @@ -128,7 +128,6 @@ static int check_tile_annotation_conflicts_with_physical_tile( ++tile_info_id) { /* Must find a valid physical tile in the same name */ size_t found_matched_physical_tile = 0; - size_t found_matched_physical_tile_port = 0; std::string required_tile_name = tile_annotation.global_port_tile_names(tile_global_port)[tile_info_id]; @@ -146,6 +145,7 @@ static int check_tile_annotation_conflicts_with_physical_tile( /* Must found a valid port where both port name and port size must * match!!! */ for (const t_sub_tile& sub_tile : physical_tile.sub_tiles) { + size_t found_matched_physical_tile_port = 0; for (const t_physical_tile_port& tile_port : sub_tile.ports) { if (std::string(tile_port.name) != required_tile_port.get_name()) { continue; @@ -167,7 +167,7 @@ static int check_tile_annotation_conflicts_with_physical_tile( } /* Check if port property matches */ - int grid_pin_index = tile_port.absolute_first_pin_index; + int grid_pin_index = sub_tile.sub_tile_to_tile_pin_indices[tile_port.absolute_first_pin_index]; if (tile_port.is_clock != tile_annotation.global_port_is_clock(tile_global_port)) { @@ -215,6 +215,26 @@ static int check_tile_annotation_conflicts_with_physical_tile( found_matched_physical_tile_port++; } + if (0 == found_matched_physical_tile_port) { + VTR_LOGF_ERROR( + __FILE__, __LINE__, + "Tile port '%s.%s[%ld:%ld]' in tile annotation '%s' does not match " + "any physical tile port!\n", + required_tile_name.c_str(), required_tile_port.get_name().c_str(), + required_tile_port.get_lsb(), required_tile_port.get_msb(), + tile_annotation.global_port_name(tile_global_port).c_str()); + num_err++; + } + if (1 < found_matched_physical_tile_port) { + VTR_LOGF_ERROR( + __FILE__, __LINE__, + "Tile port '%s.%s[%ld:%ld]' in tile annotation '%s' match more than " + "1 physical tile port!\n", + required_tile_name.c_str(), required_tile_port.get_name().c_str(), + required_tile_port.get_lsb(), required_tile_port.get_msb(), + tile_annotation.global_port_name(tile_global_port).c_str()); + num_err++; + } } } @@ -228,17 +248,6 @@ static int check_tile_annotation_conflicts_with_physical_tile( tile_annotation.global_port_name(tile_global_port).c_str()); num_err++; } - if (0 == found_matched_physical_tile_port) { - VTR_LOGF_ERROR( - __FILE__, __LINE__, - "Tile port '%s.%s[%ld:%ld]' in tile annotation '%s' does not match " - "any physical tile port!\n", - required_tile_name.c_str(), required_tile_port.get_name().c_str(), - required_tile_port.get_lsb(), required_tile_port.get_msb(), - tile_annotation.global_port_name(tile_global_port).c_str()); - num_err++; - } - /* If we found more than 1 match, error out */ if (1 < found_matched_physical_tile) { VTR_LOGF_ERROR( @@ -249,16 +258,6 @@ static int check_tile_annotation_conflicts_with_physical_tile( tile_annotation.global_port_name(tile_global_port).c_str()); num_err++; } - if (1 < found_matched_physical_tile_port) { - VTR_LOGF_ERROR( - __FILE__, __LINE__, - "Tile port '%s.%s[%ld:%ld]' in tile annotation '%s' match more than " - "1 physical tile port!\n", - required_tile_name.c_str(), required_tile_port.get_name().c_str(), - required_tile_port.get_lsb(), required_tile_port.get_msb(), - tile_annotation.global_port_name(tile_global_port).c_str()); - num_err++; - } } } From 19d4d9a16d6f391dfaa3ebf932887955d60e9f8c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Aug 2023 21:05:26 -0700 Subject: [PATCH 2/7] [core] code format --- .../src/fabric/build_top_module_child_tile_instance.cpp | 8 +++++--- openfpga/src/utils/check_tile_annotation.cpp | 9 ++++++--- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp index 88c0e0731..e8ef67488 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp @@ -1341,8 +1341,9 @@ static int build_top_module_global_net_for_given_tile_module( return CMD_EXEC_FATAL_ERROR; } grid_pin_start_index = - sub_tile.sub_tile_to_tile_pin_indices[(subtile_index - sub_tile.capacity.low) * sub_tile_num_pins + - tile_port.absolute_first_pin_index]; + sub_tile.sub_tile_to_tile_pin_indices + [(subtile_index - sub_tile.capacity.low) * sub_tile_num_pins + + tile_port.absolute_first_pin_index]; physical_tile_port = tile_port; break; } @@ -1386,7 +1387,8 @@ static int build_top_module_global_net_for_given_tile_module( generate_tile_module_port_name(grid_instance_name, grid_port_name); ModulePortId tile_grid_port_id = module_manager.find_module_port(tile_module, tile_grid_port_name); - VTR_LOG("Finding global port '%s' from grid '%s'\n", tile_grid_port_name.c_str(), tile_module_name.c_str()); + VTR_LOG("Finding global port '%s' from grid '%s'\n", + tile_grid_port_name.c_str(), tile_module_name.c_str()); VTR_ASSERT(true == module_manager.valid_module_port_id( tile_module, tile_grid_port_id)); diff --git a/openfpga/src/utils/check_tile_annotation.cpp b/openfpga/src/utils/check_tile_annotation.cpp index 68097d2af..929a3b24e 100644 --- a/openfpga/src/utils/check_tile_annotation.cpp +++ b/openfpga/src/utils/check_tile_annotation.cpp @@ -167,7 +167,8 @@ static int check_tile_annotation_conflicts_with_physical_tile( } /* Check if port property matches */ - int grid_pin_index = sub_tile.sub_tile_to_tile_pin_indices[tile_port.absolute_first_pin_index]; + int grid_pin_index = sub_tile.sub_tile_to_tile_pin_indices + [tile_port.absolute_first_pin_index]; if (tile_port.is_clock != tile_annotation.global_port_is_clock(tile_global_port)) { @@ -218,7 +219,8 @@ static int check_tile_annotation_conflicts_with_physical_tile( if (0 == found_matched_physical_tile_port) { VTR_LOGF_ERROR( __FILE__, __LINE__, - "Tile port '%s.%s[%ld:%ld]' in tile annotation '%s' does not match " + "Tile port '%s.%s[%ld:%ld]' in tile annotation '%s' does not " + "match " "any physical tile port!\n", required_tile_name.c_str(), required_tile_port.get_name().c_str(), required_tile_port.get_lsb(), required_tile_port.get_msb(), @@ -228,7 +230,8 @@ static int check_tile_annotation_conflicts_with_physical_tile( if (1 < found_matched_physical_tile_port) { VTR_LOGF_ERROR( __FILE__, __LINE__, - "Tile port '%s.%s[%ld:%ld]' in tile annotation '%s' match more than " + "Tile port '%s.%s[%ld:%ld]' in tile annotation '%s' match more " + "than " "1 physical tile port!\n", required_tile_name.c_str(), required_tile_port.get_name().c_str(), required_tile_port.get_lsb(), required_tile_port.get_msb(), From 5ac8919ce029cbc0d7dddb60dc6091bf6463bf11 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Aug 2023 21:37:15 -0700 Subject: [PATCH 3/7] [test] add a new testcase to validate subtile with tile annotations --- ...balTileClk_registerable_io_cc_openfpga.xml | 14 +++ .../regression_test_scripts/basic_reg_test.sh | 1 + .../config/task.conf | 35 ++++++ ...ble_GlobalTileClk_registerable_io_40nm.xml | 116 ++++++++++++++++++ 4 files changed, 166 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile/config/task.conf diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml index 8722f8614..0a5978d27 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml @@ -158,6 +158,13 @@ + + + + + + + @@ -175,6 +182,7 @@ + @@ -186,6 +194,12 @@ + + + + + + diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 2a3687033..16845c00f 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -198,6 +198,7 @@ run-task basic_tests/group_config_block/group_config_block_hetero_fabric_tile_Ls echo -e "Testing global port definition from tiles"; run-task basic_tests/global_tile_ports/global_tile_clock $@ +run-task basic_tests/global_tile_ports/global_tile_clock_subtile $@ run-task basic_tests/global_tile_ports/global_tile_reset $@ run-task basic_tests/global_tile_ports/global_tile_4clock $@ run-task basic_tests/global_tile_ports/global_tile_4clock_pin $@ diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile/config/task.conf new file mode 100644 index 000000000..d75851ad9 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile/config/task.conf @@ -0,0 +1,35 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=2x2_hybrid_io + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2_pipelined + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml index 1f8022119..509187cfb 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml @@ -34,6 +34,11 @@ + + + + + @@ -55,6 +60,41 @@ + + + + + + + + + + + + io_input.inpad io_input.clk + io_input.inpad io_input.clk + io_input.inpad io_input.clk + io_input.inpad io_input.clk + + + + + + + + + + + + + + io.outpad io.inpad io.clk + io.outpad io.inpad io.clk + io.outpad io.inpad io.clk + io.outpad io.inpad io.clk + + + @@ -87,6 +127,13 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - + + + @@ -316,8 +316,8 @@ - - + + @@ -333,11 +333,11 @@ - + - + From 5f6050d40474c9a55f61828eb2d705134966b895 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Aug 2023 21:48:40 -0700 Subject: [PATCH 5/7] [test] add a new test to validate combo: group tile, tile annotation and subtile --- .../regression_test_scripts/basic_reg_test.sh | 1 + .../config/task.conf | 42 +++++++++++++++++++ .../config/tile_config.xml | 1 + 3 files changed, 44 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile/config/tile_config.xml diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 16845c00f..4ec35395f 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -179,6 +179,7 @@ run-task basic_tests/tile_organization/io_subtile_strong $@ echo -e "Testing tile grouping on a homogeneous FPGA fabric (Full testbench)"; run-task basic_tests/tile_organization/homo_fabric_tile $@ echo -e "Testing tile grouping on a homogeneous FPGA fabric (Preconfigured testbench)"; +run-task basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile $@ run-task basic_tests/tile_organization/homo_fabric_tile_preconfig $@ run-task basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig $@ run-task basic_tests/tile_organization/homo_fabric_tile_4x4_preconfig $@ diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile/config/task.conf new file mode 100644 index 000000000..1c477f704 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=2x2_hybrid_io +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping + + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2_pipelined + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile/config/tile_config.xml @@ -0,0 +1 @@ + From 15a8d8a76a8be493a88548c540c53b24cfb18cf3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Aug 2023 21:59:06 -0700 Subject: [PATCH 6/7] [test] added a new test to validate combo: group_tile, group_config_block, io subtile, tile annotation --- .../regression_test_scripts/basic_reg_test.sh | 1 + .../config/task.conf | 42 +++++++++++++++++++ .../config/tile_config.xml | 1 + 3 files changed, 44 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/group_config_block/group_config_block_homo_fabric_tile_global_tile_clock_io_subtile/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/group_config_block/group_config_block_homo_fabric_tile_global_tile_clock_io_subtile/config/tile_config.xml diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 4ec35395f..a96902f98 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -196,6 +196,7 @@ run-task basic_tests/group_config_block/group_config_block_homo_fabric_tile_Lsha run-task basic_tests/group_config_block/group_config_block_homo_fabric_tile_core_wrapper $@ run-task basic_tests/group_config_block/group_config_block_hetero_fabric_tile $@ run-task basic_tests/group_config_block/group_config_block_hetero_fabric_tile_Lshape $@ +run-task basic_tests/group_config_block/group_config_block_homo_fabric_tile_global_tile_clock_io_subtile $@ echo -e "Testing global port definition from tiles"; run-task basic_tests/global_tile_ports/global_tile_clock $@ diff --git a/openfpga_flow/tasks/basic_tests/group_config_block/group_config_block_homo_fabric_tile_global_tile_clock_io_subtile/config/task.conf b/openfpga_flow/tasks/basic_tests/group_config_block/group_config_block_homo_fabric_tile_global_tile_clock_io_subtile/config/task.conf new file mode 100644 index 000000000..a04c046d9 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/group_config_block/group_config_block_homo_fabric_tile_global_tile_clock_io_subtile/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_config_block_preconfig_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=2x2_hybrid_io +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_option=--group_tile ${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping +openfpga_add_fpga_core_module= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2_pipelined + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/group_config_block/group_config_block_homo_fabric_tile_global_tile_clock_io_subtile/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/group_config_block/group_config_block_homo_fabric_tile_global_tile_clock_io_subtile/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/group_config_block/group_config_block_homo_fabric_tile_global_tile_clock_io_subtile/config/tile_config.xml @@ -0,0 +1 @@ + From 66cc37599670e93a4c07f31b6bf5b759c32d23bb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Aug 2023 22:08:47 -0700 Subject: [PATCH 7/7] [core] remove debugging messages --- .../src/fabric/build_top_module_child_fine_grained_instance.cpp | 1 - openfpga/src/fabric/build_top_module_child_tile_instance.cpp | 2 -- 2 files changed, 3 deletions(-) diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp index 47067a2cb..13c09952f 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp @@ -402,7 +402,6 @@ static void add_top_module_io_children( /* Now walk through the coordinates */ for (vtr::Point coord : coords) { - VTR_LOG("Adding coord [%lu][%lu]\n", coord.x(), coord.y()); t_physical_tile_loc phy_tile_loc(coord.x(), coord.y(), layer); t_physical_tile_type_ptr grid_type = grids.get_physical_type(phy_tile_loc); /* Bypass EMPTY grid */ diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp index e8ef67488..dd4669c3f 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp @@ -1387,8 +1387,6 @@ static int build_top_module_global_net_for_given_tile_module( generate_tile_module_port_name(grid_instance_name, grid_port_name); ModulePortId tile_grid_port_id = module_manager.find_module_port(tile_module, tile_grid_port_name); - VTR_LOG("Finding global port '%s' from grid '%s'\n", - tile_grid_port_name.c_str(), tile_module_name.c_str()); VTR_ASSERT(true == module_manager.valid_module_port_id( tile_module, tile_grid_port_id));