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[script] turn off the pb_pin_fix_up in vpr run for mcnc and vtr benchmarks

This commit is contained in:
tangxifan 2022-08-27 20:04:29 -07:00
parent b9abdbc5d4
commit b9fade4c76
2 changed files with 2 additions and 2 deletions
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2
openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga
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@ -2,7 +2,7 @@
# When the global clock is defined as a port of a tile, clock routing in VPR should be skipped # When the global clock is defined as a port of a tile, clock routing in VPR should be skipped
# This is due to the Fc_in of clock port is set to 0 for global wiring # This is due to the Fc_in of clock port is set to 0 for global wiring
# The constant net such as logic '0' and logic '1' must be routed because current architecture cannot produce them locally # The constant net such as logic '0' and logic '1' must be routed because current architecture cannot produce them locally
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route --skip_sync_clustering_and_routing_results on
# Read OpenFPGA architecture definition # Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

2
openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga
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@ -1,6 +1,6 @@
# Run VPR for the 'and' design # Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml #--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffer_luts off vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffer_luts off --skip_sync_clustering_and_routing_results on
# Read OpenFPGA architecture definition # Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}