riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

don't leave bus ports unconnected

This commit is contained in:
Tarachand Pagarani 2022-03-09 08:25:20 -08:00
parent 1543624279
commit b9e4977e7e
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
vpr/src/base/netlist_writer.cpp
View File

@ -2191,7 +2191,7 @@ void print_verilog_port(std::ostream& os, size_t& unconn_count, const std::strin
os << "1'b0"; os << "1'b0";
} else { } else {
VTR_ASSERT(type == PortType::OUTPUT); VTR_ASSERT(type == PortType::OUTPUT);
os << ""; os << create_unconn_net(unconn_count);
} }
} else { } else {
//Connected //Connected