update documentation about memory bank configuration protocol
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@ -100,6 +100,8 @@ When the decoder of sub block, e.g., the LUT, is enabled, each memory cells can
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- a Bit-Line input to load the data
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- a Bit-Line input to load the data
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- a Word-Line input to enable data write
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- a Word-Line input to enable data write
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.. warning:: Please do NOT add inverted Bit-Line and Word-Line inputs. It is not supported yet!
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Memory bank Example
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Memory bank Example
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~~~~~~~~~~~~~~~~~~~
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~~~~~~~~~~~~~~~~~~~
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The following XML code describes a memory-bank circuitry to configure the core logic of FPGA, as illustrated in :numref:`fig_sram`.
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The following XML code describes a memory-bank circuitry to configure the core logic of FPGA, as illustrated in :numref:`fig_sram`.
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@ -119,7 +121,13 @@ It will use the circuit model defined in :numref:`fig_sram_blwl`.
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Example of a memory organization using memory decoders
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Example of a memory organization using memory decoders
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.. warning:: THIS IS STILL UNDER CONSTRUCTION
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.. note:: Memory-bank decoders does require a memory cell to have
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- two outputs (one regular and another inverted)
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- a Bit-Line input to load the data
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- a Word-Line input to enable data write
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.. warning:: Please do NOT add inverted Bit-Line and Word-Line inputs. It is not supported yet!
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Standalone SRAM Example
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Standalone SRAM Example
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~~~~~~~~~~~~~~~~~~~~~~~
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~~~~~~~~~~~~~~~~~~~~~~~
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@ -147,5 +155,7 @@ The following XML code shows an example where we use the circuit model defined i
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- a Bit-Line input to load the data
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- a Bit-Line input to load the data
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- a Word-Line input to enable data write
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- a Word-Line input to enable data write
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.. warning:: Please do NOT add inverted Bit-Line and Word-Line inputs. It is not supported yet!
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.. warning:: This is a vanilla configuration method, which allow users to build their own configuration protocol on top of it.
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.. warning:: This is a vanilla configuration method, which allow users to build their own configuration protocol on top of it.
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