diff --git a/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_FF.xml b/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_FF.xml new file mode 100755 index 000000000..cc714cbed --- /dev/null +++ b/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_FF.xml @@ -0,0 +1,1427 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + 1 1 1 + 1 1 + + + + 1 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 127e-12 + 127e-12 + 127e-12 + 127e-12 + 127e-12 + 127e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.clk + clb.I[19:0] clb.O[4:0] + clb.I[39:20] clb.O[9:5] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_MC.xml b/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_MC.xml new file mode 100755 index 000000000..a7d20cb1c --- /dev/null +++ b/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_MC.xml @@ -0,0 +1,1428 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + 1 1 1 + 1 1 + + + + 1 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 127e-12 + 127e-12 + 127e-12 + 127e-12 + 127e-12 + 127e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.clk + clb.I[19:0] clb.O[4:0] + clb.I[39:20] clb.O[9:5] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_SS.xml b/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_SS.xml new file mode 100755 index 000000000..1b43d2b52 --- /dev/null +++ b/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_SS.xml @@ -0,0 +1,1427 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + 1 1 1 + 1 1 + + + + 1 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 127e-12 + 127e-12 + 127e-12 + 127e-12 + 127e-12 + 127e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.clk + clb.I[19:0] clb.O[4:0] + clb.I[39:20] clb.O[9:5] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml b/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml new file mode 100755 index 000000000..8224f2fa0 --- /dev/null +++ b/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml @@ -0,0 +1,1427 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + 1 1 1 + 1 1 + + + + 1 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 127e-12 + 127e-12 + 127e-12 + 127e-12 + 127e-12 + 127e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.clk + clb.I[19:0] clb.O[4:0] + clb.I[39:20] clb.O[9:5] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/C1355.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/C1355.blif new file mode 100644 index 000000000..7f43f6af0 --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/C1355.blif @@ -0,0 +1,1102 @@ + + +# ATPG -- Automatic Test Pattern Generation for +# Combinational Circuits +# ATPG, Version 1.0, 4/29/86, Author: Ruey-sing Wei and Tony Ma + +.model C1355.iscas +.inputs 1GAT(0) 8GAT(1) 15GAT(2) 22GAT(3) 29GAT(4) 36GAT(5) 43GAT(6) 50GAT(7) 57GAT(8) 64GAT(9) 71GAT(10) 78GAT(11) 85GAT(12) 92GAT(13) 99GAT(14) 106GAT(15) 113GAT(16) 120GAT(17) 127GAT(18) 134GAT(19) 141GAT(20) 148GAT(21) 155GAT(22) 162GAT(23) 169GAT(24) 176GAT(25) 183GAT(26) 190GAT(27) 197GAT(28) 204GAT(29) 211GAT(30) 218GAT(31) 225GAT(32) 226GAT(33) 227GAT(34) 228GAT(35) 229GAT(36) 230GAT(37) 231GAT(38) 232GAT(39) 233GAT(40) +.outputs 1324GAT(583) 1325GAT(579) 1326GAT(575) 1327GAT(571) 1328GAT(584) 1329GAT(580) 1330GAT(576) 1331GAT(572) 1332GAT(585) 1333GAT(581) 1334GAT(577) 1335GAT(573) 1336GAT(586) 1337GAT(582) 1338GAT(578) 1339GAT(574) 1340GAT(567) 1341GAT(563) 1342GAT(559) 1343GAT(555) 1344GAT(568) 1345GAT(564) 1346GAT(560) 1347GAT(556) 1348GAT(569) 1349GAT(565) 1350GAT(561) 1351GAT(557) 1352GAT(570) 1353GAT(566) 1354GAT(562) 1355GAT(558) +.names 232GAT(39) 233GAT(40) 263GAT(41) +11 1 +.names 231GAT(38) 233GAT(40) 260GAT(42) +11 1 +.names 230GAT(37) 233GAT(40) 257GAT(43) +11 1 +.names 229GAT(36) 233GAT(40) 254GAT(44) +11 1 +.names 228GAT(35) 233GAT(40) 251GAT(45) +11 1 +.names 227GAT(34) 233GAT(40) 248GAT(46) +11 1 +.names 226GAT(33) 233GAT(40) 245GAT(47) +11 1 +.names 225GAT(32) 233GAT(40) 242GAT(48) +11 1 +.names 211GAT(30) 218GAT(31) 311GAT(49) +11 0 +.names 197GAT(28) 204GAT(29) 308GAT(50) +11 0 +.names 190GAT(27) 218GAT(31) 359GAT(51) +11 0 +.names 183GAT(26) 211GAT(30) 353GAT(52) +11 0 +.names 183GAT(26) 190GAT(27) 305GAT(53) +11 0 +.names 176GAT(25) 204GAT(29) 347GAT(54) +11 0 +.names 169GAT(24) 197GAT(28) 341GAT(55) +11 0 +.names 169GAT(24) 176GAT(25) 302GAT(56) +11 0 +.names 155GAT(22) 162GAT(23) 299GAT(57) +11 0 +.names 141GAT(20) 148GAT(21) 296GAT(58) +11 0 +.names 134GAT(19) 162GAT(23) 356GAT(59) +11 0 +.names 127GAT(18) 155GAT(22) 350GAT(60) +11 0 +.names 127GAT(18) 134GAT(19) 293GAT(61) +11 0 +.names 120GAT(17) 148GAT(21) 344GAT(62) +11 0 +.names 113GAT(16) 141GAT(20) 338GAT(63) +11 0 +.names 113GAT(16) 120GAT(17) 290GAT(64) +11 0 +.names 99GAT(14) 106GAT(15) 287GAT(65) +11 0 +.names 85GAT(12) 92GAT(13) 284GAT(66) +11 0 +.names 78GAT(11) 106GAT(15) 335GAT(67) +11 0 +.names 71GAT(10) 99GAT(14) 329GAT(68) +11 0 +.names 71GAT(10) 78GAT(11) 281GAT(69) +11 0 +.names 64GAT(9) 92GAT(13) 323GAT(70) +11 0 +.names 57GAT(8) 85GAT(12) 317GAT(71) +11 0 +.names 57GAT(8) 64GAT(9) 278GAT(72) +11 0 +.names 43GAT(6) 50GAT(7) 275GAT(73) +11 0 +.names 29GAT(4) 36GAT(5) 272GAT(74) +11 0 +.names 22GAT(3) 50GAT(7) 332GAT(75) +11 0 +.names 15GAT(2) 43GAT(6) 326GAT(76) +11 0 +.names 15GAT(2) 22GAT(3) 269GAT(77) +11 0 +.names 8GAT(1) 36GAT(5) 320GAT(78) +11 0 +.names 1GAT(0) 29GAT(4) 314GAT(79) +11 0 +.names 1GAT(0) 8GAT(1) 266GAT(80) +11 0 +.names 218GAT(31) 359GAT(51) 425GAT(81) +11 0 +.names 218GAT(31) 311GAT(49) 393GAT(82) +11 0 +.names 211GAT(30) 353GAT(52) 421GAT(83) +11 0 +.names 211GAT(30) 311GAT(49) 392GAT(84) +11 0 +.names 204GAT(29) 347GAT(54) 417GAT(85) +11 0 +.names 204GAT(29) 308GAT(50) 391GAT(86) +11 0 +.names 197GAT(28) 341GAT(55) 413GAT(87) +11 0 +.names 197GAT(28) 308GAT(50) 390GAT(88) +11 0 +.names 190GAT(27) 359GAT(51) 424GAT(89) +11 0 +.names 190GAT(27) 305GAT(53) 389GAT(90) +11 0 +.names 183GAT(26) 353GAT(52) 420GAT(91) +11 0 +.names 183GAT(26) 305GAT(53) 388GAT(92) +11 0 +.names 176GAT(25) 347GAT(54) 416GAT(93) +11 0 +.names 176GAT(25) 302GAT(56) 387GAT(94) +11 0 +.names 169GAT(24) 341GAT(55) 412GAT(95) +11 0 +.names 169GAT(24) 302GAT(56) 386GAT(96) +11 0 +.names 162GAT(23) 356GAT(59) 423GAT(97) +11 0 +.names 162GAT(23) 299GAT(57) 385GAT(98) +11 0 +.names 155GAT(22) 350GAT(60) 419GAT(99) +11 0 +.names 155GAT(22) 299GAT(57) 384GAT(100) +11 0 +.names 148GAT(21) 344GAT(62) 415GAT(101) +11 0 +.names 148GAT(21) 296GAT(58) 383GAT(102) +11 0 +.names 141GAT(20) 338GAT(63) 411GAT(103) +11 0 +.names 141GAT(20) 296GAT(58) 382GAT(104) +11 0 +.names 134GAT(19) 356GAT(59) 422GAT(105) +11 0 +.names 134GAT(19) 293GAT(61) 381GAT(106) +11 0 +.names 127GAT(18) 350GAT(60) 418GAT(107) +11 0 +.names 127GAT(18) 293GAT(61) 380GAT(108) +11 0 +.names 120GAT(17) 344GAT(62) 414GAT(109) +11 0 +.names 120GAT(17) 290GAT(64) 379GAT(110) +11 0 +.names 113GAT(16) 338GAT(63) 410GAT(111) +11 0 +.names 113GAT(16) 290GAT(64) 378GAT(112) +11 0 +.names 106GAT(15) 335GAT(67) 409GAT(113) +11 0 +.names 106GAT(15) 287GAT(65) 377GAT(114) +11 0 +.names 99GAT(14) 329GAT(68) 405GAT(115) +11 0 +.names 99GAT(14) 287GAT(65) 376GAT(116) +11 0 +.names 92GAT(13) 323GAT(70) 401GAT(117) +11 0 +.names 92GAT(13) 284GAT(66) 375GAT(118) +11 0 +.names 85GAT(12) 317GAT(71) 397GAT(119) +11 0 +.names 85GAT(12) 284GAT(66) 374GAT(120) +11 0 +.names 78GAT(11) 335GAT(67) 408GAT(121) +11 0 +.names 78GAT(11) 281GAT(69) 373GAT(122) +11 0 +.names 71GAT(10) 329GAT(68) 404GAT(123) +11 0 +.names 71GAT(10) 281GAT(69) 372GAT(124) +11 0 +.names 64GAT(9) 323GAT(70) 400GAT(125) +11 0 +.names 64GAT(9) 278GAT(72) 371GAT(126) +11 0 +.names 57GAT(8) 317GAT(71) 396GAT(127) +11 0 +.names 57GAT(8) 278GAT(72) 370GAT(128) +11 0 +.names 50GAT(7) 332GAT(75) 407GAT(129) +11 0 +.names 50GAT(7) 275GAT(73) 369GAT(130) +11 0 +.names 43GAT(6) 326GAT(76) 403GAT(131) +11 0 +.names 43GAT(6) 275GAT(73) 368GAT(132) +11 0 +.names 36GAT(5) 320GAT(78) 399GAT(133) +11 0 +.names 36GAT(5) 272GAT(74) 367GAT(134) +11 0 +.names 29GAT(4) 314GAT(79) 395GAT(135) +11 0 +.names 29GAT(4) 272GAT(74) 366GAT(136) +11 0 +.names 22GAT(3) 332GAT(75) 406GAT(137) +11 0 +.names 22GAT(3) 269GAT(77) 365GAT(138) +11 0 +.names 15GAT(2) 326GAT(76) 402GAT(139) +11 0 +.names 15GAT(2) 269GAT(77) 364GAT(140) +11 0 +.names 8GAT(1) 320GAT(78) 398GAT(141) +11 0 +.names 8GAT(1) 266GAT(80) 363GAT(142) +11 0 +.names 1GAT(0) 314GAT(79) 394GAT(143) +11 0 +.names 1GAT(0) 266GAT(80) 362GAT(144) +11 0 +.names 424GAT(89) 425GAT(81) 519GAT(145) +11 0 +.names 392GAT(84) 393GAT(82) 471GAT(146) +11 0 +.names 420GAT(91) 421GAT(83) 513GAT(147) +11 0 +.names 416GAT(93) 417GAT(85) 507GAT(148) +11 0 +.names 390GAT(88) 391GAT(86) 468GAT(149) +11 0 +.names 412GAT(95) 413GAT(87) 501GAT(150) +11 0 +.names 388GAT(92) 389GAT(90) 465GAT(151) +11 0 +.names 386GAT(96) 387GAT(94) 462GAT(152) +11 0 +.names 422GAT(105) 423GAT(97) 516GAT(153) +11 0 +.names 384GAT(100) 385GAT(98) 459GAT(154) +11 0 +.names 418GAT(107) 419GAT(99) 510GAT(155) +11 0 +.names 414GAT(109) 415GAT(101) 504GAT(156) +11 0 +.names 382GAT(104) 383GAT(102) 456GAT(157) +11 0 +.names 410GAT(111) 411GAT(103) 498GAT(158) +11 0 +.names 380GAT(108) 381GAT(106) 453GAT(159) +11 0 +.names 378GAT(112) 379GAT(110) 450GAT(160) +11 0 +.names 408GAT(121) 409GAT(113) 495GAT(161) +11 0 +.names 376GAT(116) 377GAT(114) 447GAT(162) +11 0 +.names 404GAT(123) 405GAT(115) 489GAT(163) +11 0 +.names 400GAT(125) 401GAT(117) 483GAT(164) +11 0 +.names 374GAT(120) 375GAT(118) 444GAT(165) +11 0 +.names 396GAT(127) 397GAT(119) 477GAT(166) +11 0 +.names 372GAT(124) 373GAT(122) 441GAT(167) +11 0 +.names 370GAT(128) 371GAT(126) 438GAT(168) +11 0 +.names 406GAT(137) 407GAT(129) 492GAT(169) +11 0 +.names 368GAT(132) 369GAT(130) 435GAT(170) +11 0 +.names 402GAT(139) 403GAT(131) 486GAT(171) +11 0 +.names 398GAT(141) 399GAT(133) 480GAT(172) +11 0 +.names 366GAT(136) 367GAT(134) 432GAT(173) +11 0 +.names 394GAT(143) 395GAT(135) 474GAT(174) +11 0 +.names 364GAT(140) 365GAT(138) 429GAT(175) +11 0 +.names 362GAT(144) 363GAT(142) 426GAT(176) +11 0 +.names 516GAT(153) 519GAT(145) 567GAT(177) +11 0 +.names 468GAT(149) 471GAT(146) 543GAT(178) +11 0 +.names 510GAT(155) 513GAT(147) 564GAT(179) +11 0 +.names 504GAT(156) 507GAT(148) 561GAT(180) +11 0 +.names 498GAT(158) 501GAT(150) 558GAT(181) +11 0 +.names 462GAT(152) 465GAT(151) 540GAT(182) +11 0 +.names 456GAT(157) 459GAT(154) 537GAT(183) +11 0 +.names 450GAT(160) 453GAT(159) 534GAT(184) +11 0 +.names 492GAT(169) 495GAT(161) 555GAT(185) +11 0 +.names 444GAT(165) 447GAT(162) 531GAT(186) +11 0 +.names 486GAT(171) 489GAT(163) 552GAT(187) +11 0 +.names 480GAT(172) 483GAT(164) 549GAT(188) +11 0 +.names 474GAT(174) 477GAT(166) 546GAT(189) +11 0 +.names 438GAT(168) 441GAT(167) 528GAT(190) +11 0 +.names 432GAT(173) 435GAT(170) 525GAT(191) +11 0 +.names 426GAT(176) 429GAT(175) 522GAT(192) +11 0 +.names 519GAT(145) 567GAT(177) 601GAT(193) +11 0 +.names 471GAT(146) 543GAT(178) 585GAT(194) +11 0 +.names 513GAT(147) 564GAT(179) 599GAT(195) +11 0 +.names 507GAT(148) 561GAT(180) 597GAT(196) +11 0 +.names 468GAT(149) 543GAT(178) 584GAT(197) +11 0 +.names 501GAT(150) 558GAT(181) 595GAT(198) +11 0 +.names 465GAT(151) 540GAT(182) 583GAT(199) +11 0 +.names 462GAT(152) 540GAT(182) 582GAT(200) +11 0 +.names 516GAT(153) 567GAT(177) 600GAT(201) +11 0 +.names 459GAT(154) 537GAT(183) 581GAT(202) +11 0 +.names 510GAT(155) 564GAT(179) 598GAT(203) +11 0 +.names 504GAT(156) 561GAT(180) 596GAT(204) +11 0 +.names 456GAT(157) 537GAT(183) 580GAT(205) +11 0 +.names 498GAT(158) 558GAT(181) 594GAT(206) +11 0 +.names 453GAT(159) 534GAT(184) 579GAT(207) +11 0 +.names 450GAT(160) 534GAT(184) 578GAT(208) +11 0 +.names 495GAT(161) 555GAT(185) 593GAT(209) +11 0 +.names 447GAT(162) 531GAT(186) 577GAT(210) +11 0 +.names 489GAT(163) 552GAT(187) 591GAT(211) +11 0 +.names 483GAT(164) 549GAT(188) 589GAT(212) +11 0 +.names 444GAT(165) 531GAT(186) 576GAT(213) +11 0 +.names 477GAT(166) 546GAT(189) 587GAT(214) +11 0 +.names 441GAT(167) 528GAT(190) 575GAT(215) +11 0 +.names 438GAT(168) 528GAT(190) 574GAT(216) +11 0 +.names 492GAT(169) 555GAT(185) 592GAT(217) +11 0 +.names 435GAT(170) 525GAT(191) 573GAT(218) +11 0 +.names 486GAT(171) 552GAT(187) 590GAT(219) +11 0 +.names 480GAT(172) 549GAT(188) 588GAT(220) +11 0 +.names 432GAT(173) 525GAT(191) 572GAT(221) +11 0 +.names 474GAT(174) 546GAT(189) 586GAT(222) +11 0 +.names 429GAT(175) 522GAT(192) 571GAT(223) +11 0 +.names 426GAT(176) 522GAT(192) 570GAT(224) +11 0 +.names 600GAT(201) 601GAT(193) 663GAT(225) +11 0 +.names 584GAT(197) 585GAT(194) 637GAT(226) +11 0 +.names 598GAT(203) 599GAT(195) 660GAT(227) +11 0 +.names 596GAT(204) 597GAT(196) 657GAT(228) +11 0 +.names 594GAT(206) 595GAT(198) 654GAT(229) +11 0 +.names 582GAT(200) 583GAT(199) 632GAT(230) +11 0 +.names 580GAT(205) 581GAT(202) 627GAT(231) +11 0 +.names 578GAT(208) 579GAT(207) 622GAT(232) +11 0 +.names 592GAT(217) 593GAT(209) 651GAT(233) +11 0 +.names 576GAT(213) 577GAT(210) 617GAT(234) +11 0 +.names 590GAT(219) 591GAT(211) 648GAT(235) +11 0 +.names 588GAT(220) 589GAT(212) 645GAT(236) +11 0 +.names 586GAT(222) 587GAT(214) 642GAT(237) +11 0 +.names 574GAT(216) 575GAT(215) 612GAT(238) +11 0 +.names 572GAT(221) 573GAT(218) 607GAT(239) +11 0 +.names 570GAT(224) 571GAT(223) 602GAT(240) +11 0 +.names 632GAT(230) 637GAT(226) 681GAT(241) +11 0 +.names 627GAT(231) 637GAT(226) 687GAT(242) +11 0 +.names 622GAT(232) 632GAT(230) 684GAT(243) +11 0 +.names 622GAT(232) 627GAT(231) 678GAT(244) +11 0 +.names 612GAT(238) 617GAT(234) 669GAT(245) +11 0 +.names 607GAT(239) 617GAT(234) 675GAT(246) +11 0 +.names 602GAT(240) 612GAT(238) 672GAT(247) +11 0 +.names 602GAT(240) 607GAT(239) 666GAT(248) +11 0 +.names 637GAT(226) 681GAT(241) 701GAT(249) +11 0 +.names 637GAT(226) 687GAT(242) 705GAT(250) +11 0 +.names 632GAT(230) 681GAT(241) 700GAT(251) +11 0 +.names 632GAT(230) 684GAT(243) 703GAT(252) +11 0 +.names 627GAT(231) 678GAT(244) 699GAT(253) +11 0 +.names 627GAT(231) 687GAT(242) 704GAT(254) +11 0 +.names 622GAT(232) 678GAT(244) 698GAT(255) +11 0 +.names 622GAT(232) 684GAT(243) 702GAT(256) +11 0 +.names 617GAT(234) 669GAT(245) 693GAT(257) +11 0 +.names 617GAT(234) 675GAT(246) 697GAT(258) +11 0 +.names 612GAT(238) 669GAT(245) 692GAT(259) +11 0 +.names 612GAT(238) 672GAT(247) 695GAT(260) +11 0 +.names 607GAT(239) 666GAT(248) 691GAT(261) +11 0 +.names 607GAT(239) 675GAT(246) 696GAT(262) +11 0 +.names 602GAT(240) 666GAT(248) 690GAT(263) +11 0 +.names 602GAT(240) 672GAT(247) 694GAT(264) +11 0 +.names 700GAT(251) 701GAT(249) 721GAT(265) +11 0 +.names 704GAT(254) 705GAT(250) 727GAT(266) +11 0 +.names 702GAT(256) 703GAT(252) 724GAT(267) +11 0 +.names 698GAT(255) 699GAT(253) 718GAT(268) +11 0 +.names 692GAT(259) 693GAT(257) 709GAT(269) +11 0 +.names 696GAT(262) 697GAT(258) 715GAT(270) +11 0 +.names 694GAT(264) 695GAT(260) 712GAT(271) +11 0 +.names 690GAT(263) 691GAT(261) 706GAT(272) +11 0 +.names 263GAT(41) 715GAT(270) 751GAT(273) +11 0 +.names 260GAT(42) 712GAT(271) 748GAT(274) +11 0 +.names 257GAT(43) 709GAT(269) 745GAT(275) +11 0 +.names 254GAT(44) 706GAT(272) 742GAT(276) +11 0 +.names 251GAT(45) 727GAT(266) 739GAT(277) +11 0 +.names 248GAT(46) 724GAT(267) 736GAT(278) +11 0 +.names 245GAT(47) 721GAT(265) 733GAT(279) +11 0 +.names 242GAT(48) 718GAT(268) 730GAT(280) +11 0 +.names 263GAT(41) 751GAT(273) 768GAT(281) +11 0 +.names 260GAT(42) 748GAT(274) 766GAT(282) +11 0 +.names 257GAT(43) 745GAT(275) 764GAT(283) +11 0 +.names 254GAT(44) 742GAT(276) 762GAT(284) +11 0 +.names 251GAT(45) 739GAT(277) 760GAT(285) +11 0 +.names 248GAT(46) 736GAT(278) 758GAT(286) +11 0 +.names 245GAT(47) 733GAT(279) 756GAT(287) +11 0 +.names 242GAT(48) 730GAT(280) 754GAT(288) +11 0 +.names 721GAT(265) 733GAT(279) 757GAT(289) +11 0 +.names 727GAT(266) 739GAT(277) 761GAT(290) +11 0 +.names 724GAT(267) 736GAT(278) 759GAT(291) +11 0 +.names 718GAT(268) 730GAT(280) 755GAT(292) +11 0 +.names 709GAT(269) 745GAT(275) 765GAT(293) +11 0 +.names 715GAT(270) 751GAT(273) 769GAT(294) +11 0 +.names 712GAT(271) 748GAT(274) 767GAT(295) +11 0 +.names 706GAT(272) 742GAT(276) 763GAT(296) +11 0 +.names 768GAT(281) 769GAT(294) 791GAT(297) +11 0 +.names 766GAT(282) 767GAT(295) 788GAT(298) +11 0 +.names 764GAT(283) 765GAT(293) 785GAT(299) +11 0 +.names 762GAT(284) 763GAT(296) 782GAT(300) +11 0 +.names 760GAT(285) 761GAT(290) 779GAT(301) +11 0 +.names 758GAT(286) 759GAT(291) 776GAT(302) +11 0 +.names 756GAT(287) 757GAT(289) 773GAT(303) +11 0 +.names 754GAT(288) 755GAT(292) 770GAT(304) +11 0 +.names 663GAT(225) 791GAT(297) 815GAT(305) +11 0 +.names 660GAT(227) 788GAT(298) 812GAT(306) +11 0 +.names 657GAT(228) 785GAT(299) 809GAT(307) +11 0 +.names 654GAT(229) 782GAT(300) 806GAT(308) +11 0 +.names 651GAT(233) 779GAT(301) 803GAT(309) +11 0 +.names 648GAT(235) 776GAT(302) 800GAT(310) +11 0 +.names 645GAT(236) 773GAT(303) 797GAT(311) +11 0 +.names 642GAT(237) 770GAT(304) 794GAT(312) +11 0 +.names 791GAT(297) 815GAT(305) 833GAT(313) +11 0 +.names 788GAT(298) 812GAT(306) 831GAT(314) +11 0 +.names 785GAT(299) 809GAT(307) 829GAT(315) +11 0 +.names 782GAT(300) 806GAT(308) 827GAT(316) +11 0 +.names 779GAT(301) 803GAT(309) 825GAT(317) +11 0 +.names 776GAT(302) 800GAT(310) 823GAT(318) +11 0 +.names 773GAT(303) 797GAT(311) 821GAT(319) +11 0 +.names 770GAT(304) 794GAT(312) 819GAT(320) +11 0 +.names 663GAT(225) 815GAT(305) 832GAT(321) +11 0 +.names 660GAT(227) 812GAT(306) 830GAT(322) +11 0 +.names 657GAT(228) 809GAT(307) 828GAT(323) +11 0 +.names 654GAT(229) 806GAT(308) 826GAT(324) +11 0 +.names 651GAT(233) 803GAT(309) 824GAT(325) +11 0 +.names 648GAT(235) 800GAT(310) 822GAT(326) +11 0 +.names 645GAT(236) 797GAT(311) 820GAT(327) +11 0 +.names 642GAT(237) 794GAT(312) 818GAT(328) +11 0 +.names 832GAT(321) 833GAT(313) 899GAT(329) +11 0 +.names 830GAT(322) 831GAT(314) 912GAT(330) +11 0 +.names 828GAT(323) 829GAT(315) 886GAT(331) +11 0 +.names 826GAT(324) 827GAT(316) 925GAT(332) +11 0 +.names 824GAT(325) 825GAT(317) 873GAT(333) +11 0 +.names 822GAT(326) 823GAT(318) 860GAT(334) +11 0 +.names 820GAT(327) 821GAT(319) 847GAT(335) +11 0 +.names 818GAT(328) 819GAT(320) 834GAT(336) +11 0 +.names 899GAT(329) 951GAT(337) +1 0 +.names 899GAT(329) 955GAT(338) +1 0 +.names 899GAT(329) 963GAT(339) +1 0 +.names 899GAT(329) 966GAT(340) +1 0 +.names 899GAT(329) 969GAT(341) +1 0 +.names 912GAT(330) 953GAT(342) +1 0 +.names 912GAT(330) 957GAT(343) +1 0 +.names 912GAT(330) 960GAT(344) +1 0 +.names 912GAT(330) 965GAT(345) +1 0 +.names 912GAT(330) 968GAT(346) +1 0 +.names 886GAT(331) 950GAT(347) +1 0 +.names 886GAT(331) 952GAT(348) +1 0 +.names 886GAT(331) 959GAT(349) +1 0 +.names 886GAT(331) 962GAT(350) +1 0 +.names 886GAT(331) 967GAT(351) +1 0 +.names 925GAT(332) 954GAT(352) +1 0 +.names 925GAT(332) 956GAT(353) +1 0 +.names 925GAT(332) 958GAT(354) +1 0 +.names 925GAT(332) 961GAT(355) +1 0 +.names 925GAT(332) 964GAT(356) +1 0 +.names 873GAT(333) 943GAT(357) +1 0 +.names 873GAT(333) 946GAT(358) +1 0 +.names 873GAT(333) 949GAT(359) +1 0 +.names 873GAT(333) 971GAT(360) +1 0 +.names 873GAT(333) 975GAT(361) +1 0 +.names 860GAT(334) 940GAT(362) +1 0 +.names 860GAT(334) 945GAT(363) +1 0 +.names 860GAT(334) 948GAT(364) +1 0 +.names 860GAT(334) 973GAT(365) +1 0 +.names 860GAT(334) 977GAT(366) +1 0 +.names 847GAT(335) 939GAT(367) +1 0 +.names 847GAT(335) 942GAT(368) +1 0 +.names 847GAT(335) 947GAT(369) +1 0 +.names 847GAT(335) 970GAT(370) +1 0 +.names 847GAT(335) 972GAT(371) +1 0 +.names 834GAT(336) 938GAT(372) +1 0 +.names 834GAT(336) 941GAT(373) +1 0 +.names 834GAT(336) 944GAT(374) +1 0 +.names 834GAT(336) 974GAT(375) +1 0 +.names 834GAT(336) 976GAT(376) +1 0 +.names 958GAT(354) 959GAT(349) 960GAT(344) 899GAT(329) 982GAT(377) +1111 1 +.names 961GAT(355) 962GAT(350) 912GAT(330) 963GAT(339) 983GAT(378) +1111 1 +.names 964GAT(356) 886GAT(331) 965GAT(345) 966GAT(340) 984GAT(379) +1111 1 +.names 925GAT(332) 967GAT(351) 968GAT(346) 969GAT(341) 985GAT(380) +1111 1 +.names 938GAT(372) 939GAT(367) 940GAT(362) 873GAT(333) 978GAT(381) +1111 1 +.names 941GAT(373) 942GAT(368) 860GAT(334) 943GAT(357) 979GAT(382) +1111 1 +.names 944GAT(374) 847GAT(335) 945GAT(363) 946GAT(358) 980GAT(383) +1111 1 +.names 834GAT(336) 947GAT(369) 948GAT(364) 949GAT(359) 981GAT(384) +1111 1 +.names 982GAT(377) 983GAT(378) 984GAT(379) 985GAT(380) 991GAT(385) +0000 0 +.names 978GAT(381) 979GAT(382) 980GAT(383) 981GAT(384) 986GAT(386) +0000 0 +.names 925GAT(332) 952GAT(348) 953GAT(342) 899GAT(329) 986GAT(386) 1001GAT(387) +11111 1 +.names 956GAT(353) 886GAT(331) 957GAT(343) 899GAT(329) 986GAT(386) 1011GAT(388) +11111 1 +.names 925GAT(332) 950GAT(347) 912GAT(330) 951GAT(337) 986GAT(386) 996GAT(389) +11111 1 +.names 954GAT(352) 886GAT(331) 912GAT(330) 955GAT(338) 986GAT(386) 1006GAT(390) +11111 1 +.names 834GAT(336) 972GAT(371) 973GAT(365) 873GAT(333) 991GAT(385) 1021GAT(391) +11111 1 +.names 976GAT(376) 847GAT(335) 977GAT(366) 873GAT(333) 991GAT(385) 1031GAT(392) +11111 1 +.names 834GAT(336) 970GAT(370) 860GAT(334) 971GAT(360) 991GAT(385) 1016GAT(393) +11111 1 +.names 974GAT(375) 847GAT(335) 860GAT(334) 975GAT(361) 991GAT(385) 1026GAT(394) +11111 1 +.names 899GAT(329) 1016GAT(393) 1093GAT(395) +11 1 +.names 899GAT(329) 1021GAT(391) 1105GAT(396) +11 1 +.names 899GAT(329) 1026GAT(394) 1117GAT(397) +11 1 +.names 899GAT(329) 1031GAT(392) 1129GAT(398) +11 1 +.names 912GAT(330) 1016GAT(393) 1090GAT(399) +11 1 +.names 912GAT(330) 1021GAT(391) 1102GAT(400) +11 1 +.names 912GAT(330) 1026GAT(394) 1114GAT(401) +11 1 +.names 912GAT(330) 1031GAT(392) 1126GAT(402) +11 1 +.names 886GAT(331) 1016GAT(393) 1087GAT(403) +11 1 +.names 886GAT(331) 1021GAT(391) 1099GAT(404) +11 1 +.names 886GAT(331) 1026GAT(394) 1111GAT(405) +11 1 +.names 886GAT(331) 1031GAT(392) 1123GAT(406) +11 1 +.names 925GAT(332) 1016GAT(393) 1084GAT(407) +11 1 +.names 925GAT(332) 1021GAT(391) 1096GAT(408) +11 1 +.names 925GAT(332) 1026GAT(394) 1108GAT(409) +11 1 +.names 925GAT(332) 1031GAT(392) 1120GAT(410) +11 1 +.names 873GAT(333) 996GAT(389) 1045GAT(411) +11 1 +.names 873GAT(333) 1001GAT(387) 1057GAT(412) +11 1 +.names 873GAT(333) 1006GAT(390) 1069GAT(413) +11 1 +.names 873GAT(333) 1011GAT(388) 1081GAT(414) +11 1 +.names 860GAT(334) 996GAT(389) 1042GAT(415) +11 1 +.names 860GAT(334) 1001GAT(387) 1054GAT(416) +11 1 +.names 860GAT(334) 1006GAT(390) 1066GAT(417) +11 1 +.names 860GAT(334) 1011GAT(388) 1078GAT(418) +11 1 +.names 847GAT(335) 996GAT(389) 1039GAT(419) +11 1 +.names 847GAT(335) 1001GAT(387) 1051GAT(420) +11 1 +.names 847GAT(335) 1006GAT(390) 1063GAT(421) +11 1 +.names 847GAT(335) 1011GAT(388) 1075GAT(422) +11 1 +.names 834GAT(336) 996GAT(389) 1036GAT(423) +11 1 +.names 834GAT(336) 1001GAT(387) 1048GAT(424) +11 1 +.names 834GAT(336) 1006GAT(390) 1060GAT(425) +11 1 +.names 834GAT(336) 1011GAT(388) 1072GAT(426) +11 1 +.names 218GAT(31) 1129GAT(398) 1225GAT(427) +11 0 +.names 211GAT(30) 1126GAT(402) 1222GAT(428) +11 0 +.names 204GAT(29) 1123GAT(406) 1219GAT(429) +11 0 +.names 197GAT(28) 1120GAT(410) 1216GAT(430) +11 0 +.names 190GAT(27) 1117GAT(397) 1213GAT(431) +11 0 +.names 183GAT(26) 1114GAT(401) 1210GAT(432) +11 0 +.names 176GAT(25) 1111GAT(405) 1207GAT(433) +11 0 +.names 169GAT(24) 1108GAT(409) 1204GAT(434) +11 0 +.names 162GAT(23) 1105GAT(396) 1201GAT(435) +11 0 +.names 155GAT(22) 1102GAT(400) 1198GAT(436) +11 0 +.names 148GAT(21) 1099GAT(404) 1195GAT(437) +11 0 +.names 141GAT(20) 1096GAT(408) 1192GAT(438) +11 0 +.names 134GAT(19) 1093GAT(395) 1189GAT(439) +11 0 +.names 127GAT(18) 1090GAT(399) 1186GAT(440) +11 0 +.names 120GAT(17) 1087GAT(403) 1183GAT(441) +11 0 +.names 113GAT(16) 1084GAT(407) 1180GAT(442) +11 0 +.names 106GAT(15) 1081GAT(414) 1177GAT(443) +11 0 +.names 99GAT(14) 1078GAT(418) 1174GAT(444) +11 0 +.names 92GAT(13) 1075GAT(422) 1171GAT(445) +11 0 +.names 85GAT(12) 1072GAT(426) 1168GAT(446) +11 0 +.names 78GAT(11) 1069GAT(413) 1165GAT(447) +11 0 +.names 71GAT(10) 1066GAT(417) 1162GAT(448) +11 0 +.names 64GAT(9) 1063GAT(421) 1159GAT(449) +11 0 +.names 57GAT(8) 1060GAT(425) 1156GAT(450) +11 0 +.names 50GAT(7) 1057GAT(412) 1153GAT(451) +11 0 +.names 43GAT(6) 1054GAT(416) 1150GAT(452) +11 0 +.names 36GAT(5) 1051GAT(420) 1147GAT(453) +11 0 +.names 29GAT(4) 1048GAT(424) 1144GAT(454) +11 0 +.names 22GAT(3) 1045GAT(411) 1141GAT(455) +11 0 +.names 15GAT(2) 1042GAT(415) 1138GAT(456) +11 0 +.names 8GAT(1) 1039GAT(419) 1135GAT(457) +11 0 +.names 1GAT(0) 1036GAT(423) 1132GAT(458) +11 0 +.names 1093GAT(395) 1189GAT(439) 1267GAT(459) +11 0 +.names 1105GAT(396) 1201GAT(435) 1275GAT(460) +11 0 +.names 1117GAT(397) 1213GAT(431) 1283GAT(461) +11 0 +.names 1129GAT(398) 1225GAT(427) 1291GAT(462) +11 0 +.names 1090GAT(399) 1186GAT(440) 1265GAT(463) +11 0 +.names 1102GAT(400) 1198GAT(436) 1273GAT(464) +11 0 +.names 1114GAT(401) 1210GAT(432) 1281GAT(465) +11 0 +.names 1126GAT(402) 1222GAT(428) 1289GAT(466) +11 0 +.names 1087GAT(403) 1183GAT(441) 1263GAT(467) +11 0 +.names 1099GAT(404) 1195GAT(437) 1271GAT(468) +11 0 +.names 1111GAT(405) 1207GAT(433) 1279GAT(469) +11 0 +.names 1123GAT(406) 1219GAT(429) 1287GAT(470) +11 0 +.names 1084GAT(407) 1180GAT(442) 1261GAT(471) +11 0 +.names 1096GAT(408) 1192GAT(438) 1269GAT(472) +11 0 +.names 1108GAT(409) 1204GAT(434) 1277GAT(473) +11 0 +.names 1120GAT(410) 1216GAT(430) 1285GAT(474) +11 0 +.names 1045GAT(411) 1141GAT(455) 1235GAT(475) +11 0 +.names 1057GAT(412) 1153GAT(451) 1243GAT(476) +11 0 +.names 1069GAT(413) 1165GAT(447) 1251GAT(477) +11 0 +.names 1081GAT(414) 1177GAT(443) 1259GAT(478) +11 0 +.names 1042GAT(415) 1138GAT(456) 1233GAT(479) +11 0 +.names 1054GAT(416) 1150GAT(452) 1241GAT(480) +11 0 +.names 1066GAT(417) 1162GAT(448) 1249GAT(481) +11 0 +.names 1078GAT(418) 1174GAT(444) 1257GAT(482) +11 0 +.names 1039GAT(419) 1135GAT(457) 1231GAT(483) +11 0 +.names 1051GAT(420) 1147GAT(453) 1239GAT(484) +11 0 +.names 1063GAT(421) 1159GAT(449) 1247GAT(485) +11 0 +.names 1075GAT(422) 1171GAT(445) 1255GAT(486) +11 0 +.names 1036GAT(423) 1132GAT(458) 1229GAT(487) +11 0 +.names 1048GAT(424) 1144GAT(454) 1237GAT(488) +11 0 +.names 1060GAT(425) 1156GAT(450) 1245GAT(489) +11 0 +.names 1072GAT(426) 1168GAT(446) 1253GAT(490) +11 0 +.names 218GAT(31) 1225GAT(427) 1290GAT(491) +11 0 +.names 211GAT(30) 1222GAT(428) 1288GAT(492) +11 0 +.names 204GAT(29) 1219GAT(429) 1286GAT(493) +11 0 +.names 197GAT(28) 1216GAT(430) 1284GAT(494) +11 0 +.names 190GAT(27) 1213GAT(431) 1282GAT(495) +11 0 +.names 183GAT(26) 1210GAT(432) 1280GAT(496) +11 0 +.names 176GAT(25) 1207GAT(433) 1278GAT(497) +11 0 +.names 169GAT(24) 1204GAT(434) 1276GAT(498) +11 0 +.names 162GAT(23) 1201GAT(435) 1274GAT(499) +11 0 +.names 155GAT(22) 1198GAT(436) 1272GAT(500) +11 0 +.names 148GAT(21) 1195GAT(437) 1270GAT(501) +11 0 +.names 141GAT(20) 1192GAT(438) 1268GAT(502) +11 0 +.names 134GAT(19) 1189GAT(439) 1266GAT(503) +11 0 +.names 127GAT(18) 1186GAT(440) 1264GAT(504) +11 0 +.names 120GAT(17) 1183GAT(441) 1262GAT(505) +11 0 +.names 113GAT(16) 1180GAT(442) 1260GAT(506) +11 0 +.names 106GAT(15) 1177GAT(443) 1258GAT(507) +11 0 +.names 99GAT(14) 1174GAT(444) 1256GAT(508) +11 0 +.names 92GAT(13) 1171GAT(445) 1254GAT(509) +11 0 +.names 85GAT(12) 1168GAT(446) 1252GAT(510) +11 0 +.names 78GAT(11) 1165GAT(447) 1250GAT(511) +11 0 +.names 71GAT(10) 1162GAT(448) 1248GAT(512) +11 0 +.names 64GAT(9) 1159GAT(449) 1246GAT(513) +11 0 +.names 57GAT(8) 1156GAT(450) 1244GAT(514) +11 0 +.names 50GAT(7) 1153GAT(451) 1242GAT(515) +11 0 +.names 43GAT(6) 1150GAT(452) 1240GAT(516) +11 0 +.names 36GAT(5) 1147GAT(453) 1238GAT(517) +11 0 +.names 29GAT(4) 1144GAT(454) 1236GAT(518) +11 0 +.names 22GAT(3) 1141GAT(455) 1234GAT(519) +11 0 +.names 15GAT(2) 1138GAT(456) 1232GAT(520) +11 0 +.names 8GAT(1) 1135GAT(457) 1230GAT(521) +11 0 +.names 1GAT(0) 1132GAT(458) 1228GAT(522) +11 0 +.names 1266GAT(503) 1267GAT(459) 1311GAT(523) +11 0 +.names 1274GAT(499) 1275GAT(460) 1315GAT(524) +11 0 +.names 1282GAT(495) 1283GAT(461) 1319GAT(525) +11 0 +.names 1290GAT(491) 1291GAT(462) 1323GAT(526) +11 0 +.names 1264GAT(504) 1265GAT(463) 1310GAT(527) +11 0 +.names 1272GAT(500) 1273GAT(464) 1314GAT(528) +11 0 +.names 1280GAT(496) 1281GAT(465) 1318GAT(529) +11 0 +.names 1288GAT(492) 1289GAT(466) 1322GAT(530) +11 0 +.names 1262GAT(505) 1263GAT(467) 1309GAT(531) +11 0 +.names 1270GAT(501) 1271GAT(468) 1313GAT(532) +11 0 +.names 1278GAT(497) 1279GAT(469) 1317GAT(533) +11 0 +.names 1286GAT(493) 1287GAT(470) 1321GAT(534) +11 0 +.names 1260GAT(506) 1261GAT(471) 1308GAT(535) +11 0 +.names 1268GAT(502) 1269GAT(472) 1312GAT(536) +11 0 +.names 1276GAT(498) 1277GAT(473) 1316GAT(537) +11 0 +.names 1284GAT(494) 1285GAT(474) 1320GAT(538) +11 0 +.names 1234GAT(519) 1235GAT(475) 1295GAT(539) +11 0 +.names 1242GAT(515) 1243GAT(476) 1299GAT(540) +11 0 +.names 1250GAT(511) 1251GAT(477) 1303GAT(541) +11 0 +.names 1258GAT(507) 1259GAT(478) 1307GAT(542) +11 0 +.names 1232GAT(520) 1233GAT(479) 1294GAT(543) +11 0 +.names 1240GAT(516) 1241GAT(480) 1298GAT(544) +11 0 +.names 1248GAT(512) 1249GAT(481) 1302GAT(545) +11 0 +.names 1256GAT(508) 1257GAT(482) 1306GAT(546) +11 0 +.names 1230GAT(521) 1231GAT(483) 1293GAT(547) +11 0 +.names 1238GAT(517) 1239GAT(484) 1297GAT(548) +11 0 +.names 1246GAT(513) 1247GAT(485) 1301GAT(549) +11 0 +.names 1254GAT(509) 1255GAT(486) 1305GAT(550) +11 0 +.names 1228GAT(522) 1229GAT(487) 1292GAT(551) +11 0 +.names 1236GAT(518) 1237GAT(488) 1296GAT(552) +11 0 +.names 1244GAT(514) 1245GAT(489) 1300GAT(553) +11 0 +.names 1252GAT(510) 1253GAT(490) 1304GAT(554) +11 0 +.names 1311GAT(523) 1343GAT(555) +1 1 +.names 1315GAT(524) 1347GAT(556) +1 1 +.names 1319GAT(525) 1351GAT(557) +1 1 +.names 1323GAT(526) 1355GAT(558) +1 1 +.names 1310GAT(527) 1342GAT(559) +1 1 +.names 1314GAT(528) 1346GAT(560) +1 1 +.names 1318GAT(529) 1350GAT(561) +1 1 +.names 1322GAT(530) 1354GAT(562) +1 1 +.names 1309GAT(531) 1341GAT(563) +1 1 +.names 1313GAT(532) 1345GAT(564) +1 1 +.names 1317GAT(533) 1349GAT(565) +1 1 +.names 1321GAT(534) 1353GAT(566) +1 1 +.names 1308GAT(535) 1340GAT(567) +1 1 +.names 1312GAT(536) 1344GAT(568) +1 1 +.names 1316GAT(537) 1348GAT(569) +1 1 +.names 1320GAT(538) 1352GAT(570) +1 1 +.names 1295GAT(539) 1327GAT(571) +1 1 +.names 1299GAT(540) 1331GAT(572) +1 1 +.names 1303GAT(541) 1335GAT(573) +1 1 +.names 1307GAT(542) 1339GAT(574) +1 1 +.names 1294GAT(543) 1326GAT(575) +1 1 +.names 1298GAT(544) 1330GAT(576) +1 1 +.names 1302GAT(545) 1334GAT(577) +1 1 +.names 1306GAT(546) 1338GAT(578) +1 1 +.names 1293GAT(547) 1325GAT(579) +1 1 +.names 1297GAT(548) 1329GAT(580) +1 1 +.names 1301GAT(549) 1333GAT(581) +1 1 +.names 1305GAT(550) 1337GAT(582) +1 1 +.names 1292GAT(551) 1324GAT(583) +1 1 +.names 1296GAT(552) 1328GAT(584) +1 1 +.names 1300GAT(553) 1332GAT(585) +1 1 +.names 1304GAT(554) 1336GAT(586) +1 1 +.end diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/alu2.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/alu2.blif new file mode 100644 index 000000000..f3a83d3fe --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/alu2.blif @@ -0,0 +1,263 @@ +.model alu4_cl +.inputs a b c d e f g h i j +.outputs k l m n o p +.names j d0 f0 i h m1 n1 c e f o1 l1 g z0 p1 q1 h0 r1 s1 c1 d1 f1 v0 k +1-11------------------- 1 +1-00------------------- 1 +11--0------------------ 1 +0---1-1---------------- 1 +0----1-10-------------- 1 +0-------001------------ 1 +0---1----0-----1------- 1 +0---1----0------1------ 1 +0---1----0-------1----- 1 +0------1-1----------1-- 1 +0---1----1-----------1- 1 +0--------1------1----1- 1 +0---1----0-11---------- 1 +0---1----0---11-------- 1 +0-------01--------01--- 1 +0-------11--1---------1 1 +0---0--010--1---------- 1 +0---0---10-00---------- 1 +.names j d0 e0 f0 i h y0 b d f g h0 w0 z0 a1 b1 j0 e u0 c1 p0 d1 n l +1-10------------------- 1 +1-1-1------------------ 1 +11---0----------------- 1 +0-----1-1-------------- 1 +0-----1--0------------- 1 +1-010------------------ 1 +0----1-1--1------------ 1 +0----1---0-1----------- 1 +0--------0-10---------- 1 +0----1---0----1-------- 1 +0----1---0------1------ 1 +0-------11-----------1- 1 +0----1---1------------1 1 +0--------1-1----------1 1 +0----1---01-1---------- 1 +0----1---0---1-1------- 1 +0--------11------11---- 1 +0--------1-------0-10-- 1 +0----0--001------1----- 1 +0----0---00-0----1----- 1 +.names p0 n m +0- 1 +-1 1 +.names b d n +11 1 +.names j c0 d0 e0 f0 i h g0 h0 i0 f j0 k0 l0 e m0 n0 o0 p0 q0 r0 n a b g s0 t0 \ +u0 v0 w0 x0 o +111---------------------------- 1 +1-1---0------------------------ 1 +1-----0--1--------------------- 1 +1--110------------------------- 1 +1-----1--------1--1------------ 1 +1-----1-------------11--------- 1 +1-----1----------1---------1--- 1 +11----0-1-1-------------------- 1 +1-----01---1-1----------------- 1 +1-----1------------1--00------- 1 +1-----1----------1-----1----1-- 1 +1-----1----------1----------11- 1 +1-----01----110---------------- 1 +1-----01----1-0--------1------- 1 +1-----1-----1---1-------01----- 1 +1-----1-----1---1-------0-1---- 1 +1-----1---------1-------011---- 1 +1-----01------1----------1---1- 1 +1-----01------1----------1----1 1 +1-----01------1--------------11 1 +.names m f1 s1 p +11- 1 +1-0 1 +.names w0 l1 c0 +00 1 +.names g h1 d0 +01 1 +.names j m0 e1 j0 r0 n f1 f g h n0 g1 h1 w0 b d i1 c0 i0 j1 k1 k0 l1 o0 p0 s0 \ +m1 n1 a b1 a1 x0 t0 e0 +11---1--------------------------- 1 +1---1----0-----1----------------- 1 +1-------10--------1-------------- 1 +11-------1--------------0-------- 1 +1---1-0----------------------1--- 1 +1---1-0-----------------------1-- 1 +1-11---00------------------------ 1 +1--1---0-0-0--------------------- 1 +1-------001--1------------------- 1 +1-------00--0-1------------------ 1 +1-------101------1--------------- 1 +1-------01--1----1--------------- 1 +1--------01--1--------1---------- 1 +1-1------1----1--------1--------- 1 +1-0------1----0--------1--------- 1 +1--------1--11------------1------ 1 +1--------1--1-1------------1----- 1 +1-------10-1--0-1---------------- 1 +1-------10--1-------11----------- 1 +1-------11--1-0-------------0---- 1 +1-------10---1-----1-----1-----1- 1 +1-------10---0-----1-----0-----1- 1 +1-------10---0-----1-----1-----0- 1 +1-------10---1-----1-----0-----0- 1 +1-------011----------1---1------1 1 +1-------011----------0---0------1 1 +1-------011----------0---1------0 1 +1-------011----------1---0------0 1 +.names j f g h n1 h1 l1 a n0 q0 g0 o1 k1 e r1 q1 p1 t1 i1 f0 +1--1---0-1--------- 1 +1--0----1--1------- 1 +1--0-----1--0------ 1 +1-01-10------------ 1 +1--1100------------ 1 +1-00-0-1----------- 1 +1-11--10----------- 1 +100---0-------1---- 1 +10-0--------0-1---- 1 +100----------1-1--- 1 +100----------1--1-- 1 +1--1--10----------1 1 +1--0---0--1-10----- 1 +1-01----1---0----1- 1 +1--0--0---1--1---1- 1 +1-01----1---1----0- 1 +1--0--1---1--1---0- 1 +.names f g g0 +01 1 +.names e g h0 +01 1 +.names k0 k1 h1 i0 +001 1 +.names b e j0 +10 1 +.names u1 w1 u0 w0 h1 j1 i1 n b k0 +1--1----- 1 +1-------1 1 +-11-1---- 1 +-1-0--1-- 1 +-1---1-1- 1 +.names a k1 l0 +11 1 +.names r0 f1 m0 +11 1 +.names e f n0 +01 1 +.names g0 h0 i1 o0 +1-- 1 +-1- 1 +--1 1 +.names b d p0 +1- 1 +-1 1 +.names g h1 q0 +11 1 +.names f z0 r0 +01 1 +.names k0 u1 v1 w1 j1 s0 +-11-- 1 +0--11 1 +.names t1 k1 t0 +11 1 +.names b w0 u0 +11 1 +.names a l1 v0 +11 1 +.names x1 y1 z1 p0 v1 a2 j1 d j e h b2 b c2 p1 n f n1 a1 b1 w0 +--1----0------------ 1 +1-------1----------- 1 +1--------0---------- 1 +-1-1--1------------- 1 +---------0-10------- 1 +----11---11--------- 1 +--------10---111---- 1 +---0----10----1-1--- 1 +----1---101-----0--- 1 +--------101-----01-- 1 +--------10----0-1-1- 1 +--------10---10-1--1 1 +.names t1 l1 x0 +11 1 +.names e g w0 y0 +001 1 +.names e g z0 +10 1 +.names b d a1 +10 1 +.names b d b1 +01 1 +.names g h c1 +10 1 +.names e h d1 +01 1 +.names w0 v0 e1 +11 1 +00 1 +.names a c f1 +11 1 +.names k0 l0 g1 +01 1 +10 1 +.names e f h1 +11 1 +.names e f i1 +00 1 +.names e f j1 +10 1 +.names u1 w1 l1 v0 h1 j1 f1 i1 a k1 +1-1------ 1 +1-------1 1 +-1-11---- 1 +-1---11-- 1 +-10----1- 1 +.names s1 y1 z1 j1 f1 c j e g h b2 c1 a2 q1 a h1 i1 p1 f l1 +--1--0------------- 1 +11-1--------------- 1 +-------0----11----- 1 +-------0--1---0---- 1 +-------0---11----1- 1 +----1--0---1------0 1 +----1-1-01-----1--- 1 +----1-1-01------1-- 1 +.names g l1 m1 +01 1 +.names a g n1 +11 1 +.names g m1 l1 o1 +-1- 1 +1-0 1 +.names a c p1 +01 1 +.names a c q1 +10 1 +.names a e r1 +10 1 +.names a c s1 +1- 1 +-1 1 +.names k1 u1 w1 j1 g f1 t1 +0-11-- 1 +-1--01 1 +.names a2 d1 u1 +11 1 +.names g n v1 +01 1 +.names j c1 w1 +11 1 +.names n f c2 x1 +101 1 +.names g h j y1 +1-1 1 +000 1 +.names e j h1 g0 a2 c1 h z1 +--1--1- 1 +0---10- 1 +10-1--1 1 +.names f j a2 +11 1 +.names j g f h b2 +000- 1 +00-0 1 +.names g h c2 +10 1 +.end diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/alu4.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/alu4.blif new file mode 100644 index 000000000..f20f491ba --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/alu4.blif @@ -0,0 +1,502 @@ +.model alu4_cl +.inputs a b c d e f g h i j k l m n +.outputs o p q r s t u v +.names j1 n g3 m k1 h3 m1 i3 e j n1 j3 o1 p1 q1 k3 l3 l s1 t1 r1 u1 m3 n3 o +1----------------------- 1 +-111-------------------- 1 +-100-------------------- 1 +-0--11------------------ 1 +-0----111--------------- 1 +-0------11---1---------- 1 +-0-------1-1--1--------- 1 +-0-------11----1-------- 1 +-0-------1--1---1------- 1 +-0-----0-0--------1----- 1 +-0-----1-0----------1--- 1 +-0------00-----------1-- 1 +-0-------0-------1----1- 1 +-0-------0---------1---1 1 +.names j1 n k2 l2 k1 m1 m2 b f j l s1 t1 r1 u1 n2 o2 n1 o1 p1 q1 p2 q2 p +1---------------------- 1 +-111------------------- 1 +-100------------------- 1 +-0---11-1-------------- 1 +-0--1--1--1------------ 1 +-0----0--0-1----------- 1 +-0----1--0---1--------- 1 +-0------00----1-------- 1 +-0-------01----1------- 1 +-0-------0--1---1------ 1 +-0------11---------1--- 1 +-0-------1----------11- 1 +-0-------1-------1----1 1 +-0----11-1--------1---- 1 +.names j1 n v1 w1 k1 x1 m1 y1 g j n1 z1 a2 o1 p1 q1 c r1 s1 t1 u1 q +1-------------------- 1 +-111----------------- 1 +-100----------------- 1 +-0--11--------------- 1 +-0----111------------ 1 +-0---1--00----------- 1 +-0-------11-1-------- 1 +-0------11----1------ 1 +-0-------1-0---1----- 1 +-0-----1-0-------1--- 1 +-0-----0-0--------1-- 1 +-0------00----------1 1 +-0-----1-1---1--1---- 1 +-0------10------0--1- 1 +.names j1 n m0 p0 k1 l1 m1 h1 h j n1 o1 p1 q1 b1 d1 t r1 s1 t1 d u1 r +1--------------------- 1 +-111------------------ 1 +-100------------------ 1 +-0--11---------------- 1 +-0----111------------- 1 +-0---1--00------------ 1 +-0------11--1--------- 1 +-0-------1-1--1------- 1 +-0-------1---1-1------ 1 +-0-------11-----1----- 1 +-0-----1-0-------1---- 1 +-0-----0-0--------1--- 1 +-0------00-----------1 1 +-0------10---------10- 1 +.names t d1 s +1- 1 +-1 1 +.names d h t +11 1 +.names n m0 n0 o0 p0 l q0 r0 s0 t0 u0 k i v0 w0 x0 y0 d z0 a1 b1 c1 d1 t e1 f1 \ +g1 h1 i1 u +1-11------------------------- 1 +10--1------------------------ 1 +1--1-0----------------------- 1 +1----1--------1--------1----- 1 +1----1--------------1----1--- 1 +1----01--01------------------ 1 +1-1--0-1---1----------------- 1 +1----1-------1--10----------- 1 +1----1---1-----1--1---------- 1 +1----1---1-----1---1--------- 1 +1----1---------1--11--------- 1 +1----10----1--------1-------- 1 +1----1--------1-------0-1---- 1 +1----1-----------1---1---1--- 1 +1----1---------------1---1-1- 1 +1----0--11--0----1----------- 1 +1----10----1-----1---1------- 1 +1----0--11--0-------------1-- 1 +1----0--1---0----1--------1-- 1 +1----0--1---1-----1--------1- 1 +1----10----1---------1-----1- 1 +1----0--1---1-----1---------1 1 +1----0--1---1--------------11 1 +.names s e f a2 d3 y0 g j3 q2 k3 p2 z1 v +1--1---11--- 1 +1--1----11-- 1 +1--1-----11- 1 +1------11--0 1 +1-------11-0 1 +1--------110 1 +10011------- 1 +100--10----- 1 +.names v1 w1 m0 +1- 1 +-0 1 +.names h1 e2 n0 +01 1 +.names k q0 o0 +01 1 +.names n b2 c2 v0 n0 l1 d2 w0 x0 h1 e2 y0 d i l z0 t0 a1 f2 g2 e1 h g1 f1 u0 \ +h2 i1 i2 j2 d1 t p0 +11--1-------------------------- 1 +1-----------1---------------1-- 1 +1-1------10-------------------- 1 +1--1-1-----0------------------- 1 +1-------11----0---------------- 1 +1-----------0-----11----------- 1 +1------1------0------1--------- 1 +1-----------1-----0--------1--- 1 +1------1------------1---------1 1 +1--1-------10-1---------------- 1 +1------1----0-------01--------- 1 +1------1----1-------00--------- 1 +1--1----------0-0-------1------ 1 +1--1----------0-1-------0------ 1 +1-----1------1-----------01---- 1 +1-----1------1-----------10---- 1 +1------1------1-----1--------1- 1 +1-------1-----1111------------- 1 +1-------1-----1001------------- 1 +1-------1-----1010------------- 1 +1-------1-----1100------------- 1 +1-----1-----00--0-----1-------- 1 +1-----1-----00--1-----0-------- 1 +1-----------1-0-1-----11------- 1 +1-----------1-0-0-----01------- 1 +.names i j q0 +11 1 +.names i j r0 +01 1 +.names j k s0 +01 1 +.names b4 c4 b1 h1 t f1 q0 v3 d t0 +-1-1----- 1 +-1------1 1 +1--0-1--- 1 +1-1---1-- 1 +1---1--1- 1 +.names e3 v2 u0 +10 1 +.names k q0 v0 +11 1 +.names j x2 w0 +01 1 +.names j m1 x0 +11 1 +.names c d3 y0 +01 1 +.names t0 y3 z3 t z0 +0-1- 1 +-1-1 1 +.names v2 u2 w2 a1 +11- 1 +1-1 1 +-11 1 +.names d h1 b1 +11 1 +.names y1 b3 c c1 +11- 1 +1-1 1 +-11 1 +.names d h d1 +00 1 +.names t2 z1 a2 e1 +--1 1 +11- 1 +.names i j f1 +00 1 +.names v2 x3 c g1 +11- 1 +1-1 1 +-11 1 +.names d4 d1 e4 t h n i d2 d k f4 g4 u3 x1 s0 j l h1 +-01-------------- 1 +1---0------------ 1 +---1-1-1--------- 1 +---1--01--------- 1 +---1-1----1------ 1 +-----10------11-- 1 +---1-10----01---- 1 +-1---10----0---1- 1 +-----00-00-----0- 1 +-----00-00------0 1 +----010-1--1---1- 1 +----110-0--11--1- 1 +.names y1 u2 z2 i1 +11- 1 +1-1 1 +-11 1 +.names n p1 s0 l4 q0 j1 +011-- 1 +1--11 1 +.names k f1 k1 +1- 1 +-1 1 +.names d l l1 +11 1 +.names i k m1 +00 1 +.names l c3 n1 +1- 1 +-1 1 +.names i k o1 +11 1 +.names i l p1 +01 1 +.names i u3 q1 +01 1 +.names k l m1 r1 +--1 1 +11- 1 +.names i c3 l4 s1 +-1- 1 +1-1 1 +.names l x2 t1 +11 1 +.names i u3 u1 +11 1 +.names k2 l2 v1 +1- 1 +-0 1 +.names n b2 v0 r2 w0 s2 y1 t2 e2 c u2 v2 w2 o1 x2 g y2 z2 i2 a3 j2 i b3 g2 c3 \ +x1 d3 y0 l e3 u0 c2 x0 f3 z1 a2 w1 +11------1--------------------------- 1 +1--------1----------1--------------- 1 +1--1----------11-------------------- 1 +1-1----------------------10--------- 1 +1-1------------------------11------- 1 +1-1-------------------------0-1----- 1 +1-----1---------------------0---1--- 1 +1-----1------------------------1-0-- 1 +1---1--1---------------------------1 1 +1----1----111----------------------- 1 +1----1----001----------------------- 1 +1----1----010----------------------- 1 +1----1----100----------------------- 1 +1---1--0-0-----1-------------------- 1 +1---1--0-1-----0-------------------- 1 +1--1---------1--11------------------ 1 +1--1---------1--00------------------ 1 +1--1-----1---------0-0-------------- 1 +1-----1--1--------1---1------------- 1 +1-----0--1--------1---0------------- 1 +1-----0--0------------11------------ 1 +1-----1--0------------01------------ 1 +1--1-----0---------1----1----------- 1 +1-1--------1----------------00------ 1 +1---1--1--------------------1-----0- 1 +.names c l x1 +11 1 +.names d4 h4 z1 a2 e4 i4 c g n i u3 s0 j4 b j l y1 +-1-1------------ 1 +--1-1----------- 1 +-----10--------- 1 +1------0-------- 1 +--------10-1-1-1 1 +------11101-1--- 1 +------0010--1-1- 1 +------1010--0-1- 1 +------01101-0-1- 1 +.names c g z1 +1- 1 +-1 1 +.names c g a2 +11 1 +.names j q1 l o0 b2 +11-- 1 +--11 1 +.names l r0 o0 c2 +01- 1 +1-1 1 +.names j u3 d2 +01 1 +.names f3 y1 e2 +10 1 +.names c1 h1 f2 +01 1 +10 1 +.names l f1 k q0 g2 +11-- 1 +1-10 1 +.names z0 h1 h2 +01 1 +10 1 +.names k g2 f1 i2 +-1- 1 +0-1 1 +.names l4 q0 j2 +10 1 +.names m g3 k2 +1- 1 +-0 1 +.names n b2 v0 g2 r2 w0 s2 m2 l3 f3 b o3 o1 x2 c3 f i p3 d3 l q3 r3 e3 s3 t3 \ +i2 j2 h3 k3 c2 x0 i3 o2 p2 q2 l2 +11-------1------------------------- 1 +1---------1---------------1-------- 1 +1---1--------1-1------------------- 1 +1-1---------------11--------------- 1 +1-1----------------0--1------------ 1 +1-1-------1----------------1------- 1 +1------1-----------0----------1---- 1 +1------1---------------------1-1--- 1 +1----1----------------------0---1-- 1 +1----1----------------------1-----1 1 +1--1---01-0------------------------ 1 +1--1---10-0------------------------ 1 +1---1-----01--1-------------------- 1 +1---1-----10----0------------------ 1 +1-1----------------011------------- 1 +1-----1--------------1-11---------- 1 +1-----1--------------0-01---------- 1 +1-----1--------------0-10---------- 1 +1-----1--------------1-00---------- 1 +1------11-1--------------1--------- 1 +1------00-1--------------1--------- 1 +1----1----1----0------------0------ 1 +1----1-------------1--------1----1- 1 +1---1--1----1----1-----1----------- 1 +1---1--0----1----0-----1----------- 1 +1---1--0----1----1-----0----------- 1 +1---1--1----1----0-----0----------- 1 +.names d4 h4 p2 e4 q2 i4 b f n i u3 s0 h3 n3 j n2 o2 m2 +--01------------- 1 +-1--1------------ 1 +-----10---------- 1 +1------0--------- 1 +--------10-11---- 1 +----1---101--1--- 1 +--1-----10---11-- 1 +--------10---011- 1 +--------101--01-1 1 +.names b f n2 +10 1 +.names b f o2 +01 1 +.names b f p2 +00 1 +.names b f q2 +11 1 +.names j l r2 +00 1 +.names k j p1 s2 +011 1 +.names q2 k3 p2 t2 +1-- 1 +-10 1 +.names v2 y3 z3 a2 u2 +0-1- 1 +-1-1 1 +.names b4 c4 f1 y1 c i g j v2 +-1-1---- 1 +-1--1--- 1 +1-10---- 1 +1--111-1 1 +1---1110 1 +.names r3 s3 t3 w2 +11- 1 +1-1 1 +-11 1 +.names i k x2 +10 1 +.names u2 y1 y2 +11 1 +00 1 +.names m2 s3 p3 z2 +11- 1 +1-1 1 +-11 1 +.names x3 v2 a3 +01 1 +10 1 +.names m2 l3 b b3 +11- 1 +1-1 1 +-11 1 +.names i k c3 +01 1 +.names a b d3 +00 1 +.names r3 q3 e3 +00 1 +.names m2 i3 f3 +00 1 +.names n b2 u3 q0 v3 r2 m1 i3 q3 k l x2 a e i x0 w3 k1 v0 j m3 n3 g3 +11-----0-------------- 1 +1-11----0------------- 1 +1-----1---0-1--------- 1 +1----1-----1-1-------- 1 +1---------1-0-----1--- 1 +1---1----0----------1- 1 +1---1----0-----------1 1 +1----1--0---1-0------- 1 +1-------0-1----11----- 1 +1-------1-1----10----- 1 +1------1--1-0----1---- 1 +1-----11--0--------1-- 1 +1-----10----1------0-- 1 +1--0---0-11-1--------- 1 +1----1--11--0-0------- 1 +1----1-0-1----1-1----- 1 +1----1-1-1----1-0----- 1 +.names a l h3 +11 1 +.names d4 k4 j3 r0 e4 i4 k3 a e n m3 u3 n3 i3 +--0-1-------- 1 +-1----1------ 1 +-----1-0----- 1 +1-------0---- 1 +---1-----11-- 1 +---1-----1-11 1 +.names a e j3 +00 1 +.names a e k3 +11 1 +.names a i3 l3 +11 1 +.names a e m3 +10 1 +.names a e n3 +01 1 +.names r3 a4 o3 +01 1 +10 1 +.names w3 i3 p3 +11 1 +.names b4 c4 i3 l3 k3 f1 q0 v3 a q3 +-11------ 1 +-1------1 1 +1-0--1--- 1 +1--1--1-- 1 +1---1--1- 1 +.names b4 c4 f1 m2 b i f j r3 +-1-1---- 1 +-1--1--- 1 +1-10---- 1 +1--111-1 1 +1---1110 1 +.names r3 y3 z3 q2 s3 +0-1- 1 +-1-1 1 +.names w3 q3 t3 +11 1 +.names k l u3 +10 1 +.names i j v3 +10 1 +.names q3 y3 z3 k3 w3 +0-1- 1 +-1-1 1 +.names r3 a4 b x3 +11- 1 +1-1 1 +-11 1 +.names k c4 y3 +01 1 +.names j n u1 z3 +011 1 +.names a q3 a4 +11 1 +.names n u3 b4 +11 1 +.names n j p1 c4 +111 1 +.names j l n u3 o1 q0 r0 d4 +---1-1- 1 +--10--1 1 +010-1-- 1 +.names v3 k n l4 e4 +111- 1 +1-01 1 +.names k l f1 q0 f4 +011- 1 +01-1 1 +.names j4 c g g4 +01- 1 +0-0 1 +-10 1 +.names n k4 d2 h4 +-1- 1 +1-1 1 +.names m1 n j l i4 +100- 1 +10-0 1 +.names n2 o2 n3 j4 +-1- 1 +0-1 1 +.names j n f4 q1 k4 +-11- 1 +0--1 1 +.names k l l4 +00 1 +.end diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/apex7.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/apex7.blif new file mode 100644 index 000000000..db4f107dc --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/apex7.blif @@ -0,0 +1,220 @@ +.model apex7 +.inputs CAPSD CAT0 CAT1 CAT2 CAT3 CAT4 CAT5 VACC MMERR IBT0 IBT1 IBT2 \ +ICLR LSD ACCRPY VERR_N RATR MARSSR VLENESR VSUMESR PLUTO0 PLUTO1 PLUTO2 \ +PLUTO3 PLUTO4 PLUTO5 ORWD_N OWL_N PY END FBI WATCH OVACC KBG_N DEL1 \ +COMPPAR VST0 VST1 STAR0 STAR1 STAR2 STAR3 BULL0 BULL1 BULL2 BULL3 \ +BULL4 BULL5 BULL6 +.outputs SDO LSD_P ACCRPY_P VERR_F RATR_P MARSSR_P VLENESR_P VSUMESR_P \ +PLUTO0_P PLUTO1_P PLUTO2_P PLUTO3_P PLUTO4_P PLUTO5_P ORWD_F OWL_F PY_P \ +END_P FBI_P WATCH_P OVACC_P KBG_F DEL1_P COMPPAR_P VST0_P VST1_P \ +STAR0_P STAR1_P STAR2_P STAR3_P BULL0_P BULL1_P BULL2_P BULL3_P \ +BULL4_P BULL5_P BULL6_P +.names FBI STAR3 C2G5 _260_m_ LSD OWL_N LSD_P +0---11 1 +-0--11 1 +--1-11 1 +1000-- 1 +.names ACCRPY OWL_N _199_m__inv _219_m_ ACCRPY_P +11-- 1 +--00 1 +.names VERR_N WATCH _199_m__inv _42_m_ TIMOT OWL_N _219_m_ VERR_F +-----01 1 +100---- 1 +1-0-0-- 1 +1--10-- 1 +.names RATR OWL_N _886_m_ COMPPAR _58_m__inv RATR_P +--1-- 1 +11--- 1 +---00 1 +.names MARSSR OWL_N C29G7 TIMOT MARSSR_P +11-- 1 +--01 1 +.names VLENESR OWL_N KBG_N VLENESR_P +11- 1 +-10 1 +.names VSUMESR OWL_N VST1 _58_m__inv VSUMESR_P +11-- 1 +--10 1 +.names IBT0 PLUTO0 OWL_N _1015_m_ _894_m_ PLUTO0_P +-11-- 1 +0--11 1 +.names IBT0 PLUTO1 OWL_N _1015_m_ _894_m_ PLUTO1_P +-11-- 1 +1--11 1 +.names IBT1 PLUTO2 OWL_N IBT0 IBT2 _1015_m_ PLUTO2_P +-11--- 1 +0--011 1 +.names IBT1 PLUTO3 OWL_N IBT0 IBT2 _1015_m_ PLUTO3_P +-11--- 1 +0--111 1 +.names IBT1 PLUTO4 OWL_N IBT0 IBT2 _1015_m_ PLUTO4_P +-11--- 1 +1--011 1 +.names IBT1 PLUTO5 OWL_N IBT0 IBT2 _1015_m_ PLUTO5_P +-11--- 1 +1--111 1 +.names WATCH C1G3 ORWD_F +0- 1 +-0 1 +.names WATCH TIMOT ICLR END KBG_N OWL_F +0-001 1 +-0001 1 +.names PY DEL1 _89_m_ _90_m_ PY_P +1-1- 1 +-1-1 1 +.names _58_m__inv _199_m__inv _219_m_ END_P +0-- 1 +-00 1 +.names ORWD_N FBI _99_m_ _80_m_ _254_m__inv _260_m_ C2G5 _219_m_ STAR2 \ +_2087_m_ FBI_P +-1---0---- 1 +0---00---- 1 +---000---- 1 +0-----10-- 1 +-1----10-- 1 +---0--10-- 1 +-1----1-11 1 +--1---1-11 1 +.names VACC OWL_N OVACC C29G7 WATCH_P +---0 1 +011- 1 +.names VACC ICLR OVACC_P +10 1 +.names KBG_N _199_m__inv _42_m_ OWL_N _219_m_ KBG_F +10--- 1 +1-1-- 1 +---01 1 +.names CAPSD ICLR DEL1_P +10 1 +.names FBI DEL1 COMPPAR _219_m_ OWL_N COMPPAR_P +-100- 1 +0-1-1 1 +-01-1 1 +.names VST0 VST1 _89_m_ _90_m_ VST0_P +1-1- 1 +-1-1 1 +.names PY VST1 _89_m_ _90_m_ VST1_P +-11- 1 +1--1 1 +.names STAR0 _254_m__inv _44_m__inv STAR0_P +00- 1 +1-0 1 +.names STAR0 STAR1 _99_m_ _44_m__inv _2087_m_ _80_m_ _219_m_ STAR1_P +-1-0--- 1 +101---- 1 +01--1-- 1 +1----00 1 +.names STAR2 _99_m_ _44_m__inv C2G5 _80_m_ _219_m_ _2087_m_ STAR2_P +1-0---- 1 +-1-0--- 1 +1-----1 1 +0---10- 1 +.names OWL_N STAR2 STAR3 _254_m__inv _44_m__inv _2087_m_ _80_m_ \ +STAR3_P +--1-0-- 1 +--1--1- 1 +101---- 1 +-100--1 1 +.names BULL0 C29G7 OWL_N WATCH BULL0_P +00-- 1 +1-10 1 +.names BULL1 _1214_m_ BULL0 C29G7 BULL1_P +11-- 1 +0-10 1 +.names BULL1 BULL2 _1214_m_ BULL0 C29G7 BULL2_P +-11-- 1 +10-10 1 +.names OWL_N BULL3 _226_m_ BULL3_P +111 1 +100 1 +.names BULL4 OWL_N BULL3 _226_m_ _873_m_ BULL4_P +0---1 1 +110-- 1 +11-1- 1 +.names BULL5 BULL4_P BULL4 _873_m_ OWL_N BULL3 _226_m_ BULL5_P +11----- 1 +0-11--- 1 +1---10- 1 +1---1-1 1 +.names BULL2 BULL3 BULL4 BULL5 BULL6 _1214_m_ _873_m_ _226_m_ OWL_N \ +BULL6_P +----11--- 1 +0---1---1 1 +-0--1---1 1 +--0-1---1 1 +---01---1 1 +--110-1-- 1 +-111-1-0- 1 +.names STAR2 _80_m_ C2G5 +1- 1 +-0 1 +.names C1G3 C29G7 _260_m_ +0- 1 +-1 1 +.names ORWD_F _219_m_ C2G5 _199_m__inv +00- 1 +-01 1 +.names OWL_N FBI _219_m_ +0- 1 +-0 1 +.names STAR3 ORWD_F C2G5 CAT1 WATCH CAT0 _894_m_ _42_m_ +00----- 1 +-01---- 1 +0--0101 1 +--10101 1 +.names BULL0 BULL3 BULL4 BULL5 BULL6 BULL1 BULL2 TIMOT +0010110 1 +.names MMERR VST0 _58_m__inv _886_m_ +000 1 +.names OWL_N END _58_m__inv +0- 1 +-0 1 +.names OWL_N WATCH C29G7 +0- 1 +-0 1 +.names _886_m_ C29G7 TIMOT COMPPAR _58_m__inv VST1 OWL_N KBG_N _1015_m_ +1------- 1 +-01----- 1 +---00--- 1 +----01-- 1 +------10 1 +.names IBT1 IBT2 _894_m_ +10 1 +.names CAT1 CAT2 CAT3 CAT4 CAT5 IBT0 _894_m_ CAT0 IBT1 IBT2 C1G3 +0----11--- 1 +-----010-- 1 +----01--11 1 +---0-0--11 1 +--0--1--01 1 +-0---0--01 1 +.names ICLR FBI _89_m_ +00 1 +.names ICLR FBI _90_m_ +01 1 +.names ORWD_N _260_m_ _99_m_ +00 1 +.names STAR0 STAR1 _80_m_ +11 1 +.names _99_m_ _219_m_ _254_m__inv +01 1 +.names OWL_N _80_m_ _2087_m_ +10 1 +.names ORWD_N OWL_N FBI ORWD_F _44_m__inv +-0-- 1 +--1- 1 +0--0 1 +.names OWL_N BULL0 BULL1 WATCH _1214_m_ +10-- 1 +1-0- 1 +1--0 1 +.names WATCH BULL0 BULL1 BULL2 _226_m_ +0--- 1 +-0-- 1 +--0- 1 +---0 1 +.names OWL_N BULL3 _226_m_ _873_m_ +110 1 +.names VST0 SDO +1 1 +.end + diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/cavlc.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/cavlc.blif new file mode 100644 index 000000000..6ea1b8515 --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/cavlc.blif @@ -0,0 +1,1394 @@ +.model top +.inputs totalcoeffs[0] totalcoeffs[1] totalcoeffs[2] totalcoeffs[3] \ + totalcoeffs[4] ctable[0] ctable[1] ctable[2] trailingones[0] \ + trailingones[1] +.outputs coeff_token[0] coeff_token[1] coeff_token[2] coeff_token[3] \ + coeff_token[4] coeff_token[5] ctoken_len[0] ctoken_len[1] ctoken_len[2] \ + ctoken_len[3] ctoken_len[4] +.names totalcoeffs[3] ctable[0] n22 +00 1 +.names totalcoeffs[1] trailingones[1] n23 +01 1 +.names totalcoeffs[0] trailingones[1] n24 +01 1 +.names totalcoeffs[1] n24 n25 +10 1 +.names n23 n25 n26 +00 1 +.names n22 n26 n27 +11 1 +.names totalcoeffs[0] trailingones[1] n28 +10 1 +.names totalcoeffs[1] n28 n29 +00 1 +.names totalcoeffs[1] trailingones[1] n30 +10 1 +.names ctable[2] n30 n31 +00 1 +.names n29 n31 n32 +01 1 +.names n27 n32 n33 +00 1 +.names totalcoeffs[2] n33 n34 +00 1 +.names totalcoeffs[2] ctable[0] n35 +00 1 +.names totalcoeffs[0] n35 n36 +00 1 +.names totalcoeffs[1] totalcoeffs[2] n37 +11 1 +.names n36 n37 n38 +00 1 +.names trailingones[1] n38 n39 +00 1 +.names totalcoeffs[2] totalcoeffs[3] n40 +00 1 +.names trailingones[1] n40 n41 +10 1 +.names totalcoeffs[0] totalcoeffs[3] n42 +11 1 +.names n41 n42 n43 +00 1 +.names totalcoeffs[1] n43 n44 +00 1 +.names totalcoeffs[1] totalcoeffs[3] n45 +10 1 +.names n44 n45 n46 +00 1 +.names n39 n46 n47 +01 1 +.names ctable[2] n47 n48 +00 1 +.names n34 n48 n49 +00 1 +.names trailingones[0] n49 n50 +00 1 +.names ctable[2] trailingones[0] n51 +11 1 +.names ctable[0] n51 n52 +01 1 +.names ctable[2] trailingones[1] n53 +01 1 +.names n52 n53 n54 +00 1 +.names totalcoeffs[1] n54 n55 +10 1 +.names totalcoeffs[1] ctable[2] n56 +10 1 +.names ctable[0] trailingones[1] n57 +00 1 +.names n56 n57 n58 +01 1 +.names n55 n58 n59 +00 1 +.names totalcoeffs[0] totalcoeffs[2] n60 +10 1 +.names n59 n60 n61 +01 1 +.names totalcoeffs[2] trailingones[1] n62 +10 1 +.names totalcoeffs[0] totalcoeffs[1] n63 +00 1 +.names n62 n63 n64 +11 1 +.names n52 n64 n65 +11 1 +.names n61 n65 n66 +00 1 +.names totalcoeffs[3] n66 n67 +00 1 +.names n50 n67 n68 +00 1 +.names ctable[1] n68 n69 +00 1 +.names totalcoeffs[0] totalcoeffs[2] n70 +00 1 +.names n23 n70 n71 +11 1 +.names ctable[0] n71 n72 +00 1 +.names ctable[1] n72 n73 +10 1 +.names totalcoeffs[0] trailingones[1] n74 +00 1 +.names totalcoeffs[0] trailingones[1] n75 +11 1 +.names n74 n75 n76 +00 1 +.names totalcoeffs[1] n76 n77 +10 1 +.names totalcoeffs[2] n77 n78 +11 1 +.names ctable[0] n78 n79 +11 1 +.names n73 n79 n80 +00 1 +.names trailingones[0] n80 n81 +10 1 +.names totalcoeffs[1] n24 n82 +00 1 +.names trailingones[0] n82 n83 +00 1 +.names totalcoeffs[1] totalcoeffs[2] n84 +01 1 +.names n28 n84 n85 +11 1 +.names n83 n85 n86 +00 1 +.names ctable[0] n86 n87 +00 1 +.names n81 n87 n88 +00 1 +.names totalcoeffs[3] n88 n89 +10 1 +.names totalcoeffs[2] n28 n90 +00 1 +.names ctable[1] n90 n91 +10 1 +.names n40 n77 n92 +11 1 +.names n91 n92 n93 +00 1 +.names ctable[0] n93 n94 +10 1 +.names totalcoeffs[2] trailingones[1] n95 +11 1 +.names totalcoeffs[2] n30 n96 +01 1 +.names n95 n96 n97 +00 1 +.names totalcoeffs[0] totalcoeffs[3] n98 +00 1 +.names n97 n98 n99 +01 1 +.names ctable[1] n99 n100 +11 1 +.names n94 n100 n101 +00 1 +.names trailingones[0] n101 n102 +10 1 +.names totalcoeffs[2] totalcoeffs[3] n103 +10 1 +.names n23 n103 n104 +11 1 +.names totalcoeffs[1] trailingones[0] n105 +10 1 +.names n104 n105 n106 +00 1 +.names totalcoeffs[0] n106 n107 +00 1 +.names totalcoeffs[1] trailingones[1] n108 +00 1 +.names totalcoeffs[2] ctable[1] n109 +01 1 +.names totalcoeffs[3] n109 n110 +10 1 +.names n108 n110 n111 +10 1 +.names n95 n111 n112 +00 1 +.names trailingones[0] n112 n113 +00 1 +.names n107 n113 n114 +00 1 +.names ctable[0] n114 n115 +00 1 +.names totalcoeffs[0] n40 n116 +01 1 +.names trailingones[0] n108 n117 +01 1 +.names n116 n117 n118 +11 1 +.names n115 n118 n119 +00 1 +.names n102 n119 n120 +01 1 +.names n89 n120 n121 +01 1 +.names ctable[2] n121 n122 +00 1 +.names n69 n122 n123 +00 1 +.names totalcoeffs[4] n123 n124 +00 1 +.names trailingones[0] trailingones[1] n125 +00 1 +.names ctable[1] n125 n126 +01 1 +.names totalcoeffs[4] trailingones[0] n127 +11 1 +.names ctable[1] n127 n128 +11 1 +.names n126 n128 n129 +00 1 +.names ctable[0] n129 n130 +10 1 +.names ctable[1] trailingones[1] n131 +10 1 +.names totalcoeffs[4] trailingones[1] n132 +11 1 +.names n131 n132 n133 +00 1 +.names ctable[0] ctable[1] n134 +11 1 +.names n133 n134 n135 +00 1 +.names trailingones[0] n135 n136 +01 1 +.names n130 n136 n137 +00 1 +.names ctable[2] n137 n138 +00 1 +.names totalcoeffs[1] totalcoeffs[3] n139 +00 1 +.names totalcoeffs[2] n139 n140 +01 1 +.names n138 n140 n141 +11 1 +.names totalcoeffs[0] n141 n142 +01 1 +.names n124 n142 coeff_token[0] +00 0 +.names totalcoeffs[0] trailingones[0] n144 +11 1 +.names n95 n144 n145 +11 1 +.names totalcoeffs[2] trailingones[0] n146 +00 1 +.names n74 n146 n147 +11 1 +.names n145 n147 n148 +00 1 +.names ctable[0] n148 n149 +10 1 +.names ctable[0] trailingones[0] n150 +01 1 +.names ctable[1] trailingones[1] n151 +11 1 +.names n150 n151 n152 +00 1 +.names totalcoeffs[0] n152 n153 +00 1 +.names trailingones[0] n151 n154 +11 1 +.names trailingones[0] n57 n155 +01 1 +.names n154 n155 n156 +00 1 +.names n153 n156 n157 +01 1 +.names totalcoeffs[2] n157 n158 +10 1 +.names n149 n158 n159 +00 1 +.names totalcoeffs[4] n159 n160 +00 1 +.names ctable[1] trailingones[1] n161 +01 1 +.names ctable[0] trailingones[0] n162 +10 1 +.names n127 n162 n163 +00 1 +.names ctable[1] n163 n164 +00 1 +.names n132 n164 n165 +00 1 +.names n161 n165 n166 +00 1 +.names n70 n166 n167 +11 1 +.names n160 n167 n168 +00 1 +.names totalcoeffs[1] n168 n169 +00 1 +.names ctable[1] trailingones[0] n170 +11 1 +.names n152 n170 n171 +00 1 +.names totalcoeffs[0] n171 n172 +11 1 +.names totalcoeffs[0] ctable[0] n173 +01 1 +.names trailingones[0] trailingones[1] n174 +01 1 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n693 n694 +00 1 +.names trailingones[0] n381 n695 +00 1 +.names n676 n695 n696 +10 1 +.names totalcoeffs[2] n696 n697 +11 1 +.names n694 n697 n698 +00 1 +.names totalcoeffs[1] n698 n699 +00 1 +.names ctable[0] n103 n700 +00 1 +.names ctable[1] n700 n701 +10 1 +.names n699 n701 n702 +00 1 +.names n687 n702 n703 +01 1 +.names n675 n703 n704 +01 1 +.names n674 n704 n705 +01 1 +.names n672 n705 n706 +01 1 +.names n669 n706 ctoken_len[3] +01 1 +.names trailingones[0] n29 n708 +00 1 +.names n25 n708 n709 +00 1 +.names n423 n709 n710 +10 1 +.names totalcoeffs[2] n710 n711 +11 1 +.names n430 n711 n712 +00 1 +.names ctable[2] n712 n713 +00 1 +.names n342 n713 ctoken_len[4] +11 1 +.end diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/ctrl.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/ctrl.blif new file mode 100644 index 000000000..560ceda29 --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/ctrl.blif @@ -0,0 +1,358 @@ +.model top +.inputs opcode[0] opcode[1] opcode[2] opcode[3] opcode[4] op_ext[0] \ + op_ext[1] +.outputs sel_reg_dst[0] sel_reg_dst[1] sel_alu_opB[0] sel_alu_opB[1] \ + alu_op[0] alu_op[1] alu_op[2] alu_op_ext[0] alu_op_ext[1] alu_op_ext[2] \ + alu_op_ext[3] halt reg_write sel_pc_opA sel_pc_opB beqz bnez bgez bltz \ + jump Cin invA invB sign mem_write sel_wb +.names opcode[0] opcode[1] n35 +10 1 +.names opcode[3] opcode[4] n36 +11 1 +.names n35 n36 n37 +11 1 +.names opcode[1] opcode[3] n38 +11 1 +.names opcode[4] n38 n39 +11 1 +.names n37 n39 n40 +00 1 +.names opcode[2] n40 n41 +00 1 +.names opcode[1] opcode[3] n42 +01 1 +.names opcode[4] n42 n43 +11 1 +.names opcode[3] opcode[4] n44 +00 1 +.names n36 n44 n45 +00 1 +.names opcode[1] n45 n46 +10 1 +.names n43 n46 n47 +00 1 +.names opcode[2] n47 n48 +10 1 +.names n41 n48 sel_reg_dst[0] +00 0 +.names opcode[0] n36 n50 +00 1 +.names opcode[0] n50 n51 +00 1 +.names opcode[1] n51 n52 +00 1 +.names opcode[3] n44 n53 +00 1 +.names opcode[1] n53 n54 +10 1 +.names n52 n54 n55 +00 1 +.names opcode[2] n55 n56 +00 1 +.names opcode[3] opcode[4] n57 +01 1 +.names opcode[3] n57 n58 +00 1 +.names opcode[1] n58 n59 +10 1 +.names opcode[1] n59 n60 +10 1 +.names opcode[2] n60 n61 +10 1 +.names n56 n61 sel_reg_dst[1] +00 1 +.names opcode[0] n45 n63 +00 1 +.names opcode[3] n36 n64 +10 1 +.names opcode[0] n64 n65 +10 1 +.names n63 n65 n66 +00 1 +.names opcode[1] n66 n67 +10 1 +.names n52 n67 n68 +00 1 +.names opcode[2] n68 n69 +00 1 +.names opcode[2] n69 sel_alu_opB[0] +00 1 +.names opcode[0] opcode[3] n71 +00 1 +.names n57 n71 n72 +01 1 +.names opcode[0] n45 n73 +10 1 +.names n72 n73 n74 +00 1 +.names opcode[1] n74 n75 +00 1 +.names n54 n75 n76 +00 1 +.names opcode[2] n76 n77 +00 1 +.names opcode[2] n53 n78 +10 1 +.names n77 n78 sel_alu_opB[1] +00 1 +.names opcode[0] opcode[3] n80 +01 1 +.names opcode[4] op_ext[0] n81 +11 1 +.names n80 n81 n82 +11 1 +.names opcode[3] op_ext[1] n83 +10 1 +.names n36 n83 n84 +01 1 +.names opcode[3] op_ext[0] n85 +10 1 +.names n36 n85 n86 +01 1 +.names opcode[3] op_ext[0] n87 +11 1 +.names n86 n87 n88 +00 1 +.names op_ext[1] n88 n89 +10 1 +.names n84 n89 n90 +00 1 +.names opcode[0] n90 n91 +10 1 +.names n82 n91 n92 +00 1 +.names opcode[1] n92 n93 +10 1 +.names opcode[2] n93 n94 +00 1 +.names opcode[0] n53 n95 +10 1 +.names opcode[0] n95 n96 +10 1 +.names opcode[2] n96 n97 +10 1 +.names n94 n97 alu_op[0] +00 1 +.names opcode[3] op_ext[1] n99 +11 1 +.names n84 n99 n100 +00 1 +.names opcode[1] n100 n101 +10 1 +.names opcode[2] n101 n102 +00 1 +.names opcode[1] n54 n103 +10 1 +.names opcode[2] n103 n104 +10 1 +.names n102 n104 alu_op[1] +00 1 +.names opcode[1] n36 n106 +00 1 +.names n44 n106 n107 +01 1 +.names n44 n50 n108 +01 1 +.names opcode[0] n58 n109 +10 1 +.names n108 n109 n110 +00 1 +.names opcode[1] n110 n111 +10 1 +.names n107 n111 n112 +00 1 +.names opcode[2] n112 n113 +00 1 +.names opcode[2] opcode[3] n114 +11 1 +.names opcode[4] n114 n115 +11 1 +.names n113 n115 alu_op[2] +00 0 +.names opcode[1] opcode[2] n117 +00 1 +.names n52 n117 n118 +01 1 +.names opcode[1] n74 n119 +10 1 +.names n37 n119 n120 +00 1 +.names opcode[2] n120 n121 +10 1 +.names n118 n121 alu_op_ext[0] +00 0 +.names opcode[0] n53 n123 +00 1 +.names opcode[0] n123 n124 +00 1 +.names opcode[1] n124 n125 +10 1 +.names opcode[1] opcode[2] n126 +10 1 +.names n125 n126 n127 +01 1 +.names opcode[1] opcode[2] n128 +11 1 +.names n45 n128 n129 +01 1 +.names n127 n129 alu_op_ext[1] +00 0 +.names n106 n125 n131 +00 1 +.names opcode[2] n131 n132 +00 1 +.names n61 n132 alu_op_ext[2] +00 1 +.names n80 n109 n134 +00 1 +.names opcode[1] n134 n135 +10 1 +.names opcode[2] n107 n136 +00 1 +.names n135 n136 n137 +01 1 +.names n78 n137 alu_op_ext[3] +00 1 +.names opcode[0] n58 n139 +00 1 +.names opcode[0] n139 n140 +00 1 +.names opcode[1] n140 n141 +00 1 +.names opcode[1] n141 n142 +00 1 +.names opcode[2] n142 n143 +00 1 +.names opcode[2] n143 halt +00 1 +.names opcode[1] n134 n145 +00 1 +.names n59 n145 n146 +00 1 +.names opcode[2] n146 n147 +00 1 +.names opcode[1] opcode[4] n148 +01 1 +.names opcode[1] n64 n149 +10 1 +.names n148 n149 n150 +00 1 +.names opcode[2] n150 n151 +10 1 +.names n147 n151 reg_write +00 0 +.names opcode[0] n109 n153 +10 1 +.names opcode[2] n153 n154 +10 1 +.names opcode[2] n154 sel_pc_opA +10 1 +.names opcode[2] n140 n156 +10 1 +.names opcode[2] n156 sel_pc_opB +10 1 +.names opcode[0] n64 n158 +00 1 +.names opcode[0] n158 n159 +00 1 +.names opcode[1] n159 n160 +00 1 +.names opcode[1] n160 n161 +00 1 +.names opcode[2] n161 n162 +10 1 +.names opcode[2] n162 beqz +10 1 +.names opcode[0] n65 n164 +10 1 +.names opcode[1] n164 n165 +00 1 +.names opcode[1] n165 n166 +00 1 +.names opcode[2] n166 n167 +10 1 +.names opcode[2] n167 bnez +10 1 +.names opcode[1] n164 n169 +10 1 +.names opcode[1] n169 n170 +10 1 +.names opcode[2] n170 n171 +10 1 +.names opcode[2] n171 bgez +10 1 +.names opcode[1] n159 n173 +10 1 +.names opcode[1] n173 n174 +10 1 +.names opcode[2] n174 n175 +10 1 +.names opcode[2] n175 bltz +10 1 +.names opcode[2] n58 n177 +10 1 +.names opcode[2] n177 jump +10 1 +.names opcode[0] opcode[1] n179 +11 1 +.names n88 n179 n180 +01 1 +.names n35 n65 n181 +10 1 +.names opcode[2] n181 n182 +00 1 +.names n180 n182 n183 +01 1 +.names opcode[1] n51 n184 +10 1 +.names n106 n184 n185 +00 1 +.names opcode[2] n185 n186 +10 1 +.names n183 n186 Cin +00 1 +.names op_ext[0] n36 n188 +11 1 +.names op_ext[1] n188 n189 +00 1 +.names op_ext[1] n189 n190 +00 1 +.names opcode[0] n190 n191 +10 1 +.names opcode[0] n191 n192 +10 1 +.names opcode[1] n192 n193 +10 1 +.names n165 n193 n194 +00 1 +.names opcode[2] n194 n195 +00 1 +.names opcode[2] n195 invA +00 1 +.names n90 n179 n197 +01 1 +.names opcode[2] n197 n198 +00 1 +.names n186 n198 invB +00 1 +.names opcode[1] n124 n200 +00 1 +.names opcode[1] n96 n201 +10 1 +.names n200 n201 n202 +00 1 +.names opcode[2] n202 n203 +00 1 +.names opcode[2] n203 mem_write +00 1 +.names opcode[1] n96 n205 +00 1 +.names opcode[1] n205 n206 +00 1 +.names opcode[2] n206 n207 +00 1 +.names opcode[2] n207 sel_wb +00 1 +.names sign + 1 +.end diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/dalu.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/dalu.blif new file mode 100644 index 000000000..b3b0547e4 --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/dalu.blif @@ -0,0 +1,1103 @@ +.model TOP +.inputs Psh2 Psh1 Psh0 Popsel3 Popsel2 Popsel1 Popsel0 Pmusel4 Pmusel3 Pmusel2 \ +Pmusel1 PinD15 PinD14 PinD13 PinD12 PinD11 PinD10 PinD9 PinD8 PinD7 PinD6 \ +PinD5 PinD4 PinD3 PinD2 PinD1 PinD0 PinC15 PinC14 PinC13 PinC12 PinC11 PinC10 \ +PinC9 PinC8 PinC7 PinC6 PinC5 PinC4 PinC3 PinC2 PinC1 PinC0 PinB15 PinB14 \ +PinB13 PinB12 PinB11 PinB10 PinB9 PinB8 PinB7 PinB6 PinB5 PinB4 PinB3 PinB2 \ +PinB1 PinB0 PinA15 PinA14 PinA13 PinA12 PinA11 PinA10 PinA9 PinA8 PinA7 PinA6 \ +PinA5 PinA4 PinA3 PinA2 PinA1 PinA0 +.outputs PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0 +.names n1 PO15 +0 1 +.names n2 PO14 +0 1 +.names n3 PO13 +0 1 +.names n4 PO12 +0 1 +.names n5 PO11 +0 1 +.names n6 PO10 +0 1 +.names n7 PO9 +0 1 +.names n8 PO8 +0 1 +.names n9 PO7 +0 1 +.names n10 PO6 +0 1 +.names n11 PO5 +0 1 +.names n12 PO4 +0 1 +.names n13 PO3 +0 1 +.names n14 PO2 +0 1 +.names n15 PO1 +0 1 +.names n16 PO0 +0 1 +.names n184 n185 n36 n120 n1 +111- 1 +11-1 1 +.names n194 n193 n120 n2 +11- 1 +1-1 1 +.names n205 n199 n120 n3 +11- 1 +1-1 1 +.names n212 n96 n209 n4 +11- 1 +1-1 1 +.names n109 n218 n217 n344 n5 +11-- 1 +-11- 1 +-1-0 1 +.names n222 n224 n225 n354 n6 +111- 1 +-110 1 +.names n81 n86 n87 n354 n7 +111- 1 +-110 1 +.names n97 n91 n96 n8 +11- 1 +1-1 1 +.names n110 n108 n109 n9 +11- 1 +1-1 1 +.names n121 n114 n120 n10 +11- 1 +1-1 1 +.names n131 n125 n120 n11 +11- 1 +1-1 1 +.names n139 n96 n135 n12 +11- 1 +1-1 1 +.names n152 n143 n120 n13 +11- 1 +1-1 1 +.names n160 n96 n156 n14 +11- 1 +1-1 1 +.names n233 n229 n96 n15 +11- 1 +1-1 1 +.names n241 n237 n96 n16 +11- 1 +1-1 1 +.names n164 n309 n18 +11 1 +.names n34 n35 n20 +1- 1 +-1 1 +.names PinD12 PinB12 n18 n20 n17 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names PinD9 PinB9 n18 n20 n22 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names PinD14 PinB14 n18 n20 n25 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names PinD10 PinB10 n18 n20 n28 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names PinD11 PinB11 n18 n20 n31 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pmusel2 Pmusel1 n34 +11 1 +00 1 +.names Pmusel4 Pmusel3 n35 +1- 1 +-0 1 +.names PinD15 PinB15 n18 n20 n36 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Psh2 n36 n40 +0- 1 +-1 1 +.names n40 Psh2 n31 n39 +11- 1 +1-1 1 +.names PinD13 PinB13 n18 n20 n41 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names n22 n208 n92 n207 n46 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n378 n93 n39 n353 n47 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names Psh2 n351 n45 +1- 1 +-1 1 +.names n46 n47 n17 n45 n44 +111- 1 +11-1 1 +.names Pmusel2 PinC7 PinA7 n49 +11- 1 +0-1 1 +-11 1 +.names Pmusel4 n49 n76 n384 n48 +0--0 1 +010- 1 +.names Pmusel2 PinC6 PinA6 n54 +11- 1 +0-1 1 +-11 1 +.names Pmusel4 n54 n76 n386 n53 +0--0 1 +010- 1 +.names Pmusel2 PinC5 PinA5 n57 +11- 1 +0-1 1 +-11 1 +.names Pmusel4 n57 n76 n389 n56 +0--0 1 +010- 1 +.names Pmusel2 PinC3 PinA3 n60 +11- 1 +0-1 1 +-11 1 +.names Pmusel4 n60 n76 n394 n59 +0--0 1 +010- 1 +.names Pmusel2 PinC2 PinA2 n63 +11- 1 +0-1 1 +-11 1 +.names Pmusel4 n63 n76 n396 n62 +0--0 1 +010- 1 +.names Pmusel2 PinC1 PinA1 n66 +11- 1 +0-1 1 +-11 1 +.names Pmusel4 n66 n76 n409 n65 +0--0 1 +010- 1 +.names Pmusel2 PinC0 PinA0 n69 +11- 1 +0-1 1 +-11 1 +.names Pmusel4 n69 n76 n413 n68 +0--0 1 +010- 1 +.names Pmusel2 PinC4 PinA4 n72 +11- 1 +0-1 1 +-11 1 +.names Pmusel4 n72 n76 n392 n71 +0--0 1 +010- 1 +.names PinD8 PinB8 n348 n349 n77 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pmusel3 Pmusel1 n76 +1- 1 +-0 1 +.names n77 n76 n376 n74 +11- 1 +1-0 1 +.names Pmusel2 PinC9 PinA9 n79 +11- 1 +0-1 1 +-11 1 +.names Pmusel4 n76 n79 n377 n78 +0--0 1 +001- 1 +.names Popsel1 Popsel0 n82 +11 1 +00 1 +.names PinA9 n20 n78 n261 n83 +0-01 1 +-101 1 +.names Popsel0 Popsel1 n84 +1- 1 +-1 1 +.names n82 n83 n44 n84 n81 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n109 n242 n344 n86 +1-- 1 +-1- 1 +--0 1 +.names n44 n120 n87 +1- 1 +-1 1 +.names PinD8 PinB8 n18 n20 n88 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names n102 n207 n31 n45 n94 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n381 n382 n28 n360 n95 +111- 1 +11-1 1 +.names Psh2 n22 n41 n92 +01- 1 +1-1 1 +-11 1 +.names Psh1 Psh0 n93 +1- 1 +-0 1 +.names n94 n95 n92 n93 n91 +111- 1 +11-1 1 +.names n383 n359 n380 n379 n97 +11-- 1 +1-11 1 +.names n84 n120 n354 n96 +11- 1 +-10 1 +.names PinD7 PinB7 n18 n20 n98 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names n115 n207 n28 n45 n103 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n385 n382 n22 n360 n104 +111- 1 +11-1 1 +.names Psh2 n17 n88 n102 +11- 1 +0-1 1 +-11 1 +.names n103 n104 n102 n93 n101 +111- 1 +11-1 1 +.names n264 n279 n106 +1- 1 +-1 1 +.names n253 n266 n107 +11 1 +00 1 +.names n106 n107 n105 +1- 1 +-1 1 +.names n270 n359 n101 n96 n110 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n105 n267 n108 +11 1 +00 1 +.names Popsel3 n345 n109 +1- 1 +-1 1 +.names PinD6 PinB6 n18 n20 n111 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names n126 n207 n22 n45 n116 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n387 n88 n360 n117 +11- 1 +1-1 1 +.names Psh2 n31 n98 n115 +11- 1 +0-1 1 +-11 1 +.names n116 n117 n115 n93 n114 +111- 1 +11-1 1 +.names PinA6 n20 n53 n277 n119 +0-01 1 +-101 1 +.names n82 n119 n114 n84 n118 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n109 n118 n274 n354 n121 +11-- 1 +-10- 1 +1--0 1 +--00 1 +.names Popsel3 Popsel2 n84 n120 +1-- 1 +-0- 1 +--0 1 +.names PinD5 PinB5 n18 n20 n122 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names n136 n207 n88 n45 n127 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n390 n98 n360 n128 +11- 1 +1-1 1 +.names Psh2 n28 n111 n126 +11- 1 +0-1 1 +-11 1 +.names n127 n128 n126 n93 n125 +111- 1 +11-1 1 +.names PinA5 n20 n56 n282 n130 +0-01 1 +-101 1 +.names n82 n130 n125 n84 n129 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n109 n129 n278 n354 n131 +11-- 1 +-10- 1 +1--0 1 +--00 1 +.names PinD4 PinB4 n18 n20 n132 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names n144 n207 n98 n45 n137 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n393 n111 n360 n138 +11- 1 +1-1 1 +.names Psh2 n22 n122 n136 +11- 1 +0-1 1 +-11 1 +.names n137 n138 n136 n93 n135 +111- 1 +11-1 1 +.names n283 n109 n285 n359 n139 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names PinD3 PinB3 n18 n20 n140 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names n157 n207 n111 n45 n145 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n395 n122 n360 n146 +11- 1 +1-1 1 +.names Psh2 n88 n132 n144 +11- 1 +0-1 1 +-11 1 +.names n145 n146 n144 n93 n143 +111- 1 +11-1 1 +.names n248 n335 n148 +1- 1 +-1 1 +.names n245 n253 n149 +11 1 +00 1 +.names n148 n149 n147 +1- 1 +-1 1 +.names PinA3 n20 n59 n293 n151 +0-01 1 +-101 1 +.names n82 n151 n143 n84 n150 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n109 n150 n289 n354 n152 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names PinD2 PinB2 n18 n20 n153 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names n230 n207 n122 n45 n158 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n397 n132 n360 n159 +11- 1 +1-1 1 +.names Psh2 n98 n140 n157 +11- 1 +0-1 1 +-11 1 +.names n158 n159 n157 n93 n156 +111- 1 +11-1 1 +.names n109 n294 n295 n359 n160 +1-1- 1 +-01- 1 +1--1 1 +-0-1 1 +.names Pmusel2 PinC15 PinA15 n162 +11- 1 +0-1 1 +-11 1 +.names Pmusel4 n76 n162 n399 n161 +0--0 1 +001- 1 +.names Pmusel2 Pmusel1 n35 n164 +0-- 1 +-0- 1 +--1 1 +.names Pmusel2 PinC14 PinA14 n168 +11- 1 +0-1 1 +-11 1 +.names Pmusel4 n76 n168 n400 n167 +0--0 1 +001- 1 +.names Pmusel2 PinC13 PinA13 n171 +11- 1 +0-1 1 +-11 1 +.names Pmusel4 n76 n171 n401 n170 +0--0 1 +001- 1 +.names Pmusel2 PinC12 PinA12 n174 +11- 1 +0-1 1 +-11 1 +.names Pmusel4 n76 n174 n403 n173 +0--0 1 +001- 1 +.names Pmusel2 PinC11 PinA11 n177 +11- 1 +0-1 1 +-11 1 +.names Pmusel4 n76 n177 n406 n176 +0--0 1 +001- 1 +.names Pmusel2 PinC10 PinA10 n180 +11- 1 +0-1 1 +-11 1 +.names Pmusel4 n76 n180 n407 n179 +0--0 1 +001- 1 +.names PinA15 n20 n161 n306 n183 +0-01 1 +-101 1 +.names n82 n183 n36 n84 n182 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n182 n354 n184 +1- 1 +-0 1 +.names n109 n189 n301 n190 n185 +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names Psh2 Psh1 Psh0 n187 +00- 1 +1-1 1 +-01 1 +.names n187 n93 n186 +11 1 +.names n299 n318 n189 +1- 1 +-1 1 +.names n253 n303 n190 +11 1 +00 1 +.names n189 n190 n188 +1- 1 +-1 1 +.names PinC14 n167 n312 n309 n192 +001- 1 +-011 1 +.names n25 n36 n186 n193 +11- 1 +1-1 1 +-10 1 +.names n82 n192 n193 n84 n191 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n109 n191 n307 n354 n194 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names Psh2 Psh1 n36 n353 n195 +--00 1 +010- 1 +.names Psh1 n40 n41 n186 n202 +1-1- 1 +-11- 1 +1--0 1 +-1-0 1 +.names Psh2 n93 n200 +1- 1 +-1 1 +.names n25 n195 n202 n200 n199 +101- 1 +-011 1 +.names PinC13 n170 n309 n316 n204 +00-1 1 +-011 1 +.names n82 n204 n199 n84 n203 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n109 n203 n313 n354 n205 +11-- 1 +-10- 1 +1--0 1 +--00 1 +.names Psh2 n351 n208 +0- 1 +-1 1 +.names Psh0 Psh1 n207 +1- 1 +-1 1 +.names n208 Psh2 n207 n206 +11- 1 +1-1 1 +.names n41 n200 n25 n360 n210 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n36 n40 n45 n351 n211 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names n210 n211 n17 n206 n209 +111- 1 +11-1 1 +.names n109 n317 n319 n359 n212 +1-1- 1 +-01- 1 +1--1 1 +-0-1 1 +.names n17 n200 n41 n360 n214 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n25 n40 n45 n351 n215 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names n214 n215 n31 n206 n213 +111- 1 +11-1 1 +.names n323 n359 n213 n96 n218 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n253 n257 n217 +11 1 +00 1 +.names n378 n207 n41 n45 n220 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n408 n382 n17 n360 n221 +111- 1 +11-1 1 +.names n220 n221 n39 n93 n219 +111- 1 +11-1 1 +.names PinA10 n20 n179 n329 n223 +0-01 1 +-101 1 +.names n82 n223 n219 n84 n222 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n109 n255 n344 n224 +1-- 1 +-1- 1 +--0 1 +.names n219 n120 n225 +1- 1 +-1 1 +.names PinD1 PinB1 n18 n20 n226 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names n411 n207 n132 n45 n231 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n410 n140 n360 n232 +11- 1 +1-1 1 +.names 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n263 n262 +11 1 +00 1 +.names n57 n341 n265 +10 1 +.names n253 n265 n264 +11 1 +00 1 +.names n54 n341 n266 +10 1 +.names n49 n341 n268 +10 1 +.names n253 n268 n267 +11 1 +00 1 +.names PinC7 n164 n309 n273 +0-- 1 +-11 1 +.names PinA7 n20 n48 n273 n270 +0-01 1 +-101 1 +.names n106 n107 n274 +01 1 +10 1 +.names PinC6 n164 n309 n277 +0-- 1 +-11 1 +.names n262 n343 n279 +1- 1 +-1 1 +.names n279 n264 n278 +01 1 +10 1 +.names PinC5 n164 n309 n282 +0-- 1 +-11 1 +.names n262 n343 n283 +11 1 +00 1 +.names PinC4 n164 n309 n288 +0-- 1 +-11 1 +.names PinA4 n20 n71 n288 n285 +0-01 1 +-101 1 +.names n147 n246 n289 +11 1 +00 1 +.names PinC3 n164 n309 n293 +0-- 1 +-11 1 +.names n148 n149 n294 +01 1 +10 1 +.names PinC2 n164 n309 n298 +0-- 1 +-11 1 +.names PinA2 n20 n62 n298 n295 +0-01 1 +-101 1 +.names n174 n341 n300 +10 1 +.names n253 n300 n299 +11 1 +00 1 +.names n168 n341 n302 +10 1 +.names n253 n302 n301 +11 1 +00 1 +.names n171 n341 n303 +10 1 +.names PinC15 n164 n309 n306 +0-- 1 +-11 1 +.names n188 n301 n307 +11 1 +00 1 +.names PinC14 PinA14 n20 n164 n312 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names Pmusel4 Pmusel3 Pmusel2 Pmusel1 n309 +0--- 1 +-1-- 1 +--1- 1 +---1 1 +.names n189 n190 n313 +01 1 +10 1 +.names PinC13 PinA13 n20 n164 n316 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names n262 n264 n107 n267 n344 n318 +1---- 1 +-1--- 1 +--1-- 1 +---1- 1 +----1 1 +.names n318 n299 n317 +01 1 +10 1 +.names PinC12 PinA12 n20 n164 n322 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PinC12 n173 n309 n322 n319 +00-1 1 +-011 1 +.names PinC11 n164 n309 n326 +0-- 1 +-11 1 +.names PinA11 n20 n176 n326 n323 +0-01 1 +-101 1 +.names PinC10 n164 n309 n329 +0-- 1 +-11 1 +.names PinC1 n164 n309 n333 +0-- 1 +-11 1 +.names PinA1 n20 n65 n333 n330 +0-01 1 +-101 1 +.names n250 n253 n335 +1- 1 +-0 1 +.names n335 n248 n334 +01 1 +10 1 +.names PinC0 n164 n309 n339 +0-- 1 +-11 1 +.names PinA0 n20 n68 n339 n336 +0-01 1 +-101 1 +.names n250 n253 n340 +01 1 +10 1 +.names Pmusel4 Pmusel3 n34 n341 +0-- 1 +-1- 1 +--1 1 +.names n149 n246 n248 n250 n253 n343 +1---- 1 +-1--- 1 +--1-- 1 +---1- 1 +----0 1 +.names n242 n252 n255 n217 n343 n344 +1---- 1 +-1--- 1 +--1-- 1 +---1- 1 +----1 1 +.names Popsel2 n84 n345 +11 1 +00 1 +.names Pmusel3 Pmusel2 Pmusel1 n348 +0-- 1 +-1- 1 +--1 1 +.names Pmusel3 Pmusel2 Pmusel1 n349 +1-- 1 +-0- 1 +--1 1 +.names Psh1 Psh0 n351 +0- 1 +-0 1 +.names Psh1 Psh0 n353 +0- 1 +-1 1 +.names Popsel3 Popsel2 n354 +10 1 +.names n82 n354 n359 +1- 1 +-0 1 +.names Psh2 n353 n360 +1- 1 +-1 1 +.names Psh2 n353 n363 +0- 1 +-1 1 +.names Pmusel2 PinC8 PinA8 n376 +11- 1 +0-1 1 +-11 1 +.names PinD9 PinB9 n348 n349 n377 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Psh2 n25 n28 n378 +11- 1 +0-1 1 +-11 1 +.names Pmusel4 PinA8 n20 n74 n379 +10-- 1 +1-1- 1 +-0-1 1 +--11 1 +.names PinC8 n164 n309 n380 +0-- 1 +-11 1 +.names n88 n208 n381 +1- 1 +-1 1 +.names n353 n40 n382 +1- 1 +-1 1 +.names n109 n252 n344 n383 +1-- 1 +-1- 1 +--0 1 +.names PinD7 PinB7 n348 n349 n384 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names n98 n208 n385 +1- 1 +-1 1 +.names PinD6 PinB6 n348 n349 n386 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names n25 n363 n111 n208 n387 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names PinD5 PinB5 n348 n349 n389 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names n41 n363 n122 n208 n390 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names PinD4 PinB4 n348 n349 n392 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names n17 n363 n132 n208 n393 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names PinD3 PinB3 n348 n349 n394 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names n31 n363 n140 n208 n395 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names PinD2 PinB2 n348 n349 n396 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names n28 n363 n153 n208 n397 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names PinD15 PinB15 n348 n349 n399 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names PinD14 PinB14 n348 n349 n400 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names PinD13 PinB13 n348 n349 n401 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names PinD12 PinB12 n348 n349 n403 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names PinD11 PinB11 n348 n349 n406 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names PinD10 PinB10 n348 n349 n407 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names n28 n208 n408 +1- 1 +-1 1 +.names PinD1 PinB1 n348 n349 n409 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names n22 n363 n226 n208 n410 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names Psh2 n122 n226 n411 +11- 1 +0-1 1 +-11 1 +.names PinD0 PinB0 n348 n349 n413 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names n88 n363 n414 +1- 1 +-1 1 +.names Psh2 n132 n207 n415 +0-- 1 +-1- 1 +--1 1 +.end diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/e64.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/e64.blif new file mode 100644 index 000000000..ec65989f1 --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/e64.blif @@ -0,0 +1,768 @@ +.model TOP +.inputs i_0_ i_1_ i_2_ i_3_ i_4_ i_5_ i_6_ i_7_ i_8_ i_9_ i_10_ i_11_ i_12_ \ +i_13_ i_14_ i_15_ i_16_ i_17_ i_18_ i_19_ i_20_ i_21_ i_22_ i_23_ i_24_ i_25_ \ +i_26_ i_27_ i_28_ i_29_ i_30_ i_31_ i_32_ i_33_ i_34_ i_35_ i_36_ i_37_ i_38_ \ +i_39_ i_40_ i_41_ i_42_ i_43_ i_44_ i_45_ i_46_ i_47_ i_48_ i_49_ i_50_ i_51_ \ +i_52_ i_53_ i_54_ i_55_ i_56_ i_57_ i_58_ i_59_ i_60_ i_61_ i_62_ i_63_ i_64_ +.outputs o_0_ o_1_ o_2_ o_3_ o_4_ o_5_ o_6_ o_7_ o_8_ o_9_ o_10_ o_11_ o_12_ \ +o_13_ o_14_ o_15_ o_16_ o_17_ o_18_ o_19_ o_20_ o_21_ o_22_ o_23_ o_24_ o_25_ \ +o_26_ o_27_ o_28_ o_29_ o_30_ o_31_ o_32_ o_33_ o_34_ o_35_ o_36_ o_37_ o_38_ \ +o_39_ o_40_ o_41_ o_42_ o_43_ o_44_ o_45_ o_46_ o_47_ o_48_ o_49_ o_50_ o_51_ \ +o_52_ o_53_ o_54_ o_55_ o_56_ o_57_ o_58_ o_59_ o_60_ o_61_ o_62_ o_63_ o_64_ +.names n178 o_0_ +0 1 +.names i_5_ n71 n83 n181 o_1_ +1000 1 +.names n172 o_2_ +0 1 +.names n168 o_3_ +0 1 +.names i_15_ i_29_ o_4_ +11 1 +.names i_14_ i_15_ n112 o_6_ +101 1 +.names i_15_ i_43_ n129 o_7_ +011 1 +.names n162 o_8_ +0 1 +.names n158 o_9_ +0 1 +.names i_15_ i_28_ i_29_ i_37_ o_10_ +0110 1 +.names i_15_ i_29_ i_37_ o_11_ +011 1 +.names i_6_ i_15_ i_24_ n14 n144 n195 o_12_ +100100 1 +.names i_41_ n151 n18 n132 o_13_ +1111 1 +.names i_50_ n154 o_14_ +11 1 +.names i_10_ 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i_35_ n46 n54 n55 n89 n88 +0------ 1 +-1----- 1 +--1---- 1 +---1--- 1 +----1-- 1 +-----1- 1 +------1 1 +.names i_58_ i_59_ i_60_ n187 n91 +0000 1 +.names i_60_ n187 n98 +1- 1 +-1 1 +.names i_50_ n203 n99 +1- 1 +-1 1 +.names n71 n231 n196 n208 n101 +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names i_59_ n72 n98 n99 n101 n97 +0---- 1 +-1--- 1 +--1-- 1 +---1- 1 +----1 1 +.names n225 n143 n104 +1- 1 +-1 1 +.names i_16_ n199 n36 i_20_ i_21_ i_13_ n105 +1----- 1 +-1---- 1 +--1--- 1 +---1-- 1 +----1- 1 +-----1 1 +.names i_29_ i_30_ n106 +0- 1 +-1 1 +.names i_19_ i_32_ n20 n77 n79 n104 n105 n106 n102 +0------- 1 +-1------ 1 +--1----- 1 +---1---- 1 +----1--- 1 +-----1-- 1 +------1- 1 +-------1 1 +.names i_58_ n66 n108 +00 1 +.names i_40_ i_43_ n14 n78 n214 n110 +00100 1 +.names i_43_ n129 n112 +01 1 +.names n82 n135 n125 i_30_ i_36_ n191 n117 +1----- 1 +-1---- 1 +--1--- 1 +---1-- 1 +----1- 1 +-----1 1 +.names n91 n188 n223 n118 +0-- 1 +-1- 1 +--1 1 +.names i_21_ n50 n117 n118 n115 +0--- 1 +-1-- 1 +--1- 1 +---1 1 +.names i_10_ n198 n121 +00 1 +.names i_18_ n219 n221 n125 +1-- 1 +-1- 1 +--1 1 +.names i_36_ n165 n212 n127 +1-- 1 +-1- 1 +--1 1 +.names i_32_ n79 n105 n125 n127 n124 +0---- 1 +-1--- 1 +--1-- 1 +---1- 1 +----1 1 +.names i_37_ n205 n129 +00 1 +.names i_15_ n192 n132 +01 1 +.names n79 n199 n36 n135 +1-- 1 +-1- 1 +--1 1 +.names i_16_ i_21_ i_29_ n104 n127 n135 n133 +0----- 1 +-1---- 1 +--0--- 1 +---1-- 1 +----1- 1 +-----1 1 +.names i_48_ n184 n137 +1- 1 +-1 1 +.names i_49_ n73 n138 +1- 1 +-1 1 +.names i_57_ i_62_ n188 n203 n204 n139 +1---- 1 +-1--- 1 +--1-- 1 +---1- 1 +----1 1 +.names i_36_ n22 n87 n89 n137 n138 n139 n136 +0------ 1 +-1----- 1 +--1---- 1 +---1--- 1 +----1-- 1 +-----1- 1 +------1 1 +.names i_10_ n197 n215 n142 +1-- 1 +-1- 1 +--1 1 +.names i_22_ i_18_ i_24_ n143 +1-- 1 +-1- 1 +--1 1 +.names i_62_ n16 n89 n106 n225 n144 +1---- 1 +-0--- 1 +--1-- 1 +---1- 1 +----1 1 +.names i_0_ i_3_ n142 n143 n144 n141 +0---- 1 +-1--- 1 +--1-- 1 +---1- 1 +----1 1 +.names i_28_ i_43_ n51 n106 n192 n214 n215 n216 n149 +1------- 1 +-1------ 1 +--1----- 1 +---1---- 1 +----0--- 1 +-----1-- 1 +------1- 1 +-------1 1 +.names i_7_ i_62_ n149 n148 +1-- 1 +-0- 1 +--1 1 +.names i_62_ n195 n151 +00 1 +.names i_58_ n112 n121 n154 +011 1 +.names n164 n191 i_52_ n190 n160 +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names i_19_ n105 n200 n161 +1-- 1 +-1- 1 +--1 1 +.names i_23_ n82 n160 n161 n158 +0--- 1 +-1-- 1 +--1- 1 +---1 1 +.names i_37_ i_39_ n163 +1- 1 +-1 1 +.names n79 n186 i_32_ i_36_ n164 +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names n139 n87 i_52_ n73 n32 n31 n72 n165 +1------ 1 +-1----- 1 +--1---- 1 +---1--- 1 +----1-- 1 +-----1- 1 +------1 1 +.names i_23_ n161 n167 +1- 1 +-1 1 +.names i_38_ n163 n164 n165 n167 n162 +0---- 1 +-1--- 1 +--1-- 1 +---1- 1 +----1 1 +.names n118 n138 n137 i_37_ i_52_ n202 n170 +1----- 1 +-1---- 1 +--1--- 1 +---1-- 1 +----1- 1 +-----1 1 +.names i_38_ i_39_ n171 +1- 1 +-1 1 +.names i_43_ i_44_ i_45_ n72 n164 n167 n170 n171 n168 +1------- 1 +-0------ 1 +--1----- 1 +---1---- 1 +----1--- 1 +-----1-- 1 +------1- 1 +-------1 1 +.names i_45_ n184 n174 +1- 1 +-1 1 +.names i_42_ i_43_ n175 +1- 1 +-1 1 +.names i_27_ i_38_ i_44_ n89 n160 n167 n174 n175 n172 +0------- 1 +-1------ 1 +--1----- 1 +---1---- 1 +----1--- 1 +-----1-- 1 +------1- 1 +-------1 1 +.names i_47_ n73 n179 +1- 1 +-1 1 +.names i_46_ i_43_ n180 +1- 1 +-1 1 +.names i_9_ n196 n222 n142 n33 n181 +1---- 1 +-1--- 1 +--1-- 1 +---1- 1 +----1 1 +.names i_5_ i_45_ n48 n87 n179 n180 n181 n178 +1------ 1 +-0----- 1 +--1---- 1 +---1--- 1 +----1-- 1 +-----1- 1 +------1 1 +.names i_40_ i_39_ n183 +1- 1 +-1 1 +.names i_47_ i_46_ n184 +1- 1 +-1 1 +.names i_37_ n183 n185 +00 1 +.names i_28_ n106 n186 +1- 1 +-1 1 +.names i_61_ i_62_ n187 +1- 1 +-1 1 +.names i_63_ i_64_ n188 +1- 1 +-1 1 +.names i_54_ n66 n189 +1- 1 +-1 1 +.names n98 n189 i_51_ n188 i_59_ i_58_ i_57_ i_53_ n190 +1------- 1 +-1------ 1 +--1----- 1 +---1---- 1 +----1--- 1 +-----1-- 1 +------1- 1 +-------1 1 +.names i_48_ i_49_ i_50_ n191 +1-- 1 +-1- 1 +--1 1 +.names i_24_ i_25_ n192 +00 1 +.names i_26_ n192 n193 +1- 1 +-0 1 +.names i_8_ i_7_ n195 +1- 1 +-1 1 +.names i_4_ i_0_ i_3_ n196 +1-- 1 +-1- 1 +--1 1 +.names i_6_ n195 n197 +1- 1 +-1 1 +.names i_15_ i_14_ n198 +1- 1 +-1 1 +.names n198 n37 i_12_ i_17_ n199 +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names i_22_ i_18_ n193 n200 +1-- 1 +-1- 1 +--1 1 +.names i_53_ i_54_ n202 +1- 1 +-1 1 +.names i_56_ i_58_ n203 +1- 1 +-1 1 +.names i_59_ i_61_ i_60_ n204 +1-- 1 +-1- 1 +--1 1 +.names i_28_ i_29_ n205 +1- 1 +-0 1 +.names i_14_ n61 n208 +1- 1 +-1 1 +.names i_30_ n163 n212 +1- 1 +-1 1 +.names i_60_ n203 n214 +1- 1 +-1 1 +.names i_11_ n198 n215 +1- 1 +-1 1 +.names i_8_ i_10_ n216 +1- 1 +-1 1 +.names i_26_ n205 n219 +1- 1 +-1 1 +.names i_22_ n192 n221 +1- 1 +-0 1 +.names n186 n200 n222 +1- 1 +-1 1 +.names i_57_ n66 n223 +1- 1 +-1 1 +.names i_41_ n183 n224 +1- 1 +-1 1 +.names i_25_ i_26_ i_28_ n225 +1-- 1 +-1- 1 +--1 1 +.names i_0_ i_3_ n142 n226 +1-- 1 +-1- 1 +--1 1 +.names i_41_ n104 n106 n179 n180 n185 n226 n227 +1------ 1 +-1----- 1 +--1---- 1 +---1--- 1 +----1-- 1 +-----0- 1 +------1 1 +.names n82 n86 n50 n228 +1-- 1 +-1- 1 +--1 1 +.names n91 n191 n228 n229 +0-- 1 +-1- 1 +--1 1 +.names i_55_ i_51_ n197 n70 n35 n231 +1---- 1 +-1--- 1 +--1-- 1 +---1- 1 +----1 1 +.names i_21_ n190 n117 n232 +1-- 1 +-1- 1 +--1 1 +.names i_29_ o_5_ +1 1 +.end diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/elliptic.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/elliptic.blif new file mode 100644 index 000000000..d395d2dc4 --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/elliptic.blif @@ -0,0 +1,1479 @@ +.model TOP +.inputs PCLK PRESET Preset_0_0_ Pinp_0_0_ Pinp_1_1_ Pinp_2_2_ Pinp_3_3_ \ +Pinp_4_4_ Pinp_5_5_ Pinp_6_6_ Pinp_7_7_ Pinp_8_8_ Pinp_9_9_ Pinp_10_10_ \ +Pinp_11_11_ Pinp_12_12_ Pinp_13_13_ Pinp_14_14_ Pinp_15_15_ +.outputs PDN Pover_0_0_ +.latch N_N8025 N_N8199 re PCLK 2 +.latch N_N9279 N_N9280 re PCLK 2 +.latch N_N8802 N_N8803 re PCLK 2 +.latch N_N7548 N_N8240 re PCLK 2 +.latch N_N6924 N_N8274 re PCLK 2 +.latch N_N7048 N_N8198 re PCLK 2 +.latch N_N7371 N_N8239 re PCLK 2 +.latch N_N8614 N_N8615 re PCLK 2 +.latch N_N7294 N_N7703 re PCLK 2 +.latch N_N7007 N_N8273 re PCLK 2 +.latch N_N8365 N_N8366 re PCLK 2 +.latch N_N7894 N_N8272 re PCLK 2 +.latch N_N6941 N_N8238 re PCLK 2 +.latch N_N7547 N_N8531 re PCLK 2 +.latch N_N7982 N_N7983 re PCLK 2 +.latch N_N7131 N_N8575 re PCLK 2 +.latch N_N7000 N_N7854 re PCLK 2 +.latch N_N7633 N_N8237 re PCLK 2 +.latch N_N7447 N_N8197 re PCLK 2 +.latch N_N7047 N_N8271 re PCLK 2 +.latch N_N6982 N_N8530 re PCLK 2 +.latch N_N7785 N_N8650 re PCLK 2 +.latch N_N7984 N_N7985 re PCLK 2 +.latch N_N8709 N_N8710 re PCLK 2 +.latch N_N7006 N_N8574 re PCLK 2 +.latch N_N8311 N_N8312 re PCLK 2 +.latch N_N8190 N_N8270 re PCLK 2 +.latch N_N7063 N_N8573 re PCLK 2 +.latch N_N8934 N_N8935 re PCLK 2 +.latch N_N7280 N_N8649 re PCLK 2 +.latch N_N7893 N_N8196 re PCLK 2 +.latch N_N8137 N_N8236 re PCLK 2 +.latch N_N9243 N_N9244 re PCLK 2 +.latch N_N8347 N_N8348 re PCLK 2 +.latch N_N9149 N_N9150 re PCLK 2 +.latch N_N7194 N_N8648 re PCLK 2 +.latch N_N7313 N_N8269 re PCLK 2 +.latch N_N7465 N_N8235 re PCLK 2 +.latch N_N9274 N_N9275 re PCLK 2 +.latch N_N8969 N_N8970 re PCLK 2 +.latch N_N7266 N_N9554 re PCLK 2 +.latch N_N9012 N_N9013 re PCLK 2 +.latch N_N8507 N_N8508 re PCLK 2 +.latch N_N8136 N_N8529 re PCLK 2 +.latch N_N9241 N_N9242 re PCLK 2 +.latch N_N8169 N_N8572 re PCLK 2 +.latch N_N7312 N_N8571 re PCLK 2 +.latch N_N8363 N_N9436 re PCLK 2 +.latch N_N7377 N_N8528 re PCLK 2 +.latch N_N8795 N_N8796 re PCLK 2 +.latch N_N7001 N_N7770 re PCLK 2 +.latch N_N8364 N_N9357 re PCLK 2 +.latch N_N8684 N_N8685 re PCLK 2 +.latch N_N9295 N_N9296 re PCLK 2 +.latch N_N6995 N_N9555 re PCLK 2 +.latch N_N6971 N_N7628 re PCLK 2 +.latch N_N9509 N_N9510 re PCLK 2 +.latch N_N9577 N_N9578 re PCLK 2 +.latch N_N8446 N_N8447 re PCLK 2 +.latch N_N7137 N_N9437 re PCLK 2 +.latch N_N7042 N_N7771 re PCLK 2 +.latch N_N7305 N_N8570 re PCLK 2 +.latch N_N8527 N_N8647 re PCLK 2 +.latch N_N6957 N_N7704 re PCLK 2 +.latch N_N6926 N_N8646 re PCLK 2 +.latch N_N6958 N_N7629 re PCLK 2 +.latch N_N7096 NDN3_11 re PCLK 2 +.latch N_N7460 NDN3_12 re PCLK 2 +.latch N_N8036 N_N8037 re PCLK 2 +.latch N_N8540 NDN3_16 re PCLK 2 +.latch N_N7087 NDN3_17 re PCLK 2 +.latch N_N9543 NDN3_19 re PCLK 2 +.latch N_N7883 NDN3_22 re PCLK 2 +.latch N_N8293 NDN3_25 re PCLK 2 +.latch N_N9328 NDN3_26 re PCLK 2 +.latch N_N7301 N_N7584 re PCLK 2 +.latch N_N9620 NDN3_28 re PCLK 2 +.latch N_N8217 NDN3_29 re PCLK 2 +.latch N_N7158 NDN3_40 re PCLK 2 +.latch N_N9425 NDN3_39 re PCLK 2 +.latch N_N7690 NDN3_42 re PCLK 2 +.latch N_N7232 NDN3_44 re PCLK 2 +.latch N_N7574 NDN3_46 re PCLK 2 +.latch N_N7608 N_N9358 re PCLK 2 +.latch N_N9538 N_N9539 re PCLK 2 +.latch N_N7795 N_N9556 re PCLK 2 +.latch N_N8147 N_N7306 re PCLK 2 +.latch N_N7038 NEN3_16 re PCLK 2 +.latch N_N9111 N_N9160 re PCLK 2 +.latch N_N7477 NEN3_19 re PCLK 2 +.latch N_N8299 NEN3_22 re PCLK 2 +.latch N_N7077 N_N8930 re PCLK 2 +.latch N_N7529 NEN3_28 re PCLK 2 +.latch N_N7796 N_N9438 re PCLK 2 +.latch N_N8825 NEN3_34 re PCLK 2 +.latch N_N7891 NEN3_36 re PCLK 2 +.latch N_N8317 NEN3_39 re PCLK 2 +.latch N_N7960 N_N7961 re PCLK 2 +.latch N_N8814 NLC1_2 re PCLK 2 +.latch N_N7126 N_N9359 re PCLK 2 +.latch N_N7475 N_N7476 re PCLK 2 +.latch N_N8576 N_N8577 re PCLK 2 +.latch N_N8178 N_N9289 re PCLK 2 +.latch N_N7397 N_N9557 re PCLK 2 +.latch N_N7238 N_N7630 re PCLK 2 +.latch N_N8829 N_N9161 re PCLK 2 +.latch N_N8690 N_N8691 re PCLK 2 +.latch N_N7449 N_N9439 re PCLK 2 +.latch N_N7747 N_N8798 re PCLK 2 +.latch N_N7750 N_N8869 re PCLK 2 +.latch N_N7450 N_N9360 re PCLK 2 +.latch N_N7535 N_N8911 re PCLK 2 +.latch N_N7451 N_N9290 re PCLK 2 +.latch N_N6942 N_N9558 re PCLK 2 +.latch N_N8181 N_N8993 re PCLK 2 +.latch N_N9039 N_N9162 re PCLK 2 +.latch N_N7538 N_N9034 re PCLK 2 +.latch N_N7998 N_N9440 re PCLK 2 +.latch N_N7799 N_N9361 re PCLK 2 +.latch N_N9297 N_N9298 re PCLK 2 +.latch N_N8737 N_N9559 re PCLK 2 +.latch N_N7193 N_N9163 re PCLK 2 +.latch N_N9549 N_N9550 re PCLK 2 +.latch N_N7729 PDN re PCLK 2 +.latch N_N8170 N_N8171 re PCLK 2 +.latch N_N8172 N_N8173 re PCLK 2 +.latch N_N8385 N_N9011 re PCLK 2 +.latch N_N9551 N_N9552 re PCLK 2 +.latch N_N7515 N_N7701 re PCLK 2 +.latch N_N8286 N_N8964 re PCLK 2 +.latch N_N7957 N_N9291 re PCLK 2 +.latch N_N8345 N_N9560 re PCLK 2 +.latch N_N6917 N_N7627 re PCLK 2 +.latch N_N7095 N_N8913 re PCLK 2 +.latch N_N8755 N_N8756 re PCLK 2 +.latch N_N7059 N_N9164 re PCLK 2 +.latch N_N8015 N_N8016 re PCLK 2 +.latch N_N8952 N_N9441 re PCLK 2 +.latch N_N8283 N_N8847 re PCLK 2 +.latch N_N7094 N_N8631 re PCLK 2 +.latch N_N7870 N_N9362 re PCLK 2 +.latch N_N7199 Pover_0_0_ re PCLK 2 +.latch N_N7015 NDN1_4 re PCLK 2 +.latch N_N7439 N_N8561 re PCLK 2 +.latch N_N6927 N_N9292 re PCLK 2 +.latch N_N7470 N_N9561 re PCLK 2 +.latch N_N7098 NGFDN_3 re PCLK 2 +.latch N_N6928 N_N9165 re PCLK 2 +.latch N_N7382 N_N9442 re PCLK 2 +.latch N_N7528 N_N7768 re PCLK 2 +.latch N_N8117 N_N8118 re PCLK 2 +.latch N_N8122 NDN2_2 re PCLK 2 +.latch N_N8874 N_N8875 re PCLK 2 +.latch N_N7448 N_N7852 re PCLK 2 +.latch N_N7318 N_N7582 re PCLK 2 +.latch N_N9330 N_N9331 re PCLK 2 +.latch N_N7981 N_N9363 re PCLK 2 +.latch N_N9293 N_N9294 re PCLK 2 +.latch N_N9443 NDN3_2 re PCLK 2 +.latch N_N8565 NDN3_4 re PCLK 2 +.latch N_N8399 NDN3_7 re PCLK 2 +.latch N_N7188 NDN3_9 re PCLK 2 +.latch N_N9409 N_N9410 re PCLK 2 +.latch N_N8612 N_N8613 re PCLK 2 +.latch N_N8971 N_N8972 re PCLK 2 +.latch N_N9461 N_N9247 re PCLK 2 +.latch N_N7030 N_N9166 re PCLK 2 +.latch N_N8967 N_N8968 re PCLK 2 +.latch N_N8478 NAK3_13 re PCLK 2 +.latch N_N8451 N_N8668 re PCLK 2 +.latch N_N8922 N_N8923 re PCLK 2 +.latch N_N7162 N_N7769 re PCLK 2 +.latch N_N8926 N_N8933 re PCLK 2 +.latch N_N7163 N_N7702 re PCLK 2 +.latch N_N7828 N_N8978 re PCLK 2 +.latch N_N8140 N_N8141 re PCLK 2 +.latch N_N7132 N_N8200 re PCLK 2 +.latch N_N8722 N_N8929 re PCLK 2 +.latch N_N7446 N_N7853 re PCLK 2 +.latch N_N8356 N_N9031 re PCLK 2 +.latch N_N7379 N_N8241 re PCLK 2 +.latch N_N7357 N_N7583 re PCLK 2 +.latch N_N11 NSr3_13 re PCLK 2 +.latch N_N10 N_N9248 re PCLK 2 +.latch N_N9 NSr3_14 re PCLK 2 +.latch N_N8 NSr3_20 re PCLK 2 +.latch N_N7 N_N9198 re PCLK 2 +.latch N_N6 NSr3_23 re PCLK 2 +.latch N_N5 NSr3_30 re PCLK 2 +.latch N_N4 NSr3_35 re PCLK 2 +.latch N_N3 NSr3_37 re PCLK 2 +.latch N_N2 NSr3_38 re PCLK 2 +.latch N_N1 NSr1_2 re PCLK 2 +.latch N_N0 N_N8603 re PCLK 2 +.names NEN3_28 NDN3_28 n1826 N_N9620 +1-0 1 +-10 1 +.names PRESET n1323 N_N9578 n16 +11- 1 +-10 1 +.names n16 N_N9577 +0 1 +.names PRESET n2838 n22 +01 1 +.names N_N9552 n22 N_N9551 +11 1 +.names N_N9550 n22 N_N9549 +11 1 +.names NDN3_19 NEN3_19 n1826 N_N9543 +1-0 1 +-10 1 +.names N_N9539 n22 N_N9538 +11 1 +.names N_N9510 n22 N_N9509 +11 1 +.names PRESET n413 n3115 N_N9247 n41 +0-1- 1 +00-1 1 +.names n41 N_N9248 N_N9461 +11 1 +.names NDN3_2 n1607 n1826 N_N9443 +1-0 1 +-00 1 +.names NDN3_39 NEN3_39 n1826 N_N9425 +1-0 1 +-10 1 +.names N_N9410 n22 N_N9409 +11 1 +.names N_N9331 n22 N_N9330 +11 1 +.names NDN3_26 NDN3_25 n1826 N_N9328 +1-0 1 +-10 1 +.names N_N9298 n22 N_N9297 +11 1 +.names N_N9296 n22 N_N9295 +11 1 +.names N_N9294 n22 N_N9293 +11 1 +.names N_N9280 n22 N_N9279 +11 1 +.names N_N9275 n22 N_N9274 +11 1 +.names N_N9244 n22 N_N9243 +11 1 +.names N_N9242 n22 N_N9241 +11 1 +.names N_N9150 n22 N_N9149 +11 1 +.names PRESET n1323 N_N9160 n103 +11- 1 +-10 1 +.names n103 N_N9111 +0 1 +.names PRESET n1323 N_N9162 n126 +11- 1 +-10 1 +.names n126 N_N9039 +0 1 +.names N_N9013 n22 N_N9012 +11 1 +.names N_N8972 n22 N_N8971 +11 1 +.names N_N8970 n22 N_N8969 +11 1 +.names N_N8968 n22 N_N8967 +11 1 +.names N_N9441 n22 N_N8952 +11 1 +.names N_N8935 n22 N_N8934 +11 1 +.names PRESET n1804 n1807 N_N8933 n156 +1-1- 1 +-11- 1 +1--0 1 +-1-0 1 +.names n156 N_N8926 +0 1 +.names PRESET n1807 n1808 N_N8923 n157 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names n157 N_N8922 +0 1 +.names N_N8875 n22 N_N8874 +11 1 +.names PRESET n1323 N_N9161 n191 +11- 1 +-10 1 +.names n191 N_N8829 +0 1 +.names NEN3_34 n1826 NGFDN_3 n1855 n193 +0-1- 1 +-11- 1 +0--1 1 +-1-1 1 +.names n193 N_N8825 +0 1 +.names PRESET PDN n196 +00 1 +.names n196 NLC1_2 NSr1_2 N_N8814 +11- 1 +1-1 1 +.names N_N8803 n22 N_N8802 +11 1 +.names N_N8796 n22 N_N8795 +11 1 +.names N_N8756 n22 N_N8755 +11 1 +.names N_N9559 n22 N_N8737 +11 1 +.names N_N9198 n1799 n1800 n227 +101 1 +.names PRESET N_N8929 n227 N_N8722 +01- 1 +0-1 1 +.names N_N8710 n22 N_N8709 +11 1 +.names N_N8691 n22 N_N8690 +11 1 +.names N_N8685 n22 N_N8684 +11 1 +.names N_N8615 n22 N_N8614 +11 1 +.names N_N8613 n22 N_N8612 +11 1 +.names N_N8577 n22 N_N8576 +11 1 +.names NDN3_2 NDN3_4 n1826 N_N8565 +1-0 1 +-10 1 +.names NDN3_16 NEN3_16 n1826 N_N8540 +1-0 1 +-10 1 +.names N_N8647 n22 N_N8527 +11 1 +.names N_N8508 n22 N_N8507 +11 1 +.names PRESET n1798 N_N8478 +00 1 +.names PRESET n1798 n315 +01 1 +.names N_N8668 n315 N_N8451 +11 1 +.names N_N8447 n22 N_N8446 +11 1 +.names NDN3_4 NDN3_7 n1826 N_N8399 +1-0 1 +-10 1 +.names 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n1520 +11- 1 +1-0 1 +.names N_N8913 n1534 n1526 +1- 1 +-1 1 +.names n1526 n1534 N_N8913 n1523 +10- 1 +1-0 1 +.names N_N9031 n1546 n1530 +1- 1 +-1 1 +.names n1530 n1546 N_N9031 n1527 +10- 1 +1-0 1 +.names N_N8847 n1538 n1534 +1- 1 +-1 1 +.names n1534 n1538 N_N8847 n1531 +10- 1 +1-0 1 +.names N_N8631 n1542 n1538 +1- 1 +-1 1 +.names n1538 n1542 N_N8631 n1535 +10- 1 +1-0 1 +.names N_N8561 n1550 n1542 +1- 1 +-1 1 +.names n1542 n1550 N_N8561 n1539 +10- 1 +1-0 1 +.names N_N8993 n1507 n1546 +1- 1 +-1 1 +.names n1507 n1546 N_N8993 n1543 +01- 1 +-10 1 +.names N_N9034 n1530 n1550 +1- 1 +-1 1 +.names n1530 n1550 N_N9034 n1547 +01- 1 +-10 1 +.names NLC1_2 NSr1_2 n1608 +1- 1 +-0 1 +.names Preset_0_0_ n1608 n3136 n1607 +1-0 1 +-10 1 +.names n2851 n2849 n2858 n2853 n2847 n2845 n2977 n1799 +1111111 1 +.names N_N8930 n3111 n3112 n3118 n1800 +1--1 1 +-0-1 1 +--01 1 +.names N_N9198 n1799 n1800 n1798 +11- 1 +1-1 1 +.names N_N8668 n1798 n1802 +1- 1 +-1 1 +.names n1800 n1802 n3115 n1801 +1-0 1 +-10 1 +.names n1371 n1801 N_N8933 n3008 n1806 +1-0- 1 +-10- 1 +1--1 1 +-1-1 1 +.names N_N9248 N_N7306 N_N9247 n1805 +0-- 1 +-1- 1 +--0 1 +.names n1806 n1508 n1805 n1804 +11- 1 +1-1 1 +.names PRESET n3007 n1807 +1- 1 +-0 1 +.names n1361 n1801 N_N8923 n3008 n1809 +1-0- 1 +-10- 1 +1--1 1 +-1-1 1 +.names n1809 n1512 n1805 n1808 +11- 1 +1-1 1 +.names NGFDN_3 PRESET n1826 +1- 1 +-1 1 +.names NSr3_35 PRESET n1855 +1- 1 +-1 1 +.names n1411 n1801 N_N9011 n3008 n2066 +1-0- 1 +-10- 1 +1--1 1 +-1-1 1 +.names N_N9011 n2789 n2065 +01 1 +10 1 +.names n2066 n2065 n1805 n2064 +11- 1 +1-1 1 +.names n1406 n1801 N_N9031 n3008 n2080 +1-0- 1 +-10- 1 +1--1 1 +-1-1 1 +.names n2080 n1527 n1805 n2079 +11- 1 +1-1 1 +.names NSr3_38 PRESET n2093 +1- 1 +-1 1 +.names NSr3_23 PRESET n2099 +1- 1 +-1 1 +.names n1416 n1801 N_N8964 n3008 n2106 +1-0- 1 +-10- 1 +1--1 1 +-1-1 1 +.names N_N8964 n1526 n2105 +01 1 +10 1 +.names n2106 n2105 n1805 n2104 +11- 1 +1-1 1 +.names n1391 n1801 N_N8847 n3008 n2109 +1-0- 1 +-10- 1 +1--1 1 +-1-1 1 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net_320 S6_q re clk 2 +.latch net_321 S3_q re clk 2 +.latch net_322 S2_q re clk 2 +.latch net_324 S7_q re clk 2 +.latch net_325 S1_q re clk 2 +.latch net_326 S0_q re clk 2 +.names net_24 o0 +0 1 +.names net_25 o1 +0 1 +.names net_174 o2 +0 1 +.names net_26 o3 +0 1 +.names net_156 o4 +0 1 +.names net_27 o5 +0 1 +.names net_138 o6 +0 1 +.names net_108 o7 +0 1 +.names net_28 net_29 net_30 S0_q S2_q S4_q o8 +1----- 1 +-1---- 1 +--1--- 1 +---1-- 1 +----1- 1 +-----1 1 +.names net_31 o9 +0 1 +.names net_32 o10 +0 1 +.names i0 S3_q net_254 net_295 net_326 +0--0 1 +010- 1 +.names S7_q net_237 net_242 net_6 +0-1 1 +-11 1 +.names net_6 net_325 +0 1 +.names i7 i5 net_104 net_182 net_222 net_8 +1---- 1 +-1--- 1 +--1-- 1 +---1- 1 +----1 1 +.names net_209 net_223 net_9 +1- 1 +-1 1 +.names S0_q net_217 net_11 +0- 1 +-1 1 +.names net_8 net_9 net_11 S6_q net_7 +1110 1 +.names S7_q net_261 net_13 +0- 1 +-1 1 +.names i3 net_43 net_182 net_244 net_14 +1--- 1 +-1-- 1 +--1- 1 +---0 1 +.names S0_q S1_q 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net_248 +11 1 +.names i1 i2 i3 net_252 +10- 1 +-01 1 +1-0 1 +.names net_248 net_252 net_251 +11 1 +.names i4 i7 net_143 net_250 net_254 +1--- 1 +-0-- 1 +--1- 1 +---1 1 +.names i5 net_143 net_255 +1- 1 +-1 1 +.names i7 net_45 net_255 net_256 +0-- 1 +-1- 1 +--1 1 +.names i5 net_162 net_250 net_257 +000 1 +.names i5 i7 net_259 +0- 1 +-1 1 +.names net_136 net_121 net_260 +1- 1 +-1 1 +.names net_125 net_235 i4 net_64 net_261 +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names i5 net_51 i0 i2 net_262 +1111 1 +.names i5 i6 net_64 net_263 +11- 1 +1-1 1 +-01 1 +.names i3 i4 net_121 net_125 net_264 +0-11 1 +-111 1 +.names net_115 net_101 net_45 net_267 +11- 1 +1-1 1 +.names i0 net_249 net_269 +1- 1 +-1 1 +.names i4 net_44 net_240 net_269 net_268 +01-1 1 +-111 1 +.names i2 net_65 net_128 net_271 +11- 1 +0-1 1 +-11 1 +.names i1 i3 net_62 net_271 net_270 +0-11 1 +-011 1 +.names i0 net_254 net_272 +1- 1 +-1 1 +.names i1 i7 net_222 net_274 +1-- 1 +-1- 1 +--1 1 +.names i3 i5 net_206 net_274 net_273 +-0-1 1 +0-11 1 +.names i0 i4 i7 S7_q net_255 net_275 +0---- 1 +-1--- 1 +--1-- 1 +---0- 1 +----1 1 +.names i2 net_222 net_277 +01 1 +.names i0 S5_q net_98 net_235 net_278 +1--- 1 +-0-- 1 +--1- 1 +---1 1 +.names i5 net_182 net_222 net_255 net_279 +0--1 1 +-111 1 +.names S3_q net_125 net_247 net_280 +0-- 1 +-1- 1 +--1 1 +.names i0 i1 i5 i6 net_281 +11-- 1 +1-1- 1 +-1-0 1 +--10 1 +.names i1 i3 i4 net_98 net_282 +10-- 1 +-00- 1 +1--1 1 +--01 1 +.names i2 net_107 net_259 net_285 +01- 1 +1-1 1 +-11 1 +.names i2 net_191 net_222 net_284 +11- 1 +0-1 1 +-11 1 +.names i4 i7 net_208 net_255 net_286 +0-0- 1 +00-0 1 +.names i2 S4_q S5_q net_51 net_290 +-00- 1 +00-1 1 +.names i6 net_95 net_292 +0- 1 +-1 1 +.names i2 i7 net_293 +0- 1 +-0 1 +.names i5 net_121 net_143 net_153 net_294 +0--- 1 +-1-- 1 +--1- 1 +---1 1 +.names S7_q net_243 net_260 net_295 +00- 1 +-01 1 +.names i0 i4 i6 net_45 net_297 +-0-0 1 +000- 1 +.names i2 i6 net_299 +0- 1 +-0 1 +.names i2 i3 i4 i5 net_300 +010- 1 +0-00 1 +.names i1 net_245 net_249 net_303 +11- 1 +0-0 1 +-10 1 +.names i3 i4 i6 net_306 +0-- 1 +-1- 1 +--1 1 +.names i4 net_125 net_306 net_305 +0-1 1 +-11 1 +.names i0 i2 net_51 net_244 net_309 +0011 1 +.names net_7 net_324 +0 1 +.names net_21 net_318 +0 1 +.names net_12 net_322 +0 1 +.end diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/i2c.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/i2c.blif new file mode 100644 index 000000000..e7cbdfcf8 --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/i2c.blif @@ -0,0 +1,2669 @@ +# Benchmark "i2c" written by ABC on Mon Aug 29 15:33:09 2005 +.model i2c +.inputs wb_clk_i wb_rst_i arst_i wb_we_i wb_stb_i wb_cyc_i scl_pad_i \ + sda_pad_i wb_adr_i[0] wb_adr_i[1] wb_adr_i[2] wb_dat_i[0] wb_dat_i[1] \ + wb_dat_i[2] wb_dat_i[3] wb_dat_i[4] wb_dat_i[5] wb_dat_i[6] wb_dat_i[7] +.outputs wb_dat_o[0] wb_dat_o[1] wb_dat_o[2] wb_dat_o[3] wb_dat_o[4] \ + wb_dat_o[5] wb_dat_o[6] wb_dat_o[7] wb_ack_o wb_inta_o scl_pad_o \ + scl_padoen_o sda_pad_o sda_padoen_o + +.latch byte_controller_bit_controller_sda_oen_reg_in byte_controller_bit_controller_sda_oen_reg 1 +.latch byte_controller_bit_controller_scl_oen_reg_in byte_controller_bit_controller_scl_oen_reg 1 +.latch \byte_controller_bit_controller_cnt_reg[15]_in \byte_controller_bit_controller_cnt_reg[15] 0 +.latch byte_controller_bit_controller_al_reg_in byte_controller_bit_controller_al_reg 0 +.latch \byte_controller_bit_controller_c_state_reg[8]_in \byte_controller_bit_controller_c_state_reg[8] 0 +.latch \byte_controller_bit_controller_c_state_reg[13]_in \byte_controller_bit_controller_c_state_reg[13] 0 +.latch \byte_controller_bit_controller_c_state_reg[9]_in \byte_controller_bit_controller_c_state_reg[9] 0 +.latch \byte_controller_bit_controller_c_state_reg[4]_in \byte_controller_bit_controller_c_state_reg[4] 0 +.latch \byte_controller_bit_controller_c_state_reg[3]_in \byte_controller_bit_controller_c_state_reg[3] 0 +.latch \byte_controller_bit_controller_c_state_reg[16]_in \byte_controller_bit_controller_c_state_reg[16] 0 +.latch \byte_controller_bit_controller_c_state_reg[7]_in \byte_controller_bit_controller_c_state_reg[7] 0 +.latch \byte_controller_bit_controller_c_state_reg[15]_in \byte_controller_bit_controller_c_state_reg[15] 0 +.latch \byte_controller_bit_controller_c_state_reg[12]_in \byte_controller_bit_controller_c_state_reg[12] 0 +.latch \byte_controller_bit_controller_c_state_reg[5]_in \byte_controller_bit_controller_c_state_reg[5] 0 +.latch \byte_controller_bit_controller_c_state_reg[6]_in \byte_controller_bit_controller_c_state_reg[6] 0 +.latch \byte_controller_bit_controller_cnt_reg[13]_in \byte_controller_bit_controller_cnt_reg[13] 0 +.latch \byte_controller_bit_controller_c_state_reg[10]_in \byte_controller_bit_controller_c_state_reg[10] 0 +.latch \byte_controller_bit_controller_c_state_reg[0]_in \byte_controller_bit_controller_c_state_reg[0] 0 +.latch \byte_controller_bit_controller_c_state_reg[11]_in \byte_controller_bit_controller_c_state_reg[11] 0 +.latch \byte_controller_bit_controller_c_state_reg[1]_in \byte_controller_bit_controller_c_state_reg[1] 0 +.latch \byte_controller_bit_controller_cnt_reg[14]_in \byte_controller_bit_controller_cnt_reg[14] 0 +.latch \byte_controller_bit_controller_c_state_reg[2]_in \byte_controller_bit_controller_c_state_reg[2] 0 +.latch \byte_controller_bit_controller_c_state_reg[14]_in \byte_controller_bit_controller_c_state_reg[14] 0 +.latch byte_controller_bit_controller_busy_reg_in byte_controller_bit_controller_busy_reg 0 +.latch \byte_controller_bit_controller_cnt_reg[11]_in \byte_controller_bit_controller_cnt_reg[11] 0 +.latch \byte_controller_core_cmd_reg[3]_in \byte_controller_core_cmd_reg[3] 0 +.latch \byte_controller_c_state_reg[1]_in \byte_controller_c_state_reg[1] 0 +.latch \byte_controller_c_state_reg[2]_in \byte_controller_c_state_reg[2] 0 +.latch \byte_controller_core_cmd_reg[2]_in \byte_controller_core_cmd_reg[2] 0 +.latch \byte_controller_core_cmd_reg[1]_in \byte_controller_core_cmd_reg[1] 0 +.latch \byte_controller_sr_reg[0]_in \byte_controller_sr_reg[0] 0 +.latch \byte_controller_sr_reg[1]_in \byte_controller_sr_reg[1] 0 +.latch \byte_controller_sr_reg[2]_in \byte_controller_sr_reg[2] 0 +.latch \byte_controller_sr_reg[3]_in \byte_controller_sr_reg[3] 0 +.latch \byte_controller_sr_reg[4]_in \byte_controller_sr_reg[4] 0 +.latch \byte_controller_sr_reg[5]_in \byte_controller_sr_reg[5] 0 +.latch \byte_controller_sr_reg[6]_in \byte_controller_sr_reg[6] 0 +.latch \byte_controller_sr_reg[7]_in \byte_controller_sr_reg[7] 0 +.latch \byte_controller_bit_controller_cnt_reg[3]_in \byte_controller_bit_controller_cnt_reg[3] 0 +.latch \byte_controller_dcnt_reg[2]_in \byte_controller_dcnt_reg[2] 0 +.latch \byte_controller_bit_controller_cnt_reg[2]_in \byte_controller_bit_controller_cnt_reg[2] 0 +.latch \byte_controller_bit_controller_cnt_reg[6]_in \byte_controller_bit_controller_cnt_reg[6] 0 +.latch \byte_controller_bit_controller_cnt_reg[1]_in \byte_controller_bit_controller_cnt_reg[1] 0 +.latch \byte_controller_bit_controller_cnt_reg[7]_in \byte_controller_bit_controller_cnt_reg[7] 0 +.latch \byte_controller_bit_controller_cnt_reg[0]_in \byte_controller_bit_controller_cnt_reg[0] 0 +.latch \byte_controller_bit_controller_cnt_reg[10]_in \byte_controller_bit_controller_cnt_reg[10] 0 +.latch \byte_controller_bit_controller_cnt_reg[5]_in \byte_controller_bit_controller_cnt_reg[5] 0 +.latch \byte_controller_bit_controller_cnt_reg[8]_in \byte_controller_bit_controller_cnt_reg[8] 0 +.latch \byte_controller_bit_controller_cnt_reg[9]_in \byte_controller_bit_controller_cnt_reg[9] 0 +.latch \byte_controller_bit_controller_cnt_reg[12]_in \byte_controller_bit_controller_cnt_reg[12] 0 +.latch \byte_controller_bit_controller_cnt_reg[4]_in \byte_controller_bit_controller_cnt_reg[4] 0 +.latch \byte_controller_dcnt_reg[0]_in \byte_controller_dcnt_reg[0] 0 +.latch \byte_controller_dcnt_reg[1]_in \byte_controller_dcnt_reg[1] 0 +.latch \byte_controller_c_state_reg[4]_in \byte_controller_c_state_reg[4] 0 +.latch byte_controller_bit_controller_clk_en_reg_in byte_controller_bit_controller_clk_en_reg 1 +.latch byte_controller_bit_controller_sta_condition_reg_in byte_controller_bit_controller_sta_condition_reg 0 +.latch byte_controller_core_txd_reg_in byte_controller_core_txd_reg 0 +.latch byte_controller_ack_out_reg_in byte_controller_ack_out_reg 0 +.latch \byte_controller_c_state_reg[3]_in \byte_controller_c_state_reg[3] 0 +.latch \byte_controller_core_cmd_reg[0]_in \byte_controller_core_cmd_reg[0] 0 +.latch byte_controller_bit_controller_dout_reg_in byte_controller_bit_controller_dout_reg 2 +.latch byte_controller_bit_controller_sto_condition_reg_in byte_controller_bit_controller_sto_condition_reg 0 +.latch \prer_reg[9]_in \prer_reg[9] 1 +.latch \prer_reg[11]_in \prer_reg[11] 1 +.latch \prer_reg[8]_in \prer_reg[8] 1 +.latch \prer_reg[15]_in \prer_reg[15] 1 +.latch \prer_reg[4]_in \prer_reg[4] 1 +.latch \prer_reg[0]_in \prer_reg[0] 1 +.latch \prer_reg[10]_in \prer_reg[10] 1 +.latch \prer_reg[12]_in \prer_reg[12] 1 +.latch \prer_reg[13]_in \prer_reg[13] 1 +.latch \prer_reg[14]_in \prer_reg[14] 1 +.latch \prer_reg[1]_in \prer_reg[1] 1 +.latch \prer_reg[2]_in \prer_reg[2] 1 +.latch \prer_reg[3]_in \prer_reg[3] 1 +.latch \prer_reg[5]_in \prer_reg[5] 1 +.latch \prer_reg[6]_in \prer_reg[6] 1 +.latch \prer_reg[7]_in \prer_reg[7] 1 +.latch \ctr_reg[3]_in \ctr_reg[3] 0 +.latch \ctr_reg[4]_in \ctr_reg[4] 0 +.latch \ctr_reg[5]_in \ctr_reg[5] 0 +.latch \ctr_reg[6]_in \ctr_reg[6] 0 +.latch \ctr_reg[7]_in \ctr_reg[7] 0 +.latch \wb_dat_o_reg[1]_in \wb_dat_o_reg[1] 2 +.latch \ctr_reg[2]_in \ctr_reg[2] 0 +.latch \byte_controller_c_state_reg[0]_in \byte_controller_c_state_reg[0] 0 +.latch \ctr_reg[0]_in \ctr_reg[0] 0 +.latch \ctr_reg[1]_in \ctr_reg[1] 0 +.latch \txr_reg[0]_in \txr_reg[0] 0 +.latch \txr_reg[1]_in \txr_reg[1] 0 +.latch \txr_reg[3]_in \txr_reg[3] 0 +.latch \txr_reg[4]_in \txr_reg[4] 0 +.latch \txr_reg[5]_in \txr_reg[5] 0 +.latch \txr_reg[7]_in \txr_reg[7] 0 +.latch \cr_reg[3]_in \cr_reg[3] 0 +.latch \cr_reg[4]_in \cr_reg[4] 0 +.latch \cr_reg[7]_in \cr_reg[7] 0 +.latch \cr_reg[6]_in \cr_reg[6] 0 +.latch \txr_reg[6]_in \txr_reg[6] 0 +.latch \txr_reg[2]_in \txr_reg[2] 0 +.latch \cr_reg[5]_in \cr_reg[5] 0 +.latch \wb_dat_o_reg[7]_in \wb_dat_o_reg[7] 2 +.latch \wb_dat_o_reg[4]_in \wb_dat_o_reg[4] 2 +.latch \wb_dat_o_reg[3]_in \wb_dat_o_reg[3] 2 +.latch \wb_dat_o_reg[2]_in \wb_dat_o_reg[2] 2 +.latch \wb_dat_o_reg[5]_in \wb_dat_o_reg[5] 2 +.latch byte_controller_ld_reg_in byte_controller_ld_reg 0 +.latch \wb_dat_o_reg[6]_in \wb_dat_o_reg[6] 2 +.latch \wb_dat_o_reg[0]_in \wb_dat_o_reg[0] 2 +.latch byte_controller_shift_reg_in byte_controller_shift_reg 0 +.latch byte_controller_cmd_ack_reg_in byte_controller_cmd_ack_reg 0 +.latch \cr_reg[0]_in \cr_reg[0] 0 +.latch \cr_reg[2]_in \cr_reg[2] 0 +.latch byte_controller_bit_controller_sda_chk_reg_in byte_controller_bit_controller_sda_chk_reg 0 +.latch byte_controller_bit_controller_dSDA_reg_in byte_controller_bit_controller_dSDA_reg 1 +.latch \cr_reg[1]_in \cr_reg[1] 0 +.latch byte_controller_bit_controller_cmd_ack_reg_in byte_controller_bit_controller_cmd_ack_reg 0 +.latch byte_controller_bit_controller_dSCL_reg_in byte_controller_bit_controller_dSCL_reg 1 +.latch byte_controller_bit_controller_cmd_stop_reg_in byte_controller_bit_controller_cmd_stop_reg 0 +.latch tip_reg_in tip_reg 0 +.latch irq_flag_reg_in irq_flag_reg 0 +.latch wb_inta_o_reg_in wb_inta_o_reg 0 +.latch byte_controller_bit_controller_sSCL_reg_in byte_controller_bit_controller_sSCL_reg 1 +.latch byte_controller_bit_controller_sSDA_reg_in byte_controller_bit_controller_sSDA_reg 1 +.latch rxack_reg_in rxack_reg 0 +.latch al_reg_in al_reg 0 +.latch wb_ack_o_reg_in wb_ack_o_reg 2 +.latch byte_controller_bit_controller_dscl_oen_reg_in byte_controller_bit_controller_dscl_oen_reg 2 + +.names [161] + 0 +.names [162] + 1 +.names [161] sda_pad_o +1 1 +.names [161] scl_pad_o +1 1 +.names byte_controller_bit_controller_sda_oen_reg sda_padoen_o +1 1 +.names byte_controller_bit_controller_scl_oen_reg \ + byte_controller_bit_controller_dscl_oen_reg_in +1 1 +.names [957] [777] byte_controller_bit_controller_sda_oen_reg_in +11 0 +.names [963] [777] byte_controller_bit_controller_scl_oen_reg_in +11 0 +.names \byte_controller_bit_controller_cnt_reg[15] [169] +1 1 +.names byte_controller_bit_controller_al_reg [170] +1 1 +.names \byte_controller_bit_controller_c_state_reg[8] [171] +1 1 +.names [555] [200] [865] byte_controller_bit_controller_al_reg_in +11- 0 +--1 0 +.names \byte_controller_bit_controller_c_state_reg[13] [173] +1 1 +.names \byte_controller_bit_controller_c_state_reg[9] [174] +1 1 +.names \byte_controller_bit_controller_c_state_reg[4] [175] +1 1 +.names \byte_controller_bit_controller_c_state_reg[3] [176] +1 1 +.names \byte_controller_bit_controller_c_state_reg[16] [177] +1 1 +.names \byte_controller_bit_controller_c_state_reg[7] [178] +1 1 +.names \byte_controller_bit_controller_c_state_reg[15] [179] +1 1 +.names \byte_controller_bit_controller_c_state_reg[12] [180] +1 1 +.names \byte_controller_bit_controller_c_state_reg[5] [181] +1 1 +.names \byte_controller_bit_controller_c_state_reg[6] [182] +1 1 +.names \byte_controller_bit_controller_cnt_reg[13] [183] +1 1 +.names \byte_controller_bit_controller_c_state_reg[10] [184] +1 1 +.names \byte_controller_bit_controller_c_state_reg[0] [185] +1 1 +.names \byte_controller_bit_controller_c_state_reg[11] [186] +1 1 +.names [239] [814] [1047] \byte_controller_bit_controller_c_state_reg[3]_in +11- 0 +--1 0 +.names [1120] sda_padoen_o [215] [188] +11- 0 +--1 0 +.names [231] [810] [1047] \byte_controller_bit_controller_c_state_reg[9]_in +11- 0 +--1 0 +.names [230] [809] [1047] \byte_controller_bit_controller_c_state_reg[7]_in +11- 0 +--1 0 +.names [229] [706] [790] \byte_controller_bit_controller_c_state_reg[16]_in +00- 1 +--0 1 +.names \byte_controller_bit_controller_c_state_reg[1] [192] +1 1 +.names \byte_controller_bit_controller_cnt_reg[14] [193] +1 1 +.names \byte_controller_bit_controller_c_state_reg[2] [194] +1 1 +.names \byte_controller_bit_controller_c_state_reg[14] [195] +1 1 +.names byte_controller_bit_controller_busy_reg [196] +1 1 +.names [210] [197] +0 1 +.names [269] [697] [819] \byte_controller_bit_controller_c_state_reg[5]_in +11- 0 +--1 0 +.names [268] [502] [733] \byte_controller_bit_controller_c_state_reg[10]_in +00- 1 +--0 1 +.names [576] [262] [722] [262] [200] +11-- 0 +--11 0 +.names [268] [605] [792] \byte_controller_bit_controller_c_state_reg[11]_in +00- 1 +--0 1 +.names [266] [812] [1047] \byte_controller_bit_controller_c_state_reg[6]_in +11- 0 +--1 0 +.names [265] [696] [1047] \byte_controller_bit_controller_c_state_reg[0]_in +11- 0 +--1 0 +.names [786] [233] \byte_controller_bit_controller_c_state_reg[12]_in +11 0 +.names [788] [235] \byte_controller_bit_controller_c_state_reg[15]_in +11 0 +.names \byte_controller_bit_controller_cnt_reg[11] [206] +1 1 +.names \byte_controller_core_cmd_reg[3] [207] +1 1 +.names \byte_controller_c_state_reg[1] [208] +1 1 +.names \byte_controller_c_state_reg[2] [209] +1 1 +.names [1120] [1023] [276] [210] +111 0 +.names [785] [263] \byte_controller_bit_controller_c_state_reg[14]_in +11 0 +.names [967] \byte_controller_bit_controller_c_state_reg[1]_in +0 1 +.names [238] \byte_controller_bit_controller_c_state_reg[2]_in +0 1 +.names [275] [916] [264] byte_controller_bit_controller_busy_reg_in +11- 0 +--1 0 +.names [267] [1120] [215] +00 1 +.names \byte_controller_core_cmd_reg[2] [216] +1 1 +.names \byte_controller_core_cmd_reg[1] [217] +1 1 +.names \byte_controller_sr_reg[0] [218] +1 1 +.names \byte_controller_sr_reg[1] [219] +1 1 +.names \byte_controller_sr_reg[2] [220] +1 1 +.names \byte_controller_sr_reg[3] [221] +1 1 +.names \byte_controller_sr_reg[4] [222] +1 1 +.names \byte_controller_sr_reg[5] [223] +1 1 +.names \byte_controller_sr_reg[6] [224] +1 1 +.names \byte_controller_sr_reg[7] [225] +1 1 +.names \byte_controller_bit_controller_cnt_reg[3] [226] +1 1 +.names [1122] [841] \byte_controller_core_cmd_reg[3]_in +11 1 +.names \byte_controller_dcnt_reg[2] [228] +1 1 +.names [277] [821] [990] [995] [229] +1111 0 +.names [507] [1183] [879] [745] [230] +1111 0 +.names [976] [1074] [874] [868] [231] +1111 0 +.names [290] [525] [1047] \byte_controller_c_state_reg[2]_in +11- 0 +--1 0 +.names [684] [627] [982] [335] [233] +1111 0 +.names \byte_controller_bit_controller_cnt_reg[2] [234] +1 1 +.names [772] [736] [335] [591] [235] +1111 0 +.names [289] [1296] [1047] \byte_controller_c_state_reg[1]_in +11- 0 +--1 0 +.names \byte_controller_bit_controller_cnt_reg[6] [237] +1 1 +.names [688] [992] [1046] [1209] [238] +11-- 0 +--11 0 +.names [1178] [838] [988] [239] +111 0 +.names \byte_controller_bit_controller_cnt_reg[1] [240] +1 1 +.names \byte_controller_bit_controller_cnt_reg[7] [241] +1 1 +.names \byte_controller_bit_controller_cnt_reg[0] [242] +1 1 +.names \byte_controller_bit_controller_cnt_reg[10] [243] +1 1 +.names \byte_controller_bit_controller_cnt_reg[5] [244] +1 1 +.names \byte_controller_bit_controller_cnt_reg[8] [245] +1 1 +.names \byte_controller_bit_controller_cnt_reg[9] [246] +1 1 +.names \byte_controller_bit_controller_cnt_reg[12] [247] +1 1 +.names \byte_controller_bit_controller_cnt_reg[4] [248] +1 1 +.names \byte_controller_dcnt_reg[0] [249] +1 1 +.names \byte_controller_dcnt_reg[1] [250] +1 1 +.names [297] [841] \byte_controller_core_cmd_reg[2]_in +11 1 +.names [337] [321] [1279] \byte_controller_sr_reg[0]_in +11- 0 +--1 0 +.names [338] [322] [1279] \byte_controller_sr_reg[1]_in +11- 0 +--1 0 +.names [339] [323] [865] \byte_controller_sr_reg[2]_in +11- 0 +--1 0 +.names [340] [324] [865] \byte_controller_sr_reg[3]_in +11- 0 +--1 0 +.names [341] [325] [865] \byte_controller_sr_reg[4]_in +11- 0 +--1 0 +.names [342] [326] [1279] \byte_controller_sr_reg[5]_in +11- 0 +--1 0 +.names [343] [327] [1279] \byte_controller_sr_reg[6]_in +11- 0 +--1 0 +.names [344] [328] [1279] \byte_controller_sr_reg[7]_in +11- 0 +--1 0 +.names wb_rst_i [299] \byte_controller_bit_controller_cnt_reg[3]_in +00 1 +.names [1085] [169] [300] [261] +11- 0 +--1 0 +.names [291] [611] [262] +00 1 +.names [545] [335] [988] [772] [263] +1111 0 +.names [291] [880] [264] +11 0 +.names [292] [271] [1074] [287] [265] +1111 0 +.names [504] [335] [1207] [807] [266] +1111 0 +.names [276] [267] +0 1 +.names [277] [268] +0 1 +.names [850] [976] [874] [269] +111 0 +.names \byte_controller_c_state_reg[4] [270] +1 1 +.names byte_controller_bit_controller_clk_en_reg [271] +1 1 +.names [360] [391] [1279] \byte_controller_bit_controller_cnt_reg[1]_in +11- 0 +--1 0 +.names [361] [393] wb_rst_i \byte_controller_bit_controller_cnt_reg[2]_in +11- 0 +--1 0 +.names [386] [362] [1279] \byte_controller_bit_controller_cnt_reg[5]_in +11- 0 +--1 0 +.names byte_controller_bit_controller_sta_condition_reg [275] +0 1 +.names byte_controller_core_txd_reg [276] +1 1 +.names [293] [277] +0 1 +.names [699] [865] [336] \byte_controller_dcnt_reg[1]_in +00- 1 +--0 1 +.names [650] [865] [336] \byte_controller_dcnt_reg[2]_in +00- 1 +--0 1 +.names [390] [392] [1279] \byte_controller_bit_controller_cnt_reg[7]_in +11- 0 +--1 0 +.names [848] [865] [336] \byte_controller_dcnt_reg[0]_in +00- 1 +--0 1 +.names [363] [388] wb_rst_i \byte_controller_bit_controller_cnt_reg[8]_in +11- 0 +--1 0 +.names [397] [387] wb_rst_i \byte_controller_bit_controller_cnt_reg[6]_in +11- 0 +--1 0 +.names [398] [389] wb_rst_i \byte_controller_bit_controller_cnt_reg[9]_in +11- 0 +--1 0 +.names byte_controller_ack_out_reg [285] +1 1 +.names \byte_controller_c_state_reg[3] [286] +1 1 +.names \byte_controller_core_cmd_reg[0] [287] +1 1 +.names byte_controller_bit_controller_dout_reg [288] +1 1 +.names [595] [787] [366] [289] +11- 0 +--1 0 +.names [597] [787] [367] [290] +11- 0 +--1 0 +.names byte_controller_bit_controller_sto_condition_reg [291] +0 1 +.names [892] [1005] [292] +00 1 +.names [1005] [825] [293] +11 0 +.names [357] [841] \byte_controller_c_state_reg[4]_in +11 1 +.names [331] byte_controller_bit_controller_clk_en_reg_in +0 1 +.names \prer_reg[9] [296] +0 1 +.names [365] [421] [525] [549] [297] +1111 0 +.names \prer_reg[11] [298] +0 1 +.names [1235] [464] [394] [299] +11- 0 +--1 0 +.names [169] [1085] [300] +00 1 +.names \prer_reg[8] [301] +0 1 +.names \prer_reg[15] [302] +0 1 +.names \prer_reg[4] [303] +0 1 +.names \prer_reg[0] [304] +0 1 +.names \prer_reg[10] [305] +0 1 +.names \prer_reg[12] [306] +0 1 +.names \prer_reg[13] [307] +0 1 +.names \prer_reg[14] [308] +0 1 +.names \prer_reg[1] [309] +0 1 +.names \prer_reg[2] [310] +0 1 +.names \prer_reg[3] [311] +0 1 +.names \prer_reg[5] [312] +0 1 +.names \prer_reg[6] [313] +0 1 +.names \prer_reg[7] [314] +0 1 +.names \ctr_reg[3] [315] +1 1 +.names \ctr_reg[4] [316] +1 1 +.names \ctr_reg[5] [317] +1 1 +.names \ctr_reg[6] [318] +1 1 +.names \ctr_reg[7] [319] +1 1 +.names \wb_dat_o_reg[1] wb_dat_o[1] +1 1 +.names [856] [405] [321] +00 0 +.names [857] [405] [322] +00 0 +.names [859] [405] [323] +00 0 +.names [858] [405] [324] +00 0 +.names [845] [405] [325] +00 0 +.names [855] [405] [326] +00 0 +.names [854] [405] [327] +00 0 +.names [847] [405] [328] +00 0 +.names [453] [660] [819] \byte_controller_c_state_reg[3]_in +11- 0 +--1 0 +.names \ctr_reg[2] [330] +1 1 +.names [1235] [1056] [865] [331] +11- 0 +--1 0 +.names [404] [648] byte_controller_bit_controller_sta_condition_reg_in +11 1 +.names [471] [455] [1047] byte_controller_ack_out_reg_in +11- 0 +--1 0 +.names [407] [1047] byte_controller_core_txd_reg_in +00 1 +.names [969] [335] +0 1 +.names [405] [1280] [336] +11 0 +.names [405] [349] [337] +11 0 +.names [405] [350] [338] +11 0 +.names [405] [395] [339] +11 0 +.names [405] [351] [340] +11 0 +.names [405] [352] [341] +11 0 +.names [405] [353] [342] +11 0 +.names [405] [364] [343] +11 0 +.names [405] [354] [344] +11 0 +.names [472] [452] [1047] \byte_controller_core_cmd_reg[0]_in +11- 0 +--1 0 +.names \byte_controller_c_state_reg[0] [346] +1 1 +.names \ctr_reg[0] [347] +1 1 +.names \ctr_reg[1] [348] +1 1 +.names \txr_reg[0] [349] +1 1 +.names \txr_reg[1] [350] +1 1 +.names \txr_reg[3] [351] +1 1 +.names \txr_reg[4] [352] +1 1 +.names \txr_reg[5] [353] +1 1 +.names \txr_reg[7] [354] +1 1 +.names \cr_reg[3] [355] +1 1 +.names \cr_reg[4] [356] +1 1 +.names [547] [530] [527] [1134] [357] +1111 0 +.names \cr_reg[7] [358] +1 1 +.names \cr_reg[6] [359] +1 1 +.names [1264] [498] [360] +11 0 +.names [1264] [499] [361] +11 0 +.names [1264] [500] [362] +11 0 +.names [1264] [490] [363] +11 0 +.names \txr_reg[6] [364] +1 1 +.names [1079] [660] [365] +11 1 +.names [596] [457] [599] [366] +111 0 +.names [630] [458] [1082] [367] +111 0 +.names [288] [741] [461] byte_controller_bit_controller_dout_reg_in +01- 1 +1-1 1 +.names [422] [880] \prer_reg[0]_in +11 0 +.names [423] [1280] \prer_reg[10]_in +11 0 +.names [424] [1280] \prer_reg[11]_in +11 0 +.names [425] [1280] \prer_reg[12]_in +11 0 +.names [426] [1280] \prer_reg[13]_in +11 0 +.names [427] [1280] \prer_reg[14]_in +11 0 +.names [428] [1280] \prer_reg[15]_in +11 0 +.names [429] [1280] \prer_reg[1]_in +11 0 +.names [430] [1280] \prer_reg[2]_in +11 0 +.names [420] [603] byte_controller_bit_controller_sto_condition_reg_in +11 1 +.names [431] [1280] \prer_reg[3]_in +11 0 +.names [432] [1280] \prer_reg[4]_in +11 0 +.names [433] [880] \prer_reg[5]_in +11 0 +.names [434] [1280] \prer_reg[6]_in +11 0 +.names [435] [880] \prer_reg[7]_in +11 0 +.names [436] [880] \prer_reg[8]_in +11 0 +.names [437] [1280] \prer_reg[9]_in +11 0 +.names [1235] [624] [386] +00 0 +.names [1275] [569] [387] +00 0 +.names [570] [1275] [388] +00 0 +.names [466] [1275] [389] +00 0 +.names [1264] [489] [390] +11 0 +.names [805] [1275] [391] +00 0 +.names [568] [1275] [392] +00 0 +.names [656] [1275] [393] +00 0 +.names [704] [679] [1235] [394] +11- 0 +--1 0 +.names \txr_reg[2] [395] +1 1 +.names \cr_reg[5] [396] +1 1 +.names [1264] [463] [397] +11 0 +.names [1264] [491] [398] +11 0 +.names \wb_dat_o_reg[7] wb_dat_o[7] +1 1 +.names \wb_dat_o_reg[4] wb_dat_o[4] +1 1 +.names \wb_dat_o_reg[3] wb_dat_o[3] +1 1 +.names \wb_dat_o_reg[2] wb_dat_o[2] +1 1 +.names \wb_dat_o_reg[5] wb_dat_o[5] +1 1 +.names [465] [740] [404] +00 1 +.names byte_controller_ld_reg [405] +1 1 +.names [503] [523] [1047] \byte_controller_c_state_reg[0]_in +11- 0 +--1 0 +.names [529] [225] [476] [407] +11- 0 +--1 0 +.names [477] [1279] \ctr_reg[1]_in +00 1 +.names [478] [865] \ctr_reg[2]_in +00 1 +.names [479] [1279] \ctr_reg[3]_in +00 1 +.names [480] [1279] \ctr_reg[4]_in +00 1 +.names [481] [865] \ctr_reg[5]_in +00 1 +.names [482] [865] \ctr_reg[6]_in +00 1 +.names [483] [865] \ctr_reg[7]_in +00 1 +.names [484] [1279] \ctr_reg[0]_in +00 1 +.names [663] [488] [735] [637] \wb_dat_o_reg[1]_in +1111 0 +.names [459] [599] [417] +11 0 +.names \wb_dat_o_reg[6] wb_dat_o[6] +1 1 +.names [936] [1226] [419] +00 1 +.names [501] [740] [420] +00 1 +.names [572] [1084] [658] [421] +11- 0 +--1 0 +.names [833] [927] [505] [422] +11- 0 +--1 0 +.names [833] [906] [506] [423] +11- 0 +--1 0 +.names [833] [903] [508] [424] +11- 0 +--1 0 +.names [833] [925] [509] [425] +11- 0 +--1 0 +.names [833] [910] [510] [426] +11- 0 +--1 0 +.names [833] [924] [511] [427] +11- 0 +--1 0 +.names [833] [911] [512] [428] +11- 0 +--1 0 +.names [870] [914] [513] [429] +11- 0 +--1 0 +.names [870] [930] [514] [430] +11- 0 +--1 0 +.names [870] [922] [515] [431] +11- 0 +--1 0 +.names [870] [904] [516] [432] +11- 0 +--1 0 +.names [833] [900] [517] [433] +11- 0 +--1 0 +.names [833] [928] [518] [434] +11- 0 +--1 0 +.names [833] [915] [519] [435] +11- 0 +--1 0 +.names [833] [918] [520] [436] +11- 0 +--1 0 +.names [833] [902] [521] [437] +11- 0 +--1 0 +.names [766] [546] [865] \cr_reg[4]_in +11- 0 +--1 0 +.names [765] [574] [865] \cr_reg[5]_in +11- 0 +--1 0 +.names [753] [575] [865] \cr_reg[6]_in +11- 0 +--1 0 +.names [767] [573] [865] \cr_reg[7]_in +11- 0 +--1 0 +.names [531] [1279] \txr_reg[0]_in +00 1 +.names [532] [1279] \txr_reg[1]_in +00 1 +.names [533] [865] \txr_reg[2]_in +00 1 +.names [534] [865] \txr_reg[3]_in +00 1 +.names [535] [865] \txr_reg[4]_in +00 1 +.names [536] [865] \txr_reg[5]_in +00 1 +.names [537] [865] \txr_reg[6]_in +00 1 +.names [538] [1279] \txr_reg[7]_in +00 1 +.names [539] [865] \cr_reg[3]_in +00 1 +.names \wb_dat_o_reg[0] wb_dat_o[0] +1 1 +.names [1100] [808] [571] [452] +11- 0 +--1 0 +.names [729] [813] [526] [453] +11- 0 +--1 0 +.names byte_controller_shift_reg [454] +1 1 +.names [554] [285] [560] [455] +11- 0 +--1 0 +.names byte_controller_cmd_ack_reg [456] +1 1 +.names [1080] [1216] [1139] [457] +111 0 +.names [1100] [1244] [1139] [458] +111 0 +.names [1100] [1126] [459] +11 0 +.names [884] [1204] [1197] [460] +01- 1 +1-1 1 +.names [553] [740] [461] +00 1 +.names [557] [1001] [462] +11 0 +.names [951] [1053] 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[1299] [1301] +0 1 +.names [1303] [1302] +0 1 +.names [1304] [1305] [1306] [1303] +111 0 +.names [346] [1304] +0 1 +.names [208] [1305] +0 1 +.names [209] [1306] +0 1 +.names byte_controller_bit_controller_dscl_oen_reg_in scl_padoen_o +1 1 +.end diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/int2float.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/int2float.blif new file mode 100644 index 000000000..d0f7e0f43 --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/int2float.blif @@ -0,0 +1,524 @@ +.model top +.inputs B[0] B[1] B[2] B[3] B[4] B[5] B[6] B[7] B[8] B[9] B[10] +.outputs M[0] M[1] M[2] M[3] E[0] E[1] E[2] +.names B[1] B[4] n19 +01 1 +.names B[4] B[8] n20 +00 1 +.names n19 n20 n21 +00 1 +.names B[0] n21 n22 +10 1 +.names B[1] B[4] n23 +11 1 +.names B[0] n23 n24 +01 1 +.names n22 n24 n25 +00 1 +.names B[6] n25 n26 +00 1 +.names B[7] n26 n27 +01 1 +.names B[4] B[8] n28 +11 1 +.names n27 n28 n29 +00 1 +.names B[5] n29 n30 +00 1 +.names B[4] B[7] n31 +01 1 +.names B[1] B[2] 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n277 E[2] +11 0 +.end diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/mult32a.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/mult32a.blif new file mode 100644 index 000000000..8c2c27cce --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/mult32a.blif @@ -0,0 +1,1033 @@ +## inputs 33 +## outputs 1 +## latches 32 +## initial 00000000000000000000000000000000 +# + + + +.model MultiplierA_32 +.inputs 1 3 4 5 6 7 8 9 10 11 +.inputs 12 13 14 15 16 17 18 19 20 21 +.inputs 22 23 24 25 26 27 28 29 30 31 +.inputs 32 33 34 + +.outputs 68 +.latch 67 2 0 +.latch 69 36 0 +.latch 70 37 0 +.latch 71 38 0 +.latch 72 39 0 +.latch 73 40 0 +.latch 74 41 0 +.latch 75 42 0 +.latch 76 43 0 +.latch 77 44 0 +.latch 78 45 0 +.latch 79 46 0 +.latch 80 47 0 +.latch 81 48 0 +.latch 82 49 0 +.latch 83 50 0 +.latch 84 51 0 +.latch 85 52 0 +.latch 86 53 0 +.latch 87 54 0 +.latch 88 55 0 +.latch 89 56 0 +.latch 90 57 0 +.latch 91 58 0 +.latch 92 59 0 +.latch 93 60 0 +.latch 94 61 0 +.latch 95 62 0 +.latch 96 63 0 +.latch 97 64 0 +.latch 98 65 0 +.latch 99 66 0 + +.names 101 100 +0 1 + +.names 1 204 101 +00 1 +11 1 + +.names 3 102 +1 1 + +.names 4 103 +1 1 + +.names 5 104 +1 1 + +.names 6 105 +1 1 + +.names 7 106 +1 1 + +.names 8 107 +1 1 + +.names 9 108 +1 1 + +.names 10 109 +1 1 + +.names 11 110 +1 1 + +.names 12 111 +1 1 + +.names 13 112 +1 1 + +.names 14 113 +1 1 + +.names 15 114 +1 1 + +.names 16 115 +1 1 + +.names 17 116 +1 1 + +.names 18 117 +1 1 + +.names 19 118 +1 1 + +.names 20 119 +1 1 + +.names 21 120 +1 1 + +.names 22 121 +1 1 + +.names 23 122 +1 1 + +.names 24 123 +1 1 + +.names 25 124 +1 1 + +.names 26 125 +1 1 + +.names 27 126 +1 1 + +.names 28 127 +1 1 + +.names 29 128 +1 1 + +.names 30 129 +1 1 + +.names 31 130 +1 1 + +.names 32 131 +1 1 + +.names 33 132 +1 1 + +.names 34 133 +1 1 + +.names 134 + +.names 135 + +.names 136 + +.names 137 + +.names 138 + +.names 139 + +.names 140 + +.names 141 + +.names 142 + +.names 143 + +.names 144 + +.names 145 + +.names 146 + +.names 147 + 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227 +-11 1 +1-1 1 +11- 1 + +.names 318 319 228 +-1 1 +1- 1 + +.names 47 227 228 229 +-11 1 +1-1 1 +11- 1 + +.names 316 317 230 +-1 1 +1- 1 + +.names 48 229 230 231 +-11 1 +1-1 1 +11- 1 + +.names 314 315 232 +-1 1 +1- 1 + +.names 49 231 232 233 +-11 1 +1-1 1 +11- 1 + +.names 312 313 234 +-1 1 +1- 1 + +.names 50 233 234 235 +-11 1 +1-1 1 +11- 1 + +.names 310 311 236 +-1 1 +1- 1 + +.names 51 235 236 237 +-11 1 +1-1 1 +11- 1 + +.names 308 309 238 +-1 1 +1- 1 + +.names 52 237 238 239 +-11 1 +1-1 1 +11- 1 + +.names 306 307 240 +-1 1 +1- 1 + +.names 53 239 240 241 +-11 1 +1-1 1 +11- 1 + +.names 304 305 242 +-1 1 +1- 1 + +.names 54 241 242 243 +-11 1 +1-1 1 +11- 1 + +.names 302 303 244 +-1 1 +1- 1 + +.names 55 243 244 245 +-11 1 +1-1 1 +11- 1 + +.names 300 301 246 +-1 1 +1- 1 + +.names 56 245 246 247 +-11 1 +1-1 1 +11- 1 + +.names 298 299 248 +-1 1 +1- 1 + +.names 57 247 248 249 +-11 1 +1-1 1 +11- 1 + +.names 296 297 250 +-1 1 +1- 1 + +.names 58 249 250 251 +-11 1 +1-1 1 +11- 1 + +.names 294 295 252 +-1 1 +1- 1 + +.names 59 251 252 253 +-11 1 +1-1 1 +11- 1 + +.names 292 293 254 +-1 1 +1- 1 + +.names 60 253 254 255 +-11 1 +1-1 1 +11- 1 + +.names 290 291 256 +-1 1 +1- 1 + +.names 61 255 256 257 +-11 1 +1-1 1 +11- 1 + +.names 288 289 258 +-1 1 +1- 1 + +.names 62 257 258 259 +-11 1 +1-1 1 +11- 1 + +.names 286 287 260 +-1 1 +1- 1 + +.names 63 259 260 261 +-11 1 +1-1 1 +11- 1 + +.names 284 285 262 +-1 1 +1- 1 + +.names 64 261 262 263 +-11 1 +1-1 1 +11- 1 + +.names 282 283 264 +-1 1 +1- 1 + +.names 65 263 264 265 +-11 1 +1-1 1 +11- 1 + +.names 280 281 266 +-1 1 +1- 1 + +.names 278 279 267 +-1 1 +1- 1 + +.names 166 267 268 +01 1 +10 1 + +.names 2 267 269 +11 1 + +.names 166 270 +0 1 + +.names 267 271 +0 1 + +.names 2 271 272 +11 1 + +.names 2 273 +0 1 + +.names 267 273 274 +11 1 + +.names 2 267 275 +11 1 + +.names 199 200 276 +-1 1 +1- 1 + +.names 201 202 277 +-1 1 +1- 1 + +.names 203 67 +1 1 + +.names 167 68 +1 1 + +.names 168 69 +1 1 + +.names 169 70 +1 1 + +.names 170 71 +1 1 + +.names 171 72 +1 1 + +.names 172 73 +1 1 + +.names 173 74 +1 1 + +.names 174 75 +1 1 + +.names 175 76 +1 1 + +.names 176 77 +1 1 + +.names 177 78 +1 1 + +.names 178 79 +1 1 + +.names 179 80 +1 1 + +.names 180 81 +1 1 + +.names 181 82 +1 1 + +.names 182 83 +1 1 + +.names 183 84 +1 1 + +.names 184 85 +1 1 + +.names 185 86 +1 1 + +.names 186 87 +1 1 + +.names 187 88 +1 1 + +.names 188 89 +1 1 + +.names 189 90 +1 1 + +.names 190 91 +1 1 + +.names 191 92 +1 1 + +.names 192 93 +1 1 + +.names 193 94 +1 1 + +.names 194 95 +1 1 + +.names 195 96 +1 1 + +.names 196 97 +1 1 + +.names 197 98 +1 1 + +.names 198 99 +1 1 + +.names 100 133 278 +11 1 + +.names 101 165 279 +11 1 + +.names 100 132 280 +11 1 + +.names 101 164 281 +11 1 + +.names 100 131 282 +11 1 + +.names 101 163 283 +11 1 + +.names 100 130 284 +11 1 + +.names 101 162 285 +11 1 + +.names 100 129 286 +11 1 + +.names 101 161 287 +11 1 + +.names 100 128 288 +11 1 + +.names 101 160 289 +11 1 + +.names 100 127 290 +11 1 + +.names 101 159 291 +11 1 + +.names 100 126 292 +11 1 + +.names 101 158 293 +11 1 + +.names 100 125 294 +11 1 + +.names 101 157 295 +11 1 + +.names 100 124 296 +11 1 + +.names 101 156 297 +11 1 + +.names 100 123 298 +11 1 + +.names 101 155 299 +11 1 + +.names 100 122 300 +11 1 + +.names 101 154 301 +11 1 + +.names 100 121 302 +11 1 + +.names 101 153 303 +11 1 + +.names 100 120 304 +11 1 + +.names 101 152 305 +11 1 + +.names 100 119 306 +11 1 + +.names 101 151 307 +11 1 + +.names 100 118 308 +11 1 + +.names 101 150 309 +11 1 + +.names 100 117 310 +11 1 + +.names 101 149 311 +11 1 + +.names 100 116 312 +11 1 + +.names 101 148 313 +11 1 + +.names 100 115 314 +11 1 + +.names 101 147 315 +11 1 + +.names 100 114 316 +11 1 + +.names 101 146 317 +11 1 + +.names 100 113 318 +11 1 + +.names 101 145 319 +11 1 + +.names 100 112 320 +11 1 + +.names 101 144 321 +11 1 + +.names 100 111 322 +11 1 + +.names 101 143 323 +11 1 + +.names 100 110 324 +11 1 + +.names 101 142 325 +11 1 + +.names 100 109 326 +11 1 + +.names 101 141 327 +11 1 + +.names 100 108 328 +11 1 + +.names 101 140 329 +11 1 + +.names 100 107 330 +11 1 + +.names 101 139 331 +11 1 + +.names 100 106 332 +11 1 + +.names 101 138 333 +11 1 + +.names 100 105 334 +11 1 + +.names 101 137 335 +11 1 + +.names 100 104 336 +11 1 + +.names 101 136 337 +11 1 + +.names 100 103 338 +11 1 + +.names 101 135 339 +11 1 + +.names 100 102 340 +11 1 + +.names 101 134 341 +11 1 + +.end diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/pci_conf_cyc_addr_dec.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/pci_conf_cyc_addr_dec.blif new file mode 100644 index 000000000..a0588d70f --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/pci_conf_cyc_addr_dec.blif @@ -0,0 +1,259 @@ +# Benchmark "pci_conf_cyc_addr_dec" written by ABC on Mon Aug 29 15:33:11 2005 +.model pci_conf_cyc_addr_dec +.inputs ccyc_addr_in[0] ccyc_addr_in[1] ccyc_addr_in[2] ccyc_addr_in[3] \ + ccyc_addr_in[4] ccyc_addr_in[5] ccyc_addr_in[6] ccyc_addr_in[7] \ + ccyc_addr_in[8] ccyc_addr_in[9] ccyc_addr_in[10] ccyc_addr_in[11] \ + ccyc_addr_in[12] ccyc_addr_in[13] ccyc_addr_in[14] ccyc_addr_in[15] \ + ccyc_addr_in[16] ccyc_addr_in[17] ccyc_addr_in[18] ccyc_addr_in[19] \ + ccyc_addr_in[20] ccyc_addr_in[21] ccyc_addr_in[22] ccyc_addr_in[23] \ + ccyc_addr_in[24] ccyc_addr_in[25] ccyc_addr_in[26] ccyc_addr_in[27] \ + ccyc_addr_in[28] ccyc_addr_in[29] ccyc_addr_in[30] ccyc_addr_in[31] +.outputs ccyc_addr_out[0] ccyc_addr_out[1] ccyc_addr_out[2] \ + ccyc_addr_out[3] ccyc_addr_out[4] ccyc_addr_out[5] ccyc_addr_out[6] \ + ccyc_addr_out[7] ccyc_addr_out[8] ccyc_addr_out[9] ccyc_addr_out[10] \ + ccyc_addr_out[11] ccyc_addr_out[12] ccyc_addr_out[13] ccyc_addr_out[14] \ + ccyc_addr_out[15] ccyc_addr_out[16] ccyc_addr_out[17] ccyc_addr_out[18] \ + ccyc_addr_out[19] ccyc_addr_out[20] ccyc_addr_out[21] ccyc_addr_out[22] \ + ccyc_addr_out[23] ccyc_addr_out[24] ccyc_addr_out[25] ccyc_addr_out[26] \ + ccyc_addr_out[27] ccyc_addr_out[28] ccyc_addr_out[29] ccyc_addr_out[30] \ + ccyc_addr_out[31] +.names [64] + 0 +.names [65] + 1 +.names ccyc_addr_in[1] ccyc_addr_out[1] +1 1 +.names ccyc_addr_in[2] ccyc_addr_out[2] +1 1 +.names ccyc_addr_in[3] ccyc_addr_out[3] +1 1 +.names ccyc_addr_in[4] ccyc_addr_out[4] +1 1 +.names ccyc_addr_in[5] ccyc_addr_out[5] +1 1 +.names ccyc_addr_in[6] ccyc_addr_out[6] +1 1 +.names ccyc_addr_in[7] ccyc_addr_out[7] +1 1 +.names ccyc_addr_in[8] ccyc_addr_out[8] +1 1 +.names ccyc_addr_in[9] ccyc_addr_out[9] +1 1 +.names ccyc_addr_in[10] ccyc_addr_out[10] +1 1 +.names [126] [98] [115] ccyc_addr_out[30] +00- 1 +--0 1 +.names [147] [98] [151] ccyc_addr_out[29] +00- 1 +--0 1 +.names [131] [97] [123] ccyc_addr_out[28] +00- 1 +--0 1 +.names [120] [97] [116] ccyc_addr_out[27] +00- 1 +--0 1 +.names [105] ccyc_addr_out[0] [143] ccyc_addr_out[31] +00- 1 +--0 1 +.names [134] [99] [118] ccyc_addr_out[26] +00- 1 +--0 1 +.names [142] [99] [138] ccyc_addr_out[25] +00- 1 +--0 1 +.names [145] [104] [144] ccyc_addr_out[24] +00- 1 +--0 1 +.names [122] [104] [148] ccyc_addr_out[23] +00- 1 +--0 1 +.names [121] [106] [152] ccyc_addr_out[22] +00- 1 +--0 1 +.names [119] [106] [117] ccyc_addr_out[21] +00- 1 +--0 1 +.names [128] [107] [133] ccyc_addr_out[20] +00- 1 +--0 1 +.names [130] [107] [125] ccyc_addr_out[19] +00- 1 +--0 1 +.names [137] [102] [132] ccyc_addr_out[18] +00- 1 +--0 1 +.names [139] [102] [135] ccyc_addr_out[17] +00- 1 +--0 1 +.names [140] [100] [141] ccyc_addr_out[16] +00- 1 +--0 1 +.names [129] [100] [158] ccyc_addr_out[15] +00- 1 +--0 1 +.names [146] [101] [153] ccyc_addr_out[14] +00- 1 +--0 1 +.names [149] [101] [154] ccyc_addr_out[13] +00- 1 +--0 1 +.names [150] [103] [157] ccyc_addr_out[12] +00- 1 +--0 1 +.names [124] [103] [136] ccyc_addr_out[11] +00- 1 +--0 1 +.names [108] [168] [97] +11 0 +.names [109] ccyc_addr_in[12] [98] +11 0 +.names [111] ccyc_addr_in[12] [99] +11 0 +.names [112] [168] [100] +11 0 +.names [113] ccyc_addr_in[12] [101] +11 0 +.names [112] ccyc_addr_in[12] [102] +11 0 +.names [113] [168] [103] +11 0 +.names [111] [168] [104] +11 0 +.names [155] [127] ccyc_addr_in[13] [105] +111 0 +.names [114] ccyc_addr_in[12] [106] +11 0 +.names [114] [168] [107] +11 0 +.names [110] [108] +0 1 +.names [110] [109] +0 1 +.names [171] [165] [167] [110] +111 0 +.names [156] [167] [111] +00 1 +.names [159] [167] [112] +00 1 +.names [159] ccyc_addr_in[13] [113] +00 1 +.names [156] ccyc_addr_in[13] [114] +00 1 +.names ccyc_addr_in[30] ccyc_addr_out[0] [115] +11 0 +.names ccyc_addr_in[27] ccyc_addr_out[0] [116] +11 0 +.names ccyc_addr_in[21] ccyc_addr_out[0] [117] +11 0 +.names ccyc_addr_in[26] ccyc_addr_out[0] [118] +11 0 +.names [163] ccyc_addr_out[0] [119] +00 0 +.names [163] ccyc_addr_out[0] [120] +00 0 +.names ccyc_addr_in[11] [162] [121] +11 0 +.names [163] ccyc_addr_out[0] [122] +00 0 +.names ccyc_addr_in[28] ccyc_addr_out[0] [123] +11 0 +.names [163] ccyc_addr_out[0] [124] +00 0 +.names ccyc_addr_in[19] ccyc_addr_out[0] [125] +11 0 +.names [160] [162] [126] +11 0 +.names [165] [171] [127] +11 1 +.names [160] [162] [128] +11 0 +.names [163] ccyc_addr_out[0] [129] +00 0 +.names [163] ccyc_addr_out[0] [130] +00 0 +.names [160] [162] [131] +11 0 +.names ccyc_addr_in[18] ccyc_addr_out[0] [132] +11 0 +.names ccyc_addr_in[20] ccyc_addr_out[0] [133] +11 0 +.names [160] [162] [134] +11 0 +.names ccyc_addr_in[17] ccyc_addr_out[0] [135] +11 0 +.names [160] ccyc_addr_out[0] [136] +11 0 +.names [160] [162] [137] +11 0 +.names ccyc_addr_in[25] ccyc_addr_out[0] [138] +11 0 +.names [163] ccyc_addr_out[0] [139] +00 0 +.names ccyc_addr_in[11] [162] [140] +11 0 +.names ccyc_addr_in[16] ccyc_addr_out[0] [141] +11 0 +.names [163] ccyc_addr_out[0] [142] +00 0 +.names ccyc_addr_in[31] ccyc_addr_out[0] [143] +11 0 +.names ccyc_addr_in[24] ccyc_addr_out[0] [144] +11 0 +.names [160] [162] [145] +11 0 +.names [160] [162] [146] +11 0 +.names [163] ccyc_addr_out[0] [147] +00 0 +.names ccyc_addr_in[23] ccyc_addr_out[0] [148] +11 0 +.names [163] ccyc_addr_in[0] [149] +00 0 +.names ccyc_addr_in[11] [162] [150] +11 0 +.names ccyc_addr_in[29] ccyc_addr_out[0] [151] +11 0 +.names ccyc_addr_in[22] ccyc_addr_out[0] [152] +11 0 +.names [165] [166] [153] +00 0 +.names [167] [166] [154] +00 0 +.names [163] ccyc_addr_in[12] [155] +00 1 +.names [172] ccyc_addr_in[14] [156] +11 0 +.names [168] [166] [157] +00 0 +.names [170] [166] [158] +00 0 +.names [172] [169] [159] +11 0 +.names [164] [160] +0 1 +.names [166] ccyc_addr_out[0] +0 1 +.names ccyc_addr_in[0] [162] +0 1 +.names ccyc_addr_in[11] [163] +1 1 +.names ccyc_addr_in[11] [164] +0 1 +.names ccyc_addr_in[14] [165] +0 1 +.names ccyc_addr_in[0] [166] +0 1 +.names ccyc_addr_in[13] [167] +0 1 +.names ccyc_addr_in[12] [168] +0 1 +.names ccyc_addr_in[14] [169] +0 1 +.names [171] [170] +0 1 +.names [172] [171] +0 1 +.names ccyc_addr_in[15] [172] +0 1 +.end diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/planet.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/planet.blif new file mode 100644 index 000000000..de95230e8 --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/planet.blif @@ -0,0 +1,324 @@ +.model planet.kiss2 +.inputs v0 v1 v2 v3 v4 v5 v6 +.outputs v13.6 v13.7 v13.8 v13.9 v13.10 v13.11 v13.12 v13.13 v13.14 v13.15 \ +v13.16 v13.17 v13.18 v13.19 v13.20 v13.21 v13.22 v13.23 v13.24 +.latch v13.0 v7 0 +.latch v13.1 v8 0 +.latch v13.2 v9 0 +.latch v13.3 v10 0 +.latch v13.4 v11 1 +.latch v13.5 v12 0 +.names [104] v13.6 +0 1 +.names [106] v13.7 +0 1 +.names [108] v13.8 +0 1 +.names [110] v13.9 +0 1 +.names [112] v13.10 +0 1 +.names [114] v13.11 +0 1 +.names [116] v13.12 +0 1 +.names [118] v13.13 +0 1 +.names [120] v13.14 +0 1 +.names [122] v13.15 +0 1 +.names [124] v13.16 +0 1 +.names [126] v13.17 +0 1 +.names [128] v13.18 +0 1 +.names [130] v13.19 +0 1 +.names [132] v13.20 +0 1 +.names [134] v13.21 +0 1 +.names [136] v13.22 +0 1 +.names [138] v13.23 +0 1 +.names [140] v13.24 +0 1 +.names [92] v13.0 +0 1 +.names [94] v13.1 +0 1 +.names [96] v13.2 +0 1 +.names [98] v13.3 +0 1 +.names [100] v13.4 +0 1 +.names [102] v13.5 +0 1 +.names v4 v5 v7 v8 v9 v10 v11 v12 [0] +10000000 1 +.names v4 v5 v7 v8 v9 v10 v11 [1] +1111000 1 +.names v0 v1 v3 v7 v9 v10 v11 v12 [2] +01100011 1 +.names v0 v3 v6 v7 v9 v10 v11 v12 [3] +01000011 1 +.names v2 v4 v5 v7 v8 v9 v11 v12 [4] +01011000 1 +.names v2 v4 v5 v8 v9 v10 v11 v12 [5] +01010001 1 +.names v0 v2 v8 v9 v10 v11 [6] +001100 1 +.names v4 v5 v7 v8 v9 v10 v11 v12 [7] +00000000 1 +.names v2 v4 v5 v7 v8 v9 v10 v11 [8] +00011000 1 +.names v0 v4 v5 v8 v9 v10 v11 v12 [9] +01010010 1 +.names v0 v4 v5 v8 v9 v10 v11 v12 [10] +00010010 1 +.names v2 v4 v7 v8 v9 v11 v12 [11] +0011000 1 +.names v2 v5 v7 v8 v9 v10 v11 [12] +0111000 1 +.names v0 v2 v8 v9 v12 [13] +01100 1 +.names v1 v7 v9 v10 v11 [14] +11111 1 +.names v2 v3 v8 v10 v11 [15] +10011 1 +.names v2 v3 v8 v11 v12 [16] +10011 1 +.names v0 v5 v8 v9 v10 v11 v12 [17] +0110010 1 +.names v4 v5 v7 v8 v9 v10 v11 v12 [18] +11000000 1 +.names v7 v8 v10 v11 v12 [19] +00110 1 +.names v2 v7 v8 v9 v10 v11 [20] +010101 1 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n1108 +11 1 +.names A[3] n1108 n1109 +01 1 +.names A[2] n1109 n1110 +01 1 +.names n1074 n1103 n1111 +11 1 +.names n906 n1111 n1112 +11 1 +.names A[1] n1112 n1113 +01 1 +.names n1110 n1113 F +11 0 +.end diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/router.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/router.blif new file mode 100644 index 000000000..857c2c552 --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/router.blif @@ -0,0 +1,585 @@ +.model top +.inputs dest_x[0] dest_x[1] dest_x[2] dest_x[3] dest_x[4] dest_x[5] \ + dest_x[6] dest_x[7] dest_x[8] dest_x[9] dest_x[10] dest_x[11] dest_x[12] \ + dest_x[13] dest_x[14] dest_x[15] dest_x[16] dest_x[17] dest_x[18] \ + dest_x[19] dest_x[20] dest_x[21] dest_x[22] dest_x[23] dest_x[24] \ + dest_x[25] dest_x[26] dest_x[27] dest_x[28] dest_x[29] dest_y[0] dest_y[1] \ + dest_y[2] dest_y[3] dest_y[4] dest_y[5] dest_y[6] dest_y[7] dest_y[8] \ + dest_y[9] dest_y[10] dest_y[11] dest_y[12] dest_y[13] dest_y[14] \ + dest_y[15] dest_y[16] dest_y[17] dest_y[18] dest_y[19] dest_y[20] \ + dest_y[21] dest_y[22] dest_y[23] dest_y[24] dest_y[25] dest_y[26] \ + dest_y[27] dest_y[28] dest_y[29] +.outputs outport[0] outport[1] outport[2] outport[3] outport[4] outport[5] \ + outport[6] outport[7] outport[8] outport[9] outport[10] outport[11] \ + outport[12] outport[13] outport[14] outport[15] outport[16] outport[17] \ + outport[18] outport[19] outport[20] outport[21] outport[22] outport[23] \ + outport[24] outport[25] outport[26] outport[27] outport[28] outport[29] +.names dest_x[9] dest_x[10] n92 +00 1 +.names dest_x[9] dest_x[10] n93 +11 1 +.names n92 n93 n94 +00 1 +.names dest_x[11] n92 n95 +10 1 +.names dest_x[11] n92 n96 +01 1 +.names n95 n96 n97 +00 1 +.names dest_x[12] n95 n98 +00 1 +.names dest_x[12] n95 n99 +11 1 +.names n98 n99 n100 +00 1 +.names dest_x[13] n98 n101 +01 1 +.names dest_x[13] n98 n102 +10 1 +.names n101 n102 n103 +00 1 +.names dest_x[14] n101 n104 +10 1 +.names dest_x[14] n101 n105 +01 1 +.names n104 n105 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n322 n323 +01 1 +.names n252 n323 n324 +11 1 +.names n254 n324 n325 +11 1 +.names n256 n325 n326 +01 1 +.names n258 n326 n327 +11 1 +.names n260 n327 n328 +01 1 +.names n263 n328 n329 +11 1 +.names n265 n329 n330 +11 1 +.names n267 n330 n331 +11 1 +.names n269 n331 n332 +01 1 +.names n272 n332 n333 +11 1 +.names n275 n333 n334 +11 1 +.names n277 n334 n335 +11 1 +.names n279 n335 n336 +01 1 +.names n282 n336 n337 +11 1 +.names dest_y[9] n337 n338 +11 1 +.names n236 n338 n339 +10 1 +.names n311 n339 n340 +00 1 +.names n239 n340 n341 +01 1 +.names n187 n341 n342 +00 1 +.names n237 n342 n343 +01 1 +.names n215 n343 outport[1] +00 1 +.names dest_x[0] n236 n345 +11 1 +.names dest_y[0] n345 n346 +11 1 +.names n339 n346 n347 +00 1 +.names outport[0] n347 outport[2] +00 1 +.names outport[3] + 0 +.names outport[4] + 0 +.names outport[5] + 0 +.names outport[6] + 0 +.names outport[7] + 0 +.names outport[8] + 0 +.names outport[9] + 0 +.names outport[10] + 0 +.names outport[11] + 0 +.names outport[12] + 0 +.names outport[13] + 0 +.names outport[14] + 0 +.names outport[15] + 0 +.names outport[16] + 0 +.names outport[17] + 0 +.names outport[18] + 0 +.names outport[19] + 0 +.names outport[20] + 0 +.names outport[21] + 0 +.names outport[22] + 0 +.names outport[23] + 0 +.names outport[24] + 0 +.names outport[25] + 0 +.names outport[26] + 0 +.names outport[27] + 0 +.names outport[28] + 0 +.names outport[29] + 0 +.end diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/s1488.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/s1488.blif new file mode 100644 index 000000000..c3dfdc8a5 --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/s1488.blif @@ -0,0 +1,796 @@ +.model TOP +.inputs s1488_in_7_ s1488_in_6_ s1488_in_5_ s1488_in_4_ s1488_in_3_ \ +s1488_in_2_ s1488_in_1_ s1488_in_0_ clock +.outputs s1488_out_18_ s1488_out_17_ s1488_out_16_ s1488_out_15_ s1488_out_14_ \ +s1488_out_13_ s1488_out_12_ s1488_out_11_ s1488_out_10_ s1488_out_9_ \ +s1488_out_8_ s1488_out_7_ s1488_out_6_ s1488_out_5_ s1488_out_4_ s1488_out_3_ \ +s1488_out_2_ s1488_out_1_ s1488_out_0_ +.latch N_N33 N_N356 re clock 2 +.latch N_N34 N_N357 re clock 2 +.latch N_N35 N_N358 re clock 2 +.latch N_N36 N_N359 re clock 2 +.latch N_N37 N_N360 re clock 2 +.latch N_N38 N_N361 re clock 2 +.names s1488_in_3_ n1 n3 n244 s1488_out_18_ +1110 1 +.names n4 s1488_out_17_ +0 1 +.names n5 s1488_out_16_ +0 1 +.names n6 s1488_out_15_ +0 1 +.names n7 s1488_out_14_ +0 1 +.names n10 n8 N_N361 n173 s1488_out_13_ +1-0- 1 +-100 1 +.names n30 s1488_out_12_ +0 1 +.names n12 s1488_out_11_ +0 1 +.names n39 s1488_out_10_ +0 1 +.names s1488_in_4_ n14 n173 n210 s1488_out_9_ +110- 1 +11-0 1 +.names n15 n16 n17 n18 s1488_out_8_ +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names n40 n42 n192 n290 s1488_out_7_ +1--- 1 +-1-- 1 +--0- 1 +---0 1 +.names n44 s1488_out_6_ +0 1 +.names n52 s1488_out_5_ +0 1 +.names n53 s1488_out_4_ +0 1 +.names n54 s1488_out_3_ +0 1 +.names n55 s1488_out_2_ +0 1 +.names n233 s1488_out_1_ +0 1 +.names n56 s1488_out_0_ +0 1 +.names n114 N_N360 n1 +10 1 +.names s1488_in_6_ s1488_in_1_ n3 +0- 1 +-1 1 +.names n10 N_N361 n164 n165 n4 +0-11 1 +-111 1 +.names n166 N_N360 n151 n5 +11- 1 +1-1 1 +.names n103 n114 n167 n187 n6 +0-0- 1 +-00- 1 +--00 1 +.names s1488_in_6_ s1488_in_3_ n5 n172 n7 +1-1- 1 +-01- 1 +--11 1 +.names n115 n210 n10 +10 1 +.names s1488_in_4_ s1488_in_5_ n8 +1- 1 +-1 1 +.names n35 n179 n180 n187 n12 +111- 1 +-110 1 +.names s1488_in_5_ N_N361 n14 +00 1 +.names N_N359 n116 n168 n226 n15 +--10 1 +101- 1 +.names n188 N_N360 n16 +11 1 +.names n206 n114 n17 +11 1 +.names s1488_in_0_ N_N359 n103 n187 n18 +1011 1 +.names n68 n76 n77 n107 n19 +111- 1 +-110 1 +.names n19 N_N38 +0 1 +.names n91 n92 N_N356 n90 n20 +111- 1 +11-1 1 +.names n20 N_N37 +0 1 +.names n97 n110 n111 n122 n21 +111- 1 +-110 1 +.names n21 N_N36 +0 1 +.names s1488_in_7_ N_N359 n119 n118 n22 +1-1- 1 +10-1 1 +.names n112 n122 n249 n262 n23 +11-- 1 +-10- 1 +-1-0 1 +.names n123 N_N359 n24 +11 1 +.names s1488_in_2_ n107 n116 n115 n26 +-11- 1 +01-1 1 +.names n104 n113 n256 n27 +11- 1 +1-0 1 +.names n22 n23 n24 n26 n27 n90 N_N35 +1----- 1 +-1---- 1 +--1--- 1 +---1-- 1 +----1- 1 +-----0 1 +.names n104 n131 n138 n278 n28 +001- 1 +-010 1 +.names n28 N_N34 +0 1 +.names n122 n139 n161 n162 n29 +0-11 1 +-111 1 +.names n29 N_N33 +0 1 +.names N_N361 n174 n31 +0- 1 +-1 1 +.names N_N356 N_N360 n252 n305 n32 +0--1 1 +-1-1 1 +--11 1 +.names n103 N_N360 n33 +0- 1 +-0 1 +.names n221 n250 n34 +0- 1 +-0 1 +.names s1488_in_0_ n119 n35 +0- 1 +-0 1 +.names n31 n32 n33 n34 n35 N_N359 n118 n199 n30 +11111000 1 +.names N_N358 N_N359 n185 n186 n39 +0-11 1 +-011 1 +.names n17 N_N360 n255 n40 +11- 1 +-10 1 +.names n200 n199 n103 n42 +11- 1 +1-1 1 +.names N_N361 n199 n46 +1- 1 +-0 1 +.names N_N356 n221 n47 +1- 1 +-0 1 +.names n1 N_N358 n50 +0- 1 +-0 1 +.names N_N361 n243 n51 +0- 1 +-1 1 +.names n33 n46 n47 n50 n51 n203 n205 n309 n44 +11111000 1 +.names N_N358 n119 n214 n215 n52 +0-11 1 +-011 1 +.names n70 N_N361 n115 n216 n217 n218 n53 +100111 1 +.names n184 n219 n220 n224 n54 +0-01 1 +-101 1 +.names s1488_in_2_ n10 N_N361 n229 n55 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names N_N358 n221 n250 n58 +1-- 1 +-0- 1 +--0 1 +.names n1 n103 n238 n59 +0-0 1 +-00 1 +.names N_N361 n115 n253 n60 +1-- 1 +-0- 1 +--1 1 +.names N_N359 N_N360 n174 n61 +0-- 1 +-0- 1 +--1 1 +.names n58 n59 n60 n61 n237 n312 n56 +111100 1 +.names s1488_in_3_ N_N358 N_N359 n63 +11- 1 +-10 1 +.names s1488_in_6_ s1488_in_3_ s1488_in_2_ s1488_in_1_ n64 +11-1 1 +1-01 1 +.names N_N358 n103 n67 +01 1 +.names N_N359 n67 N_N361 n66 +11- 1 +1-0 1 +.names s1488_in_2_ N_N356 n70 +0- 1 +-0 1 +.names s1488_in_2_ N_N358 n70 n103 n68 +1-10 1 +-010 1 +.names s1488_in_7_ n66 n266 n268 n72 +11-- 1 +1-0- 1 +1--0 1 +.names N_N359 n104 n123 n206 n76 +0-0- 1 +-00- 1 +--00 1 +.names n72 n122 n264 n265 n77 +00-- 1 +0-11 1 +.names s1488_in_7_ s1488_in_6_ N_N358 n82 +0-- 1 +-1- 1 +--0 1 +.names s1488_in_1_ n82 n104 N_N357 n78 +01-- 1 +-10- 1 +-1-0 1 +.names N_N358 N_N356 n84 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G241 G224 +0--- 1 +-0-- 1 +--0- 1 +---0 1 +.names G242 G243 G244 G40 G227 +0--- 1 +-0-- 1 +--0- 1 +---0 1 +.names G280 G267 G198 G131 +000 1 +.names G114 G115 G116 G317 G269 +0--- 1 +-0-- 1 +--0- 1 +---0 1 +.names G267 G123 G122 +00 1 +.names G318 G280 G16 G122 G46 +0--- 1 +-0-- 1 +--0- 1 +---0 1 +.names G180 G328 G317 G179 G69 +0--- 1 +-0-- 1 +--0- 1 +---0 1 +.names G318 G256 G138 +00 1 +.names G139 G138 G306 +0- 1 +-0 1 +.names G318 G256 G254 +00 1 +.names G255 G254 G84 +0- 1 +-0 1 +.names G127 G128 G129 G51 +000 1 +.names G3 G181 G1 G156 G146 +0000 1 +.names G328 G313 G317 G146 G61 +0--- 1 +-0-- 1 +--0- 1 +---0 1 +.names G231 G232 G233 G206 +000 1 +.names G210 G211 G77 +00 1 +.names G166 G167 G165 +00 1 +.names G199 G200 G192 +00 1 +.names G117 G118 G104 +00 1 +.names G120 G121 G324 +00 1 +.names G164 G165 G159 +00 1 +.names G191 G192 G186 +00 1 +.names G226 G227 G221 +00 1 +.names G268 G269 G261 +00 1 +.end diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/sasc.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/sasc.blif new file mode 100644 index 000000000..5c44ee382 --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/sasc.blif @@ -0,0 +1,1446 @@ +# Benchmark "sasc" written by ABC on Mon Aug 29 15:33:11 2005 +.model sasc +.inputs clk rst rxd_i cts_i sio_ce sio_ce_x4 re_i we_i din_i[0] din_i[1] \ + din_i[2] din_i[3] din_i[4] din_i[5] din_i[6] din_i[7] +.outputs txd_o rts_o full_o empty_o dout_o[0] dout_o[1] dout_o[2] dout_o[3] \ + dout_o[4] dout_o[5] dout_o[6] dout_o[7] + +.latch rx_fifo_gb_reg_in rx_fifo_gb_reg 2 +.latch \rx_fifo_wp_reg[0]_in \rx_fifo_wp_reg[0] 0 +.latch \rx_fifo_mem_reg[1][6]_in \rx_fifo_mem_reg[1][6] 2 +.latch \rx_fifo_mem_reg[1][7]_in \rx_fifo_mem_reg[1][7] 2 +.latch \rx_fifo_mem_reg[2][0]_in \rx_fifo_mem_reg[2][0] 2 +.latch \rx_fifo_mem_reg[2][1]_in \rx_fifo_mem_reg[2][1] 2 +.latch \rx_fifo_mem_reg[2][2]_in \rx_fifo_mem_reg[2][2] 2 +.latch \rx_fifo_mem_reg[2][3]_in \rx_fifo_mem_reg[2][3] 2 +.latch \rx_fifo_mem_reg[2][4]_in \rx_fifo_mem_reg[2][4] 2 +.latch \rx_fifo_mem_reg[2][5]_in \rx_fifo_mem_reg[2][5] 2 +.latch \rx_fifo_mem_reg[2][6]_in \rx_fifo_mem_reg[2][6] 2 +.latch \rx_fifo_mem_reg[2][7]_in \rx_fifo_mem_reg[2][7] 2 +.latch \rx_fifo_mem_reg[1][0]_in \rx_fifo_mem_reg[1][0] 2 +.latch \rx_fifo_mem_reg[1][1]_in \rx_fifo_mem_reg[1][1] 2 +.latch \rx_fifo_mem_reg[1][2]_in \rx_fifo_mem_reg[1][2] 2 +.latch \rx_fifo_mem_reg[1][3]_in \rx_fifo_mem_reg[1][3] 2 +.latch \rx_fifo_mem_reg[1][4]_in \rx_fifo_mem_reg[1][4] 2 +.latch \rx_fifo_mem_reg[1][5]_in \rx_fifo_mem_reg[1][5] 2 +.latch \rx_fifo_mem_reg[3][0]_in \rx_fifo_mem_reg[3][0] 2 +.latch \rx_fifo_mem_reg[3][1]_in \rx_fifo_mem_reg[3][1] 2 +.latch \rx_fifo_mem_reg[3][2]_in \rx_fifo_mem_reg[3][2] 2 +.latch \rx_fifo_mem_reg[3][3]_in \rx_fifo_mem_reg[3][3] 2 +.latch \rx_fifo_mem_reg[3][4]_in \rx_fifo_mem_reg[3][4] 2 +.latch \rx_fifo_mem_reg[3][5]_in \rx_fifo_mem_reg[3][5] 2 +.latch \rx_fifo_mem_reg[3][6]_in \rx_fifo_mem_reg[3][6] 2 +.latch \rx_fifo_mem_reg[3][7]_in \rx_fifo_mem_reg[3][7] 2 +.latch \rx_fifo_mem_reg[0][0]_in \rx_fifo_mem_reg[0][0] 2 +.latch \rx_fifo_mem_reg[0][1]_in \rx_fifo_mem_reg[0][1] 2 +.latch \rx_fifo_mem_reg[0][2]_in \rx_fifo_mem_reg[0][2] 2 +.latch \rx_fifo_mem_reg[0][3]_in \rx_fifo_mem_reg[0][3] 2 +.latch \rx_fifo_mem_reg[0][4]_in \rx_fifo_mem_reg[0][4] 2 +.latch \rx_fifo_mem_reg[0][5]_in \rx_fifo_mem_reg[0][5] 2 +.latch \rx_fifo_mem_reg[0][6]_in \rx_fifo_mem_reg[0][6] 2 +.latch \rx_fifo_mem_reg[0][7]_in \rx_fifo_mem_reg[0][7] 2 +.latch \rx_bit_cnt_reg[1]_in \rx_bit_cnt_reg[1] 2 +.latch \rx_fifo_wp_reg[1]_in \rx_fifo_wp_reg[1] 0 +.latch \rx_bit_cnt_reg[3]_in \rx_bit_cnt_reg[3] 2 +.latch \rx_bit_cnt_reg[0]_in \rx_bit_cnt_reg[0] 2 +.latch \rx_bit_cnt_reg[2]_in \rx_bit_cnt_reg[2] 2 +.latch \rxr_reg[3]_in \rxr_reg[3] 2 +.latch \rxr_reg[9]_in \rxr_reg[9] 2 +.latch \rxr_reg[2]_in \rxr_reg[2] 2 +.latch \rxr_reg[4]_in \rxr_reg[4] 2 +.latch \rxr_reg[5]_in \rxr_reg[5] 2 +.latch \rxr_reg[6]_in \rxr_reg[6] 2 +.latch \rxr_reg[8]_in \rxr_reg[8] 2 +.latch \rxr_reg[7]_in \rxr_reg[7] 2 +.latch \tx_bit_cnt_reg[3]_in \tx_bit_cnt_reg[3] 2 +.latch tx_fifo_gb_reg_in tx_fifo_gb_reg 2 +.latch \hold_reg_reg[6]_in \hold_reg_reg[6] 2 +.latch \hold_reg_reg[7]_in \hold_reg_reg[7] 2 +.latch \hold_reg_reg[8]_in \hold_reg_reg[8] 2 +.latch \hold_reg_reg[1]_in \hold_reg_reg[1] 2 +.latch \hold_reg_reg[2]_in \hold_reg_reg[2] 2 +.latch \hold_reg_reg[3]_in \hold_reg_reg[3] 2 +.latch \hold_reg_reg[4]_in \hold_reg_reg[4] 2 +.latch \tx_bit_cnt_reg[2]_in \tx_bit_cnt_reg[2] 2 +.latch \hold_reg_reg[5]_in \hold_reg_reg[5] 2 +.latch txf_empty_r_reg_in txf_empty_r_reg 2 +.latch \tx_fifo_mem_reg[2][1]_in \tx_fifo_mem_reg[2][1] 2 +.latch \dpll_state_reg[0]_in \dpll_state_reg[0] 1 +.latch rts_o_reg_in rts_o_reg 2 +.latch \tx_bit_cnt_reg[0]_in \tx_bit_cnt_reg[0] 2 +.latch \tx_fifo_mem_reg[1][0]_in \tx_fifo_mem_reg[1][0] 2 +.latch \tx_fifo_mem_reg[1][1]_in \tx_fifo_mem_reg[1][1] 2 +.latch \tx_fifo_mem_reg[1][2]_in \tx_fifo_mem_reg[1][2] 2 +.latch \tx_fifo_mem_reg[1][3]_in \tx_fifo_mem_reg[1][3] 2 +.latch \tx_fifo_mem_reg[1][4]_in \tx_fifo_mem_reg[1][4] 2 +.latch \tx_fifo_mem_reg[1][6]_in \tx_fifo_mem_reg[1][6] 2 +.latch \tx_fifo_mem_reg[1][7]_in \tx_fifo_mem_reg[1][7] 2 +.latch \tx_fifo_mem_reg[2][0]_in \tx_fifo_mem_reg[2][0] 2 +.latch \tx_fifo_mem_reg[2][2]_in \tx_fifo_mem_reg[2][2] 2 +.latch \tx_fifo_mem_reg[2][3]_in \tx_fifo_mem_reg[2][3] 2 +.latch \tx_fifo_mem_reg[2][4]_in \tx_fifo_mem_reg[2][4] 2 +.latch \tx_fifo_mem_reg[2][6]_in \tx_fifo_mem_reg[2][6] 2 +.latch \tx_fifo_mem_reg[2][7]_in \tx_fifo_mem_reg[2][7] 2 +.latch txd_o_reg_in txd_o_reg 2 +.latch \tx_fifo_rp_reg[1]_in \tx_fifo_rp_reg[1] 0 +.latch \hold_reg_reg[0]_in \hold_reg_reg[0] 2 +.latch \tx_fifo_mem_reg[1][5]_in \tx_fifo_mem_reg[1][5] 2 +.latch \tx_fifo_mem_reg[2][5]_in \tx_fifo_mem_reg[2][5] 2 +.latch \tx_fifo_mem_reg[3][1]_in \tx_fifo_mem_reg[3][1] 2 +.latch \tx_fifo_mem_reg[3][6]_in \tx_fifo_mem_reg[3][6] 2 +.latch rx_valid_r_reg_in rx_valid_r_reg 2 +.latch \tx_fifo_mem_reg[3][5]_in \tx_fifo_mem_reg[3][5] 2 +.latch change_reg_in change_reg 2 +.latch \tx_fifo_mem_reg[0][0]_in \tx_fifo_mem_reg[0][0] 2 +.latch \tx_fifo_mem_reg[0][3]_in \tx_fifo_mem_reg[0][3] 2 +.latch \tx_fifo_mem_reg[0][4]_in \tx_fifo_mem_reg[0][4] 2 +.latch \tx_fifo_mem_reg[0][7]_in \tx_fifo_mem_reg[0][7] 2 +.latch \tx_fifo_mem_reg[0][2]_in \tx_fifo_mem_reg[0][2] 2 +.latch \tx_fifo_mem_reg[3][0]_in \tx_fifo_mem_reg[3][0] 2 +.latch \tx_fifo_mem_reg[3][2]_in \tx_fifo_mem_reg[3][2] 2 +.latch \tx_fifo_mem_reg[3][3]_in \tx_fifo_mem_reg[3][3] 2 +.latch \tx_fifo_mem_reg[3][4]_in \tx_fifo_mem_reg[3][4] 2 +.latch \tx_fifo_mem_reg[3][7]_in \tx_fifo_mem_reg[3][7] 2 +.latch \rx_fifo_rp_reg[1]_in \rx_fifo_rp_reg[1] 0 +.latch \hold_reg_reg[9]_in \hold_reg_reg[9] 2 +.latch \tx_fifo_mem_reg[0][6]_in \tx_fifo_mem_reg[0][6] 2 +.latch \tx_fifo_mem_reg[0][5]_in \tx_fifo_mem_reg[0][5] 2 +.latch \tx_fifo_mem_reg[0][1]_in \tx_fifo_mem_reg[0][1] 2 +.latch \tx_bit_cnt_reg[1]_in \tx_bit_cnt_reg[1] 2 +.latch rx_sio_ce_reg_in rx_sio_ce_reg 2 +.latch shift_en_r_reg_in shift_en_r_reg 2 +.latch \tx_fifo_wp_reg[1]_in \tx_fifo_wp_reg[1] 0 +.latch \dpll_state_reg[1]_in \dpll_state_reg[1] 0 +.latch rx_valid_reg_in rx_valid_reg 2 +.latch \rx_fifo_rp_reg[0]_in \rx_fifo_rp_reg[0] 0 +.latch rx_go_reg_in rx_go_reg 2 +.latch \tx_fifo_rp_reg[0]_in \tx_fifo_rp_reg[0] 0 +.latch load_reg_in load_reg 2 +.latch rx_sio_ce_r2_reg_in rx_sio_ce_r2_reg 2 +.latch \tx_fifo_wp_reg[0]_in \tx_fifo_wp_reg[0] 0 +.latch shift_en_reg_in shift_en_reg 2 +.latch rx_sio_ce_r1_reg_in rx_sio_ce_r1_reg 2 +.latch rxd_r_reg_in rxd_r_reg 2 +.latch rxd_s_reg_in rxd_s_reg 2 + +.names [145] + 0 +.names [146] + 1 +.names rx_fifo_gb_reg [147] +1 1 +.names \rx_fifo_wp_reg[0] [148] +1 1 +.names \rx_fifo_mem_reg[1][6] [149] +1 1 +.names \rx_fifo_mem_reg[1][7] [150] +1 1 +.names \rx_fifo_mem_reg[2][0] [151] +1 1 +.names \rx_fifo_mem_reg[2][1] [152] +1 1 +.names \rx_fifo_mem_reg[2][2] [153] +1 1 +.names \rx_fifo_mem_reg[2][3] [154] +1 1 +.names \rx_fifo_mem_reg[2][4] [155] +1 1 +.names \rx_fifo_mem_reg[2][5] [156] +1 1 +.names \rx_fifo_mem_reg[2][6] [157] +1 1 +.names \rx_fifo_mem_reg[2][7] [158] +1 1 +.names \rx_fifo_mem_reg[1][0] [159] +1 1 +.names \rx_fifo_mem_reg[1][1] [160] +1 1 +.names \rx_fifo_mem_reg[1][2] [161] +1 1 +.names \rx_fifo_mem_reg[1][3] [162] +1 1 +.names \rx_fifo_mem_reg[1][4] [163] +1 1 +.names \rx_fifo_mem_reg[1][5] [164] +1 1 +.names \rx_fifo_mem_reg[3][0] [165] +1 1 +.names \rx_fifo_mem_reg[3][1] [166] +1 1 +.names \rx_fifo_mem_reg[3][2] [167] +1 1 +.names \rx_fifo_mem_reg[3][3] [168] +1 1 +.names \rx_fifo_mem_reg[3][4] [169] +1 1 +.names \rx_fifo_mem_reg[3][5] [170] +1 1 +.names \rx_fifo_mem_reg[3][6] [171] +1 1 +.names \rx_fifo_mem_reg[3][7] [172] +1 1 +.names \rx_fifo_mem_reg[0][0] [173] +1 1 +.names \rx_fifo_mem_reg[0][1] [174] +1 1 +.names \rx_fifo_mem_reg[0][2] [175] +1 1 +.names \rx_fifo_mem_reg[0][3] [176] +1 1 +.names \rx_fifo_mem_reg[0][4] [177] +1 1 +.names \rx_fifo_mem_reg[0][5] [178] +1 1 +.names \rx_fifo_mem_reg[0][6] [179] +1 1 +.names \rx_fifo_mem_reg[0][7] [180] +1 1 +.names [230] [607] [648] rx_fifo_gb_reg_in +11- 0 +--1 0 +.names \rx_bit_cnt_reg[1] [182] +1 1 +.names \rx_fifo_wp_reg[1] [183] +1 1 +.names \rx_bit_cnt_reg[3] [184] +1 1 +.names [672] [625] [232] \rx_fifo_wp_reg[0]_in +00- 1 +--0 1 +.names [414] [150] [242] \rx_fifo_mem_reg[1][7]_in +01- 1 +1-1 1 +.names [352] [151] [242] \rx_fifo_mem_reg[2][0]_in +01- 1 +1-1 1 +.names [353] [152] [245] \rx_fifo_mem_reg[2][1]_in +01- 1 +1-1 1 +.names [413] [149] [244] \rx_fifo_mem_reg[1][6]_in +01- 1 +1-1 1 +.names \rx_bit_cnt_reg[0] [190] +1 1 +.names \rx_bit_cnt_reg[2] [191] +1 1 +.names [355] [154] [243] \rx_fifo_mem_reg[2][3]_in +01- 1 +1-1 1 +.names [354] [153] [245] \rx_fifo_mem_reg[2][2]_in +01- 1 +1-1 1 +.names [356] [155] [242] \rx_fifo_mem_reg[2][4]_in +01- 1 +1-1 1 +.names [357] [156] [243] \rx_fifo_mem_reg[2][5]_in +01- 1 +1-1 1 +.names [358] [157] [245] \rx_fifo_mem_reg[2][6]_in +01- 1 +1-1 1 +.names [359] [158] [244] \rx_fifo_mem_reg[2][7]_in +01- 1 +1-1 1 +.names [417] [160] [242] \rx_fifo_mem_reg[1][1]_in +01- 1 +1-1 1 +.names [415] [159] [245] \rx_fifo_mem_reg[1][0]_in +01- 1 +1-1 1 +.names [416] [161] [242] \rx_fifo_mem_reg[1][2]_in +01- 1 +1-1 1 +.names [418] [162] [243] \rx_fifo_mem_reg[1][3]_in +01- 1 +1-1 1 +.names [419] [163] [242] \rx_fifo_mem_reg[1][4]_in +01- 1 +1-1 1 +.names [420] [164] [244] \rx_fifo_mem_reg[1][5]_in +01- 1 +1-1 1 +.names [360] [165] [244] \rx_fifo_mem_reg[3][0]_in +01- 1 +1-1 1 +.names [361] [166] [245] \rx_fifo_mem_reg[3][1]_in +01- 1 +1-1 1 +.names [362] [167] [243] \rx_fifo_mem_reg[3][2]_in +01- 1 +1-1 1 +.names [363] [168] [244] \rx_fifo_mem_reg[3][3]_in +01- 1 +1-1 1 +.names [364] [169] [244] \rx_fifo_mem_reg[3][4]_in +01- 1 +1-1 1 +.names [366] [170] [243] \rx_fifo_mem_reg[3][5]_in +01- 1 +1-1 1 +.names [367] [171] [245] \rx_fifo_mem_reg[3][6]_in +01- 1 +1-1 1 +.names [368] [172] [245] \rx_fifo_mem_reg[3][7]_in +01- 1 +1-1 1 +.names [373] [173] [244] \rx_fifo_mem_reg[0][0]_in +01- 1 +1-1 1 +.names [369] [174] [243] \rx_fifo_mem_reg[0][1]_in +01- 1 +1-1 1 +.names [374] [175] [245] \rx_fifo_mem_reg[0][2]_in +01- 1 +1-1 1 +.names [375] [176] [244] \rx_fifo_mem_reg[0][3]_in +01- 1 +1-1 1 +.names [378] [177] [242] \rx_fifo_mem_reg[0][4]_in +01- 1 +1-1 1 +.names [376] [178] [242] \rx_fifo_mem_reg[0][5]_in +01- 1 +1-1 1 +.names [372] [179] [243] \rx_fifo_mem_reg[0][6]_in +01- 1 +1-1 1 +.names [377] [180] [243] \rx_fifo_mem_reg[0][7]_in +01- 1 +1-1 1 +.names \rxr_reg[3] [220] +1 1 +.names \rxr_reg[9] [221] +1 1 +.names \rxr_reg[2] [222] +1 1 +.names \rxr_reg[4] [223] +1 1 +.names \rxr_reg[5] [224] +1 1 +.names \rxr_reg[6] [225] +1 1 +.names \rxr_reg[8] [226] +1 1 +.names \rxr_reg[7] [227] +1 1 +.names [543] [246] rst \rx_bit_cnt_reg[1]_in +00- 1 +--0 1 +.names [251] [543] rst \rx_bit_cnt_reg[3]_in +00- 1 +--0 1 +.names [322] [247] [500] [230] +111 0 +.names [253] [467] \rx_bit_cnt_reg[0]_in +00 1 +.names [672] [625] [232] +11 0 +.names [252] [467] \rx_bit_cnt_reg[2]_in +00 1 +.names rxd_r_reg_in [221] [280] \rxr_reg[9]_in +01- 1 +1-1 1 +.names [220] [222] [280] \rxr_reg[2]_in +01- 1 +1-1 1 +.names [223] [220] [280] \rxr_reg[3]_in +01- 1 +1-1 1 +.names [224] [223] [280] \rxr_reg[4]_in +01- 1 +1-1 1 +.names [225] [224] [280] \rxr_reg[5]_in +01- 1 +1-1 1 +.names [227] [225] [280] \rxr_reg[6]_in +01- 1 +1-1 1 +.names [226] [227] [280] \rxr_reg[7]_in +01- 1 +1-1 1 +.names [221] [226] [280] \rxr_reg[8]_in +01- 1 +1-1 1 +.names [247] [242] +0 1 +.names [248] [243] +0 1 +.names [249] [244] +0 1 +.names [250] [245] +0 1 +.names [575] [270] [182] [280] [246] +11-- 0 +--11 0 +.names [673] [247] +0 1 +.names [673] [248] +0 1 +.names [673] [249] +0 1 +.names [673] [250] +0 1 +.names [184] [280] [267] [251] +11- 0 +--1 0 +.names [191] [280] [263] [252] +11- 0 +--1 0 +.names [629] [280] [262] [253] +11- 0 +--1 0 +.names \tx_bit_cnt_reg[3] [254] +1 1 +.names tx_fifo_gb_reg [255] +0 1 +.names \hold_reg_reg[6] [256] +0 1 +.names \hold_reg_reg[7] [257] +0 1 +.names \hold_reg_reg[8] [258] +0 1 +.names \hold_reg_reg[1] [259] +0 1 +.names \hold_reg_reg[2] [260] +0 1 +.names \hold_reg_reg[3] [261] +0 1 +.names [629] [280] [262] +00 1 +.names [501] [280] [263] +00 1 +.names \hold_reg_reg[4] [264] +0 1 +.names \tx_bit_cnt_reg[2] [265] +1 1 +.names \hold_reg_reg[5] [266] +0 1 +.names [453] [280] [267] +00 1 +.names txf_empty_r_reg [268] +0 1 +.names [329] [598] rst \tx_bit_cnt_reg[3]_in +00- 1 +--0 1 +.names [280] [270] +0 1 +.names [327] [591] \tx_bit_cnt_reg[2]_in +00 1 +.names [513] [383] [598] \hold_reg_reg[6]_in +01- 1 +1-1 1 +.names [511] [382] [598] \hold_reg_reg[5]_in +01- 1 +1-1 1 +.names [514] [384] [598] \hold_reg_reg[7]_in +01- 1 +1-1 1 +.names [516] [385] [598] \hold_reg_reg[8]_in +01- 1 +1-1 1 +.names [521] [386] [598] \hold_reg_reg[1]_in +01- 1 +1-1 1 +.names [517] [387] [632] \hold_reg_reg[2]_in +01- 1 +1-1 1 +.names [515] [388] [632] \hold_reg_reg[3]_in +01- 1 +1-1 1 +.names [533] [389] [632] \hold_reg_reg[4]_in +01- 1 +1-1 1 +.names [433] [328] [280] +11 0 +.names [572] [371] [648] tx_fifo_gb_reg_in +11- 0 +--1 0 +.names \tx_fifo_mem_reg[2][1] [282] +1 1 +.names \dpll_state_reg[0] [283] +1 1 +.names rts_o_reg rts_o +1 1 +.names \tx_bit_cnt_reg[0] [285] +1 1 +.names \tx_fifo_mem_reg[1][0] [286] +1 1 +.names \tx_fifo_mem_reg[1][1] [287] +1 1 +.names \tx_fifo_mem_reg[1][2] [288] +1 1 +.names \tx_fifo_mem_reg[1][3] [289] +1 1 +.names \tx_fifo_mem_reg[1][4] [290] +1 1 +.names \tx_fifo_mem_reg[1][6] [291] +1 1 +.names \tx_fifo_mem_reg[1][7] [292] +1 1 +.names \tx_fifo_mem_reg[2][0] [293] +1 1 +.names \tx_fifo_mem_reg[2][2] [294] +1 1 +.names \tx_fifo_mem_reg[2][3] [295] +1 1 +.names \tx_fifo_mem_reg[2][4] [296] +1 1 +.names \tx_fifo_mem_reg[2][6] [297] +1 1 +.names \tx_fifo_mem_reg[2][7] [298] +1 1 +.names txd_o_reg txd_o +1 1 +.names \tx_fifo_rp_reg[1] [300] +1 1 +.names \hold_reg_reg[0] [301] +1 1 +.names \tx_fifo_mem_reg[1][5] [302] +1 1 +.names \tx_fifo_mem_reg[2][5] [303] +1 1 +.names [381] rst txf_empty_r_reg_in +11 0 +.names \tx_fifo_mem_reg[3][1] [305] +1 1 +.names \tx_fifo_mem_reg[3][6] [306] +1 1 +.names rx_valid_r_reg [307] +0 1 +.names \tx_fifo_mem_reg[3][5] [308] +1 1 +.names change_reg [309] +1 1 +.names \tx_fifo_mem_reg[0][0] [310] +1 1 +.names \tx_fifo_mem_reg[0][3] [311] +1 1 +.names \tx_fifo_mem_reg[0][4] [312] +1 1 +.names \tx_fifo_mem_reg[0][7] [313] +1 1 +.names \tx_fifo_mem_reg[0][2] [314] +1 1 +.names \tx_fifo_mem_reg[3][0] [315] +1 1 +.names \tx_fifo_mem_reg[3][2] [316] +1 1 +.names \tx_fifo_mem_reg[3][3] [317] +1 1 +.names \tx_fifo_mem_reg[3][4] [318] +1 1 +.names \tx_fifo_mem_reg[3][7] [319] +1 1 +.names \rx_fifo_rp_reg[1] [320] +1 1 +.names \hold_reg_reg[9] [321] +1 1 +.names [671] [631] [412] [322] +00- 1 +--0 1 +.names \tx_fifo_mem_reg[0][6] [323] +1 1 +.names \tx_fifo_mem_reg[0][5] [324] +1 1 +.names \tx_fifo_mem_reg[0][1] [325] +1 1 +.names \tx_bit_cnt_reg[1] [326] +1 1 +.names [265] [595] [423] [327] +11- 0 +--1 0 +.names rx_sio_ce_reg [328] +1 1 +.names [583] [254] [405] [329] +11- 0 +--1 0 +.names [291] [478] we_i \tx_fifo_mem_reg[1][6]_in +01- 1 +1-1 1 +.names [292] [479] we_i \tx_fifo_mem_reg[1][7]_in +01- 1 +1-1 1 +.names [293] [480] we_i \tx_fifo_mem_reg[2][0]_in +01- 1 +1-1 1 +.names [282] [486] we_i \tx_fifo_mem_reg[2][1]_in +01- 1 +1-1 1 +.names [294] [481] we_i \tx_fifo_mem_reg[2][2]_in +01- 1 +1-1 1 +.names [295] [482] we_i \tx_fifo_mem_reg[2][3]_in +01- 1 +1-1 1 +.names [296] [483] we_i \tx_fifo_mem_reg[2][4]_in +01- 1 +1-1 1 +.names [303] [471] we_i \tx_fifo_mem_reg[2][5]_in +01- 1 +1-1 1 +.names [297] [484] we_i \tx_fifo_mem_reg[2][6]_in +01- 1 +1-1 1 +.names [298] [485] we_i \tx_fifo_mem_reg[2][7]_in +01- 1 +1-1 1 +.names [445] [448] dout_o[4] +11 0 +.names [446] [447] dout_o[0] +11 0 +.names shift_en_r_reg [342] +1 1 +.names [444] [449] dout_o[6] +11 0 +.names [687] [499] [632] \tx_fifo_rp_reg[1]_in +01- 1 +1-1 1 +.names [495] [490] [598] \hold_reg_reg[0]_in +11- 0 +--1 0 +.names [443] [450] dout_o[7] +11 0 +.names [439] [440] dout_o[5] +11 0 +.names [437] [451] dout_o[3] +11 0 +.names [436] [438] dout_o[2] +11 0 +.names [441] [442] dout_o[1] +11 0 +.names [452] [626] empty_o +00 1 +.names [222] [151] [502] [352] +01- 1 +1-1 1 +.names [220] [152] [502] [353] +01- 1 +1-1 1 +.names [223] [153] [502] [354] +01- 1 +1-1 1 +.names [224] [154] [502] [355] +01- 1 +1-1 1 +.names [225] [155] [502] [356] +01- 1 +1-1 1 +.names [227] [156] [502] [357] +01- 1 +1-1 1 +.names [226] [157] [502] [358] +01- 1 +1-1 1 +.names [221] [158] [502] [359] +01- 1 +1-1 1 +.names [222] [165] [689] [360] +01- 1 +1-1 1 +.names [220] [166] [689] [361] +01- 1 +1-1 1 +.names [223] [167] [689] [362] +01- 1 +1-1 1 +.names [224] [168] [689] [363] +01- 1 +1-1 1 +.names [225] [169] [689] [364] +01- 1 +1-1 1 +.names [573] [590] [457] \dpll_state_reg[0]_in +111 0 +.names [227] [170] [689] [366] +01- 1 +1-1 1 +.names [226] [171] [689] [367] +01- 1 +1-1 1 +.names [221] [172] [689] [368] +01- 1 +1-1 1 +.names [174] [220] [504] [369] +01- 1 +1-1 1 +.names [678] rts_o_reg_in +0 1 +.names [458] [555] we_i [371] +111 0 +.names [179] [226] [504] [372] +01- 1 +1-1 1 +.names [173] [222] [504] [373] +01- 1 +1-1 1 +.names [175] [223] [504] [374] +01- 1 +1-1 1 +.names [176] [224] [504] [375] +01- 1 +1-1 1 +.names [178] [227] [504] [376] +01- 1 +1-1 1 +.names [180] [221] [504] [377] +01- 1 +1-1 1 +.names [177] [225] [504] [378] +01- 1 +1-1 1 +.names [434] rst txd_o_reg_in +11 0 +.names [487] [632] rst \tx_bit_cnt_reg[0]_in +00- 1 +--0 1 +.names [617] [461] [639] [655] [381] +11-- 0 +--11 0 +.names [544] [535] [462] [382] +111 0 +.names [567] [548] [464] [383] +111 0 +.names [561] [498] [465] [384] +111 0 +.names [549] [494] [466] [385] +111 0 +.names [570] [537] [468] [386] +111 0 +.names [571] [536] [469] [387] +111 0 +.names [569] [493] [470] [388] +111 0 +.names [547] [496] [463] [389] +111 0 +.names [286] [472] we_i \tx_fifo_mem_reg[1][0]_in +01- 1 +1-1 1 +.names [287] [473] we_i \tx_fifo_mem_reg[1][1]_in +01- 1 +1-1 1 +.names [288] [474] we_i \tx_fifo_mem_reg[1][2]_in +01- 1 +1-1 1 +.names [289] [476] we_i \tx_fifo_mem_reg[1][3]_in +01- 1 +1-1 1 +.names [290] [477] we_i \tx_fifo_mem_reg[1][4]_in +01- 1 +1-1 1 +.names [302] [475] we_i \tx_fifo_mem_reg[1][5]_in +01- 1 +1-1 1 +.names [315] [529] we_i \tx_fifo_mem_reg[3][0]_in +01- 1 +1-1 1 +.names [305] [530] we_i \tx_fifo_mem_reg[3][1]_in +01- 1 +1-1 1 +.names [316] [512] we_i \tx_fifo_mem_reg[3][2]_in +01- 1 +1-1 1 +.names [319] [534] we_i \tx_fifo_mem_reg[3][7]_in +01- 1 +1-1 1 +.names [317] [531] we_i \tx_fifo_mem_reg[3][3]_in +01- 1 +1-1 1 +.names [318] [520] we_i \tx_fifo_mem_reg[3][4]_in +01- 1 +1-1 1 +.names [308] [532] we_i \tx_fifo_mem_reg[3][5]_in +01- 1 +1-1 1 +.names [563] [460] rx_sio_ce_reg_in +00 1 +.names [306] [522] we_i \tx_fifo_mem_reg[3][6]_in +01- 1 +1-1 1 +.names [489] [583] [405] +00 1 +.names \tx_fifo_wp_reg[1] [406] +1 1 +.names \dpll_state_reg[1] [407] +1 1 +.names [461] [653] full_o +11 1 +.names [631] [538] re_i \rx_fifo_rp_reg[1]_in +01- 1 +1-1 1 +.names rx_valid_reg rx_valid_r_reg_in +1 1 +.names [497] [321] \hold_reg_reg[9]_in +00 0 +.names [631] [671] [412] +11 0 +.names [226] [149] [540] [413] +01- 1 +1-1 1 +.names [221] [150] [540] [414] +01- 1 +1-1 1 +.names [222] [159] [540] [415] +01- 1 +1-1 1 +.names [223] [161] [540] [416] +01- 1 +1-1 1 +.names [220] [160] [540] [417] +01- 1 +1-1 1 +.names [224] [162] [540] [418] +01- 1 +1-1 1 +.names [225] [163] [540] [419] +01- 1 +1-1 1 +.names [227] [164] [540] [420] +01- 1 +1-1 1 +.names [491] [591] \tx_bit_cnt_reg[1]_in +00 1 +.names [508] [648] [589] change_reg_in +00- 1 +--0 1 +.names [488] [595] [423] +00 1 +.names [310] [523] we_i \tx_fifo_mem_reg[0][0]_in +01- 1 +1-1 1 +.names [325] [528] we_i \tx_fifo_mem_reg[0][1]_in +01- 1 +1-1 1 +.names [314] [524] we_i \tx_fifo_mem_reg[0][2]_in +01- 1 +1-1 1 +.names [311] [525] we_i \tx_fifo_mem_reg[0][3]_in +01- 1 +1-1 1 +.names [312] [526] we_i \tx_fifo_mem_reg[0][4]_in +01- 1 +1-1 1 +.names [324] [519] we_i \tx_fifo_mem_reg[0][5]_in +01- 1 +1-1 1 +.names [323] [527] we_i \tx_fifo_mem_reg[0][6]_in +01- 1 +1-1 1 +.names [313] [518] we_i \tx_fifo_mem_reg[0][7]_in +01- 1 +1-1 1 +.names \rx_fifo_rp_reg[0] [432] +1 1 +.names rx_go_reg [433] +1 1 +.names [551] sio_ce [639] txd_o [434] +11-- 0 +--11 0 +.names [610] [596] [648] shift_en_r_reg_in +11- 0 +--1 0 +.names [153] [559] [167] [581] [436] +11-- 0 +--11 0 +.names [154] [559] [168] [581] [437] +11-- 0 +--11 0 +.names [161] [557] [175] [582] [438] +11-- 0 +--11 0 +.names [156] [559] [170] [581] [439] +11-- 0 +--11 0 +.names [164] [557] [178] [582] [440] +11-- 0 +--11 0 +.names [152] [559] [166] [581] [441] +11-- 0 +--11 0 +.names [160] [557] [174] [582] [442] +11-- 0 +--11 0 +.names [557] [150] [582] [180] [443] +11-- 0 +--11 0 +.names [149] [557] [179] [582] [444] +11-- 0 +--11 0 +.names [155] [559] [169] [581] [445] +11-- 0 +--11 0 +.names [151] [559] [165] [581] [446] +11-- 0 +--11 0 +.names [159] [557] [173] [582] [447] +11-- 0 +--11 0 +.names [163] [557] [177] [582] [448] +11-- 0 +--11 0 +.names [157] [559] [171] [581] [449] +11-- 0 +--11 0 +.names [559] [158] [581] [172] [450] +11-- 0 +--11 0 +.names [162] [557] [176] [582] [451] +11-- 0 +--11 0 +.names [657] [452] +0 1 +.names [184] [565] [453] +01 1 +10 1 +.names \tx_fifo_rp_reg[0] [454] +1 1 +.names load_reg [455] +1 1 +.names [554] [615] [573] \dpll_state_reg[1]_in +111 0 +.names [627] [613] [309] [576] [457] +11-- 0 +--11 0 +.names [688] [564] [458] +01 1 +10 1 +.names [662] [564] we_i \tx_fifo_wp_reg[1]_in +01- 1 +1-1 1 +.names rx_sio_ce_r2_reg [460] +1 1 +.names [556] [555] [461] +00 1 +.names [619] [312] [296] [578] [462] +11-- 0 +--11 0 +.names [619] [311] [289] [694] [463] +11-- 0 +--11 0 +.names [302] [694] [303] [578] [464] +11-- 0 +--11 0 +.names [601] [306] [291] [694] [465] +11-- 0 +--11 0 +.names [619] [313] [292] [694] [466] +11-- 0 +--11 0 +.names [543] [648] [467] +00 0 +.names [601] [315] [293] [578] [468] +11-- 0 +--11 0 +.names [601] [305] [282] [578] [469] +11-- 0 +--11 0 +.names [601] [316] [288] [694] [470] +11-- 0 +--11 0 +.names din_i[5] [303] [579] [471] +01- 1 +1-1 1 +.names din_i[0] [286] [695] [472] +01- 1 +1-1 1 +.names din_i[1] [287] [695] [473] +01- 1 +1-1 1 +.names din_i[2] [288] [695] [474] +01- 1 +1-1 1 +.names din_i[5] [302] [695] [475] +01- 1 +1-1 1 +.names din_i[3] [289] [695] [476] +01- 1 +1-1 1 +.names din_i[4] [290] [695] [477] +01- 1 +1-1 1 +.names din_i[6] [291] [695] [478] +01- 1 +1-1 1 +.names din_i[7] [292] [695] [479] +01- 1 +1-1 1 +.names din_i[0] [293] [579] [480] +01- 1 +1-1 1 +.names din_i[2] [294] [618] [481] +01- 1 +1-1 1 +.names din_i[3] [295] [618] [482] +01- 1 +1-1 1 +.names din_i[4] [296] [579] [483] +01- 1 +1-1 1 +.names din_i[6] [297] [618] [484] +01- 1 +1-1 1 +.names din_i[7] [298] [579] [485] +01- 1 +1-1 1 +.names din_i[1] [282] [618] [486] +01- 1 +1-1 1 +.names [285] [596] [552] [487] +11- 0 +--1 0 +.names [585] [265] [553] [488] +11- 0 +--1 0 +.names [254] [568] [489] +01 1 +10 1 +.names [259] [596] [490] +00 0 +.names [326] [595] [541] [491] +11- 0 +--1 0 +.names [599] [560] rx_valid_reg_in +00 1 +.names [294] [578] [493] +11 0 +.names [298] [578] [494] +11 0 +.names [596] [301] [495] +11 0 +.names [295] [578] [496] +11 0 +.names [596] [612] [497] +11 0 +.names [297] [578] [498] +11 0 +.names [694] [578] [499] +00 0 +.names [692] [603] [500] +01 1 +10 1 +.names [588] [191] [542] [501] +11- 0 +--1 0 +.names [507] [502] +0 1 +.names [625] [682] [503] +11 0 +.names [505] [504] +0 1 +.names [603] [685] [505] +11 0 +.names \tx_fifo_wp_reg[0] [506] +1 1 +.names [679] [507] +0 1 +.names rxd_r_reg_in [587] [508] +01 1 +10 1 +.names [644] [182] [184] [643] rx_go_reg_in +1111 0 +.names shift_en_reg [510] +1 1 +.names [646] [637] [583] [511] +01- 1 +1-1 1 +.names din_i[2] [316] [661] [512] +01- 1 +1-1 1 +.names [635] [646] [595] [513] +01- 1 +1-1 1 +.names [649] [635] [595] [514] +01- 1 +1-1 1 +.names [641] [640] [595] [515] +01- 1 +1-1 1 +.names [321] [649] [595] [516] +01- 1 +1-1 1 +.names [640] [642] [583] [517] +01- 1 +1-1 1 +.names [313] din_i[7] [600] [518] +01- 1 +1-1 1 +.names [324] din_i[5] [600] [519] +01- 1 +1-1 1 +.names din_i[4] [318] [661] [520] +01- 1 +1-1 1 +.names [642] [634] [583] [521] +01- 1 +1-1 1 +.names din_i[6] [306] [661] [522] +01- 1 +1-1 1 +.names [310] din_i[0] [600] [523] +01- 1 +1-1 1 +.names [314] din_i[2] [600] [524] +01- 1 +1-1 1 +.names [311] din_i[3] [600] [525] +01- 1 +1-1 1 +.names [312] din_i[4] [600] [526] +01- 1 +1-1 1 +.names [323] din_i[6] [600] [527] +01- 1 +1-1 1 +.names [325] din_i[1] [600] [528] +01- 1 +1-1 1 +.names din_i[0] [315] [661] [529] +01- 1 +1-1 1 +.names din_i[1] [305] [661] [530] +01- 1 +1-1 1 +.names din_i[3] [317] [661] [531] +01- 1 +1-1 1 +.names din_i[5] [308] [661] [532] +01- 1 +1-1 1 +.names [637] [641] [583] [533] +01- 1 +1-1 1 +.names din_i[7] [319] [661] [534] +01- 1 +1-1 1 +.names [290] [694] [535] +11 0 +.names [287] [694] [536] +11 0 +.names [286] [694] [537] +11 0 +.names [577] [562] [538] +00 0 +.names re_i [691] \rx_fifo_rp_reg[0]_in +01 1 +10 1 +.names [558] [540] +0 1 +.names [616] [614] [595] [541] +11- 0 +--1 0 +.names [588] [191] [542] +00 1 +.names [602] [587] [543] +00 1 +.names [601] [318] [544] +11 0 +.names [628] [632] \tx_fifo_rp_reg[0]_in +01 1 +10 1 +.names [563] rx_sio_ce_r2_reg_in +0 1 +.names [601] [317] [547] +11 0 +.names [601] [308] [548] +11 0 +.names [601] [319] [549] +11 0 +.names [594] cts_i load_reg_in +00 1 +.names [593] [301] [551] +00 0 +.names [285] [596] [552] +00 1 +.names [585] [265] [553] +00 1 +.names [576] [554] +0 1 +.names [628] [630] [597] [555] +11- 0 +--1 0 +.names [662] [687] [556] +01 1 +10 1 +.names [562] [557] +1 1 +.names [566] [558] +0 1 +.names [577] [559] +1 1 +.names [629] [184] [560] +11 0 +.names [619] [323] [561] +11 0 +.names [692] [631] [562] +00 1 +.names rx_sio_ce_r1_reg [563] +0 1 +.names [609] [618] [564] +11 0 +.names [611] [191] [565] +11 0 +.names [625] [685] [566] +11 0 +.names [619] [324] [567] +11 0 +.names [621] [265] [568] +11 0 +.names [619] [314] [569] +11 0 +.names [619] [310] [570] +11 0 +.names [619] [325] [571] +11 0 +.names [612] [653] [572] +11 0 +.names [613] [407] [652] [573] +111 0 +.names [630] we_i \tx_fifo_wp_reg[0]_in +01 1 +10 1 +.names [629] [182] [575] +01 1 +10 1 +.names sio_ce_x4 rx_sio_ce_r1_reg_in [576] +11 1 +.names [691] [665] [577] +00 1 +.names [592] [578] +0 1 +.names [586] [579] +0 1 +.names [604] [616] shift_en_reg_in +00 0 +.names [692] [665] [581] +00 1 +.names [692] [665] [582] +11 1 +.names [620] [583] +0 1 +.names [454] [688] [584] +11 0 +.names [621] [585] +0 1 +.names [618] [586] +0 1 +.names rxd_r_reg [587] +0 1 +.names [611] [588] +0 1 +.names [309] [647] rst [589] +111 0 +.names [647] [283] [590] +11 0 +.names [632] [648] [591] +00 0 +.names [650] [300] [592] +11 0 +.names [510] [342] [593] +00 1 +.names [510] [655] [594] +00 0 +.names [620] [595] +0 1 +.names [620] [596] +0 1 +.names [628] [630] [597] +00 1 +.names [612] [598] +0 1 +.names [191] [182] [599] +00 0 +.names [608] [600] +0 1 +.names [622] [601] +0 1 +.names rxd_r_reg_in [433] [602] +00 0 +.names [625] [603] +0 1 +.names [656] [254] [604] +11 0 +.names [407] [652] rx_sio_ce_r1_reg_in +00 1 +.names [651] [693] [606] +00 0 +.names re_i [645] [607] +00 0 +.names [664] [663] [608] +11 0 +.names [506] [663] [609] +11 0 +.names [342] [639] [610] +11 0 +.names [643] [636] [611] +00 1 +.names [632] [612] +0 1 +.names [309] [647] [613] +00 1 +.names [633] [326] [614] +11 0 +.names [647] [407] [615] +11 0 +.names [633] [326] [616] +00 0 +.names [639] [653] [617] +00 1 +.names [664] [406] [618] +11 0 +.names [650] [688] [619] +11 1 +.names [654] [639] [620] +00 1 +.names [633] [638] [621] +00 1 +.names [650] [688] [622] +00 0 +.names [680] [693] [623] +11 0 +.names rxd_s_reg rxd_r_reg_in +1 1 +.names [680] [625] +0 1 +.names [645] [626] +0 1 +.names [407] [283] [627] +00 1 +.names [650] [628] +0 1 +.names [643] [629] +0 1 +.names [664] [630] +0 1 +.names [665] [631] +0 1 +.names [455] sio_ce [632] +11 1 +.names [285] [633] +0 1 +.names [259] [634] +0 1 +.names [257] [635] +0 1 +.names [182] [636] +0 1 +.names [266] [637] +0 1 +.names [326] [638] +0 1 +.names sio_ce [639] +0 1 +.names [261] [640] +0 1 +.names [264] [641] +0 1 +.names [260] [642] +0 1 +.names [190] [643] +0 1 +.names [191] [644] +0 1 +.names [147] [645] +0 1 +.names [256] [646] +0 1 +.names sio_ce_x4 [647] +0 1 +.names rst [648] +0 1 +.names [258] [649] +0 1 +.names [454] [650] +0 1 +.names [148] [651] +0 1 +.names [283] [652] +0 1 +.names [255] [653] +0 1 +.names [510] [654] +0 1 +.names [268] [655] +0 1 +.names [265] [656] +0 1 +.names [659] [658] [657] +00 1 +.names [676] [658] +0 1 +.names [660] [666] [659] +11 0 +.names [683] [665] [660] +11 0 +.names [662] [630] [661] +11 0 +.names [663] [662] +0 1 +.names [406] [663] +0 1 +.names [506] [664] +0 1 +.names [320] [665] +0 1 +.names [684] [320] [666] +11 0 +.names [681] [320] [147] [667] +111 0 +.names [669] [686] [147] [668] +111 0 +.names [320] [669] +0 1 +.names [671] [683] [672] \rx_fifo_wp_reg[1]_in +01- 1 +1-1 1 +.names [679] [566] [671] +11 0 +.names [678] [677] [672] +11 0 +.names [674] [677] [673] +11 0 +.names [675] [676] [674] +11 0 +.names [668] [667] [675] +11 0 +.names [606] [623] [676] +11 0 +.names [307] rx_valid_r_reg_in [677] +11 1 +.names [674] [678] +1 1 +.names [682] [680] [679] +11 0 +.names [148] [680] +0 1 +.names [686] [681] +0 1 +.names [685] [682] +0 1 +.names [684] [683] +0 1 +.names [685] [684] +1 1 +.names [686] [685] +1 1 +.names [183] [686] +0 1 +.names [688] [687] +0 1 +.names [300] [688] +0 1 +.names [690] [689] +0 1 +.names [503] [690] +0 1 +.names [692] [691] +0 1 +.names [693] [692] +1 1 +.names [432] [693] +0 1 +.names [584] [694] +0 1 +.names [609] [695] +1 1 +.names rxd_i rxd_s_reg_in +1 1 +.end diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/scf.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/scf.blif new file mode 100644 index 000000000..3e75ec395 --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/scf.blif @@ -0,0 +1,1187 @@ +.model TOP +.inputs scf_in_26_ scf_in_25_ scf_in_24_ scf_in_23_ scf_in_22_ scf_in_21_ \ +scf_in_20_ scf_in_19_ scf_in_18_ scf_in_17_ scf_in_16_ scf_in_15_ scf_in_14_ \ +scf_in_13_ scf_in_12_ scf_in_11_ scf_in_10_ scf_in_9_ scf_in_8_ scf_in_7_ \ +scf_in_6_ scf_in_5_ scf_in_4_ scf_in_3_ scf_in_2_ scf_in_1_ scf_in_0_ clock +.outputs scf_out_55_ scf_out_54_ scf_out_53_ scf_out_52_ scf_out_51_ \ +scf_out_50_ scf_out_49_ scf_out_48_ scf_out_47_ scf_out_46_ scf_out_45_ \ +scf_out_44_ scf_out_43_ scf_out_42_ scf_out_41_ scf_out_40_ scf_out_39_ \ +scf_out_38_ scf_out_37_ scf_out_36_ scf_out_35_ scf_out_34_ scf_out_33_ \ +scf_out_32_ scf_out_31_ scf_out_30_ scf_out_29_ scf_out_28_ scf_out_27_ \ +scf_out_26_ scf_out_25_ scf_out_24_ scf_out_23_ scf_out_22_ scf_out_21_ \ +scf_out_20_ scf_out_19_ scf_out_18_ scf_out_17_ scf_out_16_ scf_out_15_ \ +scf_out_14_ scf_out_13_ scf_out_12_ scf_out_11_ scf_out_10_ scf_out_9_ \ +scf_out_8_ scf_out_7_ scf_out_6_ scf_out_5_ scf_out_4_ scf_out_3_ scf_out_2_ \ +scf_out_1_ scf_out_0_ +.latch N_N89 N_N575 re clock 2 +.latch N_N90 N_N576 re clock 2 +.latch N_N91 [36] re clock 2 +.latch N_N92 scf_out_13_ re clock 2 +.latch N_N93 N_N579 re clock 2 +.latch N_N94 N_N580 re clock 2 +.latch N_N95 N_N581 re clock 2 +.names n182 n348 scf_out_55_ +01 1 +.names n417 scf_out_54_ +0 1 +.names n22 scf_out_53_ +0 1 +.names n23 scf_out_5_ scf_out_52_ +1- 1 +-1 1 +.names n179 n183 n387 scf_out_51_ +00- 1 +0-0 1 +.names n27 scf_out_50_ +0 1 +.names n32 scf_out_49_ +0 1 +.names n33 scf_out_48_ +0 1 +.names scf_out_0_ n327 scf_out_47_ +00 1 +.names n40 scf_out_46_ +0 1 +.names n58 scf_out_45_ +0 1 +.names n61 scf_out_44_ +0 1 +.names n43 scf_out_43_ +0 1 +.names n85 scf_out_42_ +0 1 +.names scf_out_41_ +.names n46 scf_out_40_ +0 1 +.names n50 scf_out_39_ +0 1 +.names n123 scf_out_38_ +0 1 +.names n315 scf_out_37_ +0 1 +.names scf_out_36_ +.names n55 scf_out_35_ +0 1 +.names n58 scf_out_34_ +0 1 +.names n59 scf_out_33_ +0 1 +.names n60 scf_out_32_ +0 1 +.names n123 n327 scf_out_31_ +00 1 +.names N_N576 scf_out_30_ +0 1 +.names n61 scf_out_29_ +0 1 +.names n62 scf_out_28_ +0 1 +.names n417 scf_out_26_ +0 1 +.names n48 scf_out_25_ +0 1 +.names n64 scf_out_24_ +0 1 +.names scf_out_55_ n41 n409 scf_out_23_ +1-- 1 +-0- 1 +--0 1 +.names n66 scf_out_22_ +0 1 +.names n19 scf_out_21_ +0 1 +.names n41 scf_out_20_ +0 1 +.names n67 scf_out_19_ +0 1 +.names n68 scf_out_18_ +0 1 +.names n69 scf_out_17_ +0 1 +.names n70 scf_out_16_ +0 1 +.names n41 scf_out_15_ +0 1 +.names scf_out_31_ n59 n324 scf_out_14_ +1-- 1 +-0- 1 +--0 1 +.names n30 n309 n330 scf_out_12_ +0-- 1 +-0- 1 +--0 1 +.names n75 scf_out_11_ +0 1 +.names n139 scf_out_10_ +0 1 +.names n355 scf_out_9_ +0 1 +.names n151 scf_out_7_ +0 1 +.names scf_out_3_ n44 n330 scf_out_6_ +1-- 1 +-0- 1 +--0 1 +.names n298 n338 scf_out_5_ +01 1 +.names N_N576 scf_out_4_ +0 1 +.names n30 n417 scf_out_3_ +0- 1 +-0 1 +.names N_N579 [36] scf_out_2_ +1- 1 +-1 1 +.names n104 scf_out_1_ +0 1 +.names [36] N_N579 scf_out_0_ +1- 1 +-0 1 +.names n150 n123 n20 +1- 1 +-1 1 +.names N_N576 n339 n21 +0- 1 +-1 1 +.names n20 n21 n19 +1- 1 +-1 1 +.names n57 n296 n297 n22 +11- 1 +1-1 1 +.names n148 n348 n23 +01 1 +.names n128 n304 n28 +1- 1 +-0 1 +.names n298 n193 n29 +1- 1 +-1 1 +.names n175 n234 n30 +1- 1 +-1 1 +.names scf_out_0_ n175 n182 n31 +1-- 1 +-1- 1 +--1 1 +.names n28 n29 n30 n31 n27 +1111 1 +.names n300 n301 n182 n299 n32 +111- 1 +11-1 1 +.names n305 n149 n35 +1- 1 +-1 1 +.names n298 n217 n36 +1- 1 +-1 1 +.names N_N580 n150 n102 n37 +1-- 1 +-1- 1 +--1 1 +.names scf_out_2_ n175 n251 n38 +1-- 1 +-1- 1 +--1 1 +.names scf_out_0_ n148 n320 n39 +1-- 1 +-1- 1 +--1 1 +.names n35 n36 n37 n38 n39 n302 n33 +111110 1 +.names n297 n325 n41 +1- 1 +-1 1 +.names n306 n307 n21 n298 n42 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n41 n42 n40 +11 1 +.names n128 n350 n44 +1- 1 +-1 1 +.names n254 n150 n45 +1- 1 +-1 1 +.names n44 n45 n43 +11 1 +.names scf_out_2_ n179 n222 n47 +1-- 1 +-1- 1 +--1 1 +.names n23 n56 n57 n48 +011 1 +.names n335 n320 n49 +1- 1 +-1 1 +.names n47 n42 n48 n49 n46 +1111 1 +.names n298 n195 n51 +1- 1 +-1 1 +.names n28 n148 n299 n52 +11- 1 +1-1 1 +.names n41 N_N580 n217 n296 n54 +10-- 1 +1-0- 1 +1--1 1 +.names n51 n52 n54 n312 n50 +1110 1 +.names scf_out_0_ n151 n320 n56 +1-- 1 +-1- 1 +--1 1 +.names n222 n304 n57 +1- 1 +-0 1 +.names n56 n57 n44 n55 +111 1 +.names n60 n195 n298 n58 +11- 1 +1-1 1 +.names n39 n57 n151 n348 n59 +111- 1 +11-0 1 +.names n308 n251 n20 n60 +11- 1 +1-1 1 +.names n309 n296 n127 n61 +11- 1 +1-1 1 +.names n57 n254 n320 n62 +11- 1 +1-1 1 +.names scf_out_0_ n321 n296 n21 n64 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n322 n323 scf_out_0_ n321 n66 +111- 1 +11-1 1 +.names n324 n298 n297 n67 +11- 1 +1-1 1 +.names n326 n38 n127 n325 n68 +111- 1 +11-1 1 +.names n328 n329 scf_out_2_ n327 n69 +111- 1 +11-1 1 +.names n250 n324 n348 n70 +11- 1 +-10 1 +.names [36] scf_out_13_ N_N581 n251 n75 +-0-1 1 +1-01 1 +.names n116 n117 n118 n119 n31 n45 n120 n121 n78 +11111111 1 +.names n78 N_N95 +0 1 +.names n184 n185 n181 n175 n79 +111- 1 +11-1 1 +.names n79 N_N93 +0 1 +.names scf_in_26_ n231 n240 n241 n80 +0-11 1 +-111 1 +.names n80 N_N91 +0 1 +.names N_N581 n264 n386 n388 n81 +11-- 1 +1-0- 1 +1--0 1 +.names scf_in_26_ n81 n351 n396 N_N90 +11-- 1 +1-0- 1 +1--0 1 +.names n195 n294 n295 n304 n84 +111- 1 +-110 1 +.names n84 N_N89 +0 1 +.names n310 n311 n296 n250 n85 +111- 1 +11-1 1 +.names N_N575 N_N579 n89 +1- 1 +-1 1 +.names scf_in_24_ [36] n89 n333 n86 +0-10 1 +-010 1 +.names [36] scf_out_2_ n341 n91 +11- 1 +-10 1 +.names N_N575 n333 n410 n95 +1-1 1 +-01 1 +.names scf_out_13_ n86 n91 n96 +11- 1 +0-1 1 +-11 1 +.names N_N576 n95 n96 n263 n93 +111- 1 +-110 1 +.names scf_in_17_ scf_in_16_ n161 n97 +0-0 1 +-00 1 +.names scf_out_13_ n123 n102 +1- 1 +-1 1 +.names N_N581 n102 N_N576 [36] n101 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n101 N_N575 n331 n105 +10- 1 +1-1 1 +-11 1 +.names scf_out_13_ n93 N_N581 n356 n106 +01-- 1 +0-0- 1 +-1-0 1 +--00 1 +.names N_N581 N_N576 n104 +1- 1 +-1 1 +.names n105 n106 scf_out_0_ n104 n103 +111- 1 +11-1 1 +.names scf_in_25_ n127 n144 n320 n107 +-0-0 1 +100- 1 +.names n193 n144 N_N576 n150 n115 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names scf_in_26_ N_N575 n112 +0- 1 +-0 1 +.names scf_out_13_ n104 n113 +1- 1 +-1 1 +.names n107 n115 n112 n113 n111 +011- 1 +01-1 1 +.names scf_in_26_ n103 N_N580 n116 +0-- 1 +-1- 1 +--1 1 +.names N_N576 n175 n253 n117 +1-- 1 +-1- 1 +--1 1 +.names n144 n335 n118 +1- 1 +-1 1 +.names n296 n127 n111 n123 n119 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n112 n104 scf_in_9_ n143 n120 +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names scf_in_0_ n306 n331 n359 n121 +0--1 1 +-1-1 1 +--11 1 +.names scf_in_11_ scf_out_0_ n124 +1- 1 +-1 1 +.names [36] N_N579 n123 +0- 1 +-1 1 +.names scf_in_24_ n124 N_N580 n123 n122 +01-- 1 +-11- 1 +-1-1 1 +.names N_N580 n127 n128 +0- 1 +-1 1 +.names scf_out_13_ N_N576 n127 +1- 1 +-0 1 +.names n128 n127 n198 n125 +11- 1 +1-0 1 +.names N_N576 n122 n333 n130 +11- 1 +0-0 1 +-10 1 +.names N_N579 n217 n341 n360 n131 +0--1 1 +-1-1 1 +--01 1 +.names [36] n125 n130 n131 n129 +0-11 1 +-111 1 +.names scf_out_0_ n104 n128 n339 n132 +0-0- 1 +00-0 1 +.names [36] n132 N_N575 n182 n135 +-11- 1 +1-10 1 +.names scf_in_11_ n21 n333 n140 +1-- 1 +-1- 1 +--0 1 +.names N_N579 N_N580 n138 +0- 1 +-0 1 +.names [36] scf_out_13_ N_N581 n139 +0-- 1 +-0- 1 +--1 1 +.names n135 n140 n138 n139 n137 +011- 1 +01-1 1 +.names scf_out_13_ scf_out_2_ n179 n145 +0-- 1 +-1- 1 +--1 1 +.names N_N580 n306 n333 n146 +1-- 1 +-1- 1 +--0 1 +.names N_N579 N_N580 n143 +1- 1 +-0 1 +.names scf_in_26_ N_N581 n144 +0- 1 +-1 1 +.names n145 n146 n143 n144 n142 +111- 1 +11-1 1 +.names scf_out_13_ n193 n148 +0- 1 +-1 1 +.names scf_in_26_ N_N575 n149 +0- 1 +-1 1 +.names N_N575 n175 n150 +1- 1 +-1 1 +.names N_N576 N_N580 n151 +1- 1 +-0 1 +.names n148 n149 n150 n151 n147 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n123 n338 n153 +01 1 +.names N_N579 n151 n153 n175 n152 +--10 1 +10-0 1 +.names scf_in_26_ n129 n137 n320 n156 +01-- 1 +-11- 1 +0--1 1 +--11 1 +.names N_N576 n138 n142 n150 n157 +01-- 1 +-11- 1 +0--1 1 +--11 1 +.names [36] N_N580 n147 n299 n158 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names n149 n152 n333 n337 n159 +10-- 1 +-00- 1 +-0-1 1 +.names n156 n157 n158 n159 n155 +1111 1 +.names scf_in_18_ scf_in_19_ n161 +1- 1 +-1 1 +.names n161 scf_in_17_ scf_in_19_ n160 +11- 1 +1-1 1 +.names [36] n127 n160 n344 n162 +-0-0 1 +100- 1 +.names scf_out_13_ scf_out_2_ N_N576 n365 n168 +0--1 1 +-0-1 1 +--11 1 +.names scf_out_0_ N_N580 n162 n168 n165 +1-01 1 +-001 1 +.names scf_out_13_ scf_out_2_ N_N580 n144 n169 +10-0 1 +1-10 1 +.names scf_in_26_ n183 n366 n368 n171 +10-- 1 +1-0- 1 +1--0 1 +.names scf_in_26_ N_N581 n175 +0- 1 +-0 1 +.names n165 n169 n171 n175 n174 +100- 1 +-001 1 +.names n149 n250 n338 n364 n180 +1--1 1 +-101 1 +.names N_N575 n144 n179 +1- 1 +-1 1 +.names n180 scf_out_13_ n179 n178 +11- 1 +1-1 1 +.names scf_out_13_ n151 n182 +0- 1 +-1 1 +.names N_N579 n128 n183 +1- 1 +-1 1 +.names n182 n183 scf_out_2_ n21 n181 +111- 1 +11-1 1 +.names n369 n144 n361 n368 n184 +11-- 1 +1-11 1 +.names N_N579 N_N575 n174 n178 n185 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names scf_in_16_ n161 n195 n186 +000 1 +.names scf_in_21_ scf_out_2_ n127 n186 n188 +-0-1 1 +100- 1 +.names n123 n251 n189 +10 1 +.names [36] n127 n192 +1- 1 +-1 1 +.names N_N576 N_N580 n193 +0- 1 +-0 1 +.names N_N576 n123 n192 n193 n191 +0-11 1 +-111 1 +.names N_N576 n339 n195 +1- 1 +-1 1 +.names scf_in_17_ n161 n196 +1- 1 +-1 1 +.names n148 n195 n196 n194 +11- 1 +1-1 1 +.names scf_in_19_ scf_in_18_ scf_in_17_ n198 +1-- 1 +-0- 1 +--1 1 +.names n127 n198 scf_in_11_ n21 n197 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n112 n188 n189 n400 n199 +01-- 1 +0-1- 1 +0--0 1 +.names scf_out_13_ n123 n144 n370 n202 +-0-0 1 +000- 1 +.names N_N576 n296 n298 n206 +01- 1 +1-1 1 +-11 1 +.names scf_in_26_ scf_out_0_ N_N580 n411 n207 +0--1 1 +-1-1 1 +--01 1 +.names n202 n320 n371 n373 n208 +01-- 1 +0-11 1 +.names n144 n251 n209 +1- 1 +-1 1 +.names n191 n197 n304 n306 n210 +11-- 1 +1-0- 1 +-1-1 1 +--01 1 +.names n327 [36] n194 n175 n212 +11-- 1 +1-1- 1 +1--1 1 +.names scf_out_13_ N_N579 n150 n213 +0-- 1 +-0- 1 +--1 1 +.names n199 n206 n207 n208 n209 n210 n212 n213 n205 +01111111 1 +.names scf_in_22_ n123 n263 n214 +0-0 1 +-10 1 +.names N_N579 n127 n161 n218 +0-- 1 +-1- 1 +--0 1 +.names scf_out_0_ n196 n339 n378 n219 +1--1 1 +-0-1 1 +--11 1 +.names scf_out_13_ N_N576 n217 +1- 1 +-1 1 +.names n218 n219 n214 n217 n216 +111- 1 +11-1 1 +.names scf_in_11_ n21 N_N579 n221 +0-- 1 +-1- 1 +--0 1 +.names scf_out_13_ n151 n222 +1- 1 +-1 1 +.names scf_out_13_ N_N579 n104 n223 +0-- 1 +-1- 1 +--1 1 +.names scf_in_11_ n195 n333 n224 +1-- 1 +-1- 1 +--0 1 +.names scf_in_24_ N_N576 n253 n225 +1-- 1 +-0- 1 +--1 1 +.names N_N581 n151 n216 n226 +01- 1 +1-1 1 +-11 1 +.names N_N580 n139 n227 +1- 1 +-1 1 +.names scf_out_0_ N_N579 N_N576 n251 n228 +10-- 1 +-00- 1 +1--1 1 +--01 1 +.names n221 n222 n223 n224 n225 n226 n227 n228 n220 +11111111 1 +.names scf_in_23_ N_N576 n139 n253 n229 +-00- 1 +10-0 1 +.names n151 n253 n234 +1- 1 +-1 1 +.names N_N575 n220 n229 n234 n231 +0-01 1 +-101 1 +.names [36] N_N580 n127 n333 n235 +0-1- 1 +-01- 1 +0--0 1 +-0-0 1 +.names [36] n150 n151 n375 n236 +0--0 1 +000- 1 +.names n149 n236 n376 n377 n240 +10-- 1 +-011 1 +.names n382 n380 n144 n183 n241 +111- 1 +11-1 1 +.names scf_out_13_ n333 n243 +0- 1 +-0 1 +.names N_N579 n102 N_N580 n243 n242 +01-1 1 +-111 1 +.names n242 n104 N_N580 n276 n245 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names N_N581 n390 n391 n412 n246 +1--0 1 +-110 1 +.names n21 n124 n263 n339 n247 +1-0- 1 +-10- 1 +1--1 1 +-1-1 1 +.names scf_in_23_ N_N579 n193 n395 n248 +0--1 1 +-1-1 1 +--11 1 +.names n245 n246 n247 n248 n244 +1111 1 +.names scf_out_13_ N_N580 n250 +0- 1 +-0 1 +.names scf_out_13_ N_N580 n251 +1- 1 +-0 1 +.names N_N579 n250 n251 n333 n249 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names N_N579 n148 n254 +0- 1 +-1 1 +.names scf_out_13_ n123 n253 +0- 1 +-1 1 +.names N_N580 n254 n253 n252 +01- 1 +-11 1 +.names N_N581 n249 n252 n256 +11- 1 +0-1 1 +-11 1 +.names n153 n297 n333 n335 n257 +01-1 1 +0-01 1 +.names n256 n257 scf_out_0_ n127 n255 +111- 1 +11-1 1 +.names scf_in_23_ [36] N_N575 n259 +1-1 1 +-01 1 +.names scf_out_2_ n196 n259 n333 n258 +1-10 1 +-110 1 +.names scf_in_20_ scf_out_13_ scf_out_2_ N_N575 n260 +--00 1 +000- 1 +.names n333 scf_in_11_ n263 +11 1 +.names N_N580 n260 n263 n262 +01- 1 +0-1 1 +.names N_N576 n258 n262 n339 n264 +0-1- 1 +00-0 1 +.names scf_out_0_ N_N581 n339 n385 n266 +0--0 1 +000- 1 +.names scf_in_16_ n124 n160 n333 n271 +11-- 1 +-11- 1 +-1-0 1 +.names scf_in_16_ [36] n195 n196 n272 +000- 1 +-001 1 +.names scf_in_20_ scf_out_2_ n217 n274 +1-- 1 +-1- 1 +--1 1 +.names scf_in_22_ n123 n217 n276 +1-- 1 +-1- 1 +--1 1 +.names n127 n153 n271 n346 n277 +10-- 1 +-01- 1 +1--0 1 +--10 1 +.names N_N579 n128 n222 n278 +11- 1 +0-1 1 +-11 1 +.names n221 n272 n274 n276 n277 n278 n273 +101111 1 +.names N_N575 n253 n368 n403 n280 +0-1- 1 +-111 1 +.names scf_out_2_ scf_out_0_ n21 n338 n281 +11-- 1 +1-1- 1 +-1-0 1 +--10 1 +.names [36] n193 n280 n281 n279 +0-11 1 +-111 1 +.names n138 n148 scf_out_13_ scf_out_0_ n282 +111- 1 +11-1 1 +.names scf_in_21_ scf_out_13_ N_N580 n331 n283 +-1-0 1 +0-00 1 +.names scf_out_0_ n104 n151 n420 n286 +00-- 1 +0-0- 1 +0--0 1 +.names [36] n104 N_N580 n148 n288 +1--0 1 +100- 1 +.names scf_in_26_ N_N575 n352 n415 n290 +10-0 1 +1-00 1 +.names n279 n144 n273 n320 n294 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n179 n282 n290 n405 n295 +1-01 1 +-101 1 +.names scf_out_0_ n150 n296 +1- 1 +-1 1 +.names N_N580 n217 n297 +1- 1 +-1 1 +.names N_N575 n304 n298 +1- 1 +-0 1 +.names scf_out_13_ n23 N_N580 n325 n300 +10-- 1 +-01- 1 +-0-1 1 +.names n193 n349 N_N579 n327 n301 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names scf_out_2_ n144 n299 +1- 1 +-1 1 +.names n175 n333 n304 +01 1 +.names n151 n304 n350 n302 +01- 1 +0-0 1 +.names scf_out_2_ n128 n305 +1- 1 +-1 1 +.names N_N575 n144 n306 +0- 1 +-1 1 +.names n123 n127 n307 +1- 1 +-1 1 +.names n112 n123 n222 n308 +1-- 1 +-1- 1 +--1 1 +.names n21 n325 n309 +1- 1 +-1 1 +.names n30 N_N579 n128 n320 n310 +10-- 1 +1-1- 1 +1--1 1 +.names n52 n317 n21 n298 n311 +111- 1 +11-1 1 +.names n123 n128 n149 n321 n312 +0--0 1 +000- 1 +.names [36] n298 n321 n340 n316 +01-- 1 +-11- 1 +0--1 1 +--11 1 +.names n56 n47 n309 n317 +111 1 +.names n49 n45 n251 n20 n318 +111- 1 +11-1 1 +.names n316 n317 n318 n315 +111 1 +.names N_N575 n175 n320 +0- 1 +-1 1 +.names n175 n222 n321 +1- 1 +-1 1 +.names n151 n349 n322 +1- 1 +-1 1 +.names n381 N_N579 n175 n148 n323 +11-- 1 +1-1- 1 +1--1 1 +.names n325 n338 n324 +1- 1 +-0 1 +.names n222 n350 n326 +1- 1 +-1 1 +.names scf_out_2_ n150 n325 +1- 1 +-1 1 +.names n144 n182 n234 n304 n328 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names n409 n37 n28 n329 +111 1 +.names n150 n195 n327 +1- 1 +-1 1 +.names n56 n148 n298 n330 +11- 1 +1-1 1 +.names scf_out_2_ N_N576 n331 +1- 1 +-0 1 +.names N_N579 [36] n333 +11 1 +.names scf_out_0_ n251 n335 +1- 1 +-1 1 +.names scf_out_13_ n104 n337 +0- 1 +-0 1 +.names N_N580 n127 n338 +00 1 +.names scf_out_13_ N_N580 n339 +0- 1 +-1 1 +.names scf_out_13_ N_N576 n340 +0- 1 +-0 1 +.names scf_in_15_ scf_in_14_ scf_in_13_ n341 +1-- 1 +-1- 1 +--1 1 +.names scf_in_11_ scf_out_0_ n344 +0- 1 +-1 1 +.names scf_in_8_ scf_in_7_ scf_in_6_ scf_in_5_ scf_in_4_ scf_in_3_ scf_in_2_ \ +scf_in_1_ n346 +1------- 1 +-1------ 1 +--1----- 1 +---1---- 1 +----1--- 1 +-----1-- 1 +------1- 1 +-------0 1 +.names N_N575 n304 n348 +11 1 +.names scf_in_26_ N_N579 n139 n349 +0-- 1 +-1- 1 +--1 1 +.names n144 n123 n350 +1- 1 +-1 1 +.names N_N575 n244 n255 n351 +11- 1 +0-1 1 +-11 1 +.names scf_in_24_ n21 N_N579 n283 n354 +1--0 1 +-1-0 1 +--10 1 +.names n123 n151 n286 n354 n352 +1-01 1 +-101 1 +.names [36] scf_out_13_ N_N581 n416 n355 +0--1 1 +-0-1 1 +--01 1 +.names [36] N_N576 n97 N_N581 n356 +0--0 1 +000- 1 +.names [36] n113 n149 n359 +1-- 1 +-1- 1 +--1 1 +.names scf_out_0_ n340 n361 +1- 1 +-1 1 +.names n361 scf_out_2_ n97 n195 n360 +11-- 1 +1-1- 1 +1--1 1 +.names scf_in_26_ n113 n364 +0- 1 +-1 1 +.names scf_in_11_ N_N579 n307 n339 n365 +1-1- 1 +-01- 1 +--11 1 +.names scf_out_0_ n217 n341 n367 +1-- 1 +-1- 1 +--1 1 +.names scf_in_25_ n307 n367 n366 +0-1 1 +-11 1 +.names n149 n333 n337 n369 +1-- 1 +-0- 1 +--0 1 +.names [36] n251 n368 +0- 1 +-1 1 +.names scf_in_26_ n149 n222 n338 n370 +01-- 1 +0-1- 1 +-1-0 1 +--10 1 +.names scf_in_20_ scf_out_2_ n217 n372 +0-- 1 +-1- 1 +--1 1 +.names scf_in_10_ scf_out_13_ n331 n372 n371 +0--1 1 +-0-1 1 +--11 1 +.names N_N579 N_N576 n151 n344 n373 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names n21 n175 n179 n338 n375 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names [36] N_N580 n128 n333 n376 +00-- 1 +-01- 1 +0--0 1 +--10 1 +.names n123 n339 N_N576 scf_out_0_ n377 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n148 [36] scf_in_10_ n340 n378 +11-- 1 +1-1- 1 +1--1 1 +.names scf_out_2_ n175 n250 n381 +1-- 1 +-1- 1 +--1 1 +.names N_N579 n175 n251 n381 n380 +0--1 1 +-1-1 1 +--11 1 +.names n235 n179 n382 +1- 1 +-1 1 +.names N_N575 n341 n384 +0- 1 +-0 1 +.names scf_in_17_ n195 n297 n384 n385 +0-1- 1 +-11- 1 +0--1 1 +-1-1 1 +.names scf_out_2_ n193 n387 +1- 1 +-1 1 +.names N_N579 n161 n195 n387 n386 +0--1 1 +-0-1 1 +--11 1 +.names n153 n338 n344 n346 n388 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names scf_in_25_ scf_in_9_ n102 n143 n390 +01-- 1 +-11- 1 +0--1 1 +--11 1 +.names scf_out_2_ N_N580 n127 n333 n391 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names scf_in_10_ scf_out_13_ n392 +1- 1 +-0 1 +.names n331 n392 [36] n250 n393 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names scf_in_19_ scf_in_17_ n333 n338 n395 +1--- 1 +-1-- 1 +--0- 1 +---0 1 +.names N_N580 n223 n266 n305 n396 +0-01 1 +-101 1 +.names scf_out_13_ scf_out_2_ n104 n400 +0-- 1 +-1- 1 +--1 1 +.names n123 n288 n297 n400 n398 +10-1 1 +-011 1 +.names scf_out_2_ N_N576 n151 n253 n401 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names scf_in_0_ n331 n403 +1- 1 +-1 1 +.names [36] n150 n128 n406 +1-- 1 +-1- 1 +--1 1 +.names n406 N_N576 N_N580 n296 n405 +11-- 1 +1-1- 1 +1--1 1 +.names n179 n305 n409 +1- 1 +-1 1 +.names [36] N_N576 N_N575 n410 +1-- 1 +-0- 1 +--0 1 +.names n149 n139 N_N580 n411 +1-- 1 +-1- 1 +--1 1 +.names N_N581 n148 n225 n393 n412 +10-- 1 +1-0- 1 +1--0 1 +.names N_N575 n398 n401 n415 +011 1 +.names scf_out_13_ N_N579 n416 +1- 1 +-1 1 +.names n296 n338 n417 +1- 1 +-0 1 +.names scf_in_12_ n217 n341 n420 +1-- 1 +-1- 1 +--1 1 +.names n155 N_N94 +0 1 +.names n205 N_N92 +0 1 +.names [36] scf_out_27_ +1 1 +.names [36] scf_out_8_ +1 1 +.end diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/simple_spi.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/simple_spi.blif new file mode 100644 index 000000000..d2c545b2a --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/simple_spi.blif @@ -0,0 +1,2055 @@ +# Benchmark "simple_spi" written by ABC on Mon Aug 29 15:33:11 2005 +.model simple_spi +.inputs clk_i rst_i cyc_i stb_i we_i miso_i adr_i[0] adr_i[1] dat_i[0] \ + dat_i[1] dat_i[2] dat_i[3] dat_i[4] dat_i[5] dat_i[6] dat_i[7] +.outputs dat_o[0] dat_o[1] dat_o[2] dat_o[3] dat_o[4] dat_o[5] dat_o[6] \ + dat_o[7] ack_o inta_o sck_o mosi_o + +.latch \tcnt_reg[1]_in \tcnt_reg[1] 2 +.latch rfifo_gb_reg_in rfifo_gb_reg 2 +.latch \tcnt_reg[0]_in \tcnt_reg[0] 2 +.latch spif_reg_in spif_reg 2 +.latch \rfifo_wp_reg[1]_in \rfifo_wp_reg[1] 0 +.latch \rfifo_wp_reg[0]_in \rfifo_wp_reg[0] 0 +.latch \rfifo_mem_reg[1][4]_in \rfifo_mem_reg[1][4] 2 +.latch \rfifo_mem_reg[1][5]_in \rfifo_mem_reg[1][5] 2 +.latch \rfifo_mem_reg[1][6]_in \rfifo_mem_reg[1][6] 2 +.latch \rfifo_mem_reg[1][7]_in \rfifo_mem_reg[1][7] 2 +.latch \rfifo_mem_reg[1][8]_in \rfifo_mem_reg[1][8] 2 +.latch \rfifo_mem_reg[2][1]_in \rfifo_mem_reg[2][1] 2 +.latch \rfifo_mem_reg[2][2]_in \rfifo_mem_reg[2][2] 2 +.latch \rfifo_mem_reg[2][3]_in \rfifo_mem_reg[2][3] 2 +.latch \rfifo_mem_reg[2][4]_in \rfifo_mem_reg[2][4] 2 +.latch \rfifo_mem_reg[2][5]_in \rfifo_mem_reg[2][5] 2 +.latch \rfifo_mem_reg[2][6]_in \rfifo_mem_reg[2][6] 2 +.latch \rfifo_mem_reg[2][7]_in \rfifo_mem_reg[2][7] 2 +.latch \rfifo_mem_reg[2][8]_in \rfifo_mem_reg[2][8] 2 +.latch \rfifo_mem_reg[1][1]_in \rfifo_mem_reg[1][1] 2 +.latch \rfifo_mem_reg[1][2]_in \rfifo_mem_reg[1][2] 2 +.latch \rfifo_mem_reg[1][3]_in \rfifo_mem_reg[1][3] 2 +.latch \rfifo_mem_reg[3][1]_in \rfifo_mem_reg[3][1] 2 +.latch \rfifo_mem_reg[3][2]_in \rfifo_mem_reg[3][2] 2 +.latch \rfifo_mem_reg[3][3]_in \rfifo_mem_reg[3][3] 2 +.latch \rfifo_mem_reg[3][4]_in \rfifo_mem_reg[3][4] 2 +.latch \rfifo_mem_reg[3][5]_in \rfifo_mem_reg[3][5] 2 +.latch \rfifo_mem_reg[3][6]_in \rfifo_mem_reg[3][6] 2 +.latch \rfifo_mem_reg[3][7]_in \rfifo_mem_reg[3][7] 2 +.latch \rfifo_mem_reg[3][8]_in \rfifo_mem_reg[3][8] 2 +.latch \rfifo_mem_reg[0][1]_in \rfifo_mem_reg[0][1] 2 +.latch \rfifo_mem_reg[0][2]_in \rfifo_mem_reg[0][2] 2 +.latch \rfifo_mem_reg[0][4]_in \rfifo_mem_reg[0][4] 2 +.latch \rfifo_mem_reg[0][5]_in \rfifo_mem_reg[0][5] 2 +.latch \rfifo_mem_reg[0][6]_in \rfifo_mem_reg[0][6] 2 +.latch \rfifo_mem_reg[0][8]_in \rfifo_mem_reg[0][8] 2 +.latch \rfifo_mem_reg[0][3]_in \rfifo_mem_reg[0][3] 2 +.latch \rfifo_mem_reg[0][7]_in \rfifo_mem_reg[0][7] 2 +.latch sck_o_reg_in sck_o_reg 2 +.latch \state_reg[0]_in \state_reg[0] 2 +.latch \bcnt_reg[0]_in \bcnt_reg[0] 2 +.latch \bcnt_reg[2]_in \bcnt_reg[2] 2 +.latch \clkcnt_reg[8]_in \clkcnt_reg[8] 2 +.latch \treg_reg[7]_in \treg_reg[7] 2 +.latch \bcnt_reg[1]_in \bcnt_reg[1] 2 +.latch \treg_reg[2]_in \treg_reg[2] 2 +.latch \treg_reg[3]_in \treg_reg[3] 2 +.latch \treg_reg[4]_in \treg_reg[4] 2 +.latch \treg_reg[5]_in \treg_reg[5] 2 +.latch \treg_reg[6]_in \treg_reg[6] 2 +.latch \treg_reg[0]_in \treg_reg[0] 2 +.latch \treg_reg[1]_in \treg_reg[1] 2 +.latch \clkcnt_reg[10]_in \clkcnt_reg[10] 2 +.latch \clkcnt_reg[7]_in \clkcnt_reg[7] 2 +.latch \clkcnt_reg[4]_in \clkcnt_reg[4] 2 +.latch \clkcnt_reg[3]_in \clkcnt_reg[3] 2 +.latch \clkcnt_reg[6]_in \clkcnt_reg[6] 2 +.latch \clkcnt_reg[9]_in \clkcnt_reg[9] 2 +.latch \clkcnt_reg[2]_in \clkcnt_reg[2] 2 +.latch \clkcnt_reg[0]_in \clkcnt_reg[0] 2 +.latch \clkcnt_reg[1]_in \clkcnt_reg[1] 2 +.latch \clkcnt_reg[5]_in \clkcnt_reg[5] 2 +.latch \state_reg[1]_in \state_reg[1] 2 +.latch rfwe_reg_in rfwe_reg 2 +.latch \clkcnt_reg[11]_in \clkcnt_reg[11] 2 +.latch \dat_o_reg[6]_in \dat_o_reg[6] 2 +.latch wfifo_gb_reg_in wfifo_gb_reg 2 +.latch \dat_o_reg[3]_in \dat_o_reg[3] 2 +.latch \dat_o_reg[2]_in \dat_o_reg[2] 2 +.latch \dat_o_reg[1]_in \dat_o_reg[1] 2 +.latch \dat_o_reg[5]_in \dat_o_reg[5] 2 +.latch \dat_o_reg[0]_in \dat_o_reg[0] 2 +.latch wcol_reg_in wcol_reg 2 +.latch \dat_o_reg[7]_in \dat_o_reg[7] 2 +.latch \dat_o_reg[4]_in \dat_o_reg[4] 2 +.latch \rfifo_rp_reg[1]_in \rfifo_rp_reg[1] 0 +.latch \wfifo_rp_reg[1]_in \wfifo_rp_reg[1] 0 +.latch \rfifo_rp_reg[0]_in \rfifo_rp_reg[0] 0 +.latch \wfifo_mem_reg[2][5]_in \wfifo_mem_reg[2][5] 2 +.latch \wfifo_mem_reg[1][7]_in \wfifo_mem_reg[1][7] 2 +.latch \wfifo_mem_reg[2][1]_in \wfifo_mem_reg[2][1] 2 +.latch \wfifo_mem_reg[1][5]_in \wfifo_mem_reg[1][5] 2 +.latch \wfifo_wp_reg[1]_in \wfifo_wp_reg[1] 0 +.latch \wfifo_wp_reg[0]_in \wfifo_wp_reg[0] 0 +.latch \wfifo_mem_reg[1][1]_in \wfifo_mem_reg[1][1] 2 +.latch \wfifo_mem_reg[1][2]_in \wfifo_mem_reg[1][2] 2 +.latch \wfifo_mem_reg[1][3]_in \wfifo_mem_reg[1][3] 2 +.latch \wfifo_mem_reg[1][4]_in \wfifo_mem_reg[1][4] 2 +.latch \wfifo_mem_reg[1][6]_in \wfifo_mem_reg[1][6] 2 +.latch \wfifo_mem_reg[1][8]_in \wfifo_mem_reg[1][8] 2 +.latch \wfifo_mem_reg[2][2]_in \wfifo_mem_reg[2][2] 2 +.latch \wfifo_mem_reg[2][3]_in \wfifo_mem_reg[2][3] 2 +.latch \wfifo_mem_reg[2][4]_in \wfifo_mem_reg[2][4] 2 +.latch \wfifo_mem_reg[2][6]_in \wfifo_mem_reg[2][6] 2 +.latch \wfifo_mem_reg[2][7]_in \wfifo_mem_reg[2][7] 2 +.latch \wfifo_mem_reg[2][8]_in \wfifo_mem_reg[2][8] 2 +.latch \wfifo_mem_reg[0][5]_in \wfifo_mem_reg[0][5] 2 +.latch \wfifo_mem_reg[3][5]_in \wfifo_mem_reg[3][5] 2 +.latch \wfifo_mem_reg[3][1]_in \wfifo_mem_reg[3][1] 2 +.latch \wfifo_mem_reg[0][8]_in \wfifo_mem_reg[0][8] 2 +.latch \wfifo_mem_reg[0][1]_in \wfifo_mem_reg[0][1] 2 +.latch \wfifo_mem_reg[0][2]_in \wfifo_mem_reg[0][2] 2 +.latch \wfifo_mem_reg[0][3]_in \wfifo_mem_reg[0][3] 2 +.latch \wfifo_mem_reg[0][4]_in \wfifo_mem_reg[0][4] 2 +.latch \wfifo_mem_reg[0][7]_in \wfifo_mem_reg[0][7] 2 +.latch \wfifo_mem_reg[0][6]_in \wfifo_mem_reg[0][6] 2 +.latch \wfifo_mem_reg[3][2]_in \wfifo_mem_reg[3][2] 2 +.latch \wfifo_mem_reg[3][3]_in \wfifo_mem_reg[3][3] 2 +.latch \wfifo_mem_reg[3][4]_in \wfifo_mem_reg[3][4] 2 +.latch \wfifo_mem_reg[3][6]_in \wfifo_mem_reg[3][6] 2 +.latch \wfifo_mem_reg[3][7]_in \wfifo_mem_reg[3][7] 2 +.latch \wfifo_mem_reg[3][8]_in \wfifo_mem_reg[3][8] 2 +.latch \sper_reg[5]_in \sper_reg[5] 0 +.latch wfre_reg_in wfre_reg 2 +.latch \sper_reg[0]_in \sper_reg[0] 0 +.latch \sper_reg[1]_in \sper_reg[1] 0 +.latch \sper_reg[2]_in \sper_reg[2] 0 +.latch \sper_reg[3]_in \sper_reg[3] 0 +.latch \sper_reg[4]_in \sper_reg[4] 0 +.latch \sper_reg[6]_in \sper_reg[6] 0 +.latch \sper_reg[7]_in \sper_reg[7] 0 +.latch \spcr_reg[7]_in \spcr_reg[7] 0 +.latch \spcr_reg[5]_in \spcr_reg[5] 0 +.latch \spcr_reg[0]_in \spcr_reg[0] 0 +.latch \spcr_reg[2]_in \spcr_reg[2] 0 +.latch \spcr_reg[4]_in \spcr_reg[4] 1 +.latch \spcr_reg[1]_in \spcr_reg[1] 0 +.latch \spcr_reg[3]_in \spcr_reg[3] 0 +.latch \spcr_reg[6]_in \spcr_reg[6] 0 +.latch \wfifo_rp_reg[0]_in \wfifo_rp_reg[0] 0 +.latch ack_o_reg_in ack_o_reg 0 +.latch inta_o_reg_in inta_o_reg 2 + +.names [160] + 0 +.names [161] + 1 +.names \tcnt_reg[1] [162] +1 1 +.names rfifo_gb_reg [163] +1 1 +.names [243] [203] \tcnt_reg[1]_in +11 0 +.names \tcnt_reg[0] [165] +1 1 +.names spif_reg [166] +1 1 +.names [574] [241] [767] rfifo_gb_reg_in +11- 0 +--1 0 +.names \rfifo_wp_reg[1] [168] +1 1 +.names \rfifo_wp_reg[0] [169] +1 1 +.names \rfifo_mem_reg[1][4] [170] +1 1 +.names \rfifo_mem_reg[1][5] [171] +1 1 +.names \rfifo_mem_reg[1][6] [172] +1 1 +.names \rfifo_mem_reg[1][7] [173] +1 1 +.names \rfifo_mem_reg[1][8] [174] +1 1 +.names \rfifo_mem_reg[2][1] [175] +1 1 +.names \rfifo_mem_reg[2][2] [176] +1 1 +.names \rfifo_mem_reg[2][3] [177] +1 1 +.names \rfifo_mem_reg[2][4] [178] +1 1 +.names \rfifo_mem_reg[2][5] [179] +1 1 +.names \rfifo_mem_reg[2][6] [180] +1 1 +.names \rfifo_mem_reg[2][7] [181] +1 1 +.names \rfifo_mem_reg[2][8] [182] +1 1 +.names \rfifo_mem_reg[1][1] [183] +1 1 +.names \rfifo_mem_reg[1][2] [184] +1 1 +.names \rfifo_mem_reg[1][3] [185] +1 1 +.names \rfifo_mem_reg[3][1] [186] +1 1 +.names \rfifo_mem_reg[3][2] [187] +1 1 +.names \rfifo_mem_reg[3][3] [188] +1 1 +.names \rfifo_mem_reg[3][4] [189] +1 1 +.names \rfifo_mem_reg[3][5] [190] +1 1 +.names \rfifo_mem_reg[3][6] [191] +1 1 +.names \rfifo_mem_reg[3][7] [192] +1 1 +.names \rfifo_mem_reg[3][8] [193] +1 1 +.names \rfifo_mem_reg[0][1] [194] +1 1 +.names \rfifo_mem_reg[0][2] [195] +1 1 +.names \rfifo_mem_reg[0][4] [196] +1 1 +.names \rfifo_mem_reg[0][5] [197] +1 1 +.names \rfifo_mem_reg[0][6] [198] +1 1 +.names \rfifo_mem_reg[0][8] [199] +1 1 +.names \rfifo_mem_reg[0][3] [200] +1 1 +.names \rfifo_mem_reg[0][7] [201] +1 1 +.names [531] [239] spif_reg_in +11 0 +.names [240] [836] [203] +11 0 +.names [465] [244] [831] \tcnt_reg[0]_in +01- 1 +1-1 1 +.names [640] [172] [272] \rfifo_mem_reg[1][6]_in +01- 1 +1-1 1 +.names [641] [173] [272] \rfifo_mem_reg[1][7]_in +01- 1 +1-1 1 +.names [650] [174] [272] \rfifo_mem_reg[1][8]_in +01- 1 +1-1 1 +.names [648] [175] [272] \rfifo_mem_reg[2][1]_in +01- 1 +1-1 1 +.names [644] [176] [272] \rfifo_mem_reg[2][2]_in +01- 1 +1-1 1 +.names [647] [178] [272] \rfifo_mem_reg[2][4]_in +01- 1 +1-1 1 +.names [646] [177] [272] \rfifo_mem_reg[2][3]_in +01- 1 +1-1 1 +.names [645] [179] [272] \rfifo_mem_reg[2][5]_in +01- 1 +1-1 1 +.names [654] [180] [272] \rfifo_mem_reg[2][6]_in +01- 1 +1-1 1 +.names [643] [181] [272] \rfifo_mem_reg[2][7]_in +01- 1 +1-1 1 +.names [651] [182] [272] \rfifo_mem_reg[2][8]_in +01- 1 +1-1 1 +.names [649] [183] [272] \rfifo_mem_reg[1][1]_in +01- 1 +1-1 1 +.names [653] [184] [272] \rfifo_mem_reg[1][2]_in +01- 1 +1-1 1 +.names [655] [185] [272] \rfifo_mem_reg[1][3]_in +01- 1 +1-1 1 +.names [705] [186] [272] \rfifo_mem_reg[3][1]_in +01- 1 +1-1 1 +.names [698] [187] [272] \rfifo_mem_reg[3][2]_in +01- 1 +1-1 1 +.names [706] [188] [272] \rfifo_mem_reg[3][3]_in +01- 1 +1-1 1 +.names [697] [189] [272] \rfifo_mem_reg[3][4]_in +01- 1 +1-1 1 +.names [701] [190] [272] \rfifo_mem_reg[3][5]_in +01- 1 +1-1 1 +.names [699] [191] [272] \rfifo_mem_reg[3][6]_in +01- 1 +1-1 1 +.names [700] [192] [272] \rfifo_mem_reg[3][7]_in +01- 1 +1-1 1 +.names [702] [193] [272] \rfifo_mem_reg[3][8]_in +01- 1 +1-1 1 +.names [743] [194] [272] \rfifo_mem_reg[0][1]_in +01- 1 +1-1 1 +.names [744] [195] [272] \rfifo_mem_reg[0][2]_in +01- 1 +1-1 1 +.names [745] [200] [272] \rfifo_mem_reg[0][3]_in +01- 1 +1-1 1 +.names [746] [196] [272] \rfifo_mem_reg[0][4]_in +01- 1 +1-1 1 +.names [736] [197] [272] \rfifo_mem_reg[0][5]_in +01- 1 +1-1 1 +.names [737] [198] [272] \rfifo_mem_reg[0][6]_in +01- 1 +1-1 1 +.names [747] [201] [272] \rfifo_mem_reg[0][7]_in +01- 1 +1-1 1 +.names [748] [199] [272] \rfifo_mem_reg[0][8]_in +01- 1 +1-1 1 +.names [248] [252] [971] \rfifo_wp_reg[1]_in +11- 0 +--1 0 +.names [246] [247] [971] \rfifo_wp_reg[0]_in +11- 0 +--1 0 +.names [652] [170] [272] \rfifo_mem_reg[1][4]_in +01- 1 +1-1 1 +.names [642] [171] [272] \rfifo_mem_reg[1][5]_in +01- 1 +1-1 1 +.names [249] [627] [876] [239] +111 0 +.names [253] [245] [240] +11 0 +.names [250] [722] [241] +11 0 +.names sck_o_reg sck_o +1 1 +.names [809] [272] [473] [844] [243] +11-- 0 +--11 0 +.names [776] [272] [268] [244] +00- 1 +--0 1 +.names [270] [853] [165] [245] +111 0 +.names [882] [272] [246] +11 0 +.names [882] [272] [247] +00 0 +.names [168] [272] [248] +11 0 +.names [272] [859] [249] +00 1 +.names [685] [272] [250] +00 1 +.names \state_reg[0] [251] +1 1 +.names [760] [272] [252] +00 0 +.names [269] [876] [253] +11 0 +.names \bcnt_reg[0] [254] +1 1 +.names [267] sck_o_reg_in +0 1 +.names \bcnt_reg[2] [256] +1 1 +.names \clkcnt_reg[8] [257] +1 1 +.names \treg_reg[7] mosi_o +1 1 +.names \bcnt_reg[1] [259] +1 1 +.names \treg_reg[2] [260] +1 1 +.names \treg_reg[3] [261] +1 1 +.names \treg_reg[4] [262] +1 1 +.names \treg_reg[5] [263] +1 1 +.names \treg_reg[6] [264] +1 1 +.names \treg_reg[0] [265] +1 1 +.names \treg_reg[1] [266] +1 1 +.names [932] [771] [267] +11 0 +.names [165] [297] [268] +11 0 +.names [297] [903] [269] +00 1 +.names [297] [902] [270] +00 1 +.names [279] \state_reg[0]_in +0 1 +.names [285] [272] +0 1 +.names [298] [333] \clkcnt_reg[8]_in +11 0 +.names [414] [300] [814] \treg_reg[0]_in +11- 0 +--1 0 +.names [322] [975] [971] \bcnt_reg[2]_in +11- 0 +--1 0 +.names [415] [308] [859] \treg_reg[1]_in +11- 0 +--1 0 +.names [416] [309] [859] \treg_reg[2]_in +11- 0 +--1 0 +.names [417] [311] [859] \treg_reg[3]_in +11- 0 +--1 0 +.names [299] [771] [279] +11 0 +.names [418] [312] [814] \treg_reg[4]_in +11- 0 +--1 0 +.names [419] [313] [814] \treg_reg[5]_in +11- 0 +--1 0 +.names [420] [314] [859] \treg_reg[6]_in +11- 0 +--1 0 +.names [315] [411] [814] \treg_reg[7]_in +11- 0 +--1 0 +.names [305] [975] [971] \bcnt_reg[1]_in +11- 0 +--1 0 +.names [297] [285] +0 1 +.names \clkcnt_reg[10] [286] +1 1 +.names \clkcnt_reg[7] [287] +1 1 +.names \clkcnt_reg[4] [288] +1 1 +.names \clkcnt_reg[3] [289] +1 1 +.names \clkcnt_reg[6] [290] +1 1 +.names \clkcnt_reg[9] [291] +1 1 +.names \clkcnt_reg[2] [292] +1 1 +.names \clkcnt_reg[0] [293] +1 1 +.names \clkcnt_reg[1] [294] +1 1 +.names \clkcnt_reg[5] [295] +1 1 +.names \state_reg[1] [296] +1 1 +.names rfwe_reg [297] +0 1 +.names [537] [388] [324] [298] +11- 0 +--1 0 +.names [365] [528] [372] [758] [299] +1111 0 +.names [358] [977] [265] [973] [300] +11-- 0 +--11 0 +.names [325] rfwe_reg_in +0 1 +.names [348] [332] \clkcnt_reg[4]_in +11 0 +.names [351] [334] \clkcnt_reg[0]_in +11 0 +.names [350] [337] \clkcnt_reg[2]_in +11 0 +.names [356] [977] [873] [973] [305] +11-- 0 +--11 0 +.names \clkcnt_reg[11] [306] +1 1 +.names [340] [338] \clkcnt_reg[3]_in +11 0 +.names [359] [977] [266] [973] [308] +11-- 0 +--11 0 +.names [360] [977] [260] [973] [309] +11-- 0 +--11 0 +.names \dat_o_reg[6] dat_o[6] +1 1 +.names [361] [977] [261] [973] [311] +11-- 0 +--11 0 +.names [362] [977] [262] [973] [312] +11-- 0 +--11 0 +.names [363] [977] [263] [973] [313] +11-- 0 +--11 0 +.names [364] [977] [264] [973] [314] +11-- 0 +--11 0 +.names [357] [977] [973] mosi_o [315] +11-- 0 +--11 0 +.names [353] [334] \clkcnt_reg[1]_in +11 0 +.names [349] [336] \clkcnt_reg[10]_in +11 0 +.names [354] [332] \clkcnt_reg[5]_in +11 0 +.names [335] [343] \clkcnt_reg[7]_in +11 0 +.names [365] [830] [339] \state_reg[1]_in +00- 1 +--0 1 +.names [370] [333] \clkcnt_reg[9]_in +11 0 +.names [373] [977] [869] [973] [322] +11-- 0 +--11 0 +.names [341] [331] \clkcnt_reg[6]_in +11 0 +.names [753] [382] [838] [324] +11- 0 +--1 0 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[770] [428] [674] +11 0 +.names [770] [432] [675] +11 0 +.names ack_o_reg ack_o +1 1 +.names [459] [855] [677] +01 1 +10 1 +.names [726] [678] +0 1 +.names [728] [679] +0 1 +.names [942] [774] [680] +11 0 +.names [812] [915] [774] [681] +11- 0 +--1 0 +.names [858] [901] [804] [682] +111 0 +.names [770] [410] [683] +11 0 +.names [950] [954] [326] [684] +111 0 +.names [880] [913] [787] [685] +01- 1 +1-1 1 +.names dat_i[6] [752] [686] +11 1 +.names [732] [687] +0 1 +.names [847] [918] [688] +00 1 +.names [849] [752] [689] +11 1 +.names [510] [849] [461] [826] [690] +11-- 0 +--11 0 +.names [488] [849] [462] [826] [691] +11-- 0 +--11 0 +.names [500] [849] [464] [826] [692] +11-- 0 +--11 0 +.names [485] [849] [458] [826] [693] +11-- 0 +--11 0 +.names [826] [465] [891] [798] [694] +11-- 0 +--11 0 +.names [827] [186] [175] [792] [695] +11-- 0 +--11 0 +.names [827] [193] [182] [792] [696] +11-- 0 +--11 0 +.names [261] [189] [825] [697] +01- 1 +1-1 1 +.names [266] [187] [825] [698] +01- 1 +1-1 1 +.names [263] [191] [825] [699] +01- 1 +1-1 1 +.names [264] [192] [825] [700] +01- 1 +1-1 1 +.names [262] [190] [825] [701] +01- 1 +1-1 1 +.names mosi_o [193] [825] [702] +01- 1 +1-1 1 +.names [894] [849] [782] [703] +00- 1 +--0 1 +.names [849] [844] [780] [704] +00- 1 +--0 1 +.names [265] [186] [825] [705] +01- 1 +1-1 1 +.names [260] [188] [825] [706] +01- 1 +1-1 1 +.names [759] [707] +0 1 +.names [752] [708] +0 1 +.names [404] [789] [709] +11 1 +.names [181] [792] [710] +11 0 +.names [172] [797] [711] +11 1 +.names [403] [789] [712] +11 1 +.names [823] [802] [713] +11 0 +.names [170] [797] [714] +11 1 +.names [171] [797] [715] +11 1 +.names [389] [789] [716] +11 1 +.names [176] [792] [717] +11 1 +.names [401] [789] [718] +11 1 +.names [391] [789] [719] +11 0 +.names [405] [789] [720] +11 1 +.names [793] [790] [721] +11 0 +.names [884] [882] [807] [722] +11- 0 +--1 0 +.names [761] [723] +0 1 +.names [762] [724] +0 1 +.names [848] [846] [919] [725] +111 0 +.names [813] [812] [726] +11 1 +.names [779] [811] [727] +00 1 +.names [839] [869] [778] [728] +11- 0 +--1 0 +.names [177] [792] [729] +11 1 +.names [406] [789] [730] +11 1 +.names [511] [897] [832] [731] +01- 1 +1-1 1 +.names [777] [804] [732] +11 1 +.names [781] [824] [733] +11 0 +.names [402] [789] [734] +11 0 +.names [775] [735] +0 1 +.names [197] [262] [856] [736] +01- 1 +1-1 1 +.names [198] [263] [856] [737] +01- 1 +1-1 1 +.names [510] dat_i[1] [849] [738] +01- 1 +1-1 1 +.names [488] dat_i[2] [849] [739] +01- 1 +1-1 1 +.names [511] dat_i[3] [849] [740] +01- 1 +1-1 1 +.names [485] dat_i[5] [849] [741] +01- 1 +1-1 1 +.names [484] dat_i[7] [849] [742] +01- 1 +1-1 1 +.names [194] [265] [856] [743] +01- 1 +1-1 1 +.names [195] [266] [856] [744] +01- 1 +1-1 1 +.names [200] [260] [856] [745] +01- 1 +1-1 1 +.names [196] [261] [856] [746] +01- 1 +1-1 1 +.names [201] [264] [856] [747] +01- 1 +1-1 1 +.names [199] mosi_o [856] [748] +01- 1 +1-1 1 +.names [810] [749] +0 1 +.names [827] [191] [750] +11 0 +.names [827] [190] [751] +11 0 +.names [777] [752] +1 1 +.names [844] [765] [753] +00 1 +.names [827] [189] [754] +11 0 +.names [827] [188] [755] +11 0 +.names [865] ack_o ack_o_reg_in +00 1 +.names [163] [816] [757] +00 1 +.names [821] [885] [758] +00 0 +.names [254] [873] [829] [759] +11- 0 +--1 0 +.names [787] [760] +0 1 +.names [790] [761] +0 1 +.names [793] [762] +0 1 +.names [796] [763] +0 1 +.names [799] [764] +1 1 +.names [974] [765] +0 1 +.names [878] [871] [766] +00 1 +.names rst_i [512] [767] +11 0 +.names [881] [872] [768] +11 0 +.names [800] [769] +0 1 +.names [890] [893] [770] +11 1 +.names [814] [771] +0 1 +.names [837] [824] [772] +11 0 +.names [954] [773] +0 1 +.names [811] [774] +0 1 +.names [852] [486] [461] [775] +11- 0 +--1 0 +.names [465] [876] [834] [776] +11- 0 +--1 0 +.names [858] we_i [777] +11 1 +.names [832] [778] +0 1 +.names [848] [868] [779] +11 0 +.names [849] dat_i[6] [780] +11 0 +.names [843] [461] [781] +00 1 +.names [849] dat_i[0] [782] +11 0 +.names [864] [195] [783] +11 0 +.names [864] [194] [784] +11 0 +.names [864] [201] [785] +11 0 +.names [864] [199] [786] +11 0 +.names [841] [845] [787] +11 0 +.names [861] [842] [788] +11 0 +.names [819] [789] +0 1 +.names [881] [908] [790] +11 0 +.names [835] [791] +0 1 +.names [820] [792] +0 1 +.names [912] [872] [793] +11 0 +.names [821] [794] +0 1 +.names [860] [795] +0 1 +.names [855] [893] [796] +11 0 +.names [822] [797] +0 1 +.names [816] [798] +0 1 +.names [890] [893] [799] +00 1 +.names [912] [908] [800] +11 0 +.names [906] [859] [801] +00 1 +.names [878] [854] [802] +00 1 +.names [880] [168] [803] +01 1 +10 1 +.names [860] [892] [804] +00 1 +.names [857] [510] [805] +00 0 +.names [852] [461] [806] +00 0 +.names [904] [895] [807] +11 1 +.names [864] [196] [808] +11 0 +.names [902] [844] [809] +00 1 +.names [883] [877] [846] [810] +11- 0 +--1 0 +.names [965] [957] [886] [958] [811] +1111 0 +.names [846] [957] [812] +11 0 +.names [846] [957] [813] +00 0 +.names [836] [814] +0 1 +.names [885] [296] [815] +11 0 +.names [910] adr_i[1] [816] +00 0 +.names [907] [326] [817] +11 0 +.names [843] [818] +0 1 +.names [890] [879] [819] +11 0 +.names [904] [379] [820] +11 0 +.names [251] [914] [821] +11 0 +.names [884] [913] [822] +11 0 +.names [920] [823] +0 1 +.names [486] [510] [824] +11 0 +.names [882] [168] [825] +11 0 +.names adr_i[0] adr_i[1] [826] +11 1 +.names [850] [827] +0 1 +.names [510] [461] [828] +11 1 +.names [839] [829] +0 1 +.names [512] [830] +0 1 +.names [844] [831] +0 1 +.names [979] [909] [911] [832] +111 0 +.names inta_o_reg inta_o +1 1 +.names [876] [165] [834] +00 1 +.names [845] [835] +0 1 +.names [971] [836] +0 1 +.names [857] [837] +0 1 +.names [894] [888] [838] +00 0 +.names [979] [909] [839] +11 0 +.names [893] [908] [840] +11 0 +.names [895] [168] [841] +11 0 +.names [898] [511] [842] +11 0 +.names [894] [460] [843] +11 1 +.names [512] [844] +0 1 +.names [169] [889] [845] +11 0 +.names [958] [886] [846] +11 1 +.names [925] [886] [847] +11 0 +.names [926] [925] [848] +11 1 +.names [910] [887] [849] +11 1 +.names [904] [913] [850] +00 0 +.names [893] [908] [851] +00 0 +.names [905] [900] [852] +00 1 +.names [876] [853] +0 1 +.names [868] [854] +0 1 +.names [890] [855] +0 1 +.names [895] [889] [856] +11 1 +.names [900] [888] [857] +11 0 +.names [865] [858] +0 1 +.names [512] [859] +0 1 +.names [910] adr_i[1] [860] +11 0 +.names [488] [897] [861] +11 0 +.names [878] [862] +0 1 +.names [926] [922] [863] +11 1 +.names [904] [913] [864] +11 1 +.names cyc_i stb_i [865] +11 0 +.names [885] [866] +0 1 +.names [926] [867] +0 1 +.names [924] [868] +1 1 +.names [911] [869] +0 1 +.names [948] [870] +0 1 +.names [947] [871] +0 1 +.names [908] [872] +0 1 +.names [909] [873] +0 1 +.names [925] [874] +0 1 +.names [484] [166] inta_o_reg_in +11 1 +.names [165] [162] [876] +00 1 +.names [886] [877] +0 1 +.names [959] [878] +0 1 +.names [893] [879] +0 1 +.names [913] [880] +0 1 +.names [912] [881] +0 1 +.names [895] [882] +0 1 +.names [958] [883] +0 1 +.names [904] [884] +0 1 +.names [251] [885] +0 1 +.names [293] [886] +0 1 +.names adr_i[1] [887] +0 1 +.names [461] [888] +0 1 +.names [168] [889] +0 1 +.names [513] [890] +0 1 +.names [345] [891] +0 1 +.names ack_o [892] +0 1 +.names [380] [893] +0 1 +.names [486] [894] +0 1 +.names [169] [895] +0 1 +.names [296] [896] +0 1 +.names sck_o [897] +0 1 +.names [488] [898] +0 1 +.names [173] [899] +0 1 +.names [460] [900] +0 1 +.names we_i [901] +0 1 +.names [162] [902] +0 1 +.names [473] [903] +0 1 +.names [385] [904] +0 1 +.names [510] [905] +0 1 +.names [166] [906] +0 1 +.names [459] [907] +0 1 +.names [393] [908] +0 1 +.names [259] [909] +0 1 +.names adr_i[0] [910] +0 1 +.names [256] [911] +0 1 +.names [394] [912] +0 1 +.names [379] [913] +0 1 +.names [296] [914] +0 1 +.names [965] [915] +0 1 +.names [922] [916] +0 1 +.names [921] [917] +0 1 +.names [919] [958] [918] +11 0 +.names [943] [919] +0 1 +.names [921] [922] [920] +11 0 +.names [291] [921] +0 1 +.names [257] [922] +0 1 +.names [295] [923] +0 1 +.names [290] [924] +0 1 +.names [960] [925] +1 1 +.names [923] [926] +1 1 +.names [929] [930] [927] +00 1 +.names [944] [943] [928] +00 1 +.names [940] [929] +0 1 +.names [942] [930] +0 1 +.names [257] [291] [931] +00 1 +.names [933] [934] [938] [932] +111 0 +.names [355] [794] [933] +11 0 +.names [935] [936] [934] +00 1 +.names [897] [815] [935] +00 1 +.names [423] [530] [937] [936] +11- 0 +--1 0 +.names [978] [937] +0 1 +.names [492] [976] [938] +11 0 +.names [940] [961] [955] [939] +111 0 +.names [945] [941] [940] +00 1 +.names [931] [941] +0 1 +.names [956] [966] [942] +00 1 +.names [965] [957] [943] +11 0 +.names [964] [958] [944] +11 0 +.names [946] [947] [945] +11 0 +.names [306] [946] +0 1 +.names [286] [947] +0 1 +.names [946] [948] +1 1 +.names [950] [951] [953] [949] +111 0 +.names [851] [840] [950] +11 0 +.names [912] [890] [952] [951] +00- 1 +--0 1 +.names [912] [890] [952] +11 0 +.names [326] [953] +0 1 +.names [951] [954] +1 1 +.names [980] [956] [955] +00 1 +.names [924] [923] [956] +11 0 +.names [292] [957] +0 1 +.names [294] [958] +0 1 +.names [287] [959] +0 1 +.names [288] [960] +0 1 +.names [962] [963] [961] +00 1 +.names [960] [959] [962] +11 0 +.names [964] [965] [963] +11 0 +.names [293] [964] +0 1 +.names [289] [965] +0 1 +.names [960] [959] [966] +11 0 +.names [968] [969] [970] \bcnt_reg[0]_in +00- 1 +--0 1 +.names [254] [979] [443] [968] +01- 1 +1-1 1 +.names [296] [512] [251] [969] +111 0 +.names [971] [972] [970] +00 0 +.names [512] [971] +0 1 +.names [973] [254] [765] [972] +11- 0 +--1 0 +.names [821] [815] [973] +11 0 +.names [896] [885] [974] +11 0 +.names [765] [975] +0 1 +.names [974] [976] +0 1 +.names [978] [977] +1 1 +.names [885] [914] [978] +00 1 +.names [254] [979] +0 1 +.names [981] [982] [980] +11 0 +.names [292] [981] +0 1 +.names [294] [982] +0 1 +.end diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/sqrt8ml.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/sqrt8ml.blif new file mode 100644 index 000000000..8ed9ca00c --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/sqrt8ml.blif @@ -0,0 +1,637 @@ +# +# Written by e2fmt Tue Mar 31 16:20:04 1998 +############################################ +.model top +.inputs v_6_ v_7_ v_4_ v_5_ v_2_ v_3_ v_0_ v_1_ +.outputs sqrt_3_ sqrt_2_ sqrt_1_ sqrt_0_ +# connect ports to nets with different names +.names v_6_ n_n74 +1 1 +.names n_n81 sqrt_3_ +1 1 +.names v_7_ n_n75 +1 1 +.names n_n79 sqrt_2_ +1 1 +.names v_4_ n_n83 +1 1 +.names n_n77 sqrt_1_ +1 1 +.names v_5_ n_n73 +1 1 +.names n_n72 sqrt_0_ +1 1 +.names v_2_ n_n80 +1 1 +.names v_3_ n_n82 +1 1 +.names v_0_ n_n76 +1 1 +.names v_1_ n_n78 +1 1 +# instance g_g159 +.names n_n146 n_n21 n_n149 n_n145 +1-0 1 +-11 1 +# instance g_g148 +.names n_n120 n_n93 n_n147 +10 1 +01 1 +# instance g_g137 +.names n_n20 n_n20 n_n21 n_n95 +1-0 1 +-11 1 +# instance g_g126 +.names n_n32 n_n6 n_tmp34 +10 1 +01 1 +# instance g_g115 +.names n_n78 n_n66 n_n15 +1- 1 +-1 1 +# instance g_g104 +.names n_n21 n_n21 n_n72 n_n77 +1-0 1 +-11 1 +# instance g_g158 +.names n_n29 n_n1 n_tmp74 +10 1 +01 1 +# instance g_g149 +.names n_n114 n_n21 n_n149 +10 1 +01 1 +# instance g_g136 +.names n_n124 n_tmp70 n_n20 n_n126 +1-0 1 +-11 1 +# instance g_g127 +.names n_n4 n_n5 n_tmp36 +10 1 +01 1 +# instance g_g114 +.names n_n92 n_n26 n_n99 +11 1 +# instance g_g105 +.names n_n140 n_n94 n_n142 n_n132 +1-0 1 +-11 1 +# instance g_g168 +.names n_n76 n_n76 n_n49 n_n86 +1-0 1 +-11 1 +# instance g_g135 +.names n_n117 n_tmp71 n_n20 n_n116 +1-0 1 +-11 1 +# instance g_g124 +.names n_n34 n_n8 n_tmp32 +10 1 +01 1 +# instance g_g117 +.names n_n73 n_n64 n_n13 +1- 1 +-1 1 +# instance g_g106 +.names n_n141 n_n20 n_n143 n_n140 +1-0 1 +-11 1 +# instance g_g169 +.names n_n78 n_tmp36 n_n49 n_n88 +1-0 1 +-11 1 +# instance g_g134 +.names n_n123 n_tmp69 n_n20 n_n122 +1-0 1 +-11 1 +# instance g_g125 +.names n_n33 n_n7 n_tmp35 +10 1 +01 1 +# instance g_g116 +.names n_n83 n_n65 n_n14 +1- 1 +-1 1 +# instance g_g107 +.names n_n116 n_n94 n_n142 +10 1 +01 1 +# instance g_g133 +.names n_n119 n_tmp72 n_n20 n_n121 +1-0 1 +-11 1 +# instance g_g122 +.names n_n109 n_n10 n_tmp30 +10 1 +01 1 +# instance g_g111 +.names n_n111 n_n59 n_n17 +1- 1 +-1 1 +# instance g_g100 +.names n_n37 n_n52 n_tmp108 +10 1 +01 1 +# instance g_g9 +.names n_n83 n_n9 +0 1 +# instance g_g132 +.names n_n111 n_tmp73 n_n20 n_n110 +1-0 1 +-11 1 +# instance g_g123 +.names n_n35 n_n9 n_tmp33 +10 1 +01 1 +# instance g_g110 +.names n_n113 n_n60 n_n18 +1- 1 +-1 1 +# instance g_g101 +.names n_n124 n_n49 n_n135 +10 1 +01 1 +# instance g_g131 +.names n_n113 n_tmp74 n_n20 n_n115 +1-0 1 +-11 1 +# instance g_g120 +.names n_n74 n_n31 n_n109 +11 1 +# instance g_g113 +.names n_n16 n_n100 n_n101 +11 1 +# instance g_g102 +.names n_n134 n_n49 n_n135 n_n133 +1-0 1 +-11 1 +# instance g_g130 +.names n_n88 n_tmp75 n_n20 n_n87 +1-0 1 +-11 1 +# instance g_g121 +.names n_n31 n_n74 n_tmp31 +10 1 +01 1 +# instance g_g112 +.names n_n119 n_n27 n_n100 +11 1 +# instance g_g103 +.names n_n95 n_n95 n_n72 n_n79 +1-0 1 +-11 1 +# instance g_g162 +.names n_n74 n_tmp31 n_n49 n_n124 +1-0 1 +-11 1 +# instance g_g151 +.names n_n129 n_n124 n_n156 +11 1 +# instance g_g140 +.names n_n87 n_tmp114 n_n21 n_n89 +1-0 1 +-11 1 +# instance g_g5 +.names n_n78 n_n5 +0 1 +# instance g_g163 +.names n_n75 n_tmp30 n_n49 n_n123 +1-0 1 +-11 1 +# instance g_g150 +.names n_n129 n_n124 n_n92 +10 1 +01 1 +# instance g_g141 +.names n_n122 n_tmp108 n_n21 n_n127 +1-0 1 +-11 1 +# instance g_g6 +.names n_n82 n_n6 +0 1 +# instance g_g160 +.names n_n28 n_n0 n_tmp73 +10 1 +01 1 +# instance g_g153 +.names n_n27 n_n119 n_tmp72 +10 1 +01 1 +# instance g_g142 +.names n_n126 n_tmp109 n_n21 n_n125 +1-0 1 +-11 1 +# instance g_g7 +.names n_n80 n_n7 +0 1 +# instance g_g161 +.names n_n145 n_n95 n_n148 n_n139 +1-0 1 +-11 1 +# instance g_g152 +.names n_n139 n_n93 n_n147 n_n138 +1-0 1 +-11 1 +# instance g_g143 +.names n_n115 n_tmp113 n_n21 n_n114 +1-0 1 +-11 1 +# instance g_g8 +.names n_n73 n_n8 +0 1 +# instance g_g166 +.names n_n80 n_tmp35 n_n49 n_n113 +1-0 1 +-11 1 +# instance g_g155 +.names n_n26 n_n92 n_tmp70 +10 1 +01 1 +# instance g_g144 +.names n_n116 n_tmp110 n_n21 n_n118 +1-0 1 +-11 1 +# instance g_g119 +.names n_n82 n_n62 n_n11 +1- 1 +-1 1 +# instance g_g108 +.names n_n121 n_n20 n_n143 +10 1 +01 1 +# instance g_g1 +.names n_n113 n_n1 +0 1 +# instance g_g167 +.names n_n82 n_tmp34 n_n49 n_n111 +1-0 1 +-11 1 +# instance g_g154 +.names n_n100 n_n16 n_tmp71 +10 1 +01 1 +# instance g_g145 +.names n_n110 n_tmp112 n_n21 n_n112 +1-0 1 +-11 1 +# instance g_g118 +.names n_n80 n_n63 n_n12 +1- 1 +-1 1 +# instance g_g109 +.names n_n88 n_n61 n_n19 +1- 1 +-1 1 +# instance g_g2 +.names n_n61 n_n2 +0 1 +# instance g_g164 +.names n_n83 n_tmp33 n_n49 n_n119 +1-0 1 +-11 1 +# instance g_g157 +.names n_n2 n_n3 n_tmp75 +10 1 +01 1 +# instance g_g146 +.names n_n121 n_tmp111 n_n21 n_n120 +1-0 1 +-11 1 +# instance g_g139 +.names n_n91 n_n91 n_n21 n_n90 +1-0 1 +-11 1 +# instance g_g128 +.names n_n49 n_n49 n_n20 n_n94 +1-0 1 +-11 1 +# instance g_g3 +.names n_n88 n_n3 +0 1 +# instance g_g165 +.names n_n73 n_tmp32 n_n49 n_n117 +1-0 1 +-11 1 +# instance g_g156 +.names n_n25 n_n51 n_tmp69 +10 1 +01 1 +# instance g_g147 +.names n_n112 n_n95 n_n148 +10 1 +01 1 +# instance g_g138 +.names n_n94 n_n94 n_n21 n_n93 +1-0 1 +-11 1 +# instance g_g129 +.names n_n86 n_n86 n_n20 n_n91 +1-0 1 +-11 1 +# instance g_g4 +.names n_n66 n_n4 +0 1 +# instance g_g94 +.names n_n22 n_n23 n_tmp114 +10 1 +01 1 +# instance g_g83 +.names n_n86 n_n30 n_n61 +11 1 +# instance g_g72 +.names n_n153 n_n102 n_n41 +1- 1 +-1 1 +# instance g_g61 +.names n_n52 n_n131 n_n130 +11 1 +# instance g_g50 +.names n_n126 n_n55 +0 1 +# instance g_g95 +.names n_n42 n_n85 n_tmp111 +10 1 +01 1 +# instance g_g82 +.names n_n108 n_n73 n_n31 +1- 1 +-1 1 +# instance g_g73 +.names n_n155 n_n87 n_n40 +1- 1 +-1 1 +# instance g_g60 +.names n_n53 n_n136 n_n144 +11 1 +# instance g_g51 +.names n_n125 n_n56 +0 1 +# instance g_g96 +.names n_n41 n_n84 n_tmp110 +10 1 +01 1 +# instance g_g81 +.names n_n105 n_n80 n_n32 +1- 1 +-1 1 +# instance g_g70 +.names n_n87 n_n68 n_n43 +1- 1 +-1 1 +# instance g_g63 +.names n_n117 n_n119 n_n50 +1- 1 +-1 1 +# instance g_g52 +.names n_n118 n_n57 +0 1 +# instance g_g97 +.names n_n40 n_n115 n_tmp113 +10 1 +01 1 +# instance g_g80 +.names n_n104 n_n78 n_n33 +1- 1 +-1 1 +# instance g_g71 +.names n_n152 n_n110 n_n42 +1- 1 +-1 1 +# instance g_g62 +.names n_n51 n_n133 n_n128 +11 1 +# instance g_g53 +.names n_n58 n_n146 +0 1 +# instance g_g0 +.names n_n111 n_n0 +0 1 +# instance g_g98 +.names n_n151 n_n44 n_tmp112 +10 1 +01 1 +# instance g_g43 +.names n_n48 n_n150 +0 1 +# instance g_g32 +.names n_n76 n_n36 +0 1 +# instance g_g21 +.names n_n130 n_n21 +0 1 +# instance g_g10 +.names n_n75 n_n10 +0 1 +# instance g_g99 +.names n_n38 n_n55 n_tmp109 +10 1 +01 1 +# instance g_g42 +.names n_n71 n_n47 +0 1 +# instance g_g33 +.names n_n38 n_n67 +0 1 +# instance g_g20 +.names n_n128 n_n20 +0 1 +# instance g_g11 +.names n_n11 n_n106 +0 1 +# instance g_g41 +.names n_n70 n_n46 +0 1 +# instance g_g30 +.names n_n34 n_n64 +0 1 +# instance g_g23 +.names n_n87 n_n23 +0 1 +# instance g_g12 +.names n_n12 n_n105 +0 1 +# instance g_g40 +.names n_n69 n_n45 +0 1 +# instance g_g31 +.names n_n35 n_n65 +0 1 +# instance g_g22 +.names n_n68 n_n22 +0 1 +# instance g_g13 +.names n_n13 n_n108 +0 1 +# instance g_g69 +.names n_n44 n_n151 n_n152 +11 1 +# instance g_g58 +.names n_n55 n_n132 n_n131 +11 1 +# instance g_g47 +.names n_n122 n_n52 +0 1 +# instance g_g36 +.names n_n41 n_n70 +0 1 +# instance g_g25 +.names n_n28 n_n59 +0 1 +# instance g_g14 +.names n_n14 n_n107 +0 1 +# instance g_g68 +.names n_n115 n_n45 n_n151 +11 1 +# instance g_g59 +.names n_n110 n_n115 n_n54 +1- 1 +-1 1 +# instance g_g46 +.names n_n123 n_n51 +0 1 +# instance g_g37 +.names n_n42 n_n71 +0 1 +# instance g_g24 +.names n_n94 n_n24 +0 1 +# instance g_g15 +.names n_n15 n_n104 +0 1 +# instance g_g89 +.names n_n93 n_n93 n_n72 n_n81 +1-0 1 +-11 1 +# instance g_g78 +.names n_n106 n_n82 n_n35 +1- 1 +-1 1 +# instance g_g45 +.names n_n50 n_n134 +0 1 +# instance g_g34 +.names n_n91 n_n39 +0 1 +# instance g_g27 +.names n_n86 n_n30 +0 1 +# instance g_g16 +.names n_n117 n_n16 +0 1 +# instance g_g88 +.names n_n99 n_n156 n_n25 +1- 1 +-1 1 +# instance g_g79 +.names n_n107 n_n83 n_n34 +1- 1 +-1 1 +# instance g_g44 +.names n_n49 n_n129 +0 1 +# instance g_g35 +.names n_n40 n_n69 +0 1 +# instance g_g26 +.names n_n29 n_n60 +0 1 +# instance g_g17 +.names n_n17 n_n97 +0 1 +# instance g_g90 +.names n_n24 n_n116 n_n84 +10 1 +01 1 +# instance g_g87 +.names n_n101 n_n117 n_n26 +1- 1 +-1 1 +# instance g_g76 +.names n_n150 n_n126 n_n37 +1- 1 +-1 1 +# instance g_g65 +.names n_n126 n_n67 n_n48 +1- 1 +-1 1 +# instance g_g54 +.names n_n144 n_n72 +0 1 +# instance g_g29 +.names n_n33 n_n63 +0 1 +# instance g_g18 +.names n_n18 n_n96 +0 1 +# instance g_g91 +.names n_n128 n_n121 n_n85 +10 1 +01 1 +# instance g_g86 +.names n_n97 n_n111 n_n27 +1- 1 +-1 1 +# instance g_g77 +.names n_n76 n_n36 n_n66 +11 1 +# instance g_g64 +.names n_n75 n_n74 n_n49 +1- 1 +-1 1 +# instance g_g55 +.names n_n89 n_n90 n_n58 +1- 1 +-1 1 +# instance g_g28 +.names n_n32 n_n62 +0 1 +# instance g_g19 +.names n_n19 n_n98 +0 1 +# instance g_g92 +.names n_n128 n_n121 n_n102 +11 1 +# instance g_g85 +.names n_n96 n_n113 n_n28 +1- 1 +-1 1 +# instance g_g74 +.names n_n91 n_n39 n_n68 +11 1 +# instance g_g67 +.names n_n84 n_n46 n_n154 +11 1 +# instance g_g56 +.names n_n57 n_n138 n_n137 +11 1 +# instance g_g49 +.names n_n54 n_n141 +0 1 +# instance g_g38 +.names n_n43 n_n155 +0 1 +# instance g_g93 +.names n_n24 n_n116 n_n103 +11 1 +# instance g_g84 +.names n_n98 n_n88 n_n29 +1- 1 +-1 1 +# instance g_g75 +.names n_n154 n_n103 n_n38 +1- 1 +-1 1 +# instance g_g66 +.names n_n85 n_n47 n_n153 +11 1 +# instance g_g57 +.names n_n56 n_n137 n_n136 +11 1 +# instance g_g48 +.names n_n127 n_n53 +0 1 +# instance g_g39 +.names n_n110 n_n44 +0 1 +.end diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/ss_pcm.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/ss_pcm.blif new file mode 100644 index 000000000..81899599d --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/ss_pcm.blif @@ -0,0 +1,1142 @@ +# Benchmark "ss_pcm" written by ABC on Mon Aug 29 15:33:12 2005 +.model ss_pcm +.inputs clk rst pcm_clk_i pcm_sync_i pcm_din_i re_i ssel[0] ssel[1] ssel[2] \ + din_i[0] din_i[1] din_i[2] din_i[3] din_i[4] din_i[5] din_i[6] din_i[7] \ + we_i[0] we_i[1] +.outputs pcm_dout_o dout_o[0] dout_o[1] dout_o[2] dout_o[3] dout_o[4] \ + dout_o[5] dout_o[6] dout_o[7] + +.latch \tx_hold_reg_reg[15]_in \tx_hold_reg_reg[15] 2 +.latch \tx_hold_reg_reg[1]_in \tx_hold_reg_reg[1] 2 +.latch \tx_hold_reg_reg[2]_in \tx_hold_reg_reg[2] 2 +.latch \tx_hold_reg_reg[3]_in \tx_hold_reg_reg[3] 2 +.latch \tx_hold_reg_reg[4]_in \tx_hold_reg_reg[4] 2 +.latch \tx_hold_reg_reg[5]_in \tx_hold_reg_reg[5] 2 +.latch \tx_hold_reg_reg[6]_in \tx_hold_reg_reg[6] 2 +.latch \tx_hold_reg_reg[7]_in \tx_hold_reg_reg[7] 2 +.latch \tx_hold_reg_reg[8]_in \tx_hold_reg_reg[8] 2 +.latch \tx_hold_reg_reg[9]_in \tx_hold_reg_reg[9] 2 +.latch \tx_hold_reg_reg[11]_in \tx_hold_reg_reg[11] 2 +.latch \tx_hold_reg_reg[12]_in \tx_hold_reg_reg[12] 2 +.latch \tx_hold_reg_reg[13]_in \tx_hold_reg_reg[13] 2 +.latch \tx_hold_reg_reg[14]_in \tx_hold_reg_reg[14] 2 +.latch \tx_hold_reg_reg[0]_in \tx_hold_reg_reg[0] 2 +.latch tx_go_reg_in tx_go_reg 2 +.latch \tx_hold_reg_reg[10]_in \tx_hold_reg_reg[10] 2 +.latch \rx_reg_reg[13]_in \rx_reg_reg[13] 2 +.latch \rx_reg_reg[14]_in \rx_reg_reg[14] 2 +.latch \rx_reg_reg[15]_in \rx_reg_reg[15] 2 +.latch \rx_reg_reg[1]_in \rx_reg_reg[1] 2 +.latch \rx_reg_reg[2]_in \rx_reg_reg[2] 2 +.latch \rx_reg_reg[3]_in \rx_reg_reg[3] 2 +.latch \rx_reg_reg[4]_in \rx_reg_reg[4] 2 +.latch \rx_reg_reg[5]_in \rx_reg_reg[5] 2 +.latch \rx_reg_reg[6]_in \rx_reg_reg[6] 2 +.latch \rx_reg_reg[7]_in \rx_reg_reg[7] 2 +.latch \rx_reg_reg[8]_in \rx_reg_reg[8] 2 +.latch \rx_reg_reg[9]_in \rx_reg_reg[9] 2 +.latch \rx_reg_reg[0]_in \rx_reg_reg[0] 2 +.latch \rx_reg_reg[12]_in \rx_reg_reg[12] 2 +.latch \rx_reg_reg[10]_in \rx_reg_reg[10] 2 +.latch \rx_reg_reg[11]_in \rx_reg_reg[11] 2 +.latch \tx_cnt_reg[3]_in \tx_cnt_reg[3] 2 +.latch \tx_cnt_reg[2]_in \tx_cnt_reg[2] 2 +.latch \tx_cnt_reg[0]_in \tx_cnt_reg[0] 2 +.latch \tx_cnt_reg[1]_in \tx_cnt_reg[1] 2 +.latch \rx_hold_reg_reg[8]_in \rx_hold_reg_reg[8] 2 +.latch \rx_hold_reg_reg[10]_in \rx_hold_reg_reg[10] 2 +.latch \rx_hold_reg_reg[0]_in \rx_hold_reg_reg[0] 2 +.latch \rx_hold_reg_reg[11]_in \rx_hold_reg_reg[11] 2 +.latch \rx_hold_reg_reg[12]_in \rx_hold_reg_reg[12] 2 +.latch \rx_hold_reg_reg[14]_in \rx_hold_reg_reg[14] 2 +.latch \rx_hold_reg_reg[15]_in \rx_hold_reg_reg[15] 2 +.latch \rx_hold_reg_reg[1]_in \rx_hold_reg_reg[1] 2 +.latch \rx_hold_reg_reg[4]_in \rx_hold_reg_reg[4] 2 +.latch \rx_hold_reg_reg[5]_in \rx_hold_reg_reg[5] 2 +.latch \rx_hold_reg_reg[6]_in \rx_hold_reg_reg[6] 2 +.latch \rx_hold_reg_reg[9]_in \rx_hold_reg_reg[9] 2 +.latch \rx_hold_reg_reg[2]_in \rx_hold_reg_reg[2] 2 +.latch \rx_hold_reg_reg[7]_in \rx_hold_reg_reg[7] 2 +.latch \rx_hold_reg_reg[13]_in \rx_hold_reg_reg[13] 2 +.latch \rx_hold_reg_reg[3]_in \rx_hold_reg_reg[3] 2 +.latch tx_go_r1_reg_in tx_go_r1_reg 2 +.latch \psa_reg[2]_in \psa_reg[2] 2 +.latch \psa_reg[5]_in \psa_reg[5] 2 +.latch \psa_reg[1]_in \psa_reg[1] 2 +.latch \psa_reg[7]_in \psa_reg[7] 2 +.latch \psa_reg[6]_in \psa_reg[6] 2 +.latch \psa_reg[0]_in \psa_reg[0] 2 +.latch \psa_reg[3]_in \psa_reg[3] 2 +.latch \psa_reg[4]_in \psa_reg[4] 2 +.latch psync_reg_in psync_reg 2 +.latch pcm_sync_r1_reg_in pcm_sync_r1_reg 2 +.latch rxd_t_reg_in rxd_t_reg 2 +.latch pcm_sync_r3_reg_in pcm_sync_r3_reg 2 +.latch pcm_sync_r2_reg_in pcm_sync_r2_reg 2 +.latch pclk_r_reg_in pclk_r_reg 2 +.latch \tx_hold_byte_l_reg[5]_in \tx_hold_byte_l_reg[5] 2 +.latch \tx_hold_byte_h_reg[7]_in \tx_hold_byte_h_reg[7] 2 +.latch \tx_hold_byte_h_reg[4]_in \tx_hold_byte_h_reg[4] 2 +.latch \tx_hold_byte_h_reg[6]_in \tx_hold_byte_h_reg[6] 2 +.latch \tx_hold_byte_h_reg[1]_in \tx_hold_byte_h_reg[1] 2 +.latch \tx_hold_byte_h_reg[2]_in \tx_hold_byte_h_reg[2] 2 +.latch \tx_hold_byte_h_reg[3]_in \tx_hold_byte_h_reg[3] 2 +.latch \tx_hold_byte_h_reg[5]_in \tx_hold_byte_h_reg[5] 2 +.latch \tx_hold_byte_l_reg[1]_in \tx_hold_byte_l_reg[1] 2 +.latch \tx_hold_byte_l_reg[2]_in \tx_hold_byte_l_reg[2] 2 +.latch \tx_hold_byte_l_reg[4]_in \tx_hold_byte_l_reg[4] 2 +.latch \tx_hold_byte_l_reg[7]_in \tx_hold_byte_l_reg[7] 2 +.latch \tx_hold_byte_h_reg[0]_in \tx_hold_byte_h_reg[0] 2 +.latch \tx_hold_byte_l_reg[6]_in \tx_hold_byte_l_reg[6] 2 +.latch \tx_hold_byte_l_reg[3]_in \tx_hold_byte_l_reg[3] 2 +.latch \tx_hold_byte_l_reg[0]_in \tx_hold_byte_l_reg[0] 2 +.latch pclk_s_reg_in pclk_s_reg 2 +.latch rxd_reg_in rxd_reg 2 +.latch pclk_t_reg_in pclk_t_reg 2 + +.names [115] + 0 +.names [116] + 1 +.names \tx_hold_reg_reg[15] pcm_dout_o +1 1 +.names \tx_hold_reg_reg[1] [118] +0 1 +.names \tx_hold_reg_reg[2] [119] +0 1 +.names \tx_hold_reg_reg[3] [120] +0 1 +.names \tx_hold_reg_reg[4] [121] +0 1 +.names \tx_hold_reg_reg[5] [122] +0 1 +.names \tx_hold_reg_reg[6] [123] +0 1 +.names \tx_hold_reg_reg[7] [124] +0 1 +.names \tx_hold_reg_reg[8] [125] +0 1 +.names \tx_hold_reg_reg[9] [126] +0 1 +.names \tx_hold_reg_reg[11] [127] +0 1 +.names \tx_hold_reg_reg[12] [128] +0 1 +.names \tx_hold_reg_reg[13] [129] +0 1 +.names \tx_hold_reg_reg[14] [130] +0 1 +.names \tx_hold_reg_reg[0] [131] +1 1 +.names tx_go_reg [132] +1 1 +.names \tx_hold_reg_reg[10] [133] +1 1 +.names [221] [207] [480] \tx_hold_reg_reg[1]_in +11- 0 +--1 0 +.names [236] [190] [481] \tx_hold_reg_reg[14]_in +11- 0 +--1 0 +.names [237] [191] [481] \tx_hold_reg_reg[15]_in +11- 0 +--1 0 +.names [168] [169] \tx_hold_reg_reg[0]_in +11 0 +.names [224] [210] [481] \tx_hold_reg_reg[4]_in +11- 0 +--1 0 +.names [225] [212] [480] \tx_hold_reg_reg[5]_in +11- 0 +--1 0 +.names [226] [213] [476] \tx_hold_reg_reg[6]_in +11- 0 +--1 0 +.names [227] [215] [478] \tx_hold_reg_reg[7]_in +11- 0 +--1 0 +.names \rx_reg_reg[13] [142] +0 1 +.names \rx_reg_reg[14] [143] +0 1 +.names \rx_reg_reg[15] [144] +0 1 +.names \rx_reg_reg[1] [145] +0 1 +.names \rx_reg_reg[2] [146] +0 1 +.names \rx_reg_reg[3] [147] +0 1 +.names \rx_reg_reg[4] [148] +0 1 +.names \rx_reg_reg[5] [149] +0 1 +.names \rx_reg_reg[6] [150] +0 1 +.names \rx_reg_reg[7] [151] +0 1 +.names \rx_reg_reg[8] [152] +0 1 +.names \rx_reg_reg[9] [153] +0 1 +.names \rx_reg_reg[0] [154] +0 1 +.names \rx_reg_reg[12] [155] +0 1 +.names \rx_reg_reg[10] [156] +0 1 +.names [228] [216] [480] \tx_hold_reg_reg[8]_in +11- 0 +--1 0 +.names \rx_reg_reg[11] [158] +0 1 +.names [229] [217] [574] \tx_hold_reg_reg[9]_in +11- 0 +--1 0 +.names [222] [208] [481] \tx_hold_reg_reg[2]_in +11- 0 +--1 0 +.names [223] [209] [480] \tx_hold_reg_reg[3]_in +11- 0 +--1 0 +.names [233] [218] [478] \tx_hold_reg_reg[11]_in +11- 0 +--1 0 +.names [234] [219] [476] \tx_hold_reg_reg[12]_in +11- 0 +--1 0 +.names [235] [189] [478] \tx_hold_reg_reg[13]_in +11- 0 +--1 0 +.names [414] [193] tx_go_reg_in +00 0 +.names \tx_cnt_reg[3] [166] +1 1 +.names [232] [238] [478] \tx_hold_reg_reg[10]_in +11- 0 +--1 0 +.names [230] [441] [168] +11 0 +.names [131] rst [303] [576] [169] +1111 0 +.names \tx_cnt_reg[2] [170] +1 1 +.names \tx_cnt_reg[0] [171] +1 1 +.names \tx_cnt_reg[1] [172] +1 1 +.names [273] [257] [477] \rx_reg_reg[14]_in +11- 0 +--1 0 +.names [277] [261] [475] \rx_reg_reg[3]_in +11- 0 +--1 0 +.names [272] [256] [475] \rx_reg_reg[13]_in +11- 0 +--1 0 +.names [274] [258] [574] \rx_reg_reg[15]_in +11- 0 +--1 0 +.names [275] [259] [574] \rx_reg_reg[1]_in +11- 0 +--1 0 +.names [276] [260] [474] \rx_reg_reg[2]_in +11- 0 +--1 0 +.names [279] [263] [474] \rx_reg_reg[5]_in +11- 0 +--1 0 +.names [280] [264] [477] \rx_reg_reg[6]_in +11- 0 +--1 0 +.names [281] [265] [474] \rx_reg_reg[7]_in +11- 0 +--1 0 +.names [282] [266] [474] \rx_reg_reg[8]_in +11- 0 +--1 0 +.names [283] [267] [476] \rx_reg_reg[9]_in +11- 0 +--1 0 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we_i[1] din_i[0] [494] +11 0 +.names we_i[1] din_i[6] [495] +11 0 +.names [586] [496] +0 1 +.names din_i[4] we_i[0] [497] +11 0 +.names pclk_t_reg pclk_s_reg_in +1 1 +.names [431] [499] +0 1 +.names [437] [500] +0 1 +.names [435] [501] +0 1 +.names [156] [502] +0 1 +.names [123] [503] +0 1 +.names [142] [504] +0 1 +.names [124] [505] +0 1 +.names [130] [506] +0 1 +.names [125] [507] +0 1 +.names [153] [508] +0 1 +.names [429] [509] +0 1 +.names [433] [510] +0 1 +.names [421] [511] +0 1 +.names [292] [512] +0 1 +.names [121] [513] +0 1 +.names [144] [514] +0 1 +.names [128] [515] +0 1 +.names [143] [516] +0 1 +.names [155] [517] +0 1 +.names [427] [518] +0 1 +.names [122] [519] +0 1 +.names [149] [520] +0 1 +.names [201] [521] +0 1 +.names [214] [522] +0 1 +.names [127] [523] +0 1 +.names [339] [524] +0 1 +.names [150] [525] +0 1 +.names [146] [526] +0 1 +.names [432] [527] +0 1 +.names [428] [528] +0 1 +.names [434] [529] +0 1 +.names [133] [530] +0 1 +.names [145] [531] +0 1 +.names [148] [532] +0 1 +.names [151] [533] +0 1 +.names [436] [534] +0 1 +.names [202] [535] +0 1 +.names [196] [536] +0 1 +.names [152] [537] +0 1 +.names [147] [538] +0 1 +.names [430] [539] +0 1 +.names [154] [540] +0 1 +.names [119] [541] +0 1 +.names [171] [542] +0 1 +.names [194] [543] +0 1 +.names rst [544] +0 1 +.names [129] [545] +0 1 +.names [204] [546] +0 1 +.names [203] [547] +0 1 +.names [118] [548] +0 1 +.names [120] [549] +0 1 +.names [211] [550] +0 1 +.names [205] [551] +0 1 +.names [200] [552] +0 1 +.names [426] [553] +0 1 +.names [158] [554] +0 1 +.names [198] [555] +0 1 +.names [341] rxd_reg_in +0 1 +.names [425] [557] +0 1 +.names [199] [558] +0 1 +.names [192] [559] +0 1 +.names [195] [560] +0 1 +.names [172] [561] +0 1 +.names [424] [562] +0 1 +.names [206] [563] +0 1 +.names [197] [564] +0 1 +.names [126] [565] +0 1 +.names [567] [566] +0 1 +.names [568] [567] +1 1 +.names [569] [568] +0 1 +.names [585] [443] [569] +11 0 +.names [572] [570] +0 1 +.names [572] [571] +0 1 +.names [581] [572] +0 1 +.names [574] [575] \tx_cnt_reg[3]_in +00 1 +.names rst [574] +0 1 +.names [166] [576] [579] [575] +11- 0 +--1 0 +.names [577] [576] +0 1 +.names [578] [577] +0 1 +.names [496] [568] [578] +11 0 +.names [417] [576] [579] +00 1 +.names [568] [496] [580] +11 0 +.names [586] [584] [581] +00 1 +.names [583] [586] [292] [582] +111 0 +.names [584] [583] +0 1 +.names [585] [443] [584] +11 0 +.names [416] [585] +0 1 +.names [132] [586] +0 1 +.names pcm_clk_i pclk_t_reg_in +1 1 +.end diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/steppermotordrive.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/steppermotordrive.blif new file mode 100644 index 000000000..655eb5c3d --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/steppermotordrive.blif @@ -0,0 +1,515 @@ +# Benchmark "steppermotordrive" written by ABC on Mon Aug 29 15:33:12 2005 +.model steppermotordrive +.inputs clock Direction StepEnable ProvideStaticHolding +.outputs StepDrive[0] StepDrive[1] StepDrive[2] StepDrive[3] + +.latch \StepCounter_reg[16]_in \StepCounter_reg[16] 2 +.latch \StepCounter_reg[15]_in \StepCounter_reg[15] 2 +.latch \StepCounter_reg[11]_in \StepCounter_reg[11] 2 +.latch \StepDrive_reg[0]_in \StepDrive_reg[0] 2 +.latch \StepDrive_reg[1]_in \StepDrive_reg[1] 2 +.latch \StepCounter_reg[17]_in \StepCounter_reg[17] 2 +.latch \StepCounter_reg[12]_in \StepCounter_reg[12] 2 +.latch \StepCounter_reg[14]_in \StepCounter_reg[14] 2 +.latch \state_reg[1]_in \state_reg[1] 2 +.latch \StepDrive_reg[2]_in \StepDrive_reg[2] 2 +.latch \StepCounter_reg[8]_in \StepCounter_reg[8] 2 +.latch \StepCounter_reg[10]_in \StepCounter_reg[10] 2 +.latch \StepDrive_reg[3]_in \StepDrive_reg[3] 2 +.latch InternalStepEnable_reg_in InternalStepEnable_reg 2 +.latch \StepCounter_reg[13]_in \StepCounter_reg[13] 2 +.latch \StepCounter_reg[7]_in \StepCounter_reg[7] 2 +.latch \StepCounter_reg[3]_in \StepCounter_reg[3] 2 +.latch \StepCounter_reg[6]_in \StepCounter_reg[6] 2 +.latch \state_reg[0]_in \state_reg[0] 2 +.latch \StepCounter_reg[2]_in \StepCounter_reg[2] 2 +.latch \StepCounter_reg[9]_in \StepCounter_reg[9] 2 +.latch \StepCounter_reg[0]_in \StepCounter_reg[0] 2 +.latch \StepCounter_reg[4]_in \StepCounter_reg[4] 2 +.latch \StepCounter_reg[5]_in \StepCounter_reg[5] 2 +.latch \StepCounter_reg[1]_in \StepCounter_reg[1] 2 + +.names [33] + 0 +.names [34] + 1 +.names \StepCounter_reg[16] [35] +1 1 +.names \StepCounter_reg[15] [36] +1 1 +.names \StepCounter_reg[11] [37] +1 1 +.names \StepDrive_reg[0] StepDrive[0] +1 1 +.names \StepDrive_reg[1] StepDrive[1] +1 1 +.names [42] \StepCounter_reg[16]_in +0 1 +.names \StepCounter_reg[17] [41] +1 1 +.names [54] [100] [42] +11 0 +.names [65] [95] \StepDrive_reg[0]_in +11 0 +.names [63] [95] \StepDrive_reg[1]_in +11 0 +.names \StepCounter_reg[12] [45] +1 1 +.names \StepCounter_reg[14] [46] +1 1 +.names \state_reg[1] [47] +1 1 +.names \StepDrive_reg[2] StepDrive[2] +1 1 +.names \StepCounter_reg[8] [49] +1 1 +.names \StepCounter_reg[10] [50] +1 1 +.names \StepDrive_reg[3] StepDrive[3] +1 1 +.names InternalStepEnable_reg [52] +1 1 +.names \StepCounter_reg[13] [53] +1 1 +.names [143] [35] [241] [54] +01- 1 +1-1 1 +.names \StepCounter_reg[7] [55] +1 1 +.names \StepCounter_reg[3] [56] +1 1 +.names \StepCounter_reg[6] [57] +1 1 +.names \state_reg[0] [58] +1 1 +.names \StepCounter_reg[2] [59] +1 1 +.names \StepCounter_reg[9] [60] +1 1 +.names \StepCounter_reg[0] [61] +1 1 +.names [78] [95] \StepDrive_reg[2]_in +11 0 +.names [100] StepDrive[1] [75] [63] +11- 0 +--1 0 +.names [109] [146] [76] \state_reg[1]_in +00- 1 +--0 1 +.names [100] StepDrive[0] [87] [65] +11- 0 +--1 0 +.names [84] [100] \StepCounter_reg[14]_in +11 1 +.names [169] [100] \StepCounter_reg[13]_in +11 1 +.names [77] InternalStepEnable_reg_in +0 1 +.names [93] [98] \StepCounter_reg[10]_in +00 1 +.names \StepCounter_reg[4] [70] +1 1 +.names \StepCounter_reg[5] [71] +1 1 +.names \StepCounter_reg[1] [72] +1 1 +.names [89] [95] \StepDrive_reg[3]_in +11 0 +.names [92] [100] \StepCounter_reg[8]_in +11 1 +.names [119] [146] [75] +00 1 +.names [146] [47] [76] +11 0 +.names [100] [133] StepEnable [77] +11- 0 +--1 0 +.names [131] [178] [179] StepDrive[2] [78] +11-- 0 +--11 0 +.names [125] [58] [259] \state_reg[0]_in +01- 1 +1-1 1 +.names [107] [97] \StepCounter_reg[3]_in +00 1 +.names [97] [230] \StepCounter_reg[0]_in +00 1 +.names [108] [98] \StepCounter_reg[2]_in +00 1 +.names [101] [97] \StepCounter_reg[9]_in +00 1 +.names [132] [103] [84] +01 1 +10 1 +.names [96] [97] \StepCounter_reg[7]_in +00 1 +.names [106] [97] \StepCounter_reg[6]_in +00 1 +.names [118] [146] [87] +00 1 +.names [105] [178] \StepCounter_reg[4]_in +00 1 +.names [126] [223] [179] StepDrive[3] [89] +11-- 0 +--11 0 +.names [114] [100] \StepCounter_reg[1]_in +11 1 +.names [104] [178] \StepCounter_reg[5]_in +00 1 +.names [151] [117] [102] [92] +00- 1 +--0 1 +.names [204] [236] [99] [93] +11- 0 +--1 0 +.names [161] [94] +0 1 +.names [136] [223] [95] +11 0 +.names [148] [234] [96] +01 1 +10 1 +.names [100] [97] +0 1 +.names [259] [98] +0 1 +.names [204] [236] [99] +00 1 +.names [223] [100] +0 1 +.names [60] [157] [101] +01 1 +10 1 +.names [151] [117] [102] +11 0 +.names [111] [204] [103] +00 1 +.names [71] [229] [104] +01 1 +10 1 +.names [70] [153] [105] +01 1 +10 1 +.names [135] [210] [106] +01 1 +10 1 +.names [122] [233] [107] +01 1 +10 1 +.names [113] [128] [110] [108] +11- 0 +--1 0 +.names [124] Direction [112] [109] +11- 0 +--1 0 +.names [113] [128] [110] +00 1 +.names [244] [186] [111] +11 0 +.names [119] Direction [112] +00 1 +.names [196] [113] +0 1 +.names [130] [230] [114] +01 1 +10 1 +.names [71] [55] [115] +11 0 +.names [217] [116] +0 1 +.names [194] [117] +0 1 +.names [124] [118] +0 1 +.names [58] [47] [134] [119] +11- 0 +--1 0 +.names [140] [215] [120] +00 1 +.names [138] [170] [121] +00 1 +.names [202] [122] +0 1 +.names [140] [123] +0 1 +.names [47] [58] [124] +01 1 +10 1 +.names [52] [58] [125] +01 1 +10 1 +.names [47] [142] [126] +00 1 +.names [139] [140] [127] +11 0 +.names [253] [128] +0 1 +.names [215] [129] +0 1 +.names [190] [130] +0 1 +.names [47] [52] [131] +11 1 +.names [138] [132] +0 1 +.names [142] [133] +0 1 +.names [58] [47] [134] +00 1 +.names [228] [135] +0 1 +.names ProvideStaticHolding [52] [136] +00 1 +.names [37] [137] +0 1 +.names [46] [138] +0 1 +.names [53] [139] +0 1 +.names [45] [140] +0 1 +.names [55] [141] +0 1 +.names [52] [142] +0 1 +.names [35] [143] +0 1 +.names [60] [144] +0 1 +.names [60] [236] [145] +11 0 +.names [147] [52] [146] +11 0 +.names [180] [147] +0 1 +.names [227] [148] +0 1 +.names [248] [197] [150] [149] +111 0 +.names [228] [202] [150] +00 1 +.names [152] [153] [151] +00 0 +.names [191] [232] [152] +00 0 +.names [201] [154] [153] +11 0 +.names [192] [154] +0 1 +.names [115] [155] +0 1 +.names [140] [144] [156] +00 0 +.names [158] [157] +0 1 +.names [229] [182] [158] +00 1 +.names [145] [160] [159] +00 1 +.names [227] [194] [160] +00 0 +.names [168] [161] +0 1 +.names [137] [162] +0 1 +.names [36] [163] +0 1 +.names [165] \StepCounter_reg[11]_in +0 1 +.names [166] [259] [165] +11 0 +.names [94] [129] [167] [166] +00- 1 +--0 1 +.names [168] [37] [167] +11 0 +.names [235] [159] [168] +11 0 +.names [170] [171] [169] +01 1 +10 1 +.names [53] [170] +0 1 +.names [172] [181] [189] [171] +111 0 +.names [229] [172] +0 1 +.names [174] [177] [178] \StepCounter_reg[15]_in +11- 0 +--1 0 +.names [175] [36] [174] +11 0 +.names [161] [176] [175] +11 0 +.names [120] [121] [176] +11 1 +.names [121] [120] [161] [163] [177] +1111 0 +.names [179] [178] +0 1 +.names [180] [179] +1 1 +.names [225] [224] [180] +11 0 +.names [182] [181] +0 1 +.names [193] [155] [182] +11 0 +.names [184] [185] [183] +00 1 +.names [231] [35] [184] +11 0 +.names [186] [187] [188] [185] +111 0 +.names [116] [186] +0 1 +.names [156] [187] +0 1 +.names [121] [36] [188] +11 1 +.names [156] [116] [189] +00 1 +.names [252] [190] +1 1 +.names [70] [71] [191] +11 0 +.names [59] [56] [192] +11 0 +.names [194] [228] [193] +00 1 +.names [49] [194] +0 1 +.names [46] [36] [195] +00 0 +.names [252] [250] [196] +00 1 +.names [237] [203] [197] +00 1 +.names [191] [192] [198] +00 1 +.names [228] [141] [199] +00 1 +.names [194] [250] [200] +00 0 +.names [250] [190] [201] +00 1 +.names [56] [202] +0 1 +.names [70] [203] +0 1 +.names [205] [207] [148] [193] [204] +1111 0 +.names [202] [206] [205] +00 1 +.names [59] [71] [70] [206] +111 0 +.names [208] [250] [207] +00 1 +.names [209] [60] [208] +11 0 +.names [252] [209] +0 1 +.names [211] [61] [213] [210] +111 0 +.names [212] [202] [211] +00 1 +.names [209] [212] +0 1 +.names [206] [213] +0 1 +.names [200] [214] +0 1 +.names [37] [215] +0 1 +.names [226] [217] [49] [216] +111 0 +.names [37] [50] [217] +11 1 +.names [127] [195] [218] +00 1 +.names [220] \StepCounter_reg[12]_in +0 1 +.names [221] [222] [100] [220] +111 0 +.names [123] [246] [221] +00 0 +.names [246] [123] [222] +11 0 +.names [260] [223] +0 1 +.names [216] [218] [239] [224] +111 0 +.names [41] [35] [225] +11 1 +.names [228] [227] [226] +11 0 +.names [55] [227] +0 1 +.names [57] [228] +0 1 +.names [250] [251] [229] +00 0 +.names [250] [230] +0 1 +.names [251] [231] +0 1 +.names [199] [232] +0 1 +.names [248] [233] +0 1 +.names [235] [234] +0 1 +.names [149] [235] +0 1 +.names [50] [236] +1 1 +.names [71] [237] +0 1 +.names [239] [238] +0 1 +.names [162] [236] [60] [239] +111 0 +.names [190] [232] [240] +00 1 +.names [242] [240] [238] [214] [241] +1111 0 +.names [243] [242] +0 1 +.names [198] [244] [245] [243] +111 0 +.names [170] [140] [244] +00 1 +.names [138] [163] [245] +00 1 +.names [247] [246] +0 1 +.names [240] [238] [214] [198] [247] +1111 0 +.names [249] [248] +0 1 +.names [61] [72] [59] [249] +111 0 +.names [61] [250] +0 1 +.names [209] [59] [56] [70] [251] +1111 0 +.names [72] [252] +0 1 +.names [59] [253] +0 1 +.names [255] [257] [98] \StepCounter_reg[17]_in +11- 0 +--1 0 +.names [256] [41] [255] +11 0 +.names [183] [181] [230] [256] +111 0 +.names [183] [181] [230] [258] [257] +1111 0 +.names [41] [258] +0 1 +.names [260] [259] +1 1 +.names [224] [225] [260] +11 0 +.end diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/stereovision3.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/stereovision3.blif new file mode 100644 index 000000000..604b91293 --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/stereovision3.blif @@ -0,0 +1,881 @@ +# Benchmark "sv_chip3_hierarchy_no_mem" written by ABC on Tue Apr 9 16:48:04 2013 +.model sv_chip3_hierarchy_no_mem +.inputs top^tm3_clk_v0 top^tm3_clk_v2 top^tm3_vidin_llc top^tm3_vidin_vs \ + top^tm3_vidin_href top^tm3_vidin_cref top^tm3_vidin_rts0 \ + top^tm3_vidin_vpo~0 top^tm3_vidin_vpo~1 top^tm3_vidin_vpo~2 \ + top^tm3_vidin_vpo~3 top^tm3_vidin_vpo~4 top^tm3_vidin_vpo~5 \ + top^tm3_vidin_vpo~6 top^tm3_vidin_vpo~7 top^tm3_vidin_vpo~8 \ + top^tm3_vidin_vpo~9 top^tm3_vidin_vpo~10 top^tm3_vidin_vpo~11 \ + top^tm3_vidin_vpo~12 top^tm3_vidin_vpo~13 top^tm3_vidin_vpo~14 \ + top^tm3_vidin_vpo~15 +.outputs top^tm3_vidin_sda top^tm3_vidin_scl top^vidin_new_data \ + top^vidin_rgb_reg~0 top^vidin_rgb_reg~1 top^vidin_rgb_reg~2 \ + top^vidin_rgb_reg~3 top^vidin_rgb_reg~4 top^vidin_rgb_reg~5 \ + top^vidin_rgb_reg~6 top^vidin_rgb_reg~7 top^vidin_addr_reg~0 \ + top^vidin_addr_reg~1 top^vidin_addr_reg~2 top^vidin_addr_reg~3 \ + top^vidin_addr_reg~4 top^vidin_addr_reg~5 top^vidin_addr_reg~6 \ + top^vidin_addr_reg~7 top^vidin_addr_reg~8 top^vidin_addr_reg~9 \ + top^vidin_addr_reg~10 top^vidin_addr_reg~11 top^vidin_addr_reg~12 \ + top^vidin_addr_reg~13 top^vidin_addr_reg~14 top^vidin_addr_reg~15 \ + top^vidin_addr_reg~16 top^vidin_addr_reg~17 top^vidin_addr_reg~18 + +.latch n107 top^FF_NODE~20 re top^tm3_clk_v0 0 +.latch n112 top^FF_NODE~30 re top^tm3_clk_v0 0 +.latch n117 top^FF_NODE~41 re top^tm3_clk_v0 0 +.latch n122 top^FF_NODE~135 re top^tm3_clk_v0 0 +.latch n127 top^FF_NODE~31 re top^tm3_clk_v0 0 +.latch n132 top^FF_NODE~42 re top^tm3_clk_v0 0 +.latch n137 top^FF_NODE~119 re top^tm3_clk_v0 0 +.latch n142 top^FF_NODE~32 re top^tm3_clk_v0 0 +.latch n147 top^FF_NODE~43 re top^tm3_clk_v0 0 +.latch n152 top^FF_NODE~120 re top^tm3_clk_v0 0 +.latch n157 top^FF_NODE~33 re top^tm3_clk_v0 0 +.latch n162 top^FF_NODE~44 re top^tm3_clk_v0 0 +.latch n167 top^FF_NODE~121 re top^tm3_clk_v0 0 +.latch n172 top^FF_NODE~34 re top^tm3_clk_v0 0 +.latch n177 top^FF_NODE~45 re top^tm3_clk_v0 0 +.latch n182 top^FF_NODE~122 re top^tm3_clk_v0 0 +.latch n187 top^FF_NODE~35 re top^tm3_clk_v0 0 +.latch n192 top^FF_NODE~46 re top^tm3_clk_v0 0 +.latch n197 top^FF_NODE~123 re top^tm3_clk_v0 0 +.latch n202 top^FF_NODE~36 re top^tm3_clk_v0 0 +.latch n207 top^FF_NODE~47 re top^tm3_clk_v0 0 +.latch n212 top^FF_NODE~124 re top^tm3_clk_v0 0 +.latch n217 top^FF_NODE~37 re top^tm3_clk_v0 0 +.latch n222 top^FF_NODE~48 re top^tm3_clk_v0 0 +.latch n227 top^FF_NODE~125 re top^tm3_clk_v0 0 +.latch n232 top^FF_NODE~38 re top^tm3_clk_v0 0 +.latch n237 top^FF_NODE~117 re top^tm3_clk_v0 0 +.latch n242 top^FF_NODE~118 re top^tm3_clk_v0 0 +.latch n247 top^FF_NODE~126 re top^tm3_clk_v0 0 +.latch n252 top^FF_NODE~127 re top^tm3_clk_v0 0 +.latch n257 top^FF_NODE~128 re top^tm3_clk_v0 0 +.latch n262 top^FF_NODE~129 re top^tm3_clk_v0 0 +.latch n267 top^FF_NODE~130 re top^tm3_clk_v0 0 +.latch n272 top^FF_NODE~131 re top^tm3_clk_v0 0 +.latch n277 top^FF_NODE~132 re top^tm3_clk_v0 0 +.latch n282 top^FF_NODE~133 re top^tm3_clk_v0 0 +.latch n287 top^FF_NODE~134 re top^tm3_clk_v0 0 +.latch n292 top^FF_NODE~136 re top^tm3_clk_v0 0 +.latch n297 top^FF_NODE~137 re top^tm3_clk_v0 0 +.latch n302 top^FF_NODE~138 re top^tm3_clk_v0 0 +.latch n307 top^FF_NODE~139 re top^tm3_clk_v0 0 +.latch n312 top^FF_NODE~140 re top^tm3_clk_v0 0 +.latch n317 top^FF_NODE~141 re top^tm3_clk_v0 0 +.latch n322 top^FF_NODE~142 re top^tm3_clk_v0 0 +.latch n327 top^FF_NODE~143 re top^tm3_clk_v0 0 +.latch n332 top^FF_NODE~144 re top^tm3_clk_v0 0 +.latch n337 top^FF_NODE~21 re top^tm3_clk_v0 0 +.latch n342 top^FF_NODE~39 re top^tm3_clk_v0 0 +.latch n347 top^FF_NODE~22 re top^tm3_clk_v0 0 +.latch n352 top^FF_NODE~49 re top^tm3_clk_v0 0 +.latch n357 top^FF_NODE~23 re top^tm3_clk_v0 0 +.latch n362 top^FF_NODE~50 re top^tm3_clk_v0 0 +.latch n367 top^FF_NODE~24 re top^tm3_clk_v0 0 +.latch n372 top^FF_NODE~51 re top^tm3_clk_v0 0 +.latch n377 top^FF_NODE~25 re top^tm3_clk_v0 0 +.latch n382 top^FF_NODE~52 re top^tm3_clk_v0 0 +.latch n387 top^FF_NODE~26 re top^tm3_clk_v0 0 +.latch n392 top^FF_NODE~53 re top^tm3_clk_v0 0 +.latch n397 top^FF_NODE~27 re top^tm3_clk_v0 0 +.latch n402 top^FF_NODE~54 re top^tm3_clk_v0 0 +.latch n407 top^FF_NODE~28 re top^tm3_clk_v0 0 +.latch n412 top^FF_NODE~55 re top^tm3_clk_v0 0 +.latch n417 top^FF_NODE~29 re top^tm3_clk_v0 0 +.latch n422 top^FF_NODE~56 re top^tm3_clk_v0 0 +.latch n427 top^FF_NODE~228 re top^tm3_clk_v2 0 +.latch n432 top^FF_NODE~381 re top^tm3_clk_v2 0 +.latch n437 top^FF_NODE~386 re top^tm3_clk_v2 0 +.latch n442 top^FF_NODE~229 re top^tm3_clk_v2 0 +.latch n447 top^FF_NODE~230 re top^tm3_clk_v2 0 +.latch n452 top^FF_NODE~387 re top^tm3_clk_v2 0 +.latch n457 top^FF_NODE~388 re top^tm3_clk_v2 0 +.latch n462 top^FF_NODE~389 re top^tm3_clk_v2 0 +.latch n467 top^FF_NODE~390 re top^tm3_clk_v2 0 +.latch n472 top^FF_NODE~391 re top^tm3_clk_v2 0 +.latch n477 top^FF_NODE~392 re top^tm3_clk_v2 0 +.latch n482 top^FF_NODE~382 re top^tm3_clk_v2 0 +.latch n487 top^FF_NODE~383 re top^tm3_clk_v2 0 +.latch n492 top^FF_NODE~384 re top^tm3_clk_v2 0 +.latch n497 top^FF_NODE~385 re top^tm3_clk_v2 0 +.latch n502 top^FF_NODE~378 re top^tm3_clk_v2 0 +.latch n507 top^FF_NODE~40 re top^tm3_clk_v0 0 +.latch n512 top^FF_NODE~57 re top^tm3_clk_v0 0 +.latch n517 top^FF_NODE~81 re top^tm3_clk_v0 0 +.latch n522 top^FF_NODE~58 re top^tm3_clk_v0 0 +.latch n527 top^FF_NODE~82 re top^tm3_clk_v0 0 +.latch n632 top^FF_NODE~69 re top^tm3_clk_v0 0 +.latch n637 top^FF_NODE~93 re top^tm3_clk_v0 0 +.latch n682 top^FF_NODE~74 re top^tm3_clk_v0 0 +.latch n687 top^FF_NODE~98 re top^tm3_clk_v0 0 +.latch n692 top^FF_NODE~75 re top^tm3_clk_v0 0 +.latch n697 top^FF_NODE~99 re top^tm3_clk_v0 0 +.latch n702 top^FF_NODE~76 re top^tm3_clk_v0 0 +.latch n707 top^FF_NODE~100 re top^tm3_clk_v0 0 +.latch n712 top^FF_NODE~77 re top^tm3_clk_v0 0 +.latch n717 top^FF_NODE~101 re top^tm3_clk_v0 0 +.latch n722 top^FF_NODE~78 re top^tm3_clk_v0 0 +.latch n727 top^FF_NODE~102 re top^tm3_clk_v0 0 +.latch n751 top^FF_NODE~114 re top^tm3_clk_v0 0 +.latch n755 top^FF_NODE~115 re top^tm3_clk_v0 0 +.latch n759 top^FF_NODE~116 re top^tm3_clk_v0 0 +.latch n763 top^FF_NODE~379 re top^tm3_clk_v2 0 +.latch n767 top^FF_NODE~380 re top^tm3_clk_v2 0 + +.names top^tm3_vidin_href top^tm3_vidin_cref top^FF_NODE~20 n107 +100 1 +111 1 +.names top^tm3_vidin_vs top^FF_NODE~30 n458 n112 +001 1 +010 1 +.names top^tm3_vidin_href top^FF_NODE~20 top^FF_NODE~22 top^FF_NODE~28 \ + top^FF_NODE~29 n459 n458 +1----- 0 +-00001 0 +.names top^FF_NODE~21 top^FF_NODE~23 top^FF_NODE~24 top^FF_NODE~25 \ + top^FF_NODE~26 top^FF_NODE~27 n459 +000000 1 +.names top^tm3_vidin_cref top^FF_NODE~30 top^FF_NODE~41 n117 +01- 1 +1-1 1 +.names top^FF_NODE~38 top^FF_NODE~40 top^FF_NODE~115 top^FF_NODE~116 n292 +0001 1 +.names top^tm3_vidin_vs top^FF_NODE~31 top^FF_NODE~30 n458 n127 +0011 1 +010- 1 +01-0 1 +.names top^tm3_vidin_cref top^FF_NODE~31 top^FF_NODE~42 n132 +01- 1 +1-1 1 +.names top^tm3_vidin_vs top^FF_NODE~31 top^FF_NODE~32 top^FF_NODE~30 n458 \ + n142 +001-- 1 +01011 1 +0-10- 1 +0-1-0 1 +.names top^tm3_vidin_cref top^FF_NODE~32 top^FF_NODE~43 n147 +01- 1 +1-1 1 +.names top^tm3_vidin_vs top^FF_NODE~33 top^FF_NODE~30 n458 top^FF_NODE~31 \ + top^FF_NODE~32 n157 +001111 1 +010--- 1 +01-0-- 1 +01--0- 1 +01---0 1 +.names top^tm3_vidin_cref top^FF_NODE~33 top^FF_NODE~44 n162 +01- 1 +1-1 1 +.names top^tm3_vidin_vs top^FF_NODE~33 top^FF_NODE~34 n473 top^FF_NODE~30 \ + n458 n172 +001--- 1 +010111 1 +0-10-- 1 +0-1-0- 1 +0-1--0 1 +.names top^FF_NODE~31 top^FF_NODE~32 n473 +11 1 +.names top^tm3_vidin_cref top^FF_NODE~34 top^FF_NODE~45 n177 +01- 1 +1-1 1 +.names top^tm3_vidin_vs top^FF_NODE~33 top^FF_NODE~34 top^FF_NODE~35 n477_1 \ + n473 n187 +00-1-- 1 +011011 1 +0-01-- 1 +0--10- 1 +0--1-0 1 +.names top^FF_NODE~30 n458 n477_1 +11 1 +.names top^tm3_vidin_cref top^FF_NODE~35 top^FF_NODE~46 n192 +01- 1 +1-1 1 +.names top^tm3_vidin_vs top^FF_NODE~36 n481 n202 +001 1 +010 1 +.names top^FF_NODE~33 top^FF_NODE~34 top^FF_NODE~35 n473 top^FF_NODE~30 \ + n458 n481 +111111 1 +.names top^tm3_vidin_cref top^FF_NODE~36 top^FF_NODE~47 n207 +01- 1 +1-1 1 +.names top^tm3_vidin_vs top^FF_NODE~36 top^FF_NODE~37 n481 n217 +001- 1 +0101 1 +0-10 1 +.names top^tm3_vidin_cref top^FF_NODE~37 top^FF_NODE~48 n222 +01- 1 +1-1 1 +.names top^FF_NODE~126 n292 n247 +10 1 +.names top^FF_NODE~127 n292 n252 +10 1 +.names top^tm3_vidin_href top^FF_NODE~21 top^tm3_vidin_cref top^FF_NODE~20 \ + n337 +1001 1 +111- 1 +11-0 1 +.names top^tm3_vidin_cref top^FF_NODE~21 top^FF_NODE~39 n342 +01- 1 +1-1 1 +.names top^tm3_vidin_href top^FF_NODE~21 top^FF_NODE~22 top^tm3_vidin_cref \ + top^FF_NODE~20 n347 +101-- 1 +11001 1 +1-11- 1 +1-1-0 1 +.names top^tm3_vidin_href top^FF_NODE~21 top^FF_NODE~22 top^FF_NODE~23 \ + top^tm3_vidin_cref top^FF_NODE~20 n357 +10-1-- 1 +111001 1 +1-01-- 1 +1--11- 1 +1--1-0 1 +.names top^tm3_vidin_href top^FF_NODE~21 top^FF_NODE~22 top^FF_NODE~23 \ + top^FF_NODE~24 n514 n367 +10--1- 1 +111101 1 +1-0-1- 1 +1--01- 1 +1---10 1 +.names top^tm3_vidin_cref top^FF_NODE~20 n514 +01 1 +.names top^tm3_vidin_cref top^FF_NODE~24 top^FF_NODE~51 n372 +01- 1 +1-1 1 +.names top^tm3_vidin_href top^FF_NODE~25 n517_1 n377 +101 1 +110 1 +.names top^tm3_vidin_cref top^FF_NODE~20 top^FF_NODE~21 top^FF_NODE~22 \ + top^FF_NODE~23 top^FF_NODE~24 n517_1 +011111 1 +.names top^tm3_vidin_cref top^FF_NODE~25 top^FF_NODE~52 n382 +01- 1 +1-1 1 +.names top^tm3_vidin_href top^FF_NODE~25 top^FF_NODE~26 n517_1 n387 +101- 1 +1101 1 +1-10 1 +.names top^tm3_vidin_cref top^FF_NODE~26 top^FF_NODE~53 n392 +01- 1 +1-1 1 +.names top^tm3_vidin_href top^FF_NODE~27 n522_1 n397 +101 1 +110 1 +.names top^FF_NODE~25 top^FF_NODE~26 n517_1 n522_1 +111 1 +.names top^tm3_vidin_cref top^FF_NODE~27 top^FF_NODE~54 n402 +01- 1 +1-1 1 +.names top^tm3_vidin_href top^FF_NODE~27 top^FF_NODE~28 n522_1 n407 +101- 1 +1101 1 +1-10 1 +.names top^tm3_vidin_cref top^FF_NODE~28 top^FF_NODE~55 n412 +01- 1 +1-1 1 +.names top^tm3_vidin_href top^FF_NODE~27 top^FF_NODE~28 top^FF_NODE~29 \ + n522_1 n417 +10-1- 1 +11101 1 +1-01- 1 +1--10 1 +.names top^tm3_vidin_cref top^FF_NODE~29 top^FF_NODE~56 n422 +01- 1 +1-1 1 +.names n529 n531 n533 n539 n543 n546 n528 +1----- 0 +-01111 0 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n530 n529 +100011 1 +.names top^FF_NODE~391 top^FF_NODE~392 n530 +01 1 +.names top^FF_NODE~392 n532 n531 +00 1 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 top^FF_NODE~391 n532 +00010- 0 +10-010 0 +11100- 0 +1111-0 0 +11-100 0 +1-0010 0 +-00010 0 +--1100 0 +.names top^FF_NODE~391 top^FF_NODE~392 n534 n535 n536 n538 n533 +1---1- 1 +-1--10 1 +--1110 1 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n534 +-0-11 0 +-1101 0 +--011 0 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n535 +01001 0 +01111 0 +10010 0 +10100 0 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n537 n536 +001011 0 +11-111 0 +1-1111 0 +-11111 0 +.names top^FF_NODE~391 top^FF_NODE~392 n537 +10 1 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n538 +0-000 1 +-0000 1 +.names top^FF_NODE~390 top^FF_NODE~391 top^FF_NODE~392 n540 n541 n542 n539 +0101-- 0 +-00--0 0 +-10-0- 0 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 n540 +0110 1 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n541 +1-010 0 +-1010 0 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n542 +01010 0 +0-100 0 +11000 0 +.names top^FF_NODE~391 top^FF_NODE~392 n538 n544 n545 n543 +01--0 0 +101-- 0 +10-0- 0 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n544 +11000 0 +-0100 0 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n545 +011-0 0 +101-0 0 +11-10 0 +--110 0 +.names top^FF_NODE~391 top^FF_NODE~392 n547 n548 n549 n550 n546 +00---- 1 +11---- 1 +-011-- 1 +-1--11 1 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n547 +0-110 0 +-0110 0 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n548 +00-11 0 +0-0-1 0 +11110 0 +1--01 0 +-00-1 0 +-1-01 0 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n549 +11100 0 +-0010 0 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n550 +00100 0 +01010 0 +11000 0 +-0001 0 +.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \ + top^FF_NODE~385 n552 +00000 1 +11-11 1 +--111 1 +.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \ + top^FF_NODE~385 n553 +11011 1 +.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \ + top^FF_NODE~385 n555 +0---- 1 +-1-11 1 +--111 1 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n537 n557 +000011 1 +001001 1 +010101 1 +100001 1 +101101 1 +110011 1 +111001 1 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n537 n558 +001111 1 +011011 1 +100111 1 +.names top^FF_NODE~389 top^FF_NODE~390 top^FF_NODE~391 top^FF_NODE~392 n560 \ + n561 n559 +10001- 0 +1110-1 0 +-000-1 0 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 n560 +001 1 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 n561 +111 1 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n530 n562 +000011 1 +000101 1 +010001 1 +011101 1 +101001 1 +110101 1 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n564 n563 +000111 1 +00-001 1 +010-01 1 +011-11 1 +01-011 1 +110111 1 +-00001 1 +.names top^FF_NODE~391 top^FF_NODE~392 n564 +00 1 +.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \ + top^FF_NODE~385 n547 n566 +000100 1 +00-010 1 +010110 1 +011-00 1 +01-000 1 +0-1000 1 +.names n568 n544 n569 n570 n571 n573 n567 +01-00- 1 +0-100- 1 +-1-001 1 +--1001 1 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n568 +0-011 1 +-0011 1 +.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \ + top^FF_NODE~385 n569 +01101 0 +0-011 0 +.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \ + top^FF_NODE~385 n541 n570 +000100 1 +001010 1 +010010 1 +011000 1 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n572 n571 +000100 1 +-11000 1 +.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \ + top^FF_NODE~385 n572 +00-01 0 +01-10 0 +0-001 0 +0-110 0 +.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \ + top^FF_NODE~385 n573 +00010 0 +01-00 0 +0-001 0 +.names n575 n582 n586 n589 n591 n595 n574 +000011 1 +.names n576 top^FF_NODE~391 top^FF_NODE~392 n575 +001 1 +.names n549 n577 n578 n579 n580 n581 n576 +0--0-- 0 +-10--- 0 +----00 0 +.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~385 n577 +0001 1 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n578 +0-100 0 +-0100 0 +.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \ + top^FF_NODE~385 n579 +00001 0 +0-100 0 +.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \ + top^FF_NODE~385 n580 +01100 0 +0-011 0 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n581 +-1000 0 +.names n583 n580 n584 n585 top^FF_NODE~391 top^FF_NODE~392 n582 +10--01 1 +--0001 1 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n583 +10000 1 +.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \ + top^FF_NODE~385 n584 +001-0 0 +00-01 0 +01011 0 +0-100 0 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n585 +00110 0 +-1010 0 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 n587 n537 n588 n586 +101110 1 +.names top^FF_NODE~389 top^FF_NODE~390 n587 +11 1 +.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \ + top^FF_NODE~385 n588 +00010 0 +0-100 0 +.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \ + top^FF_NODE~385 n590 n589 +01--01 1 +0-0101 1 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n537 n590 +1-1011 1 +-11011 1 +.names n588 n592 n593 n594 top^FF_NODE~391 top^FF_NODE~392 n591 +00--10 0 +--0010 0 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n592 +00111 0 +11011 0 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n593 +11110 0 +-0001 0 +.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \ + top^FF_NODE~385 n594 +000-1 0 +001-0 0 +00-10 0 +.names n596 n597 n598 n599 n600 n601 n595 +0--001 1 +-0-001 1 +--000- 1 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 n596 +0111 1 +.names top^FF_NODE~390 top^FF_NODE~391 top^FF_NODE~392 n597 +110 1 +.names top^FF_NODE~384 n577 n598 +11 1 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n564 n599 +000101 1 +100001 1 +-11001 1 +.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ + top^FF_NODE~390 n564 n600 +000011 1 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top^FF_NODE~392 n561 n587 n555 n477 +001--- 1 +01011- 1 +0-10-- 1 +0-1-0- 1 +1-1--1 1 +.names top^FF_NODE~381 top^FF_NODE~382 top^FF_NODE~383 top^FF_NODE~384 \ + top^FF_NODE~385 top^FF_NODE~378 n502 +10000- 1 +-----1 1 +.names top^tm3_vidin_cref top^tm3_vidin_vpo~0 top^FF_NODE~74 n682 +01- 1 +1-1 1 +.names top^tm3_vidin_cref top^FF_NODE~74 top^FF_NODE~98 n687 +0-1 1 +11- 1 +.names top^tm3_vidin_cref top^tm3_vidin_vpo~1 top^FF_NODE~75 n692 +01- 1 +1-1 1 +.names top^tm3_vidin_cref top^FF_NODE~75 top^FF_NODE~99 n697 +0-1 1 +11- 1 +.names top^tm3_vidin_cref top^tm3_vidin_vpo~2 top^FF_NODE~76 n702 +01- 1 +1-1 1 +.names top^tm3_vidin_cref top^FF_NODE~76 top^FF_NODE~100 n707 +0-1 1 +11- 1 +.names top^tm3_vidin_cref top^tm3_vidin_vpo~3 top^FF_NODE~77 n712 +01- 1 +1-1 1 +.names top^tm3_vidin_cref top^FF_NODE~77 top^FF_NODE~101 n717 +0-1 1 +11- 1 +.names top^tm3_vidin_cref top^tm3_vidin_vpo~4 top^FF_NODE~78 n722 +01- 1 +1-1 1 +.names top^tm3_vidin_cref top^FF_NODE~78 top^FF_NODE~102 n727 +0-1 1 +11- 1 +.names top^tm3_vidin_cref n751 +1 1 +.names top^FF_NODE~114 n755 +1 1 +.names top^FF_NODE~115 n759 +1 1 +.names top^tm3_vidin_rts0 n763 +1 1 +.names top^FF_NODE~379 n767 +1 1 +.end diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/tbk.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/tbk.blif new file mode 100644 index 000000000..a8d8cbed3 --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/tbk.blif @@ -0,0 +1,413 @@ +.model tbk.kiss2 +.inputs v0 v1 v2 v3 v4 v5 +.outputs v11.5 v11.6 v11.7 +.latch v11.0 v6 0 +.latch v11.1 v7 0 +.latch v11.2 v8 0 +.latch v11.3 v9 0 +.latch v11.4 v10 0 +.names [186] v11.5 +0 1 +.names [188] v11.6 +0 1 +.names [190] v11.7 +0 1 +.names [176] v11.0 +0 1 +.names [178] v11.1 +0 1 +.names [180] v11.2 +0 1 +.names [182] v11.3 +0 1 +.names [184] v11.4 +0 1 +.names v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 [0] +11001110001 1 +.names v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 [1] +11001100010 1 +.names v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 [2] +01001110001 1 +.names v0 v1 v2 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1 +.names [3] [5] [6] [7] [8] [9] [11] [13] [15] [18] [19] [20] [21] [23] [24] \ +[26] [28] [30] [34] [40] [41] [44] [49] [55] [59] [68] [188] +00000000000000000000000000 1 +.names [0] [1] [2] [7] [25] [26] [190] +000000 1 +.end diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/traffic.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/traffic.blif new file mode 100644 index 000000000..0167de3c7 --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/traffic.blif @@ -0,0 +1,172 @@ +.model tlc.sim +.inputs in1 +.inputs in2 +.inputs in3 +.outputs out11 +.outputs out12 +.outputs out13 +.outputs out14 +.outputs out15 +.latch out1 in4 0 +.latch out2 in5 0 +.latch out3 in6 0 +.latch out4 in7 0 +.latch out5 in8 0 +.latch out6 in9 0 +.latch out7 in10 0 +.latch out8 in11 0 +.latch out9 in12 0 +.latch out10 in13 0 +.names in1 in1* +0 1 +.names in3 in3* +0 1 +.names in4 in4* +0 1 +.names in5 in5* +0 1 +.names in6 in6* +0 1 +.names in7 in7* +0 1 +.names in8 in8* +0 1 +.names in1* in4* in5* in6* in7 g_1and1 +11111 1 +.names in1* in4 in5 in6* in7* g_1and2 +11111 1 +.names in1* in4 in5 in6 in7* g_1and3 +11111 1 +.names in1* in3 in8* g_1and4 +111 1 +.names in1* in3* in8 g_1and5 +111 1 +.names in1* in4 in5* in7* g_1and6 +1111 1 +.names in1* in4* in5 in7* g_1and7 +1111 1 +.names in1* in5* in6 in7* g_1and8 +1111 1 +.names in1* in4* in6 in7* g_1and9 +1111 1 +.names in1* in4* in7* g_1and10 +111 1 +.names g_1and1 g_1and10 out1 +00 0 +.names g_1and6 g_1and7 out2 +00 0 +.names g_1and2 g_1and8 g_1and9 out3 +000 0 +.names g_1and1 g_1and3 out4 +00 0 +.names g_1and4 g_1and5 out5 +00 0 +.names in1 gin1* +0 1 +.names in2 gin2* +0 1 +.names in4 gin4* +0 1 +.names in5 gin5* +0 1 +.names in6 gin6* +0 1 +.names in7 gin7* +0 1 +.names in9 gin9* +0 1 +.names in10 gin10* +0 1 +.names in11 gin11* +0 1 +.names in12 gin12* +0 1 +.names in13 gin13* +0 1 +.names gin1* gin4* gin5* gin6* gin9* in12 g_2and1 +111111 1 +.names gin1* gin4* gin5* gin6* gin9* in11 g_2and2 +111111 1 +.names gin1* gin4* gin5* gin6* gin9* in13 g_2and3 +111111 1 +.names gin1* gin4* gin5* gin6* gin9* in10 g_2and4 +111111 1 +.names gin1* in6 in7 in10 in11 gin12* gin13* g_2and5 +1111111 1 +.names gin1* in5 in7 in10 in11 gin12* gin13* g_2and6 +1111111 1 +.names gin1* in4 in7 in10 in11 gin12* gin13* g_2and7 +1111111 1 +.names gin1* in6 in7 in10 in11 in12 gin13* g_2and8 +1111111 1 +.names gin1* in5 in7 in10 in11 in12 gin13* g_2and9 +1111111 1 +.names gin1* in4 in7 in10 in11 in12 gin13* g_2and10 +1111111 1 +.names gin1* in6 in7 gin10* gin11* gin12* in13 g_2and11 +1111111 1 +.names gin1* in5 in7 gin10* gin11* gin12* in13 g_2and12 +1111111 1 +.names gin1* in4 in7 gin10* gin11* gin12* in13 g_2and13 +1111111 1 +.names gin1* in9 in10 in11 gin12* gin13* g_2and14 +111111 1 +.names gin1* in6 in7 in10 gin11* gin13* g_2and15 +111111 1 +.names gin1* in5 in7 in10 gin11* gin13* g_2and16 +111111 1 +.names gin1* in4 in7 in10 gin11* gin13* g_2and17 +111111 1 +.names gin1* in9 in10 in11 in12 gin13* g_2and18 +111111 1 +.names gin1* in9 gin10* gin11* gin12* in13 g_2and19 +111111 1 +.names gin1* in9 in10 gin11* gin13* g_2and20 +11111 1 +.names gin1* gin10* in12 gin13* g_2and21 +1111 1 +.names gin1* in6 in7 gin10* gin13* g_2and22 +11111 1 +.names gin1* in5 in7 gin10* gin13* g_2and23 +11111 1 +.names gin1* in4 in7 gin10* gin13* g_2and24 +11111 1 +.names gin1* gin7* gin9* in12 g_2and25 +1111 1 +.names gin1* gin7* gin9* in11 g_2and26 +1111 1 +.names gin1* gin7* gin9* in13 g_2and27 +1111 1 +.names gin1* gin2* in9 g_2and28 +111 1 +.names gin1* in2 gin9* g_2and29 +111 1 +.names gin1* gin7* gin9* in10 g_2and30 +1111 1 +.names gin1* gin11* in12 gin13* g_2and31 +1111 1 +.names gin1* in9 gin10* gin13* g_2and32 +1111 1 +.names gin1* gin10* in11 gin13* g_2and33 +1111 1 +.names g_2and28 g_2and29 out6 +00 0 +.names g_2and4 g_2and11 g_2and12 g_2and13 g_2and19 g_2and22 g_2and23 g_2and24 g_2and30 g_2and32 out7 +0000000000 0 +.names g_2and2 g_2and15 g_2and16 g_2and17 g_2and20 g_2and26 g_2and33 out8 +0000000 0 +.names g_2and1 g_2and5 g_2and6 g_2and7 g_2and14 g_2and21 g_2and25 g_2and31 out9 +00000000 0 +.names g_2and3 g_2and8 g_2and9 g_2and10 g_2and11 g_2and12 g_2and13 g_2and18 g_2and19 g_2and27 out10 +0000000000 0 +.names g_2and28 g_2and29 out11 +00 0 +.names g_2and4 g_2and11 g_2and12 g_2and13 g_2and19 g_2and22 g_2and23 g_2and24 g_2and30 g_2and32 out12 +0000000000 0 +.names g_2and2 g_2and15 g_2and16 g_2and17 g_2and20 g_2and26 g_2and33 out13 +0000000 0 +.names g_2and1 g_2and5 g_2and6 g_2and7 g_2and14 g_2and21 g_2and25 g_2and31 out14 +00000000 0 +.names g_2and3 g_2and8 g_2and9 g_2and10 g_2and11 g_2and12 g_2and13 g_2and18 g_2and19 g_2and27 out15 +0000000000 0 +.end diff --git a/fpga_flow/benchmarks/FPGA_SPICE_bench/usb_phy.blif b/fpga_flow/benchmarks/FPGA_SPICE_bench/usb_phy.blif new file mode 100644 index 000000000..8b8f164ad --- /dev/null +++ b/fpga_flow/benchmarks/FPGA_SPICE_bench/usb_phy.blif @@ -0,0 +1,1308 @@ +# Benchmark "usb_phy" written by ABC on Mon Aug 29 15:33:14 2005 +.model usb_phy +.inputs clk rst phy_tx_mode rxd rxdp rxdn TxValid_i DataOut_i[0] \ + DataOut_i[1] DataOut_i[2] DataOut_i[3] DataOut_i[4] DataOut_i[5] \ + DataOut_i[6] DataOut_i[7] +.outputs usb_rst txdp txdn txoe TxReady_o RxValid_o RxActive_o RxError_o \ + DataIn_o[0] DataIn_o[1] DataIn_o[2] DataIn_o[3] DataIn_o[4] DataIn_o[5] \ + DataIn_o[6] DataIn_o[7] LineState_o[0] LineState_o[1] + +.latch i_rx_phy_shift_en_reg_in i_rx_phy_shift_en_reg 2 +.latch \i_rx_phy_fs_state_reg[0]_in \i_rx_phy_fs_state_reg[0] 2 +.latch i_rx_phy_rx_active_reg_in i_rx_phy_rx_active_reg 2 +.latch i_rx_phy_sync_err_reg_in i_rx_phy_sync_err_reg 2 +.latch \i_rx_phy_fs_state_reg[1]_in \i_rx_phy_fs_state_reg[1] 2 +.latch \i_rx_phy_fs_state_reg[2]_in \i_rx_phy_fs_state_reg[2] 2 +.latch i_rx_phy_byte_err_reg_in i_rx_phy_byte_err_reg 2 +.latch \i_tx_phy_hold_reg_reg[7]_in \i_tx_phy_hold_reg_reg[7] 2 +.latch i_rx_phy_bit_stuff_err_reg_in i_rx_phy_bit_stuff_err_reg 2 +.latch \i_tx_phy_hold_reg_reg[0]_in \i_tx_phy_hold_reg_reg[0] 2 +.latch \i_tx_phy_hold_reg_reg[1]_in \i_tx_phy_hold_reg_reg[1] 2 +.latch \i_tx_phy_hold_reg_reg[2]_in \i_tx_phy_hold_reg_reg[2] 2 +.latch \i_tx_phy_hold_reg_reg[3]_in \i_tx_phy_hold_reg_reg[3] 2 +.latch \i_tx_phy_hold_reg_reg[4]_in \i_tx_phy_hold_reg_reg[4] 2 +.latch \i_tx_phy_hold_reg_reg[5]_in \i_tx_phy_hold_reg_reg[5] 2 +.latch \i_tx_phy_hold_reg_reg[6]_in \i_tx_phy_hold_reg_reg[6] 2 +.latch i_rx_phy_se0_s_reg_in i_rx_phy_se0_s_reg 2 +.latch \i_tx_phy_state_reg[0]_in \i_tx_phy_state_reg[0] 2 +.latch \i_rx_phy_dpll_state_reg[0]_in \i_rx_phy_dpll_state_reg[0] 2 +.latch \i_tx_phy_state_reg[2]_in \i_tx_phy_state_reg[2] 2 +.latch i_rx_phy_rx_valid1_reg_in i_rx_phy_rx_valid1_reg 2 +.latch \i_rx_phy_dpll_state_reg[1]_in \i_rx_phy_dpll_state_reg[1] 2 +.latch i_rx_phy_rx_valid_r_reg_in i_rx_phy_rx_valid_r_reg 2 +.latch i_rx_phy_se0_r_reg_in i_rx_phy_se0_r_reg 2 +.latch \rst_cnt_reg[3]_in \rst_cnt_reg[3] 2 +.latch \rst_cnt_reg[4]_in \rst_cnt_reg[4] 2 +.latch \rst_cnt_reg[2]_in \rst_cnt_reg[2] 2 +.latch \i_tx_phy_state_reg[1]_in \i_tx_phy_state_reg[1] 2 +.latch \i_rx_phy_one_cnt_reg[2]_in \i_rx_phy_one_cnt_reg[2] 2 +.latch \i_rx_phy_one_cnt_reg[1]_in \i_rx_phy_one_cnt_reg[1] 2 +.latch i_tx_phy_sd_raw_o_reg_in i_tx_phy_sd_raw_o_reg 2 +.latch \i_rx_phy_bit_cnt_reg[2]_in \i_rx_phy_bit_cnt_reg[2] 2 +.latch \i_tx_phy_bit_cnt_reg[2]_in \i_tx_phy_bit_cnt_reg[2] 2 +.latch i_tx_phy_append_eop_reg_in i_tx_phy_append_eop_reg 2 +.latch \i_rx_phy_one_cnt_reg[0]_in \i_rx_phy_one_cnt_reg[0] 2 +.latch \i_rx_phy_bit_cnt_reg[0]_in \i_rx_phy_bit_cnt_reg[0] 2 +.latch \i_rx_phy_bit_cnt_reg[1]_in \i_rx_phy_bit_cnt_reg[1] 2 +.latch i_tx_phy_ld_data_reg_in i_tx_phy_ld_data_reg 2 +.latch \i_tx_phy_one_cnt_reg[1]_in \i_tx_phy_one_cnt_reg[1] 2 +.latch \i_tx_phy_one_cnt_reg[2]_in \i_tx_phy_one_cnt_reg[2] 2 +.latch i_tx_phy_TxReady_o_reg_in i_tx_phy_TxReady_o_reg 2 +.latch \i_tx_phy_bit_cnt_reg[0]_in \i_tx_phy_bit_cnt_reg[0] 2 +.latch \i_tx_phy_bit_cnt_reg[1]_in \i_tx_phy_bit_cnt_reg[1] 2 +.latch \i_tx_phy_one_cnt_reg[0]_in \i_tx_phy_one_cnt_reg[0] 2 +.latch i_rx_phy_rx_valid_reg_in i_rx_phy_rx_valid_reg 2 +.latch \i_rx_phy_hold_reg_reg[6]_in \i_rx_phy_hold_reg_reg[6] 2 +.latch \i_rx_phy_hold_reg_reg[4]_in \i_rx_phy_hold_reg_reg[4] 2 +.latch \i_rx_phy_hold_reg_reg[0]_in \i_rx_phy_hold_reg_reg[0] 2 +.latch \i_rx_phy_hold_reg_reg[1]_in \i_rx_phy_hold_reg_reg[1] 2 +.latch \i_rx_phy_hold_reg_reg[2]_in \i_rx_phy_hold_reg_reg[2] 2 +.latch \i_rx_phy_hold_reg_reg[3]_in \i_rx_phy_hold_reg_reg[3] 2 +.latch \i_rx_phy_hold_reg_reg[5]_in \i_rx_phy_hold_reg_reg[5] 2 +.latch \i_rx_phy_hold_reg_reg[7]_in \i_rx_phy_hold_reg_reg[7] 2 +.latch i_tx_phy_tx_ip_reg_in i_tx_phy_tx_ip_reg 2 +.latch \rst_cnt_reg[1]_in \rst_cnt_reg[1] 2 +.latch i_tx_phy_txdp_reg_in i_tx_phy_txdp_reg 2 +.latch i_rx_phy_sd_nrzi_reg_in i_rx_phy_sd_nrzi_reg 2 +.latch i_tx_phy_sd_bs_o_reg_in i_tx_phy_sd_bs_o_reg 2 +.latch \rst_cnt_reg[0]_in \rst_cnt_reg[0] 2 +.latch i_tx_phy_txdn_reg_in i_tx_phy_txdn_reg 2 +.latch i_tx_phy_append_eop_sync3_reg_in i_tx_phy_append_eop_sync3_reg 2 +.latch i_tx_phy_txoe_reg_in i_tx_phy_txoe_reg 2 +.latch i_rx_phy_rxdn_s_reg_in i_rx_phy_rxdn_s_reg 2 +.latch i_rx_phy_rxdp_s_reg_in i_rx_phy_rxdp_s_reg 2 +.latch i_tx_phy_sft_done_reg_in i_tx_phy_sft_done_reg 2 +.latch i_tx_phy_tx_ip_sync_reg_in i_tx_phy_tx_ip_sync_reg 2 +.latch i_tx_phy_txoe_r1_reg_in i_tx_phy_txoe_r1_reg 2 +.latch i_tx_phy_append_eop_sync1_reg_in i_tx_phy_append_eop_sync1_reg 2 +.latch i_tx_phy_append_eop_sync2_reg_in i_tx_phy_append_eop_sync2_reg 2 +.latch i_tx_phy_txoe_r2_reg_in i_tx_phy_txoe_r2_reg 2 +.latch usb_rst_reg_in usb_rst_reg 2 +.latch i_tx_phy_sd_nrzi_o_reg_in i_tx_phy_sd_nrzi_o_reg 2 +.latch i_tx_phy_append_eop_sync4_reg_in i_tx_phy_append_eop_sync4_reg 2 +.latch i_rx_phy_fs_ce_reg_in i_rx_phy_fs_ce_reg 2 +.latch i_rx_phy_rxd_s_reg_in i_rx_phy_rxd_s_reg 2 +.latch i_rx_phy_sd_r_reg_in i_rx_phy_sd_r_reg 2 +.latch i_rx_phy_fs_ce_r2_reg_in i_rx_phy_fs_ce_r2_reg 2 +.latch i_tx_phy_data_done_reg_in i_tx_phy_data_done_reg 2 +.latch i_rx_phy_rxdn_s_r_reg_in i_rx_phy_rxdn_s_r_reg 2 +.latch i_rx_phy_rxdp_s_r_reg_in i_rx_phy_rxdp_s_r_reg 2 +.latch i_rx_phy_fs_ce_r1_reg_in i_rx_phy_fs_ce_r1_reg 2 +.latch i_rx_phy_rxd_r_reg_in i_rx_phy_rxd_r_reg 2 +.latch i_rx_phy_rxdn_s1_reg_in i_rx_phy_rxdn_s1_reg 2 +.latch i_rx_phy_rxd_s1_reg_in i_rx_phy_rxd_s1_reg 2 +.latch i_rx_phy_rxdp_s1_reg_in i_rx_phy_rxdp_s1_reg 2 +.latch \i_tx_phy_hold_reg_d_reg[1]_in \i_tx_phy_hold_reg_d_reg[1] 2 +.latch \i_tx_phy_hold_reg_d_reg[5]_in \i_tx_phy_hold_reg_d_reg[5] 2 +.latch i_rx_phy_rxd_s0_reg_in i_rx_phy_rxd_s0_reg 2 +.latch \i_tx_phy_hold_reg_d_reg[3]_in \i_tx_phy_hold_reg_d_reg[3] 2 +.latch i_rx_phy_rxdn_s0_reg_in i_rx_phy_rxdn_s0_reg 2 +.latch \i_tx_phy_hold_reg_d_reg[6]_in \i_tx_phy_hold_reg_d_reg[6] 2 +.latch i_tx_phy_sft_done_r_reg_in i_tx_phy_sft_done_r_reg 2 +.latch \i_tx_phy_hold_reg_d_reg[0]_in \i_tx_phy_hold_reg_d_reg[0] 2 +.latch i_rx_phy_rxdp_s0_reg_in i_rx_phy_rxdp_s0_reg 2 +.latch \i_tx_phy_hold_reg_d_reg[2]_in \i_tx_phy_hold_reg_d_reg[2] 2 +.latch i_rx_phy_rx_en_reg_in i_rx_phy_rx_en_reg 2 +.latch \i_tx_phy_hold_reg_d_reg[7]_in \i_tx_phy_hold_reg_d_reg[7] 2 +.latch \i_tx_phy_hold_reg_d_reg[4]_in \i_tx_phy_hold_reg_d_reg[4] 2 + +.names [131] + 0 +.names [132] + 1 +.names [142] [137] [145] RxError_o +111 0 +.names i_rx_phy_shift_en_reg [134] +1 1 +.names \i_rx_phy_fs_state_reg[0] [135] +1 1 +.names i_rx_phy_rx_active_reg RxActive_o +1 1 +.names i_rx_phy_sync_err_reg [137] +0 1 +.names [547] \i_rx_phy_fs_state_reg[0]_in +0 1 +.names \i_rx_phy_fs_state_reg[1] [139] +1 1 +.names \i_rx_phy_fs_state_reg[2] [140] +1 1 +.names [154] [551] [403] \i_rx_phy_fs_state_reg[1]_in +11- 0 +--1 0 +.names i_rx_phy_byte_err_reg [142] +0 1 +.names [157] [198] [143] +11 0 +.names \i_tx_phy_hold_reg_reg[7] \i_tx_phy_hold_reg_d_reg[7]_in +1 1 +.names i_rx_phy_bit_stuff_err_reg [145] +0 1 +.names \i_tx_phy_hold_reg_reg[0] \i_tx_phy_hold_reg_d_reg[0]_in +1 1 +.names \i_tx_phy_hold_reg_reg[1] \i_tx_phy_hold_reg_d_reg[1]_in +1 1 +.names \i_tx_phy_hold_reg_reg[2] \i_tx_phy_hold_reg_d_reg[2]_in +1 1 +.names \i_tx_phy_hold_reg_reg[3] \i_tx_phy_hold_reg_d_reg[3]_in +1 1 +.names \i_tx_phy_hold_reg_reg[4] \i_tx_phy_hold_reg_d_reg[4]_in +1 1 +.names \i_tx_phy_hold_reg_reg[5] \i_tx_phy_hold_reg_d_reg[5]_in +1 1 +.names \i_tx_phy_hold_reg_reg[6] \i_tx_phy_hold_reg_d_reg[6]_in +1 1 +.names [661] [175] [191] \i_tx_phy_hold_reg_reg[7]_in +111 0 +.names [170] [589] [154] +11 0 +.names [168] i_rx_phy_bit_stuff_err_reg_in +0 1 +.names [171] [195] i_rx_phy_byte_err_reg_in +00 1 +.names [393] [415] [174] [157] +111 0 +.names i_rx_phy_se0_s_reg [158] +1 1 +.names [615] [606] [159] +11 0 +.names [179] [661] \i_tx_phy_hold_reg_reg[0]_in +11 1 +.names [180] [661] \i_tx_phy_hold_reg_reg[1]_in +11 1 +.names [181] [661] \i_tx_phy_hold_reg_reg[2]_in +11 1 +.names [182] [661] \i_tx_phy_hold_reg_reg[3]_in +11 1 +.names [183] [661] \i_tx_phy_hold_reg_reg[4]_in +11 1 +.names [184] [661] \i_tx_phy_hold_reg_reg[5]_in +11 1 +.names [185] [661] \i_tx_phy_hold_reg_reg[6]_in +11 1 +.names [629] [190] [167] +11 0 +.names [374] [431] [236] \i_rx_phy_hold_reg_reg[7]_in [168] +1111 0 +.names \i_tx_phy_state_reg[0] [169] +1 1 +.names [582] [170] +0 1 +.names [217] [212] [193] [171] +00- 1 +--0 1 +.names [519] [602] [194] i_rx_phy_se0_s_reg_in +00- 1 +--0 1 +.names \i_rx_phy_dpll_state_reg[0] [173] +1 1 +.names [612] [197] [174] +00 1 +.names [207] DataOut_i[7] [175] +11 0 +.names [583] [176] +0 1 +.names [583] [177] +0 1 +.names [556] [619] [414] \i_tx_phy_state_reg[0]_in +11- 0 +--1 0 +.names DataOut_i[0] \i_tx_phy_hold_reg_d_reg[0]_in [222] [179] +01- 1 +1-1 1 +.names DataOut_i[1] \i_tx_phy_hold_reg_d_reg[1]_in [222] [180] +01- 1 +1-1 1 +.names DataOut_i[2] \i_tx_phy_hold_reg_d_reg[2]_in [222] [181] +01- 1 +1-1 1 +.names DataOut_i[3] \i_tx_phy_hold_reg_d_reg[3]_in [222] [182] +01- 1 +1-1 1 +.names DataOut_i[4] \i_tx_phy_hold_reg_d_reg[4]_in [222] [183] +01- 1 +1-1 1 +.names DataOut_i[5] \i_tx_phy_hold_reg_d_reg[5]_in [222] [184] +01- 1 +1-1 1 +.names DataOut_i[6] \i_tx_phy_hold_reg_d_reg[6]_in [222] [185] +01- 1 +1-1 1 +.names \i_tx_phy_state_reg[2] [186] +1 1 +.names i_rx_phy_rx_valid1_reg [187] +1 1 +.names \i_rx_phy_dpll_state_reg[1] [188] +1 1 +.names i_rx_phy_rx_valid_r_reg [189] +1 1 +.names [618] [666] [190] +11 0 +.names \i_tx_phy_hold_reg_d_reg[7]_in [222] [191] +11 0 +.names [225] [261] rst \i_rx_phy_dpll_state_reg[0]_in +111 0 +.names i_rx_phy_se0_r_reg [193] +0 1 +.names i_rx_phy_se0_r_reg_in [674] [194] +11 0 +.names i_rx_phy_se0_r_reg_in RxActive_o [195] +11 0 +.names [189] i_rx_phy_se0_r_reg_in [196] +11 0 +.names [634] [197] +0 1 +.names [221] [443] [636] [198] +111 0 +.names \rst_cnt_reg[3] [199] +1 1 +.names \rst_cnt_reg[4] [200] +1 1 +.names \rst_cnt_reg[2] [201] +1 1 +.names \i_tx_phy_state_reg[1] [202] +1 1 +.names \i_rx_phy_one_cnt_reg[2] [203] +1 1 +.names \i_rx_phy_one_cnt_reg[1] [204] +1 1 +.names [612] [471] [205] +11 0 +.names [261] [479] [414] \i_rx_phy_dpll_state_reg[1]_in +11- 0 +--1 0 +.names [222] [207] +0 1 +.names [427] RxValid_o i_rx_phy_rx_valid_r_reg_in +00 0 +.names [255] [348] [404] \i_tx_phy_state_reg[2]_in +11- 0 +--1 0 +.names [585] [238] i_rx_phy_rx_valid1_reg_in +11 0 +.names i_tx_phy_sd_raw_o_reg [211] +1 1 +.names \i_rx_phy_bit_cnt_reg[2] [212] +1 1 +.names \i_tx_phy_bit_cnt_reg[2] [213] +1 1 +.names i_tx_phy_append_eop_reg [214] +1 1 +.names \i_rx_phy_one_cnt_reg[0] [215] +1 1 +.names \i_rx_phy_bit_cnt_reg[0] [216] +1 1 +.names \i_rx_phy_bit_cnt_reg[1] [217] +1 1 +.names [265] [385] \rst_cnt_reg[2]_in +00 1 +.names [430] [276] [651] \i_rx_phy_one_cnt_reg[1]_in +11- 0 +--1 0 +.names [236] i_rx_phy_se0_r_reg_in +0 1 +.names [272] [552] [221] +00 1 +.names i_tx_phy_ld_data_reg [222] +0 1 +.names \i_tx_phy_one_cnt_reg[1] [223] +1 1 +.names [243] \rst_cnt_reg[4]_in +0 1 +.names [465] [299] [260] [225] +11- 0 +--1 0 +.names [652] rst \i_tx_phy_state_reg[1]_in +11 1 +.names [264] [385] \rst_cnt_reg[3]_in +00 1 +.names \i_tx_phy_one_cnt_reg[2] [228] +1 1 +.names i_tx_phy_TxReady_o_reg TxReady_o +1 1 +.names \i_tx_phy_bit_cnt_reg[0] [230] +1 1 +.names \i_tx_phy_bit_cnt_reg[1] [231] +1 1 +.names \i_tx_phy_one_cnt_reg[0] [232] +1 1 +.names [275] [475] \i_tx_phy_bit_cnt_reg[2]_in +00 1 +.names [291] [302] [651] \i_rx_phy_bit_cnt_reg[2]_in +11- 0 +--1 0 +.names [554] [537] [235] +00 1 +.names [272] [553] [236] +11 0 +.names [280] [310] [496] i_tx_phy_sd_raw_o_reg_in +11- 0 +--1 0 +.names [586] [212] rst [473] [238] +1111 0 +.names [477] [658] [414] i_tx_phy_append_eop_reg_in +11- 0 +--1 0 +.names [292] [315] [651] \i_rx_phy_bit_cnt_reg[0]_in +11- 0 +--1 0 +.names [426] [300] [651] \i_rx_phy_one_cnt_reg[0]_in +11- 0 +--1 0 +.names [293] [312] [651] \i_rx_phy_bit_cnt_reg[1]_in +11- 0 +--1 0 +.names [273] [356] [243] +11 0 +.names i_rx_phy_rx_valid_reg RxValid_o +1 1 +.names \i_rx_phy_hold_reg_reg[6] \i_rx_phy_hold_reg_reg[5]_in +1 1 +.names \i_rx_phy_hold_reg_reg[4] \i_rx_phy_hold_reg_reg[3]_in +1 1 +.names \i_rx_phy_hold_reg_reg[0] DataIn_o[0] +1 1 +.names \i_rx_phy_hold_reg_reg[1] \i_rx_phy_hold_reg_reg[0]_in +1 1 +.names \i_rx_phy_hold_reg_reg[2] \i_rx_phy_hold_reg_reg[1]_in +1 1 +.names \i_rx_phy_hold_reg_reg[3] \i_rx_phy_hold_reg_reg[2]_in +1 1 +.names \i_rx_phy_hold_reg_reg[5] \i_rx_phy_hold_reg_reg[4]_in +1 1 +.names \i_rx_phy_hold_reg_reg[7] \i_rx_phy_hold_reg_reg[6]_in +1 1 +.names i_tx_phy_tx_ip_reg [253] +1 1 +.names [428] [307] [475] \i_tx_phy_one_cnt_reg[1]_in +11- 0 +--1 0 +.names [318] [641] [321] [255] +11- 0 +--1 0 +.names [314] [336] [475] \i_tx_phy_bit_cnt_reg[0]_in +11- 0 +--1 0 +.names [305] [340] [475] \i_tx_phy_bit_cnt_reg[1]_in +11- 0 +--1 0 +.names \rst_cnt_reg[1] [258] +1 1 +.names [334] [290] i_tx_phy_TxReady_o_reg_in +11 0 +.names [299] [479] [260] +00 1 +.names [299] [188] [530] [261] +111 0 +.names [423] [306] [475] \i_tx_phy_one_cnt_reg[2]_in +11- 0 +--1 0 +.names [346] [541] [301] i_tx_phy_ld_data_reg_in +00- 1 +--0 1 +.names [425] [199] [279] [264] +11- 0 +--1 0 +.names [425] [201] [281] [265] +11- 0 +--1 0 +.names i_tx_phy_txdp_reg txdp +1 1 +.names i_rx_phy_sd_nrzi_reg \i_rx_phy_hold_reg_reg[7]_in +1 1 +.names i_tx_phy_sd_bs_o_reg [268] +1 1 +.names \rst_cnt_reg[0] [269] +1 1 +.names i_tx_phy_txdn_reg txdn +1 1 +.names i_tx_phy_append_eop_sync3_reg [271] +1 1 +.names [282] [272] +0 1 +.names [328] [425] [371] [273] +00- 1 +--0 1 +.names [424] [338] [475] \i_tx_phy_one_cnt_reg[0]_in +11- 0 +--1 0 +.names [342] [213] [308] [275] +11- 0 +--1 0 +.names [446] [649] [276] +11 0 +.names [586] [187] i_rx_phy_rx_valid_reg_in +11 1 +.names i_tx_phy_txoe_reg i_rx_phy_rx_en_reg_in +1 1 +.names [344] [367] [425] [279] +11- 0 +--1 0 +.names [382] [337] [280] +00 1 +.names [332] [425] [281] +00 1 +.names i_rx_phy_rxdn_s_reg [282] +1 1 +.names i_rx_phy_rxdp_s_reg [283] +1 1 +.names [373] [357] [385] \rst_cnt_reg[1]_in +11- 0 +--1 0 +.names [331] rst i_tx_phy_txdp_reg_in +11 0 +.names [359] RxActive_o [414] i_rx_phy_sd_nrzi_reg_in +11- 0 +--1 0 +.names [429] [360] [403] i_tx_phy_txdn_reg_in +11- 0 +--1 0 +.names [326] [385] \rst_cnt_reg[0]_in +00 1 +.names [351] [339] i_tx_phy_sd_bs_o_reg_in +11 0 +.names [320] [363] [572] [451] [290] +1111 0 +.names [212] [587] [291] +11 0 +.names [216] [587] [292] +11 0 +.names [217] [587] [293] +11 0 +.names i_tx_phy_sft_done_reg i_tx_phy_sft_done_r_reg_in +1 1 +.names i_tx_phy_tx_ip_sync_reg [295] +1 1 +.names i_tx_phy_txoe_r1_reg [296] +1 1 +.names i_tx_phy_append_eop_sync1_reg [297] +1 1 +.names i_tx_phy_append_eop_sync2_reg [298] +1 1 +.names [327] [534] [299] +00 0 +.names [319] [528] [674] [300] +111 0 +.names [363] [541] [592] [301] +111 0 +.names [432] [586] [302] +11 0 +.names i_tx_phy_txoe_r2_reg [303] +1 1 +.names usb_rst_reg usb_rst +1 1 +.names [342] [508] [305] +11 0 +.names [433] [355] [306] +11 0 +.names [448] [355] [307] +11 0 +.names [441] [442] [342] [308] +11- 0 +--1 0 +.names [350] [354] i_tx_phy_append_eop_sync3_reg_in +11 0 +.names [370] [213] [388] [310] +11- 0 +--1 0 +.names [586] [134] [311] +11 0 +.names [447] [586] [312] +11 0 +.names [349] rst i_tx_phy_txoe_reg_in +11 0 +.names [342] [230] [314] +11 0 +.names [514] [586] [315] +11 0 +.names i_tx_phy_sd_nrzi_o_reg [316] +1 1 +.names i_tx_phy_append_eop_sync4_reg [317] +1 1 +.names [623] [535] [318] +11 0 +.names [343] [319] +0 1 +.names [624] [655] [320] +00 1 +.names [539] [321] +0 1 +.names [381] [404] i_tx_phy_txoe_r1_reg_in +00 1 +.names [378] [404] i_tx_phy_tx_ip_sync_reg_in +00 1 +.names [379] [404] i_tx_phy_append_eop_sync1_reg_in +00 1 +.names [380] [403] i_tx_phy_append_eop_sync2_reg_in +00 1 +.names [425] [505] [377] [326] +11- 0 +--1 0 +.names [375] [376] [327] +11 0 +.names [200] [516] [400] [328] +01- 1 +1-1 1 +.names [392] [383] i_rx_phy_rxdn_s_reg_in +11 0 +.names [390] [384] i_rx_phy_rxdp_s_reg_in +11 0 +.names [391] [316] [597] txdp [331] +11-- 0 +--11 0 +.names [455] [201] [386] [332] +11- 0 +--1 0 +.names i_rx_phy_fs_ce_reg [333] +1 1 +.names [368] [421] [334] +11 0 +.names i_rx_phy_rxd_s_reg [335] +1 1 +.names [364] [526] [336] +11 0 +.names [369] [213] [337] +00 1 +.names [365] [522] [674] [338] +111 0 +.names [364] [211] [466] [339] +111 0 +.names [418] [364] [340] +11 0 +.names [361] i_tx_phy_sft_done_reg_in +0 1 +.names [440] [598] [342] +11 0 +.names [588] \i_rx_phy_hold_reg_reg[7]_in [343] +11 0 +.names [402] [199] [344] +11 0 +.names [399] [404] i_tx_phy_txoe_r2_reg_in +00 1 +.names [368] [346] +0 1 +.names [397] [403] i_tx_phy_append_eop_sync4_reg_in +00 1 +.names [641] [271] [620] [348] +00- 1 +--0 1 +.names [594] i_rx_phy_rx_en_reg_in [395] [349] +11- 0 +--1 0 +.names [401] [503] [350] +11 0 +.names [401] [268] [351] +11 0 +.names [405] [295] rst [296] i_tx_phy_sd_nrzi_o_reg_in +1111 0 +.names [400] [516] usb_rst_reg_in +00 1 +.names [674] [417] rst [354] +111 0 +.names [389] [595] [355] +00 1 +.names [385] [356] +0 1 +.names [452] [453] [357] +11 0 +.names i_rx_phy_sd_r_reg [358] +1 1 +.names [445] [431] [438] \i_rx_phy_hold_reg_reg[7]_in [359] +11-- 0 +--11 0 +.names [411] [503] [412] [360] +00- 1 +--0 1 +.names [440] [508] [213] [468] [361] +1111 0 +.names i_rx_phy_fs_ce_r2_reg i_rx_phy_fs_ce_reg_in +1 1 +.names [372] [627] [363] +11 1 +.names [413] [600] [364] +00 1 +.names [389] [365] +0 1 +.names [540] [535] [366] +11 0 +.names [434] [533] [367] +11 0 +.names [655] [627] [368] +11 1 +.names [485] [498] [419] [369] +11- 0 +--1 0 +.names [489] [462] [416] [370] +00- 1 +--0 1 +.names [425] [200] [371] +11 0 +.names i_tx_phy_data_done_reg [372] +1 1 +.names [425] [504] [373] +11 0 +.names [588] [374] +0 1 +.names [422] [524] [375] +00 0 +.names [422] [524] [376] +11 0 +.names [425] [505] [377] +00 1 +.names [253] [598] [295] [595] [378] +11-- 0 +--11 0 +.names [214] [674] [297] [595] [379] +11-- 0 +--11 0 +.names [297] [598] [298] [596] [380] +11-- 0 +--11 0 +.names [295] [674] [296] [595] [381] +11-- 0 +--11 0 +.names [442] [492] [436] [382] +00- 1 +--0 1 +.names i_rx_phy_rxdn_s_r_reg [383] +0 1 +.names i_rx_phy_rxdp_s_r_reg [384] +0 1 +.names [409] rst [385] +11 0 +.names [455] [201] [386] +00 1 +.names [439] [457] [437] i_rx_phy_rxd_s_reg_in +00- 1 +--0 1 +.names [459] [463] [406] [388] +00- 1 +--0 1 +.names [440] [211] [389] +11 0 +.names i_rx_phy_rxdp_s_r_reg_in [390] +0 1 +.names [470] [271] [469] [391] +00- 1 +--0 1 +.names i_rx_phy_rxdn_s_r_reg_in [392] +0 1 +.names [636] [393] +0 1 +.names [666] [394] +0 1 +.names [303] [296] [596] [395] +000 1 +.names [546] [396] +0 1 +.names [317] [594] [503] [674] [397] +11-- 0 +--11 0 +.names i_rx_phy_rxd_r_reg_in [358] [594] i_rx_phy_sd_r_reg_in +01- 1 +1-1 1 +.names [303] [594] [296] [674] [399] +11-- 0 +--11 0 +.names [472] [474] [400] +11 0 +.names rst [600] [401] +11 1 +.names [434] [402] +0 1 +.names rst [403] +0 1 +.names rst [404] +0 1 +.names [454] [598] [316] [597] [405] +11-- 0 +--11 0 +.names [509] [485] [213] [406] +111 0 +.names i_rx_phy_rxdp_s1_reg_in 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[594] [134] [678] +11 0 +.names i_rx_phy_rx_en_reg_in txoe +1 1 +.names \i_rx_phy_hold_reg_reg[0]_in DataIn_o[1] +1 1 +.names \i_rx_phy_hold_reg_reg[1]_in DataIn_o[2] +1 1 +.names \i_rx_phy_hold_reg_reg[2]_in DataIn_o[3] +1 1 +.names \i_rx_phy_hold_reg_reg[3]_in DataIn_o[4] +1 1 +.names \i_rx_phy_hold_reg_reg[4]_in DataIn_o[5] +1 1 +.names \i_rx_phy_hold_reg_reg[5]_in DataIn_o[6] +1 1 +.names \i_rx_phy_hold_reg_reg[6]_in DataIn_o[7] +1 1 +.names rxd i_rx_phy_rxd_s0_reg_in +1 1 +.names rxdn i_rx_phy_rxdn_s0_reg_in +1 1 +.names rxdp i_rx_phy_rxdp_s0_reg_in +1 1 +.end diff --git a/fpga_flow/benchmarks/MCNC_big20/alu4.blif b/fpga_flow/benchmarks/MCNC_big20/alu4.blif new file mode 100644 index 000000000..a969985d8 --- /dev/null +++ b/fpga_flow/benchmarks/MCNC_big20/alu4.blif @@ -0,0 +1,2541 @@ +.model TOP +.inputs i_0_ i_1_ i_2_ i_3_ i_4_ i_5_ i_6_ i_7_ i_8_ i_9_ i_10_ i_11_ i_12_ \ +i_13_ +.outputs o_0_ o_1_ o_2_ o_3_ o_4_ o_5_ o_6_ o_7_ +.names n19 o_0_ +0 1 +.names n636 o_1_ +0 1 +.names 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+.names n407 n156 n725 +1- 1 +-1 1 +.names n335 n453 n531 n724 n728 +1--1 1 +-0-1 1 +--11 1 +.names n127 n297 n729 +1- 1 +-1 1 +.names i_7_ n204 n453 n730 +1-- 1 +-1- 1 +--0 1 +.names n275 n184 n186 n732 +1-- 1 +-1- 1 +--1 1 +.names n732 n403 n326 n731 +11- 1 +1-1 1 +.names n139 n441 n733 +1- 1 +-1 1 +.names n531 n184 n483 n734 +1-- 1 +-1- 1 +--1 1 +.names n687 n186 n427 n735 +11- 1 +1-1 1 +.names n439 n154 n179 n180 n736 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n528 n153 n275 n190 n737 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n531 n433 n149 n125 n738 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n319 n191 n740 +1- 1 +-1 1 +.names n552 n153 n741 +1- 1 +-1 1 +.names n514 n108 n740 n741 n739 +1111 1 +.names i_8_ n214 n483 n743 +1-- 1 +-1- 1 +--1 1 +.names n743 n199 n354 n399 n742 +11-- 1 +1-1- 1 +1--1 1 +.names i_3_ n442 n453 n742 n744 +1--1 1 +-1-1 1 +--01 1 +.names n194 n306 n535 n745 +1-- 1 +-0- 1 +--1 1 +.names n468 n411 n466 n200 n746 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n153 n510 n531 n543 n747 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n747 n416 n738 n737 n748 +11-- 1 +1-11 1 +.names i_0_ i_2_ i_7_ n323 n750 +0--- 1 +-0-- 1 +--0- 1 +---1 1 +.names n254 n46 n750 n366 n129 n40 n749 +111111 1 +.names n190 n306 n478 n595 n751 +10-- 1 +1-1- 1 +-0-1 1 +--11 1 +.names n481 n149 n752 +1- 1 +-1 1 +.names n354 n166 n550 n753 +1-- 1 +-1- 1 +--1 1 +.names n535 n399 n407 n190 n754 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n369 n269 n683 n755 +111 1 +.names i_4_ i_6_ n512 n756 +1-- 1 +-1- 1 +--1 1 +.names n173 n163 n700 n121 n741 n228 n757 +111111 1 +.names n142 n536 n194 n758 +11- 1 +1-1 1 +.names i_2_ i_5_ n762 n763 n759 +0--- 1 +-0-- 1 +--1- 1 +---1 1 +.names i_3_ n416 n578 n760 +1-- 1 +-1- 1 +--1 1 +.names n482 n568 n761 +1- 1 +-1 1 +.names i_1_ i_4_ n189 n762 +11- 1 +1-1 1 +.names i_1_ i_4_ n166 n763 +00- 1 +0-1 1 +.end diff --git a/fpga_flow/benchmarks/MCNC_big20/bigkey.blif b/fpga_flow/benchmarks/MCNC_big20/bigkey.blif new file mode 100644 index 000000000..aeae8a903 --- /dev/null +++ b/fpga_flow/benchmarks/MCNC_big20/bigkey.blif @@ -0,0 +1,5474 @@ +.model TOP +.inputs Pstart_0_ Pkey_255_ Pkey_254_ Pkey_253_ Pkey_252_ Pkey_251_ Pkey_250_ \ +Pkey_249_ Pkey_248_ Pkey_247_ Pkey_246_ Pkey_245_ Pkey_244_ Pkey_243_ \ +Pkey_242_ Pkey_241_ Pkey_240_ Pkey_239_ Pkey_238_ Pkey_237_ Pkey_236_ \ +Pkey_235_ Pkey_234_ Pkey_233_ Pkey_232_ Pkey_231_ Pkey_230_ Pkey_229_ \ +Pkey_228_ Pkey_227_ Pkey_226_ Pkey_225_ Pkey_224_ Pkey_223_ Pkey_222_ \ +Pkey_221_ Pkey_220_ Pkey_219_ Pkey_218_ Pkey_217_ Pkey_216_ Pkey_215_ \ +Pkey_214_ Pkey_213_ Pkey_212_ Pkey_211_ Pkey_210_ Pkey_209_ Pkey_208_ \ +Pkey_207_ Pkey_206_ Pkey_205_ Pkey_204_ Pkey_203_ Pkey_202_ Pkey_201_ \ +Pkey_200_ Pkey_199_ Pkey_198_ Pkey_197_ Pkey_196_ Pkey_195_ Pkey_194_ \ +Pkey_193_ Pkey_192_ Pkey_191_ Pkey_190_ Pkey_189_ Pkey_188_ Pkey_187_ \ +Pkey_186_ Pkey_185_ Pkey_184_ Pkey_183_ Pkey_182_ Pkey_181_ Pkey_180_ \ +Pkey_179_ Pkey_178_ Pkey_177_ Pkey_176_ Pkey_175_ Pkey_174_ Pkey_173_ \ +Pkey_172_ Pkey_171_ Pkey_170_ Pkey_169_ Pkey_168_ Pkey_167_ Pkey_166_ \ +Pkey_165_ Pkey_164_ Pkey_163_ Pkey_162_ Pkey_161_ Pkey_160_ Pkey_159_ \ +Pkey_158_ Pkey_157_ Pkey_156_ Pkey_155_ Pkey_154_ Pkey_153_ Pkey_152_ \ +Pkey_151_ Pkey_150_ Pkey_149_ Pkey_148_ Pkey_147_ Pkey_146_ Pkey_145_ \ +Pkey_144_ Pkey_143_ Pkey_142_ Pkey_141_ Pkey_140_ Pkey_139_ Pkey_138_ \ +Pkey_137_ Pkey_136_ Pkey_135_ Pkey_134_ Pkey_133_ Pkey_132_ Pkey_131_ \ +Pkey_130_ Pkey_129_ Pkey_128_ Pkey_127_ Pkey_126_ Pkey_125_ Pkey_124_ \ +Pkey_123_ Pkey_122_ Pkey_121_ Pkey_120_ Pkey_119_ Pkey_118_ Pkey_117_ \ +Pkey_116_ Pkey_115_ Pkey_114_ Pkey_113_ Pkey_112_ Pkey_111_ Pkey_110_ \ +Pkey_109_ Pkey_108_ Pkey_107_ Pkey_106_ Pkey_105_ Pkey_104_ Pkey_103_ \ +Pkey_102_ Pkey_101_ Pkey_100_ Pkey_99_ Pkey_98_ Pkey_97_ Pkey_96_ Pkey_95_ \ +Pkey_94_ Pkey_93_ Pkey_92_ Pkey_91_ Pkey_90_ Pkey_89_ Pkey_88_ Pkey_87_ \ +Pkey_86_ Pkey_85_ Pkey_84_ Pkey_83_ Pkey_82_ Pkey_81_ Pkey_80_ Pkey_79_ \ +Pkey_78_ Pkey_77_ Pkey_76_ Pkey_75_ Pkey_74_ Pkey_73_ Pkey_72_ Pkey_71_ \ +Pkey_70_ Pkey_69_ Pkey_68_ Pkey_67_ Pkey_66_ Pkey_65_ Pkey_64_ Pkey_63_ \ +Pkey_62_ Pkey_61_ Pkey_60_ Pkey_59_ Pkey_58_ Pkey_57_ Pkey_56_ Pkey_55_ \ +Pkey_54_ Pkey_53_ Pkey_52_ Pkey_51_ Pkey_50_ Pkey_49_ Pkey_48_ Pkey_47_ \ +Pkey_46_ Pkey_45_ Pkey_44_ Pkey_43_ Pkey_42_ Pkey_41_ Pkey_40_ Pkey_39_ \ +Pkey_38_ Pkey_37_ Pkey_36_ Pkey_35_ Pkey_34_ Pkey_33_ Pkey_32_ Pkey_31_ \ +Pkey_30_ Pkey_29_ Pkey_28_ Pkey_27_ Pkey_26_ Pkey_25_ Pkey_24_ Pkey_23_ \ +Pkey_22_ Pkey_21_ Pkey_20_ Pkey_19_ Pkey_18_ Pkey_17_ Pkey_16_ Pkey_15_ \ +Pkey_14_ Pkey_13_ Pkey_12_ Pkey_11_ Pkey_10_ Pkey_9_ Pkey_8_ Pkey_7_ Pkey_6_ \ +Pkey_5_ Pkey_4_ Pkey_3_ Pkey_2_ Pkey_1_ Pkey_0_ Pencrypt_0_ Pcount_3_ \ +Pcount_2_ Pcount_1_ Pcount_0_ PCLK +.outputs Pnew_count_3_ Pnew_count_2_ Pnew_count_1_ Pnew_count_0_ \ +Pdata_ready_0_ PKSi_191_ PKSi_190_ PKSi_189_ PKSi_188_ PKSi_187_ PKSi_186_ \ +PKSi_185_ PKSi_184_ PKSi_183_ PKSi_182_ PKSi_181_ PKSi_180_ PKSi_179_ \ +PKSi_178_ PKSi_177_ PKSi_176_ PKSi_175_ PKSi_174_ PKSi_173_ PKSi_172_ \ +PKSi_171_ PKSi_170_ PKSi_169_ PKSi_168_ PKSi_167_ PKSi_166_ PKSi_165_ \ +PKSi_164_ PKSi_163_ PKSi_162_ PKSi_161_ PKSi_160_ PKSi_159_ PKSi_158_ \ +PKSi_157_ PKSi_156_ PKSi_155_ PKSi_154_ PKSi_153_ PKSi_152_ PKSi_151_ \ +PKSi_150_ PKSi_149_ PKSi_148_ PKSi_147_ PKSi_146_ PKSi_145_ PKSi_144_ \ +PKSi_143_ PKSi_142_ PKSi_141_ PKSi_140_ PKSi_139_ PKSi_138_ PKSi_137_ \ +PKSi_136_ PKSi_135_ PKSi_134_ PKSi_133_ PKSi_132_ PKSi_131_ PKSi_130_ \ +PKSi_129_ PKSi_128_ PKSi_127_ PKSi_126_ PKSi_125_ PKSi_124_ PKSi_123_ \ +PKSi_122_ PKSi_121_ PKSi_120_ PKSi_119_ PKSi_118_ PKSi_117_ PKSi_116_ \ +PKSi_115_ PKSi_114_ PKSi_113_ PKSi_112_ PKSi_111_ PKSi_110_ PKSi_109_ \ +PKSi_108_ PKSi_107_ PKSi_106_ PKSi_105_ PKSi_104_ PKSi_103_ PKSi_102_ \ +PKSi_101_ PKSi_100_ PKSi_99_ PKSi_98_ PKSi_97_ PKSi_96_ PKSi_95_ PKSi_94_ \ +PKSi_93_ PKSi_92_ PKSi_91_ PKSi_90_ PKSi_89_ PKSi_88_ PKSi_87_ PKSi_86_ \ +PKSi_85_ PKSi_84_ PKSi_83_ PKSi_82_ PKSi_81_ PKSi_80_ PKSi_79_ PKSi_78_ \ +PKSi_77_ PKSi_76_ PKSi_75_ PKSi_74_ PKSi_73_ PKSi_72_ PKSi_71_ PKSi_70_ \ +PKSi_69_ PKSi_68_ PKSi_67_ PKSi_66_ PKSi_65_ PKSi_64_ PKSi_63_ PKSi_62_ \ +PKSi_61_ PKSi_60_ PKSi_59_ PKSi_58_ PKSi_57_ PKSi_56_ PKSi_55_ PKSi_54_ \ +PKSi_53_ PKSi_52_ PKSi_51_ PKSi_50_ PKSi_49_ PKSi_48_ PKSi_47_ PKSi_46_ \ +PKSi_45_ PKSi_44_ PKSi_43_ PKSi_42_ PKSi_41_ PKSi_40_ PKSi_39_ PKSi_38_ \ +PKSi_37_ PKSi_36_ PKSi_35_ PKSi_34_ PKSi_33_ PKSi_32_ PKSi_31_ PKSi_30_ \ +PKSi_29_ PKSi_28_ PKSi_27_ PKSi_26_ PKSi_25_ PKSi_24_ PKSi_23_ PKSi_22_ \ +PKSi_21_ PKSi_20_ PKSi_19_ PKSi_18_ PKSi_17_ PKSi_16_ PKSi_15_ PKSi_14_ \ +PKSi_13_ PKSi_12_ PKSi_11_ PKSi_10_ PKSi_9_ PKSi_8_ PKSi_7_ PKSi_6_ PKSi_5_ \ +PKSi_4_ PKSi_3_ PKSi_2_ PKSi_1_ PKSi_0_ +.latch N_N2733 PKSi_79_ re PCLK 2 +.latch N_N2734 PKSi_92_ re PCLK 2 +.latch N_N2735 [333] re PCLK 2 +.latch N_N2736 N_N2737 re PCLK 2 +.latch N_N2738 PKSi_75_ re PCLK 2 +.latch N_N2739 PKSi_84_ re PCLK 2 +.latch N_N2740 N_N2741 re PCLK 2 +.latch N_N2742 PKSi_82_ re PCLK 2 +.latch N_N2743 PKSi_93_ re PCLK 2 +.latch N_N2744 PKSi_85_ re PCLK 2 +.latch N_N2745 N_N2746 re PCLK 2 +.latch N_N2747 PKSi_73_ re PCLK 2 +.latch N_N2748 N_N2749 re PCLK 2 +.latch N_N2750 PKSi_80_ re PCLK 2 +.latch N_N2751 PKSi_72_ re PCLK 2 +.latch N_N2752 PKSi_94_ re PCLK 2 +.latch N_N2753 PKSi_86_ re PCLK 2 +.latch N_N2754 PKSi_74_ re PCLK 2 +.latch N_N2755 PKSi_83_ re PCLK 2 +.latch N_N2756 N_N2757 re PCLK 2 +.latch N_N2758 PKSi_89_ re PCLK 2 +.latch N_N2759 PKSi_91_ re PCLK 2 +.latch N_N2760 PKSi_81_ re PCLK 2 +.latch N_N2761 PKSi_77_ re PCLK 2 +.latch N_N2762 PKSi_87_ re PCLK 2 +.latch N_N2763 PKSi_78_ re PCLK 2 +.latch N_N2764 PKSi_95_ re PCLK 2 +.latch N_N2765 PKSi_76_ re PCLK 2 +.latch N_N2766 PKSi_55_ re PCLK 2 +.latch N_N2767 PKSi_68_ re PCLK 2 +.latch N_N2768 PKSi_64_ re PCLK 2 +.latch N_N2769 N_N2770 re PCLK 2 +.latch N_N2771 PKSi_51_ re PCLK 2 +.latch N_N2772 PKSi_60_ re PCLK 2 +.latch N_N2773 N_N2774 re PCLK 2 +.latch N_N2775 PKSi_58_ re PCLK 2 +.latch N_N2776 PKSi_69_ re PCLK 2 +.latch N_N2777 PKSi_61_ re PCLK 2 +.latch N_N2778 N_N2779 re PCLK 2 +.latch N_N2780 PKSi_49_ re PCLK 2 +.latch N_N2781 PKSi_66_ re PCLK 2 +.latch N_N2782 PKSi_56_ re PCLK 2 +.latch N_N2783 PKSi_48_ re PCLK 2 +.latch N_N2784 PKSi_70_ re PCLK 2 +.latch N_N2785 PKSi_62_ re PCLK 2 +.latch N_N2786 PKSi_50_ re PCLK 2 +.latch N_N2787 PKSi_59_ re PCLK 2 +.latch N_N2788 N_N2789 re PCLK 2 +.latch N_N2790 PKSi_65_ re PCLK 2 +.latch N_N2791 PKSi_67_ re PCLK 2 +.latch N_N2792 PKSi_57_ re PCLK 2 +.latch N_N2793 PKSi_53_ re PCLK 2 +.latch N_N2794 PKSi_63_ re PCLK 2 +.latch N_N2795 PKSi_54_ re PCLK 2 +.latch N_N2796 PKSi_71_ re PCLK 2 +.latch N_N2797 PKSi_52_ re PCLK 2 +.latch N_N2798 PKSi_31_ re PCLK 2 +.latch N_N2799 PKSi_44_ re PCLK 2 +.latch N_N2800 PKSi_40_ re PCLK 2 +.latch N_N2801 N_N2802 re PCLK 2 +.latch N_N2803 PKSi_27_ re PCLK 2 +.latch N_N2804 PKSi_36_ re PCLK 2 +.latch N_N2805 N_N2806 re PCLK 2 +.latch N_N2807 PKSi_34_ re PCLK 2 +.latch N_N2808 PKSi_45_ re PCLK 2 +.latch N_N2809 PKSi_37_ re PCLK 2 +.latch N_N2810 N_N2811 re PCLK 2 +.latch N_N2812 PKSi_25_ re PCLK 2 +.latch N_N2813 PKSi_42_ re PCLK 2 +.latch N_N2814 PKSi_32_ re PCLK 2 +.latch N_N2815 PKSi_24_ re PCLK 2 +.latch N_N2816 PKSi_46_ re PCLK 2 +.latch N_N2817 PKSi_38_ re PCLK 2 +.latch N_N2818 PKSi_26_ re PCLK 2 +.latch N_N2819 PKSi_35_ re PCLK 2 +.latch N_N2820 N_N2821 re PCLK 2 +.latch N_N2822 PKSi_41_ re PCLK 2 +.latch N_N2823 PKSi_43_ re PCLK 2 +.latch N_N2824 PKSi_33_ re PCLK 2 +.latch N_N2825 PKSi_29_ re PCLK 2 +.latch N_N2826 PKSi_39_ re PCLK 2 +.latch N_N2827 PKSi_30_ re PCLK 2 +.latch N_N2828 PKSi_47_ re PCLK 2 +.latch N_N2829 PKSi_28_ re PCLK 2 +.latch N_N2830 PKSi_7_ re PCLK 2 +.latch N_N2831 PKSi_20_ re PCLK 2 +.latch N_N2832 PKSi_16_ re PCLK 2 +.latch N_N2833 N_N2834 re PCLK 2 +.latch N_N2835 PKSi_3_ re PCLK 2 +.latch N_N2836 PKSi_12_ re PCLK 2 +.latch N_N2837 N_N2838 re PCLK 2 +.latch N_N2839 PKSi_10_ re PCLK 2 +.latch N_N2840 PKSi_21_ re PCLK 2 +.latch N_N2841 PKSi_13_ re PCLK 2 +.latch N_N2842 N_N2843 re PCLK 2 +.latch N_N2844 PKSi_1_ re PCLK 2 +.latch N_N2845 PKSi_18_ re PCLK 2 +.latch N_N2846 PKSi_8_ re PCLK 2 +.latch N_N2847 PKSi_0_ re PCLK 2 +.latch N_N2848 PKSi_22_ re PCLK 2 +.latch N_N2849 PKSi_14_ re PCLK 2 +.latch N_N2850 PKSi_2_ re PCLK 2 +.latch N_N2851 PKSi_11_ re PCLK 2 +.latch N_N2852 N_N2853 re PCLK 2 +.latch N_N2854 PKSi_17_ re PCLK 2 +.latch N_N2855 PKSi_19_ re PCLK 2 +.latch N_N2856 PKSi_9_ re PCLK 2 +.latch N_N2857 PKSi_5_ re PCLK 2 +.latch N_N2858 PKSi_15_ re PCLK 2 +.latch N_N2859 PKSi_6_ re PCLK 2 +.latch N_N2860 PKSi_23_ re PCLK 2 +.latch N_N2861 PKSi_4_ re PCLK 2 +.latch N_N2862 PKSi_183_ re PCLK 2 +.latch N_N2863 PKSi_173_ re PCLK 2 +.latch N_N2864 N_N2865 re PCLK 2 +.latch N_N2866 PKSi_185_ re PCLK 2 +.latch N_N2867 PKSi_169_ re PCLK 2 +.latch N_N2868 PKSi_176_ re PCLK 2 +.latch N_N2869 PKSi_188_ re PCLK 2 +.latch N_N2870 [253] re PCLK 2 +.latch N_N2871 PKSi_179_ re PCLK 2 +.latch N_N2872 PKSi_172_ re PCLK 2 +.latch N_N2873 PKSi_186_ re PCLK 2 +.latch N_N2874 PKSi_177_ re PCLK 2 +.latch N_N2875 PKSi_180_ re PCLK 2 +.latch N_N2876 N_N2877 re PCLK 2 +.latch N_N2878 N_N2879 re PCLK 2 +.latch N_N2880 N_N2881 re PCLK 2 +.latch N_N2882 PKSi_175_ re PCLK 2 +.latch N_N2883 PKSi_182_ re PCLK 2 +.latch N_N2884 N_N2885 re PCLK 2 +.latch N_N2886 PKSi_171_ re PCLK 2 +.latch N_N2887 PKSi_189_ re PCLK 2 +.latch N_N2888 N_N2889 re PCLK 2 +.latch N_N2890 PKSi_184_ re PCLK 2 +.latch N_N2891 PKSi_178_ re PCLK 2 +.latch N_N2892 [234] re PCLK 2 +.latch N_N2893 PKSi_170_ re PCLK 2 +.latch N_N2894 PKSi_174_ re PCLK 2 +.latch N_N2895 PKSi_190_ re PCLK 2 +.latch N_N2896 PKSi_159_ re PCLK 2 +.latch N_N2897 PKSi_149_ re PCLK 2 +.latch N_N2898 N_N2899 re PCLK 2 +.latch N_N2900 PKSi_161_ re PCLK 2 +.latch N_N2901 PKSi_145_ re PCLK 2 +.latch N_N2902 PKSi_152_ re PCLK 2 +.latch N_N2903 PKSi_164_ re PCLK 2 +.latch N_N2904 PKSi_157_ re PCLK 2 +.latch N_N2905 PKSi_155_ re PCLK 2 +.latch N_N2906 PKSi_148_ re PCLK 2 +.latch N_N2907 PKSi_162_ re PCLK 2 +.latch N_N2908 N_N2909 re PCLK 2 +.latch N_N2910 PKSi_156_ re PCLK 2 +.latch N_N2911 PKSi_153_ re PCLK 2 +.latch N_N2912 PKSi_163_ re PCLK 2 +.latch N_N2913 PKSi_144_ re PCLK 2 +.latch N_N2914 PKSi_151_ re PCLK 2 +.latch N_N2915 PKSi_158_ re PCLK 2 +.latch N_N2916 N_N2917 re PCLK 2 +.latch N_N2918 PKSi_147_ re PCLK 2 +.latch N_N2919 PKSi_165_ re PCLK 2 +.latch N_N2920 N_N2921 re PCLK 2 +.latch N_N2922 PKSi_160_ re PCLK 2 +.latch N_N2923 PKSi_154_ re PCLK 2 +.latch N_N2924 PKSi_167_ re PCLK 2 +.latch N_N2925 PKSi_146_ re PCLK 2 +.latch N_N2926 PKSi_150_ re PCLK 2 +.latch N_N2927 PKSi_166_ re PCLK 2 +.latch N_N2928 PKSi_135_ re PCLK 2 +.latch N_N2929 PKSi_125_ re PCLK 2 +.latch N_N2930 N_N2931 re PCLK 2 +.latch N_N2932 PKSi_137_ re PCLK 2 +.latch N_N2933 PKSi_121_ re PCLK 2 +.latch N_N2934 PKSi_128_ re PCLK 2 +.latch N_N2935 PKSi_140_ re PCLK 2 +.latch N_N2936 PKSi_133_ re PCLK 2 +.latch N_N2937 PKSi_131_ re PCLK 2 +.latch N_N2938 PKSi_124_ re PCLK 2 +.latch N_N2939 PKSi_138_ re PCLK 2 +.latch N_N2940 PKSi_129_ re PCLK 2 +.latch N_N2941 PKSi_132_ re PCLK 2 +.latch N_N2942 N_N2943 re PCLK 2 +.latch N_N2944 N_N2945 re PCLK 2 +.latch N_N2946 PKSi_120_ re PCLK 2 +.latch N_N2947 PKSi_127_ re PCLK 2 +.latch N_N2948 PKSi_134_ re PCLK 2 +.latch N_N2949 N_N2950 re PCLK 2 +.latch N_N2951 PKSi_123_ re PCLK 2 +.latch N_N2952 PKSi_141_ re PCLK 2 +.latch N_N2953 N_N2954 re PCLK 2 +.latch N_N2955 PKSi_136_ re PCLK 2 +.latch N_N2956 PKSi_130_ re PCLK 2 +.latch N_N2957 [282] re PCLK 2 +.latch N_N2958 PKSi_122_ re PCLK 2 +.latch N_N2959 PKSi_126_ re PCLK 2 +.latch N_N2960 PKSi_142_ re PCLK 2 +.latch N_N2961 PKSi_111_ re PCLK 2 +.latch N_N2962 PKSi_101_ re PCLK 2 +.latch N_N2963 N_N2964 re PCLK 2 +.latch N_N2965 PKSi_113_ re PCLK 2 +.latch N_N2966 PKSi_97_ re PCLK 2 +.latch N_N2967 PKSi_104_ re PCLK 2 +.latch N_N2968 PKSi_116_ re PCLK 2 +.latch N_N2969 PKSi_109_ re PCLK 2 +.latch N_N2970 PKSi_107_ re PCLK 2 +.latch N_N2971 PKSi_100_ re PCLK 2 +.latch N_N2972 PKSi_114_ re PCLK 2 +.latch N_N2973 PKSi_105_ re PCLK 2 +.latch N_N2974 PKSi_108_ re PCLK 2 +.latch N_N2975 N_N2976 re PCLK 2 +.latch N_N2977 PKSi_115_ re PCLK 2 +.latch N_N2978 PKSi_96_ re PCLK 2 +.latch N_N2979 PKSi_103_ re PCLK 2 +.latch N_N2980 PKSi_110_ re PCLK 2 +.latch N_N2981 N_N2982 re PCLK 2 +.latch N_N2983 PKSi_99_ re PCLK 2 +.latch N_N2984 PKSi_117_ re PCLK 2 +.latch N_N2985 N_N2986 re PCLK 2 +.latch N_N2987 PKSi_112_ re PCLK 2 +.latch N_N2988 PKSi_106_ re PCLK 2 +.latch N_N2989 PKSi_119_ re PCLK 2 +.latch N_N2990 PKSi_98_ re PCLK 2 +.latch N_N2991 PKSi_102_ re PCLK 2 +.latch N_N2992 PKSi_118_ re PCLK 2 +.names n17 Pnew_count_3_ +0 1 +.names n18 Pnew_count_2_ +0 1 +.names n19 Pnew_count_1_ +0 1 +.names n20 Pnew_count_0_ +0 1 +.names n16 Pdata_ready_0_ +0 1 +.names Pstart_0_ Pencrypt_0_ n15 +0- 1 +-1 1 +.names Pstart_0_ Pencrypt_0_ n13 +0- 1 +-0 1 +.names Pstart_0_ Pencrypt_0_ n245 n11 +1-- 1 +-1- 1 +--1 1 +.names Pstart_0_ Pencrypt_0_ n245 n1741 +001 1 +.names n925 Pstart_0_ n924 n16 +11- 1 +1-1 1 +.names Pstart_0_ n15 n937 n17 +11- 1 +-11 1 +.names Pencrypt_0_ n249 n930 n934 n18 +1-01 1 +-101 1 +.names Pcount_0_ n15 n929 n928 n19 +011- 1 +-111 1 +.names Pstart_0_ Pcount_0_ n15 n20 +1-1 1 +-11 1 +.names Pkey_62_ n13 n586 n587 n21 +0-11 1 +-111 1 +.names n21 N_N2862 +0 1 +.names Pkey_195_ n13 n583 n584 n22 +0-11 1 +-111 1 +.names n22 N_N2863 +0 1 +.names Pkey_203_ n13 n580 n581 n23 +0-11 1 +-111 1 +.names n23 N_N2864 +0 1 +.names Pkey_211_ n13 n577 n578 n24 +0-11 1 +-111 1 +.names n24 N_N2866 +0 1 +.names Pkey_219_ n13 n574 n575 n25 +0-11 1 +-111 1 +.names n25 N_N2867 +0 1 +.names Pkey_196_ n13 n571 n572 n26 +0-11 1 +-111 1 +.names n26 N_N2868 +0 1 +.names Pkey_204_ n13 n568 n569 n27 +0-11 1 +-111 1 +.names n27 N_N2869 +0 1 +.names Pkey_212_ n13 n565 n566 n28 +0-11 1 +-111 1 +.names n28 N_N2870 +0 1 +.names Pkey_220_ n13 n562 n563 n29 +0-11 1 +-111 1 +.names n29 N_N2871 +0 1 +.names Pkey_228_ n13 n559 n560 n30 +0-11 1 +-111 1 +.names n30 N_N2872 +0 1 +.names Pkey_172_ n13 n556 n557 n31 +0-11 1 +-111 1 +.names n31 N_N2873 +0 1 +.names Pkey_244_ n13 n554 n555 n32 +0-11 1 +-111 1 +.names n32 N_N2874 +0 1 +.names Pkey_252_ n13 n551 n552 n33 +0-11 1 +-111 1 +.names n33 N_N2875 +0 1 +.names Pkey_197_ n13 n548 n549 n34 +0-11 1 +-111 1 +.names n34 N_N2876 +0 1 +.names Pkey_205_ n13 n545 n546 n35 +0-11 1 +-111 1 +.names n35 N_N2878 +0 1 +.names Pkey_213_ n13 n542 n543 n36 +0-11 1 +-111 1 +.names n36 N_N2880 +0 1 +.names Pkey_221_ n13 n539 n540 n37 +0-11 1 +-111 1 +.names n37 N_N2882 +0 1 +.names Pkey_229_ n13 n536 n537 n38 +0-11 1 +-111 1 +.names n38 N_N2883 +0 1 +.names Pkey_237_ n13 n533 n534 n39 +0-11 1 +-111 1 +.names n39 N_N2884 +0 1 +.names Pkey_245_ n13 n530 n531 n40 +0-11 1 +-111 1 +.names n40 N_N2886 +0 1 +.names Pkey_253_ n13 n527 n528 n41 +0-11 1 +-111 1 +.names n41 N_N2887 +0 1 +.names Pkey_198_ n13 n524 n525 n42 +0-11 1 +-111 1 +.names n42 N_N2888 +0 1 +.names Pkey_206_ n13 n521 n522 n43 +0-11 1 +-111 1 +.names n43 N_N2890 +0 1 +.names Pkey_214_ n13 n518 n519 n44 +0-11 1 +-111 1 +.names n44 N_N2891 +0 1 +.names Pkey_222_ n13 n515 n516 n45 +0-11 1 +-111 1 +.names n45 N_N2892 +0 1 +.names Pkey_230_ n13 n512 n513 n46 +0-11 1 +-111 1 +.names n46 N_N2893 +0 1 +.names Pkey_238_ n13 n509 n510 n47 +0-11 1 +-111 1 +.names n47 N_N2894 +0 1 +.names Pkey_246_ n13 n506 n507 n48 +0-11 1 +-111 1 +.names n48 N_N2895 +0 1 +.names Pkey_254_ n13 n503 n504 n49 +0-11 1 +-111 1 +.names n49 N_N2896 +0 1 +.names Pkey_131_ n13 n500 n501 n50 +0-11 1 +-111 1 +.names n50 N_N2897 +0 1 +.names Pkey_139_ n13 n497 n498 n51 +0-11 1 +-111 1 +.names n51 N_N2898 +0 1 +.names Pkey_147_ n13 n494 n495 n52 +0-11 1 +-111 1 +.names n52 N_N2900 +0 1 +.names Pkey_155_ n13 n491 n492 n53 +0-11 1 +-111 1 +.names n53 N_N2901 +0 1 +.names Pkey_132_ n13 n488 n489 n54 +0-11 1 +-111 1 +.names n54 N_N2902 +0 1 +.names Pkey_140_ n13 n485 n486 n55 +0-11 1 +-111 1 +.names n55 N_N2903 +0 1 +.names Pkey_148_ n13 n482 n483 n56 +0-11 1 +-111 1 +.names n56 N_N2904 +0 1 +.names Pkey_156_ n13 n479 n480 n57 +0-11 1 +-111 1 +.names n57 N_N2905 +0 1 +.names Pkey_164_ n13 n476 n477 n58 +0-11 1 +-111 1 +.names n58 N_N2906 +0 1 +.names Pkey_172_ n13 n473 n474 n59 +0-11 1 +-111 1 +.names n59 N_N2907 +0 1 +.names Pkey_180_ n13 n470 n471 n60 +0-11 1 +-111 1 +.names n60 N_N2908 +0 1 +.names Pkey_188_ n13 n467 n468 n61 +0-11 1 +-111 1 +.names n61 N_N2910 +0 1 +.names Pkey_133_ n13 n464 n465 n62 +0-11 1 +-111 1 +.names n62 N_N2911 +0 1 +.names Pkey_141_ n13 n461 n462 n63 +0-11 1 +-111 1 +.names n63 N_N2912 +0 1 +.names Pkey_149_ n13 n458 n459 n64 +0-11 1 +-111 1 +.names n64 N_N2913 +0 1 +.names Pkey_157_ n13 n455 n456 n65 +0-11 1 +-111 1 +.names n65 N_N2914 +0 1 +.names Pkey_165_ n13 n452 n453 n66 +0-11 1 +-111 1 +.names n66 N_N2915 +0 1 +.names Pkey_173_ n13 n449 n450 n67 +0-11 1 +-111 1 +.names n67 N_N2916 +0 1 +.names Pkey_181_ n13 n446 n447 n68 +0-11 1 +-111 1 +.names n68 N_N2918 +0 1 +.names Pkey_189_ n13 n443 n444 n69 +0-11 1 +-111 1 +.names n69 N_N2919 +0 1 +.names Pkey_134_ n13 n440 n441 n70 +0-11 1 +-111 1 +.names n70 N_N2920 +0 1 +.names Pkey_142_ n13 n437 n438 n71 +0-11 1 +-111 1 +.names n71 N_N2922 +0 1 +.names Pkey_150_ n13 n434 n435 n72 +0-11 1 +-111 1 +.names n72 N_N2923 +0 1 +.names Pkey_158_ n13 n431 n432 n73 +0-11 1 +-111 1 +.names n73 N_N2924 +0 1 +.names Pkey_166_ n13 n428 n429 n74 +0-11 1 +-111 1 +.names n74 N_N2925 +0 1 +.names Pkey_174_ n13 n425 n426 n75 +0-11 1 +-111 1 +.names n75 N_N2926 +0 1 +.names Pkey_182_ n13 n422 n423 n76 +0-11 1 +-111 1 +.names n76 N_N2927 +0 1 +.names Pkey_190_ n13 n419 n420 n77 +0-11 1 +-111 1 +.names n77 N_N2928 +0 1 +.names Pkey_67_ n13 n416 n417 n78 +0-11 1 +-111 1 +.names n78 N_N2929 +0 1 +.names Pkey_75_ n13 n413 n414 n79 +0-11 1 +-111 1 +.names n79 N_N2930 +0 1 +.names Pkey_83_ n13 n410 n411 n80 +0-11 1 +-111 1 +.names n80 N_N2932 +0 1 +.names Pkey_91_ n13 n407 n408 n81 +0-11 1 +-111 1 +.names n81 N_N2933 +0 1 +.names Pkey_68_ n13 n404 n405 n82 +0-11 1 +-111 1 +.names n82 N_N2934 +0 1 +.names Pkey_76_ n13 n401 n402 n83 +0-11 1 +-111 1 +.names n83 N_N2935 +0 1 +.names Pkey_84_ n13 n398 n399 n84 +0-11 1 +-111 1 +.names n84 N_N2936 +0 1 +.names Pkey_92_ n13 n395 n396 n85 +0-11 1 +-111 1 +.names n85 N_N2937 +0 1 +.names Pkey_100_ n13 n392 n393 n86 +0-11 1 +-111 1 +.names n86 N_N2938 +0 1 +.names Pkey_44_ n13 n389 n390 n87 +0-11 1 +-111 1 +.names n87 N_N2939 +0 1 +.names Pkey_116_ n13 n387 n388 n88 +0-11 1 +-111 1 +.names n88 N_N2940 +0 1 +.names Pkey_124_ n13 n384 n385 n89 +0-11 1 +-111 1 +.names n89 N_N2941 +0 1 +.names Pkey_69_ n13 n381 n382 n90 +0-11 1 +-111 1 +.names n90 N_N2942 +0 1 +.names Pkey_77_ n13 n378 n379 n91 +0-11 1 +-111 1 +.names n91 N_N2944 +0 1 +.names Pkey_85_ n13 n375 n376 n92 +0-11 1 +-111 1 +.names n92 N_N2946 +0 1 +.names Pkey_93_ n13 n372 n373 n93 +0-11 1 +-111 1 +.names n93 N_N2947 +0 1 +.names Pkey_101_ n13 n369 n370 n94 +0-11 1 +-111 1 +.names n94 N_N2948 +0 1 +.names Pkey_109_ n13 n366 n367 n95 +0-11 1 +-111 1 +.names n95 N_N2949 +0 1 +.names Pkey_117_ n13 n363 n364 n96 +0-11 1 +-111 1 +.names n96 N_N2951 +0 1 +.names Pkey_125_ n13 n360 n361 n97 +0-11 1 +-111 1 +.names n97 N_N2952 +0 1 +.names Pkey_70_ n13 n357 n358 n98 +0-11 1 +-111 1 +.names n98 N_N2953 +0 1 +.names Pkey_78_ n13 n354 n355 n99 +0-11 1 +-111 1 +.names n99 N_N2955 +0 1 +.names Pkey_86_ n13 n351 n352 n100 +0-11 1 +-111 1 +.names n100 N_N2956 +0 1 +.names Pkey_94_ n13 n348 n349 n101 +0-11 1 +-111 1 +.names n101 N_N2957 +0 1 +.names Pkey_102_ n13 n345 n346 n102 +0-11 1 +-111 1 +.names n102 N_N2958 +0 1 +.names Pkey_110_ n13 n342 n343 n103 +0-11 1 +-111 1 +.names n103 N_N2959 +0 1 +.names Pkey_118_ n13 n339 n340 n104 +0-11 1 +-111 1 +.names n104 N_N2960 +0 1 +.names Pkey_126_ n13 n336 n337 n105 +0-11 1 +-111 1 +.names n105 N_N2961 +0 1 +.names Pkey_3_ n13 n333 n334 n106 +0-11 1 +-111 1 +.names n106 N_N2962 +0 1 +.names Pkey_11_ n13 n330 n331 n107 +0-11 1 +-111 1 +.names n107 N_N2963 +0 1 +.names Pkey_19_ n13 n327 n328 n108 +0-11 1 +-111 1 +.names n108 N_N2965 +0 1 +.names Pkey_27_ n13 n324 n325 n109 +0-11 1 +-111 1 +.names n109 N_N2966 +0 1 +.names Pkey_4_ n13 n321 n322 n110 +0-11 1 +-111 1 +.names n110 N_N2967 +0 1 +.names Pkey_12_ n13 n318 n319 n111 +0-11 1 +-111 1 +.names n111 N_N2968 +0 1 +.names Pkey_20_ n13 n315 n316 n112 +0-11 1 +-111 1 +.names n112 N_N2969 +0 1 +.names Pkey_28_ n13 n312 n313 n113 +0-11 1 +-111 1 +.names n113 N_N2970 +0 1 +.names Pkey_36_ n13 n309 n310 n114 +0-11 1 +-111 1 +.names n114 N_N2971 +0 1 +.names Pkey_44_ n13 n306 n307 n115 +0-11 1 +-111 1 +.names n115 N_N2972 +0 1 +.names Pkey_52_ n13 n303 n304 n116 +0-11 1 +-111 1 +.names n116 N_N2973 +0 1 +.names Pkey_60_ n13 n300 n301 n117 +0-11 1 +-111 1 +.names n117 N_N2974 +0 1 +.names Pkey_5_ n13 n297 n298 n118 +0-11 1 +-111 1 +.names n118 N_N2975 +0 1 +.names Pkey_13_ n13 n294 n295 n119 +0-11 1 +-111 1 +.names n119 N_N2977 +0 1 +.names Pkey_21_ n13 n291 n292 n120 +0-11 1 +-111 1 +.names n120 N_N2978 +0 1 +.names Pkey_29_ n13 n288 n289 n121 +0-11 1 +-111 1 +.names n121 N_N2979 +0 1 +.names Pkey_37_ n13 n285 n286 n122 +0-11 1 +-111 1 +.names n122 N_N2980 +0 1 +.names Pkey_45_ n13 n282 n283 n123 +0-11 1 +-111 1 +.names n123 N_N2981 +0 1 +.names Pkey_53_ n13 n279 n280 n124 +0-11 1 +-111 1 +.names n124 N_N2983 +0 1 +.names Pkey_61_ n13 n276 n277 n125 +0-11 1 +-111 1 +.names n125 N_N2984 +0 1 +.names Pkey_6_ n13 n273 n274 n126 +0-11 1 +-111 1 +.names n126 N_N2985 +0 1 +.names Pkey_14_ n13 n270 n271 n127 +0-11 1 +-111 1 +.names n127 N_N2987 +0 1 +.names Pkey_22_ n13 n267 n268 n128 +0-11 1 +-111 1 +.names n128 N_N2988 +0 1 +.names Pkey_30_ n13 n264 n265 n129 +0-11 1 +-111 1 +.names n129 N_N2989 +0 1 +.names Pkey_38_ n13 n261 n262 n130 +0-11 1 +-111 1 +.names n130 N_N2990 +0 1 +.names Pkey_46_ n13 n258 n259 n131 +0-11 1 +-111 1 +.names n131 N_N2991 +0 1 +.names Pkey_54_ n13 n255 n256 n132 +0-11 1 +-111 1 +.names n132 N_N2992 +0 1 +.names Pkey_56_ n13 n922 n923 n133 +0-11 1 +-111 1 +.names n133 N_N2733 +0 1 +.names Pkey_227_ n13 n919 n920 n134 +0-11 1 +-111 1 +.names n134 N_N2734 +0 1 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n842 n160 +0-11 1 +-111 1 +.names n160 N_N2765 +0 1 +.names Pkey_248_ n13 n838 n839 n161 +0-11 1 +-111 1 +.names n161 N_N2766 +0 1 +.names Pkey_163_ n13 n835 n836 n162 +0-11 1 +-111 1 +.names n162 N_N2767 +0 1 +.names Pkey_171_ n13 n832 n833 n163 +0-11 1 +-111 1 +.names n163 N_N2768 +0 1 +.names Pkey_179_ n13 n829 n830 n164 +0-11 1 +-111 1 +.names n164 N_N2769 +0 1 +.names Pkey_187_ n13 n826 n827 n165 +0-11 1 +-111 1 +.names n165 N_N2771 +0 1 +.names Pkey_130_ n13 n823 n824 n166 +0-11 1 +-111 1 +.names n166 N_N2772 +0 1 +.names Pkey_138_ n13 n820 n821 n167 +0-11 1 +-111 1 +.names n167 N_N2773 +0 1 +.names Pkey_146_ n13 n817 n818 n168 +0-11 1 +-111 1 +.names n168 N_N2775 +0 1 +.names Pkey_154_ n13 n814 n815 n169 +0-11 1 +-111 1 +.names n169 N_N2776 +0 1 +.names Pkey_162_ n13 n811 n812 n170 +0-11 1 +-111 1 +.names n170 N_N2777 +0 1 +.names Pkey_170_ n13 n808 n809 n171 +0-11 1 +-111 1 +.names n171 N_N2778 +0 1 +.names Pkey_178_ n13 n805 n806 n172 +0-11 1 +-111 1 +.names n172 N_N2780 +0 1 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n1166 N_N2802 n1394 n410 +0--1 1 +-1-1 1 +--01 1 +.names Pkey_91_ n15 n1395 n411 +0-1 1 +-11 1 +.names PKSi_40_ N_N2931 n1166 n1396 n413 +0--1 1 +-0-1 1 +--11 1 +.names Pkey_83_ n15 n1397 n414 +0-1 1 +-11 1 +.names PKSi_125_ PKSi_44_ n1166 n1398 n416 +0--1 1 +-0-1 1 +--11 1 +.names Pkey_75_ n15 n1399 n417 +0-1 1 +-11 1 +.names PKSi_135_ PKSi_31_ n1166 n1400 n419 +0--1 1 +-0-1 1 +--11 1 +.names Pkey_67_ n15 n1401 n420 +0-1 1 +-11 1 +.names PKSi_166_ PKSi_52_ n1166 n1402 n422 +0--1 1 +-0-1 1 +--11 1 +.names Pkey_190_ n15 n1403 n423 +0-1 1 +-11 1 +.names PKSi_150_ PKSi_71_ n1166 n1404 n425 +0--1 1 +-0-1 1 +--11 1 +.names Pkey_182_ n15 n1405 n426 +0-1 1 +-11 1 +.names PKSi_146_ PKSi_54_ n1166 n1406 n428 +0--1 1 +-0-1 1 +--11 1 +.names Pkey_174_ n15 n1407 n429 +0-1 1 +-11 1 +.names PKSi_167_ PKSi_63_ n1166 n1408 n431 +0--1 1 +-0-1 1 +--11 1 +.names Pkey_166_ n15 n1409 n432 +0-1 1 +-11 1 +.names PKSi_154_ PKSi_53_ n1166 n1410 n434 +0--1 1 +-0-1 1 +--11 1 +.names Pkey_158_ n15 n1411 n435 +0-1 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Pkey_149_ n15 n1429 n462 +0-1 1 +-11 1 +.names PKSi_153_ PKSi_56_ n1166 n1430 n464 +0--1 1 +-0-1 1 +--11 1 +.names Pkey_141_ n15 n1431 n465 +0-1 1 +-11 1 +.names PKSi_156_ PKSi_66_ n1166 n1432 n467 +0--1 1 +-0-1 1 +--11 1 +.names Pkey_133_ n15 n1433 n468 +0-1 1 +-11 1 +.names PKSi_49_ N_N2909 n1166 n1434 n470 +0--1 1 +-0-1 1 +--11 1 +.names Pkey_188_ n15 n1435 n471 +0-1 1 +-11 1 +.names PKSi_162_ n1166 N_N2779 n1436 n473 +0--1 1 +-1-1 1 +--01 1 +.names Pkey_180_ n15 n1437 n474 +0-1 1 +-11 1 +.names PKSi_148_ PKSi_61_ n1166 n1438 n476 +0--1 1 +-0-1 1 +--11 1 +.names Pkey_172_ n15 n1439 n477 +0-1 1 +-11 1 +.names PKSi_155_ PKSi_69_ n1166 n1440 n479 +0--1 1 +-0-1 1 +--11 1 +.names Pkey_164_ n15 n1441 n480 +0-1 1 +-11 1 +.names PKSi_157_ PKSi_58_ n1166 n1442 n482 +0--1 1 +-0-1 1 +--11 1 +.names Pkey_156_ n15 n1443 n483 +0-1 1 +-11 1 +.names PKSi_164_ n1166 N_N2774 n1444 n485 +0--1 1 +-1-1 1 +--01 1 +.names Pkey_148_ n15 n1445 n486 +0-1 1 +-11 1 +.names PKSi_152_ PKSi_60_ n1166 n1446 n488 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[234] PKSi_87_ n1166 n1464 n515 +0--1 1 +-0-1 1 +--11 1 +.names Pkey_230_ n15 n1465 n516 +0-1 1 +-11 1 +.names PKSi_178_ PKSi_77_ n1166 n1466 n518 +0--1 1 +-0-1 1 +--11 1 +.names Pkey_222_ n15 n1467 n519 +0-1 1 +-11 1 +.names PKSi_184_ PKSi_81_ n1166 n1468 n521 +0--1 1 +-0-1 1 +--11 1 +.names Pkey_214_ n15 n1469 n522 +0-1 1 +-11 1 +.names PKSi_91_ N_N2889 n1166 n1470 n524 +0--1 1 +-0-1 1 +--11 1 +.names Pkey_206_ n15 n1471 n525 +0-1 1 +-11 1 +.names PKSi_189_ PKSi_89_ n1166 n1472 n527 +0--1 1 +-0-1 1 +--11 1 +.names Pkey_198_ n15 n1473 n528 +0-1 1 +-11 1 +.names PKSi_171_ n1166 N_N2757 n1474 n530 +0--1 1 +-1-1 1 +--01 1 +.names Pkey_253_ n15 n1475 n531 +0-1 1 +-11 1 +.names PKSi_83_ N_N2885 n1166 n1476 n533 +0--1 1 +-0-1 1 +--11 1 +.names Pkey_245_ n15 n1477 n534 +0-1 1 +-11 1 +.names PKSi_182_ PKSi_74_ n1166 n1478 n536 +0--1 1 +-0-1 1 +--11 1 +.names Pkey_237_ n15 n1479 n537 +0-1 1 +-11 1 +.names PKSi_175_ PKSi_86_ n1166 n1480 n539 +0--1 1 +-0-1 1 +--11 1 +.names Pkey_229_ n15 n1481 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n1116 n1284 n1286 n1691 n853 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names Pkey_216_ n15 n1692 n854 +0-1 1 +-11 1 +.names n1118 n1284 n1286 n1693 n856 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names Pkey_208_ n15 n1694 n857 +0-1 1 +-11 1 +.names n1120 n1284 n1286 n1695 n859 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names Pkey_200_ n15 n1696 n860 +0-1 1 +-11 1 +.names n1122 n1284 n1286 n1697 n862 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names Pkey_192_ n15 n1698 n863 +0-1 1 +-11 1 +.names n1124 n1284 n1286 n1699 n865 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names Pkey_249_ n15 n1700 n866 +0-1 1 +-11 1 +.names n1126 n1284 n1286 n1701 n868 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names Pkey_241_ n15 n1702 n869 +0-1 1 +-11 1 +.names n1128 n1284 n1286 n1703 n871 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names Pkey_233_ n15 n1704 n872 +0-1 1 +-11 1 +.names n1130 n1284 n1286 n1705 n874 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names Pkey_225_ n15 n1706 n875 +0-1 1 +-11 1 +.names n1132 n1284 n1286 n1707 n877 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names Pkey_217_ n15 n1708 n878 +0-1 1 +-11 1 +.names n1134 n1284 n1286 n1709 n880 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names Pkey_209_ n15 n1710 n881 +0-1 1 +-11 1 +.names n1136 n1284 n1286 n1711 n883 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names Pkey_201_ n15 n1712 n884 +0-1 1 +-11 1 +.names n1138 n1284 n1286 n1713 n886 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names Pkey_193_ n15 n1714 n887 +0-1 1 +-11 1 +.names n1140 n1284 n1286 n1715 n889 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names Pkey_250_ n15 n1716 n890 +0-1 1 +-11 1 +.names n1142 n1284 n1286 n1717 n892 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names Pkey_242_ n15 n1718 n893 +0-1 1 +-11 1 +.names n1144 n1284 n1286 n1719 n895 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names Pkey_234_ n15 n1720 n896 +0-1 1 +-11 1 +.names n1146 n1284 n1286 n1721 n898 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names Pkey_226_ n15 n1722 n899 +0-1 1 +-11 1 +.names n1148 n1284 n1286 n1723 n901 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names Pkey_218_ n15 n1724 n902 +0-1 1 +-11 1 +.names n1150 n1284 n1286 n1725 n904 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names Pkey_210_ n15 n1726 n905 +0-1 1 +-11 1 +.names n1152 n1284 n1286 n1727 n907 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names Pkey_202_ n15 n1728 n908 +0-1 1 +-11 1 +.names n1154 n1284 n1286 n1729 n910 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names Pkey_194_ n15 n1730 n911 +0-1 1 +-11 1 +.names n1156 n1284 n1286 n1731 n913 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names Pkey_251_ n15 n1732 n914 +0-1 1 +-11 1 +.names n1158 n1284 n1286 n1733 n916 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names Pkey_243_ n15 n1734 n917 +0-1 1 +-11 1 +.names n1160 n1284 n1286 n1735 n919 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names Pkey_235_ n15 n1736 n920 +0-1 1 +-11 1 +.names n1162 n1284 n1286 n1737 n922 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names Pkey_227_ n15 n1738 n923 +0-1 1 +-11 1 +.names Pcount_3_ n246 n1287 n925 +0-- 1 +-1- 1 +--1 1 +.names Pcount_3_ Pencrypt_0_ n249 n924 +1-- 1 +-1- 1 +--1 1 +.names Pcount_1_ n1966 n1967 n929 +01- 1 +1-1 1 +-11 1 +.names Pencrypt_0_ Pcount_1_ n928 +1- 1 +-0 1 +.names Pcount_2_ n928 n1967 n930 +10- 1 +1-0 1 +.names Pstart_0_ Pcount_0_ n15 n1289 n934 +1-1- 1 +-01- 1 +--10 1 +.names Pcount_2_ Pcount_0_ n935 +00 1 +.names Pencrypt_0_ n252 n924 n939 +0-1 1 +-11 1 +.names Pencrypt_0_ n246 n935 n938 +10- 1 +0-1 1 +-01 1 +.names Pcount_3_ n928 n939 n938 n937 +0-1- 1 +-111 1 +.names PKSi_118_ PKSi_4_ n940 +11 1 +00 1 +.names PKSi_102_ PKSi_23_ n942 +11 1 +00 1 +.names PKSi_98_ PKSi_6_ n944 +11 1 +00 1 +.names PKSi_119_ PKSi_15_ n946 +11 1 +00 1 +.names PKSi_106_ PKSi_5_ n948 +11 1 +00 1 +.names PKSi_112_ PKSi_9_ n950 +11 1 +00 1 +.names PKSi_19_ N_N2986 n952 +11 1 +00 1 +.names PKSi_117_ PKSi_17_ n954 +11 1 +00 1 +.names PKSi_99_ N_N2853 n956 +11 1 +00 1 +.names PKSi_11_ N_N2982 n958 +11 1 +00 1 +.names PKSi_110_ PKSi_2_ n960 +11 1 +00 1 +.names PKSi_103_ PKSi_14_ n962 +11 1 +00 1 +.names PKSi_96_ PKSi_22_ n964 +11 1 +00 1 +.names PKSi_115_ PKSi_0_ n966 +11 1 +00 1 +.names PKSi_8_ N_N2976 n968 +11 1 +00 1 +.names PKSi_108_ PKSi_18_ n970 +11 1 +00 1 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1 +.names PKSi_127_ PKSi_38_ n1018 +11 1 +00 1 +.names PKSi_120_ PKSi_46_ n1020 +11 1 +00 1 +.names PKSi_24_ N_N2945 n1022 +11 1 +00 1 +.names PKSi_32_ N_N2943 n1024 +11 1 +00 1 +.names PKSi_132_ PKSi_42_ n1026 +11 1 +00 1 +.names PKSi_129_ PKSi_25_ n1028 +11 1 +00 1 +.names PKSi_138_ N_N2811 n1030 +11 1 +00 1 +.names PKSi_124_ PKSi_37_ n1032 +11 1 +00 1 +.names PKSi_131_ PKSi_45_ n1034 +11 1 +00 1 +.names PKSi_133_ PKSi_34_ n1036 +11 1 +00 1 +.names PKSi_140_ N_N2806 n1038 +11 1 +00 1 +.names PKSi_128_ PKSi_36_ n1040 +11 1 +00 1 +.names PKSi_121_ PKSi_27_ n1042 +11 1 +00 1 +.names PKSi_137_ N_N2802 n1044 +11 1 +00 1 +.names PKSi_40_ N_N2931 n1046 +11 1 +00 1 +.names PKSi_125_ PKSi_44_ n1048 +11 1 +00 1 +.names PKSi_135_ PKSi_31_ n1050 +11 1 +00 1 +.names PKSi_166_ PKSi_52_ n1052 +11 1 +00 1 +.names PKSi_150_ PKSi_71_ n1054 +11 1 +00 1 +.names PKSi_146_ PKSi_54_ n1056 +11 1 +00 1 +.names PKSi_167_ PKSi_63_ n1058 +11 1 +00 1 +.names PKSi_154_ PKSi_53_ n1060 +11 1 +00 1 +.names PKSi_160_ PKSi_57_ n1062 +11 1 +00 1 +.names PKSi_67_ N_N2921 n1064 +11 1 +00 1 +.names PKSi_165_ PKSi_65_ n1066 +11 1 +00 1 +.names PKSi_147_ N_N2789 n1068 +11 1 +00 1 +.names PKSi_59_ N_N2917 n1070 +11 1 +00 1 +.names PKSi_158_ PKSi_50_ n1072 +11 1 +00 1 +.names PKSi_151_ PKSi_62_ n1074 +11 1 +00 1 +.names PKSi_144_ PKSi_70_ n1076 +11 1 +00 1 +.names PKSi_163_ PKSi_48_ n1078 +11 1 +00 1 +.names PKSi_153_ PKSi_56_ n1080 +11 1 +00 1 +.names PKSi_156_ PKSi_66_ n1082 +11 1 +00 1 +.names PKSi_49_ N_N2909 n1084 +11 1 +00 1 +.names PKSi_162_ N_N2779 n1086 +11 1 +00 1 +.names PKSi_148_ PKSi_61_ n1088 +11 1 +00 1 +.names PKSi_155_ PKSi_69_ n1090 +11 1 +00 1 +.names PKSi_157_ PKSi_58_ n1092 +11 1 +00 1 +.names PKSi_164_ N_N2774 n1094 +11 1 +00 1 +.names PKSi_152_ PKSi_60_ n1096 +11 1 +00 1 +.names PKSi_145_ PKSi_51_ n1098 +11 1 +00 1 +.names PKSi_161_ N_N2770 n1100 +11 1 +00 1 +.names PKSi_64_ N_N2899 n1102 +11 1 +00 1 +.names PKSi_149_ PKSi_68_ n1104 +11 1 +00 1 +.names PKSi_159_ PKSi_55_ n1106 +11 1 +00 1 +.names PKSi_190_ PKSi_76_ n1108 +11 1 +00 1 +.names PKSi_174_ PKSi_95_ n1110 +11 1 +00 1 +.names PKSi_170_ PKSi_78_ n1112 +11 1 +00 1 +.names [234] PKSi_87_ n1114 +11 1 +00 1 +.names PKSi_178_ PKSi_77_ n1116 +11 1 +00 1 +.names PKSi_184_ PKSi_81_ n1118 +11 1 +00 1 +.names PKSi_91_ N_N2889 n1120 +11 1 +00 1 +.names PKSi_189_ PKSi_89_ n1122 +11 1 +00 1 +.names PKSi_171_ N_N2757 n1124 +11 1 +00 1 +.names PKSi_83_ N_N2885 n1126 +11 1 +00 1 +.names PKSi_182_ PKSi_74_ n1128 +11 1 +00 1 +.names PKSi_175_ PKSi_86_ n1130 +11 1 +00 1 +.names PKSi_94_ N_N2881 n1132 +11 1 +00 1 +.names PKSi_72_ N_N2879 n1134 +11 1 +00 1 +.names PKSi_80_ N_N2877 n1136 +11 1 +00 1 +.names PKSi_180_ N_N2749 n1138 +11 1 +00 1 +.names PKSi_177_ PKSi_73_ n1140 +11 1 +00 1 +.names PKSi_186_ N_N2746 n1142 +11 1 +00 1 +.names PKSi_172_ PKSi_85_ n1144 +11 1 +00 1 +.names PKSi_179_ PKSi_93_ n1146 +11 1 +00 1 +.names [253] PKSi_82_ n1148 +11 1 +00 1 +.names PKSi_188_ N_N2741 n1150 +11 1 +00 1 +.names PKSi_176_ PKSi_84_ n1152 +11 1 +00 1 +.names PKSi_169_ PKSi_75_ n1154 +11 1 +00 1 +.names PKSi_185_ N_N2737 n1156 +11 1 +00 1 +.names [333] N_N2865 n1158 +11 1 +00 1 +.names PKSi_173_ PKSi_92_ n1160 +11 1 +00 1 +.names PKSi_183_ PKSi_79_ n1162 +11 1 +00 1 +.names Pencrypt_0_ n250 n1167 +10 1 +.names Pstart_0_ n1167 n1166 +1- 1 +-1 1 +.names Pstart_0_ n1167 n1170 +1- 1 +-0 1 +.names Pencrypt_0_ n250 n1285 +0- 1 +-0 1 +.names Pstart_0_ n1285 n1284 +01 1 +.names Pstart_0_ n1285 n1286 +1- 1 +-1 1 +.names Pstart_0_ Pencrypt_0_ n1287 +1- 1 +-0 1 +.names Pencrypt_0_ Pcount_2_ Pcount_1_ n1968 n1289 +--01 1 +10-1 1 +.names n940 n1170 n1290 +1- 1 +-1 1 +.names n11 n1741 n1740 n1291 +10- 1 +1-1 1 +-00 1 +.names n942 n1170 n1292 +1- 1 +-1 1 +.names n11 n1741 n1744 n1293 +10- 1 +1-1 1 +-00 1 +.names n944 n1170 n1294 +1- 1 +-1 1 +.names n11 n1741 n1746 n1295 +10- 1 +1-1 1 +-00 1 +.names n946 n1170 n1296 +1- 1 +-1 1 +.names n11 n1741 n1748 n1297 +10- 1 +1-1 1 +-00 1 +.names n948 n1170 n1298 +1- 1 +-1 1 +.names n11 n1741 n1750 n1299 +10- 1 +1-1 1 +-00 1 +.names n950 n1170 n1300 +1- 1 +-1 1 +.names n11 n1741 n1752 n1301 +10- 1 +1-1 1 +-00 1 +.names n952 n1170 n1302 +1- 1 +-1 1 +.names n11 n1741 n1754 n1303 +10- 1 +1-1 1 +-00 1 +.names n954 n1170 n1304 +1- 1 +-1 1 +.names n11 n1741 n1756 n1305 +10- 1 +1-1 1 +-00 1 +.names n956 n1170 n1306 +1- 1 +-1 1 +.names n11 n1741 n1758 n1307 +10- 1 +1-1 1 +-00 1 +.names n958 n1170 n1308 +1- 1 +-1 1 +.names n11 n1741 n1760 n1309 +10- 1 +1-1 1 +-00 1 +.names n960 n1170 n1310 +1- 1 +-1 1 +.names n11 n1741 n1762 n1311 +10- 1 +1-1 1 +-00 1 +.names n962 n1170 n1312 +1- 1 +-1 1 +.names n11 n1741 n1764 n1313 +10- 1 +1-1 1 +-00 1 +.names n964 n1170 n1314 +1- 1 +-1 1 +.names n11 n1741 n1766 n1315 +10- 1 +1-1 1 +-00 1 +.names n966 n1170 n1316 +1- 1 +-1 1 +.names n11 n1741 n1768 n1317 +10- 1 +1-1 1 +-00 1 +.names n968 n1170 n1318 +1- 1 +-1 1 +.names n11 n1741 n1770 n1319 +10- 1 +1-1 1 +-00 1 +.names n970 n1170 n1320 +1- 1 +-1 1 +.names n11 n1741 n1772 n1321 +10- 1 +1-1 1 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n1876 n1650 +10- 1 +-01 1 +1-0 1 +.names PKSi_144_ PKSi_70_ n1651 +0- 1 +-0 1 +.names n11 n1741 n1878 n1652 +10- 1 +-01 1 +1-0 1 +.names PKSi_163_ PKSi_48_ n1653 +0- 1 +-0 1 +.names n11 n1741 n1880 n1654 +10- 1 +-01 1 +1-0 1 +.names PKSi_153_ PKSi_56_ n1655 +0- 1 +-0 1 +.names n11 n1741 n1882 n1656 +10- 1 +-01 1 +1-0 1 +.names PKSi_156_ PKSi_66_ n1657 +0- 1 +-0 1 +.names n11 n1741 n1884 n1658 +10- 1 +-01 1 +1-0 1 +.names PKSi_49_ N_N2909 n1659 +0- 1 +-0 1 +.names n11 n1741 n1886 n1660 +10- 1 +-01 1 +1-0 1 +.names PKSi_162_ N_N2779 n1661 +0- 1 +-0 1 +.names n11 n1741 n1888 n1662 +10- 1 +-01 1 +1-0 1 +.names PKSi_148_ PKSi_61_ n1663 +0- 1 +-0 1 +.names n11 n1741 n1890 n1664 +10- 1 +-01 1 +1-0 1 +.names PKSi_155_ PKSi_69_ n1665 +0- 1 +-0 1 +.names n11 n1741 n1892 n1666 +10- 1 +-01 1 +1-0 1 +.names PKSi_157_ PKSi_58_ n1667 +0- 1 +-0 1 +.names n11 n1741 n1894 n1668 +10- 1 +-01 1 +1-0 1 +.names PKSi_164_ N_N2774 n1669 +0- 1 +-0 1 +.names n11 n1741 n1896 n1670 +10- 1 +-01 1 +1-0 1 +.names PKSi_152_ PKSi_60_ n1671 +0- 1 +-0 1 +.names n11 n1741 n1898 n1672 +10- 1 +-01 1 +1-0 1 +.names PKSi_145_ PKSi_51_ n1673 +0- 1 +-0 1 +.names n11 n1741 n1900 n1674 +10- 1 +-01 1 +1-0 1 +.names PKSi_161_ N_N2770 n1675 +0- 1 +-0 1 +.names n11 n1741 n1902 n1676 +10- 1 +-01 1 +1-0 1 +.names PKSi_64_ N_N2899 n1677 +0- 1 +-0 1 +.names n11 n1741 n1904 n1678 +10- 1 +-01 1 +1-0 1 +.names PKSi_149_ PKSi_68_ n1679 +0- 1 +-0 1 +.names n11 n1741 n1906 n1680 +10- 1 +-01 1 +1-0 1 +.names PKSi_159_ PKSi_55_ n1681 +0- 1 +-0 1 +.names n11 n1741 n1908 n1682 +10- 1 +-01 1 +1-0 1 +.names PKSi_190_ PKSi_76_ n1683 +0- 1 +-0 1 +.names n11 n1741 n1910 n1684 +10- 1 +-01 1 +1-0 1 +.names PKSi_174_ PKSi_95_ n1685 +0- 1 +-0 1 +.names n11 n1741 n1912 n1686 +10- 1 +-01 1 +1-0 1 +.names PKSi_170_ PKSi_78_ n1687 +0- 1 +-0 1 +.names n11 n1741 n1914 n1688 +10- 1 +-01 1 +1-0 1 +.names [234] PKSi_87_ n1689 +0- 1 +-0 1 +.names n11 n1741 n1916 n1690 +10- 1 +-01 1 +1-0 1 +.names PKSi_178_ PKSi_77_ n1691 +0- 1 +-0 1 +.names n11 n1741 n1918 n1692 +10- 1 +-01 1 +1-0 1 +.names PKSi_184_ PKSi_81_ n1693 +0- 1 +-0 1 +.names n11 n1741 n1920 n1694 +10- 1 +-01 1 +1-0 1 +.names PKSi_91_ N_N2889 n1695 +0- 1 +-0 1 +.names n11 n1741 n1922 n1696 +10- 1 +-01 1 +1-0 1 +.names PKSi_189_ PKSi_89_ n1697 +0- 1 +-0 1 +.names n11 n1741 n1924 n1698 +10- 1 +-01 1 +1-0 1 +.names PKSi_171_ N_N2757 n1699 +0- 1 +-0 1 +.names n11 n1741 n1926 n1700 +10- 1 +-01 1 +1-0 1 +.names PKSi_83_ N_N2885 n1701 +0- 1 +-0 1 +.names n11 n1741 n1928 n1702 +10- 1 +-01 1 +1-0 1 +.names PKSi_182_ PKSi_74_ n1703 +0- 1 +-0 1 +.names n11 n1741 n1930 n1704 +10- 1 +-01 1 +1-0 1 +.names PKSi_175_ PKSi_86_ n1705 +0- 1 +-0 1 +.names n11 n1741 n1932 n1706 +10- 1 +-01 1 +1-0 1 +.names PKSi_94_ N_N2881 n1707 +0- 1 +-0 1 +.names n11 n1741 n1934 n1708 +10- 1 +-01 1 +1-0 1 +.names PKSi_72_ N_N2879 n1709 +0- 1 +-0 1 +.names n11 n1741 n1936 n1710 +10- 1 +-01 1 +1-0 1 +.names PKSi_80_ N_N2877 n1711 +0- 1 +-0 1 +.names n11 n1741 n1938 n1712 +10- 1 +-01 1 +1-0 1 +.names PKSi_180_ N_N2749 n1713 +0- 1 +-0 1 +.names n11 n1741 n1940 n1714 +10- 1 +-01 1 +1-0 1 +.names PKSi_177_ PKSi_73_ n1715 +0- 1 +-0 1 +.names n11 n1741 n1942 n1716 +10- 1 +-01 1 +1-0 1 +.names PKSi_186_ N_N2746 n1717 +0- 1 +-0 1 +.names n11 n1741 n1944 n1718 +10- 1 +-01 1 +1-0 1 +.names PKSi_172_ PKSi_85_ n1719 +0- 1 +-0 1 +.names n11 n1741 n1946 n1720 +10- 1 +-01 1 +1-0 1 +.names PKSi_179_ PKSi_93_ n1721 +0- 1 +-0 1 +.names n11 n1741 n1948 n1722 +10- 1 +-01 1 +1-0 1 +.names [253] PKSi_82_ n1723 +0- 1 +-0 1 +.names n11 n1741 n1950 n1724 +10- 1 +-01 1 +1-0 1 +.names PKSi_188_ N_N2741 n1725 +0- 1 +-0 1 +.names n11 n1741 n1952 n1726 +10- 1 +-01 1 +1-0 1 +.names PKSi_176_ PKSi_84_ n1727 +0- 1 +-0 1 +.names n11 n1741 n1954 n1728 +10- 1 +-01 1 +1-0 1 +.names PKSi_169_ PKSi_75_ n1729 +0- 1 +-0 1 +.names n11 n1741 n1956 n1730 +10- 1 +-01 1 +1-0 1 +.names PKSi_185_ N_N2737 n1731 +0- 1 +-0 1 +.names n11 n1741 n1958 n1732 +10- 1 +-01 1 +1-0 1 +.names [333] N_N2865 n1733 +0- 1 +-0 1 +.names n11 n1741 n1960 n1734 +10- 1 +-01 1 +1-0 1 +.names PKSi_173_ PKSi_92_ n1735 +0- 1 +-0 1 +.names n11 n1741 n1962 n1736 +10- 1 +-01 1 +1-0 1 +.names PKSi_183_ PKSi_79_ n1737 +0- 1 +-0 1 +.names n11 n1741 n1964 n1738 +10- 1 +-01 1 +1-0 1 +.names PKSi_4_ PKSi_118_ n1740 +1- 1 +-1 1 +.names PKSi_23_ PKSi_102_ n1744 +1- 1 +-1 1 +.names PKSi_6_ PKSi_98_ n1746 +1- 1 +-1 1 +.names PKSi_15_ PKSi_119_ n1748 +1- 1 +-1 1 +.names PKSi_5_ PKSi_106_ n1750 +1- 1 +-1 1 +.names PKSi_9_ PKSi_112_ n1752 +1- 1 +-1 1 +.names PKSi_19_ N_N2986 n1754 +1- 1 +-1 1 +.names PKSi_17_ PKSi_117_ n1756 +1- 1 +-1 1 +.names N_N2853 PKSi_99_ n1758 +1- 1 +-1 1 +.names PKSi_11_ N_N2982 n1760 +1- 1 +-1 1 +.names PKSi_2_ PKSi_110_ n1762 +1- 1 +-1 1 +.names PKSi_14_ PKSi_103_ n1764 +1- 1 +-1 1 +.names PKSi_22_ PKSi_96_ n1766 +1- 1 +-1 1 +.names PKSi_0_ PKSi_115_ n1768 +1- 1 +-1 1 +.names PKSi_8_ N_N2976 n1770 +1- 1 +-1 1 +.names PKSi_18_ PKSi_108_ n1772 +1- 1 +-1 1 +.names PKSi_1_ PKSi_105_ n1774 +1- 1 +-1 1 +.names N_N2843 PKSi_114_ n1776 +1- 1 +-1 1 +.names PKSi_13_ PKSi_100_ n1778 +1- 1 +-1 1 +.names PKSi_21_ PKSi_107_ n1780 +1- 1 +-1 1 +.names PKSi_10_ PKSi_109_ n1782 +1- 1 +-1 1 +.names N_N2838 PKSi_116_ n1784 +1- 1 +-1 1 +.names PKSi_12_ PKSi_104_ n1786 +1- 1 +-1 1 +.names PKSi_3_ PKSi_97_ n1788 +1- 1 +-1 1 +.names N_N2834 PKSi_113_ n1790 +1- 1 +-1 1 +.names PKSi_16_ N_N2964 n1792 +1- 1 +-1 1 +.names PKSi_20_ PKSi_101_ n1794 +1- 1 +-1 1 +.names PKSi_7_ PKSi_111_ n1796 +1- 1 +-1 1 +.names PKSi_28_ PKSi_142_ n1798 +1- 1 +-1 1 +.names PKSi_47_ PKSi_126_ n1800 +1- 1 +-1 1 +.names PKSi_30_ PKSi_122_ n1802 +1- 1 +-1 1 +.names PKSi_39_ [282] n1804 +1- 1 +-1 1 +.names PKSi_29_ PKSi_130_ n1806 +1- 1 +-1 1 +.names PKSi_33_ PKSi_136_ n1808 +1- 1 +-1 1 +.names PKSi_43_ N_N2954 n1810 +1- 1 +-1 1 +.names PKSi_41_ PKSi_141_ n1812 +1- 1 +-1 1 +.names N_N2821 PKSi_123_ n1814 +1- 1 +-1 1 +.names PKSi_35_ N_N2950 n1816 +1- 1 +-1 1 +.names PKSi_26_ PKSi_134_ n1818 +1- 1 +-1 1 +.names PKSi_38_ PKSi_127_ n1820 +1- 1 +-1 1 +.names PKSi_46_ PKSi_120_ n1822 +1- 1 +-1 1 +.names PKSi_24_ N_N2945 n1824 +1- 1 +-1 1 +.names PKSi_32_ N_N2943 n1826 +1- 1 +-1 1 +.names PKSi_42_ PKSi_132_ n1828 +1- 1 +-1 1 +.names PKSi_25_ PKSi_129_ n1830 +1- 1 +-1 1 +.names N_N2811 PKSi_138_ n1832 +1- 1 +-1 1 +.names PKSi_37_ PKSi_124_ n1834 +1- 1 +-1 1 +.names PKSi_45_ PKSi_131_ n1836 +1- 1 +-1 1 +.names PKSi_34_ PKSi_133_ n1838 +1- 1 +-1 1 +.names N_N2806 PKSi_140_ n1840 +1- 1 +-1 1 +.names PKSi_36_ PKSi_128_ n1842 +1- 1 +-1 1 +.names PKSi_27_ PKSi_121_ n1844 +1- 1 +-1 1 +.names N_N2802 PKSi_137_ n1846 +1- 1 +-1 1 +.names PKSi_40_ N_N2931 n1848 +1- 1 +-1 1 +.names PKSi_44_ PKSi_125_ n1850 +1- 1 +-1 1 +.names PKSi_31_ PKSi_135_ n1852 +1- 1 +-1 1 +.names PKSi_52_ PKSi_166_ n1854 +1- 1 +-1 1 +.names PKSi_71_ PKSi_150_ n1856 +1- 1 +-1 1 +.names PKSi_54_ PKSi_146_ n1858 +1- 1 +-1 1 +.names PKSi_63_ PKSi_167_ n1860 +1- 1 +-1 1 +.names PKSi_53_ PKSi_154_ n1862 +1- 1 +-1 1 +.names PKSi_57_ PKSi_160_ n1864 +1- 1 +-1 1 +.names PKSi_67_ N_N2921 n1866 +1- 1 +-1 1 +.names PKSi_65_ PKSi_165_ n1868 +1- 1 +-1 1 +.names N_N2789 PKSi_147_ n1870 +1- 1 +-1 1 +.names PKSi_59_ N_N2917 n1872 +1- 1 +-1 1 +.names PKSi_50_ PKSi_158_ n1874 +1- 1 +-1 1 +.names PKSi_62_ PKSi_151_ n1876 +1- 1 +-1 1 +.names PKSi_70_ PKSi_144_ n1878 +1- 1 +-1 1 +.names PKSi_48_ PKSi_163_ n1880 +1- 1 +-1 1 +.names PKSi_56_ PKSi_153_ n1882 +1- 1 +-1 1 +.names PKSi_66_ PKSi_156_ n1884 +1- 1 +-1 1 +.names PKSi_49_ N_N2909 n1886 +1- 1 +-1 1 +.names N_N2779 PKSi_162_ n1888 +1- 1 +-1 1 +.names PKSi_61_ PKSi_148_ n1890 +1- 1 +-1 1 +.names PKSi_69_ PKSi_155_ n1892 +1- 1 +-1 1 +.names PKSi_58_ PKSi_157_ n1894 +1- 1 +-1 1 +.names N_N2774 PKSi_164_ n1896 +1- 1 +-1 1 +.names PKSi_60_ PKSi_152_ n1898 +1- 1 +-1 1 +.names PKSi_51_ PKSi_145_ n1900 +1- 1 +-1 1 +.names N_N2770 PKSi_161_ n1902 +1- 1 +-1 1 +.names PKSi_64_ N_N2899 n1904 +1- 1 +-1 1 +.names PKSi_68_ PKSi_149_ n1906 +1- 1 +-1 1 +.names PKSi_55_ PKSi_159_ n1908 +1- 1 +-1 1 +.names PKSi_76_ PKSi_190_ n1910 +1- 1 +-1 1 +.names PKSi_95_ PKSi_174_ n1912 +1- 1 +-1 1 +.names PKSi_78_ PKSi_170_ n1914 +1- 1 +-1 1 +.names PKSi_87_ [234] n1916 +1- 1 +-1 1 +.names PKSi_77_ PKSi_178_ n1918 +1- 1 +-1 1 +.names PKSi_81_ PKSi_184_ n1920 +1- 1 +-1 1 +.names PKSi_91_ N_N2889 n1922 +1- 1 +-1 1 +.names PKSi_89_ PKSi_189_ n1924 +1- 1 +-1 1 +.names N_N2757 PKSi_171_ n1926 +1- 1 +-1 1 +.names PKSi_83_ N_N2885 n1928 +1- 1 +-1 1 +.names PKSi_74_ PKSi_182_ n1930 +1- 1 +-1 1 +.names PKSi_86_ PKSi_175_ n1932 +1- 1 +-1 1 +.names PKSi_94_ N_N2881 n1934 +1- 1 +-1 1 +.names PKSi_72_ N_N2879 n1936 +1- 1 +-1 1 +.names PKSi_80_ N_N2877 n1938 +1- 1 +-1 1 +.names N_N2749 PKSi_180_ n1940 +1- 1 +-1 1 +.names PKSi_73_ PKSi_177_ n1942 +1- 1 +-1 1 +.names N_N2746 PKSi_186_ n1944 +1- 1 +-1 1 +.names PKSi_85_ PKSi_172_ n1946 +1- 1 +-1 1 +.names PKSi_93_ PKSi_179_ n1948 +1- 1 +-1 1 +.names PKSi_82_ [253] n1950 +1- 1 +-1 1 +.names N_N2741 PKSi_188_ n1952 +1- 1 +-1 1 +.names PKSi_84_ PKSi_176_ n1954 +1- 1 +-1 1 +.names PKSi_75_ PKSi_169_ n1956 +1- 1 +-1 1 +.names N_N2737 PKSi_185_ n1958 +1- 1 +-1 1 +.names [333] N_N2865 n1960 +1- 1 +-1 1 +.names PKSi_92_ PKSi_173_ n1962 +1- 1 +-1 1 +.names PKSi_79_ PKSi_183_ n1964 +1- 1 +-1 1 +.names Pencrypt_0_ Pcount_0_ n1287 n1966 +10- 1 +1-1 1 +-11 1 +.names Pcount_0_ n1287 n1967 +1- 1 +-1 1 +.names Pcount_1_ Pcount_2_ n1968 +1- 1 +-1 1 +.names [234] PKSi_191_ +1 1 +.names [234] PKSi_187_ +1 1 +.names [253] PKSi_181_ +1 1 +.names [253] PKSi_168_ +1 1 +.names [282] PKSi_143_ +1 1 +.names [282] PKSi_139_ +1 1 +.names [333] PKSi_90_ +1 1 +.names [333] PKSi_88_ +1 1 +.end diff --git a/fpga_flow/benchmarks/MCNC_big20/clma.blif b/fpga_flow/benchmarks/MCNC_big20/clma.blif new file mode 100644 index 000000000..6c51691e9 --- /dev/null +++ b/fpga_flow/benchmarks/MCNC_big20/clma.blif @@ -0,0 +1,14167 @@ +.model TOP +.inputs Pi416 Pi415 Pi414 Pi413 Pi412 Pi411 Pi410 Pi409 Pi408 Pi407 Pi406 \ +Pi405 Pi404 Pi403 Pi402 Pi401 Pi400 Pi399 Pi398 Pi397 Pi396 Pi395 Pi394 Pi393 \ +Pi392 Pi391 Pi390 Pi389 Pi388 Pi387 Pi386 Pi385 Pi384 Pi383 Pi382 Pi381 Pi380 \ +Pi379 Pi378 Pi377 Pi376 Pi375 Pi374 Pi373 Pi372 Pi371 Pi370 Pi369 Pi368 Pi367 \ +Pi366 Pi365 Pi364 Pi363 Pi362 Pi361 Pi360 Pi359 Pi358 Pi357 Pi356 Pi355 Pi354 \ +Pi353 Pi352 Pi351 Pi350 Pi349 Pi348 Pi347 Pi346 Pi345 Pi344 Pi343 Pi342 Pi341 \ +Pi340 Pi339 Pi338 Pi337 Pi336 Pi335 Pi334 Pi333 Pi332 Pi331 Pi330 Pi329 Pi328 \ +Pi327 Pi326 Pi325 Pi324 Pi323 Pi322 Pi321 Pi320 Pi319 Pi318 Pi317 Pi316 Pi315 \ +Pi314 Pi313 Pi312 Pi311 Pi310 Pi309 Pi308 Pi307 Pi306 Pi305 Pi304 Pi303 Pi302 \ +Pi301 Pi300 Pi299 Pi298 Pi297 Pi296 Pi295 Pi294 Pi293 Pi292 Pi291 Pi290 Pi289 \ +Pi288 Pi287 Pi286 Pi285 Pi284 Pi283 Pi282 Pi281 Pi280 Pi279 Pi278 Pi277 Pi276 \ +Pi275 Pi274 Pi273 Pi272 Pi271 Pi270 Pi269 Pi268 Pi267 Pi266 Pi265 Pi264 Pi263 \ +Pi262 Pi261 Pi260 Pi259 Pi258 Pi257 Pi256 Pi255 Pi254 Pi253 Pi252 Pi251 Pi250 \ +Pi249 Pi248 Pi247 Pi246 Pi245 Pi244 Pi243 Pi242 Pi241 Pi240 Pi239 Pi238 Pi237 \ +Pi236 Pi235 Pi234 Pi233 Pi232 Pi231 Pi230 Pi229 Pi228 Pi227 Pi226 Pi225 Pi224 \ +Pi223 Pi222 Pi221 Pi220 Pi219 Pi218 Pi217 Pi216 Pi215 Pi214 Pi213 Pi212 Pi211 \ +Pi210 Pi209 Pi208 Pi207 Pi206 Pi205 Pi204 Pi203 Pi202 Pi201 Pi200 Pi199 Pi198 \ +Pi197 Pi196 Pi195 Pi194 Pi193 Pi192 Pi191 Pi190 Pi189 Pi188 Pi187 Pi186 Pi185 \ +Pi184 Pi183 Pi182 Pi181 Pi180 Pi179 Pi178 Pi177 Pi176 Pi175 Pi174 Pi173 Pi172 \ +Pi171 Pi170 Pi169 Pi168 Pi167 Pi166 Pi165 Pi164 Pi163 Pi162 Pi161 Pi160 Pi159 \ +Pi158 Pi157 Pi156 Pi155 Pi154 Pi153 Pi152 Pi151 Pi150 Pi149 Pi148 Pi147 Pi146 \ +Pi145 Pi144 Pi143 Pi142 Pi141 Pi140 Pi139 Pi138 Pi137 Pi136 Pi135 Pi134 Pi133 \ +Pi132 Pi131 Pi130 Pi129 Pi128 Pi127 Pi126 Pi125 Pi124 Pi123 Pi122 Pi121 Pi120 \ +Pi119 Pi118 Pi117 Pi116 Pi115 Pi114 Pi113 Pi112 Pi111 Pi110 Pi109 Pi108 Pi107 \ +Pi106 Pi105 Pi104 Pi103 Pi102 Pi101 Pi100 Pi99 Pi98 Pi97 Pi96 Pi95 Pi94 Pi93 \ +Pi92 Pi91 Pi90 Pi89 Pi88 Pi87 Pi86 Pi85 Pi84 Pi83 Pi82 Pi81 Pi80 Pi79 Pi78 \ +Pi77 Pi76 Pi75 Pi74 Pi73 Pi72 Pi71 Pi70 Pi69 Pi68 Pi67 Pi66 Pi65 Pi64 Pi63 \ +Pi62 Pi61 Pi60 Pi59 Pi58 Pi57 Pi56 Pi55 Pi54 Pi53 Pi52 Pi51 Pi50 Pi49 Pi28 \ +Pi27 Pi26 Pi25 Pi24 Pi23 Pi22 Pi21 Pi20 Pi19 Pi18 Pi17 Pi16 Pi15 PCLK +.outputs P__cmxir_1 P__cmxir_0 P__cmxig_1 P__cmxig_0 P__cmxcl_1 P__cmxcl_0 \ +P__cmx1ad_35 P__cmx1ad_34 P__cmx1ad_33 P__cmx1ad_32 P__cmx1ad_31 P__cmx1ad_30 \ +P__cmx1ad_29 P__cmx1ad_28 P__cmx1ad_27 P__cmx1ad_26 P__cmx1ad_25 P__cmx1ad_24 \ +P__cmx1ad_23 P__cmx1ad_22 P__cmx1ad_21 P__cmx1ad_20 P__cmx1ad_19 P__cmx1ad_18 \ +P__cmx1ad_17 P__cmx1ad_16 P__cmx1ad_15 P__cmx1ad_14 P__cmx1ad_13 P__cmx1ad_12 \ +P__cmx1ad_11 P__cmx1ad_10 P__cmx1ad_9 P__cmx1ad_8 P__cmx1ad_7 P__cmx1ad_6 \ +P__cmx1ad_5 P__cmx1ad_4 P__cmx1ad_3 P__cmx1ad_2 P__cmx1ad_1 P__cmx1ad_0 \ +P__cmx0ad_35 P__cmx0ad_34 P__cmx0ad_33 P__cmx0ad_32 P__cmx0ad_31 P__cmx0ad_30 \ +P__cmx0ad_29 P__cmx0ad_28 P__cmx0ad_27 P__cmx0ad_26 P__cmx0ad_25 P__cmx0ad_24 \ +P__cmx0ad_23 P__cmx0ad_22 P__cmx0ad_21 P__cmx0ad_20 P__cmx0ad_19 P__cmx0ad_18 \ +P__cmx0ad_17 P__cmx0ad_16 P__cmx0ad_15 P__cmx0ad_14 P__cmx0ad_13 P__cmx0ad_12 \ +P__cmx0ad_11 P__cmx0ad_10 P__cmx0ad_9 P__cmx0ad_8 P__cmx0ad_7 P__cmx0ad_6 \ +P__cmx0ad_5 P__cmx0ad_4 P__cmx0ad_3 P__cmx0ad_2 P__cmx0ad_1 P__cmx0ad_0 \ +P__cmnxcp_1 P__cmnxcp_0 P__cmndst1p0 P__cmndst0p0 +.latch Nv2 Ni48 re PCLK 2 +.latch Nv14 Ni47 re PCLK 2 +.latch Nv31 Ni46 re PCLK 2 +.latch Nv43 Ni45 re PCLK 2 +.latch Nv59 Ni44 re PCLK 2 +.latch N_N13960 Ni43 re PCLK 2 +.latch N_N13959 Ni42 re PCLK 2 +.latch Nv243 Ni41 re PCLK 2 +.latch Nv294 Ni40 re PCLK 2 +.latch Nv345 Ni39 re PCLK 2 +.latch Nv349 Ni38 re PCLK 2 +.latch Nv437 Ni37 re PCLK 2 +.latch Nv499 Ni36 re PCLK 2 +.latch Nv550 Ni35 re PCLK 2 +.latch Nv601 Ni34 re PCLK 2 +.latch Nv2153 Ni33 re PCLK 2 +.latch Nv3888 Ni32 re PCLK 2 +.latch Nv6425 Ni31 re PCLK 2 +.latch Nv6437 Ni30 re PCLK 2 +.latch Nv8909 n18 re PCLK 2 +.latch Nv10056 Ni14 re PCLK 2 +.latch Nv10068 Ni13 re PCLK 2 +.latch Nv10082 Ni12 re PCLK 2 +.latch Nv10091 Ni11 re PCLK 2 +.latch Nv10099 Ni10 re PCLK 2 +.latch Nv10112 Ni9 re PCLK 2 +.latch Nv10126 Ni8 re PCLK 2 +.latch Nv10135 Ni7 re PCLK 2 +.latch Nv10143 Ni6 re PCLK 2 +.latch Nv10247 Ni5 re PCLK 2 +.latch Nv10316 Ni4 re PCLK 2 +.latch P__cmxcl_0 Ni3 re PCLK 2 +.latch N_N13958 Ni2 re PCLK 2 +.names n157 n3113 n3540 P__cmxir_1 +100 1 +.names n138 n3476 P__cmxir_0 +00 1 +.names n157 P__cmxig_1 +0 1 +.names n3837 P__cmxig_0 +0 1 +.names n3540 P__cmxcl_1 +0 1 +.names n3540 P__cmxcl_0 +0 1 +.names P__cmx1ad_35 +.names P__cmx1ad_34 +.names P__cmx1ad_33 +.names P__cmx1ad_32 +.names Pi255 n3880 P__cmx1ad_31 +10 1 +.names Pi254 n3880 P__cmx1ad_30 +10 1 +.names Pi253 n3880 P__cmx1ad_29 +10 1 +.names Pi252 n3880 P__cmx1ad_28 +10 1 +.names Pi251 n3880 P__cmx1ad_27 +10 1 +.names Pi250 n3880 P__cmx1ad_26 +10 1 +.names Pi249 n3880 P__cmx1ad_25 +10 1 +.names Pi248 n3880 P__cmx1ad_24 +10 1 +.names Pi247 n3880 P__cmx1ad_23 +10 1 +.names Pi246 n3880 P__cmx1ad_22 +10 1 +.names Pi245 n3880 P__cmx1ad_21 +10 1 +.names Pi244 n3880 P__cmx1ad_20 +10 1 +.names Pi243 n3880 P__cmx1ad_19 +10 1 +.names Pi242 n3880 P__cmx1ad_18 +10 1 +.names Pi241 n3880 P__cmx1ad_17 +10 1 +.names Pi240 n3880 P__cmx1ad_16 +10 1 +.names Pi27 Pi26 n3880 P__cmx1ad_15 +110 1 +.names n3966 P__cmx1ad_14 +0 1 +.names n161 n3880 P__cmx1ad_13 +10 1 +.names n4813 P__cmx1ad_12 +0 1 +.names P__cmx1ad_11 +.names P__cmx1ad_10 +.names n3880 P__cmx1ad_9 +0 1 +.names P__cmx1ad_8 +.names Pi239 n3880 P__cmx1ad_7 +10 1 +.names Pi238 n3880 P__cmx1ad_6 +10 1 +.names Pi237 n3880 P__cmx1ad_5 +10 1 +.names Pi236 n3880 P__cmx1ad_4 +10 1 +.names Pi235 n3880 P__cmx1ad_3 +10 1 +.names Pi234 n3880 P__cmx1ad_2 +10 1 +.names Pi233 n3880 P__cmx1ad_1 +10 1 +.names Pi232 n3880 P__cmx1ad_0 +10 1 +.names P__cmx0ad_35 +.names P__cmx0ad_34 +.names P__cmx0ad_33 +.names P__cmx0ad_32 +.names Pi72 n3881 P__cmx0ad_31 +10 1 +.names Pi71 n3881 P__cmx0ad_30 +10 1 +.names Pi70 n3881 P__cmx0ad_29 +10 1 +.names Pi69 n3881 P__cmx0ad_28 +10 1 +.names Pi68 n3881 P__cmx0ad_27 +10 1 +.names Pi67 n3881 P__cmx0ad_26 +10 1 +.names Pi66 n3881 P__cmx0ad_25 +10 1 +.names Pi65 n3881 P__cmx0ad_24 +10 1 +.names Pi64 n3881 P__cmx0ad_23 +10 1 +.names Pi63 n3881 P__cmx0ad_22 +10 1 +.names Pi62 n3881 P__cmx0ad_21 +10 1 +.names Pi61 n3881 P__cmx0ad_20 +10 1 +.names Pi60 n3881 P__cmx0ad_19 +10 1 +.names Pi59 n3881 P__cmx0ad_18 +10 1 +.names Pi58 n3881 P__cmx0ad_17 +10 1 +.names Pi57 n3881 P__cmx0ad_16 +10 1 +.names Pi24 Pi23 n3881 P__cmx0ad_15 +110 1 +.names n3967 P__cmx0ad_14 +0 1 +.names n160 n3881 P__cmx0ad_13 +10 1 +.names n4815 P__cmx0ad_12 +0 1 +.names P__cmx0ad_11 +.names P__cmx0ad_10 +.names n3881 P__cmx0ad_9 +0 1 +.names P__cmx0ad_8 +.names Pi56 n3881 P__cmx0ad_7 +10 1 +.names Pi55 n3881 P__cmx0ad_6 +10 1 +.names Pi54 n3881 P__cmx0ad_5 +10 1 +.names Pi53 n3881 P__cmx0ad_4 +10 1 +.names Pi52 n3881 P__cmx0ad_3 +10 1 +.names Pi51 n3881 P__cmx0ad_2 +10 1 +.names Pi50 n3881 P__cmx0ad_1 +10 1 +.names Pi49 n3881 P__cmx0ad_0 +10 1 +.names n159 P__cmnxcp_1 +0 1 +.names n158 P__cmnxcp_0 +0 1 +.names n153 n3593 P__cmndst1p0 +10 1 +.names n150 n3879 P__cmndst0p0 +10 1 +.names Pi22 n3478 n3482 Ni48 n19 +-0-0 1 +001- 1 +.names n19 Nv2 +0 1 +.names Pi20 n299 n2947 n2946 n20 +101- 1 +-011 1 +.names Pi21 Ni32 n2065 Ni46 n21 +1--1 1 +-001 1 +.names n20 n21 Nv31 +1- 1 +-1 1 +.names Ni44 n3592 n3687 n22 +0-0 1 +-00 1 +.names n22 Nv59 +0 1 +.names Ni44 Ni39 n25 +11 1 +00 1 +.names n25 Ni38 n24 +11 1 +.names n25 Ni32 Ni37 n24 n23 +111- 1 +11-1 1 +.names n2040 n2954 Ni41 n26 +11- 1 +-10 1 +.names n26 Nv243 +0 1 +.names n2040 n2952 Ni40 n27 +11- 1 +-10 1 +.names n27 Nv294 +0 1 +.names n32 n2028 Ni39 n28 +11- 1 +-10 1 +.names n28 Nv345 +0 1 +.names n694 n2025 n2937 n3735 n29 +0-00 1 +-000 1 +.names n190 n400 n796 n2937 n30 +1-00 1 +-000 1 +.names Pi15 n107 n3879 n31 +100 1 +.names Ni32 n2055 n32 +01 1 +.names n2937 n2939 n3879 n34 +010 1 +.names n29 n30 n31 n32 n34 n4835 Nv349 +1----- 1 +-1---- 1 +--1--- 1 +---1-- 1 +----1- 1 +-----0 1 +.names Ni36 n2040 n2048 n2052 n35 +0-01 1 +-101 1 +.names n35 Nv499 +0 1 +.names Ni35 n2036 n2042 n2040 n36 +001- 1 +-011 1 +.names n36 Nv550 +0 1 +.names Ni34 n2016 n3540 n3657 n37 +00-0 1 +-000 1 +.names n37 Nv601 +0 1 +.names Ni44 n104 Ni42 n38 +0-0 1 +-00 1 +.names Ni44 n104 Ni42 n42 +1-0 1 +-00 1 +.names Ni47 Ni45 n44 +00 1 +.names Ni42 Ni43 n45 +0- 1 +-1 1 +.names n44 n45 n43 +11 1 +.names n3471 n3477 n3476 n3474 n46 +-11- 1 +01-1 1 +.names n46 Nv2153 +0 1 +.names n1653 n2932 n2936 n4391 n47 +001- 1 +-010 1 +.names n47 Nv3888 +0 1 +.names n43 n200 n1660 n3540 n48 +0-10 1 +-010 1 +.names Ni32 Ni30 n1866 n3540 n49 +0010 1 +.names n48 n49 Ni31 Nv6425 +1-- 1 +-1- 1 +--1 1 +.names Ni30 n1657 n1658 n3540 n50 +011- 1 +-110 1 +.names n50 Nv6437 +0 1 +.names n878 n879 n52 n877 n55 +111- 1 +11-1 1 +.names n4823 n79 n52 +11 1 +.names n200 Ni36 n53 +0- 1 +-0 1 +.names n55 n52 n53 n1063 n51 +11-0 1 +1-10 1 +.names n878 n879 n59 n882 n60 +111- 1 +11-1 1 +.names n4825 n79 n59 +11 1 +.names n53 n60 n59 n1063 n58 +11-0 1 +-110 1 +.names n62 n390 Ni38 n64 +11- 1 +-10 1 +.names n111 Ni35 n1063 n65 +1-0 1 +-00 1 +.names n52 n79 Ni40 n62 +11- 1 +-10 1 +.names Ni37 Ni36 n63 +1- 1 +-0 1 +.names n64 n65 n62 n63 n61 +111- 1 +11-1 1 +.names n67 n390 Ni38 n68 +11- 1 +-10 1 +.names n114 Ni35 n1063 n69 +1-0 1 +-00 1 +.names n59 n79 Ni40 n67 +11- 1 +-10 1 +.names n68 n69 n67 n63 n66 +111- 1 +11-1 1 +.names n71 n390 Ni38 n72 +11- 1 +-10 1 +.names Ni35 n116 n1063 n73 +1-0 1 +-10 1 +.names n79 Ni40 n52 n71 +11- 1 +1-1 1 +.names n72 n73 n71 n63 n70 +111- 1 +11-1 1 +.names n75 n390 Ni38 n76 +11- 1 +-10 1 +.names Ni35 n118 n1063 n77 +1-0 1 +-10 1 +.names n79 Ni40 n59 n75 +11- 1 +1-1 1 +.names n76 n77 n75 n63 n74 +111- 1 +11-1 1 +.names n79 n390 Ni38 n80 +11- 1 +-10 1 +.names n104 n835 Ni41 n79 +11- 1 +1-0 1 +.names n63 n80 n79 n1063 n78 +11-0 1 +-110 1 +.names n878 n879 n82 n877 n83 +111- 1 +11-1 1 +.names n104 n4823 n82 +11 1 +.names n53 n83 n82 n1063 n81 +11-0 1 +-110 1 +.names n878 n879 n85 n882 n86 +111- 1 +11-1 1 +.names n104 n4825 n85 +11 1 +.names n53 n86 n85 n1063 n84 +11-0 1 +-110 1 +.names n88 n390 Ni38 n89 +11- 1 +-10 1 +.names Ni35 n122 n1063 n90 +0-0 1 +-10 1 +.names n82 n104 Ni40 n88 +11- 1 +-10 1 +.names n89 n90 n88 n63 n87 +111- 1 +11-1 1 +.names n92 n390 Ni38 n93 +11- 1 +-10 1 +.names Ni35 n124 n1063 n94 +0-0 1 +-10 1 +.names n85 n104 Ni40 n92 +11- 1 +-10 1 +.names n93 n94 n92 n63 n91 +111- 1 +11-1 1 +.names n96 n390 Ni38 n97 +11- 1 +-10 1 +.names Ni35 n126 n1063 n98 +1-0 1 +-10 1 +.names n104 Ni40 n82 n96 +11- 1 +1-1 1 +.names n97 n98 n96 n63 n95 +111- 1 +11-1 1 +.names n100 n390 Ni38 n101 +11- 1 +-10 1 +.names Ni35 n128 n1063 n102 +1-0 1 +-10 1 +.names n104 Ni40 n85 n100 +11- 1 +1-1 1 +.names n101 n102 n100 n63 n99 +111- 1 +11-1 1 +.names n104 n390 Ni38 n105 +11- 1 +-10 1 +.names n44 Ni43 n104 +10 1 +.names n63 n105 n104 n1063 n103 +11-0 1 +-110 1 +.names n390 n1063 n108 +10 1 +.names Ni36 Ni38 n107 +0- 1 +-0 1 +.names n55 n108 n52 n107 n106 +111- 1 +11-1 1 +.names n60 n108 n59 n107 n109 +111- 1 +11-1 1 +.names n62 n202 n111 +1- 1 +-1 1 +.names n64 n111 Ni35 n1063 n110 +11-0 1 +1-00 1 +.names n67 n240 n114 +1- 1 +-1 1 +.names n68 n114 Ni35 n1063 n113 +11-0 1 +1-00 1 +.names n71 n202 n116 +1- 1 +-1 1 +.names n72 Ni35 n116 n1063 n115 +11-0 1 +1-10 1 +.names n75 n240 n118 +1- 1 +-1 1 +.names n76 Ni35 n118 n1063 n117 +11-0 1 +1-10 1 +.names n108 n83 n82 n107 n119 +111- 1 +11-1 1 +.names n108 n86 n85 n107 n120 +111- 1 +11-1 1 +.names n88 n202 n122 +1- 1 +-1 1 +.names n89 Ni35 n122 n1063 n121 +10-0 1 +1-10 1 +.names n92 n240 n124 +1- 1 +-1 1 +.names n93 Ni35 n124 n1063 n123 +10-0 1 +1-10 1 +.names n96 n202 n126 +1- 1 +-1 1 +.names n97 Ni35 n126 n1063 n125 +11-0 1 +1-10 1 +.names n100 n240 n128 +1- 1 +-1 1 +.names n101 Ni35 n128 n1063 n127 +11-0 1 +1-10 1 +.names Ni47 n320 n130 +1- 1 +-1 1 +.names Ni44 n130 Ni41 n129 +0-0 1 +-10 1 +.names Ni45 n320 n133 +1- 1 +-1 1 +.names Ni44 n133 Ni41 n132 +0-0 1 +-10 1 +.names Ni44 n130 Ni41 n134 +1-0 1 +-10 1 +.names Ni44 n133 Ni41 n135 +1-0 1 +-10 1 +.names Ni14 n3545 n3569 Ni2 n136 +0-0- 1 +-100 1 +.names n136 Nv10056 +0 1 +.names Ni13 n3540 n3564 n3568 n137 +0-1- 1 +-010 1 +.names n137 Nv10068 +0 1 +.names Pi25 Ni10 n140 +0- 1 +-1 1 +.names n140 Ni10 Ni9 n3837 n138 +100- 1 +1-00 1 +.names n3540 n3555 Ni9 n3844 n142 +-10- 1 +01-0 1 +.names n142 Nv10112 +0 1 +.names n2049 Ni8 n3540 n3549 n143 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names n143 Nv10126 +0 1 +.names Ni6 n3544 n3548 n4805 n144 +1-10 1 +-110 1 +.names n144 Nv10143 +0 1 +.names Ni6 n3488 n3705 n3876 n145 +100- 1 +1-00 1 +.names n3542 n3543 n2066 n3539 n149 +111- 1 +11-1 1 +.names n149 Nv10247 +0 1 +.names Ni37 Ni38 n150 +01 1 +.names Ni32 Ni30 n153 +0- 1 +-0 1 +.names n18 Ni33 n157 +0- 1 +-0 1 +.names n3615 n3616 n3611 n3540 n158 +111- 1 +11-1 1 +.names n3540 n3601 n3604 n3608 n159 +1-01 1 +-101 1 +.names Pi23 Pi24 n160 +1- 1 +-1 1 +.names Pi26 Pi27 n161 +1- 1 +-1 1 +.names n153 n3592 n3590 n3591 n162 +01-- 1 +-111 1 +.names n162 N_N13960 +0 1 +.names Ni34 Ni30 Ni32 Ni31 n163 +11-- 1 +1-1- 1 +1--1 1 +.names Pi21 n2328 n166 +0- 1 +-0 1 +.names n160 Ni30 n166 n953 n164 +111- 1 +-110 1 +.names Pi24 Pi23 n168 +1- 1 +-0 1 +.names Ni30 n166 n168 n953 n167 +111- 1 +11-0 1 +.names n3640 n3843 n3863 n171 +0-- 1 +-1- 1 +--1 1 +.names n171 n1471 n4827 n169 +10- 1 +-00 1 +.names n171 n1866 n3342 n4827 n173 +10-- 1 +-00- 1 +-0-0 1 +.names n3843 n3592 n177 +1- 1 +-1 1 +.names Ni32 Ni31 n178 +0- 1 +-0 1 +.names n177 n178 n176 +11 1 +.names n3666 n2083 n180 +11 1 +.names n180 Ni33 n2068 n179 +1-0 1 +-00 1 +.names n180 Ni33 n2068 n183 +1-0 1 +-10 1 +.names n23 Ni31 n153 n184 +0-0 1 +-10 1 +.names Pi20 n3060 n3869 n188 +01- 1 +-10 1 +.names Ni35 Ni30 n190 +00 1 +.names n171 n4827 n193 +1- 1 +-0 1 +.names Pi22 n193 n3342 n192 +11- 1 +1-0 1 +.names n2069 Ni45 n2068 n195 +11- 1 +1-1 1 +.names n178 n3687 n196 +10 1 +.names n195 n196 n194 +11 1 +.names Ni37 Ni38 n200 +0- 1 +-1 1 +.names n269 Ni40 n457 n198 +11- 1 +1-1 1 +.names Ni37 n200 n198 n197 +01- 1 +-11 1 +.names n2961 n3722 n202 +0- 1 +-1 1 +.names n43 n198 n202 n201 +11- 1 +1-1 1 +.names n43 n150 n198 n197 n203 +10-1 1 +1-11 1 +.names n198 n63 n203 n2087 n206 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n197 n206 Ni35 n201 n205 +111- 1 +11-1 1 +.names Ni37 n44 Ni36 n2961 n207 +0-1- 1 +01-0 1 +.names n510 n511 n212 +1- 1 +-1 1 +.names Ni36 n207 n210 +01 1 +.names Ni35 n2094 n211 +1- 1 +-1 1 +.names n212 n210 n211 n209 +11- 1 +1-1 1 +.names n272 Ni40 n463 n214 +11- 1 +1-1 1 +.names Ni37 n200 n214 n213 +01- 1 +-11 1 +.names n3718 n3724 n216 +1- 1 +-1 1 +.names n216 n213 n214 n202 n215 +111- 1 +11-1 1 +.names Ni38 n3718 n218 +1- 1 +-1 1 +.names n150 n214 n213 n218 n217 +0-11 1 +-111 1 +.names n214 n464 n213 n275 n220 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n217 n3726 n215 n397 n221 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n220 n221 n219 +11 1 +.names n278 Ni40 n470 n223 +11- 1 +1-1 1 +.names Ni37 n200 n223 n222 +01- 1 +-11 1 +.names n3749 n3724 n225 +1- 1 +-1 1 +.names n225 n222 n223 n202 n224 +111- 1 +11-1 1 +.names Ni38 n3749 n227 +1- 1 +-1 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1 +1--1 1 +-1-1 1 +.names n3358 n3763 n3374 n3774 n4652 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n3798 n1068 n4785 n4786 n4654 +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names n168 Ni10 n1654 n3492 n4657 +1--- 1 +-0-- 1 +--1- 1 +---1 1 +.names n3492 n3613 n3614 n4658 +1-- 1 +-1- 1 +--1 1 +.names Ni31 Ni30 Ni5 Ni4 n4659 +10-- 1 +1-0- 1 +1--1 1 +.names Pi15 n773 n781 n4665 +11- 1 +0-1 1 +-11 1 +.names Pi17 n758 n763 n4006 n4666 +01-- 1 +0-1- 1 +0--0 1 +.names Pi17 n4008 n4009 n4666 n4667 +0--0 1 +-110 1 +.names n3113 n4665 n4667 n4669 +11- 1 +0-1 1 +-11 1 +.names n3775 n4027 n4028 n4670 +011 1 +.names n1654 n3775 n4667 n4670 n4671 +0--1 1 +011- 1 +.names n1654 Ni7 n4669 n4671 n4672 +-0-1 1 +101- 1 +.names n3540 Ni7 n4669 n4672 n4673 +0--1 1 +011- 1 +.names n4186 n3650 Ni14 n4675 +111 1 +.names Ni14 n4100 n4101 n4676 +011 1 +.names n4108 n4107 Ni14 n4677 +111 1 +.names n848 n1053 n1505 n1508 n1511 n1514 n1517 n4068 n4678 +0------- 1 +-0------ 1 +--1----- 1 +---1---- 1 +----1--- 1 +-----1-- 1 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+.names Pi20 n4299 n4302 n4708 n4709 +1--0 1 +-110 1 +.names Pi15 n4287 n4706 n4711 +011 1 +.names n4317 n4709 Pi15 n4712 +111 1 +.names n4703 n4704 n3113 Ni10 n4713 +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names Pi17 n4326 n4328 n4714 +00- 1 +0-0 1 +.names n4332 n2024 n2031 n4716 +111 1 +.names Pi23 n2026 n2031 n3660 n4717 +--01 1 +010- 1 +.names n4333 n2043 n2031 n4718 +111 1 +.names Pi24 n2031 n2046 n3663 n4719 +-0-1 1 +001- 1 +.names Ni33 n275 n2031 n2046 n4720 +1-01 1 +-101 1 +.names Ni44 n3572 Ni42 Ni39 n4722 +00-0 1 +0-10 1 +.names Ni44 n320 Ni39 n4722 n4724 +0--0 1 +-0-0 1 +--00 1 +.names Pi21 n3674 n4730 +1- 1 +-1 1 +.names Pi26 n2327 n2329 n4733 +10- 1 +0-0 1 +-00 1 +.names Pi26 Pi21 Ni32 n2303 n4735 +-0-0 1 +001- 1 +.names Pi26 n2327 n2329 n4737 +00- 1 +1-0 1 +-00 1 +.names Ni14 n4405 n4406 n4738 +011 1 +.names n2070 n2377 n2782 n2785 n2788 n2791 n2794 n4372 n4740 +0------- 1 +-0------ 1 +--1----- 1 +---1---- 1 +----1--- 1 +-----1-- 1 +------1- 1 +-------0 1 +.names n2070 n2350 n2764 n2767 n2770 n2773 n2776 n4382 n4743 +0------- 1 +-0------ 1 +--1----- 1 +---1---- 1 +----1--- 1 +-----1-- 1 +------1- 1 +-------0 1 +.names n2632 n3792 n4747 +1- 1 +-1 1 +.names Pi15 n4440 n4443 n4446 n4447 n4747 n4746 +011111 1 +.names n2688 n3792 n4749 +1- 1 +-1 1 +.names n4460 n4749 n4463 n4467 n4466 Pi15 n4748 +111111 1 +.names Pi17 n4359 n4361 n4750 +10- 1 +1-0 1 +.names Pi17 n2070 n4384 n4385 n4752 +0111 1 +.names n4388 n2070 n4387 Pi17 n4753 +1111 1 +.names n4475 Ni10 Ni11 n2699 n4754 +111- 1 +11-1 1 +.names n2397 n2401 n2404 n4755 +1-- 1 +-1- 1 +--1 1 +.names Pi17 n4394 n4395 n4756 +011 1 +.names Pi20 n2937 Ni39 n3858 n4759 +01-1 1 +0-01 1 +.names n3858 Pi20 Ni39 n2937 n4760 +111- 1 +11-1 1 +.names n2031 Ni40 n4761 +0- 1 +-0 1 +.names n2031 n3686 n3925 n4763 +01- 1 +1-0 1 +-10 1 +.names n2031 Ni41 n4764 +0- 1 +-0 1 +.names n2031 n3692 n3931 n4766 +01- 1 +1-0 1 +-10 1 +.names Pi21 n171 n1063 n2946 n4767 +01-- 1 +0-01 1 +.names Pi20 n3463 n3465 n4629 n4769 +11-- 1 +1-1- 1 +1--0 1 +.names Pi20 n4623 n4625 n4769 n4770 +1--0 1 +-110 1 +.names Pi20 n3441 n3444 n4645 n4772 +11-- 1 +1-1- 1 +1--0 1 +.names Pi20 n4639 n4641 n4772 n4773 +1--0 1 +-110 1 +.names Pi15 n4631 n4770 n4775 +011 1 +.names n4647 n4773 Pi15 n4776 +111 1 +.names Pi17 n4648 n4649 n4777 +011 1 +.names Ni10 n4775 n4776 n4779 +01- 1 +0-1 1 +.names Pi15 n3271 n3273 n4573 n4575 n4577 n4780 +000111 1 +.names Pi17 n4588 n4589 n4783 +011 1 +.names n4591 n4590 Pi17 n4784 +111 1 +.names Pi15 Ni10 n3937 n4780 n4785 +-0-1 1 +101- 1 +.names Ni10 n4783 n4784 n4786 +11- 1 +1-1 1 +.names Pi15 n3335 n3337 n4598 n4600 n4602 n4787 +000111 1 +.names Pi17 n4612 n4613 n4790 +011 1 +.names n4615 n4614 Pi17 n4791 +111 1 +.names Pi15 Ni10 n3942 n4787 n4792 +-0-1 1 +101- 1 +.names Ni14 Ni12 n4836 n4797 +0-- 1 +-0- 1 +--1 1 +.names Ni6 Ni5 n3527 Ni4 n4798 +0--0 1 +-0-0 1 +--00 1 +.names Ni31 Ni6 Ni5 n4799 +0-- 1 +-0- 1 +--0 1 +.names n4799 Ni4 n2066 n3874 n4800 +111- 1 +11-1 1 +.names Ni4 Ni3 n4799 n4800 n4801 +-1-1 1 +010- 1 +.names Ni2 Ni3 n3952 n4801 n4803 +0--1 1 +001- 1 +.names Ni31 Ni6 Ni2 Ni3 n4805 +-11- 1 +01-1 1 +.names Ni12 n3540 n3559 n3568 n4808 +11-- 1 +1-01 1 +.names Pi20 n184 n3585 n3595 n4810 +11-- 1 +1-1- 1 +1--1 1 +.names Ni44 n3573 Ni42 Ni39 n4811 +0-10 1 +-110 1 +.names Pi27 n3880 n4813 +1- 1 +-1 1 +.names Pi27 Pi26 n3880 n4814 +0-- 1 +-1- 1 +--1 1 +.names Pi24 n3881 n4815 +1- 1 +-1 1 +.names Pi24 Pi23 n3881 n4816 +0-- 1 +-1- 1 +--1 1 +.names n2065 Ni4 n3863 n4817 +10- 1 +-01 1 +.names Ni4 Ni33 n3874 n4818 +11- 1 +1-1 1 +.names Ni33 n834 n4819 +10 1 +.names Ni33 n834 n4820 +00 1 +.names n63 n2086 n4822 +1- 1 +-1 1 +.names n38 Ni41 n4823 +0- 1 +-1 1 +.names n42 Ni41 n4825 +0- 1 +-1 1 +.names Ni33 n2966 n4827 +0- 1 +-1 1 +.names n1062 n953 n4832 +11 1 +.names n1071 n1075 n1079 n4223 n4833 +1--- 1 +-1-- 1 +--1- 1 +---0 1 +.names n4759 n4760 n3879 n4835 +1-- 1 +-1- 1 +--1 1 +.names n3492 Pi27 n4836 +11 1 +.end diff --git a/fpga_flow/benchmarks/MCNC_big20/des.blif b/fpga_flow/benchmarks/MCNC_big20/des.blif new file mode 100644 index 000000000..2e5b6489d --- /dev/null +++ b/fpga_flow/benchmarks/MCNC_big20/des.blif @@ -0,0 +1,5078 @@ +.model TOP +.inputs Preset_0_ Poutreg_63_ Poutreg_62_ Poutreg_61_ Poutreg_60_ Poutreg_59_ \ +Poutreg_58_ Poutreg_57_ Poutreg_56_ Poutreg_55_ Poutreg_54_ Poutreg_53_ \ +Poutreg_52_ Poutreg_51_ Poutreg_50_ Poutreg_49_ Poutreg_48_ Poutreg_47_ \ +Poutreg_46_ Poutreg_45_ Poutreg_44_ Poutreg_43_ Poutreg_42_ Poutreg_41_ \ +Poutreg_40_ Poutreg_39_ Poutreg_38_ Poutreg_37_ Poutreg_36_ Poutreg_35_ \ +Poutreg_34_ Poutreg_33_ Poutreg_32_ Poutreg_31_ Poutreg_30_ Poutreg_29_ \ +Poutreg_28_ Poutreg_27_ Poutreg_26_ Poutreg_25_ Poutreg_24_ Poutreg_23_ \ +Poutreg_22_ Poutreg_21_ Poutreg_20_ Poutreg_19_ Poutreg_18_ Poutreg_17_ \ +Poutreg_16_ Poutreg_15_ Poutreg_14_ Poutreg_13_ Poutreg_12_ Poutreg_11_ \ +Poutreg_10_ Poutreg_9_ Poutreg_8_ Poutreg_7_ Poutreg_6_ Poutreg_5_ Poutreg_4_ \ +Poutreg_3_ Poutreg_2_ Poutreg_1_ Poutreg_0_ Pload_key_0_ Pinreg_55_ Pinreg_54_ \ +Pinreg_53_ Pinreg_52_ Pinreg_51_ Pinreg_50_ Pinreg_49_ Pinreg_48_ Pinreg_47_ \ +Pinreg_46_ Pinreg_45_ Pinreg_44_ Pinreg_43_ Pinreg_42_ Pinreg_41_ Pinreg_40_ \ +Pinreg_39_ Pinreg_38_ Pinreg_37_ Pinreg_36_ Pinreg_35_ Pinreg_34_ Pinreg_33_ \ +Pinreg_32_ Pinreg_31_ Pinreg_30_ Pinreg_29_ Pinreg_28_ Pinreg_27_ Pinreg_26_ \ +Pinreg_25_ Pinreg_24_ Pinreg_23_ Pinreg_22_ Pinreg_21_ Pinreg_20_ Pinreg_19_ \ +Pinreg_18_ Pinreg_17_ Pinreg_16_ Pinreg_15_ Pinreg_14_ Pinreg_13_ Pinreg_12_ \ +Pinreg_11_ Pinreg_10_ Pinreg_9_ Pinreg_8_ Pinreg_7_ Pinreg_6_ Pinreg_5_ \ +Pinreg_4_ Pinreg_3_ Pinreg_2_ Pinreg_1_ Pinreg_0_ Pencrypt_mode_0_ Pencrypt_0_ \ +Pdata_in_7_ Pdata_in_6_ Pdata_in_5_ Pdata_in_4_ Pdata_in_3_ Pdata_in_2_ \ +Pdata_in_1_ Pdata_in_0_ Pdata_63_ Pdata_62_ Pdata_61_ Pdata_60_ Pdata_59_ \ +Pdata_58_ Pdata_57_ Pdata_56_ Pdata_55_ Pdata_54_ Pdata_53_ Pdata_52_ \ +Pdata_51_ Pdata_50_ Pdata_49_ Pdata_48_ Pdata_47_ Pdata_46_ Pdata_45_ \ +Pdata_44_ Pdata_43_ Pdata_42_ Pdata_41_ Pdata_40_ Pdata_39_ Pdata_38_ \ +Pdata_37_ Pdata_36_ Pdata_35_ Pdata_34_ Pdata_33_ Pdata_32_ Pdata_31_ \ +Pdata_30_ Pdata_29_ Pdata_28_ Pdata_27_ Pdata_26_ Pdata_25_ Pdata_24_ \ +Pdata_23_ Pdata_22_ Pdata_21_ Pdata_20_ Pdata_19_ Pdata_18_ Pdata_17_ \ +Pdata_16_ Pdata_15_ Pdata_14_ Pdata_13_ Pdata_12_ Pdata_11_ Pdata_10_ Pdata_9_ \ +Pdata_8_ Pdata_7_ Pdata_6_ Pdata_5_ Pdata_4_ Pdata_3_ Pdata_2_ Pdata_1_ \ +Pdata_0_ Pcount_3_ Pcount_2_ Pcount_1_ Pcount_0_ PD_27_ PD_26_ PD_25_ PD_24_ \ +PD_23_ PD_22_ PD_21_ PD_20_ PD_19_ PD_18_ PD_17_ PD_16_ PD_15_ PD_14_ PD_13_ \ +PD_12_ PD_11_ PD_10_ PD_9_ PD_8_ PD_7_ PD_6_ PD_5_ PD_4_ PD_3_ PD_2_ PD_1_ \ +PD_0_ PC_27_ PC_26_ PC_25_ PC_24_ PC_23_ PC_22_ PC_21_ PC_20_ PC_19_ PC_18_ \ +PC_17_ PC_16_ PC_15_ PC_14_ PC_13_ PC_12_ PC_11_ PC_10_ PC_9_ PC_8_ PC_7_ \ +PC_6_ PC_5_ PC_4_ PC_3_ PC_2_ PC_1_ PC_0_ +.outputs Poutreg_new_63_ Poutreg_new_62_ Poutreg_new_61_ Poutreg_new_60_ \ +Poutreg_new_59_ Poutreg_new_58_ Poutreg_new_57_ Poutreg_new_56_ \ +Poutreg_new_55_ Poutreg_new_54_ Poutreg_new_53_ Poutreg_new_52_ \ +Poutreg_new_51_ Poutreg_new_50_ Poutreg_new_49_ Poutreg_new_48_ \ +Poutreg_new_47_ Poutreg_new_46_ Poutreg_new_45_ Poutreg_new_44_ \ +Poutreg_new_43_ Poutreg_new_42_ Poutreg_new_41_ Poutreg_new_40_ \ +Poutreg_new_39_ Poutreg_new_38_ Poutreg_new_37_ Poutreg_new_36_ \ +Poutreg_new_35_ Poutreg_new_34_ Poutreg_new_33_ Poutreg_new_32_ \ +Poutreg_new_31_ Poutreg_new_30_ Poutreg_new_29_ Poutreg_new_28_ \ +Poutreg_new_27_ Poutreg_new_26_ Poutreg_new_25_ Poutreg_new_24_ \ +Poutreg_new_23_ Poutreg_new_22_ Poutreg_new_21_ Poutreg_new_20_ \ +Poutreg_new_19_ Poutreg_new_18_ Poutreg_new_17_ Poutreg_new_16_ \ +Poutreg_new_15_ Poutreg_new_14_ Poutreg_new_13_ Poutreg_new_12_ \ +Poutreg_new_11_ Poutreg_new_10_ Poutreg_new_9_ Poutreg_new_8_ Poutreg_new_7_ \ +Poutreg_new_6_ Poutreg_new_5_ Poutreg_new_4_ Poutreg_new_3_ Poutreg_new_2_ \ +Poutreg_new_1_ Poutreg_new_0_ Pinreg_new_55_ Pinreg_new_54_ Pinreg_new_53_ \ +Pinreg_new_52_ Pinreg_new_51_ Pinreg_new_50_ Pinreg_new_49_ Pinreg_new_48_ \ +Pinreg_new_47_ Pinreg_new_46_ Pinreg_new_45_ Pinreg_new_44_ Pinreg_new_43_ \ +Pinreg_new_42_ Pinreg_new_41_ Pinreg_new_40_ Pinreg_new_39_ Pinreg_new_38_ \ +Pinreg_new_37_ Pinreg_new_36_ Pinreg_new_35_ Pinreg_new_34_ Pinreg_new_33_ \ +Pinreg_new_32_ Pinreg_new_31_ Pinreg_new_30_ Pinreg_new_29_ Pinreg_new_28_ \ +Pinreg_new_27_ Pinreg_new_26_ Pinreg_new_25_ Pinreg_new_24_ Pinreg_new_23_ \ +Pinreg_new_22_ Pinreg_new_21_ Pinreg_new_20_ Pinreg_new_19_ Pinreg_new_18_ \ +Pinreg_new_17_ Pinreg_new_16_ Pinreg_new_15_ Pinreg_new_14_ Pinreg_new_13_ \ +Pinreg_new_12_ Pinreg_new_11_ Pinreg_new_10_ Pinreg_new_9_ Pinreg_new_8_ \ +Pinreg_new_7_ Pinreg_new_6_ Pinreg_new_5_ Pinreg_new_4_ Pinreg_new_3_ \ +Pinreg_new_2_ Pinreg_new_1_ Pinreg_new_0_ Pencrypt_mode_new_0_ Pdata_new_63_ \ +Pdata_new_62_ Pdata_new_61_ Pdata_new_60_ Pdata_new_59_ Pdata_new_58_ \ +Pdata_new_57_ Pdata_new_56_ Pdata_new_55_ Pdata_new_54_ Pdata_new_53_ \ +Pdata_new_52_ Pdata_new_51_ Pdata_new_50_ Pdata_new_49_ Pdata_new_48_ \ +Pdata_new_47_ Pdata_new_46_ Pdata_new_45_ Pdata_new_44_ Pdata_new_43_ \ +Pdata_new_42_ Pdata_new_41_ Pdata_new_40_ Pdata_new_39_ Pdata_new_38_ \ +Pdata_new_37_ Pdata_new_36_ Pdata_new_35_ Pdata_new_34_ Pdata_new_33_ \ +Pdata_new_32_ Pdata_new_31_ Pdata_new_30_ Pdata_new_29_ Pdata_new_28_ \ +Pdata_new_27_ Pdata_new_26_ Pdata_new_25_ Pdata_new_24_ Pdata_new_23_ \ +Pdata_new_22_ Pdata_new_21_ Pdata_new_20_ Pdata_new_19_ Pdata_new_18_ \ +Pdata_new_17_ Pdata_new_16_ Pdata_new_15_ Pdata_new_14_ Pdata_new_13_ \ +Pdata_new_12_ Pdata_new_11_ Pdata_new_10_ Pdata_new_9_ Pdata_new_8_ \ +Pdata_new_7_ Pdata_new_6_ Pdata_new_5_ Pdata_new_4_ Pdata_new_3_ Pdata_new_2_ \ +Pdata_new_1_ Pdata_new_0_ Pcount_new_3_ Pcount_new_2_ Pcount_new_1_ \ +Pcount_new_0_ PD_new_27_ PD_new_26_ PD_new_25_ PD_new_24_ PD_new_23_ \ +PD_new_22_ PD_new_21_ PD_new_20_ PD_new_19_ PD_new_18_ PD_new_17_ PD_new_16_ \ +PD_new_15_ PD_new_14_ PD_new_13_ PD_new_12_ PD_new_11_ PD_new_10_ PD_new_9_ \ +PD_new_8_ PD_new_7_ PD_new_6_ PD_new_5_ PD_new_4_ PD_new_3_ PD_new_2_ \ +PD_new_1_ PD_new_0_ PC_new_27_ PC_new_26_ PC_new_25_ PC_new_24_ PC_new_23_ \ +PC_new_22_ PC_new_21_ PC_new_20_ PC_new_19_ PC_new_18_ PC_new_17_ PC_new_16_ \ +PC_new_15_ PC_new_14_ PC_new_13_ PC_new_12_ PC_new_11_ PC_new_10_ PC_new_9_ \ +PC_new_8_ PC_new_7_ PC_new_6_ PC_new_5_ PC_new_4_ PC_new_3_ PC_new_2_ \ +PC_new_1_ PC_new_0_ +.names n2 Poutreg_new_63_ +0 1 +.names n105 Poutreg_new_62_ +0 1 +.names n3 Poutreg_new_61_ +0 1 +.names n101 Poutreg_new_60_ +0 1 +.names n4 Poutreg_new_59_ +0 1 +.names n97 Poutreg_new_58_ +0 1 +.names n5 Poutreg_new_57_ +0 1 +.names n91 Poutreg_new_56_ +0 1 +.names n6 Poutreg_new_55_ +0 1 +.names n124 Poutreg_new_54_ +0 1 +.names n7 Poutreg_new_53_ +0 1 +.names n94 Poutreg_new_52_ +0 1 +.names n8 Poutreg_new_51_ +0 1 +.names n123 Poutreg_new_50_ +0 1 +.names n9 Poutreg_new_49_ +0 1 +.names n122 Poutreg_new_48_ +0 1 +.names n10 Poutreg_new_47_ +0 1 +.names n121 Poutreg_new_46_ +0 1 +.names n11 Poutreg_new_45_ +0 1 +.names n120 Poutreg_new_44_ +0 1 +.names n12 Poutreg_new_43_ +0 1 +.names n119 Poutreg_new_42_ +0 1 +.names n13 Poutreg_new_41_ +0 1 +.names n118 Poutreg_new_40_ +0 1 +.names n14 Poutreg_new_39_ +0 1 +.names n117 Poutreg_new_38_ +0 1 +.names n15 Poutreg_new_37_ +0 1 +.names n116 Poutreg_new_36_ +0 1 +.names n16 Poutreg_new_35_ +0 1 +.names n115 Poutreg_new_34_ +0 1 +.names n17 Poutreg_new_33_ +0 1 +.names n114 Poutreg_new_32_ +0 1 +.names n18 Poutreg_new_31_ +0 1 +.names n113 Poutreg_new_30_ +0 1 +.names n19 Poutreg_new_29_ +0 1 +.names n112 Poutreg_new_28_ +0 1 +.names n20 Poutreg_new_27_ +0 1 +.names n111 Poutreg_new_26_ +0 1 +.names n21 Poutreg_new_25_ +0 1 +.names n110 Poutreg_new_24_ +0 1 +.names n22 Poutreg_new_23_ +0 1 +.names n109 Poutreg_new_22_ +0 1 +.names n23 Poutreg_new_21_ +0 1 +.names n108 Poutreg_new_20_ +0 1 +.names n24 Poutreg_new_19_ +0 1 +.names n107 Poutreg_new_18_ +0 1 +.names n25 Poutreg_new_17_ +0 1 +.names n106 Poutreg_new_16_ +0 1 +.names n26 Poutreg_new_15_ +0 1 +.names n104 Poutreg_new_14_ +0 1 +.names n27 Poutreg_new_13_ +0 1 +.names n103 Poutreg_new_12_ +0 1 +.names n28 Poutreg_new_11_ +0 1 +.names n102 Poutreg_new_10_ +0 1 +.names n29 Poutreg_new_9_ +0 1 +.names n100 Poutreg_new_8_ +0 1 +.names n30 Poutreg_new_7_ +0 1 +.names n99 Poutreg_new_6_ +0 1 +.names n31 Poutreg_new_5_ +0 1 +.names n98 Poutreg_new_4_ +0 1 +.names n32 Poutreg_new_3_ +0 1 +.names n96 Poutreg_new_2_ +0 1 +.names n33 Poutreg_new_1_ +0 1 +.names n95 Poutreg_new_0_ +0 1 +.names n35 Pinreg_new_55_ +0 1 +.names n36 Pinreg_new_54_ +0 1 +.names n37 Pinreg_new_53_ +0 1 +.names n38 Pinreg_new_52_ +0 1 +.names n39 Pinreg_new_51_ +0 1 +.names n40 Pinreg_new_50_ +0 1 +.names n41 Pinreg_new_49_ +0 1 +.names n42 Pinreg_new_48_ +0 1 +.names n43 Pinreg_new_47_ +0 1 +.names n44 Pinreg_new_46_ +0 1 +.names n45 Pinreg_new_45_ +0 1 +.names n46 Pinreg_new_44_ +0 1 +.names n47 Pinreg_new_43_ +0 1 +.names n48 Pinreg_new_42_ +0 1 +.names n49 Pinreg_new_41_ +0 1 +.names n50 Pinreg_new_40_ +0 1 +.names n51 Pinreg_new_39_ +0 1 +.names n52 Pinreg_new_38_ +0 1 +.names n53 Pinreg_new_37_ +0 1 +.names n54 Pinreg_new_36_ +0 1 +.names n55 Pinreg_new_35_ +0 1 +.names n56 Pinreg_new_34_ +0 1 +.names n57 Pinreg_new_33_ +0 1 +.names n58 Pinreg_new_32_ +0 1 +.names n59 Pinreg_new_31_ +0 1 +.names n60 Pinreg_new_30_ +0 1 +.names n61 Pinreg_new_29_ +0 1 +.names n62 Pinreg_new_28_ +0 1 +.names n63 Pinreg_new_27_ +0 1 +.names n64 Pinreg_new_26_ +0 1 +.names n65 Pinreg_new_25_ +0 1 +.names n66 Pinreg_new_24_ +0 1 +.names n67 Pinreg_new_23_ +0 1 +.names n68 Pinreg_new_22_ +0 1 +.names n69 Pinreg_new_21_ +0 1 +.names n70 Pinreg_new_20_ +0 1 +.names n71 Pinreg_new_19_ +0 1 +.names n72 Pinreg_new_18_ +0 1 +.names n73 Pinreg_new_17_ +0 1 +.names n74 Pinreg_new_16_ +0 1 +.names n75 Pinreg_new_15_ +0 1 +.names n76 Pinreg_new_14_ +0 1 +.names n77 Pinreg_new_13_ +0 1 +.names n78 Pinreg_new_12_ +0 1 +.names n79 Pinreg_new_11_ +0 1 +.names n80 Pinreg_new_10_ +0 1 +.names n81 Pinreg_new_9_ +0 1 +.names n82 Pinreg_new_8_ +0 1 +.names n83 Pinreg_new_7_ +0 1 +.names n84 Pinreg_new_6_ +0 1 +.names n85 Pinreg_new_5_ +0 1 +.names n86 Pinreg_new_4_ +0 1 +.names n87 Pinreg_new_3_ +0 1 +.names n88 Pinreg_new_2_ +0 1 +.names n89 Pinreg_new_1_ +0 1 +.names n90 Pinreg_new_0_ +0 1 +.names n1454 Pencrypt_mode_new_0_ +0 1 +.names n1387 Pdata_new_63_ +0 1 +.names n1388 Pdata_new_62_ +0 1 +.names n1389 Pdata_new_61_ +0 1 +.names n1390 Pdata_new_60_ +0 1 +.names n1391 Pdata_new_59_ +0 1 +.names n1392 Pdata_new_58_ +0 1 +.names n1393 Pdata_new_57_ +0 1 +.names n1394 Pdata_new_56_ +0 1 +.names n1395 Pdata_new_55_ +0 1 +.names n1396 Pdata_new_54_ +0 1 +.names n1397 Pdata_new_53_ +0 1 +.names n1398 Pdata_new_52_ +0 1 +.names n1399 Pdata_new_51_ +0 1 +.names n1400 Pdata_new_50_ +0 1 +.names n1401 Pdata_new_49_ +0 1 +.names n1402 Pdata_new_48_ +0 1 +.names n1403 Pdata_new_47_ +0 1 +.names n1404 Pdata_new_46_ +0 1 +.names n1405 Pdata_new_45_ +0 1 +.names n1406 Pdata_new_44_ +0 1 +.names n1407 Pdata_new_43_ +0 1 +.names n1408 Pdata_new_42_ +0 1 +.names n1409 Pdata_new_41_ +0 1 +.names n1410 Pdata_new_40_ +0 1 +.names n1411 Pdata_new_39_ +0 1 +.names n1412 Pdata_new_38_ +0 1 +.names n1413 Pdata_new_37_ +0 1 +.names n1414 Pdata_new_36_ +0 1 +.names n1415 Pdata_new_35_ +0 1 +.names n1416 Pdata_new_34_ +0 1 +.names n1417 Pdata_new_33_ +0 1 +.names n1418 Pdata_new_32_ +0 1 +.names n1419 Pdata_new_31_ +0 1 +.names n1420 Pdata_new_30_ +0 1 +.names n1421 Pdata_new_29_ +0 1 +.names n1422 Pdata_new_28_ +0 1 +.names n1423 Pdata_new_27_ +0 1 +.names n1424 Pdata_new_26_ +0 1 +.names n1425 Pdata_new_25_ +0 1 +.names n1426 Pdata_new_24_ +0 1 +.names n1427 Pdata_new_23_ +0 1 +.names n1428 Pdata_new_22_ +0 1 +.names n1429 Pdata_new_21_ +0 1 +.names n1430 Pdata_new_20_ +0 1 +.names n1431 Pdata_new_19_ +0 1 +.names n1432 Pdata_new_18_ +0 1 +.names n1433 Pdata_new_17_ +0 1 +.names n1434 Pdata_new_16_ +0 1 +.names n1435 Pdata_new_15_ +0 1 +.names n1436 Pdata_new_14_ +0 1 +.names n1437 Pdata_new_13_ +0 1 +.names n1438 Pdata_new_12_ +0 1 +.names n1439 Pdata_new_11_ +0 1 +.names n1440 Pdata_new_10_ +0 1 +.names n1441 Pdata_new_9_ +0 1 +.names n1442 Pdata_new_8_ +0 1 +.names n1443 Pdata_new_7_ +0 1 +.names n1444 Pdata_new_6_ +0 1 +.names n1445 Pdata_new_5_ +0 1 +.names n1446 Pdata_new_4_ +0 1 +.names n1447 Pdata_new_3_ +0 1 +.names n1448 Pdata_new_2_ +0 1 +.names n1449 Pdata_new_1_ +0 1 +.names n1450 Pdata_new_0_ +0 1 +.names n34 Pcount_new_3_ +0 1 +.names n1451 Pcount_new_2_ +0 1 +.names n1452 Pcount_new_1_ +0 1 +.names n925 Pcount_new_0_ +0 1 +.names n1043 PD_new_27_ +0 1 +.names n1047 PD_new_26_ +0 1 +.names n1051 PD_new_25_ +0 1 +.names n1055 PD_new_24_ +0 1 +.names n1059 PD_new_23_ +0 1 +.names n1063 PD_new_22_ +0 1 +.names n1067 PD_new_21_ +0 1 +.names n1071 PD_new_20_ +0 1 +.names n1075 PD_new_19_ +0 1 +.names n1079 PD_new_18_ +0 1 +.names n1083 PD_new_17_ +0 1 +.names n1087 PD_new_16_ +0 1 +.names n1091 PD_new_15_ +0 1 +.names n1095 PD_new_14_ +0 1 +.names n1099 PD_new_13_ +0 1 +.names n1103 PD_new_12_ +0 1 +.names n1107 PD_new_11_ +0 1 +.names n1111 PD_new_10_ +0 1 +.names n1115 PD_new_9_ +0 1 +.names n1119 PD_new_8_ +0 1 +.names n1123 PD_new_7_ +0 1 +.names n1127 PD_new_6_ +0 1 +.names n1131 PD_new_5_ +0 1 +.names n1135 PD_new_4_ +0 1 +.names n1139 PD_new_3_ +0 1 +.names n1143 PD_new_2_ +0 1 +.names n1147 PD_new_1_ +0 1 +.names n1151 PD_new_0_ +0 1 +.names n931 PC_new_27_ +0 1 +.names n935 PC_new_26_ +0 1 +.names n939 PC_new_25_ +0 1 +.names n943 PC_new_24_ +0 1 +.names n947 PC_new_23_ +0 1 +.names n951 PC_new_22_ +0 1 +.names n955 PC_new_21_ +0 1 +.names n959 PC_new_20_ +0 1 +.names n963 PC_new_19_ +0 1 +.names n967 PC_new_18_ +0 1 +.names n971 PC_new_17_ +0 1 +.names n975 PC_new_16_ +0 1 +.names n979 PC_new_15_ +0 1 +.names n983 PC_new_14_ +0 1 +.names n987 PC_new_13_ +0 1 +.names n991 PC_new_12_ +0 1 +.names n995 PC_new_11_ +0 1 +.names n999 PC_new_10_ +0 1 +.names n1003 PC_new_9_ +0 1 +.names n1007 PC_new_8_ +0 1 +.names n1011 PC_new_7_ +0 1 +.names n1015 PC_new_6_ +0 1 +.names n1019 PC_new_5_ +0 1 +.names n1023 PC_new_4_ +0 1 +.names n1027 PC_new_3_ +0 1 +.names n1031 PC_new_2_ +0 1 +.names n1035 PC_new_1_ +0 1 +.names n1039 PC_new_0_ +0 1 +.names Pcount_3_ n1177 n1 +0- 1 +-1 1 +.names Poutreg_63_ Pcount_0_ n1 n234 n2 +0-1- 1 +-11- 1 +0--1 1 +-1-1 1 +.names Poutreg_61_ Pcount_0_ n1 n287 n3 +0-1- 1 +-11- 1 +0--1 1 +-1-1 1 +.names Poutreg_59_ Pcount_0_ n1 n309 n4 +0-1- 1 +-11- 1 +0--1 1 +-1-1 1 +.names Poutreg_57_ Pcount_0_ n1 n346 n5 +0-1- 1 +-11- 1 +0--1 1 +-1-1 1 +.names Poutreg_55_ Pcount_0_ n365 n6 +0-1 1 +-11 1 +.names Poutreg_53_ Pcount_0_ n412 n7 +0-1 1 +-11 1 +.names Poutreg_51_ Pcount_0_ n428 n8 +0-1 1 +-11 1 +.names Poutreg_49_ Pcount_0_ n455 n9 +0-1 1 +-11 1 +.names Poutreg_47_ Pcount_0_ n505 n10 +0-1 1 +-11 1 +.names Poutreg_45_ Pcount_0_ n538 n11 +0-1 1 +-11 1 +.names Poutreg_43_ Pcount_0_ n551 n12 +0-1 1 +-11 1 +.names Poutreg_41_ Pcount_0_ n564 n13 +0-1 1 +-11 1 +.names Poutreg_39_ Pcount_0_ n580 n14 +0-1 1 +-11 1 +.names Poutreg_37_ Pcount_0_ n596 n15 +0-1 1 +-11 1 +.names Poutreg_35_ Pcount_0_ n639 n16 +0-1 1 +-11 1 +.names Poutreg_33_ Pcount_0_ n650 n17 +0-1 1 +-11 1 +.names Poutreg_31_ Pcount_0_ n665 n18 +0-1 1 +-11 1 +.names Poutreg_29_ Pcount_0_ n687 n19 +0-1 1 +-11 1 +.names Poutreg_27_ Pcount_0_ n698 n20 +0-1 1 +-11 1 +.names Poutreg_25_ Pcount_0_ n706 n21 +0-1 1 +-11 1 +.names Poutreg_23_ Pcount_0_ n762 n22 +0-1 1 +-11 1 +.names Poutreg_21_ Pcount_0_ n783 n23 +0-1 1 +-11 1 +.names Poutreg_19_ Pcount_0_ n797 n24 +0-1 1 +-11 1 +.names Poutreg_17_ Pcount_0_ n819 n25 +0-1 1 +-11 1 +.names Poutreg_15_ Pcount_0_ n831 n26 +0-1 1 +-11 1 +.names Poutreg_13_ Pcount_0_ n843 n27 +0-1 1 +-11 1 +.names Poutreg_11_ Pcount_0_ n855 n28 +0-1 1 +-11 1 +.names Poutreg_9_ Pcount_0_ n869 n29 +0-1 1 +-11 1 +.names Poutreg_7_ Pcount_0_ n884 n30 +0-1 1 +-11 1 +.names Poutreg_5_ Pcount_0_ n891 n31 +0-1 1 +-11 1 +.names Poutreg_3_ Pcount_0_ n907 n32 +0-1 1 +-11 1 +.names Poutreg_1_ Pcount_0_ n920 n33 +0-1 1 +-11 1 +.names Pcount_3_ n924 n926 n928 n34 +01-- 1 +-11- 1 +0--1 1 +--11 1 +.names Pinreg_55_ Pinreg_47_ Pcount_0_ n126 n35 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_54_ Pinreg_46_ Pcount_0_ n126 n36 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_53_ Pinreg_45_ Pcount_0_ n126 n37 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_52_ Pinreg_44_ Pcount_0_ n126 n38 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_51_ Pinreg_43_ Pcount_0_ n126 n39 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_50_ Pinreg_42_ Pcount_0_ n126 n40 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_49_ Pinreg_41_ Pcount_0_ n126 n41 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_48_ Pinreg_40_ Pcount_0_ n126 n42 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_47_ Pinreg_39_ Pcount_0_ n126 n43 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_46_ Pinreg_38_ Pcount_0_ n126 n44 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_45_ Pinreg_37_ Pcount_0_ n126 n45 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_44_ Pinreg_36_ Pcount_0_ n126 n46 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_43_ Pinreg_35_ Pcount_0_ n126 n47 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_42_ Pinreg_34_ Pcount_0_ n126 n48 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_41_ Pinreg_33_ Pcount_0_ n126 n49 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_40_ Pinreg_32_ Pcount_0_ n126 n50 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_39_ Pinreg_31_ Pcount_0_ n126 n51 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_38_ Pinreg_30_ Pcount_0_ n126 n52 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_37_ Pinreg_29_ Pcount_0_ n126 n53 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_36_ Pinreg_28_ Pcount_0_ n126 n54 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_35_ Pinreg_27_ Pcount_0_ n126 n55 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_34_ Pinreg_26_ Pcount_0_ n126 n56 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_33_ Pinreg_25_ Pcount_0_ n126 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n357 n591 n590 +01-- 1 +-111 1 +.names n328 n1215 n594 +0- 1 +-1 1 +.names n594 n323 n593 +1- 1 +-1 1 +.names Poutreg_45_ n1 n126 n1504 n596 +01-- 1 +-11- 1 +0--1 1 +--11 1 +.names Poutreg_44_ Poutreg_36_ Pcount_0_ n126 n598 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names n609 n766 n862 n1380 n602 +10-- 1 +-00- 1 +1--0 1 +--00 1 +.names n873 n1167 n600 +1- 1 +-0 1 +.names n602 n600 n781 n599 +11- 1 +1-0 1 +.names n629 n1166 n607 +01 1 +.names n775 n1167 n604 +00 1 +.names n766 n776 n605 +00 1 +.names n600 n607 n604 n605 n603 +01-- 1 +-111 1 +.names n772 n781 n1292 n612 +0-- 1 +-0- 1 +--1 1 +.names n1292 n1293 n609 +1- 1 +-0 1 +.names n603 n612 n609 n773 n608 +011- 1 +01-0 1 +.names n766 n776 n615 +1- 1 +-0 1 +.names n607 n605 n615 n862 n613 +0-1- 1 +-01- 1 +0--0 1 +-0-0 1 +.names n766 n1166 n1295 n620 +0-- 1 +-1- 1 +--0 1 +.names n609 n781 n621 +1- 1 +-0 1 +.names n613 n620 n621 n777 n618 +111- 1 +-110 1 +.names n773 n772 n862 n1293 n622 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names n607 n780 n1293 n626 +0-- 1 +-0- 1 +--0 1 +.names n604 n1297 n627 +0- 1 +-1 1 +.names n622 n626 n627 n777 n625 +111- 1 +-110 1 +.names n780 n862 n631 +0- 1 +-0 1 +.names n777 n776 n1300 n632 +0-- 1 +-0- 1 +--1 1 +.names Pdata_57_ PD_10_ n629 +01 1 +10 1 +.names n631 n632 n629 n866 n628 +111- 1 +11-0 1 +.names n1624 n1300 n1301 n634 +11- 1 +1-1 1 +.names n608 n599 n635 +11 1 +.names n628 n766 n775 n1297 n636 +1-0- 1 +-00- 1 +1--1 1 +-0-1 1 +.names n773 n878 n1166 n1298 n637 +01-- 1 +0-0- 1 +-1-1 1 +--01 1 +.names n634 n635 n618 n625 n636 n637 n633 +111111 1 +.names Poutreg_43_ n1 n126 n1505 n639 +01-- 1 +-11- 1 +0--1 1 +--11 1 +.names Poutreg_42_ Poutreg_34_ Pcount_0_ n126 n641 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names n508 n1165 n1265 n1303 n642 +1-0- 1 +-00- 1 +1--0 1 +-0-0 1 +.names n510 n531 n648 +0- 1 +-0 1 +.names Pdata_53_ PD_22_ n647 +01 1 +10 1 +.names n510 n648 n647 n1265 n646 +11-0 1 +-110 1 +.names Poutreg_41_ n1 n126 n1507 n650 +01-- 1 +-11- 1 +0--1 1 +--11 1 +.names Poutreg_40_ Poutreg_32_ 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n720 n732 n727 +1-- 1 +-0- 1 +--1 1 +.names n814 n895 n724 +0- 1 +-0 1 +.names n751 n732 n725 +1- 1 +-1 1 +.names n718 n727 n724 n725 n723 +011- 1 +01-1 1 +.names n738 n1169 n729 +0- 1 +-1 1 +.names n742 n895 n730 +0- 1 +-0 1 +.names n719 n729 n730 n728 +0-- 1 +-1- 1 +--1 1 +.names n738 n1169 n732 +1- 1 +-0 1 +.names n732 n814 n888 n731 +1-- 1 +-0- 1 +--0 1 +.names n710 n711 n722 n735 +1-- 1 +-1- 1 +--0 1 +.names Pdata_44_ PC_7_ n738 +01 1 +10 1 +.names n802 n895 n1169 n740 +0-- 1 +-0- 1 +--1 1 +.names n738 n740 n751 n737 +1-- 1 +-1- 1 +--0 1 +.names n732 n742 n898 n744 +1-- 1 +-0- 1 +--1 1 +.names n1635 n729 n724 n751 n745 +11-- 1 +1-1- 1 +1--1 1 +.names Pdata_39_ PC_22_ n742 +01 1 +10 1 +.names n725 n756 n895 n743 +1-- 1 +-0- 1 +--0 1 +.names n744 n745 n742 n743 n741 +111- 1 +11-1 1 +.names n711 n719 n742 n748 +10- 1 +-01 1 +1-0 1 +.names n748 n751 n802 n746 +10- 1 +1-0 1 +.names Pdata_41_ PC_11_ n751 +01 1 +10 1 +.names n751 n888 n895 n749 +10- 1 +-00 1 +.names n801 n898 n754 +0- 1 +-1 1 +.names n722 n749 n754 n756 n752 +0-1- 1 +-11- 1 +--10 1 +.names Pdata_40_ PC_18_ n756 +01 1 +10 1 +.names n719 n742 n751 n756 n755 +0-0- 1 +-10- 1 +0--1 1 +-1-1 1 +.names n746 n814 n1169 n759 +01- 1 +0-1 1 +-10 1 +.names n738 n759 n895 n757 +010 1 +.names n740 n751 n760 +1- 1 +-1 1 +.names Poutreg_31_ n1 n126 n1517 n762 +01-- 1 +-11- 1 +0--1 1 +--11 1 +.names Poutreg_30_ Poutreg_22_ Pcount_0_ n126 n764 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names Pdata_59_ PD_5_ n766 +01 1 +10 1 +.names n766 n1166 n1295 n765 +1-- 1 +-0- 1 +--0 1 +.names n607 n604 n1293 n769 +0-- 1 +-0- 1 +--0 1 +.names n629 n1166 n773 +00 1 +.names n766 n776 n772 +10 1 +.names n600 n604 n773 n772 n771 +0-1- 1 +-111 1 +.names n775 n1167 n777 +10 1 +.names Pdata_56_ PD_20_ n775 +01 1 +10 1 +.names Pdata_55_ PD_15_ n776 +01 1 +10 1 +.names n629 n777 n775 n776 n774 +01-- 1 +0-11 1 +.names n775 n1167 n780 +11 1 +.names n629 n1166 n781 +10 1 +.names n780 n781 n779 +11 1 +.names Poutreg_29_ n1 n126 n1521 n783 +01-- 1 +-11- 1 +0--1 1 +--11 1 +.names Poutreg_28_ Poutreg_20_ Pcount_0_ n126 n785 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names n207 n789 n914 n786 +00- 1 +-00 1 +.names n220 n222 n789 +11 1 +.names n789 n209 n788 +11 1 +.names n230 n915 n1155 n1383 n790 +-0-0 1 +100- 1 +.names n1155 n1188 n795 +0- 1 +-1 1 +.names n795 n1184 n794 +1- 1 +-0 1 +.names Poutreg_27_ n1 n126 n1524 n797 +01-- 1 +-11- 1 +0--1 1 +--11 1 +.names Poutreg_26_ Poutreg_18_ Pcount_0_ n126 n799 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names n742 n756 n802 +10 1 +.names n751 n895 n803 +00 1 +.names n738 n1169 n801 +00 1 +.names n802 n803 n801 n722 n800 +111- 1 +11-1 1 +.names n751 n814 n1318 n806 +1-- 1 +-0- 1 +--1 1 +.names n721 n801 n800 n806 n804 +0-01 1 +-001 1 +.names n711 n720 n801 n808 +1-- 1 +-0- 1 +--0 1 +.names n732 n749 n802 n809 +1-- 1 +-1- 1 +--0 1 +.names n730 n710 n811 +11 1 +.names n719 n811 n1340 n810 +0-- 1 +-1- 1 +--0 1 +.names n742 n756 n814 +00 1 +.names n725 n814 n895 n813 +010 1 +.names n742 n898 n1169 n817 +001 1 +.names n817 n738 n816 +11 1 +.names Poutreg_25_ n1 n126 n1718 n819 +01-- 1 +-11- 1 +0--0 1 +--10 1 +.names Poutreg_24_ Poutreg_16_ Pcount_0_ n126 n821 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names n266 n1172 n824 +0- 1 +-1 1 +.names n254 n264 n279 n824 n822 +1-01 1 +-001 1 +.names n254 n297 n827 +0- 1 +-1 1 +.names n274 n822 n835 n1201 n829 +0-0- 1 +-10- 1 +0--0 1 +-1-0 1 +.names n249 n257 n296 n827 n829 n1702 n826 +111110 1 +.names Poutreg_23_ n1 n126 n1528 n831 +01-- 1 +-11- 1 +0--1 1 +--11 1 +.names Poutreg_22_ Poutreg_14_ Pcount_0_ n126 n833 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names Pdata_33_ PC_10_ n835 +01 1 +10 1 +.names n274 n266 n835 n834 +11- 1 +1-1 1 +.names n254 n297 n1384 n837 +01- 1 +1-0 1 +-10 1 +.names n296 n1203 n838 +10 1 +.names n275 n835 n1647 n1648 n839 +1--- 1 +-0-- 1 +--1- 1 +---1 1 +.names n244 n266 n1202 n841 +10- 1 +1-1 1 +.names n257 n837 n838 n839 n841 n1649 n836 +111110 1 +.names Poutreg_21_ n1 n126 n1529 n843 +01-- 1 +-11- 1 +0--1 1 +--11 1 +.names Poutreg_20_ Poutreg_12_ Pcount_0_ n126 n845 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names n459 n475 n675 n847 +0-- 1 +-1- 1 +--0 1 +.names n459 n475 n847 n846 +1-1 1 +-01 1 +.names n460 n491 n849 +01 1 +.names n459 n675 n849 n848 +011 1 +.names n475 n675 n851 +00 1 +.names n460 n675 n475 n852 +111 1 +.names n851 n852 n1249 n850 +1-0 1 +-10 1 +.names Poutreg_19_ n1 n126 n1533 n855 +01-- 1 +-11- 1 +0--1 1 +--11 1 +.names Poutreg_18_ Poutreg_10_ Pcount_0_ n126 n857 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names n772 n781 n780 n858 +111 1 +.names n607 n605 n777 n859 +101 1 +.names n1166 n629 n862 +11 1 +.names n605 n1167 n1325 n863 +11- 1 +1-1 1 +-01 1 +.names n775 n862 n863 n860 +011 1 +.names n777 n776 n1166 n866 +100 1 +.names n766 n866 n878 n864 +01- 1 +0-0 1 +.names Poutreg_17_ n1 n126 n1719 n869 +01-- 1 +-11- 1 +0--0 1 +--10 1 +.names Poutreg_16_ Poutreg_8_ Pcount_0_ n126 n871 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names n775 n1300 n1325 n874 +0-- 1 +-0- 1 +--1 1 +.names n1297 n775 n875 +1- 1 +-1 1 +.names n775 n615 n873 +1- 1 +-1 1 +.names n862 n874 n875 n873 n872 +011- 1 +-111 1 +.names n629 n776 n1292 n1654 n877 +1--1 1 +-0-1 1 +--11 1 +.names n775 n1289 n878 +0- 1 +-1 1 +.names n866 n877 n878 n1166 n876 +0--0 1 +011- 1 +.names n615 n629 n777 n879 +1-- 1 +-1- 1 +--0 1 +.names n781 n1298 n1301 n880 +10- 1 +1-0 1 +.names Poutreg_15_ n1 n126 n1538 n884 +01-- 1 +-11- 1 +0--1 1 +--11 1 +.names Poutreg_14_ Poutreg_6_ Pcount_0_ n126 n886 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names n751 n895 n888 +10 1 +.names n756 n888 n887 +01 1 +.names n725 n811 n889 +1- 1 +-1 1 +.names Poutreg_13_ n1 n126 n1539 n891 +01-- 1 +-11- 1 +0--1 1 +--11 1 +.names Poutreg_12_ Poutreg_4_ Pcount_0_ n126 n893 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names n801 n895 n896 +1- 1 +-0 1 +.names Pdata_43_ PC_25_ n895 +01 1 +10 1 +.names n725 n756 n896 n895 n894 +001- 1 +-011 1 +.names n711 n895 n898 +1- 1 +-0 1 +.names n738 n743 n894 n898 n897 +010- 1 +-101 1 +.names n741 n804 n808 n1319 n901 +1111 1 +.names n742 n754 n897 n902 +01- 1 +1-1 1 +-11 1 +.names n724 n751 n1340 n903 +1-- 1 +-0- 1 +--1 1 +.names n710 n719 n1169 n904 +1-- 1 +-0- 1 +--0 1 +.names n895 n1341 n746 n1318 n905 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n901 n723 n902 n903 n904 n905 n900 +111111 1 +.names Poutreg_11_ n1 n126 n1540 n907 +01-- 1 +-11- 1 +0--1 1 +--11 1 +.names Poutreg_10_ Poutreg_2_ Pcount_0_ n126 n909 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names n201 n914 n912 +01 1 +.names n220 n1156 n911 +10 1 +.names n231 n912 n911 n207 n910 +111- 1 +11-1 1 +.names Pdata_47_ PD_12_ n914 +01 1 +10 1 +.names Pdata_52_ PD_26_ n915 +01 1 +10 1 +.names n914 n915 n1660 n913 +1-- 1 +-1- 1 +--0 1 +.names n212 n226 n917 +1- 1 +-0 1 +.names Poutreg_9_ n1 n126 n1541 n920 +01-- 1 +-11- 1 +0--1 1 +--11 1 +.names Poutreg_8_ Poutreg_0_ Pcount_0_ n126 n922 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names Pcount_0_ n924 n925 +1- 1 +-1 1 +.names n92 Preset_0_ n924 +1- 1 +-1 1 +.names n925 Pcount_1_ n924 n923 +11- 1 +1-1 1 +.names n923 Pcount_2_ n924 n926 +11- 1 +1-1 1 +.names Pcount_3_ n1177 n928 +1- 1 +-1 1 +.names Pcount_0_ n1 n928 n1453 n929 +111- 1 +-110 1 +.names PC_26_ PC_0_ n1352 n1353 n932 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names PC_25_ PC_1_ n1348 n1351 n933 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names PC_27_ n1359 n1542 n934 +0-1 1 +-11 1 +.names n932 n933 n934 n931 +111 1 +.names PC_27_ PC_25_ n1352 n1353 n936 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_24_ PC_0_ n1348 n1351 n937 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names PC_26_ n1359 n1543 n938 +0-1 1 +-11 1 +.names n936 n937 n938 n935 +111 1 +.names PC_26_ PC_24_ n1352 n1353 n940 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_27_ PC_23_ n1348 n1351 n941 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_25_ n1359 n1544 n942 +0-1 1 +-11 1 +.names n940 n941 n942 n939 +111 1 +.names PC_25_ PC_23_ n1352 n1353 n944 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_26_ PC_22_ n1348 n1351 n945 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_24_ n1359 n1545 n946 +0-1 1 +-11 1 +.names n944 n945 n946 n943 +111 1 +.names PC_24_ PC_22_ n1352 n1353 n948 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_25_ PC_21_ n1348 n1351 n949 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_23_ n1359 n1546 n950 +0-1 1 +-11 1 +.names n948 n949 n950 n947 +111 1 +.names PC_23_ PC_21_ n1352 n1353 n952 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_24_ PC_20_ n1348 n1351 n953 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_22_ n1359 n1547 n954 +0-1 1 +-11 1 +.names n952 n953 n954 n951 +111 1 +.names PC_22_ PC_20_ n1352 n1353 n956 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_23_ PC_19_ n1348 n1351 n957 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_21_ n1359 n1548 n958 +0-1 1 +-11 1 +.names n956 n957 n958 n955 +111 1 +.names PC_21_ PC_19_ n1352 n1353 n960 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_22_ PC_18_ n1348 n1351 n961 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_20_ n1359 n1549 n962 +0-1 1 +-11 1 +.names n960 n961 n962 n959 +111 1 +.names PC_20_ PC_18_ n1352 n1353 n964 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_21_ PC_17_ n1348 n1351 n965 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_19_ n1359 n1550 n966 +0-1 1 +-11 1 +.names n964 n965 n966 n963 +111 1 +.names PC_19_ PC_17_ n1352 n1353 n968 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_20_ PC_16_ n1348 n1351 n969 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_18_ n1359 n1551 n970 +0-1 1 +-11 1 +.names n968 n969 n970 n967 +111 1 +.names PC_18_ PC_16_ n1352 n1353 n972 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_19_ PC_15_ n1348 n1351 n973 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_17_ n1359 n1552 n974 +0-1 1 +-11 1 +.names n972 n973 n974 n971 +111 1 +.names PC_17_ PC_15_ n1352 n1353 n976 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_18_ PC_14_ n1348 n1351 n977 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_16_ n1359 n1553 n978 +0-1 1 +-11 1 +.names n976 n977 n978 n975 +111 1 +.names PC_16_ PC_14_ n1352 n1353 n980 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_17_ PC_13_ n1348 n1351 n981 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_15_ n1359 n1554 n982 +0-1 1 +-11 1 +.names n980 n981 n982 n979 +111 1 +.names PC_15_ PC_13_ n1352 n1353 n984 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_16_ PC_12_ n1348 n1351 n985 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_14_ n1359 n1555 n986 +0-1 1 +-11 1 +.names n984 n985 n986 n983 +111 1 +.names PC_14_ PC_12_ n1352 n1353 n988 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_15_ PC_11_ n1348 n1351 n989 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_13_ n1359 n1556 n990 +0-1 1 +-11 1 +.names n988 n989 n990 n987 +111 1 +.names PC_13_ PC_11_ n1352 n1353 n992 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_14_ PC_10_ n1348 n1351 n993 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_12_ n1359 n1557 n994 +0-1 1 +-11 1 +.names n992 n993 n994 n991 +111 1 +.names PC_12_ PC_10_ n1352 n1353 n996 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_13_ PC_9_ n1348 n1351 n997 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_11_ n1359 n1558 n998 +0-1 1 +-11 1 +.names n996 n997 n998 n995 +111 1 +.names PC_11_ PC_9_ n1352 n1353 n1000 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_12_ PC_8_ n1348 n1351 n1001 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_10_ n1359 n1559 n1002 +0-1 1 +-11 1 +.names n1000 n1001 n1002 n999 +111 1 +.names PC_10_ PC_8_ n1352 n1353 n1004 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_11_ PC_7_ n1348 n1351 n1005 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_9_ n1359 n1560 n1006 +0-1 1 +-11 1 +.names n1004 n1005 n1006 n1003 +111 1 +.names PC_9_ PC_7_ n1352 n1353 n1008 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_10_ PC_6_ n1348 n1351 n1009 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_8_ n1359 n1561 n1010 +0-1 1 +-11 1 +.names n1008 n1009 n1010 n1007 +111 1 +.names PC_8_ PC_6_ n1352 n1353 n1012 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_9_ PC_5_ n1348 n1351 n1013 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_7_ n1359 n1562 n1014 +0-1 1 +-11 1 +.names n1012 n1013 n1014 n1011 +111 1 +.names PC_7_ PC_5_ n1352 n1353 n1016 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_8_ PC_4_ n1348 n1351 n1017 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_6_ n1359 n1563 n1018 +0-1 1 +-11 1 +.names n1016 n1017 n1018 n1015 +111 1 +.names PC_6_ PC_4_ n1352 n1353 n1020 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_7_ PC_3_ n1348 n1351 n1021 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_5_ n1359 n1564 n1022 +0-1 1 +-11 1 +.names n1020 n1021 n1022 n1019 +111 1 +.names PC_5_ PC_3_ n1352 n1353 n1024 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_6_ PC_2_ n1348 n1351 n1025 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_4_ n1359 n1565 n1026 +0-1 1 +-11 1 +.names n1024 n1025 n1026 n1023 +111 1 +.names PC_4_ PC_2_ n1352 n1353 n1028 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_5_ PC_1_ n1348 n1351 n1029 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_3_ n1359 n1566 n1030 +0-1 1 +-11 1 +.names n1028 n1029 n1030 n1027 +111 1 +.names PC_3_ PC_1_ n1352 n1353 n1032 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_4_ PC_0_ n1348 n1351 n1033 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_2_ n1359 n1567 n1034 +0-1 1 +-11 1 +.names n1032 n1033 n1034 n1031 +111 1 +.names PC_2_ PC_0_ n1352 n1353 n1036 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PC_27_ PC_3_ n1348 n1351 n1037 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names PC_1_ n1359 n1568 n1038 +0-1 1 +-11 1 +.names n1036 n1037 n1038 n1035 +111 1 +.names PC_27_ PC_1_ n1352 n1353 n1040 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names PC_26_ PC_2_ n1348 n1351 n1041 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names PC_0_ n1359 n1569 n1042 +0-1 1 +-11 1 +.names n1040 n1041 n1042 n1039 +111 1 +.names PD_26_ PD_0_ n1352 n1353 n1044 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names PD_25_ PD_1_ n1348 n1351 n1045 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names PD_27_ n1359 n1570 n1046 +0-1 1 +-11 1 +.names n1044 n1045 n1046 n1043 +111 1 +.names PD_27_ PD_25_ n1352 n1353 n1048 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_24_ PD_0_ n1348 n1351 n1049 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names PD_26_ n1359 n1571 n1050 +0-1 1 +-11 1 +.names n1048 n1049 n1050 n1047 +111 1 +.names PD_26_ PD_24_ n1352 n1353 n1052 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_27_ PD_23_ n1348 n1351 n1053 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_25_ n1359 n1572 n1054 +0-1 1 +-11 1 +.names n1052 n1053 n1054 n1051 +111 1 +.names PD_25_ PD_23_ n1352 n1353 n1056 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_26_ PD_22_ n1348 n1351 n1057 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_24_ n1359 n1573 n1058 +0-1 1 +-11 1 +.names n1056 n1057 n1058 n1055 +111 1 +.names PD_24_ PD_22_ n1352 n1353 n1060 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_25_ PD_21_ n1348 n1351 n1061 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_23_ n1359 n1574 n1062 +0-1 1 +-11 1 +.names n1060 n1061 n1062 n1059 +111 1 +.names PD_23_ PD_21_ n1352 n1353 n1064 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_24_ PD_20_ n1348 n1351 n1065 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_22_ n1359 n1575 n1066 +0-1 1 +-11 1 +.names n1064 n1065 n1066 n1063 +111 1 +.names PD_22_ PD_20_ n1352 n1353 n1068 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_23_ PD_19_ n1348 n1351 n1069 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_21_ n1359 n1576 n1070 +0-1 1 +-11 1 +.names n1068 n1069 n1070 n1067 +111 1 +.names PD_21_ PD_19_ n1352 n1353 n1072 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_22_ PD_18_ n1348 n1351 n1073 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_20_ n1359 n1577 n1074 +0-1 1 +-11 1 +.names n1072 n1073 n1074 n1071 +111 1 +.names PD_20_ PD_18_ n1352 n1353 n1076 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_21_ PD_17_ n1348 n1351 n1077 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_19_ n1359 n1578 n1078 +0-1 1 +-11 1 +.names n1076 n1077 n1078 n1075 +111 1 +.names PD_19_ PD_17_ n1352 n1353 n1080 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_20_ PD_16_ n1348 n1351 n1081 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_18_ n1359 n1579 n1082 +0-1 1 +-11 1 +.names n1080 n1081 n1082 n1079 +111 1 +.names PD_18_ PD_16_ n1352 n1353 n1084 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_19_ PD_15_ n1348 n1351 n1085 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_17_ n1359 n1580 n1086 +0-1 1 +-11 1 +.names n1084 n1085 n1086 n1083 +111 1 +.names PD_17_ PD_15_ n1352 n1353 n1088 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_18_ PD_14_ n1348 n1351 n1089 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_16_ n1359 n1581 n1090 +0-1 1 +-11 1 +.names n1088 n1089 n1090 n1087 +111 1 +.names PD_16_ PD_14_ n1352 n1353 n1092 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_17_ PD_13_ n1348 n1351 n1093 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_15_ n1359 n1582 n1094 +0-1 1 +-11 1 +.names n1092 n1093 n1094 n1091 +111 1 +.names PD_15_ PD_13_ n1352 n1353 n1096 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_16_ PD_12_ n1348 n1351 n1097 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_14_ n1359 n1583 n1098 +0-1 1 +-11 1 +.names n1096 n1097 n1098 n1095 +111 1 +.names PD_14_ PD_12_ n1352 n1353 n1100 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_15_ PD_11_ n1348 n1351 n1101 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_13_ n1359 n1584 n1102 +0-1 1 +-11 1 +.names n1100 n1101 n1102 n1099 +111 1 +.names PD_13_ PD_11_ n1352 n1353 n1104 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_14_ PD_10_ n1348 n1351 n1105 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_12_ n1359 n1585 n1106 +0-1 1 +-11 1 +.names n1104 n1105 n1106 n1103 +111 1 +.names PD_12_ PD_10_ n1352 n1353 n1108 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_13_ PD_9_ n1348 n1351 n1109 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_11_ n1359 n1586 n1110 +0-1 1 +-11 1 +.names n1108 n1109 n1110 n1107 +111 1 +.names PD_11_ PD_9_ n1352 n1353 n1112 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_12_ PD_8_ n1348 n1351 n1113 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_10_ n1359 n1587 n1114 +0-1 1 +-11 1 +.names n1112 n1113 n1114 n1111 +111 1 +.names PD_10_ PD_8_ n1352 n1353 n1116 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_11_ PD_7_ n1348 n1351 n1117 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_9_ n1359 n1588 n1118 +0-1 1 +-11 1 +.names n1116 n1117 n1118 n1115 +111 1 +.names PD_9_ PD_7_ n1352 n1353 n1120 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_10_ PD_6_ n1348 n1351 n1121 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_8_ n1359 n1589 n1122 +0-1 1 +-11 1 +.names n1120 n1121 n1122 n1119 +111 1 +.names PD_8_ PD_6_ n1352 n1353 n1124 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_9_ PD_5_ n1348 n1351 n1125 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_7_ n1359 n1590 n1126 +0-1 1 +-11 1 +.names n1124 n1125 n1126 n1123 +111 1 +.names PD_7_ PD_5_ n1352 n1353 n1128 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_8_ PD_4_ n1348 n1351 n1129 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_6_ n1359 n1591 n1130 +0-1 1 +-11 1 +.names n1128 n1129 n1130 n1127 +111 1 +.names PD_6_ PD_4_ n1352 n1353 n1132 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_7_ PD_3_ n1348 n1351 n1133 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_5_ n1359 n1592 n1134 +0-1 1 +-11 1 +.names n1132 n1133 n1134 n1131 +111 1 +.names PD_5_ PD_3_ n1352 n1353 n1136 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_6_ PD_2_ n1348 n1351 n1137 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_4_ n1359 n1593 n1138 +0-1 1 +-11 1 +.names n1136 n1137 n1138 n1135 +111 1 +.names PD_4_ PD_2_ n1352 n1353 n1140 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_5_ PD_1_ n1348 n1351 n1141 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_3_ n1359 n1594 n1142 +0-1 1 +-11 1 +.names n1140 n1141 n1142 n1139 +111 1 +.names PD_3_ PD_1_ n1352 n1353 n1144 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_4_ PD_0_ n1348 n1351 n1145 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_2_ n1359 n1595 n1146 +0-1 1 +-11 1 +.names n1144 n1145 n1146 n1143 +111 1 +.names PD_2_ PD_0_ n1352 n1353 n1148 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names PD_27_ PD_3_ n1348 n1351 n1149 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names PD_1_ n1359 n1596 n1150 +0-1 1 +-11 1 +.names n1148 n1149 n1150 n1147 +111 1 +.names PD_27_ PD_1_ n1352 n1353 n1152 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names PD_26_ PD_2_ n1348 n1351 n1153 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names PD_0_ n1359 n1597 n1154 +0-1 1 +-11 1 +.names n1152 n1153 n1154 n1151 +111 1 +.names Pdata_48_ PD_23_ n1155 +01 1 +10 1 +.names Pdata_51_ PD_18_ n1156 +01 1 +10 1 +.names Pdata_45_ PC_26_ n1158 +01 1 +10 1 +.names Pdata_38_ PC_5_ n1159 +01 1 +10 1 +.names n375 n385 n432 n572 n1160 +10-- 1 +1-10 1 +.names Pdata_52_ PD_11_ n1163 +01 1 +10 1 +.names Pdata_56_ PD_19_ n1164 +01 1 +10 1 +.names n1164 n546 n1165 +01 1 +10 1 +.names Pdata_60_ PD_24_ n1166 +01 1 +10 1 +.names Pdata_58_ PD_27_ n1167 +01 1 +10 1 +.names n460 n475 n1168 +11 1 +00 1 +.names Pdata_42_ PC_3_ n1169 +01 1 +10 1 +.names n220 n1155 n1184 n1170 +0-0 1 +-00 1 +.names n254 n835 n1172 +11 1 +00 1 +.names Pencrypt_mode_0_ Pencrypt_0_ n1173 +11 1 +00 1 +.names Pcount_2_ Pcount_1_ Pcount_0_ n1177 +0-- 1 +-0- 1 +--0 1 +.names n220 n1156 n1184 +00 1 +.names n220 n1156 n1185 +11 1 +.names n915 n1155 n1186 +00 1 +.names n1184 n209 n1187 +11 1 +.names n201 n914 n915 n1188 +0-- 1 +-0- 1 +--1 1 +.names n201 n209 n914 n1189 +0-- 1 +-0- 1 +--0 1 +.names n269 n275 n835 n1198 +1-- 1 +-0- 1 +--0 1 +.names n275 n240 n1199 +11 1 +.names n266 n835 n1200 +10 1 +.names n266 n269 n275 n1201 +010 1 +.names n275 n274 n835 n1202 +1-- 1 +-0- 1 +--0 1 +.names n254 n266 n1199 n1204 +011 1 +.names n1200 n295 n254 n1205 +111 1 +.names n278 n280 n1204 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n1281 +1- 1 +-0 1 +.names n629 n776 n1167 n1289 +1-- 1 +-1- 1 +--0 1 +.names n775 n1167 n1292 +1- 1 +-0 1 +.names n776 n766 n1293 +11 1 +.names n775 n1289 n1295 +00 1 +.names n605 n781 n1297 +0- 1 +-0 1 +.names n615 n780 n1298 +1- 1 +-0 1 +.names n607 n781 n1300 +00 1 +.names n873 n1167 n1301 +1- 1 +-1 1 +.names n1164 n546 n1303 +11 1 +.names n895 n729 n1318 +1- 1 +-1 1 +.names n735 n737 n728 n731 n1319 +1111 1 +.names n1319 n723 n714 n1321 +111 1 +.names n781 n1167 n1293 n1323 +101 1 +.names n629 n1301 n1324 +1- 1 +-1 1 +.names n605 n1293 n1325 +00 1 +.names n625 n765 n769 n771 n1326 +1110 1 +.names n215 n554 n1329 +11 1 +.names n801 n722 n1340 +1- 1 +-1 1 +.names n751 n814 n1340 n1341 +0-- 1 +-0- 1 +--0 1 +.names n924 n1358 n1345 +1- 1 +-0 1 +.names Pencrypt_mode_0_ n1345 n1347 +1- 1 +-1 1 +.names n929 n1347 n1348 +0- 1 +-1 1 +.names Pencrypt_mode_0_ n1345 n1350 +0- 1 +-1 1 +.names n929 n1350 n1351 +0- 1 +-1 1 +.names n929 n1347 n1352 +1- 1 +-1 1 +.names n929 n1350 n1353 +1- 1 +-1 1 +.names Preset_0_ n92 n1354 +1- 1 +-0 1 +.names Pencrypt_0_ n1354 n1356 +1- 1 +-1 1 +.names Pencrypt_0_ n1354 n1357 +0- 1 +-1 1 +.names n1173 n1 n1358 +1- 1 +-1 1 +.names n924 n1358 n1359 +1- 1 +-1 1 +.names n243 n261 n269 n1598 n1369 +0--1 1 +-1-1 1 +--01 1 +.names n254 n266 n295 n1600 n1371 +0--0 1 +-110 1 +.names n281 n294 n835 n1372 +11- 1 +1-1 1 +-10 1 +.names n323 n326 n328 n355 n1373 +1-1- 1 +10-1 1 +.names n344 n357 n1373 n1375 +11- 1 +1-0 1 +-00 1 +.names n319 n323 n1216 n1376 +00- 1 +0-0 1 +-10 1 +.names n220 n228 n914 n1617 n1378 +1--0 1 +-0-0 1 +--10 1 +.names n878 n1166 n1295 n1380 +00- 1 +0-1 1 +-11 1 +.names n642 n647 n1625 n1382 +1-1 1 +-01 1 +.names n207 n914 n1170 n1383 +00- 1 +0-1 1 +-11 1 +.names n275 n834 n1200 n262 n1384 +11-- 1 +1-11 1 +.names n220 n222 n228 n230 n1385 +--11 1 +011- 1 +.names n228 n914 n915 n1185 n1386 +1--1 1 +-011 1 +.names Pdata_in_6_ n1 n1538 n1387 +00- 1 +0-1 1 +-11 1 +.names Pinreg_6_ n1 n1528 n1388 +00- 1 +0-1 1 +-11 1 +.names Pinreg_14_ n1 n1517 n1389 +00- 1 +0-1 1 +-11 1 +.names Pinreg_22_ n1 n1510 n1390 +00- 1 +0-1 1 +-11 1 +.names Pinreg_30_ n1 n1503 n1391 +00- 1 +0-1 1 +-11 1 +.names Pinreg_38_ n1 n1483 n1392 +00- 1 +0-1 1 +-11 1 +.names Pinreg_46_ n1 n1472 n1393 +00- 1 +0-1 1 +-11 1 +.names Pinreg_54_ n1 n234 n1394 +00- 1 +0-1 1 +-11 1 +.names Pdata_in_4_ n1 n1539 n1395 +00- 1 +0-1 1 +-11 1 +.names Pinreg_4_ n1 n1529 n1396 +00- 1 +0-1 1 +-11 1 +.names Pinreg_12_ n1 n1521 n1397 +00- 1 +0-1 1 +-11 1 +.names Pinreg_20_ n1 n1511 n1398 +00- 1 +0-1 1 +-11 1 +.names Pinreg_28_ n1 n1504 n1399 +00- 1 +0-1 1 +-11 1 +.names Pinreg_36_ n1 n1494 n1400 +00- 1 +0-1 1 +-11 1 +.names Pinreg_44_ n1 n1477 n1401 +00- 1 +0-1 1 +-11 1 +.names Pinreg_52_ n1 n287 n1402 +00- 1 +0-1 1 +-11 1 +.names Pdata_in_2_ n1 n1540 n1403 +00- 1 +0-1 1 +-11 1 +.names Pinreg_2_ n1 n1533 n1404 +00- 1 +0-1 1 +-11 1 +.names Pinreg_10_ n1 n1524 n1405 +00- 1 +0-1 1 +-11 1 +.names Pinreg_18_ n1 n1512 n1406 +00- 1 +0-1 1 +-11 1 +.names Pinreg_26_ n1 n1505 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Pinreg_47_ Pdata_57_ n1 n1425 +00- 1 +-01 1 +0-0 1 +.names Pinreg_55_ Pdata_56_ n1 n1426 +00- 1 +-01 1 +0-0 1 +.names Pdata_in_5_ Pdata_55_ n1 n1427 +00- 1 +-01 1 +0-0 1 +.names Pinreg_5_ Pdata_54_ n1 n1428 +00- 1 +-01 1 +0-0 1 +.names Pinreg_13_ Pdata_53_ n1 n1429 +00- 1 +-01 1 +0-0 1 +.names Pinreg_21_ Pdata_52_ n1 n1430 +00- 1 +-01 1 +0-0 1 +.names Pinreg_29_ Pdata_51_ n1 n1431 +00- 1 +-01 1 +0-0 1 +.names Pinreg_37_ Pdata_50_ n1 n1432 +00- 1 +-01 1 +0-0 1 +.names Pinreg_45_ Pdata_49_ n1 n1433 +00- 1 +-01 1 +0-0 1 +.names Pinreg_53_ Pdata_48_ n1 n1434 +00- 1 +-01 1 +0-0 1 +.names Pdata_in_3_ Pdata_47_ n1 n1435 +00- 1 +-01 1 +0-0 1 +.names Pinreg_3_ Pdata_46_ n1 n1436 +00- 1 +-01 1 +0-0 1 +.names Pinreg_11_ Pdata_45_ n1 n1437 +00- 1 +-01 1 +0-0 1 +.names Pinreg_19_ Pdata_44_ n1 n1438 +00- 1 +-01 1 +0-0 1 +.names Pinreg_27_ Pdata_43_ n1 n1439 +00- 1 +-01 1 +0-0 1 +.names Pinreg_35_ Pdata_42_ n1 n1440 +00- 1 +-01 1 +0-0 1 +.names Pinreg_43_ Pdata_41_ n1 n1441 +00- 1 +-01 1 +0-0 1 +.names Pinreg_51_ Pdata_40_ n1 n1442 +00- 1 +-01 1 +0-0 1 +.names Pdata_in_1_ Pdata_39_ n1 n1443 +00- 1 +-01 1 +0-0 1 +.names Pinreg_1_ Pdata_38_ n1 n1444 +00- 1 +-01 1 +0-0 1 +.names Pinreg_9_ Pdata_37_ n1 n1445 +00- 1 +-01 1 +0-0 1 +.names Pinreg_17_ Pdata_36_ n1 n1446 +00- 1 +-01 1 +0-0 1 +.names Pinreg_25_ Pdata_35_ n1 n1447 +00- 1 +-01 1 +0-0 1 +.names Pinreg_33_ Pdata_34_ n1 n1448 +00- 1 +-01 1 +0-0 1 +.names Pinreg_41_ Pdata_33_ n1 n1449 +00- 1 +-01 1 +0-0 1 +.names Pinreg_49_ Pdata_32_ n1 n1450 +00- 1 +-01 1 +0-0 1 +.names Pcount_2_ n923 n1664 n1451 +0-1 1 +-11 1 +.names Pcount_1_ n925 n1665 n1452 +0-1 1 +-11 1 +.names Pcount_3_ Pcount_2_ Pcount_1_ n1666 n1453 +--00 1 +11-0 1 +.names Pencrypt_mode_0_ Pencrypt_0_ n1 n1454 +00- 1 +0-1 1 +-00 1 +.names n201 n209 n207 n914 n1457 +1--- 1 +-0-- 1 +--0- 1 +---1 1 +.names n220 n795 n911 n1189 n1458 +1-0- 1 +-10- 1 +1--1 1 +-1-1 1 +.names n561 n914 n1184 n1188 n1459 +0-0- 1 +-00- 1 +0--1 1 +-0-1 1 +.names n261 n266 n269 n835 n1464 +1--- 1 +-1-- 1 +--0- 1 +---1 1 +.names n357 n588 n591 n1465 +1-- 1 +-0- 1 +--0 1 +.names n355 n588 n1217 n1466 +0-- 1 +-0- 1 +--1 1 +.names n585 n1220 n340 n357 n1468 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n1158 n355 n337 n1470 +1-- 1 +-1- 1 +--1 1 +.names n326 n357 n420 n1470 n1469 +0--1 1 +-1-1 1 +--11 1 +.names n357 n588 n591 n1471 +0-- 1 +-0- 1 +--0 1 +.names Pdata_25_ n1675 n1472 +01 1 +10 1 +.names n392 n432 n445 n1473 +1-- 1 +-0- 1 +--0 1 +.names n432 n447 n445 n1475 +0-- 1 +-0- 1 +--0 1 +.names n1475 n401 n375 n452 n1474 +11-- 1 +1-1- 1 +1--1 1 +.names n369 n444 n570 n1476 +1-- 1 +-0- 1 +--1 1 +.names n407 Pdata_17_ n1477 +01 1 +10 1 +.names n422 Pdata_9_ n1478 +01 1 +10 1 +.names Pdata_1_ n1678 n1479 +01 1 +10 1 +.names n475 n476 n1480 +0- 1 +-1 1 +.names n459 n1257 n1482 +0- 1 +-1 1 +.names n496 Pdata_26_ n1483 +01 1 +10 1 +.names n526 n647 n654 n1486 +1-- 1 +-0- 1 +--1 1 +.names n511 n546 n1484 +1- 1 +-0 1 +.names n525 n522 n1487 +1- 1 +-1 1 +.names n542 n549 n647 n1488 +1-- 1 +-0- 1 +--0 1 +.names n522 n658 n1163 n1274 n1489 +1-0- 1 +-10- 1 +1--1 1 +-1-1 1 +.names n529 n549 n1265 n1275 n1490 +1-0- 1 +-00- 1 +1--1 1 +-0-1 1 +.names n648 n1163 n1165 n1493 +1-- 1 +-1- 1 +--0 1 +.names n513 n517 n526 n1493 n1492 +-1-1 1 +0-11 1 +.names n533 Pdata_18_ n1494 +01 1 +10 1 +.names n648 n647 n1275 n1495 +1-- 1 +-1- 1 +--1 1 +.names n529 n510 n654 n1497 +1-- 1 +-1- 1 +--1 1 +.names n1497 n508 n1275 n1496 +11- 1 +1-1 1 +.names n655 n658 n1163 n1272 n1499 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names Pdata_10_ n1680 n1500 +01 1 +10 1 +.names n392 n432 n434 n449 n1502 +10-- 1 +-01- 1 +1--1 1 +--11 1 +.names n575 Pdata_27_ n1503 +01 1 +10 1 +.names Pdata_19_ n1684 n1504 +01 1 +10 1 +.names n633 Pdata_11_ n1505 +01 1 +10 1 +.names n525 n646 n1272 n1275 n1506 +11-- 1 +-10- 1 +1--1 1 +--01 1 +.names Pdata_3_ n1688 n1507 +01 1 +10 1 +.names n510 n549 n1270 n1508 +0-- 1 +-0- 1 +--1 1 +.names n510 n515 n546 n1509 +1-- 1 +-0- 1 +--0 1 +.names n661 Pdata_28_ n1510 +01 1 +10 1 +.names n680 Pdata_20_ n1511 +01 1 +10 1 +.names n693 Pdata_12_ n1512 +01 1 +10 1 +.names n469 n475 n1248 n1514 +10- 1 +1-1 1 +-11 1 +.names n701 Pdata_4_ n1515 +01 1 +10 1 +.names n742 n752 n755 n1318 n1516 +0-1- 1 +-11- 1 +0--1 1 +-1-1 1 +.names Pdata_29_ n1690 n1517 +01 1 +10 1 +.names n772 n777 n1300 n1520 +0-- 1 +-0- 1 +--1 1 +.names n775 n1323 n1520 n1518 +1-1 1 +-01 1 +.names Pdata_21_ n1692 n1521 +01 1 +10 1 +.names n228 n786 n914 n1187 n1522 +0-1- 1 +-11- 1 +0--0 1 +-1-0 1 +.names Pdata_13_ n1695 n1524 +01 1 +10 1 +.names n729 n730 n738 n724 n1525 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n826 Pdata_30_ n1528 +01 1 +10 1 +.names n836 Pdata_22_ n1529 +01 1 +10 1 +.names n460 n491 n846 n1248 n1530 +0--1 1 +-0-1 1 +--11 1 +.names n470 n475 n495 n675 n1532 +1-1- 1 +-11- 1 +1--0 1 +-1-0 1 +.names Pdata_14_ n1703 n1533 +01 1 +10 1 +.names n629 n1166 n1298 n1324 n1534 +01-- 1 +-11- 1 +0--1 1 +--11 1 +.names n766 n872 n876 n1167 n1537 +01-- 1 +-11- 1 +0--0 1 +--10 1 +.names Pdata_31_ n1709 n1538 +01 1 +10 1 +.names Pdata_23_ n1711 n1539 +01 1 +10 1 +.names n900 Pdata_15_ n1540 +01 1 +10 1 +.names Pdata_7_ n1714 n1541 +01 1 +10 1 +.names Pinreg_48_ Pinreg_27_ n1356 n1357 n1542 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names Pinreg_35_ Pinreg_27_ n1356 n1357 n1543 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_43_ Pinreg_35_ n1356 n1357 n1544 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_51_ Pinreg_43_ n1356 n1357 n1545 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_51_ Pdata_in_2_ n1356 n1357 n1546 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names Pinreg_2_ Pdata_in_2_ n1356 n1357 n1547 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_10_ Pinreg_2_ n1356 n1357 n1548 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_18_ Pinreg_10_ n1356 n1357 n1549 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_26_ Pinreg_18_ n1356 n1357 n1550 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_34_ Pinreg_26_ n1356 n1357 n1551 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_42_ Pinreg_34_ n1356 n1357 n1552 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_50_ Pinreg_42_ n1356 n1357 n1553 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_50_ Pdata_in_1_ n1356 n1357 n1554 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names Pinreg_1_ Pdata_in_1_ n1356 n1357 n1555 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_9_ Pinreg_1_ n1356 n1357 n1556 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_17_ Pinreg_9_ n1356 n1357 n1557 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_25_ Pinreg_17_ n1356 n1357 n1558 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_33_ Pinreg_25_ n1356 n1357 n1559 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_41_ Pinreg_33_ n1356 n1357 n1560 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_49_ Pinreg_41_ n1356 n1357 n1561 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_49_ Pdata_in_0_ n1356 n1357 n1562 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names Pinreg_0_ Pdata_in_0_ n1356 n1357 n1563 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_8_ Pinreg_0_ n1356 n1357 n1564 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_16_ Pinreg_8_ n1356 n1357 n1565 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_24_ Pinreg_16_ n1356 n1357 n1566 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_32_ Pinreg_24_ n1356 n1357 n1567 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_40_ Pinreg_32_ n1356 n1357 n1568 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_48_ Pinreg_40_ n1356 n1357 n1569 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_54_ Pdata_in_3_ n1356 n1357 n1570 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names Pinreg_3_ Pdata_in_3_ n1356 n1357 n1571 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_11_ Pinreg_3_ n1356 n1357 n1572 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_19_ Pinreg_11_ n1356 n1357 n1573 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_19_ Pdata_in_4_ n1356 n1357 n1574 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names Pinreg_4_ Pdata_in_4_ n1356 n1357 n1575 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_12_ Pinreg_4_ n1356 n1357 n1576 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_20_ Pinreg_12_ n1356 n1357 n1577 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_28_ Pinreg_20_ n1356 n1357 n1578 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_36_ Pinreg_28_ n1356 n1357 n1579 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_44_ Pinreg_36_ n1356 n1357 n1580 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_52_ Pinreg_44_ n1356 n1357 n1581 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_52_ Pdata_in_5_ n1356 n1357 n1582 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names Pinreg_5_ Pdata_in_5_ n1356 n1357 n1583 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_13_ Pinreg_5_ n1356 n1357 n1584 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_21_ Pinreg_13_ n1356 n1357 n1585 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_29_ Pinreg_21_ n1356 n1357 n1586 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_37_ Pinreg_29_ n1356 n1357 n1587 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_45_ Pinreg_37_ n1356 n1357 n1588 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_53_ Pinreg_45_ n1356 n1357 n1589 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_53_ Pdata_in_6_ n1356 n1357 n1590 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names Pinreg_6_ Pdata_in_6_ n1356 n1357 n1591 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_14_ Pinreg_6_ n1356 n1357 n1592 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_22_ Pinreg_14_ n1356 n1357 n1593 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_30_ Pinreg_22_ n1356 n1357 n1594 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_38_ Pinreg_30_ n1356 n1357 n1595 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_46_ Pinreg_38_ n1356 n1357 n1596 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names Pinreg_54_ Pinreg_46_ n1356 n1357 n1597 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names n264 n269 n292 n1598 +1-- 1 +-1- 1 +--0 1 +.names n270 n273 n835 n1369 n1599 +1-0- 1 +-10- 1 +--00 1 +.names n243 n254 n262 n269 n1600 +00-- 1 +-01- 1 +-0-1 1 +.names n254 n274 n835 n1602 +00- 1 +0-1 1 +.names n317 n355 n1158 n1375 n1604 +--00 1 +000- 1 +.names n317 n326 n1158 n1218 n1605 +011- 1 +-110 1 +.names n458 n477 n851 n1250 n1607 +01-- 1 +-111 1 +.names n460 n477 n851 n1252 n1609 +0--- 1 +-0-- 1 +--0- 1 +---0 1 +.names n508 n1275 n647 n1610 +1-- 1 +-1- 1 +--1 1 +.names n512 n526 n549 n647 n1611 +1--0 1 +-010 1 +.names n647 n1163 n1272 n1496 n1614 +1--0 1 +101- 1 +.names n545 n647 n1165 n1265 n1615 +10-- 1 +-011 1 +.names n230 n789 n1155 n1616 +11- 1 +1-1 1 +-10 1 +.names n914 n1187 n228 n220 n1617 +11-- 1 +1-11 1 +.names n201 n227 n231 n1378 n1619 +1--0 1 +111- 1 +.names n201 n915 n1616 n1620 +001 1 +.names n583 n1218 n1622 +1- 1 +-0 1 +.names n326 n587 n1158 n1622 n1621 +-10- 1 +1-01 1 +.names n344 n357 n1158 n1623 +1-- 1 +-1- 1 +--0 1 +.names n604 n1300 n1325 n1624 +0-- 1 +-0- 1 +--1 1 +.names n647 n1265 n1303 n1625 +1-- 1 +-0- 1 +--1 1 +.names n1163 n1164 n1272 n1382 n1626 +0--0 1 +011- 1 +.names n508 n647 n1163 n1303 n1627 +1--- 1 +-0-- 1 +--0- 1 +---0 1 +.names n477 n847 n849 n1628 +0-- 1 +-1- 1 +--0 1 +.names n375 n432 n1629 +10 1 +.names n375 n403 n438 n1630 +01- 1 +0-1 1 +.names n570 n572 n1629 n1630 n1631 +0--- 1 +-0-- 1 +--1- 1 +---1 1 +.names n851 n849 n1633 +11 1 +.names n477 n852 n1252 n1633 n1632 +0--1 1 +011- 1 +.names n722 n751 n802 n895 n1635 +0--- 1 +-0-- 1 +--0- 1 +---0 1 +.names n777 n779 n862 n1325 n1636 +-1-0 1 +1-10 1 +.names n862 n1167 n1325 n1638 +0-- 1 +-0- 1 +--0 1 +.names n766 n774 n1166 n1295 n1639 +010- 1 +0-01 1 +.names n1166 n1324 n1640 +0- 1 +-1 1 +.names n201 n227 n1186 n1522 n1641 +1--0 1 +111- 1 +.names n201 n561 n788 n790 n1642 +01-- 1 +0-1- 1 +0--1 1 +.names n751 n814 n1318 n1525 n1643 +1--0 1 +110- 1 +.names n751 n802 n1318 n1668 n1645 +0--0 1 +010- 1 +.names n266 n263 n1647 +11 1 +.names n261 n266 n269 n1648 +00- 1 +-01 1 +.names n274 n281 n835 n1201 n1649 +--01 1 +110- 1 +.names n472 n477 n1246 n1530 n1651 +-1-0 1 +011- 1 +.names n477 n493 n848 n850 n1653 +00-- 1 +0-1- 1 +0--1 1 +.names n629 n775 n776 n1654 +0-- 1 +-1- 1 +--1 1 +.names n729 n742 n749 n756 n1655 +1--- 1 +-1-- 1 +--1- 1 +---0 1 +.names n742 n887 n898 n1340 n1656 +11-1 1 +1-01 1 +.names n738 n740 n1657 +0- 1 +-1 1 +.names n738 n803 n814 n817 n1658 +0--1 1 +011- 1 +.names n201 n1184 n1185 n1659 +01- 1 +1-1 1 +-11 1 +.names n207 n1155 n1659 n1660 +10- 1 +1-1 1 +-11 1 +.names n201 n1385 n1386 n1663 +10- 1 +0-0 1 +-00 1 +.names Pcount_2_ Pcount_1_ Pcount_0_ n924 n1664 +1--- 1 +-0-- 1 +--0- 1 +---1 1 +.names Pcount_1_ Pcount_0_ n924 n1665 +1-- 1 +-0- 1 +--1 1 +.names Pcount_3_ Pcount_2_ Pcount_1_ n1666 +1-0 1 +-10 1 +.names n722 n724 n1668 +0- 1 +-1 1 +.names n202 n210 n215 n223 n225 n229 n1458 n1459 n1669 +11110011 1 +.names n331 n424 n1468 n1604 n1605 n1672 +11100 1 +.names n331 n333 n350 n353 n358 n360 n421 n1220 n1675 +11101011 1 +.names n386 n400 n433 n437 n439 n443 n448 n451 n1678 +11111011 1 +.names n516 n521 n541 n1499 n1614 n1615 n1680 +111100 1 +.names n202 n208 n210 n554 n558 n560 n1619 n1620 n1683 +0------- 1 +-1------ 1 +--0----- 1 +---0---- 1 +----1--- 1 +-----1-- 1 +------1- 1 +-------1 1 +.names n331 n336 n350 n590 n593 n1221 n1621 n1623 n1684 +11101101 1 +.names n519 n534 n541 n1506 n1626 n1627 n1688 +111101 1 +.names n741 n757 n760 n1321 n1341 n1516 n1690 +101111 1 +.names n599 n618 n1326 n1518 n1636 n1638 n1639 n1640 n1692 +11110101 1 +.names n199 n210 n794 n1329 n1641 n1642 n1695 +111100 1 +.names n714 n809 n810 n813 n816 n901 n1643 n1645 n1698 +0------- 1 +-0------ 1 +--0----- 1 +---1---- 1 +----1--- 1 +-----0-- 1 +------1- 1 +-------1 1 +.names n262 n264 n269 n1172 n1702 +1001 1 +.names n466 n668 n1254 n1532 n1651 n1653 n1703 +111100 1 +.names n635 n858 n859 n860 n864 n1323 n1326 n1534 n1706 +0------- 1 +-1------ 1 +--1----- 1 +---1---- 1 +----1--- 1 +-----1-- 1 +------0- 1 +-------0 1 +.names n608 n618 n879 n880 n1326 n1537 n1709 +111011 1 +.names n804 n889 n1321 n1655 n1656 n1657 n1658 n1668 n1711 +11110101 1 +.names n202 n910 n913 n917 n1329 n1663 n1714 +101111 1 +.names Pdata_2_ n1683 n1717 +01 1 +10 1 +.names Pdata_5_ n1698 n1718 +01 1 +10 1 +.names Pdata_6_ n1706 n1719 +01 1 +10 1 +.end diff --git a/fpga_flow/benchmarks/MCNC_big20/diffeq.blif b/fpga_flow/benchmarks/MCNC_big20/diffeq.blif new file mode 100644 index 000000000..da068664d --- /dev/null +++ b/fpga_flow/benchmarks/MCNC_big20/diffeq.blif @@ -0,0 +1,3834 @@ +.model TOP +.inputs PCLK PRESET Pdxport_0_0_ Pdxport_1_1_ Pdxport_2_2_ Pdxport_3_3_ \ +Pdxport_4_4_ Pdxport_5_5_ Pdxport_6_6_ Pdxport_7_7_ Pdxport_8_8_ Pdxport_9_9_ \ +Pdxport_10_10_ Pdxport_11_11_ Paport_0_0_ Paport_1_1_ Paport_2_2_ Paport_3_3_ \ +Paport_4_4_ Paport_5_5_ Paport_6_6_ Paport_7_7_ Paport_8_8_ Paport_9_9_ \ +Paport_10_10_ Paport_11_11_ Preset_0_0_ Pready_0_0_ +.outputs PDN Pnext_0_0_ Pover_0_0_ +.latch N_N4053 N_N4054 re PCLK 2 +.latch N_N3744 N_N3745 re PCLK 2 +.latch N_N3406 N_N4119 re PCLK 2 +.latch N_N3825 N_N3826 re PCLK 2 +.latch N_N3817 N_N3818 re PCLK 2 +.latch N_N3078 N_N3345 re PCLK 2 +.latch N_N3409 N_N3924 re PCLK 2 +.latch N_N3814 N_N3815 re PCLK 2 +.latch N_N3690 N_N3691 re PCLK 2 +.latch N_N2972 N_N3157 re PCLK 2 +.latch N_N3123 N_N3872 re PCLK 2 +.latch N_N3787 N_N3788 re PCLK 2 +.latch N_N3374 N_N3375 re PCLK 2 +.latch N_N3136 N_N3143 re PCLK 2 +.latch N_N3847 N_N4197 re PCLK 2 +.latch N_N3668 N_N3843 re PCLK 2 +.latch N_N3425 N_N3426 re PCLK 2 +.latch N_N3506 N_N4118 re PCLK 2 +.latch N_N3579 N_N3580 re PCLK 2 +.latch N_N3174 N_N3175 re PCLK 2 +.latch N_N3070 N_N3071 re PCLK 2 +.latch N_N3349 N_N3808 re PCLK 2 +.latch N_N3227 N_N3923 re PCLK 2 +.latch N_N3249 N_N3250 re PCLK 2 +.latch N_N3486 N_N4221 re PCLK 2 +.latch N_N3068 N_N3069 re PCLK 2 +.latch N_N3216 N_N3464 re PCLK 2 +.latch N_N3454 N_N3535 re PCLK 2 +.latch N_N2952 N_N3871 re PCLK 2 +.latch N_N3247 N_N3248 re PCLK 2 +.latch N_N3334 N_N4180 re PCLK 2 +.latch N_N3310 N_N3311 re PCLK 2 +.latch N_N3215 N_N3442 re PCLK 2 +.latch N_N3980 N_N3981 re PCLK 2 +.latch N_N3413 N_N3842 re PCLK 2 +.latch N_N3104 N_N3105 re PCLK 2 +.latch N_N2997 N_N4133 re PCLK 2 +.latch N_N3661 N_N4117 re PCLK 2 +.latch N_N2973 N_N3420 re PCLK 2 +.latch N_N3640 N_N3761 re PCLK 2 +.latch N_N3009 N_N3062 re PCLK 2 +.latch N_N3615 N_N4071 re PCLK 2 +.latch N_N3859 N_N4227 re PCLK 2 +.latch N_N3129 N_N3807 re PCLK 2 +.latch N_N3222 N_N4145 re PCLK 2 +.latch N_N3652 N_N3922 re PCLK 2 +.latch N_N2992 N_N3516 re PCLK 2 +.latch N_N3488 N_N3489 re PCLK 2 +.latch N_N4029 N_N4030 re PCLK 2 +.latch N_N3050 N_N3540 re PCLK 2 +.latch N_N3487 N_N3513 re PCLK 2 +.latch N_N2963 N_N4083 re PCLK 2 +.latch N_N3431 N_N3841 re PCLK 2 +.latch N_N3717 N_N4018 re PCLK 2 +.latch N_N3801 N_N3971 re PCLK 2 +.latch N_N4231 N_N4232 re PCLK 2 +.latch N_N3276 N_N4246 re PCLK 2 +.latch N_N3173 N_N3806 re PCLK 2 +.latch N_N3723 N_N3992 re PCLK 2 +.latch N_N4085 N_N4086 re PCLK 2 +.latch N_N4229 N_N4230 re PCLK 2 +.latch N_N3599 N_N4212 re PCLK 2 +.latch N_N3005 Pnext_0_0_ re PCLK 2 +.latch N_N3162 N_N3626 re PCLK 2 +.latch N_N3106 N_N3965 re PCLK 2 +.latch N_N3570 N_N3890 re PCLK 2 +.latch N_N3287 NDN3_11 re PCLK 2 +.latch N_N3231 NDN5_10 re PCLK 2 +.latch N_N3785 N_N3786 re PCLK 2 +.latch N_N3596 N_N4171 re PCLK 2 +.latch N_N3063 NDN5_16 re PCLK 2 +.latch N_N3798 N_N3799 re PCLK 2 +.latch N_N3315 N_N3844 re PCLK 2 +.latch N_N3152 N_N3196 re PCLK 2 +.latch N_N3277 N_N4126 re PCLK 2 +.latch N_N3400 N_N3681 re PCLK 2 +.latch N_N3049 N_N3679 re PCLK 2 +.latch N_N3339 N_N3340 re PCLK 2 +.latch N_N3969 N_N4116 re PCLK 2 +.latch N_N3316 N_N3810 re PCLK 2 +.latch N_N2974 N_N3235 re PCLK 2 +.latch N_N3053 N_N3283 re PCLK 2 +.latch N_N3399 N_N3716 re PCLK 2 +.latch N_N3048 N_N3701 re PCLK 2 +.latch N_N3524 N_N3921 re PCLK 2 +.latch N_N3558 N_N3625 re PCLK 2 +.latch N_N3115 N_N3751 re PCLK 2 +.latch N_N3456 N_N3736 re PCLK 2 +.latch N_N3772 N_N3870 re PCLK 2 +.latch N_N4023 N_N4024 re PCLK 2 +.latch N_N3804 N_N3876 re PCLK 2 +.latch N_N3133 N_N3840 re PCLK 2 +.latch N_N4020 N_N4021 re PCLK 2 +.latch N_N3189 N_N3932 re PCLK 2 +.latch N_N3811 NLC1_2 re PCLK 2 +.latch N_N3132 N_N3805 re PCLK 2 +.latch N_N3259 N_N3700 re PCLK 2 +.latch N_N3015 N_N3735 re PCLK 2 +.latch N_N2987 NLak3_2 re PCLK 2 +.latch N_N3465 NLak3_9 re PCLK 2 +.latch N_N3003 N_N3906 re PCLK 2 +.latch N_N2953 N_N3388 re PCLK 2 +.latch N_N4007 N_N4057 re PCLK 2 +.latch N_N2969 N_N3011 re PCLK 2 +.latch N_N3037 N_N3346 re PCLK 2 +.latch N_N2998 N_N3677 re PCLK 2 +.latch N_N3146 N_N4165 re PCLK 2 +.latch N_N3010 N_N4080 re PCLK 2 +.latch N_N3372 N_N3373 re PCLK 2 +.latch N_N3616 N_N3709 re PCLK 2 +.latch N_N3483 N_N4206 re PCLK 2 +.latch N_N3119 N_N3324 re PCLK 2 +.latch N_N3325 N_N3575 re PCLK 2 +.latch N_N3058 N_N4159 re PCLK 2 +.latch N_N3638 NAK5_2 re PCLK 2 +.latch N_N3915 N_N3916 re PCLK 2 +.latch N_N3666 N_N3743 re PCLK 2 +.latch N_N3052 N_N4242 re PCLK 2 +.latch N_N2966 N_N3312 re PCLK 2 +.latch N_N3595 N_N3733 re PCLK 2 +.latch N_N3664 N_N3774 re PCLK 2 +.latch N_N3332 N_N4214 re PCLK 2 +.latch N_N2965 N_N3294 re PCLK 2 +.latch N_N3795 N_N3796 re PCLK 2 +.latch N_N3523 N_N3574 re PCLK 2 +.latch N_N3653 N_N3791 re PCLK 2 +.latch N_N3266 N_N3480 re PCLK 2 +.latch N_N3914 N_N4243 re PCLK 2 +.latch N_N3263 N_N3940 re PCLK 2 +.latch N_N3241 N_N3509 re PCLK 2 +.latch N_N3913 N_N4015 re PCLK 2 +.latch N_N2988 N_N2989 re PCLK 2 +.latch N_N2955 N_N3919 re PCLK 2 +.latch N_N3389 N_N3578 re PCLK 2 +.latch N_N3240 N_N3529 re PCLK 2 +.latch N_N4174 N_N4222 re PCLK 2 +.latch N_N3909 N_N3910 re PCLK 2 +.latch N_N2956 N_N3868 re PCLK 2 +.latch N_N3946 N_N3947 re PCLK 2 +.latch N_N3390 N_N4181 re PCLK 2 +.latch N_N3695 N_N3793 re PCLK 2 +.latch N_N3004 N_N3822 re PCLK 2 +.latch N_N3153 N_N3813 re PCLK 2 +.latch N_N4113 N_N4114 re PCLK 2 +.latch N_N3156 N_N4134 re PCLK 2 +.latch N_N2961 N_N3866 re PCLK 2 +.latch N_N4217 N_N4218 re PCLK 2 +.latch N_N3589 N_N3939 re PCLK 2 +.latch N_N3614 N_N3776 re PCLK 2 +.latch N_N3145 N_N3387 re PCLK 2 +.latch N_N3051 N_N4194 re PCLK 2 +.latch N_N3014 N_N3821 re PCLK 2 +.latch N_N3705 N_N3882 re PCLK 2 +.latch N_N4166 N_N4167 re PCLK 2 +.latch N_N3201 N_N3800 re PCLK 2 +.latch N_N3192 N_N4237 re PCLK 2 +.latch N_N3416 N_N3417 re PCLK 2 +.latch N_N3592 N_N3918 re PCLK 2 +.latch N_N3437 N_N4158 re PCLK 2 +.latch N_N2976 N_N3630 re PCLK 2 +.latch N_N3103 N_N3344 re PCLK 2 +.latch N_N3206 N_N4072 re PCLK 2 +.latch N_N3273 N_N3274 re PCLK 2 +.latch N_N3472 N_N3473 re PCLK 2 +.latch N_N3511 N_N4205 re PCLK 2 +.latch N_N4110 N_N4111 re PCLK 2 +.latch N_N3008 N_N3680 re PCLK 2 +.latch N_N3432 N_N3838 re PCLK 2 +.latch N_N2984 N_N3262 re PCLK 2 +.latch N_N4098 N_N4099 re PCLK 2 +.latch N_N2975 N_N3607 re PCLK 2 +.latch N_N3320 N_N3323 re PCLK 2 +.latch N_N3611 N_N3612 re PCLK 2 +.latch N_N4032 N_N4079 re PCLK 2 +.latch N_N3620 PDN re PCLK 2 +.latch N_N3102 N_N3457 re PCLK 2 +.latch N_N3155 N_N3445 re PCLK 2 +.latch N_N3559 N_N3794 re PCLK 2 +.latch N_N3662 N_N3663 re PCLK 2 +.latch N_N3007 N_N3715 re PCLK 2 +.latch N_N4038 N_N4039 re PCLK 2 +.latch N_N2983 N_N3280 re PCLK 2 +.latch N_N4238 N_N4239 re PCLK 2 +.latch N_N3987 N_N3988 re PCLK 2 +.latch N_N3172 N_N3433 re PCLK 2 +.latch N_N4074 N_N4075 re PCLK 2 +.latch N_N3038 N_N3468 re PCLK 2 +.latch N_N4044 N_N4045 re PCLK 2 +.latch N_N3481 N_N3482 re PCLK 2 +.latch N_N3086 N_N3832 re PCLK 2 +.latch N_N3210 N_N3304 re PCLK 2 +.latch N_N3040 N_N3750 re PCLK 2 +.latch N_N3633 N_N3634 re PCLK 2 +.latch N_N3177 N_N3293 re PCLK 2 +.latch N_N3658 N_N3659 re PCLK 2 +.latch N_N3671 N_N4252 re PCLK 2 +.latch N_N3449 N_N3912 re PCLK 2 +.latch N_N3117 N_N3862 re PCLK 2 +.latch N_N3209 N_N3221 re PCLK 2 +.latch N_N3113 N_N3875 re PCLK 2 +.latch N_N3602 N_N3949 re PCLK 2 +.latch N_N3322 N_N3908 re PCLK 2 +.latch N_N3710 N_N3711 re PCLK 2 +.latch N_N3244 N_N3931 re PCLK 2 +.latch N_N2996 N_N3469 re PCLK 2 +.latch N_N3435 N_N3436 re PCLK 2 +.latch N_N3027 N_N3974 re PCLK 2 +.latch N_N3904 N_N3905 re PCLK 2 +.latch N_N3740 N_N3741 re PCLK 2 +.latch N_N3165 N_N3369 re PCLK 2 +.latch N_N3144 N_N3164 re PCLK 2 +.latch N_N3499 N_N3500 re PCLK 2 +.latch N_N3200 N_N3996 re PCLK 2 +.latch N_N2979 N_N3356 re PCLK 2 +.latch N_N3147 N_N4093 re PCLK 2 +.latch N_N3061 Pover_0_0_ re PCLK 2 +.latch N_N3586 N_N4224 re PCLK 2 +.latch N_N2980 N_N4027 re PCLK 2 +.latch N_N3305 NDN1_4 re PCLK 2 +.latch N_N2978 N_N3384 re PCLK 2 +.latch N_N3093 N_N4036 re PCLK 2 +.latch N_N3967 N_N3968 re PCLK 2 +.latch N_N3190 N_N4183 re PCLK 2 +.latch N_N3542 NGFDN_3 re PCLK 2 +.latch N_N4089 N_N4090 re PCLK 2 +.latch N_N3091 N_N4004 re PCLK 2 +.latch N_N3204 N_N3205 re PCLK 2 +.latch N_N3191 N_N4136 re PCLK 2 +.latch N_N3101 N_N3303 re PCLK 2 +.latch N_N3352 N_N3533 re PCLK 2 +.latch N_N3335 N_N3336 re PCLK 2 +.latch N_N2964 N_N3961 re PCLK 2 +.latch N_N3057 N_N3331 re PCLK 2 +.latch N_N3202 N_N3203 re PCLK 2 +.latch N_N4028 N_N4236 re PCLK 2 +.latch N_N3321 N_N3884 re PCLK 2 +.latch N_N3366 N_N3367 re PCLK 2 +.latch N_N4139 N_N4140 re PCLK 2 +.latch N_N3476 NDN2_2 re PCLK 2 +.latch N_N4105 N_N4106 re PCLK 2 +.latch N_N3028 N_N3100 re PCLK 2 +.latch N_N3720 N_N4193 re PCLK 2 +.latch N_N3034 N_N3470 re PCLK 2 +.latch N_N3423 N_N3424 re PCLK 2 +.latch N_N3958 N_N3959 re PCLK 2 +.latch N_N3318 N_N3393 re PCLK 2 +.latch N_N4041 N_N4042 re PCLK 2 +.latch N_N3075 N_N3188 re PCLK 2 +.latch N_N4094 N_N4095 re PCLK 2 +.latch N_N3956 N_N3957 re PCLK 2 +.latch N_N3401 N_N3517 re PCLK 2 +.latch N_N4046 N_N4047 re PCLK 2 +.latch N_N2977 N_N3081 re PCLK 2 +.latch N_N2962 N_N3541 re PCLK 2 +.latch N_N3087 N_N4177 re PCLK 2 +.latch N_N3530 NDN3_3 re PCLK 2 +.latch N_N3479 N_N4176 re PCLK 2 +.latch N_N3584 N_N3585 re PCLK 2 +.latch N_N3752 NDN3_8 re PCLK 2 +.latch N_N3503 N_N4209 re PCLK 2 +.latch N_N3823 N_N3824 re PCLK 2 +.latch N_N3130 N_N4208 re PCLK 2 +.latch N_N3895 N_N4120 re PCLK 2 +.latch N_N3707 N_N3708 re PCLK 2 +.latch N_N3941 N_N4220 re PCLK 2 +.latch N_N4254 N_N3999 re PCLK 2 +.latch N_N3314 N_N4223 re PCLK 2 +.latch N_N3178 N_N3179 re PCLK 2 +.latch N_N3963 N_N4179 re PCLK 2 +.latch N_N3474 N_N3475 re PCLK 2 +.latch N_N3194 N_N4132 re PCLK 2 +.latch N_N2958 N_N4182 re PCLK 2 +.latch N_N3163 N_N3797 re PCLK 2 +.latch N_N3213 N_N3214 re PCLK 2 +.latch N_N3193 N_N4070 re PCLK 2 +.latch N_N2957 N_N4135 re PCLK 2 +.latch N_N3042 NLD3_9 re PCLK 2 +.latch N_N3160 NDN5_2 re PCLK 2 +.latch N_N3041 NDN5_3 re PCLK 2 +.latch N_N3284 N_N3778 re PCLK 2 +.latch N_N3739 NDN5_4 re PCLK 2 +.latch N_N3211 N_N3212 re PCLK 2 +.latch N_N3348 NDN5_5 re PCLK 2 +.latch N_N3016 NDN5_6 re PCLK 2 +.latch N_N3538 NDN5_7 re PCLK 2 +.latch N_N3029 NDN5_8 re PCLK 2 +.latch N_N3338 N_N4073 re PCLK 2 +.latch N_N3458 NDN5_9 re PCLK 2 +.latch N_N3618 NEN5_9 re PCLK 2 +.latch N_N3683 N_N3684 re PCLK 2 +.latch N_N4055 N_N4056 re PCLK 2 +.latch N_N3712 N_N3713 re PCLK 2 +.latch N_N3828 N_N3829 re PCLK 2 +.latch N_N47 N_N4060 re PCLK 2 +.latch N_N46 NSr3_2 re PCLK 2 +.latch N_N45 NSr5_2 re PCLK 2 +.latch N_N44 NSr5_3 re PCLK 2 +.latch N_N43 N_N3462 re PCLK 2 +.latch N_N42 N_N3460 re PCLK 2 +.latch N_N41 NSr5_4 re PCLK 2 +.latch N_N40 NSr3_9 re PCLK 2 +.latch N_N39 NSr5_5 re PCLK 2 +.latch N_N38 NSr5_7 re PCLK 2 +.latch N_N37 NSr5_8 re PCLK 2 +.latch N_N36 N_N3998 re PCLK 2 +.names PRESET n410 n3 +01 1 +.names N_N3460 n411 n412 n2 +101 1 +.names n3 n2 N_N3999 N_N4254 +11- 1 +1-1 1 +.names PRESET n458 n463 N_N4239 n4 +1-1- 1 +-11- 1 +1--0 1 +-1-0 1 +.names n4 N_N4238 +0 1 +.names n464 N_N4232 n5 +1- 1 +-0 1 +.names n5 N_N4231 +0 1 +.names n464 N_N4230 n6 +1- 1 +-0 1 +.names n6 N_N4229 +0 1 +.names n464 N_N4218 n7 +1- 1 +-0 1 +.names n7 N_N4217 +0 1 +.names PRESET n1235 n8 +01 1 +.names N_N4222 n8 N_N4174 +11 1 +.names n591 n1194 n1237 N_N4167 n9 +1-0- 1 +-00- 1 +1--0 1 +-0-0 1 +.names n9 N_N4166 +0 1 +.names PRESET n463 n594 N_N4140 n11 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names n11 N_N4139 +0 1 +.names n597 n599 n1194 N_N4114 n12 +11-- 1 +1-0- 1 +-1-0 1 +--00 1 +.names n12 N_N4113 +0 1 +.names n607 n609 n610 N_N4111 n13 +11-- 1 +1-1- 1 +-1-0 1 +--10 1 +.names n13 N_N4110 +0 1 +.names n464 N_N4106 n14 +1- 1 +-0 1 +.names n14 N_N4105 +0 1 +.names PRESET n463 n613 N_N4099 n15 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names n15 N_N4098 +0 1 +.names PRESET n463 n618 N_N4095 n16 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names n16 N_N4094 +0 1 +.names n464 N_N4090 n17 +1- 1 +-0 1 +.names n17 N_N4089 +0 1 +.names PRESET n463 n621 N_N4086 n18 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names n18 N_N4085 +0 1 +.names n624 n625 n626 N_N4075 n19 +11-- 1 +1-1- 1 +-1-0 1 +--10 1 +.names n19 N_N4074 +0 1 +.names Paport_5_5_ n464 n466 N_N4056 n22 +01-- 1 +-11- 1 +0--0 1 +--10 1 +.names n22 N_N4055 +0 1 +.names Paport_7_7_ n464 n466 N_N4054 n23 +01-- 1 +-11- 1 +0--0 1 +--10 1 +.names n23 N_N4053 +0 1 +.names n635 n636 n637 N_N4047 n24 +11-- 1 +1-1- 1 +-1-0 1 +--10 1 +.names n24 N_N4046 +0 1 +.names n626 n635 n636 N_N4045 n25 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names n25 N_N4044 +0 1 +.names n638 n639 n640 N_N4042 n26 +11-- 1 +1-1- 1 +-1-0 1 +--10 1 +.names n26 N_N4041 +0 1 +.names n638 n639 n641 N_N4039 n27 +11-- 1 +1-1- 1 +-1-0 1 +--10 1 +.names n27 N_N4038 +0 1 +.names n597 n599 n722 N_N4079 n28 +11-- 1 +1-1- 1 +-1-0 1 +--10 1 +.names n28 N_N4032 +0 1 +.names n724 n725 n726 N_N4030 n29 +11-- 1 +1-1- 1 +-1-0 1 +--10 1 +.names n29 N_N4029 +0 1 +.names n641 n727 n729 N_N4236 n30 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names n30 N_N4028 +0 1 +.names n624 n625 n730 N_N4024 n31 +11-- 1 +1-1- 1 +-1-0 1 +--10 1 +.names n31 N_N4023 +0 1 +.names n624 n625 n731 N_N4021 n32 +11-- 1 +1-1- 1 +-1-0 1 +--10 1 +.names n32 N_N4020 +0 1 +.names Pdxport_2_2_ n464 n466 N_N4057 n34 +01-- 1 +-11- 1 +0--0 1 +--10 1 +.names n34 N_N4007 +0 1 +.names n773 n775 n776 N_N3988 n35 +11-- 1 +1-1- 1 +-1-0 1 +--10 1 +.names n35 N_N3987 +0 1 +.names n607 n610 N_N3981 n778 n36 +11-- 1 +-10- 1 +1--1 1 +--01 1 +.names n36 N_N3980 +0 1 +.names n635 n636 n781 N_N4116 n38 +11-- 1 +1-1- 1 +-1-0 1 +--10 1 +.names n38 N_N3969 +0 1 +.names n638 n639 n781 N_N3968 n39 +11-- 1 +1-1- 1 +-1-0 1 +--10 1 +.names n39 N_N3967 +0 1 +.names Pdxport_5_5_ n464 n466 N_N4179 n40 +01-- 1 +-11- 1 +0--0 1 +--10 1 +.names n40 N_N3963 +0 1 +.names n624 n625 n781 N_N3959 n41 +11-- 1 +1-1- 1 +-1-0 1 +--10 1 +.names n41 N_N3958 +0 1 +.names n624 n625 n783 N_N3957 n42 +11-- 1 +1-1- 1 +-1-0 1 +--10 1 +.names n42 N_N3956 +0 1 +.names n591 n784 n1237 N_N3947 n43 +1-0- 1 +-10- 1 +1--0 1 +-1-0 1 +.names n43 N_N3946 +0 1 +.names Pdxport_3_3_ n464 n466 N_N4220 n44 +01-- 1 +-11- 1 +0--0 1 +--10 1 +.names n44 N_N3941 +0 1 +.names Paport_0_0_ n464 n466 N_N3916 n46 +01-- 1 +-11- 1 +0--0 1 +--10 1 +.names n46 N_N3915 +0 1 +.names Paport_6_6_ n464 n466 N_N4243 n47 +01-- 1 +-11- 1 +0--0 1 +--10 1 +.names n47 N_N3914 +0 1 +.names Paport_8_8_ n464 n466 N_N4015 n48 +01-- 1 +-11- 1 +0--0 1 +--10 1 +.names n48 N_N3913 +0 1 +.names n727 n729 n793 N_N3910 n49 +11-- 1 +1-1- 1 +-1-0 1 +--10 1 +.names n49 N_N3909 +0 1 +.names N_N3905 n8 N_N3904 +11 1 +.names Pdxport_1_1_ n464 n466 N_N4120 n51 +01-- 1 +-11- 1 +0--0 1 +--10 1 +.names n51 N_N3895 +0 1 +.names n885 n886 n887 N_N4197 n56 +1-1- 1 +-11- 1 +1--0 1 +-1-0 1 +.names n56 N_N3847 +0 1 +.names n591 n888 n1237 N_N3829 n57 +1-0- 1 +-10- 1 +1--0 1 +-1-0 1 +.names n57 N_N3828 +0 1 +.names n591 n889 n1237 N_N3826 n58 +1-0- 1 +-10- 1 +1--0 1 +-1-0 1 +.names n58 N_N3825 +0 1 +.names n624 n625 n640 N_N3824 n59 +11-- 1 +1-1- 1 +-1-0 1 +--10 1 +.names n59 N_N3823 +0 1 +.names Paport_9_9_ n464 n466 N_N3818 n60 +01-- 1 +-11- 1 +0--0 1 +--10 1 +.names n60 N_N3817 +0 1 +.names n591 n892 n1237 N_N3815 n61 +1-0- 1 +-10- 1 +1--0 1 +-1-0 1 +.names n61 N_N3814 +0 1 +.names n464 N_N3876 n62 +1- 1 +-0 1 +.names n62 N_N3804 +0 1 +.names PRESET n463 n895 N_N3971 n63 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names n63 N_N3801 +0 1 +.names n638 n639 n730 N_N3799 n64 +11-- 1 +1-1- 1 +-1-0 1 +--10 1 +.names n64 N_N3798 +0 1 +.names n591 n899 n1237 N_N3796 n65 +1-0- 1 +-10- 1 +1--0 1 +-1-0 1 +.names n65 N_N3795 +0 1 +.names n591 n900 n1237 N_N3788 n66 +1-0- 1 +-10- 1 +1--0 1 +-1-0 1 +.names n66 N_N3787 +0 1 +.names n464 N_N3786 n67 +1- 1 +-0 1 +.names n67 N_N3785 +0 1 +.names n635 n636 n726 N_N3870 n68 +11-- 1 +1-1- 1 +-1-0 1 +--10 1 +.names n68 N_N3772 +0 1 +.names PRESET NGFDN_3 n72 +00 1 +.names n72 NDN3_8 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n1184 n1210 n1050 +11 1 +00 1 +.names NLD3_9 n351 N_N3940 N_N4111 n1052 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names n460 n1052 N_N4218 n1051 +11- 1 +-10 1 +.names n1186 n1211 n1058 +11 1 +00 1 +.names n1188 n1212 n1059 +11 1 +00 1 +.names NSr5_7 PRESET n1061 +1- 1 +-1 1 +.names NLD3_9 n351 N_N3923 N_N3475 n1063 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names n460 n1063 N_N4230 n1062 +11- 1 +-10 1 +.names n869 n1213 n1064 +01 1 +10 1 +.names n350 N_N3800 N_N3908 n1273 n1066 +0-0- 1 +-00- 1 +0--1 1 +-0-1 1 +.names n854 n1214 n1067 +01 1 +10 1 +.names n350 N_N4136 n1273 N_N3516 n1072 +0-1- 1 +-01- 1 +0--0 1 +-0-0 1 +.names n350 N_N4183 n1273 N_N3420 n1073 +0-1- 1 +-01- 1 +0--0 1 +-0-0 1 +.names n394 n413 N_N3369 n1271 n1082 +1-0- 1 +-10- 1 +1--1 1 +-1-1 1 +.names n1082 n418 n880 n1081 +11- 1 +1-1 1 +.names n350 N_N3862 N_N3813 n1273 n1086 +00-- 1 +-00- 1 +0--1 1 +--01 1 +.names n398 n413 N_N4093 n1271 n1091 +1-0- 1 +-10- 1 +1--1 1 +-1-1 1 +.names n1091 n425 n880 n1090 +11- 1 +1-1 1 +.names n350 N_N4208 N_N4158 n1273 n1100 +0-0- 1 +-00- 1 +0--1 1 +-0-1 1 +.names n350 N_N3807 N_N3713 n1273 n1102 +0-0- 1 +-00- 1 +0--1 1 +-0-1 1 +.names n351 n460 N_N3872 N_N3248 n1105 +01-- 1 +-10- 1 +0--0 1 +--00 1 +.names NLD3_9 n1105 N_N3761 n1104 +01- 1 +-10 1 +.names N_N3965 n844 n1108 +01 1 +10 1 +.names n353 n384 n416 N_N4036 n1115 +01-- 1 +0-1- 1 +-1-0 1 +--10 1 +.names n353 n380 n416 N_N4004 n1116 +01-- 1 +0-1- 1 +-1-0 1 +--10 1 +.names n351 n460 N_N4177 N_N3011 n1118 +01-- 1 +-10- 1 +0--0 1 +--00 1 +.names NLD3_9 N_N3884 n1118 n1117 +0-1 1 +-01 1 +.names n406 n413 N_N3283 n1271 n1129 +1-0- 1 +-10- 1 +1--1 1 +-1-1 1 +.names N_N3283 n421 n1128 +01 1 +10 1 +.names n1129 n1128 n880 n1127 +11- 1 +1-1 1 +.names n350 N_N3470 N_N3821 n1273 n1138 +0-0- 1 +-00- 1 +0--1 1 +-0-1 1 +.names n860 n1216 n1141 +01 1 +10 1 +.names n840 n1275 n1162 +01 1 +10 1 +.names n353 n376 n416 N_N3961 n1172 +01-- 1 +0-1- 1 +-1-0 1 +--10 1 +.names n863 n1217 n1173 +01 1 +10 1 +.names n350 N_N3868 N_N3832 n1273 n1178 +0-0- 1 +-00- 1 +0--1 1 +-0-1 1 +.names n350 N_N3794 N_N3919 n1273 n1179 +00-- 1 +-00- 1 +0--1 1 +--01 1 +.names n350 N_N3871 N_N3214 n1273 n1180 +0-0- 1 +-00- 1 +0--1 1 +-0-1 1 +.names n72 NSr3_9 N_N3542 +10 1 +.names PRESET Pover_0_0_ NGFDN_3 NDN3_11 n1181 +010- 1 +01-1 1 +.names N_N3542 n1181 N_N3061 +1- 1 +-1 1 +.names PRESET Pnext_0_0_ NLD3_9 NDN5_16 n1182 +010- 1 +01-1 1 +.names PRESET n1227 N_N3042 +01 1 +.names n1182 N_N3042 N_N3005 +1- 1 +-1 1 +.names N_N3283 n421 n1183 +1- 1 +-1 1 +.names n536 n493 n1184 +01 1 +10 1 +.names n550 n499 n1185 +01 1 +10 1 +.names n549 n487 n1186 +01 1 +10 1 +.names n564 n502 n1187 +01 1 +10 1 +.names n563 n484 n1188 +01 1 +10 1 +.names n518 n505 n1189 +01 1 +10 1 +.names n505 n481 n518 n1192 +111 1 +.names n1192 n508 n1191 +01 1 +10 1 +.names n584 n586 n1195 +01 1 +10 1 +.names n473 n1284 n1196 +01 1 +10 1 +.names n1195 n1196 n1194 +01 1 +10 1 +.names n573 n514 n1197 +01 1 +10 1 +.names n804 N_N4197 n1198 +11 1 +00 1 +.names n542 n519 n1199 +01 1 +10 1 +.names n553 n554 n1200 +01 1 +10 1 +.names n567 n568 n1201 +01 1 +10 1 +.names n576 n577 n1202 +01 1 +10 1 +.names n836 N_N3992 n1203 +11 1 +00 1 +.names n828 N_N4018 n1204 +11 1 +00 1 +.names n816 N_N3949 n1205 +11 1 +00 1 +.names n665 n668 n1206 +01 1 +10 1 +.names n604 n600 n1207 +1- 1 +-1 1 +.names n808 N_N3912 n1208 +11 1 +00 1 +.names n581 n511 n1209 +01 1 +10 1 +.names n533 n537 n1210 +01 1 +10 1 +.names n544 n546 n1211 +01 1 +10 1 +.names n559 n560 n1212 +01 1 +10 1 +.names n812 N_N4145 n1213 +11 1 +00 1 +.names n832 N_N3996 n1214 +11 1 +00 1 +.names n824 N_N3974 n1216 +11 1 +00 1 +.names n820 N_N4083 n1217 +11 1 +00 1 +.names n2 N_N4214 n1221 +10 1 +.names n425 n422 n418 n437 n433 n429 n1226 +111111 1 +.names NLD3_9 NDN5_9 n1227 +01 1 +.names PDN NDN1_4 n1228 +0- 1 +-1 1 +.names Preset_0_0_ NLC1_2 N_N3998 n1230 +00- 1 +0-1 1 +-11 1 +.names NDN3_3 NSr3_2 n1233 +00 1 +.names NDN2_2 n149 n1235 +1- 1 +-1 1 +.names PRESET n476 n1237 +01 1 +.names n508 n1192 n1238 +11 1 +.names NSr5_8 NDN5_8 n1242 +1- 1 +-1 1 +.names NSr5_4 NDN5_4 n1245 +1- 1 +-1 1 +.names NSr5_7 NDN5_7 n1247 +1- 1 +-1 1 +.names NSr5_3 NDN5_3 n1250 +1- 1 +-1 1 +.names NSr5_5 NDN5_5 n1252 +1- 1 +-1 1 +.names NSr5_2 NDN5_2 n1254 +1- 1 +-1 1 +.names n412 n414 n1271 +0- 1 +-1 1 +.names PRESET NLD3_9 n1273 +1- 1 +-0 1 +.names n849 N_N4027 n1275 +11 1 +00 1 +.names PRESET n879 N_N4227 n1283 n1276 +1--1 1 +-1-1 1 +--01 1 +.names n1276 N_N3859 +0 1 +.names n371 n367 n363 n384 n380 n376 n1277 +111111 1 +.names n881 n886 N_N4227 n1283 +0-- 1 +-1- 1 +--1 1 +.names n1061 N_N3538 +0 1 +.names n946 N_N3029 +0 1 +.names n1238 n478 n1284 +11 1 +.names n490 n522 n1285 +1- 1 +-1 1 +.names n642 n645 n1286 +01 1 +10 1 +.names n653 n656 n1287 +01 1 +10 1 +.names n712 n713 n1288 +01 1 +10 1 +.names n525 n1285 n1289 +01 1 +10 1 +.names n681 n682 n1290 +01 1 +10 1 +.names n695 n696 n1291 +01 1 +10 1 +.names n648 n650 n1292 +01 1 +10 1 +.names n688 n689 n1293 +01 1 +10 1 +.names n659 n662 n1294 +01 1 +10 1 +.names n702 n703 n1295 +01 1 +10 1 +.names n1001 n1003 n1296 +01 1 +10 1 +.names N_N3999 n358 n389 n394 n398 n402 n406 n1277 n1297 +01111111 1 +.names Preset_0_0_ n951 n1299 +01 1 +.end diff --git a/fpga_flow/benchmarks/MCNC_big20/dsip.blif b/fpga_flow/benchmarks/MCNC_big20/dsip.blif new file mode 100644 index 000000000..049fb4cbe --- /dev/null +++ b/fpga_flow/benchmarks/MCNC_big20/dsip.blif @@ -0,0 +1,8753 @@ +## inputs 228 +## outputs 197 +## latches 224 +## initial 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +.model dsip.sim +.inputs key<254> key<253> key<252> key<251> key<250> key<249> key<248> key<246> key<245> key<244> +.inputs key<243> key<242> key<241> key<240> key<238> key<237> key<235> key<234> key<233> key<232> +.inputs key<230> key<229> key<228> key<227> key<226> key<225> key<224> key<222> key<221> key<220> +.inputs key<219> key<218> key<217> key<216> key<214> key<213> key<212> key<211> key<210> key<209> +.inputs key<208> key<206> key<205> key<204> key<203> key<202> key<201> key<200> key<198> key<197> +.inputs key<196> key<195> key<194> key<193> key<192> key<190> key<189> key<188> key<187> key<186> +.inputs key<185> key<184> key<182> key<181> key<180> key<179> key<178> key<177> key<176> key<174> +.inputs key<173> key<172> key<171> key<170> key<169> key<168> key<166> key<165> key<164> key<163> +.inputs key<162> key<161> key<160> key<158> key<157> key<156> key<155> key<154> key<153> key<152> +.inputs key<150> key<149> key<148> key<147> key<146> key<145> key<144> key<142> key<141> key<140> +.inputs key<139> key<138> key<137> key<136> key<134> key<133> key<132> key<131> key<130> key<129> +.inputs key<128> key<126> key<125> key<124> key<123> key<122> key<121> key<120> key<118> key<117> +.inputs key<116> key<115> key<114> key<113> key<112> key<110> key<109> key<107> key<106> key<105> +.inputs key<104> key<102> key<101> key<100> key<99> key<98> key<97> key<96> key<94> key<93> +.inputs key<92> key<91> key<90> key<89> key<88> key<86> key<85> key<84> key<83> key<82> +.inputs key<81> key<80> key<78> key<77> key<76> key<75> key<74> key<73> key<72> key<70> +.inputs key<69> key<68> key<67> key<66> key<65> key<64> key<62> key<61> key<60> key<59> +.inputs key<58> key<57> key<56> key<54> key<53> key<52> key<51> key<50> key<49> key<48> +.inputs key<46> key<45> key<44> key<43> key<42> key<41> key<40> key<38> key<37> key<36> +.inputs key<35> key<34> key<33> key<32> key<30> key<29> key<28> key<27> key<26> key<25> +.inputs key<24> key<22> key<21> key<20> key<19> key<18> key<17> key<16> key<14> key<13> +.inputs key<12> key<11> key<10> key<9> key<8> key<6> key<5> key<4> key<3> key<2> +.inputs key<1> key<0> count<3> count<2> count<1> count<0> encrypt<0> start<0> +.outputs KSi<191> KSi<190> KSi<189> KSi<188> KSi<187> KSi<186> KSi<185> KSi<184> KSi<183> KSi<182> +.outputs KSi<181> KSi<180> KSi<179> KSi<178> KSi<177> KSi<176> KSi<175> KSi<174> KSi<173> KSi<172> +.outputs KSi<171> KSi<170> KSi<169> KSi<168> KSi<167> KSi<166> KSi<165> KSi<164> KSi<163> KSi<162> +.outputs KSi<161> KSi<160> KSi<159> KSi<158> KSi<157> KSi<156> KSi<155> KSi<154> KSi<153> KSi<152> +.outputs KSi<151> KSi<150> KSi<149> KSi<148> KSi<147> KSi<146> KSi<145> KSi<144> KSi<143> KSi<142> +.outputs KSi<141> KSi<140> KSi<139> KSi<138> KSi<137> KSi<136> KSi<135> KSi<134> KSi<133> KSi<132> +.outputs KSi<131> KSi<130> KSi<129> KSi<128> KSi<127> KSi<126> KSi<125> KSi<124> KSi<123> KSi<122> +.outputs KSi<121> KSi<120> KSi<119> KSi<118> KSi<117> KSi<116> KSi<115> KSi<114> KSi<113> KSi<112> +.outputs KSi<111> KSi<110> KSi<109> KSi<108> KSi<107> KSi<106> KSi<105> KSi<104> KSi<103> KSi<102> +.outputs KSi<101> KSi<100> KSi<99> KSi<98> KSi<97> KSi<96> KSi<95> KSi<94> KSi<93> KSi<92> +.outputs KSi<91> KSi<90> KSi<89> KSi<88> KSi<87> KSi<86> KSi<85> KSi<84> KSi<83> KSi<82> +.outputs KSi<81> KSi<80> KSi<79> KSi<78> KSi<77> KSi<76> KSi<75> KSi<74> KSi<73> KSi<72> +.outputs KSi<71> KSi<70> KSi<69> KSi<68> KSi<67> KSi<66> KSi<65> KSi<64> KSi<63> KSi<62> +.outputs KSi<61> KSi<60> KSi<59> KSi<58> KSi<57> KSi<56> KSi<55> KSi<54> KSi<53> KSi<52> +.outputs KSi<51> KSi<50> KSi<49> KSi<48> KSi<47> KSi<46> KSi<45> KSi<44> KSi<43> KSi<42> +.outputs KSi<41> KSi<40> KSi<39> KSi<38> KSi<37> KSi<36> KSi<35> KSi<34> KSi<33> KSi<32> +.outputs KSi<31> KSi<30> KSi<29> KSi<28> KSi<27> KSi<26> KSi<25> KSi<24> KSi<23> KSi<22> +.outputs KSi<21> KSi<20> KSi<19> KSi<18> KSi<17> KSi<16> KSi<15> KSi<14> KSi<13> KSi<12> +.outputs KSi<11> KSi<10> KSi<9> KSi<8> KSi<7> KSi<6> KSi<5> KSi<4> KSi<3> KSi<2> +.outputs KSi<1> KSi<0> new_count<3> new_count<2> new_count<1> new_count<0> data_ready<0> +.latch new_C<111> C<111> 0 +.latch new_C<110> C<110> 0 +.latch new_C<109> C<109> 0 +.latch new_C<108> C<108> 0 +.latch new_C<107> C<107> 0 +.latch new_C<106> C<106> 0 +.latch new_C<105> C<105> 0 +.latch new_C<104> C<104> 0 +.latch new_C<103> C<103> 0 +.latch new_C<102> C<102> 0 +.latch new_C<101> C<101> 0 +.latch new_C<100> C<100> 0 +.latch new_C<99> C<99> 0 +.latch new_C<98> C<98> 0 +.latch new_C<97> C<97> 0 +.latch new_C<96> C<96> 0 +.latch new_C<95> C<95> 0 +.latch new_C<94> C<94> 0 +.latch new_C<93> C<93> 0 +.latch new_C<92> C<92> 0 +.latch new_C<91> C<91> 0 +.latch new_C<90> C<90> 0 +.latch new_C<89> C<89> 0 +.latch new_C<88> C<88> 0 +.latch new_C<87> C<87> 0 +.latch new_C<86> C<86> 0 +.latch new_C<85> C<85> 0 +.latch new_C<84> C<84> 0 +.latch new_C<83> C<83> 0 +.latch new_C<82> C<82> 0 +.latch new_C<81> C<81> 0 +.latch new_C<80> C<80> 0 +.latch new_C<79> C<79> 0 +.latch new_C<78> C<78> 0 +.latch new_C<77> C<77> 0 +.latch new_C<76> C<76> 0 +.latch new_C<75> C<75> 0 +.latch new_C<74> C<74> 0 +.latch new_C<73> C<73> 0 +.latch new_C<72> C<72> 0 +.latch new_C<71> C<71> 0 +.latch new_C<70> C<70> 0 +.latch new_C<69> C<69> 0 +.latch new_C<68> C<68> 0 +.latch new_C<67> C<67> 0 +.latch new_C<66> C<66> 0 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+.names [8326] [8326]* +0 1 +.names key<131> key<131>* +0 1 +.names [8330] [8330]* +0 1 +.names D<80> D<80>* +0 1 +.names [7405] [7405]* +0 1 +.names key<139> key<139>* +0 1 +.names [8335] [8335]* +0 1 +.names D<79> D<79>* +0 1 +.names [7421] [7421]* +0 1 +.names key<147> key<147>* +0 1 +.names [8340] [8340]* +0 1 +.names D<78> D<78>* +0 1 +.names [7414] [7414]* +0 1 +.names key<155> key<155>* +0 1 +.names [8345] [8345]* +0 1 +.names D<77> D<77>* +0 1 +.names [7402] [7402]* +0 1 +.names key<132> key<132>* +0 1 +.names [8350] [8350]* +0 1 +.names D<76> D<76>* +0 1 +.names [7409] [7409]* +0 1 +.names key<140> key<140>* +0 1 +.names [8355] [8355]* +0 1 +.names D<75> D<75>* +0 1 +.names [7411] [7411]* +0 1 +.names key<148> key<148>* +0 1 +.names [8360] [8360]* +0 1 +.names D<74> D<74>* +0 1 +.names [7418] [7418]* +0 1 +.names key<156> key<156>* +0 1 +.names [8365] [8365]* +0 1 +.names D<73> D<73>* +0 1 +.names [7404] [7404]* +0 1 +.names key<164> key<164>* +0 1 +.names [8370] [8370]* +0 1 +.names D<72> D<72>* +0 1 +.names [8372] [8372]* +0 1 +.names D<71> D<71>* +0 1 +.names [7410] [7410]* +0 1 +.names key<180> key<180>* +0 1 +.names [8380] [8380]* +0 1 +.names D<70> D<70>* +0 1 +.names [7413] [7413]* +0 1 +.names key<188> key<188>* +0 1 +.names [8385] [8385]* +0 1 +.names D<69> D<69>* +0 1 +.names [7403] [7403]* +0 1 +.names key<133> key<133>* +0 1 +.names [8390] [8390]* +0 1 +.names D<68> D<68>* +0 1 +.names [7422] [7422]* +0 1 +.names key<141> key<141>* +0 1 +.names [8395] [8395]* +0 1 +.names D<67> D<67>* +0 1 +.names [7415] [7415]* +0 1 +.names key<149> key<149>* +0 1 +.names [8400] [8400]* +0 1 +.names D<66> D<66>* +0 1 +.names [7408] [7408]* +0 1 +.names key<157> key<157>* +0 1 +.names [8405] [8405]* +0 1 +.names D<65> D<65>* +0 1 +.names [8407] [8407]* +0 1 +.names key<165> key<165>* +0 1 +.names [8411] [8411]* +0 1 +.names D<64> D<64>* +0 1 +.names [7419] [7419]* +0 1 +.names key<173> key<173>* +0 1 +.names [8416] [8416]* +0 1 +.names D<63> D<63>* +0 1 +.names [7401] [7401]* +0 1 +.names key<181> key<181>* +0 1 +.names [8421] [8421]* +0 1 +.names D<62> D<62>* +0 1 +.names [8423] [8423]* +0 1 +.names key<189> key<189>* +0 1 +.names [8427] [8427]* +0 1 +.names D<61> D<61>* +0 1 +.names [7406] [7406]* +0 1 +.names key<134> key<134>* +0 1 +.names [8432] [8432]* +0 1 +.names D<60> D<60>* +0 1 +.names [7412] [7412]* +0 1 +.names key<142> key<142>* +0 1 +.names [8437] [8437]* +0 1 +.names D<59> D<59>* +0 1 +.names [7399] [7399]* +0 1 +.names key<150> key<150>* +0 1 +.names [8442] [8442]* +0 1 +.names D<58> D<58>* +0 1 +.names [7420] [7420]* +0 1 +.names key<158> key<158>* +0 1 +.names [8447] [8447]* +0 1 +.names D<57> D<57>* +0 1 +.names [7416] [7416]* +0 1 +.names key<166> key<166>* +0 1 +.names [8452] [8452]* +0 1 +.names D<56> D<56>* +0 1 +.names [7400] [7400]* +0 1 +.names key<174> key<174>* +0 1 +.names [8457] [8457]* +0 1 +.names D<55> D<55>* +0 1 +.names [7430] [7430]* +0 1 +.names key<182> key<182>* +0 1 +.names [8462] [8462]* +0 1 +.names D<54> D<54>* +0 1 +.names [7440] [7440]* +0 1 +.names key<190> key<190>* +0 1 +.names [8467] [8467]* +0 1 +.names D<53> D<53>* +0 1 +.names [8469] [8469]* +0 1 +.names key<67> key<67>* +0 1 +.names [8473] [8473]* +0 1 +.names D<52> D<52>* +0 1 +.names [7428] [7428]* +0 1 +.names key<75> key<75>* +0 1 +.names [8478] [8478]* +0 1 +.names D<51> D<51>* +0 1 +.names [7444] [7444]* +0 1 +.names key<83> key<83>* +0 1 +.names [8483] [8483]* +0 1 +.names D<50> D<50>* +0 1 +.names [7437] [7437]* +0 1 +.names key<91> key<91>* +0 1 +.names [8488] [8488]* +0 1 +.names D<49> D<49>* +0 1 +.names [7426] [7426]* +0 1 +.names key<68> key<68>* +0 1 +.names [8493] [8493]* +0 1 +.names D<48> D<48>* +0 1 +.names [7432] [7432]* +0 1 +.names key<76> key<76>* +0 1 +.names [8498] [8498]* +0 1 +.names D<47> D<47>* +0 1 +.names [7434] [7434]* +0 1 +.names key<84> key<84>* +0 1 +.names [8503] [8503]* +0 1 +.names D<46> D<46>* +0 1 +.names [7441] [7441]* +0 1 +.names key<92> key<92>* +0 1 +.names [8508] [8508]* +0 1 +.names D<45> D<45>* +0 1 +.names [7427] [7427]* +0 1 +.names key<100> key<100>* +0 1 +.names [8513] [8513]* +0 1 +.names D<44> D<44>* +0 1 +.names [7436] [7436]* +0 1 +.names key<44> key<44>* +0 1 +.names [8518] [8518]* +0 1 +.names D<43> D<43>* +0 1 +.names [7433] [7433]* +0 1 +.names key<116> key<116>* +0 1 +.names [8523] [8523]* +0 1 +.names D<42> D<42>* +0 1 +.names [8525] [8525]* +0 1 +.names key<124> key<124>* +0 1 +.names [8529] [8529]* +0 1 +.names D<41> D<41>* +0 1 +.names [8531] [8531]* +0 1 +.names key<69> key<69>* +0 1 +.names [8535] [8535]* +0 1 +.names D<40> D<40>* +0 1 +.names [7445] [7445]* +0 1 +.names key<77> key<77>* +0 1 +.names [8540] [8540]* +0 1 +.names D<39> D<39>* +0 1 +.names [7438] [7438]* +0 1 +.names key<85> key<85>* +0 1 +.names [8545] [8545]* +0 1 +.names D<38> D<38>* +0 1 +.names [7431] [7431]* +0 1 +.names key<93> key<93>* +0 1 +.names [8550] [8550]* +0 1 +.names D<37> D<37>* +0 1 +.names [8552] [8552]* +0 1 +.names key<101> key<101>* +0 1 +.names [8556] [8556]* +0 1 +.names D<36> D<36>* +0 1 +.names [7442] [7442]* +0 1 +.names key<109> key<109>* +0 1 +.names [8561] [8561]* +0 1 +.names D<35> D<35>* +0 1 +.names [7425] [7425]* +0 1 +.names key<117> key<117>* +0 1 +.names [8566] [8566]* +0 1 +.names D<34> D<34>* +0 1 +.names [8568] [8568]* +0 1 +.names key<125> key<125>* +0 1 +.names [8572] [8572]* +0 1 +.names D<33> D<33>* +0 1 +.names [7429] [7429]* +0 1 +.names key<70> key<70>* +0 1 +.names [8577] [8577]* +0 1 +.names D<32> D<32>* +0 1 +.names [7435] [7435]* +0 1 +.names key<78> key<78>* +0 1 +.names [8582] [8582]* +0 1 +.names D<31> D<31>* +0 1 +.names [7423] [7423]* +0 1 +.names key<86> key<86>* +0 1 +.names [8587] [8587]* +0 1 +.names D<30> D<30>* +0 1 +.names [7443] [7443]* +0 1 +.names key<94> key<94>* +0 1 +.names [8592] [8592]* +0 1 +.names D<29> D<29>* +0 1 +.names [7439] [7439]* +0 1 +.names key<102> key<102>* +0 1 +.names [8597] [8597]* +0 1 +.names D<28> D<28>* +0 1 +.names [7424] [7424]* +0 1 +.names key<110> key<110>* +0 1 +.names [8602] [8602]* +0 1 +.names D<27> D<27>* +0 1 +.names [7454] [7454]* +0 1 +.names key<118> key<118>* +0 1 +.names [8607] [8607]* +0 1 +.names D<26> D<26>* +0 1 +.names [7464] [7464]* +0 1 +.names key<126> key<126>* +0 1 +.names [8612] [8612]* +0 1 +.names D<25> D<25>* +0 1 +.names [8614] [8614]* +0 1 +.names key<3> key<3>* +0 1 +.names [8618] [8618]* +0 1 +.names D<24> D<24>* +0 1 +.names [7452] [7452]* +0 1 +.names key<11> key<11>* +0 1 +.names [8623] [8623]* +0 1 +.names D<23> D<23>* +0 1 +.names [7468] [7468]* +0 1 +.names key<19> key<19>* +0 1 +.names [8628] [8628]* +0 1 +.names D<22> D<22>* +0 1 +.names [7461] [7461]* +0 1 +.names key<27> key<27>* +0 1 +.names [8633] [8633]* +0 1 +.names D<21> D<21>* +0 1 +.names [7449] [7449]* +0 1 +.names key<4> key<4>* +0 1 +.names [8638] [8638]* +0 1 +.names D<20> D<20>* +0 1 +.names [7456] [7456]* +0 1 +.names key<12> key<12>* +0 1 +.names [8643] [8643]* +0 1 +.names D<19> D<19>* +0 1 +.names [7458] [7458]* +0 1 +.names key<20> key<20>* +0 1 +.names [8648] [8648]* +0 1 +.names D<18> D<18>* +0 1 +.names [7465] [7465]* +0 1 +.names key<28> key<28>* +0 1 +.names [8653] [8653]* +0 1 +.names D<17> D<17>* +0 1 +.names [7451] [7451]* +0 1 +.names key<36> key<36>* +0 1 +.names [8658] [8658]* +0 1 +.names D<16> D<16>* +0 1 +.names [7460] [7460]* +0 1 +.names D<15> D<15>* +0 1 +.names [7457] [7457]* +0 1 +.names key<52> key<52>* +0 1 +.names [8667] [8667]* +0 1 +.names D<14> D<14>* +0 1 +.names [8669] [8669]* +0 1 +.names key<60> key<60>* +0 1 +.names [8673] [8673]* +0 1 +.names D<13> D<13>* +0 1 +.names [7450] [7450]* +0 1 +.names key<5> key<5>* +0 1 +.names [8678] [8678]* +0 1 +.names D<12> D<12>* +0 1 +.names [7469] [7469]* +0 1 +.names key<13> key<13>* +0 1 +.names [8683] [8683]* +0 1 +.names D<11> D<11>* +0 1 +.names [7462] [7462]* +0 1 +.names key<21> key<21>* +0 1 +.names [8688] [8688]* +0 1 +.names D<10> D<10>* +0 1 +.names [7455] [7455]* +0 1 +.names key<29> key<29>* +0 1 +.names [8693] [8693]* +0 1 +.names D<9> D<9>* +0 1 +.names [8695] [8695]* +0 1 +.names key<37> key<37>* +0 1 +.names [8699] [8699]* +0 1 +.names D<8> D<8>* +0 1 +.names [7466] [7466]* +0 1 +.names key<45> key<45>* +0 1 +.names [8704] [8704]* +0 1 +.names D<7> D<7>* +0 1 +.names [7448] [7448]* +0 1 +.names key<53> key<53>* +0 1 +.names [8709] [8709]* +0 1 +.names D<6> D<6>* +0 1 +.names [8711] [8711]* +0 1 +.names key<61> key<61>* +0 1 +.names [8715] [8715]* +0 1 +.names D<5> D<5>* +0 1 +.names [7453] [7453]* +0 1 +.names key<6> key<6>* +0 1 +.names [8720] [8720]* +0 1 +.names D<4> D<4>* +0 1 +.names [7459] [7459]* +0 1 +.names key<14> key<14>* +0 1 +.names [8725] [8725]* +0 1 +.names D<3> D<3>* +0 1 +.names [7446] [7446]* +0 1 +.names key<22> key<22>* +0 1 +.names [8730] [8730]* +0 1 +.names D<2> D<2>* +0 1 +.names [7467] [7467]* +0 1 +.names key<30> key<30>* +0 1 +.names [8735] [8735]* +0 1 +.names key<38> key<38>* +0 1 +.names [8740] [8740]* +0 1 +.names key<46> key<46>* +0 1 +.names [8745] [8745]* +0 1 +.names key<54> key<54>* +0 1 +.names [8750] [8750]* +0 1 +.names [7570] [7570]* +0 1 +.names [7596] [7596]* +0 1 +.names [8756] [8756]* +0 1 +.names [8757] [8757]* +0 1 +.end diff --git a/fpga_flow/benchmarks/MCNC_big20/elliptic.blif b/fpga_flow/benchmarks/MCNC_big20/elliptic.blif new file mode 100644 index 000000000..d395d2dc4 --- /dev/null +++ b/fpga_flow/benchmarks/MCNC_big20/elliptic.blif @@ -0,0 +1,1479 @@ +.model TOP +.inputs PCLK PRESET Preset_0_0_ Pinp_0_0_ Pinp_1_1_ Pinp_2_2_ Pinp_3_3_ \ +Pinp_4_4_ Pinp_5_5_ Pinp_6_6_ Pinp_7_7_ Pinp_8_8_ Pinp_9_9_ Pinp_10_10_ \ +Pinp_11_11_ Pinp_12_12_ Pinp_13_13_ Pinp_14_14_ Pinp_15_15_ +.outputs PDN Pover_0_0_ +.latch N_N8025 N_N8199 re PCLK 2 +.latch N_N9279 N_N9280 re PCLK 2 +.latch N_N8802 N_N8803 re PCLK 2 +.latch N_N7548 N_N8240 re PCLK 2 +.latch N_N6924 N_N8274 re PCLK 2 +.latch N_N7048 N_N8198 re PCLK 2 +.latch N_N7371 N_N8239 re PCLK 2 +.latch N_N8614 N_N8615 re PCLK 2 +.latch N_N7294 N_N7703 re PCLK 2 +.latch N_N7007 N_N8273 re PCLK 2 +.latch N_N8365 N_N8366 re PCLK 2 +.latch N_N7894 N_N8272 re PCLK 2 +.latch N_N6941 N_N8238 re PCLK 2 +.latch N_N7547 N_N8531 re PCLK 2 +.latch N_N7982 N_N7983 re PCLK 2 +.latch N_N7131 N_N8575 re PCLK 2 +.latch N_N7000 N_N7854 re PCLK 2 +.latch N_N7633 N_N8237 re PCLK 2 +.latch N_N7447 N_N8197 re PCLK 2 +.latch N_N7047 N_N8271 re PCLK 2 +.latch N_N6982 N_N8530 re PCLK 2 +.latch N_N7785 N_N8650 re PCLK 2 +.latch N_N7984 N_N7985 re PCLK 2 +.latch N_N8709 N_N8710 re PCLK 2 +.latch N_N7006 N_N8574 re PCLK 2 +.latch N_N8311 N_N8312 re PCLK 2 +.latch N_N8190 N_N8270 re PCLK 2 +.latch N_N7063 N_N8573 re PCLK 2 +.latch N_N8934 N_N8935 re PCLK 2 +.latch N_N7280 N_N8649 re PCLK 2 +.latch N_N7893 N_N8196 re PCLK 2 +.latch N_N8137 N_N8236 re PCLK 2 +.latch N_N9243 N_N9244 re PCLK 2 +.latch N_N8347 N_N8348 re PCLK 2 +.latch N_N9149 N_N9150 re PCLK 2 +.latch N_N7194 N_N8648 re PCLK 2 +.latch N_N7313 N_N8269 re PCLK 2 +.latch N_N7465 N_N8235 re PCLK 2 +.latch N_N9274 N_N9275 re PCLK 2 +.latch N_N8969 N_N8970 re PCLK 2 +.latch N_N7266 N_N9554 re PCLK 2 +.latch N_N9012 N_N9013 re PCLK 2 +.latch N_N8507 N_N8508 re PCLK 2 +.latch N_N8136 N_N8529 re PCLK 2 +.latch N_N9241 N_N9242 re PCLK 2 +.latch N_N8169 N_N8572 re PCLK 2 +.latch N_N7312 N_N8571 re PCLK 2 +.latch N_N8363 N_N9436 re PCLK 2 +.latch N_N7377 N_N8528 re PCLK 2 +.latch N_N8795 N_N8796 re PCLK 2 +.latch N_N7001 N_N7770 re PCLK 2 +.latch N_N8364 N_N9357 re PCLK 2 +.latch N_N8684 N_N8685 re PCLK 2 +.latch N_N9295 N_N9296 re PCLK 2 +.latch N_N6995 N_N9555 re PCLK 2 +.latch N_N6971 N_N7628 re PCLK 2 +.latch N_N9509 N_N9510 re PCLK 2 +.latch N_N9577 N_N9578 re PCLK 2 +.latch N_N8446 N_N8447 re PCLK 2 +.latch N_N7137 N_N9437 re PCLK 2 +.latch N_N7042 N_N7771 re PCLK 2 +.latch N_N7305 N_N8570 re PCLK 2 +.latch N_N8527 N_N8647 re PCLK 2 +.latch N_N6957 N_N7704 re PCLK 2 +.latch N_N6926 N_N8646 re PCLK 2 +.latch N_N6958 N_N7629 re PCLK 2 +.latch N_N7096 NDN3_11 re PCLK 2 +.latch N_N7460 NDN3_12 re PCLK 2 +.latch N_N8036 N_N8037 re PCLK 2 +.latch N_N8540 NDN3_16 re PCLK 2 +.latch N_N7087 NDN3_17 re PCLK 2 +.latch N_N9543 NDN3_19 re PCLK 2 +.latch N_N7883 NDN3_22 re PCLK 2 +.latch N_N8293 NDN3_25 re PCLK 2 +.latch N_N9328 NDN3_26 re PCLK 2 +.latch N_N7301 N_N7584 re PCLK 2 +.latch N_N9620 NDN3_28 re PCLK 2 +.latch N_N8217 NDN3_29 re PCLK 2 +.latch N_N7158 NDN3_40 re PCLK 2 +.latch N_N9425 NDN3_39 re PCLK 2 +.latch N_N7690 NDN3_42 re PCLK 2 +.latch N_N7232 NDN3_44 re PCLK 2 +.latch N_N7574 NDN3_46 re PCLK 2 +.latch N_N7608 N_N9358 re PCLK 2 +.latch N_N9538 N_N9539 re PCLK 2 +.latch N_N7795 N_N9556 re PCLK 2 +.latch N_N8147 N_N7306 re PCLK 2 +.latch N_N7038 NEN3_16 re PCLK 2 +.latch N_N9111 N_N9160 re PCLK 2 +.latch N_N7477 NEN3_19 re PCLK 2 +.latch N_N8299 NEN3_22 re PCLK 2 +.latch N_N7077 N_N8930 re PCLK 2 +.latch N_N7529 NEN3_28 re PCLK 2 +.latch N_N7796 N_N9438 re PCLK 2 +.latch N_N8825 NEN3_34 re PCLK 2 +.latch N_N7891 NEN3_36 re PCLK 2 +.latch N_N8317 NEN3_39 re PCLK 2 +.latch N_N7960 N_N7961 re PCLK 2 +.latch N_N8814 NLC1_2 re PCLK 2 +.latch N_N7126 N_N9359 re PCLK 2 +.latch N_N7475 N_N7476 re PCLK 2 +.latch N_N8576 N_N8577 re PCLK 2 +.latch N_N8178 N_N9289 re PCLK 2 +.latch N_N7397 N_N9557 re PCLK 2 +.latch N_N7238 N_N7630 re PCLK 2 +.latch N_N8829 N_N9161 re PCLK 2 +.latch N_N8690 N_N8691 re PCLK 2 +.latch N_N7449 N_N9439 re PCLK 2 +.latch N_N7747 N_N8798 re PCLK 2 +.latch N_N7750 N_N8869 re PCLK 2 +.latch N_N7450 N_N9360 re PCLK 2 +.latch N_N7535 N_N8911 re PCLK 2 +.latch N_N7451 N_N9290 re PCLK 2 +.latch N_N6942 N_N9558 re PCLK 2 +.latch N_N8181 N_N8993 re PCLK 2 +.latch N_N9039 N_N9162 re PCLK 2 +.latch N_N7538 N_N9034 re PCLK 2 +.latch N_N7998 N_N9440 re PCLK 2 +.latch N_N7799 N_N9361 re PCLK 2 +.latch N_N9297 N_N9298 re PCLK 2 +.latch N_N8737 N_N9559 re PCLK 2 +.latch N_N7193 N_N9163 re PCLK 2 +.latch N_N9549 N_N9550 re PCLK 2 +.latch N_N7729 PDN re PCLK 2 +.latch N_N8170 N_N8171 re PCLK 2 +.latch N_N8172 N_N8173 re PCLK 2 +.latch N_N8385 N_N9011 re PCLK 2 +.latch N_N9551 N_N9552 re PCLK 2 +.latch N_N7515 N_N7701 re PCLK 2 +.latch N_N8286 N_N8964 re PCLK 2 +.latch N_N7957 N_N9291 re PCLK 2 +.latch N_N8345 N_N9560 re PCLK 2 +.latch N_N6917 N_N7627 re PCLK 2 +.latch N_N7095 N_N8913 re PCLK 2 +.latch N_N8755 N_N8756 re PCLK 2 +.latch N_N7059 N_N9164 re PCLK 2 +.latch N_N8015 N_N8016 re PCLK 2 +.latch N_N8952 N_N9441 re PCLK 2 +.latch N_N8283 N_N8847 re PCLK 2 +.latch N_N7094 N_N8631 re PCLK 2 +.latch N_N7870 N_N9362 re PCLK 2 +.latch N_N7199 Pover_0_0_ re PCLK 2 +.latch N_N7015 NDN1_4 re PCLK 2 +.latch N_N7439 N_N8561 re PCLK 2 +.latch N_N6927 N_N9292 re PCLK 2 +.latch N_N7470 N_N9561 re PCLK 2 +.latch N_N7098 NGFDN_3 re PCLK 2 +.latch N_N6928 N_N9165 re PCLK 2 +.latch N_N7382 N_N9442 re PCLK 2 +.latch N_N7528 N_N7768 re PCLK 2 +.latch N_N8117 N_N8118 re PCLK 2 +.latch N_N8122 NDN2_2 re PCLK 2 +.latch N_N8874 N_N8875 re PCLK 2 +.latch N_N7448 N_N7852 re PCLK 2 +.latch N_N7318 N_N7582 re PCLK 2 +.latch N_N9330 N_N9331 re PCLK 2 +.latch N_N7981 N_N9363 re PCLK 2 +.latch N_N9293 N_N9294 re PCLK 2 +.latch N_N9443 NDN3_2 re PCLK 2 +.latch N_N8565 NDN3_4 re PCLK 2 +.latch N_N8399 NDN3_7 re PCLK 2 +.latch N_N7188 NDN3_9 re PCLK 2 +.latch N_N9409 N_N9410 re PCLK 2 +.latch N_N8612 N_N8613 re PCLK 2 +.latch N_N8971 N_N8972 re PCLK 2 +.latch N_N9461 N_N9247 re PCLK 2 +.latch N_N7030 N_N9166 re PCLK 2 +.latch N_N8967 N_N8968 re PCLK 2 +.latch N_N8478 NAK3_13 re PCLK 2 +.latch N_N8451 N_N8668 re PCLK 2 +.latch N_N8922 N_N8923 re PCLK 2 +.latch N_N7162 N_N7769 re PCLK 2 +.latch N_N8926 N_N8933 re PCLK 2 +.latch N_N7163 N_N7702 re PCLK 2 +.latch N_N7828 N_N8978 re PCLK 2 +.latch N_N8140 N_N8141 re PCLK 2 +.latch N_N7132 N_N8200 re PCLK 2 +.latch N_N8722 N_N8929 re PCLK 2 +.latch N_N7446 N_N7853 re PCLK 2 +.latch N_N8356 N_N9031 re PCLK 2 +.latch N_N7379 N_N8241 re PCLK 2 +.latch N_N7357 N_N7583 re PCLK 2 +.latch N_N11 NSr3_13 re PCLK 2 +.latch N_N10 N_N9248 re PCLK 2 +.latch N_N9 NSr3_14 re PCLK 2 +.latch N_N8 NSr3_20 re PCLK 2 +.latch N_N7 N_N9198 re PCLK 2 +.latch N_N6 NSr3_23 re PCLK 2 +.latch N_N5 NSr3_30 re PCLK 2 +.latch N_N4 NSr3_35 re PCLK 2 +.latch N_N3 NSr3_37 re PCLK 2 +.latch N_N2 NSr3_38 re PCLK 2 +.latch N_N1 NSr1_2 re PCLK 2 +.latch N_N0 N_N8603 re PCLK 2 +.names NEN3_28 NDN3_28 n1826 N_N9620 +1-0 1 +-10 1 +.names PRESET n1323 N_N9578 n16 +11- 1 +-10 1 +.names n16 N_N9577 +0 1 +.names PRESET n2838 n22 +01 1 +.names N_N9552 n22 N_N9551 +11 1 +.names N_N9550 n22 N_N9549 +11 1 +.names NDN3_19 NEN3_19 n1826 N_N9543 +1-0 1 +-10 1 +.names N_N9539 n22 N_N9538 +11 1 +.names N_N9510 n22 N_N9509 +11 1 +.names PRESET n413 n3115 N_N9247 n41 +0-1- 1 +00-1 1 +.names n41 N_N9248 N_N9461 +11 1 +.names NDN3_2 n1607 n1826 N_N9443 +1-0 1 +-00 1 +.names NDN3_39 NEN3_39 n1826 N_N9425 +1-0 1 +-10 1 +.names N_N9410 n22 N_N9409 +11 1 +.names N_N9331 n22 N_N9330 +11 1 +.names NDN3_26 NDN3_25 n1826 N_N9328 +1-0 1 +-10 1 +.names N_N9298 n22 N_N9297 +11 1 +.names N_N9296 n22 N_N9295 +11 1 +.names N_N9294 n22 N_N9293 +11 1 +.names N_N9280 n22 N_N9279 +11 1 +.names N_N9275 n22 N_N9274 +11 1 +.names N_N9244 n22 N_N9243 +11 1 +.names N_N9242 n22 N_N9241 +11 1 +.names N_N9150 n22 N_N9149 +11 1 +.names PRESET n1323 N_N9160 n103 +11- 1 +-10 1 +.names n103 N_N9111 +0 1 +.names PRESET n1323 N_N9162 n126 +11- 1 +-10 1 +.names n126 N_N9039 +0 1 +.names N_N9013 n22 N_N9012 +11 1 +.names N_N8972 n22 N_N8971 +11 1 +.names N_N8970 n22 N_N8969 +11 1 +.names N_N8968 n22 N_N8967 +11 1 +.names N_N9441 n22 N_N8952 +11 1 +.names N_N8935 n22 N_N8934 +11 1 +.names PRESET n1804 n1807 N_N8933 n156 +1-1- 1 +-11- 1 +1--0 1 +-1-0 1 +.names n156 N_N8926 +0 1 +.names PRESET n1807 n1808 N_N8923 n157 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names n157 N_N8922 +0 1 +.names N_N8875 n22 N_N8874 +11 1 +.names PRESET n1323 N_N9161 n191 +11- 1 +-10 1 +.names n191 N_N8829 +0 1 +.names NEN3_34 n1826 NGFDN_3 n1855 n193 +0-1- 1 +-11- 1 +0--1 1 +-1-1 1 +.names n193 N_N8825 +0 1 +.names PRESET PDN n196 +00 1 +.names n196 NLC1_2 NSr1_2 N_N8814 +11- 1 +1-1 1 +.names N_N8803 n22 N_N8802 +11 1 +.names N_N8796 n22 N_N8795 +11 1 +.names N_N8756 n22 N_N8755 +11 1 +.names N_N9559 n22 N_N8737 +11 1 +.names N_N9198 n1799 n1800 n227 +101 1 +.names PRESET N_N8929 n227 N_N8722 +01- 1 +0-1 1 +.names N_N8710 n22 N_N8709 +11 1 +.names N_N8691 n22 N_N8690 +11 1 +.names N_N8685 n22 N_N8684 +11 1 +.names N_N8615 n22 N_N8614 +11 1 +.names N_N8613 n22 N_N8612 +11 1 +.names N_N8577 n22 N_N8576 +11 1 +.names NDN3_2 NDN3_4 n1826 N_N8565 +1-0 1 +-10 1 +.names NDN3_16 NEN3_16 n1826 N_N8540 +1-0 1 +-10 1 +.names N_N8647 n22 N_N8527 +11 1 +.names N_N8508 n22 N_N8507 +11 1 +.names PRESET n1798 N_N8478 +00 1 +.names PRESET n1798 n315 +01 1 +.names N_N8668 n315 N_N8451 +11 1 +.names N_N8447 n22 N_N8446 +11 1 +.names NDN3_4 NDN3_7 n1826 N_N8399 +1-0 1 +-10 1 +.names PRESET n1807 n2064 N_N9011 n338 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names n338 N_N8385 +0 1 +.names N_N8366 n22 N_N8365 +11 1 +.names N_N9357 n22 N_N8364 +11 1 +.names N_N9436 n22 N_N8363 +11 1 +.names PRESET n1807 n2079 N_N9031 n349 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names n349 N_N8356 +0 1 +.names N_N8348 n22 N_N8347 +11 1 +.names N_N9560 n22 N_N8345 +11 1 +.names NEN3_39 n1826 NGFDN_3 n2093 n360 +0-1- 1 +-11- 1 +0--1 1 +-1-1 1 +.names n360 N_N8317 +0 1 +.names N_N8312 n22 N_N8311 +11 1 +.names NEN3_22 n1826 NGFDN_3 n2099 n365 +0-1- 1 +-11- 1 +0--1 1 +-1-1 1 +.names n365 N_N8299 +0 1 +.names NDN3_25 NDN3_22 n1826 N_N8293 +1-0 1 +-10 1 +.names PRESET n1807 n2104 N_N8964 n370 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names n370 N_N8286 +0 1 +.names PRESET n1807 n2108 N_N8847 n371 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names n371 N_N8283 +0 1 +.names NDN3_28 NDN3_29 n1826 N_N8217 +1-0 1 +-10 1 +.names N_N8270 n22 N_N8190 +11 1 +.names PRESET n1807 n2142 N_N8993 n404 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names n404 N_N8181 +0 1 +.names N_N9289 n22 N_N8178 +11 1 +.names N_N8173 n22 N_N8172 +11 1 +.names N_N8171 n22 N_N8170 +11 1 +.names N_N8572 n22 N_N8169 +11 1 +.names n1500 n2105 n1508 n1504 n1516 n1512 n3010 n3011 n413 +11111111 1 +.names PRESET n413 N_N8147 +01 1 +.names N_N8141 n22 N_N8140 +11 1 +.names N_N8236 n22 N_N8137 +11 1 +.names N_N8529 n22 N_N8136 +11 1 +.names PRESET NDN2_2 n2782 N_N8122 +010 1 +.names N_N8118 n22 N_N8117 +11 1 +.names N_N8037 n22 N_N8036 +11 1 +.names N_N8199 n22 N_N8025 +11 1 +.names N_N8016 n22 N_N8015 +11 1 +.names N_N9440 n22 N_N7998 +11 1 +.names N_N7985 n22 N_N7984 +11 1 +.names N_N7983 n22 N_N7982 +11 1 +.names N_N9363 n22 N_N7981 +11 1 +.names N_N7961 n22 N_N7960 +11 1 +.names N_N9291 n22 N_N7957 +11 1 +.names N_N8272 n22 N_N7894 +11 1 +.names N_N8196 n22 N_N7893 +11 1 +.names NEN3_36 n1826 NGFDN_3 n2247 n486 +0-1- 1 +-11- 1 +0--1 1 +-1-1 1 +.names n486 N_N7891 +0 1 +.names NDN3_22 NEN3_22 n1826 N_N7883 +1-0 1 +-10 1 +.names N_N9362 n22 N_N7870 +11 1 +.names PRESET n1807 n2268 N_N8978 n501 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names n501 N_N7828 +0 1 +.names N_N9361 n22 N_N7799 +11 1 +.names N_N9438 n22 N_N7796 +11 1 +.names N_N9556 n22 N_N7795 +11 1 +.names N_N8650 n22 N_N7785 +11 1 +.names PRESET n1807 n2282 N_N8869 n515 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names n515 N_N7750 +0 1 +.names PRESET n1807 n2284 N_N8798 n516 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names n516 N_N7747 +0 1 +.names NDN3_42 NDN3_40 n1826 N_N7690 +1-0 1 +-10 1 +.names N_N8237 n22 N_N7633 +11 1 +.names N_N9358 n22 N_N7608 +11 1 +.names NDN3_44 n1826 N_N7098 n571 +0-0 1 +-10 1 +.names n571 N_N7574 +0 1 +.names N_N8240 n22 N_N7548 +11 1 +.names N_N8531 n22 N_N7547 +11 1 +.names PRESET n1807 n2363 N_N9034 n584 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names n584 N_N7538 +0 1 +.names PRESET n1807 n2365 N_N8911 n585 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names n585 N_N7535 +0 1 +.names NEN3_28 n1826 NGFDN_3 n2373 n590 +0-1- 1 +-11- 1 +0--1 1 +-1-1 1 +.names n590 N_N7529 +0 1 +.names N_N7768 n22 N_N7528 +11 1 +.names N_N7701 n22 N_N7515 +11 1 +.names NEN3_19 n1826 NGFDN_3 n2419 n625 +0-1- 1 +-11- 1 +0--1 1 +-1-1 1 +.names n625 N_N7477 +0 1 +.names Preset_0_0_ n1608 N_N7476 n626 +00- 1 +0-1 1 +-11 1 +.names PRESET n626 N_N7475 +01 1 +.names N_N9561 n22 N_N7470 +11 1 +.names N_N8235 n22 N_N7465 +11 1 +.names NDN3_11 NDN3_12 n1826 N_N7460 +1-0 1 +-10 1 +.names N_N9290 n22 N_N7451 +11 1 +.names N_N9360 n22 N_N7450 +11 1 +.names N_N9439 n22 N_N7449 +11 1 +.names N_N7852 n22 N_N7448 +11 1 +.names N_N8197 n22 N_N7447 +11 1 +.names N_N7853 n22 N_N7446 +11 1 +.names PRESET n1807 n2433 N_N8561 n640 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names n640 N_N7439 +0 1 +.names N_N9557 n22 N_N7397 +11 1 +.names N_N9442 n22 N_N7382 +11 1 +.names N_N8241 n22 N_N7379 +11 1 +.names N_N8528 n22 N_N7377 +11 1 +.names N_N8239 n22 N_N7371 +11 1 +.names N_N7583 n22 N_N7357 +11 1 +.names N_N7582 n22 N_N7318 +11 1 +.names N_N8269 n22 N_N7313 +11 1 +.names N_N8571 n22 N_N7312 +11 1 +.names N_N8570 n22 N_N7305 +11 1 +.names N_N7584 n22 N_N7301 +11 1 +.names N_N7703 n22 N_N7294 +11 1 +.names N_N8649 n22 N_N7280 +11 1 +.names N_N9554 n22 N_N7266 +11 1 +.names N_N7630 n22 N_N7238 +11 1 +.names NDN3_42 NDN3_44 n1826 N_N7232 +1-0 1 +-10 1 +.names N_N8648 n22 N_N7194 +11 1 +.names PRESET n1323 N_N9163 n778 +11- 1 +-10 1 +.names n778 N_N7193 +0 1 +.names NDN3_7 NDN3_9 n1826 N_N7188 +1-0 1 +-10 1 +.names N_N7702 n22 N_N7163 +11 1 +.names N_N7769 n22 N_N7162 +11 1 +.names NDN3_39 NDN3_40 n1826 N_N7158 +1-0 1 +-10 1 +.names N_N9437 n22 N_N7137 +11 1 +.names N_N8200 n22 N_N7132 +11 1 +.names N_N8575 n22 N_N7131 +11 1 +.names N_N9359 n22 N_N7126 +11 1 +.names NDN3_11 NDN3_9 n1826 N_N7096 +1-0 1 +-10 1 +.names PRESET n1807 n2648 N_N8913 n834 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names n834 N_N7095 +0 1 +.names PRESET n1807 n2650 N_N8631 n835 +11-- 1 +-11- 1 +1--0 1 +--10 1 +.names n835 N_N7094 +0 1 +.names NDN3_16 NDN3_17 n1826 N_N7087 +1-0 1 +-10 1 +.names n315 n227 N_N8930 N_N7077 +11- 1 +1-1 1 +.names N_N8573 n22 N_N7063 +11 1 +.names PRESET n1323 N_N9164 n861 +11- 1 +-10 1 +.names n861 N_N7059 +0 1 +.names N_N8198 n22 N_N7048 +11 1 +.names N_N8271 n22 N_N7047 +11 1 +.names N_N7771 n22 N_N7042 +11 1 +.names NEN3_16 n1826 NGFDN_3 n2693 n874 +0-1- 1 +-11- 1 +0--1 1 +-1-1 1 +.names n874 N_N7038 +0 1 +.names PRESET n1323 N_N9166 n880 +11- 1 +-10 1 +.names n880 N_N7030 +0 1 +.names NDN1_4 n196 N_N7015 +11 1 +.names N_N8273 n22 N_N7007 +11 1 +.names N_N8574 n22 N_N7006 +11 1 +.names N_N7770 n22 N_N7001 +11 1 +.names N_N7854 n22 N_N7000 +11 1 +.names N_N9555 n22 N_N6995 +11 1 +.names N_N8530 n22 N_N6982 +11 1 +.names N_N7628 n22 N_N6971 +11 1 +.names N_N7629 n22 N_N6958 +11 1 +.names N_N7704 n22 N_N6957 +11 1 +.names N_N9558 n22 N_N6942 +11 1 +.names N_N8238 n22 N_N6941 +11 1 +.names PRESET n1323 N_N9165 n942 +11- 1 +-10 1 +.names n942 N_N6928 +0 1 +.names N_N9292 n22 N_N6927 +11 1 +.names N_N8646 n22 N_N6926 +11 1 +.names N_N8274 n22 N_N6924 +11 1 +.names N_N7627 n22 N_N6917 +11 1 +.names n196 NDN3_12 NAK3_13 NSr3_13 n955 +1--0 1 +111- 1 +.names n955 N_N11 +0 1 +.names N_N9248 n315 n413 n956 +01- 1 +-11 1 +.names n956 N_N10 +0 1 +.names n196 NAK3_13 NSr3_13 NSr3_14 n957 +1--0 1 +110- 1 +.names n957 N_N9 +0 1 +.names n196 NDN3_17 NAK3_13 NSr3_20 n958 +1--0 1 +111- 1 +.names n958 N_N8 +0 1 +.names N_N9248 n315 n413 n1799 n959 +01-0 1 +-110 1 +.names n959 N_N7 +0 1 +.names NDN3_19 n196 NAK3_13 NSr3_23 n960 +-1-0 1 +111- 1 +.names n960 N_N6 +0 1 +.names NDN3_26 n196 NAK3_13 NSr3_30 n961 +-1-0 1 +111- 1 +.names n961 N_N5 +0 1 +.names n196 NDN3_29 NAK3_13 NSr3_35 n962 +1--0 1 +111- 1 +.names n962 N_N4 +0 1 +.names NEN3_34 n196 NAK3_13 NSr3_37 n963 +-1-0 1 +111- 1 +.names n963 N_N3 +0 1 +.names NEN3_36 n196 NAK3_13 NSr3_38 n964 +-1-0 1 +111- 1 +.names n964 N_N2 +0 1 +.names n196 NSr1_2 NGFDN_3 n2782 n965 +10-- 1 +1-1- 1 +1--1 1 +.names n965 N_N1 +0 1 +.names PRESET N_N8603 n3007 n3133 n966 +00-0 1 +0-00 1 +.names n966 N_N0 +0 1 +.names PRESET n2838 n1323 +1- 1 +-1 1 +.names N_N9552 N_N9363 n2857 n2858 n1347 +00-- 1 +0-0- 1 +-0-1 1 +--01 1 +.names N_N9362 N_N9361 n2853 n2855 n1348 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names N_N9360 N_N9359 n2849 n2851 n1349 +00-- 1 +0-1- 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n459 +11 1 +.names n232 n440 n345 n460 +111 1 +.names n196 n459 n410 n38 n461 +1111 1 +.names n335 n425 n276 n462 +111 1 +.names n402 n69 n463 +11 1 +.names n432 n462 n464 +11 1 +.names n19 n203 n12 n15 n465 +1111 1 +.names n446 n299 n245 n445 n466 +1111 1 +.names n395 n396 n442 n467 +111 1 +.names n220 n374 n468 +11 1 +.names n39 n467 n469 +11 1 +.names n354 n423 n457 n18 n341 n141 n470 +111111 1 +.names n140 n253 n471 +1- 1 +-0 1 +.names n24 n278 n472 +1- 1 +-1 1 +.names n351 n291 n365 n364 n473 +1111 1 +.names n302 n151 n133 n474 +111 1 +.names n422 n380 n475 +11 1 +.names n342 n131 n355 n476 +111 1 +.names n468 n475 n455 n462 n423 n47 n259 n275 n477 +11111111 1 +.names n7 n416 n478 +11 1 +.names n330 n285 n243 n479 +111 1 +.names n10 n209 n359 n480 +111 1 +.names n396 n411 n348 n481 +111 1 +.names n109 n140 n482 +1- 1 +-1 1 +.names n433 n130 n483 +11 1 +.names n16 n279 n303 n484 +111 1 +.names n293 n358 n406 n422 n218 n274 n485 +111111 1 +.end diff --git a/fpga_flow/benchmarks/MCNC_big20/frisc.blif b/fpga_flow/benchmarks/MCNC_big20/frisc.blif new file mode 100644 index 000000000..46c12dc3e --- /dev/null +++ b/fpga_flow/benchmarks/MCNC_big20/frisc.blif @@ -0,0 +1,11610 @@ +.model top +.inputs tin_pdata_8_8_ tin_pdata_0_0_ tin_pdata_7_7_ preset_0_0_ \ +tin_pdata_2_2_ tin_pdata_9_9_ tin_pdata_1_1_ tin_pdata_4_4_ pclk pirq_0_0_ \ +tin_pdata_10_10_ tin_pdata_3_3_ tin_pdata_6_6_ tin_pdata_15_15_ \ +tin_pdata_11_11_ tin_pdata_14_14_ tin_pdata_12_12_ tin_pdata_5_5_ preset \ +tin_pdata_13_13_ +.outputs ppeakb_7_7_ ppeakp_12_12_ ppeakp_0_0_ ppeaka_7_7_ ppeaki_15_15_ \ +ppeaki_11_11_ ppeaki_3_3_ paddress_3_3_ pdata_8_8_ pdata_0_0_ ppeakb_14_14_ \ +ppeakb_10_10_ ppeakb_8_8_ ppeakp_1_1_ ppeaka_14_14_ ppeaka_10_10_ ppeaka_8_8_ \ +ppeaki_4_4_ paddress_15_15_ paddress_11_11_ paddress_2_2_ ppeakb_9_9_ \ +ppeakp_2_2_ ppeaka_9_9_ ppeaks_12_12_ ppeaks_0_0_ ppeaki_5_5_ paddress_5_5_ \ +pdata_7_7_ ppeakb_15_15_ ppeakp_3_3_ pwr_0_0_ ppeaks_1_1_ ppeaki_6_6_ \ +paddress_4_4_ piack_0_0_ ppeakp_13_13_ ppeakp_4_4_ ppeaka_15_15_ ppeaka_11_11_ \ +ppeaks_2_2_ ppeaki_7_7_ paddress_10_10_ paddress_7_7_ pdata_2_2_ ppeakp_5_5_ \ +ppeaks_13_13_ ppeaks_3_3_ ppeaki_14_14_ ppeaki_10_10_ ppeaki_8_8_ \ +paddress_6_6_ ppeakp_6_6_ ppeaks_4_4_ ppeaki_9_9_ paddress_9_9_ pdata_9_9_ \ +pdata_1_1_ ppeakb_11_11_ ppeakp_7_7_ ppeaks_5_5_ paddress_13_13_ paddress_8_8_ \ +ppeakp_14_14_ ppeakp_10_10_ ppeakp_8_8_ ppeaks_6_6_ ppeaki_13_13_ pdata_4_4_ \ +ppeakb_0_0_ ppeakp_9_9_ ppeaka_0_0_ ppeaks_7_7_ ppeakb_1_1_ ppeaka_1_1_ \ +ppeaks_10_10_ ppeaks_8_8_ pdata_10_10_ pdata_3_3_ ppeakb_12_12_ ppeakb_2_2_ \ +ppeaka_12_12_ ppeaka_2_2_ ppeaks_15_15_ ppeaks_9_9_ ppeakb_3_3_ ppeakp_15_15_ \ +ppeakp_11_11_ ppeaka_13_13_ ppeaka_3_3_ paddress_14_14_ paddress_12_12_ \ +pdata_6_6_ ppeakb_13_13_ ppeakb_4_4_ pdn ppeaka_4_4_ ppeaki_0_0_ prd_0_0_ \ +pdata_15_15_ pdata_11_11_ ppeakb_5_5_ ppeaka_5_5_ ppeaks_14_14_ ppeaki_1_1_ \ +paddress_1_1_ pdata_14_14_ pdata_12_12_ pdata_5_5_ ppeakb_6_6_ ppeaka_6_6_ \ +ppeaks_11_11_ ppeaki_12_12_ ppeaki_2_2_ paddress_0_0_ pdata_13_13_ +.latch [4244] ndout re pclk 2 +.latch [4259] ppeakb_12_12_ re pclk 2 +.latch [4274] ppeakb_1_1_ re pclk 2 +.latch [4289] ppeaka_6_6_ re pclk 2 +.latch [4304] [4295] re pclk 2 +.latch [4319] [4310] re pclk 2 +.latch [4334] ppeaks_5_5_ re pclk 2 +.latch [4349] ppeakp_10_10_ re pclk 2 +.latch [4364] [4355] re pclk 2 +.latch [4379] [4370] re pclk 2 +.latch [4394] [4385] re pclk 2 +.latch [4409] [4400] re pclk 2 +.latch [4424] [4415] re pclk 2 +.latch [4439] [4430] re pclk 2 +.latch [4454] [4445] re pclk 2 +.latch [4469] [4460] re pclk 2 +.latch [4484] [4475] re pclk 2 +.latch [4499] [4490] re pclk 2 +.latch [4514] [4505] re pclk 2 +.latch [4529] [4520] re pclk 2 +.latch [4544] [4535] re pclk 2 +.latch [4559] [4550] re pclk 2 +.latch [4574] [4565] re pclk 2 +.latch [4589] [4580] re pclk 2 +.latch [4604] [4595] re pclk 2 +.latch [4619] [4610] re pclk 2 +.latch [4634] [4625] re pclk 2 +.latch [4649] [4640] re pclk 2 +.latch [4664] [4655] re pclk 2 +.latch [4679] [4670] re pclk 2 +.latch [4709] [4700] re pclk 2 +.latch [4724] [4715] re pclk 2 +.latch [4739] [4730] re pclk 2 +.latch [4754] [4745] re pclk 2 +.latch [4769] [4760] re pclk 2 +.latch [4784] [4775] re pclk 2 +.latch [4799] [4790] re pclk 2 +.latch [4814] [4805] re pclk 2 +.latch [4829] [4820] re pclk 2 +.latch [4844] [4835] re pclk 2 +.latch [4859] [4850] re pclk 2 +.latch [4874] [4865] re pclk 2 +.latch [4889] [4880] re pclk 2 +.latch [4904] [4895] re pclk 2 +.latch [4919] [4910] re pclk 2 +.latch [4934] [4925] re pclk 2 +.latch [4949] [4940] re pclk 2 +.latch [4964] [4955] re pclk 2 +.latch [4979] [4970] re pclk 2 +.latch [4994] ppeakb_0_0_ re pclk 2 +.latch [5009] ppeaka_7_7_ re pclk 2 +.latch [5024] [5015] re pclk 2 +.latch [5039] [5030] re pclk 2 +.latch [5054] ppeaks_4_4_ re pclk 2 +.latch [5069] ppeakp_11_11_ re pclk 2 +.latch [5084] [5075] re pclk 2 +.latch [5099] [5090] re pclk 2 +.latch [5114] [5105] re pclk 2 +.latch [5129] [5120] re pclk 2 +.latch [5144] [5135] re pclk 2 +.latch [5159] [5150] re pclk 2 +.latch [5174] [5165] re pclk 2 +.latch [5189] [5180] re pclk 2 +.latch [5204] [5195] re pclk 2 +.latch [5219] [5210] re pclk 2 +.latch [5234] [5225] re pclk 2 +.latch [5249] [5240] re pclk 2 +.latch [5264] [5255] re pclk 2 +.latch [5279] [5270] re pclk 2 +.latch [5294] [5285] re pclk 2 +.latch [5309] [5300] re pclk 2 +.latch [5324] [5315] re pclk 2 +.latch [5339] [5330] re pclk 2 +.latch [5354] [5345] re pclk 2 +.latch [5369] [5360] re pclk 2 +.latch [5384] [5375] re pclk 2 +.latch [5399] [5390] re pclk 2 +.latch [5414] [5405] re pclk 2 +.latch [5429] [5420] re pclk 2 +.latch [5444] [5435] re pclk 2 +.latch [5459] [5450] re pclk 2 +.latch [5474] [5465] re pclk 2 +.latch [5489] [5480] re pclk 2 +.latch [5504] [5495] re pclk 2 +.latch [5519] [5510] re pclk 2 +.latch [5534] [5525] re pclk 2 +.latch [5549] [5540] re pclk 2 +.latch [5564] [5555] re pclk 2 +.latch [5579] [5570] re pclk 2 +.latch [5609] [5600] re pclk 2 +.latch [5624] [5615] re pclk 2 +.latch [5639] [5630] re pclk 2 +.latch [5654] [5645] re pclk 2 +.latch [5669] [5660] re pclk 2 +.latch [5684] [5675] re pclk 2 +.latch [5699] ppeakb_10_10_ re pclk 2 +.latch [5714] ppeaka_8_8_ re pclk 2 +.latch [5729] [5720] re pclk 2 +.latch [5744] ppeaks_14_14_ re pclk 2 +.latch [5759] ppeaks_7_7_ re pclk 2 +.latch [5774] ppeakp_12_12_ re pclk 2 +.latch [5789] [5780] re pclk 2 +.latch [5804] [5795] re pclk 2 +.latch [5819] [5810] re pclk 2 +.latch [5834] [5825] re pclk 2 +.latch [5849] [5840] re pclk 2 +.latch [5864] [5855] re pclk 2 +.latch [5879] [5870] re pclk 2 +.latch [5894] [5885] re pclk 2 +.latch [5909] [5900] re pclk 2 +.latch [5924] [5915] re pclk 2 +.latch [5939] [5930] re pclk 2 +.latch [5954] [5945] re pclk 2 +.latch [5969] [5960] re pclk 2 +.latch [5984] [5975] re pclk 2 +.latch [5999] [5990] re pclk 2 +.latch [6014] [6005] re pclk 2 +.latch [6029] [6020] re pclk 2 +.latch [6044] [6035] re pclk 2 +.latch [6059] [6050] re pclk 2 +.latch [6074] [6065] re pclk 2 +.latch [6089] [6080] re pclk 2 +.latch [6104] [6095] re pclk 2 +.latch [6119] [6110] re pclk 2 +.latch [6134] [6125] re pclk 2 +.latch [6149] [6140] re pclk 2 +.latch [6164] [6155] re pclk 2 +.latch [6179] [6170] re pclk 2 +.latch [6194] [6185] re pclk 2 +.latch [6209] [6200] re pclk 2 +.latch [6224] [6215] re pclk 2 +.latch [6239] [6230] re pclk 2 +.latch [6254] [6245] re pclk 2 +.latch [6269] [6260] re pclk 2 +.latch [6284] [6275] re pclk 2 +.latch [6299] [6290] re pclk 2 +.latch [6314] [6305] re pclk 2 +.latch [6329] [6320] re pclk 2 +.latch [6344] [6335] re pclk 2 +.latch [6359] [6350] re pclk 2 +.latch [6374] [6365] re pclk 2 +.latch [6389] ppeakb_11_11_ re pclk 2 +.latch [6404] ppeakb_2_2_ re pclk 2 +.latch [6419] [6410] re pclk 2 +.latch [6434] ppeaks_15_15_ re pclk 2 +.latch [6449] ppeaks_6_6_ re pclk 2 +.latch [6464] ppeakp_13_13_ re pclk 2 +.latch [6479] [6470] re pclk 2 +.latch [6494] [6485] re pclk 2 +.latch [6509] [6500] re pclk 2 +.latch [6524] [6515] re pclk 2 +.latch [6539] [6530] re pclk 2 +.latch [6554] [6545] re pclk 2 +.latch [6569] [6560] re pclk 2 +.latch [6584] [6575] re pclk 2 +.latch [6599] [6590] re pclk 2 +.latch [6614] [6605] re pclk 2 +.latch [6629] [6620] re pclk 2 +.latch [6644] [6635] re pclk 2 +.latch [6659] [6650] re pclk 2 +.latch [6674] [6665] re pclk 2 +.latch [6689] [6680] re pclk 2 +.latch [6704] [6695] re pclk 2 +.latch [6719] [6710] re pclk 2 +.latch [6734] [6725] re pclk 2 +.latch [6749] [6740] re pclk 2 +.latch [6764] [6755] re pclk 2 +.latch [6779] [6770] re pclk 2 +.latch [6794] [6785] re pclk 2 +.latch [6824] [6815] re pclk 2 +.latch [6839] [6830] re pclk 2 +.latch [6854] [6845] re pclk 2 +.latch [6869] [6860] re pclk 2 +.latch [6884] [6875] re pclk 2 +.latch [6899] [6890] re pclk 2 +.latch [6914] [6905] re pclk 2 +.latch [6929] [6920] re pclk 2 +.latch [6944] [6935] re pclk 2 +.latch [6959] [6950] re pclk 2 +.latch [6974] [6965] re pclk 2 +.latch [6989] [6980] re pclk 2 +.latch [7004] [6995] re pclk 2 +.latch [7019] [7010] re pclk 2 +.latch [7034] [7025] re pclk 2 +.latch [7064] [7055] re pclk 2 +.latch [7079] ppeaks_12_12_ re pclk 2 +.latch [7094] ppeaks_1_1_ re pclk 2 +.latch [7109] ppeakp_3_3_ re pclk 2 +.latch [7124] [7115] re pclk 2 +.latch [7139] [7130] re pclk 2 +.latch [7154] [7145] re pclk 2 +.latch [7169] [7160] re pclk 2 +.latch [7184] [7175] re pclk 2 +.latch [7199] [7190] re pclk 2 +.latch [7214] [7205] re pclk 2 +.latch [7229] [7220] re pclk 2 +.latch [7244] [7235] re pclk 2 +.latch [7259] [7250] re pclk 2 +.latch [7274] [7265] re pclk 2 +.latch [7289] [7280] re pclk 2 +.latch [7304] [7295] re pclk 2 +.latch [7319] [7310] re pclk 2 +.latch [7334] [7325] re pclk 2 +.latch [7349] [7340] re pclk 2 +.latch [7364] [7355] re pclk 2 +.latch [7379] [7370] re pclk 2 +.latch [7394] [7385] re pclk 2 +.latch [7409] [7400] re pclk 2 +.latch [7424] [7415] re pclk 2 +.latch [7439] [7430] re pclk 2 +.latch [7454] [7445] re pclk 2 +.latch [7469] [7460] re pclk 2 +.latch [7484] [7475] re pclk 2 +.latch [7499] [7490] re pclk 2 +.latch [7514] [7505] re pclk 2 +.latch [7529] [7520] re pclk 2 +.latch [7544] [7535] re pclk 2 +.latch [7559] [7550] re pclk 2 +.latch [7574] [7565] re pclk 2 +.latch [7589] [7580] re pclk 2 +.latch [7604] [7595] re pclk 2 +.latch [7634] [7625] re pclk 2 +.latch [7649] [7640] re pclk 2 +.latch [7664] [7655] re pclk 2 +.latch [7679] [7670] re pclk 2 +.latch [7694] [7685] re pclk 2 +.latch [7709] ppeaks_13_13_ re pclk 2 +.latch [7724] ppeakp_7_7_ re pclk 2 +.latch [7739] ppeakp_2_2_ re pclk 2 +.latch [7754] [7745] re pclk 2 +.latch [7769] [7760] re pclk 2 +.latch [7784] [7775] re pclk 2 +.latch [7799] [7790] re pclk 2 +.latch [7814] [7805] re pclk 2 +.latch [7829] [7820] re pclk 2 +.latch [7844] [7835] re pclk 2 +.latch [7859] [7850] re pclk 2 +.latch [7874] [7865] re pclk 2 +.latch [7889] [7880] re pclk 2 +.latch [7904] [7895] re pclk 2 +.latch [7919] [7910] re pclk 2 +.latch [7934] [7925] re pclk 2 +.latch [7949] [7940] re pclk 2 +.latch [7964] [7955] re pclk 2 +.latch [7979] [7970] re pclk 2 +.latch [8009] [8000] re pclk 2 +.latch [8024] [8015] re pclk 2 +.latch [8039] [8030] re pclk 2 +.latch [8054] [8045] re pclk 2 +.latch [8069] [8060] re pclk 2 +.latch [8084] [8075] re pclk 2 +.latch [8099] [8090] re pclk 2 +.latch [8114] [8105] re pclk 2 +.latch [8129] [8120] re pclk 2 +.latch [8144] [8135] re pclk 2 +.latch [8159] [8150] re pclk 2 +.latch [8174] [8165] re pclk 2 +.latch [8189] [8180] re pclk 2 +.latch [8204] [8195] re pclk 2 +.latch [8219] [8210] re pclk 2 +.latch [8234] [8225] re pclk 2 +.latch [8249] [8240] re pclk 2 +.latch [8264] [8255] re pclk 2 +.latch [8294] [8285] re pclk 2 +.latch [8309] [8300] re pclk 2 +.latch [8324] [8315] re pclk 2 +.latch [8339] [8330] re pclk 2 +.latch [8354] ppeaks_3_3_ re pclk 2 +.latch [8369] ppeakp_8_8_ re pclk 2 +.latch [8384] ppeakp_1_1_ re pclk 2 +.latch [8399] [8390] re pclk 2 +.latch [8414] [8405] re pclk 2 +.latch [8429] [8420] re pclk 2 +.latch [8444] [8435] re pclk 2 +.latch [8459] [8450] re pclk 2 +.latch [8474] [8465] re pclk 2 +.latch [8489] [8480] re pclk 2 +.latch [8504] [8495] re pclk 2 +.latch [8519] [8510] re pclk 2 +.latch [8534] [8525] re pclk 2 +.latch [8549] [8540] re pclk 2 +.latch [8564] [8555] re pclk 2 +.latch [8579] [8570] re pclk 2 +.latch [8594] [8585] re pclk 2 +.latch [8609] [8600] re pclk 2 +.latch [8624] [8615] re pclk 2 +.latch [8639] [8630] re pclk 2 +.latch [8654] [8645] re pclk 2 +.latch [8669] [8660] re pclk 2 +.latch [8684] [8675] re pclk 2 +.latch [8699] [8690] re pclk 2 +.latch [8714] [8705] re pclk 2 +.latch [8729] [8720] re pclk 2 +.latch [8744] [8735] re pclk 2 +.latch [8759] [8750] re pclk 2 +.latch [8774] [8765] re pclk 2 +.latch [8789] [8780] re pclk 2 +.latch [8819] [8810] re pclk 2 +.latch [8834] [8825] re pclk 2 +.latch [8849] [8840] re pclk 2 +.latch [8864] [8855] re pclk 2 +.latch [8879] [8870] re pclk 2 +.latch [8894] [8885] re pclk 2 +.latch [8909] [8900] re pclk 2 +.latch [8924] [8915] re pclk 2 +.latch [8939] [8930] re pclk 2 +.latch [8954] [8945] re pclk 2 +.latch [8969] [8960] re pclk 2 +.latch [8984] [8975] re pclk 2 +.latch [8999] ppeaks_11_11_ re pclk 2 +.latch [9014] ppeaks_2_2_ re pclk 2 +.latch [9029] ppeakp_9_9_ re pclk 2 +.latch [9044] ppeakp_0_0_ re pclk 2 +.latch [9059] [9050] re pclk 2 +.latch [9074] [9065] re pclk 2 +.latch [9089] [9080] re pclk 2 +.latch [9104] [9095] re pclk 2 +.latch [9119] [9110] re pclk 2 +.latch [9134] [9125] re pclk 2 +.latch [9149] [9140] re pclk 2 +.latch [9164] [9155] re pclk 2 +.latch [9179] [9170] re pclk 2 +.latch [9194] [9185] re pclk 2 +.latch [9209] [9200] re pclk 2 +.latch [9224] [9215] re pclk 2 +.latch [9239] [9230] re pclk 2 +.latch [9254] [9245] re pclk 2 +.latch [9269] [9260] re pclk 2 +.latch [9284] [9275] re pclk 2 +.latch [9299] [9290] re pclk 2 +.latch [9314] [9305] re pclk 2 +.latch [9329] [9320] re pclk 2 +.latch [9344] [9335] re pclk 2 +.latch [9359] [9350] re pclk 2 +.latch [9374] [9365] re pclk 2 +.latch [9389] [9380] re pclk 2 +.latch [9404] [9395] re pclk 2 +.latch [9419] [9410] re pclk 2 +.latch [9449] [9440] re pclk 2 +.latch [9464] [9455] re pclk 2 +.latch [9479] [9470] re pclk 2 +.latch [9494] [9485] re pclk 2 +.latch [9509] [9500] re pclk 2 +.latch [9524] [9515] re pclk 2 +.latch [9539] [9530] re pclk 2 +.latch [9554] [9545] re pclk 2 +.latch [9569] [9560] re pclk 2 +.latch [9584] [9575] re pclk 2 +.latch [9599] [9590] re pclk 2 +.latch [9614] [9605] re pclk 2 +.latch [9629] [9620] re pclk 2 +.latch [9644] [9635] re pclk 2 +.latch [9659] [9650] re pclk 2 +.latch [9674] [9665] re pclk 2 +.latch [9689] [9680] re pclk 2 +.latch [9704] ppeaki_6_6_ re pclk 2 +.latch [9719] [9710] re pclk 2 +.latch [9734] [9725] re pclk 2 +.latch [9749] [9740] re pclk 2 +.latch [9779] [9770] re pclk 2 +.latch [9794] [9785] re pclk 2 +.latch [9809] [9800] re pclk 2 +.latch [9824] [9815] re pclk 2 +.latch [9839] [9830] re pclk 2 +.latch [9854] [9845] re pclk 2 +.latch [9869] [9860] re pclk 2 +.latch [9884] [9875] re pclk 2 +.latch [9899] [9890] re pclk 2 +.latch [9914] [9905] re pclk 2 +.latch [9929] [9920] re pclk 2 +.latch [9944] [9935] re pclk 2 +.latch [9959] [9950] re pclk 2 +.latch [9989] [9980] re pclk 2 +.latch [10004] [9995] re pclk 2 +.latch [10019] [10010] re pclk 2 +.latch [10034] [10025] re pclk 2 +.latch [10049] [10040] re pclk 2 +.latch [10064] [10055] re pclk 2 +.latch [10079] [10070] re pclk 2 +.latch [10094] [10085] re pclk 2 +.latch [10109] [10100] re pclk 2 +.latch [10124] [10115] re pclk 2 +.latch [10139] [10130] re pclk 2 +.latch [10154] [10145] re pclk 2 +.latch [10184] [10175] re pclk 2 +.latch [10199] [10190] re pclk 2 +.latch [10214] [10205] re pclk 2 +.latch [10229] [10220] re pclk 2 +.latch [10244] ppeaki_15_15_ re pclk 2 +.latch [10259] ppeaki_4_4_ re pclk 2 +.latch [10274] [10265] re pclk 2 +.latch [10289] [10280] re pclk 2 +.latch [10319] [10310] re pclk 2 +.latch [10334] [10325] re pclk 2 +.latch [10349] [10340] re pclk 2 +.latch [10364] [10355] re pclk 2 +.latch [10379] [10370] re pclk 2 +.latch [10409] [10400] re pclk 2 +.latch [10424] [10415] re pclk 2 +.latch [10439] [10430] re pclk 2 +.latch [10454] [10445] re pclk 2 +.latch [10469] [10460] re pclk 2 +.latch [10484] [10475] re pclk 2 +.latch [10499] [10490] re pclk 2 +.latch [10514] [10505] re pclk 2 +.latch [10529] ppeaki_14_14_ re pclk 2 +.latch [10544] ppeaki_5_5_ re pclk 2 +.latch [10559] [10550] re pclk 2 +.latch [10574] [10565] re pclk 2 +.latch [10589] [10580] re pclk 2 +.latch [10604] [10595] re pclk 2 +.latch [10619] [10610] re pclk 2 +.latch [10634] [10625] re pclk 2 +.latch [10664] [10655] re pclk 2 +.latch [10679] [10670] re pclk 2 +.latch [10694] [10685] re pclk 2 +.latch [10709] [10700] re pclk 2 +.latch [10724] [10715] re pclk 2 +.latch [10739] [10730] re pclk 2 +.latch [10754] [10745] re pclk 2 +.latch [10769] [10760] re pclk 2 +.latch [10784] [10775] re pclk 2 +.latch [10799] [10790] re pclk 2 +.latch [10814] [10805] re pclk 2 +.latch [10829] [10820] re pclk 2 +.latch [10859] [10850] re pclk 2 +.latch [10874] [10865] re pclk 2 +.latch [10889] [10880] re pclk 2 +.latch [10904] [10895] re pclk 2 +.latch [10934] [10925] re pclk 2 +.latch [10949] [10940] re pclk 2 +.latch [10964] [10955] re pclk 2 +.latch [10979] [10970] re pclk 2 +.latch [10994] [10985] re pclk 2 +.latch [11024] [11015] re pclk 2 +.latch [11039] [11030] re pclk 2 +.latch [11054] [11045] re pclk 2 +.latch [11069] [11060] re pclk 2 +.latch [11084] [11075] re pclk 2 +.latch [11099] [11090] re pclk 2 +.latch [11129] [11120] re pclk 2 +.latch [11144] [11135] re pclk 2 +.latch [11159] [11150] re pclk 2 +.latch [11174] [11165] re pclk 2 +.latch [11189] [11180] re pclk 2 +.latch [11204] [11195] re pclk 2 +.latch [11219] [11210] re pclk 2 +.latch [11234] [11225] re pclk 2 +.latch [11249] [11240] re pclk 2 +.latch [11264] [11255] re pclk 2 +.latch [11279] [11270] re pclk 2 +.latch [11294] [11285] re pclk 2 +.latch [11309] [11300] re pclk 2 +.latch [11324] [11315] re pclk 2 +.latch [11339] [11330] re pclk 2 +.latch [11354] [11345] re pclk 2 +.latch [11384] [11375] re pclk 2 +.latch [11399] [11390] re pclk 2 +.latch [11414] [11405] re pclk 2 +.latch [11429] [11420] re pclk 2 +.latch [11444] [11435] re pclk 2 +.latch [11459] [11450] re pclk 2 +.latch [11474] [11465] re pclk 2 +.latch [11489] [11480] re pclk 2 +.latch [11504] [11495] re pclk 2 +.latch [11519] [11510] re pclk 2 +.latch [11534] [11525] re pclk 2 +.latch [11549] [11540] re pclk 2 +.latch [11564] [11555] re pclk 2 +.latch [11579] [11570] re pclk 2 +.latch [11594] [11585] re pclk 2 +.latch [11609] [11600] re pclk 2 +.latch [11624] [11615] re pclk 2 +.latch [11639] [11630] re pclk 2 +.latch [11654] [11645] re pclk 2 +.latch [11669] [11660] re pclk 2 +.latch [11684] [11675] re pclk 2 +.latch [11699] [11690] re pclk 2 +.latch [11714] [11705] re pclk 2 +.latch [11729] [11720] re pclk 2 +.latch [11744] [11735] re pclk 2 +.latch [11759] [11750] re pclk 2 +.latch [11774] [11765] re pclk 2 +.latch [11789] [11780] re pclk 2 +.latch [11804] [11795] re pclk 2 +.latch [11819] [11810] re pclk 2 +.latch [11864] ppeaki_9_9_ re pclk 2 +.latch [11879] ppeakb_14_14_ re pclk 2 +.latch [11894] [11885] re pclk 2 +.latch [11909] [11900] re pclk 2 +.latch [11924] [11915] re pclk 2 +.latch [11939] [11930] re pclk 2 +.latch [11984] ppeaki_8_8_ re pclk 2 +.latch [11999] ppeakb_15_15_ re pclk 2 +.latch [12014] [12005] re pclk 2 +.latch [12029] [12020] re pclk 2 +.latch [12044] [12035] re pclk 2 +.latch [12059] [12050] re pclk 2 +.latch [12074] [12065] re pclk 2 +.latch [12089] [12080] re pclk 2 +.latch [12119] ppeaki_7_7_ re pclk 2 +.latch [12134] [12125] re pclk 2 +.latch [12149] [12140] re pclk 2 +.latch [12164] [12155] re pclk 2 +.latch [12179] [12170] re pclk 2 +.latch [12194] [12185] re pclk 2 +.latch [12209] [12200] re pclk 2 +.latch [12239] ppeakb_13_13_ re pclk 2 +.latch [12254] [12245] re pclk 2 +.latch [12269] [12260] re pclk 2 +.latch [12284] [12275] re pclk 2 +.latch [12314] ppeaki_13_13_ re pclk 2 +.latch [12329] ppeaki_2_2_ re pclk 2 +.latch [12344] [12335] re pclk 2 +.latch [12359] [12350] re pclk 2 +.latch [12374] [12365] re pclk 2 +.latch [12389] [12380] re pclk 2 +.latch [12404] [12395] re pclk 2 +.latch [12419] [12410] re pclk 2 +.latch [12434] [12425] re pclk 2 +.latch [12449] [12440] re pclk 2 +.latch [12464] [12455] re pclk 2 +.latch [12479] [12470] re pclk 2 +.latch [12494] [12485] re pclk 2 +.latch [12524] ppeaki_12_12_ re pclk 2 +.latch [12539] ppeaki_3_3_ re pclk 2 +.latch [12554] [12545] re pclk 2 +.latch [12569] [12560] re pclk 2 +.latch [12584] [12575] re pclk 2 +.latch [12599] [12590] re pclk 2 +.latch [12614] [12605] re pclk 2 +.latch [12629] [12620] re pclk 2 +.latch [12644] [12635] re pclk 2 +.latch [12659] [12650] re pclk 2 +.latch [12674] [12665] re pclk 2 +.latch [12689] [12680] re pclk 2 +.latch [12704] [12695] re pclk 2 +.latch [12749] ppeaki_11_11_ re pclk 2 +.latch [12764] ppeaki_0_0_ re pclk 2 +.latch [12779] [12770] re pclk 2 +.latch [12809] [12800] re pclk 2 +.latch [12824] [12815] re pclk 2 +.latch [12839] [12830] re pclk 2 +.latch [12854] [12845] re pclk 2 +.latch [12869] [12860] re pclk 2 +.latch [12884] [12875] re pclk 2 +.latch [12899] [12890] re pclk 2 +.latch [12914] [12905] re pclk 2 +.latch [12929] [12920] re pclk 2 +.latch [12944] [12935] re pclk 2 +.latch [12989] ppeaki_10_10_ re pclk 2 +.latch [13004] ppeaki_1_1_ re pclk 2 +.latch [13019] [13010] re pclk 2 +.latch [13034] [13025] re pclk 2 +.latch [13049] [13040] re pclk 2 +.latch [13064] [13055] re pclk 2 +.latch [13079] [13070] re pclk 2 +.latch [13094] [13085] re pclk 2 +.latch [13109] [13100] re pclk 2 +.latch [13124] [13115] re pclk 2 +.latch [13139] [13130] re pclk 2 +.latch [13169] [13160] re pclk 2 +.latch [13184] [13175] re pclk 2 +.latch [13199] ppeakb_4_4_ re pclk 2 +.latch [13214] ppeaka_9_9_ re pclk 2 +.latch [13229] [13220] re pclk 2 +.latch [13244] [13235] re pclk 2 +.latch [13259] [13250] re pclk 2 +.latch [13274] [13265] re pclk 2 +.latch [13289] [13280] re pclk 2 +.latch [13304] [13295] re pclk 2 +.latch [13319] [13310] re pclk 2 +.latch [13334] [13325] re pclk 2 +.latch [13349] [13340] re pclk 2 +.latch [13364] [13355] re pclk 2 +.latch [13379] [13370] re pclk 2 +.latch [13394] [13385] re pclk 2 +.latch [13409] [13400] re pclk 2 +.latch [13424] [13415] re pclk 2 +.latch [13439] [13430] re pclk 2 +.latch [13454] [13445] re pclk 2 +.latch [13469] [13460] re pclk 2 +.latch [13484] [13475] re pclk 2 +.latch [13499] [13490] re pclk 2 +.latch [13514] [13505] re pclk 2 +.latch [13544] ppeakb_5_5_ re pclk 2 +.latch [13559] [13550] re pclk 2 +.latch [13574] ppeakp_6_6_ re pclk 2 +.latch [13589] [13580] re pclk 2 +.latch [13604] [13595] re pclk 2 +.latch [13619] [13610] re pclk 2 +.latch [13634] [13625] re pclk 2 +.latch [13649] [13640] re pclk 2 +.latch [13664] [13655] re pclk 2 +.latch [13679] [13670] re pclk 2 +.latch [13694] [13685] re pclk 2 +.latch [13709] [13700] re pclk 2 +.latch [13724] [13715] re pclk 2 +.latch [13739] [13730] re pclk 2 +.latch [13754] [13745] re pclk 2 +.latch [13784] [13775] re pclk 2 +.latch [13799] [13790] re pclk 2 +.latch [13814] [13805] re pclk 2 +.latch [13829] [13820] re pclk 2 +.latch [13844] [13835] re pclk 2 +.latch [13859] [13850] re pclk 2 +.latch [13874] [13865] re pclk 2 +.latch [13889] [13880] re pclk 2 +.latch [13904] [13895] re pclk 2 +.latch [13919] ppeaka_11_11_ re pclk 2 +.latch [13934] ppeaka_0_0_ re pclk 2 +.latch [13949] ppeakp_5_5_ re pclk 2 +.latch [13964] [13955] re pclk 2 +.latch [13979] [13970] re pclk 2 +.latch [13994] [13985] re pclk 2 +.latch [14009] [14000] re pclk 2 +.latch [14024] [14015] re pclk 2 +.latch [14039] [14030] re pclk 2 +.latch [14054] [14045] re pclk 2 +.latch [14069] [14060] re pclk 2 +.latch [14084] [14075] re pclk 2 +.latch [14099] [14090] re pclk 2 +.latch [14114] [14105] re pclk 2 +.latch [14129] [14120] re pclk 2 +.latch [14144] [14135] re pclk 2 +.latch [14159] [14150] re pclk 2 +.latch [14174] [14165] re pclk 2 +.latch [14189] [14180] re pclk 2 +.latch [14219] [14210] re pclk 2 +.latch [14234] [14225] re pclk 2 +.latch [14249] [14240] re pclk 2 +.latch [14264] [14255] re pclk 2 +.latch [14279] [14270] re pclk 2 +.latch [14294] [14285] re pclk 2 +.latch [14309] ppeakb_3_3_ re pclk 2 +.latch [14324] ppeaka_10_10_ re pclk 2 +.latch [14339] ppeaka_1_1_ re pclk 2 +.latch [14354] ppeakp_4_4_ re pclk 2 +.latch [14369] [14360] re pclk 2 +.latch [14384] [14375] re pclk 2 +.latch [14399] [14390] re pclk 2 +.latch [14414] [14405] re pclk 2 +.latch [14429] [14420] re pclk 2 +.latch [14444] [14435] re pclk 2 +.latch [14459] [14450] re pclk 2 +.latch [14474] [14465] re pclk 2 +.latch [14489] [14480] re pclk 2 +.latch [14504] [14495] re pclk 2 +.latch [14519] [14510] re pclk 2 +.latch [14534] [14525] re pclk 2 +.latch [14549] [14540] re pclk 2 +.latch [14564] [14555] re pclk 2 +.latch [14579] [14570] re pclk 2 +.latch [14594] [14585] re pclk 2 +.latch [14609] [14600] re pclk 2 +.latch [14624] [14615] re pclk 2 +.latch [14639] [14630] re pclk 2 +.latch [14669] [14660] re pclk 2 +.latch [14684] [14675] re pclk 2 +.latch [14699] [14690] re pclk 2 +.latch [14714] [14705] re pclk 2 +.latch [14729] ppeakb_8_8_ re pclk 2 +.latch [14744] ppeaka_13_13_ re pclk 2 +.latch [14759] ppeaka_2_2_ re pclk 2 +.latch [14774] [14765] re pclk 2 +.latch [14789] ppeaks_9_9_ re pclk 2 +.latch [14804] ppeakp_14_14_ re pclk 2 +.latch [14819] [14810] re pclk 2 +.latch [14834] [14825] re pclk 2 +.latch [14849] [14840] re pclk 2 +.latch [14864] [14855] re pclk 2 +.latch [14879] [14870] re pclk 2 +.latch [14894] [14885] re pclk 2 +.latch [14909] [14900] re pclk 2 +.latch [14924] [14915] re pclk 2 +.latch [14939] [14930] re pclk 2 +.latch [14969] [14960] re pclk 2 +.latch [14984] [14975] re pclk 2 +.latch [14999] [14990] re pclk 2 +.latch [15014] [15005] re pclk 2 +.latch [15029] [15020] re pclk 2 +.latch [15044] [15035] re pclk 2 +.latch [15059] [15050] re pclk 2 +.latch [15074] [15065] re pclk 2 +.latch [15089] [15080] re pclk 2 +.latch [15104] ppeakb_9_9_ re pclk 2 +.latch [15119] ppeaka_12_12_ re pclk 2 +.latch [15134] ppeaka_3_3_ re pclk 2 +.latch [15149] [15140] re pclk 2 +.latch [15164] ppeaks_8_8_ re pclk 2 +.latch [15179] ppeakp_15_15_ re pclk 2 +.latch [15194] [15185] re pclk 2 +.latch [15209] [15200] re pclk 2 +.latch [15224] [15215] re pclk 2 +.latch [15239] [15230] re pclk 2 +.latch [15254] [15245] re pclk 2 +.latch [15269] [15260] re pclk 2 +.latch [15284] [15275] re pclk 2 +.latch [15299] [15290] re pclk 2 +.latch [15314] [15305] re pclk 2 +.latch [15329] [15320] re pclk 2 +.latch [15344] [15335] re pclk 2 +.latch [15359] [15350] re pclk 2 +.latch [15374] [15365] re pclk 2 +.latch [15389] [15380] re pclk 2 +.latch [15404] [15395] re pclk 2 +.latch [15419] [15410] re pclk 2 +.latch [15434] [15425] re pclk 2 +.latch [15449] [15440] re pclk 2 +.latch [15464] ppeakb_6_6_ re pclk 2 +.latch [15479] ppeaka_15_15_ re pclk 2 +.latch [15494] ppeaka_4_4_ re pclk 2 +.latch [15509] [15500] re pclk 2 +.latch [15524] [15515] re pclk 2 +.latch [15539] ppeaks_0_0_ re pclk 2 +.latch [15554] [15545] re pclk 2 +.latch [15569] [15560] re pclk 2 +.latch [15584] [15575] re pclk 2 +.latch [15599] [15590] re pclk 2 +.latch [15614] [15605] re pclk 2 +.latch [15629] [15620] re pclk 2 +.latch [15644] [15635] re pclk 2 +.latch [15659] [15650] re pclk 2 +.latch [15674] [15665] re pclk 2 +.latch [15689] [15680] re pclk 2 +.latch [15704] [15695] re pclk 2 +.latch [15719] [15710] re pclk 2 +.latch [15734] [15725] re pclk 2 +.latch [15764] [15755] re pclk 2 +.latch [15779] [15770] re pclk 2 +.latch [15794] [15785] re pclk 2 +.latch [15809] ppeakb_7_7_ re pclk 2 +.latch [15824] ppeaka_14_14_ re pclk 2 +.latch [15839] ppeaka_5_5_ re pclk 2 +.latch [15854] [15845] re pclk 2 +.latch [15869] [15860] re pclk 2 +.latch [15884] ppeaks_10_10_ re pclk 2 +.latch [15899] [15890] re pclk 2 +.latch [15914] [15905] re pclk 2 +.latch [15929] [15920] re pclk 2 +.latch [15944] [15935] re pclk 2 +.latch [15959] [15950] re pclk 2 +.latch [15974] [15965] re pclk 2 +.latch [15989] [15980] re pclk 2 +.latch [16004] [15995] re pclk 2 +.latch [16019] [16010] re pclk 2 +.latch [16034] [16025] re pclk 2 +.latch [16049] [16040] re pclk 2 +.latch [16064] [16055] re pclk 2 +.latch [16079] [16070] re pclk 2 +.latch [16094] [16085] re pclk 2 +.latch [16109] [16100] re pclk 2 +.latch [16904] paddress_8_8_ re pclk 2 +.latch [16917] [16907] re pclk 2 +.latch [16928] [16920] re pclk 2 +.latch [16941] [16933] re pclk 2 +.latch [16956] paddress_9_9_ re pclk 2 +.latch [16969] [16959] re pclk 2 +.latch [16980] [16972] re pclk 2 +.latch [16993] [16985] re pclk 2 +.latch [17008] [16998] re pclk 2 +.latch [17021] [17011] re pclk 2 +.latch [17032] [17024] re pclk 2 +.latch [17045] [17037] re pclk 2 +.latch [17058] [17050] re pclk 2 +.latch [17073] [17063] re pclk 2 +.latch [17086] [17076] re pclk 2 +.latch [17097] [17089] re pclk 2 +.latch [17110] [17102] re pclk 2 +.latch [17123] [17115] re pclk 2 +.latch [17138] [17128] re pclk 2 +.latch [17151] [17141] re pclk 2 +.latch [17162] [17154] re pclk 2 +.latch [17175] [17167] re pclk 2 +.latch [17188] [17180] re pclk 2 +.latch [17203] [17193] re pclk 2 +.latch [17214] [17206] re pclk 2 +.latch [17227] [17219] re pclk 2 +.latch [17240] [17232] re pclk 2 +.latch [17253] [17245] re pclk 2 +.latch [17268] [17258] re pclk 2 +.latch [17279] [17271] re pclk 2 +.latch [17292] [17284] re pclk 2 +.latch [17305] [17297] re pclk 2 +.latch [17318] [17310] re pclk 2 +.latch [17333] [17323] re pclk 2 +.latch [17346] [17336] re pclk 2 +.latch [17357] [17349] re pclk 2 +.latch [17370] [17362] re pclk 2 +.latch [17383] [17375] re pclk 2 +.latch [17396] [17388] re pclk 2 +.latch [17411] paddress_11_11_ re pclk 2 +.latch [17422] [17414] re pclk 2 +.latch [17435] [17427] re pclk 2 +.latch [17461] [17453] re pclk 2 +.latch [17476] paddress_10_10_ re pclk 2 +.latch [17489] [17479] re pclk 2 +.latch [17502] [17492] re pclk 2 +.latch [17513] [17505] re pclk 2 +.latch [17526] [17518] re pclk 2 +.latch [17539] [17531] re pclk 2 +.latch [17554] [17544] re pclk 2 +.latch [17567] paddress_13_13_ re pclk 2 +.latch [17578] [17570] re pclk 2 +.latch [17591] [17583] re pclk 2 +.latch [17604] [17596] re pclk 2 +.latch [17619] [17609] re pclk 2 +.latch [17632] paddress_12_12_ re pclk 2 +.latch [17643] [17635] re pclk 2 +.latch [17656] [17648] re pclk 2 +.latch [17669] [17661] re pclk 2 +.latch [17684] [17674] re pclk 2 +.latch [17697] paddress_15_15_ re pclk 2 +.latch [17708] [17700] re pclk 2 +.latch [17723] [17713] re pclk 2 +.latch [17736] paddress_14_14_ re pclk 2 +.latch [17747] [17739] re pclk 2 +.latch [17760] [17752] re pclk 2 +.latch [17775] [17765] re pclk 2 +.latch [17788] [17778] re pclk 2 +.latch [17799] [17791] re pclk 2 +.latch [17812] [17804] re pclk 2 +.latch [17825] [17817] re pclk 2 +.latch [17840] pwr_0_0_ re pclk 2 +.latch [17851] [17843] re pclk 2 +.latch [17866] [17856] re pclk 2 +.latch [17879] [17869] re pclk 2 +.latch [17892] [17882] re pclk 2 +.latch [17905] prd_0_0_ re pclk 2 +.latch [17918] [17908] re pclk 2 +.latch [17931] [17921] re pclk 2 +.latch [17944] [17934] re pclk 2 +.latch [17957] [17947] re pclk 2 +.latch [17970] [17960] re pclk 2 +.latch [17983] [17973] re pclk 2 +.latch [17994] [17986] re pclk 2 +.latch [18007] [17999] re pclk 2 +.latch [18022] [18012] re pclk 2 +.latch [18033] [18025] re pclk 2 +.latch [18048] [18038] re pclk 2 +.latch [18059] pdn re pclk 2 +.latch [18072] [18064] re pclk 2 +.latch [18085] [18077] re pclk 2 +.latch [18100] [18090] re pclk 2 +.latch [18111] [18103] re pclk 2 +.latch [18126] [18116] re pclk 2 +.latch [18139] [18129] re pclk 2 +.latch [18150] [18142] re pclk 2 +.latch [18165] [18155] re pclk 2 +.latch [18176] [18168] re pclk 2 +.latch [18191] [18181] re pclk 2 +.latch [18204] [18194] re pclk 2 +.latch [18215] [18207] re pclk 2 +.latch [18228] [18220] re pclk 2 +.latch [18243] [18233] re pclk 2 +.latch [18254] [18246] re pclk 2 +.latch [18269] paddress_0_0_ re pclk 2 +.latch [18282] piack_0_0_ re pclk 2 +.latch [18293] [18285] re pclk 2 +.latch [18306] [18298] re pclk 2 +.latch [18319] [18311] re pclk 2 +.latch [18334] paddress_1_1_ re pclk 2 +.latch [18347] [18337] re pclk 2 +.latch [18360] [18350] re pclk 2 +.latch [18371] [18363] re pclk 2 +.latch [18384] [18376] re pclk 2 +.latch [18397] [18389] re pclk 2 +.latch [18412] paddress_2_2_ re pclk 2 +.latch [18423] [18415] re pclk 2 +.latch [18436] [18428] re pclk 2 +.latch [18449] [18441] re pclk 2 +.latch [18464] paddress_3_3_ re pclk 2 +.latch [18475] [18467] re pclk 2 +.latch [18488] [18480] re pclk 2 +.latch [18501] [18493] re pclk 2 +.latch [18514] [18506] re pclk 2 +.latch [18529] paddress_4_4_ re pclk 2 +.latch [18542] paddress_5_5_ re pclk 2 +.latch [18555] [18545] re pclk 2 +.latch [18568] paddress_6_6_ re pclk 2 +.latch [18581] [18571] re pclk 2 +.latch [18594] [18584] re pclk 2 +.latch [18605] [18597] re pclk 2 +.latch [18618] [18610] re pclk 2 +.latch [18633] paddress_7_7_ re pclk 2 +.latch [18644] [18636] re pclk 2 +.names tin_pdata_8_8_ [16959] [17882] pdata_8_8_ +-11 1 +1-0 1 +.names tin_pdata_0_0_ [17479] [18337] pdata_0_0_ +10- 1 +-11 1 +.names tin_pdata_7_7_ [16907] [17869] pdata_7_7_ +-11 1 +1-0 1 +.names tin_pdata_2_2_ [17323] [18181] pdata_2_2_ +-11 1 +1-0 1 +.names tin_pdata_9_9_ [17765] [18571] pdata_9_9_ +-11 1 +1-0 1 +.names tin_pdata_1_1_ [17258] [18116] pdata_1_1_ +-11 1 +1-0 1 +.names tin_pdata_4_4_ [17193] [18038] pdata_4_4_ +-11 1 +1-0 1 +.names tin_pdata_10_10_ [17011] [17921] pdata_10_10_ +10- 1 +-11 1 +.names tin_pdata_3_3_ [17128] [17960] pdata_3_3_ +-11 1 +1-0 1 +.names tin_pdata_6_6_ [17063] [17934] pdata_6_6_ +-11 1 +1-0 1 +.names tin_pdata_15_15_ [17076] [17947] pdata_15_15_ +-11 1 +1-0 1 +.names tin_pdata_11_11_ [17336] [18194] pdata_11_11_ +10- 1 +-11 1 +.names tin_pdata_14_14_ [17778] [18584] pdata_14_14_ +-11 1 +1-0 1 +.names tin_pdata_12_12_ [17141] [17973] pdata_12_12_ +10- 1 +-11 1 +.names tin_pdata_5_5_ [16998] [17908] pdata_5_5_ +-11 1 +1-0 1 +.names tin_pdata_13_13_ [17492] [18350] pdata_13_13_ +-11 1 +1-0 1 +.names pdata_2_2_ [4305] [5582] [4244] +--1 1 +11- 1 +.names [17615] [17616] [17621] [4259] +1-- 1 +-1- 1 +--1 1 +.names [17626] [17627] [17631] [4274] +1-- 1 +-1- 1 +--1 1 +.names [17641] [17642] [17647] [4289] +1-- 1 +-1- 1 +--1 1 +.names [5455] [5456] [17652] [4304] +1-- 1 +-1- 1 +--1 1 +.names [5451] [5452] [17654] [4319] +1-- 1 +-1- 1 +--1 1 +.names [17672] [17673] [17678] [4334] +1-- 1 +-1- 1 +--1 1 +.names [5407] [5410] [5411] [17705] [4349] +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names pdata_0_0_ [4352] [5403] [4364] +--1 1 +11- 1 +.names pdata_11_11_ [4352] [5398] [4379] +--1 1 +11- 1 +.names preset pdata_6_6_ [4385] nrq10_4 [4394] +01-1 1 +0-10 1 +.names pdata_1_1_ [4353] [5389] [4409] +--1 1 +11- 1 +.names pdata_12_12_ [4353] [5385] [4424] +--1 1 +11- 1 +.names preset pdata_7_7_ [4430] nrq14_3 [4439] +01-1 1 +0-10 1 +.names preset pdata_2_2_ [4445] nrq14_3 [4454] +01-1 1 +0-10 1 +.names preset pdata_13_13_ [4460] nrq14_3 [4469] +01-1 1 +0-10 1 +.names pdata_8_8_ [4354] [5368] [4484] +--1 1 +11- 1 +.names pdata_3_3_ [18384] [5363] [4499] +--1 1 +11- 1 +.names pdata_14_14_ [18384] [5358] [4514] +--1 1 +11- 1 +.names [5353] [5355] [4529] +1- 1 +-1 1 +.names [5349] [5350] [4544] +1- 1 +-1 1 +.names [5344] [5346] [4559] +1- 1 +-1 1 +.names preset pdata_5_5_ [4565] nrq23_3 [4574] +01-1 1 +0-10 1 +.names preset pdata_0_0_ [4580] nrq23_3 [4589] +01-1 1 +0-10 1 +.names preset pdata_11_11_ [4595] nrq23_3 [4604] +01-1 1 +0-10 1 +.names pdata_6_6_ [4375] [5334] [4619] +--1 1 +11- 1 +.names [4625] [17461] [19360] [4340] [4634] +-11- 1 +1--1 1 +.names [4640] [17461] [4340] [19390] [4649] +1-1- 1 +-1-1 1 +.names [5143] [5145] [4664] +1- 1 +-1 1 +.names [4670] [4253] [5139] [4679] +--1 1 +11- 1 +.names [5132] [5133] [4709] +1- 1 +-1 1 +.names [4715] [4317] [5126] [4724] +--1 1 +11- 1 +.names [4730] [4317] [4381] [19368] [4739] +11-- 1 +--11 1 +.names [18501] [19359] [5073] [4754] +--1 1 +11- 1 +.names [4760] [4252] [5068] [4769] +--1 1 +11- 1 +.names [4775] [4252] [5063] [4784] +--1 1 +11- 1 +.names [5057] [5058] [4799] +1- 1 +-1 1 +.names [4805] [19360] [4277] [4278] [4814] +1-1- 1 +-1-1 1 +.names [4820] [19390] [4277] [4278] [4829] +1-1- 1 +-1-1 1 +.names preset [4835] [19088] nrq4_2 [4844] +0-11 1 +01-0 1 +.names [19092] [4345] [4902] [4859] +--1 1 +11- 1 +.names [4865] [19103] [4330] [4374] [4874] +1-1- 1 +-1-1 1 +.names [4374] [4388] [4511] [4834] [4889] +---1 1 +111- 1 +100- 1 +.names [19060] [4360] [4828] [4904] +--1 1 +11- 1 +.names [4910] [19097] [4331] [4332] [4919] +1-1- 1 +-1-1 1 +.names [4925] [4277] [4278] [19061] [4934] +11-- 1 +--11 1 +.names [4940] [4277] [4278] [19091] [4949] +11-- 1 +--11 1 +.names [4955] [19088] [4336] [4365] [4964] +1-1- 1 +-1-1 1 +.names pdata_1_1_ [4305] [4807] [4979] +--1 1 +11- 1 +.names [18037] [18039] [18043] [4994] +1-- 1 +-1- 1 +--1 1 +.names [18051] [18052] [18056] [5009] +1-- 1 +-1- 1 +--1 1 +.names [4773] [4774] [18057] [5024] +1-- 1 +-1- 1 +--1 1 +.names [4768] [4770] [18060] [5039] +1-- 1 +-1- 1 +--1 1 +.names [18071] [18073] [18078] [5054] +1-- 1 +-1- 1 +--1 1 +.names [4742] [4746] [4747] [18080] [5069] +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names pdata_1_1_ [4352] [4741] [5084] +--1 1 +11- 1 +.names pdata_10_10_ [4352] [4738] [5099] +--1 1 +11- 1 +.names pdata_2_2_ [4353] [4736] [5114] +--1 1 +11- 1 +.names pdata_11_11_ [4353] [4734] [5129] +--1 1 +11- 1 +.names preset pdata_8_8_ [5135] nrq14_3 [5144] +01-1 1 +0-10 1 +.names preset pdata_1_1_ [5150] nrq14_3 [5159] +01-1 1 +0-10 1 +.names preset pdata_14_14_ [5165] nrq14_3 [5174] +01-1 1 +0-10 1 +.names pdata_7_7_ [4354] [4725] [5189] +--1 1 +11- 1 +.names pdata_4_4_ [18384] [4719] [5204] +--1 1 +11- 1 +.names pdata_13_13_ [18384] [4717] [5219] +--1 1 +11- 1 +.names [4714] [4716] [5234] +1- 1 +-1 1 +.names [4712] [4713] [5249] +1- 1 +-1 1 +.names [4710] [4711] [5264] +1- 1 +-1 1 +.names preset pdata_4_4_ [5270] nrq23_3 [5279] +01-1 1 +0-10 1 +.names preset pdata_1_1_ [5285] nrq23_3 [5294] +01-1 1 +0-10 1 +.names preset pdata_10_10_ [5300] nrq23_3 [5309] +01-1 1 +0-10 1 +.names pdata_7_7_ [4375] [4702] [5324] +--1 1 +11- 1 +.names [17461] n_n2471 n_n2487 [4698] [5339] +---1 1 +101- 1 +110- 1 +.names [5345] [4340] [4697] [5354] +--1 1 +11- 1 +.names [19390] [4308] [4694] [5369] +--1 1 +11- 1 +.names [5375] [4253] [4693] [5384] +--1 1 +11- 1 +.names [4306] n_n2471 n_n2487 [4690] [5399] +---1 1 +101- 1 +110- 1 +.names [4306] [19359] [4688] [5414] +--1 1 +11- 1 +.names [5420] [4317] [4686] [5429] +--1 1 +11- 1 +.names [5435] [4317] [4381] [19367] [5444] +11-- 1 +--11 1 +.names [4682] [4683] [5459] +1- 1 +-1 1 +.names [17305] [19359] [4680] [5474] +--1 1 +11- 1 +.names [5480] [4245] [4252] [19367] [5489] +1-1- 1 +-1-1 1 +.names [4377] [19387] [4673] [5504] +--1 1 +11- 1 +.names [5510] [4277] [4669] [5519] +--1 1 +11- 1 +.names [5525] [4277] [4667] [5534] +--1 1 +11- 1 +.names preset [5540] [19070] nrq4_2 [5549] +0-11 1 +01-0 1 +.names [4345] [19096] [4657] [5564] +--1 1 +11- 1 +.names [5570] [4330] [4374] [19097] [5579] +11-- 1 +--11 1 +.names [4360] [19072] [4648] [5609] +--1 1 +11- 1 +.names [5615] [19103] [4331] [4332] [5624] +1-1- 1 +-1-1 1 +.names [17240] [19072] [4643] [5639] +--1 1 +11- 1 +.names [5645] [4277] [4278] [19087] [5654] +11-- 1 +--11 1 +.names [5660] [4336] [4365] [19082] [5669] +11-- 1 +--11 1 +.names pdata_0_0_ [4305] [4629] [5684] +--1 1 +11- 1 +.names [18114] [18115] [18120] [5699] +1-- 1 +-1- 1 +--1 1 +.names [18128] [18130] [18134] [5714] +1-- 1 +-1- 1 +--1 1 +.names [4596] [4597] [18135] [5729] +1-- 1 +-1- 1 +--1 1 +.names [18147] [18148] [18153] [5744] +1-- 1 +-1- 1 +--1 1 +.names [18163] [18164] [18170] [5759] +1-- 1 +-1- 1 +--1 1 +.names [4551] [4554] [4555] [18172] [5774] +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names pdata_2_2_ [4352] [4549] [5789] +--1 1 +11- 1 +.names preset pdata_4_4_ [5795] nrq10_4 [5804] +01-1 1 +0-10 1 +.names preset pdata_8_8_ [5810] nrq10_4 [5819] +01-1 1 +0-10 1 +.names preset pdata_9_9_ [5825] nrq14_3 [5834] +01-1 1 +0-10 1 +.names preset pdata_4_4_ [5840] nrq14_3 [5849] +01-1 1 +0-10 1 +.names preset pdata_11_11_ [5855] nrq14_3 [5864] +01-1 1 +0-10 1 +.names pdata_6_6_ [4354] [4536] [5879] +--1 1 +11- 1 +.names pdata_5_5_ [18384] [4532] [5894] +--1 1 +11- 1 +.names [4530] [4531] [5909] +1- 1 +-1 1 +.names [4527] [4528] [5924] +1- 1 +-1 1 +.names [4525] [4526] [5939] +1- 1 +-1 1 +.names [4523] [4524] [5954] +1- 1 +-1 1 +.names preset pdata_7_7_ [5960] nrq23_3 [5969] +01-1 1 +0-10 1 +.names preset pdata_14_14_ [5975] nrq23_3 [5984] +01-1 1 +0-10 1 +.names preset pdata_9_9_ [5990] nrq23_3 [5999] +01-1 1 +0-10 1 +.names pdata_8_8_ [4375] [4506] [6014] +--1 1 +11- 1 +.names [6020] [17461] [4340] [19396] [6029] +1-1- 1 +-1-1 1 +.names [6035] [4340] [4497] [6044] +--1 1 +11- 1 +.names [4493] [4494] [6059] +1- 1 +-1 1 +.names [6065] [4253] [4492] [6074] +--1 1 +11- 1 +.names [6080] [4243] [4253] [19367] [6089] +1-1- 1 +-1-1 1 +.names [4291] [4406] [6104] +1- 1 +-1 1 +.names [6110] [4317] [4381] [19387] [6119] +11-- 1 +--11 1 +.names [18501] n_n2471 n_n2487 [4263] [6134] +---1 1 +101- 1 +110- 1 +.names [4257] [4262] [6149] +1- 1 +-1 1 +.names [4250] [4251] [6164] +1- 1 +-1 1 +.names [6170] [4252] [4249] [6179] +--1 1 +11- 1 +.names [4246] [4247] [6194] +1- 1 +-1 1 +.names [6200] [4277] [4278] [19396] [6209] +11-- 1 +--11 1 +.names [6215] [4277] [4278] [19367] [6224] +11-- 1 +--11 1 +.names preset [6230] [19103] nrq4_2 [6239] +0-11 1 +01-0 1 +.names [19070] [4383] [4230] [6254] +--1 1 +11- 1 +.names [4345] [19061] [4227] [6269] +--1 1 +11- 1 +.names [4360] [19073] [4218] [6284] +--1 1 +11- 1 +.names [4360] [19096] [4213] [6299] +--1 1 +11- 1 +.names [6305] [4331] [4332] [19061] [6314] +11-- 1 +--11 1 +.names [4307] [4388] [4511] [4196] [6329] +---1 1 +111- 1 +100- 1 +.names [6335] [4277] [4278] [19068] [6344] +11-- 1 +--11 1 +.names [6350] [4336] [4365] [19072] [6359] +11-- 1 +--11 1 +.names [4365] [4388] [4511] [4188] [6374] +---1 1 +111- 1 +100- 1 +.names [18189] [18190] [18196] [6389] +1-- 1 +-1- 1 +--1 1 +.names [18201] [18202] [18208] [6404] +1-- 1 +-1- 1 +--1 1 +.names [4160] [4161] [18209] [6419] +1-- 1 +-1- 1 +--1 1 +.names [18221] [18222] [18226] [6434] +1-- 1 +-1- 1 +--1 1 +.names [18237] [18238] [18242] [6449] +1-- 1 +-1- 1 +--1 1 +.names [4121] [4124] [4125] [18245] [6464] +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names pdata_12_12_ [4352] [4120] [6479] +--1 1 +11- 1 +.names preset pdata_5_5_ [6485] nrq10_4 [6494] +01-1 1 +0-10 1 +.names preset pdata_7_7_ [6500] nrq10_4 [6509] +01-1 1 +0-10 1 +.names preset pdata_10_10_ [6515] nrq14_3 [6524] +01-1 1 +0-10 1 +.names preset pdata_3_3_ [6530] nrq14_3 [6539] +01-1 1 +0-10 1 +.names preset pdata_12_12_ [6545] nrq14_3 [6554] +01-1 1 +0-10 1 +.names pdata_5_5_ [4354] [4108] [6569] +--1 1 +11- 1 +.names pdata_6_6_ [18384] [4105] [6584] +--1 1 +11- 1 +.names pdata_15_15_ [18384] [4103] [6599] +--1 1 +11- 1 +.names [4101] [4102] [6614] +1- 1 +-1 1 +.names [4099] [4100] [6629] +1- 1 +-1 1 +.names preset pdata_6_6_ [6635] nrq23_3 [6644] +01-1 1 +0-10 1 +.names preset pdata_15_15_ [6650] nrq23_3 [6659] +01-1 1 +0-10 1 +.names preset pdata_8_8_ [6665] nrq23_3 [6674] +01-1 1 +0-10 1 +.names pdata_9_9_ [4375] [4092] [6689] +--1 1 +11- 1 +.names [6695] [4340] [4090] [6704] +--1 1 +11- 1 +.names [6710] [4340] [4088] [6719] +--1 1 +11- 1 +.names [4308] [19367] [4085] [6734] +--1 1 +11- 1 +.names [6740] [4243] [4253] [19387] [6749] +1-1- 1 +-1-1 1 +.names [6755] [4243] [4253] [19368] [6764] +1-1- 1 +-1-1 1 +.names [4079] [4080] [6779] +1- 1 +-1 1 +.names [6785] [4317] [4077] [6794] +--1 1 +11- 1 +.names [4075] [4076] [6824] +1- 1 +-1 1 +.names [4073] [4074] [6839] +1- 1 +-1 1 +.names [6845] [4245] [4252] [19396] [6854] +1-1- 1 +-1-1 1 +.names [6860] [4245] [4252] [19390] [6869] +1-1- 1 +-1-1 1 +.names [6875] [4277] [4067] [6884] +--1 1 +11- 1 +.names [6890] [4277] [4065] [6899] +--1 1 +11- 1 +.names preset [6905] [19082] nrq4_2 [6914] +0-11 1 +01-0 1 +.names [19072] [4383] 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[4199] [3746] n_n2772 [2949] +1111 1 +.names ppeakb_11_11_ [4199] n_n2772 [4215] [2950] +1111 1 +.names [7820] [4199] [3727] n_n2772 [2951] +1111 1 +.names [4295] [4199] n_n2772 [4207] [2952] +1111 1 +.names [13490] [4199] [3715] n_n2772 [2955] +1111 1 +.names [5120] [4199] [3740] n_n2772 [2956] +1111 1 +.names [9650] [4199] [3718] n_n2772 [2957] +1111 1 +.names [7145] [4199] [3723] n_n2772 [2959] +1111 1 +.names ppeaka_11_11_ [4199] [3744] [4515] [2962] +1--1 1 +111- 1 +.names preset [13895] [17791] [17843] [2963] +010- 1 +01-1 1 +.names [13880] [4316] [2966] +11 1 +.names preset [13835] [17999] [18077] [2972] +011- 1 +01-0 1 +.names preset [13820] [17427] [17648] [2974] +010- 1 +01-1 1 +.names preset [13790] nrq7_2 [17715] [2977] +010- 1 +01-0 1 +.names [17305] n_n2483 [19725] [19479] [2978] +1111 1 +1001 1 +1010 1 +1100 1 +.names preset [13775] nrq7_2 [17714] [2979] +010- 1 +01-0 1 +.names preset [13745] [18103] [18168] [2981] +011- 1 +01-0 1 +.names [4308] n_n2480 [19737] [19520] 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[4199] [3746] n_n2772 [3067] +1111 1 +.names [9125] [4199] [3727] n_n2772 [3069] +1111 1 +.names [5720] [4199] n_n2772 [4207] [3070] +1111 1 +.names [15770] [4199] [3715] n_n2772 [3073] +1111 1 +.names [13265] [4199] [3740] n_n2772 [3074] +1111 1 +.names [9905] [4199] [3718] n_n2772 [3075] +1111 1 +.names [5825] [4199] [3723] n_n2772 [3077] +1111 1 +.names ppeaka_9_9_ [4199] [3744] [4515] [3080] +1--1 1 +111- 1 +.names ppeaka_4_4_ [4199] n_n2772 [4224] [3081] +1111 1 +.names [14495] [4199] [3747] n_n2772 [3082] +1111 1 +.names [7280] [4199] [3744] n_n2772 [3083] +1111 1 +.names [12545] [4199] n_n2772 [3720] [3084] +1111 1 +.names [9170] [4199] [3711] n_n2772 [3085] +1111 1 +.names [5195] [4199] [3738] n_n2772 [3086] +1111 1 +.names [8585] [4199] [3718] n_n2772 [3087] +1111 1 +.names [14765] [4226] n_n2772 [3089] +111 1 +.names [5840] [4199] [3723] n_n2772 [3090] +1111 1 +.names ppeakb_4_4_ [4199] [4211] [4515] [3092] +1--1 1 +111- 1 +.names preset [13130] [17999] [18077] [3098] +011- 1 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1 +01-0 1 +.names preset [12860] [17427] [17648] [3134] +010- 1 +01-1 1 +.names preset [12845] [17427] [17648] [3136] +010- 1 +01-1 1 +.names preset [12830] nrq7_2 [17715] [3137] +010- 1 +01-0 1 +.names [17305] n_n2480 [19737] [19520] [3138] +1111 1 +1001 1 +1010 1 +1100 1 +.names preset [12815] nrq7_2 [17714] [3139] +010- 1 +01-0 1 +.names [16928] n_n2474 [19514] [19733] [3140] +1111 1 +1001 1 +1010 1 +1100 1 +.names preset [12800] [18103] [18168] [3141] +011- 1 +01-0 1 +.names [4308] n_n2477 [19735] [19504] [3142] +1111 1 +1001 1 +1010 1 +1100 1 +.names preset [12770] nrq7_2 [17714] [3143] +010- 1 +01-0 1 +.names preset pdata_14_14_ nrq7_2 [17714] [3144] +0111 1 +.names preset ppeaki_0_0_ n_n2772 [5522] [3145] +010- 1 +01-1 1 +.names [12695] [4202] [4266] [5514] [3146] +1--1 1 +101- 1 +.names preset ppeaki_11_11_ n_n2772 [5522] [3150] +010- 1 +01-1 1 +.names [11600] [4202] [4266] [5514] [3151] +1--1 1 +101- 1 +.names preset [12695] [17570] [17635] [3154] +010- 1 +01-1 1 +.names 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[17427] [17648] [3197] +010- 1 +01-1 1 +.names preset [12365] nrq7_2 [17714] [3198] +010- 1 +01-0 1 +.names preset [12350] nrq7_2 [17714] [3200] +010- 1 +01-0 1 +.names [16928] n_n2483 [19725] [19479] [3201] +1111 1 +1001 1 +1010 1 +1100 1 +.names [18176] n_n2480 [19737] [19520] [3203] +1111 1 +1001 1 +1010 1 +1100 1 +.names preset ppeaki_2_2_ n_n2772 [5522] [3204] +010- 1 +01-1 1 +.names [11585] [4202] [4266] [5514] [3205] +1--1 1 +101- 1 +.names preset ppeaki_13_13_ n_n2772 [5522] [3209] +010- 1 +01-1 1 +.names preset [12275] [17570] [17635] [3212] +010- 1 +01-1 1 +.names preset [12260] [18142] [18220] [3214] +011- 1 +01-0 1 +.names ppeaka_13_13_ [4199] [4224] [3218] +111 1 +.names [14885] [4199] [3711] [3219] +111 1 +.names [5210] [4199] [3738] [3220] +111 1 +.names [13670] [4199] [3720] [3221] +111 1 +.names [4460] [4199] [3723] [3222] +111 1 +.names [13595] [4199] n_n2344 [3770] [3223] +1111 1 +.names [7325] [4199] [3718] [3224] +111 1 +.names [14375] [4199] n_n2344 [3775] [3225] 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[3711] [3260] +111 1 +.names [6590] [4199] [3738] [3261] +111 1 +.names [4535] [4199] [3720] [3262] +111 1 +.names [8450] [4199] [3723] [3263] +111 1 +.names [14390] [4199] n_n2344 [3770] [3264] +1111 1 +.names [8600] [4199] [3718] [3265] +111 1 +.names [13580] [4199] n_n2344 [3775] [3266] +1111 1 +.names [7295] [4199] [3744] [3267] +111 1 +.names ppeakb_15_15_ [4199] [4211] [4515] [3268] +1--1 1 +111- 1 +.names [13550] n_n3925 [5513] [5514] [3269] +111- 1 +11-1 1 +.names preset ppeaki_8_8_ n_n2772 [5522] [3270] +010- 1 +01-1 1 +.names [12485] [4202] [4266] [5514] [3271] +1--1 1 +101- 1 +.names preset [11930] [17570] [17635] [3274] +010- 1 +01-1 1 +.names preset [11915] [18142] [18220] [3276] +011- 1 +01-0 1 +.names preset [11900] [17414] [17505] [3278] +010- 1 +01-1 1 +.names preset [11885] [17414] [17505] [3280] +010- 1 +01-1 1 +.names ppeaka_14_14_ [4199] n_n2772 [4224] [3281] +1111 1 +.names [7250] [4199] [3747] n_n2772 [3282] +1111 1 +.names [7925] [4199] [3744] n_n2772 [3283] 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n_n2476 [19741] [19531] [4667] +1111 1 +1001 1 +1010 1 +1100 1 +.names [4278] n_n2485 [19466] [19721] [4669] +1111 1 +1001 1 +1010 1 +1100 1 +.names preset [5495] [18311] [18506] [4673] +011- 1 +01-0 1 +.names preset [5465] nrq7_2 [17715] [4680] +010- 1 +01-0 1 +.names preset [5450] nrq7_2 [17712] [4682] +010- 1 +01-0 1 +.names [18501] n_n2477 [19735] [19504] [4683] +1111 1 +1001 1 +1010 1 +1100 1 +.names [4381] n_n2482 [19727] [19456] [4686] +1111 1 +1001 1 +1010 1 +1100 1 +.names preset [5405] [18285] [18363] [4688] +010- 1 +01-1 1 +.names preset [5390] [18285] [18363] [4690] +010- 1 +01-1 1 +.names [4243] n_n2483 [19725] [19479] [4693] +1111 1 +1001 1 +1010 1 +1100 1 +.names preset [5360] [18103] [18168] [4694] +011- 1 +01-0 1 +.names [17461] n_n2474 [19514] [19733] [4697] +1111 1 +1001 1 +1010 1 +1100 1 +.names [5330] [4340] [4698] +11 1 +.names preset [5315] [17310] [17388] [4702] +011- 1 +01-0 1 +.names preset [5255] nrq7_2 [17715] [4710] +010- 1 +01-0 1 +.names preset pdata_11_11_ nrq7_2 [17715] [4711] +0111 1 +.names preset [5240] nrq7_2 [17714] [4712] +010- 1 +01-0 1 +.names preset pdata_5_5_ nrq7_2 [17714] [4713] +0111 1 +.names preset [5225] nrq7_2 [17712] [4714] +010- 1 +01-0 1 +.names preset pdata_10_10_ nrq7_2 [17712] [4716] +0111 1 +.names preset [5210] [17284] [18376] [4717] +010- 1 +01-1 1 +.names preset [5195] [17284] [18376] [4719] +010- 1 +01-1 1 +.names preset [5180] [17167] [17362] [4725] +010- 1 +01-1 1 +.names preset [5120] [17102] [17154] [4734] +010- 1 +01-1 1 +.names preset [5105] [17102] [17154] [4736] +010- 1 +01-1 1 +.names preset [5090] [17453] [18246] [4738] +010- 1 +01-1 1 +.names preset [5075] [17453] [18246] [4741] +010- 1 +01-1 1 +.names ppeaka_11_11_ [5413] [17694] [4742] +11- 1 +1-1 1 +.names [12020] n_n3081 [4266] [4744] +111 1 +.names ppeakp_11_11_ [17696] [17698] [17703] [4746] +11-- 1 +1-1- 1 +1--1 1 +.names ppeakb_11_11_ [4199] [3744] [4747] +111 1 +.names [12245] [4199] [3754] n_n2772 [4749] +1111 1 +.names [11765] n_n2772 n_n3081 [4266] [4750] +1111 1 +.names [14675] [4199] [3750] n_n2772 [4751] +1111 1 +.names [5615] [4199] [3715] n_n2772 [4752] +1111 1 +.names [4865] [4199] [3740] n_n2772 [4753] +1111 1 +.names [13790] [4199] [3747] n_n2772 [4755] +1111 1 +.names [9785] [4199] [3744] n_n2772 [4756] +1111 1 +.names [12350] [4199] n_n2772 [3720] [4757] +1111 1 +.names [9380] [4199] [3711] n_n2772 [4758] +1111 1 +.names [4715] [4199] [3738] n_n2772 [4759] +1111 1 +.names [6875] [4199] [3718] n_n2772 [4761] +1111 1 +.names [15035] [4226] n_n2772 [4763] +111 1 +.names [8015] [4199] [3723] n_n2772 [4764] +1111 1 +.names ppeaks_4_4_ [17660] [17662] [4766] +11- 1 +1-1 1 +.names [9185] [4199] [3744] [4768] +111 1 +.names [5030] [4515] [17649] [17650] [4770] +11-- 1 +1-1- 1 +1--1 1 +.names [13835] n_n3925 [5513] [5514] [4771] +111- 1 +11-1 1 +.names [9200] [4199] [3744] [4773] +111 1 +.names [5015] [4515] [17649] [17650] [4774] +11-- 1 +1-1- 1 +1--1 1 +.names [8180] n_n3925 [5513] [5514] [4776] +111- 1 +11-1 1 +.names [7025] [4199] [3746] n_n2772 [4777] +1111 1 +.names [5180] [4199] [3727] n_n2772 [4779] +1111 1 +.names [7055] [4199] n_n2772 [4207] [4780] +1111 1 +.names [10970] [4199] [3715] n_n2772 [4783] +1111 1 +.names [13985] [4199] [3740] n_n2772 [4785] +1111 1 +.names [10460] [4199] [3718] n_n2772 [4786] +1111 1 +.names [4430] [4199] [3723] n_n2772 [4788] +1111 1 +.names ppeaka_7_7_ [4199] [3744] [4515] [4792] +1--1 1 +111- 1 +.names ppeaka_0_0_ [4199] n_n2772 [4224] [4793] +1111 1 +.names [15995] [4199] [3747] n_n2772 [4794] +1111 1 +.names [4580] [4199] [3744] n_n2772 [4795] +1111 1 +.names [13655] [4199] n_n2772 [3720] [4796] +1111 1 +.names [5900] [4199] [3711] n_n2772 [4797] +1111 1 +.names [7835] [4199] [3738] n_n2772 [4798] +1111 1 +.names [10550] [4199] [3718] n_n2772 [4800] +1111 1 +.names [4310] [4226] n_n2772 [4802] +111 1 +.names [15605] [4199] [3723] n_n2772 [4803] +1111 1 +.names ppeakb_0_0_ [4199] [4211] [4515] [4806] +1--1 1 +111- 1 +.names preset [4970] [17791] [17843] [4807] +010- 1 +01-1 1 +.names preset [4895] [17037] [18025] [4828] +011- 1 +01-0 1 +.names [4880] [4330] [4834] +11 1 +.names [11915] [17635] [17986] n_n3925 [4849] +1101 1 +.names ppeakp_11_11_ n_n3925 ndn_latch3_9 ndn_latch12_11 [4852] +1--1 1 +101- 1 +.names [16100] [17427] [17648] [4853] +110 1 +.names [10130] [17180] [17232] [4854] +110 1 +.names ppeaka_11_11_ [17245] nrq7_2 [3746] [4855] +1011 1 +.names [13115] [17999] [18077] [4856] +101 1 +.names ppeakb_11_11_ [16933] nrq7_2 [3718] [4857] +1011 1 +.names [12050] [17635] [17986] n_n3925 [4858] +1101 1 +.names ppeakp_12_12_ n_n3925 ndn_latch3_9 ndn_latch12_11 [4861] +1--1 1 +101- 1 +.names [15755] [17427] [17648] [4862] +110 1 +.names [10415] [17180] [17232] [4863] +110 1 +.names ppeaka_12_12_ [17245] nrq7_2 [3746] [4864] +1011 1 +.names [12395] [17999] [18077] [4866] +101 1 +.names ppeakb_12_12_ [16933] nrq7_2 [3718] [4867] +1011 1 +.names [12170] [17635] [17986] n_n3925 [4868] +1101 1 +.names ppeakp_13_13_ n_n3925 ndn_latch3_9 ndn_latch12_11 [4870] +1--1 1 +101- 1 +.names [13805] [17427] [17648] [4871] +110 1 +.names [10700] [17180] [17232] [4872] +110 1 +.names ppeaka_13_13_ [17245] nrq7_2 [3746] [4873] +1011 1 +.names [12620] [17999] [18077] [4875] +101 1 +.names ppeakb_13_13_ [16933] nrq7_2 [3718] [4876] +1011 1 +.names [12260] [17635] [17986] n_n3925 [4877] +1101 1 +.names ppeakp_14_14_ n_n3925 ndn_latch3_9 ndn_latch12_11 [4879] +1--1 1 +101- 1 +.names [13445] [17427] [17648] [4881] +110 1 +.names [10985] [17180] [17232] [4882] +110 1 +.names ppeaka_14_14_ [17245] nrq7_2 [3746] [4883] +1011 1 +.names [15410] [17999] [18077] [4884] +101 1 +.names ppeakb_14_14_ [16933] nrq7_2 [3718] [4885] +1011 1 +.names [12470] [17635] [17986] n_n3925 [4886] +1101 1 +.names ppeakp_15_15_ n_n3925 ndn_latch3_9 ndn_latch12_11 [4888] +1--1 1 +101- 1 +.names [14615] [17427] [17648] [4890] +110 1 +.names [6320] [17180] [17232] [4891] +110 1 +.names ppeaka_15_15_ [17245] nrq7_2 [3746] [4892] +1011 1 +.names [15050] [17999] [18077] [4893] +101 1 +.names ppeakb_15_15_ [16933] nrq7_2 [3718] [4894] +1011 1 +.names preset [4850] [17635] [17986] [4902] +010- 1 +01-1 1 +.names [11075] [17635] [17986] n_n3925 [4916] +1101 1 +.names ppeakp_7_7_ n_n3925 ndn_latch3_9 ndn_latch12_11 [4918] +1--1 1 +101- 1 +.names [5540] [17427] [17648] [4920] +110 1 +.names [8255] [17180] [17232] [4921] +110 1 +.names ppeaka_7_7_ [17245] nrq7_2 [3746] [4922] +1011 1 +.names [14630] [17999] [18077] [4923] +101 1 +.names ppeakb_7_7_ [16933] nrq7_2 [3718] [4924] +1011 1 +.names [11330] [17635] [17986] n_n3925 [4926] +1101 1 +.names ppeakp_8_8_ n_n3925 ndn_latch3_9 ndn_latch12_11 [4928] +1--1 1 +101- 1 +.names [11420] [17427] [17648] [4929] +110 1 +.names [8915] [17180] [17232] [4930] +110 1 +.names ppeaka_8_8_ [17245] nrq7_2 [3746] [4931] +1011 1 +.names [13460] [17999] [18077] [4932] +101 1 +.names ppeakb_8_8_ [16933] nrq7_2 [3718] [4933] +1011 1 +.names [11570] [17635] [17986] n_n3925 [4935] +1101 1 +.names ppeakp_9_9_ n_n3925 ndn_latch3_9 ndn_latch12_11 [4937] +1--1 1 +101- 1 +.names [11645] [17427] [17648] [4938] +110 1 +.names [9590] [17180] [17232] [4939] +110 1 +.names ppeaka_9_9_ [17245] nrq7_2 [3746] [4941] +1011 1 +.names [13820] [17999] [18077] [4942] +101 1 +.names ppeakb_9_9_ [16933] nrq7_2 [3718] [4943] +1011 1 +.names [11795] [17635] [17986] n_n3925 [4944] +1101 1 +.names ppeakp_10_10_ n_n3925 ndn_latch3_9 ndn_latch12_11 [4946] +1--1 1 +101- 1 +.names [10925] [17427] [17648] [4947] +110 1 +.names [9860] [17180] [17232] [4948] +110 1 +.names ppeaka_10_10_ [17245] nrq7_2 [3746] [4950] +1011 1 +.names [12860] [17999] [18077] [4951] +101 1 +.names ppeakb_10_10_ [16933] nrq7_2 [3718] [4952] +1011 1 +.names ppeaka_0_0_ [16933] nrq7_2 [3718] [4978] +1011 1 +.names [11555] [17635] [17986] n_n3925 [4986] +1101 1 +.names ppeakp_0_0_ n_n3925 ndn_latch3_9 ndn_latch12_11 [4988] +1--1 1 +101- 1 +.names [11630] [17427] [17648] [4989] +110 1 +.names [13175] [17180] [17232] [4990] +110 1 +.names ppeaka_0_0_ [17245] nrq7_2 [3746] [4991] +1011 1 +.names [12605] [17999] [18077] [4992] +101 1 +.names ppeakb_0_0_ [16933] nrq7_2 [3718] [4993] +1011 1 +.names [11315] [17635] [17986] n_n3925 [4995] +1101 1 +.names ppeakp_1_1_ n_n3925 ndn_latch3_9 ndn_latch12_11 [4997] +1--1 1 +101- 1 +.names [9485] [17427] [17648] [4998] +110 1 +.names [12920] [17180] [17232] [4999] +110 1 +.names ppeaka_1_1_ [17245] nrq7_2 [3746] [5000] +1011 1 +.names [12380] [17999] [18077] [5001] +101 1 +.names ppeakb_1_1_ [16933] nrq7_2 [3718] [5002] +1011 1 +.names [11060] [17635] [17986] n_n3925 [5003] +1101 1 +.names ppeakp_2_2_ n_n3925 ndn_latch3_9 ndn_latch12_11 [5005] +1--1 1 +101- 1 +.names [7535] [17427] [17648] [5006] +110 1 +.names [12680] [17180] [17232] [5007] +110 1 +.names ppeaka_2_2_ [17245] nrq7_2 [3746] [5008] +1011 1 +.names [13100] [17999] [18077] [5010] +101 1 +.names ppeakb_2_2_ [16933] nrq7_2 [3718] [5011] +1011 1 +.names [10790] [17635] [17986] n_n3925 [5012] +1101 1 +.names ppeakp_3_3_ n_n3925 ndn_latch3_9 ndn_latch12_11 [5014] +1--1 1 +101- 1 +.names [8165] [17427] [17648] [5016] +110 1 +.names [12455] [17180] [17232] [5017] +110 1 +.names ppeaka_3_3_ [17245] nrq7_2 [3746] [5018] +1011 1 +.names [12845] [17999] [18077] [5019] +101 1 +.names ppeakb_3_3_ [16933] nrq7_2 [3718] [5020] +1011 1 +.names [10505] [17635] [17986] n_n3925 [5021] +1101 1 +.names ppeakp_4_4_ n_n3925 ndn_latch3_9 ndn_latch12_11 [5023] +1--1 1 +101- 1 +.names [6230] [17427] [17648] [5025] +110 1 +.names [12245] [17180] [17232] [5026] +110 1 +.names ppeaka_4_4_ [17245] nrq7_2 [3746] [5027] +1011 1 +.names [15035] [17999] [18077] [5028] +101 1 +.names ppeakb_4_4_ [16933] nrq7_2 [3718] [5029] +1011 1 +.names [10220] [17635] [17986] n_n3925 [5031] +1101 1 +.names ppeakp_5_5_ n_n3925 ndn_latch3_9 ndn_latch12_11 [5033] +1--1 1 +101- 1 +.names [6905] [17427] [17648] [5034] +110 1 +.names [6995] [17180] [17232] [5035] +110 1 +.names ppeaka_5_5_ [17245] nrq7_2 [3746] [5036] +1011 1 +.names [15395] [17999] [18077] [5037] +101 1 +.names ppeakb_5_5_ [16933] nrq7_2 [3718] [5038] +1011 1 +.names [9950] [17635] [17986] n_n3925 [5040] +1101 1 +.names ppeakp_6_6_ n_n3925 ndn_latch3_9 ndn_latch12_11 [5042] +1--1 1 +101- 1 +.names [4835] [17427] [17648] [5043] +110 1 +.names [7625] [17180] [17232] [5044] +110 1 +.names ppeaka_6_6_ [17245] nrq7_2 [3746] [5045] +1011 1 +.names [14210] [17999] [18077] [5046] +101 1 +.names ppeakb_6_6_ [16933] nrq7_2 [3718] [5047] +1011 1 +.names [4377] n_n2480 [19737] [19520] [5057] +1111 1 +1001 1 +1010 1 +1100 1 +.names preset [4790] [18311] [18506] [5058] +011- 1 +01-0 1 +.names [4245] n_n2474 [19514] [19733] [5063] +1111 1 +1001 1 +1010 1 +1100 1 +.names [4245] n_n2485 [19466] [19721] [5068] +1111 1 +1001 1 +1010 1 +1100 1 +.names preset [4745] nrq7_2 [17712] [5073] +010- 1 +01-0 1 +.names [5106] [17836] [17844] [5088] +001 1 +.names ppeaka_15_15_ [4453] [5271] [5272] [5091] +00-- 1 +0-00 1 +.names [6755] [18285] [18363] [5094] +110 1 +.names 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n2502 n2501 +1----- 1 +-1---- 1 +--0--- 1 +---1-- 1 +----0- 1 +-----1 1 +.names n899 n491 n516 n508 n2504 +11-- 1 +1-11 1 +.names n876 n875 n868 n958 n203 n607 n2505 +111111 1 +.names n446 n542 n954 n955 n2106 n2133 n2431 n2505 n2506 +11001111 1 +.names n1798 n909 n1800 n938 n930 n925 n2509 +111111 1 +.names n1793 n1794 n1787 n1789 n1795 n942 n1797 n2509 n2510 +11111111 1 +.names n47 n71 n1380 n2512 +001 1 +.names n982 n980 n1762 n2512 n2511 +0-0- 1 +-00- 1 +0--1 1 +-0-1 1 +.names n64 n961 n1804 n2513 +011 1 +.names n1366 n2512 n2515 +0- 1 +-1 1 +.names n491 n508 n892 n2515 n2514 +1--1 1 +-101 1 +.names n1006 n1605 n2032 n1005 n2204 n2205 n789 n791 n2516 +11111111 1 +.names n546 n1578 n2517 +11 1 +.names n2277 n2360 n2300 n2518 +111 1 +.names n815 n1021 n1565 n2347 n2519 +-0-1 1 +1-11 1 +.names n135 n280 n291 n448 n2520 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names n2380 n2130 n2394 n2521 +111 1 +.names n2384 n2128 n2235 n2207 n2403 n2150 n2365 n2521 n2522 +11111111 1 +.names n236 n2281 n2369 n2523 +111 1 +.names n135 n280 n1055 n1058 n2524 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names n810 n1275 n2526 +11 1 +.names n1021 n1566 n2526 n2525 +01- 1 +-11 1 +.names n2385 n2433 n2232 n2279 n2366 n2049 n2528 +111111 1 +.names n2370 n1588 n2383 n2529 +111 1 +.names n2193 n2095 n2286 n2530 +111 1 +.names n136 n1081 n1130 n1133 n1230 n2114 n2192 n2530 n2531 +01001111 1 +.names n88 n139 n212 n381 n2534 +101- 1 +1-11 1 +.names n1107 n1925 n1933 n1098 n1940 n1124 n1917 n2534 n2535 +11111111 1 +.names n17 n21 n1184 n1196 n2536 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names n1124 n1046 n1968 n874 n1301 n1795 n2539 +111111 1 +.names n743 n1526 n2540 +11 1 +.names n2207 n2403 n1841 n2110 n1567 n2139 n1603 n803 n2541 +11111111 1 +.names n2479 n1061 n2543 +1- 1 +-1 1 +.names n291 n426 n1196 n1207 n2544 +-0-0 1 +1-10 1 +.names n21 n1145 n2547 +0- 1 +-1 1 +.names n2547 n2439 n2544 n2546 +111 1 +.names n296 n1205 n1493 n1206 n2548 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n17 n24 n371 n800 n2549 +0-0- 1 +-00- 1 +0--1 1 +-0-1 1 +.names n135 n260 n616 n1248 n2550 +0-0- 1 +-10- 1 +0--1 1 +-1-1 1 +.names n312 n324 n360 n479 n2551 +11-- 1 +1-0- 1 +-1-0 1 +--00 1 +.names n6 n180 n837 n1428 n2552 +01-- 1 +-11- 1 +0--1 1 +--11 1 +.names n722 n579 n2552 n2551 n2550 n2549 n2548 n2546 n2553 +11111111 1 +.names n1794 n76 n902 n914 n807 n843 n1577 n1604 n2554 +11111111 1 +.names n1176 n1152 n1197 n1282 n1925 n1203 n1872 n1087 n2555 +11111111 1 +.names n300 n707 n1019 n1253 n2556 +0-0- 1 +-10- 1 +0--1 1 +-1-1 1 +.names n135 n426 n611 n1474 n2557 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names n1789 n1676 n1665 n1643 n2557 n2556 n2558 +111111 1 +.names n918 n2092 n728 n1631 n1630 n237 n2559 +111111 1 +.names n354 n1007 n1238 n1478 n2560 +0-0- 1 +-101 1 +.names n616 n1240 n1329 n2011 n2562 +00-- 1 +-011 1 +.names n39 n1265 n2012 n2562 n2564 +-1-1 1 +0-11 1 +.names n360 n1016 n1236 n2011 n2565 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names n263 n381 n400 n580 n2566 +11-- 1 +1-0- 1 +-1-1 1 +--01 1 +.names n295 n1379 n296 n261 n2567 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n2566 n2567 n1428 n959 n2568 +111- 1 +11-1 1 +.names n2376 n2438 n2284 n2560 n2559 n2565 n2564 n2568 n2569 +11111111 1 +.names n426 n543 n768 n1405 n2570 +01-1 1 +-111 1 +.names n1652 n811 n1669 n1772 n820 n806 n1555 n2570 n2571 +11111111 1 +.names n1793 n77 n1022 n2572 +111 1 +.names n1966 n1176 n1228 n1297 n1284 n1086 n1107 n2572 n2573 +11111111 1 +.names n34 n2042 n2574 +0- 1 +-1 1 +.names n2300 n2089 n1049 n1611 n1601 n2356 n2575 +111111 1 +.names n616 n1252 n1579 n2576 +0-1 1 +-11 1 +.names n318 n426 n1249 n2101 n2577 +10-- 1 +1-1- 1 +-0-1 1 +--11 1 +.names n332 n704 n1270 n1493 n2578 +01-- 1 +-11- 1 +0--1 1 +--11 1 +.names n364 n1520 n2578 n2579 +0-1 1 +-11 1 +.names n2577 n2579 n1820 n545 n2580 +111- 1 +11-1 1 +.names n334 n401 n864 n1043 n2581 +10-- 1 +1-1- 1 +-0-1 1 +--11 1 +.names n300 n1352 n2581 n2582 +0-1 1 +-11 1 +.names n1411 n296 n345 n2583 +11- 1 +1-1 1 +.names n2351 n2336 n1994 n2576 n2575 n2583 n2582 n2580 n2584 +11111111 1 +.names n603 n1582 n1629 n343 n441 n548 n2585 +111111 1 +.names n841 n1672 n1681 n869 n1798 n2585 n2586 +111111 1 +.names n1036 n1066 n1078 n2587 +111 1 +.names n1152 n1228 n2033 n1296 n1241 n1098 n1185 n2587 n2588 +11111111 1 +.names n18 n28 n31 n1038 n1671 n2547 n2589 +000111 1 +.names n34 n1254 n2591 +0- 1 +-1 1 +.names n40 n546 n2010 n2574 n2589 n2591 n2590 +011111 1 +.names n247 n21 n1263 n1266 n2592 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names n34 n1261 n2592 n2593 +0-1 1 +-11 1 +.names n139 n280 n1256 n1259 n2594 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names n10 n1258 n2594 n2595 +0-1 1 +-11 1 +.names n382 n250 n444 n729 n1559 n2595 n2593 n2590 n2596 +11111111 1 +.names n790 n831 n853 n685 n752 n792 n2597 +111111 1 +.names n907 n1781 n917 n914 n922 n2597 n2598 +111111 1 +.names n949 n946 n1785 n2599 +111 1 +.names n1944 n1146 n1209 n2027 n2033 n1089 n1126 n2599 n2600 +11111111 1 +.names n1457 n2126 n1535 n2601 +111 1 +.names n21 n1273 n1278 n1428 n2602 +01-- 1 +-11- 1 +0--1 1 +--11 1 +.names n2065 n1148 n678 n2373 n1454 n2285 n2603 +111111 1 +.names n300 n1262 n1658 n2591 n2604 +0--1 1 +-111 1 +.names n448 n373 n505 n2605 +111 1 +.names n1329 n1007 n2606 +11 1 +.names n193 n824 n2607 +11 1 +.names n953 n465 n921 n2608 +111 1 +.names n263 n530 n737 n2609 +111 1 +.names n1329 n504 n2610 +11 1 +.names n1431 n503 n2611 +11 1 +.names n565 n195 n2612 +11 1 +.names n959 n504 n2613 +11 1 +.names n971 n54 n2614 +1- 1 +-1 1 +.names n985 n54 n2615 +1- 1 +-1 1 +.names n510 n54 n2616 +1- 1 +-1 1 +.names n633 n54 n2617 +1- 1 +-1 1 +.names i_12_ n204 n1328 n1392 n2618 +0111 1 +.end diff --git a/fpga_flow/benchmarks/MCNC_big20/s298.blif b/fpga_flow/benchmarks/MCNC_big20/s298.blif new file mode 100644 index 000000000..8acf0c347 --- /dev/null +++ b/fpga_flow/benchmarks/MCNC_big20/s298.blif @@ -0,0 +1,308 @@ +.model s298.bench +.inputs G0 G1 G2 +.outputs G117 G132 G66 G118 G133 G67 +.wire_load_slope 0.00 +.latch G29 G10 0 +.latch G30 G11 0 +.latch G34 G12 0 +.latch G39 G13 0 +.latch G44 G14 0 +.latch G56 G15 0 +.latch G86 G16 0 +.latch G92 G17 0 +.latch G98 G18 0 +.latch G102 G19 0 +.latch G107 G20 0 +.latch G113 G21 0 +.latch G119 G22 0 +.latch G125 G23 0 +.names II210 G117 +0 1 +.names II235 G132 +0 1 +.names II155 G66 +0 1 +.names II213 G118 +0 1 +.names II238 G133 +0 1 +.names II158 G67 +0 1 +.names G10 G130 G29 +00 1 +.names G31 G32 G33 G130 G30 +0000 1 +.names G35 G36 G37 G130 G34 +0000 1 +.names G42 G43 G39 +00 1 +.names G48 G49 G53 G44 +000 1 +.names G57 G58 G130 G56 +000 1 +.names G88 G89 G90 G112 G86 +0000 1 +.names G94 G95 G97 G92 +000 1 +.names G100 G101 G98 +00 1 +.names G105 G106 G102 +00 1 +.names G110 G111 G107 +00 1 +.names G115 G116 G113 +00 1 +.names G122 G123 G130 G119 +000 1 +.names G128 G129 G130 G125 +000 1 +.names II229 G130 +0 1 +.names G130 G28 +0 1 +.names G10 G38 +0 1 +.names G13 G40 +0 1 +.names G12 G45 +0 1 +.names G11 G46 +0 1 +.names G14 G50 +0 1 +.names G23 G51 +0 1 +.names G11 G54 +0 1 +.names G13 G55 +0 1 +.names G12 G59 +0 1 +.names G22 G60 +0 1 +.names G15 G64 +0 1 +.names G16 II155 +0 1 +.names G17 II158 +0 1 +.names G10 G76 +0 1 +.names G11 G82 +0 1 +.names G16 G87 +0 1 +.names G12 G91 +0 1 +.names G17 G93 +0 1 +.names G14 G96 +0 1 +.names G18 G99 +0 1 +.names G13 G103 +0 1 +.names G62 G63 G112 +00 1 +.names G112 G108 +0 1 +.names G21 G114 +0 1 +.names G18 II210 +0 1 +.names G19 II213 +0 1 +.names II221 G124 +0 1 +.names G124 G120 +0 1 +.names G22 G121 +0 1 +.names G2 II221 +0 1 +.names II232 G131 +0 1 +.names G131 G126 +0 1 +.names G23 G127 +0 1 +.names G0 II229 +0 1 +.names G1 II232 +0 1 +.names G20 II235 +0 1 +.names G21 II238 +0 1 +.names G28 G50 G26 +11 1 +.names G51 G28 G27 +11 1 +.names G10 G45 G13 G31 +111 1 +.names G10 G11 G32 +11 1 +.names G38 G46 G33 +11 1 +.names G10 G11 G12 G35 +111 1 +.names G38 G45 G36 +11 1 +.names G46 G45 G37 +11 1 +.names G12 G11 G10 G41 +0-- 1 +-0- 1 +--0 1 +.names G40 G41 G42 +11 1 +.names G50 G40 G47 +00 1 +.names G45 G46 G10 G47 G48 +1111 1 +.names G13 G45 G46 G10 G52 +0--- 1 +-0-- 1 +--0- 1 +---0 1 +.names G50 G51 G52 G49 +111 1 +.names G14 G55 G61 +00 1 +.names G59 G11 G60 G61 G57 +1111 1 +.names G59 G54 G22 G61 G65 +0--- 1 +-0-- 1 +--0- 1 +---0 1 +.names G64 G65 G58 +11 1 +.names G59 G11 G60 G61 G62 +1111 1 +.names G64 G65 G63 +11 1 +.names G12 G14 G19 G74 +111 1 +.names G82 G91 G14 G75 +111 1 +.names G14 G87 G88 +11 1 +.names G103 G96 G89 +11 1 +.names G91 G103 G90 +11 1 +.names G93 G13 G94 +11 1 +.names G96 G13 G95 +11 1 +.names G99 G14 G12 G100 +111 1 +.names G74 G75 G104 +00 1 +.names G103 G108 G104 G105 +111 1 +.names G71 G72 G73 G14 G109 +0--- 1 +-0-- 1 +--0- 1 +---0 1 +.names G108 G109 G110 +11 1 +.names G10 G112 G111 +11 1 +.names G114 G14 G115 +11 1 +.names G120 G121 G122 +11 1 +.names G124 G22 G123 +11 1 +.names G126 G127 G128 +11 1 +.names G131 G23 G129 +11 1 +.names G38 G46 G45 G40 G24 +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names G38 G11 G12 G25 +1-- 1 +-1- 1 +--1 1 +.names G11 G12 G13 G96 G68 +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names G103 G18 G69 +1- 1 +-1 1 +.names G103 G14 G70 +1- 1 +-1 1 +.names G82 G12 G13 G71 +1-- 1 +-1- 1 +--1 1 +.names G91 G20 G72 +1- 1 +-1 1 +.names G103 G20 G73 +1- 1 +-1 1 +.names G112 G103 G96 G19 G77 +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names G108 G76 G78 +1- 1 +-1 1 +.names G103 G14 G79 +1- 1 +-1 1 +.names G11 G14 G80 +1- 1 +-1 1 +.names G12 G13 G81 +1- 1 +-1 1 +.names G11 G12 G13 G96 G83 +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names G82 G91 G14 G84 +1-- 1 +-1- 1 +--1 1 +.names G91 G96 G17 G85 +1-- 1 +-1- 1 +--1 1 +.names G24 G25 G28 G43 +0-- 1 +-0- 1 +--0 1 +.names G83 G84 G85 G108 G97 +0--- 1 +-0-- 1 +--0- 1 +---0 1 +.names G68 G69 G70 G108 G101 +0--- 1 +-0-- 1 +--0- 1 +---0 1 +.names G77 G78 G106 +0- 1 +-0 1 +.names G79 G80 G81 G108 G116 +0--- 1 +-0-- 1 +--0- 1 +---0 1 +.names G26 G27 G53 +00 1 +.end diff --git a/fpga_flow/benchmarks/MCNC_big20/s38417.blif b/fpga_flow/benchmarks/MCNC_big20/s38417.blif new file mode 100644 index 000000000..40f97eab7 --- /dev/null +++ b/fpga_flow/benchmarks/MCNC_big20/s38417.blif @@ -0,0 +1,15102 @@ +.model TOP +.inputs Pg3234 Pg3233 Pg3232 Pg3231 Pg3230 Pg3229 Pg3228 Pg3227 Pg3226 Pg3225 \ +Pg3224 Pg3223 Pg3222 Pg3221 Pg3220 Pg3219 Pg3218 Pg3217 Pg3216 Pg3215 Pg3214 \ +Pg3213 Pg3212 Pg2637 Pg1943 Pg1249 Pg563 Pg51 PCLK +.outputs Pg27380 Pg26149 Pg26135 Pg26104 Pg25489 Pg25442 Pg25435 Pg25420 \ +Pg24734 Pg16496 Pg16437 Pg16399 Pg16355 Pg16297 Pg8275 Pg8274 Pg8273 Pg8272 \ +Pg8271 Pg8270 Pg8269 Pg8268 Pg8267 Pg8266 Pg8265 Pg8264 Pg8263 Pg8262 Pg8261 \ +Pg8260 Pg8259 Pg8258 Pg8251 Pg8249 Pg8175 Pg8167 Pg8106 Pg8096 Pg8087 Pg8082 \ +Pg8030 Pg8023 Pg8021 Pg8012 Pg8007 Pg7961 Pg7956 Pg7909 Pg7519 Pg7487 Pg7425 \ +Pg7390 Pg7357 Pg7334 Pg7302 Pg7264 Pg7229 Pg7194 Pg7161 Pg7084 Pg7052 Pg7014 \ +Pg6979 Pg6944 Pg6911 Pg6895 Pg6837 Pg6782 Pg6750 Pg6712 Pg6677 Pg6642 Pg6573 \ +Pg6518 Pg6485 Pg6447 Pg6442 Pg6368 Pg6313 Pg6231 Pg6225 Pg5796 Pg5747 Pg5738 \ +Pg5695 Pg5686 Pg5657 Pg5648 Pg5637 Pg5629 Pg5612 Pg5595 Pg5555 Pg5549 Pg5511 \ +Pg5472 Pg5437 Pg5388 Pg4590 Pg4450 Pg4323 Pg4321 Pg4200 Pg4090 Pg4088 Pg3993 +.latch Pg51 Pg8021 re PCLK 2 +.latch Ng20571 Ng2817 re PCLK 2 +.latch Ng20588 Ng2933 re PCLK 2 +.latch Ng21951 Ng13457 re PCLK 2 +.latch Ng23315 Ng2883 re PCLK 2 +.latch Ng24423 Ng2888 re PCLK 2 +.latch Ng25175 Ng2896 re PCLK 2 +.latch Ng26019 Ng2892 re PCLK 2 +.latch Ng26747 Ng2903 re PCLK 2 +.latch Ng27237 Ng2900 re PCLK 2 +.latch Ng27715 Ng2908 re PCLK 2 +.latch Ng24424 Ng2912 re PCLK 2 +.latch Ng25174 Ng2917 re PCLK 2 +.latch Ng26020 Ng2924 re PCLK 2 +.latch Ng26746 Ng2920 re PCLK 2 +.latch Ng19061 Ng2984 re PCLK 2 +.latch Ng19060 Ng2985 re PCLK 2 +.latch Pg8021 Ng2929 re PCLK 2 +.latch Ng16494 Ng2879 re PCLK 2 +.latch Pg3212 Ng2934 re PCLK 2 +.latch Pg3228 Ng2935 re PCLK 2 +.latch Pg3227 Ng2938 re PCLK 2 +.latch Pg3226 Ng2941 re PCLK 2 +.latch Pg3225 Ng2944 re PCLK 2 +.latch Pg3224 Ng2947 re PCLK 2 +.latch Pg3223 Ng2953 re PCLK 2 +.latch Pg3222 Ng2956 re PCLK 2 +.latch Pg3221 Ng2959 re PCLK 2 +.latch Pg3232 Ng2962 re PCLK 2 +.latch Pg3220 Ng2963 re PCLK 2 +.latch Pg3219 Ng2966 re PCLK 2 +.latch Pg3218 Ng2969 re PCLK 2 +.latch Pg3217 Ng2972 re PCLK 2 +.latch Pg3216 Ng2975 re PCLK 2 +.latch Pg3215 Ng2978 re PCLK 2 +.latch Pg3214 Ng2981 re PCLK 2 +.latch Pg3213 Ng2874 re PCLK 2 +.latch Ng20572 Ng1506 re PCLK 2 +.latch Ng20573 Ng1501 re PCLK 2 +.latch Ng20574 Ng1496 re PCLK 2 +.latch Ng20575 Ng1491 re PCLK 2 +.latch Ng20576 Ng1486 re PCLK 2 +.latch Ng20577 Ng1481 re PCLK 2 +.latch Ng20578 Ng1476 re PCLK 2 +.latch Ng20579 Ng1471 re PCLK 2 +.latch Ng23313 Ng13439 re PCLK 2 +.latch Ng21960 Pg8251 re PCLK 2 +.latch Pg8251 Ng813 re PCLK 2 +.latch Ng21961 Pg4090 re PCLK 2 +.latch Pg4090 Ng809 re PCLK 2 +.latch Ng21962 Pg4323 re PCLK 2 +.latch Pg4323 Ng805 re PCLK 2 +.latch Ng21963 Pg4590 re PCLK 2 +.latch Pg4590 Ng801 re PCLK 2 +.latch Ng21947 Pg6225 re PCLK 2 +.latch Pg6225 Ng797 re PCLK 2 +.latch Ng21948 Pg6442 re PCLK 2 +.latch Pg6442 Ng793 re PCLK 2 +.latch Ng21949 Pg6895 re PCLK 2 +.latch Pg6895 Ng789 re PCLK 2 +.latch Ng21950 Pg7334 re PCLK 2 +.latch Pg7334 Ng785 re PCLK 2 +.latch Ng23312 Pg7519 re PCLK 2 +.latch Pg7519 Ng13423 re PCLK 2 +.latch Ng21952 Pg8249 re PCLK 2 +.latch Pg8249 Ng125 re PCLK 2 +.latch Ng21953 Pg4088 re PCLK 2 +.latch Pg4088 Ng121 re PCLK 2 +.latch Ng21954 Pg4321 re PCLK 2 +.latch Pg4321 Ng117 re PCLK 2 +.latch Ng21955 Pg8023 re PCLK 2 +.latch Pg8023 Ng113 re PCLK 2 +.latch Ng21956 Pg8175 re PCLK 2 +.latch Pg8175 Ng109 re PCLK 2 +.latch Ng21957 Pg3993 re PCLK 2 +.latch Pg3993 Ng105 re PCLK 2 +.latch Ng21958 Pg4200 re PCLK 2 +.latch Pg4200 Ng101 re PCLK 2 +.latch Ng21959 Pg4450 re PCLK 2 +.latch Pg4450 Ng97 re PCLK 2 +.latch Ng23316 Pg8096 re PCLK 2 +.latch Pg8096 Ng13407 re PCLK 2 +.latch Ng20587 Ng2200 re PCLK 2 +.latch Ng20585 Ng2195 re PCLK 2 +.latch Ng20586 Ng2190 re PCLK 2 +.latch Ng20584 Ng2185 re PCLK 2 +.latch Ng20583 Ng2180 re PCLK 2 +.latch Ng20582 Ng2175 re PCLK 2 +.latch Ng20581 Ng2170 re PCLK 2 +.latch Ng20580 Ng2165 re PCLK 2 +.latch Ng23314 Ng13455 re PCLK 2 +.latch Ng20630 Ng3210 re PCLK 2 +.latch Ng20631 Ng3211 re PCLK 2 +.latch Ng20632 Ng3084 re PCLK 2 +.latch Ng20609 Ng3085 re PCLK 2 +.latch Ng20610 Ng3086 re PCLK 2 +.latch Ng20611 Ng3087 re PCLK 2 +.latch Ng20612 Ng3091 re PCLK 2 +.latch Ng20613 Ng3092 re PCLK 2 +.latch Ng20614 Ng3093 re PCLK 2 +.latch Ng20615 Ng3094 re PCLK 2 +.latch Ng20616 Ng3095 re PCLK 2 +.latch Ng20617 Ng3096 re PCLK 2 +.latch Ng26751 Ng3097 re PCLK 2 +.latch Ng26752 Ng3098 re PCLK 2 +.latch Ng26753 Ng3099 re PCLK 2 +.latch Ng29163 Ng3100 re PCLK 2 +.latch Ng29164 Ng3101 re PCLK 2 +.latch Ng29165 Ng3102 re PCLK 2 +.latch Ng30120 Ng3103 re PCLK 2 +.latch Ng30121 Ng3104 re PCLK 2 +.latch Ng30122 Ng3105 re PCLK 2 +.latch Ng30941 Ng3106 re PCLK 2 +.latch Ng30942 Ng3107 re PCLK 2 +.latch Ng30943 Ng3108 re PCLK 2 +.latch Ng20618 Ng3155 re PCLK 2 +.latch Ng20619 Ng3158 re PCLK 2 +.latch Ng20620 Ng3161 re PCLK 2 +.latch Ng20621 Ng3164 re PCLK 2 +.latch Ng20622 Ng3167 re PCLK 2 +.latch Ng20623 Ng3170 re PCLK 2 +.latch Ng20624 Ng3173 re PCLK 2 +.latch Ng20625 Ng3176 re PCLK 2 +.latch Ng20626 Ng3179 re PCLK 2 +.latch Ng20627 Ng3182 re PCLK 2 +.latch Ng20628 Ng3185 re PCLK 2 +.latch Ng20629 Ng3088 re PCLK 2 +.latch Pg24734 Ng3191 re PCLK 2 +.latch Ng29166 Ng3128 re PCLK 2 +.latch [1521] Ng3126 re PCLK 2 +.latch Ng28696 Ng3125 re PCLK 2 +.latch Ng28313 Ng3123 re PCLK 2 +.latch Pg26104 Ng3120 re PCLK 2 +.latch Pg25435 Ng3110 re PCLK 2 +.latch Pg27380 Ng3139 re PCLK 2 +.latch Pg26149 Ng3135 re PCLK 2 +.latch Pg26135 Ng3147 re PCLK 2 +.latch Ng29656 Ng185 re PCLK 2 +.latch Ng24259 Ng130 re PCLK 2 +.latch Ng24260 Ng131 re PCLK 2 +.latch Ng24261 Ng129 re PCLK 2 +.latch Ng24262 Ng133 re PCLK 2 +.latch Ng24263 Ng134 re PCLK 2 +.latch Ng24264 Ng132 re PCLK 2 +.latch Ng24265 Ng142 re PCLK 2 +.latch Ng24266 Ng143 re PCLK 2 +.latch Ng24267 Ng141 re PCLK 2 +.latch Ng24268 Ng145 re PCLK 2 +.latch Ng24269 Ng146 re PCLK 2 +.latch Ng24270 Ng144 re PCLK 2 +.latch Ng24271 Ng148 re PCLK 2 +.latch Ng24272 Ng149 re PCLK 2 +.latch Ng24273 Ng147 re PCLK 2 +.latch Ng24274 Ng151 re PCLK 2 +.latch Ng24275 Ng152 re PCLK 2 +.latch Ng24276 Ng150 re PCLK 2 +.latch Ng24277 Ng154 re PCLK 2 +.latch Ng24278 Ng155 re PCLK 2 +.latch Ng24279 Ng153 re PCLK 2 +.latch Ng24280 Ng157 re PCLK 2 +.latch Ng24281 Ng158 re PCLK 2 +.latch Ng24282 Ng156 re PCLK 2 +.latch Ng24283 Ng160 re PCLK 2 +.latch Ng24284 Ng161 re PCLK 2 +.latch Ng24285 Ng159 re PCLK 2 +.latch Ng24286 Ng163 re PCLK 2 +.latch Ng24287 Ng164 re PCLK 2 +.latch Ng24288 Ng162 re PCLK 2 +.latch Ng26679 Ng169 re PCLK 2 +.latch Ng26680 Ng170 re PCLK 2 +.latch Ng26681 Ng168 re PCLK 2 +.latch Ng26682 Ng172 re PCLK 2 +.latch Ng26683 Ng173 re PCLK 2 +.latch Ng26684 Ng171 re PCLK 2 +.latch Ng26685 Ng175 re PCLK 2 +.latch Ng26686 Ng176 re PCLK 2 +.latch Ng26687 Ng174 re PCLK 2 +.latch Ng26688 Ng178 re PCLK 2 +.latch Ng26689 Ng179 re PCLK 2 +.latch Ng26690 Ng177 re PCLK 2 +.latch Ng30506 Ng186 re PCLK 2 +.latch Ng30507 Ng189 re PCLK 2 +.latch Ng30508 Ng192 re PCLK 2 +.latch Ng30842 Ng231 re PCLK 2 +.latch Ng30843 Ng234 re PCLK 2 +.latch Ng30844 Ng237 re PCLK 2 +.latch Ng30836 Ng195 re PCLK 2 +.latch Ng30837 Ng198 re PCLK 2 +.latch Ng30838 Ng201 re PCLK 2 +.latch Ng30845 Ng240 re PCLK 2 +.latch Ng30846 Ng243 re PCLK 2 +.latch Ng30847 Ng246 re PCLK 2 +.latch Ng30509 Ng204 re PCLK 2 +.latch Ng30510 Ng207 re PCLK 2 +.latch Ng30511 Ng210 re PCLK 2 +.latch Ng30515 Ng249 re PCLK 2 +.latch Ng30516 Ng252 re PCLK 2 +.latch Ng30517 Ng255 re PCLK 2 +.latch Ng30512 Ng213 re PCLK 2 +.latch Ng30513 Ng216 re PCLK 2 +.latch Ng30514 Ng219 re PCLK 2 +.latch Ng30518 Ng258 re PCLK 2 +.latch Ng30519 Ng261 re PCLK 2 +.latch Ng30520 Ng264 re PCLK 2 +.latch Ng30839 Ng222 re PCLK 2 +.latch Ng30840 Ng225 re PCLK 2 +.latch Ng30841 Ng228 re PCLK 2 +.latch Ng30848 Ng267 re PCLK 2 +.latch Ng30849 Ng270 re PCLK 2 +.latch Ng30850 Ng273 re PCLK 2 +.latch Ng25983 Ng92 re PCLK 2 +.latch Ng26678 Ng88 re PCLK 2 +.latch Ng27189 Ng83 re PCLK 2 +.latch Ng27683 Ng79 re PCLK 2 +.latch Ng28206 Ng74 re PCLK 2 +.latch Ng28673 Ng70 re PCLK 2 +.latch Ng29131 Ng65 re PCLK 2 +.latch Ng29413 Ng61 re PCLK 2 +.latch Ng29627 Ng56 re PCLK 2 +.latch Ng29794 Ng52 re PCLK 2 +.latch Ng28207 Ng11497 re PCLK 2 +.latch Ng28208 Ng11498 re PCLK 2 +.latch Ng28209 Ng11499 re PCLK 2 +.latch Ng28210 Ng11500 re PCLK 2 +.latch Ng28211 Ng11501 re PCLK 2 +.latch Ng28212 Ng11502 re PCLK 2 +.latch Ng28213 Ng11503 re PCLK 2 +.latch Ng28214 Ng11504 re PCLK 2 +.latch Ng28215 Ng11505 re PCLK 2 +.latch Ng28216 Ng11506 re PCLK 2 +.latch Ng28217 Ng11507 re PCLK 2 +.latch Ng28218 Ng11508 re PCLK 2 +.latch Ng29414 Ng408 re PCLK 2 +.latch Ng29415 Ng411 re PCLK 2 +.latch Ng29416 Ng414 re PCLK 2 +.latch Ng29631 Ng417 re PCLK 2 +.latch Ng29632 Ng420 re PCLK 2 +.latch Ng29633 Ng423 re PCLK 2 +.latch Ng29417 Ng427 re PCLK 2 +.latch Ng29418 Ng428 re PCLK 2 +.latch Ng29419 Ng426 re PCLK 2 +.latch Ng27684 Ng429 re PCLK 2 +.latch Ng27685 Ng432 re PCLK 2 +.latch Ng27686 Ng435 re PCLK 2 +.latch Ng27687 Ng438 re PCLK 2 +.latch Ng27688 Ng441 re PCLK 2 +.latch Ng27689 Ng444 re PCLK 2 +.latch Ng28674 Ng448 re PCLK 2 +.latch Ng28675 Ng449 re PCLK 2 +.latch Ng28676 Ng447 re PCLK 2 +.latch Ng29795 Ng312 re PCLK 2 +.latch Ng29796 Ng313 re PCLK 2 +.latch Ng29797 Ng314 re PCLK 2 +.latch Ng30851 Ng315 re PCLK 2 +.latch Ng30852 Ng316 re PCLK 2 +.latch Ng30853 Ng317 re PCLK 2 +.latch Ng30710 Ng318 re PCLK 2 +.latch Ng30711 Ng319 re PCLK 2 +.latch Ng30712 Ng320 re PCLK 2 +.latch Ng29628 Ng322 re PCLK 2 +.latch Ng29629 Ng323 re PCLK 2 +.latch Ng29630 Ng321 re PCLK 2 +.latch Ng27191 Ng403 re PCLK 2 +.latch Ng27192 Ng404 re PCLK 2 +.latch Ng27193 Ng402 re PCLK 2 +.latch Ng11509 Ng450 re PCLK 2 +.latch Ng450 Ng451 re PCLK 2 +.latch Ng11510 Ng452 re PCLK 2 +.latch Ng452 Ng453 re PCLK 2 +.latch Ng11511 Ng454 re PCLK 2 +.latch Ng454 Ng279 re PCLK 2 +.latch Ng11491 Ng280 re PCLK 2 +.latch Ng280 Ng281 re PCLK 2 +.latch Ng11492 Ng282 re PCLK 2 +.latch Ng282 Ng283 re PCLK 2 +.latch Ng11493 Ng284 re PCLK 2 +.latch Ng284 Ng285 re PCLK 2 +.latch Ng11494 Ng286 re PCLK 2 +.latch Ng286 Ng287 re PCLK 2 +.latch Ng11495 Ng288 re PCLK 2 +.latch Ng288 Ng289 re PCLK 2 +.latch Ng13407 Ng290 re PCLK 2 +.latch Ng290 Ng291 re PCLK 2 +.latch Ng19012 Ng299 re PCLK 2 +.latch Ng23148 Ng305 re PCLK 2 +.latch Ng27190 Ng298 re PCLK 2 +.latch Ng11497 Ng342 re PCLK 2 +.latch Ng342 Ng349 re PCLK 2 +.latch Ng11498 Ng350 re PCLK 2 +.latch Ng350 Ng351 re PCLK 2 +.latch Ng11499 Ng352 re PCLK 2 +.latch Ng352 Ng353 re PCLK 2 +.latch Ng11500 Ng357 re PCLK 2 +.latch Ng357 Ng364 re PCLK 2 +.latch Ng11501 Ng365 re PCLK 2 +.latch Ng365 Ng366 re PCLK 2 +.latch Ng11502 Ng367 re PCLK 2 +.latch Ng367 Ng368 re PCLK 2 +.latch Ng11503 Ng372 re PCLK 2 +.latch Ng372 Ng379 re PCLK 2 +.latch Ng11504 Ng380 re PCLK 2 +.latch Ng380 Ng381 re PCLK 2 +.latch Ng11505 Ng382 re PCLK 2 +.latch Ng382 Ng383 re PCLK 2 +.latch Ng11506 Ng387 re PCLK 2 +.latch Ng387 Ng394 re PCLK 2 +.latch Ng11507 Ng395 re PCLK 2 +.latch Ng395 Ng396 re PCLK 2 +.latch Ng11508 Ng397 re PCLK 2 +.latch Ng397 Ng324 re PCLK 2 +.latch Ng23160 Ng554 re PCLK 2 +.latch Ng20556 Ng557 re PCLK 2 +.latch Ng20557 Ng510 re PCLK 2 +.latch Ng16467 Ng513 re PCLK 2 +.latch Ng513 Ng523 re PCLK 2 +.latch Ng523 Ng524 re PCLK 2 +.latch Ng11512 Ng564 re PCLK 2 +.latch Ng564 Ng569 re PCLK 2 +.latch Ng11515 Ng570 re PCLK 2 +.latch Ng570 Ng571 re PCLK 2 +.latch Ng11516 Ng572 re PCLK 2 +.latch Ng572 Ng573 re PCLK 2 +.latch Ng11517 Ng574 re PCLK 2 +.latch Ng574 Ng565 re PCLK 2 +.latch Ng11513 Ng566 re PCLK 2 +.latch Ng566 Ng567 re PCLK 2 +.latch Ng11514 Ng568 re PCLK 2 +.latch Ng568 Ng489 re PCLK 2 +.latch Ng24292 Ng486 re PCLK 2 +.latch Ng24293 Ng487 re PCLK 2 +.latch Ng24294 Ng488 re PCLK 2 +.latch Ng25139 Ng11512 re PCLK 2 +.latch Ng25131 Ng11515 re PCLK 2 +.latch Ng25132 Ng11516 re PCLK 2 +.latch Ng25136 Ng477 re PCLK 2 +.latch Ng25137 Ng478 re PCLK 2 +.latch Ng25138 Ng479 re PCLK 2 +.latch Ng24289 Ng480 re PCLK 2 +.latch Ng24290 Ng484 re PCLK 2 +.latch Ng24291 Ng464 re PCLK 2 +.latch Ng25133 Ng11517 re PCLK 2 +.latch Ng25134 Ng11513 re PCLK 2 +.latch Ng25135 Ng11514 re PCLK 2 +.latch Ng16468 Ng528 re PCLK 2 +.latch Ng528 Ng535 re PCLK 2 +.latch Ng535 Ng542 re PCLK 2 +.latch Ng19021 Ng543 re PCLK 2 +.latch Ng543 Ng544 re PCLK 2 +.latch Ng23159 Ng548 re PCLK 2 +.latch Ng19022 Ng549 re PCLK 2 +.latch Ng549 Ng8284 re PCLK 2 +.latch Ng19023 Ng558 re PCLK 2 +.latch Ng558 Ng559 re PCLK 2 +.latch Ng28219 Ng576 re PCLK 2 +.latch Ng28220 Ng577 re PCLK 2 +.latch Ng28221 Ng575 re PCLK 2 +.latch Ng28222 Ng579 re PCLK 2 +.latch Ng28223 Ng580 re PCLK 2 +.latch Ng28224 Ng578 re PCLK 2 +.latch Ng28225 Ng582 re PCLK 2 +.latch Ng28226 Ng583 re PCLK 2 +.latch Ng28227 Ng581 re PCLK 2 +.latch Ng28228 Ng585 re PCLK 2 +.latch Ng28229 Ng586 re PCLK 2 +.latch Ng28230 Ng584 re PCLK 2 +.latch Ng25985 Ng587 re PCLK 2 +.latch Ng25986 Ng590 re PCLK 2 +.latch Ng25987 Ng593 re PCLK 2 +.latch Ng25988 Ng596 re PCLK 2 +.latch Ng25989 Ng599 re PCLK 2 +.latch Ng25990 Ng602 re PCLK 2 +.latch Ng29135 Ng614 re PCLK 2 +.latch Ng29136 Ng617 re PCLK 2 +.latch Ng29137 Ng620 re PCLK 2 +.latch Ng29132 Ng605 re PCLK 2 +.latch Ng29133 Ng608 re PCLK 2 +.latch Ng29134 Ng611 re PCLK 2 +.latch Ng27194 Ng490 re PCLK 2 +.latch Ng27195 Ng493 re PCLK 2 +.latch Ng27196 Ng496 re PCLK 2 +.latch Ng8284 Ng506 re PCLK 2 +.latch Ng24295 Ng507 re PCLK 2 +.latch Ng23154 Pg16297 re PCLK 2 +.latch Pg16297 Ng525 re PCLK 2 +.latch Ng13410 Ng529 re PCLK 2 +.latch Ng13411 Ng530 re PCLK 2 +.latch Ng13412 Ng531 re PCLK 2 +.latch Ng13413 Ng532 re PCLK 2 +.latch Ng13414 Ng533 re PCLK 2 +.latch Ng13415 Ng534 re PCLK 2 +.latch Ng13416 Ng536 re PCLK 2 +.latch Ng13417 Ng537 re PCLK 2 +.latch Ng25984 Ng538 re PCLK 2 +.latch Ng13418 Ng541 re PCLK 2 +.latch Ng20558 Ng630 re PCLK 2 +.latch Ng21943 Ng659 re PCLK 2 +.latch Ng23161 Ng640 re PCLK 2 +.latch Ng24296 Ng633 re PCLK 2 +.latch Ng25140 Ng653 re PCLK 2 +.latch Ng25991 Ng646 re PCLK 2 +.latch Ng26691 Ng660 re PCLK 2 +.latch Ng27197 Ng672 re PCLK 2 +.latch Ng27690 Ng666 re PCLK 2 +.latch Ng28231 Ng679 re PCLK 2 +.latch Ng28677 Ng686 re PCLK 2 +.latch Ng29138 Ng692 re PCLK 2 +.latch Ng23162 Ng699 re PCLK 2 +.latch Ng23163 Ng700 re PCLK 2 +.latch Ng23164 Ng698 re PCLK 2 +.latch Ng23165 Ng702 re PCLK 2 +.latch Ng23166 Ng703 re PCLK 2 +.latch Ng23167 Ng701 re PCLK 2 +.latch Ng23168 Ng705 re PCLK 2 +.latch Ng23169 Ng706 re PCLK 2 +.latch Ng23170 Ng704 re PCLK 2 +.latch Ng23171 Ng708 re PCLK 2 +.latch Ng23172 Ng709 re PCLK 2 +.latch Ng23173 Ng707 re PCLK 2 +.latch Ng23174 Ng711 re PCLK 2 +.latch Ng23175 Ng712 re PCLK 2 +.latch Ng23176 Ng710 re PCLK 2 +.latch Ng23177 Ng714 re PCLK 2 +.latch Ng23178 Ng715 re PCLK 2 +.latch Ng23179 Ng713 re PCLK 2 +.latch Ng23180 Ng717 re PCLK 2 +.latch Ng23181 Ng718 re PCLK 2 +.latch Ng23182 Ng716 re PCLK 2 +.latch Ng23183 Ng720 re PCLK 2 +.latch Ng23184 Ng721 re PCLK 2 +.latch Ng23185 Ng719 re PCLK 2 +.latch Ng23186 Ng723 re PCLK 2 +.latch Ng23187 Ng724 re PCLK 2 +.latch Ng23188 Ng722 re PCLK 2 +.latch Ng23189 Ng726 re PCLK 2 +.latch Ng23190 Ng727 re PCLK 2 +.latch Ng23191 Ng725 re PCLK 2 +.latch Ng23192 Ng729 re PCLK 2 +.latch Ng23193 Ng730 re PCLK 2 +.latch Ng23194 Ng728 re PCLK 2 +.latch Ng23195 Ng732 re PCLK 2 +.latch Ng23196 Ng733 re PCLK 2 +.latch Ng23197 Ng731 re PCLK 2 +.latch Ng26692 Ng735 re PCLK 2 +.latch Ng26693 Ng736 re PCLK 2 +.latch Ng26694 Ng734 re PCLK 2 +.latch Ng24297 Ng738 re PCLK 2 +.latch Ng24298 Ng739 re PCLK 2 +.latch Ng24299 Ng737 re PCLK 2 +.latch Ng13457 [1612] re PCLK 2 +.latch [1612] [1594] re PCLK 2 +.latch [1594] Ng853 re PCLK 2 +.latch Ng24300 Ng818 re PCLK 2 +.latch Ng24301 Ng819 re PCLK 2 +.latch Ng24302 Ng817 re PCLK 2 +.latch Ng24303 Ng821 re PCLK 2 +.latch Ng24304 Ng822 re PCLK 2 +.latch Ng24305 Ng820 re PCLK 2 +.latch Ng24306 Ng830 re PCLK 2 +.latch Ng24307 Ng831 re PCLK 2 +.latch Ng24308 Ng829 re PCLK 2 +.latch Ng24309 Ng833 re PCLK 2 +.latch Ng24310 Ng834 re PCLK 2 +.latch Ng24311 Ng832 re PCLK 2 +.latch Ng24312 Ng836 re PCLK 2 +.latch Ng24313 Ng837 re PCLK 2 +.latch Ng24314 Ng835 re PCLK 2 +.latch Ng24315 Ng839 re PCLK 2 +.latch Ng24316 Ng840 re PCLK 2 +.latch Ng24317 Ng838 re PCLK 2 +.latch Ng24318 Ng842 re PCLK 2 +.latch Ng24319 Ng843 re PCLK 2 +.latch Ng24320 Ng841 re PCLK 2 +.latch Ng24321 Ng845 re PCLK 2 +.latch Ng24322 Ng846 re PCLK 2 +.latch Ng24323 Ng844 re PCLK 2 +.latch Ng24324 Ng848 re PCLK 2 +.latch Ng24325 Ng849 re PCLK 2 +.latch Ng24326 Ng847 re PCLK 2 +.latch Ng24327 Ng851 re PCLK 2 +.latch Ng24328 Ng852 re PCLK 2 +.latch Ng24329 Ng850 re PCLK 2 +.latch Ng26696 Ng857 re PCLK 2 +.latch Ng26697 Ng858 re PCLK 2 +.latch Ng26698 Ng856 re PCLK 2 +.latch Ng26699 Ng860 re PCLK 2 +.latch Ng26700 Ng861 re PCLK 2 +.latch Ng26701 Ng859 re PCLK 2 +.latch Ng26702 Ng863 re PCLK 2 +.latch Ng26703 Ng864 re PCLK 2 +.latch Ng26704 Ng862 re PCLK 2 +.latch Ng26705 Ng866 re PCLK 2 +.latch Ng26706 Ng867 re PCLK 2 +.latch Ng26707 Ng865 re PCLK 2 +.latch Ng30521 Ng873 re PCLK 2 +.latch Ng30522 Ng876 re PCLK 2 +.latch Ng30523 Ng879 re PCLK 2 +.latch Ng30860 Ng918 re PCLK 2 +.latch Ng30861 Ng921 re PCLK 2 +.latch Ng30862 Ng924 re PCLK 2 +.latch Ng30854 Ng882 re PCLK 2 +.latch Ng30855 Ng885 re PCLK 2 +.latch Ng30856 Ng888 re PCLK 2 +.latch Ng30863 Ng927 re PCLK 2 +.latch Ng30864 Ng930 re PCLK 2 +.latch Ng30865 Ng933 re PCLK 2 +.latch Ng30524 Ng891 re PCLK 2 +.latch Ng30525 Ng894 re PCLK 2 +.latch Ng30526 Ng897 re PCLK 2 +.latch Ng30530 Ng936 re PCLK 2 +.latch Ng30531 Ng939 re PCLK 2 +.latch Ng30532 Ng942 re PCLK 2 +.latch Ng30527 Ng900 re PCLK 2 +.latch Ng30528 Ng903 re PCLK 2 +.latch Ng30529 Ng906 re PCLK 2 +.latch Ng30533 Ng945 re PCLK 2 +.latch Ng30534 Ng948 re PCLK 2 +.latch Ng30535 Ng951 re PCLK 2 +.latch Ng30857 Ng909 re PCLK 2 +.latch Ng30858 Ng912 re PCLK 2 +.latch Ng30859 Ng915 re PCLK 2 +.latch Ng30866 Ng954 re PCLK 2 +.latch Ng30867 Ng957 re PCLK 2 +.latch Ng30868 Ng960 re PCLK 2 +.latch Ng25992 Ng780 re PCLK 2 +.latch Ng26695 Ng776 re PCLK 2 +.latch Ng27198 Ng771 re PCLK 2 +.latch Ng27691 Ng767 re PCLK 2 +.latch Ng28232 Ng762 re PCLK 2 +.latch Ng28678 Ng758 re PCLK 2 +.latch Ng29139 Ng753 re PCLK 2 +.latch Ng29420 Ng749 re PCLK 2 +.latch Ng29634 Ng744 re PCLK 2 +.latch Ng29798 Ng740 re PCLK 2 +.latch Ng28233 Ng11524 re PCLK 2 +.latch Ng28234 Ng11525 re PCLK 2 +.latch Ng28235 Ng11526 re PCLK 2 +.latch Ng28236 Ng11527 re PCLK 2 +.latch Ng28237 Ng11528 re PCLK 2 +.latch Ng28238 Ng11529 re PCLK 2 +.latch Ng28239 Ng11530 re PCLK 2 +.latch Ng28240 Ng11531 re PCLK 2 +.latch Ng28241 Ng11532 re PCLK 2 +.latch Ng28242 Ng11533 re PCLK 2 +.latch Ng28243 Ng11534 re PCLK 2 +.latch Ng28244 Ng11535 re PCLK 2 +.latch Ng29421 Ng1095 re PCLK 2 +.latch Ng29422 Ng1098 re PCLK 2 +.latch Ng29423 Ng1101 re PCLK 2 +.latch Ng29638 Ng1104 re PCLK 2 +.latch Ng29639 Ng1107 re PCLK 2 +.latch Ng29640 Ng1110 re PCLK 2 +.latch Ng29424 Ng1114 re PCLK 2 +.latch Ng29425 Ng1115 re PCLK 2 +.latch Ng29426 Ng1113 re PCLK 2 +.latch Ng27692 Ng1116 re PCLK 2 +.latch Ng27693 Ng1119 re PCLK 2 +.latch Ng27694 Ng1122 re PCLK 2 +.latch Ng27695 Ng1125 re PCLK 2 +.latch Ng27696 Ng1128 re PCLK 2 +.latch Ng27697 Ng1131 re PCLK 2 +.latch Ng28679 Ng1135 re PCLK 2 +.latch Ng28680 Ng1136 re PCLK 2 +.latch Ng28681 Ng1134 re PCLK 2 +.latch Ng29799 Ng999 re PCLK 2 +.latch Ng29800 Ng1000 re PCLK 2 +.latch Ng29801 Ng1001 re PCLK 2 +.latch Ng30869 Ng1002 re PCLK 2 +.latch Ng30870 Ng1003 re PCLK 2 +.latch Ng30871 Ng1004 re PCLK 2 +.latch Ng30713 Ng1005 re PCLK 2 +.latch Ng30714 Ng1006 re PCLK 2 +.latch Ng30715 Ng1007 re PCLK 2 +.latch Ng29635 Ng1009 re PCLK 2 +.latch Ng29636 Ng1010 re PCLK 2 +.latch Ng29637 Ng1008 re PCLK 2 +.latch Ng27206 Ng1090 re PCLK 2 +.latch Ng27207 Ng1091 re PCLK 2 +.latch Ng27208 Ng1089 re PCLK 2 +.latch Ng11536 Ng1137 re PCLK 2 +.latch Ng1137 Ng1138 re PCLK 2 +.latch Ng11537 Ng1139 re PCLK 2 +.latch Ng1139 Ng1140 re PCLK 2 +.latch Ng11538 Ng1141 re PCLK 2 +.latch Ng1141 Ng966 re PCLK 2 +.latch Ng11518 Ng967 re PCLK 2 +.latch Ng967 Ng968 re PCLK 2 +.latch Ng11519 Ng969 re PCLK 2 +.latch Ng969 Ng970 re PCLK 2 +.latch Ng11520 Ng971 re PCLK 2 +.latch Ng971 Ng972 re PCLK 2 +.latch Ng11521 Ng973 re PCLK 2 +.latch Ng973 Ng974 re PCLK 2 +.latch Ng11522 Ng975 re PCLK 2 +.latch Ng975 Ng976 re PCLK 2 +.latch Ng13423 Ng977 re PCLK 2 +.latch Ng977 Ng978 re PCLK 2 +.latch Ng19024 Ng986 re PCLK 2 +.latch Ng27200 Ng992 re PCLK 2 +.latch Ng27199 Ng985 re PCLK 2 +.latch Ng11524 Ng1029 re PCLK 2 +.latch Ng1029 Ng1036 re PCLK 2 +.latch Ng11525 Ng1037 re PCLK 2 +.latch Ng1037 Ng1038 re PCLK 2 +.latch Ng11526 Ng1039 re PCLK 2 +.latch Ng1039 Ng1040 re PCLK 2 +.latch Ng11527 Ng1044 re PCLK 2 +.latch Ng1044 Ng1051 re PCLK 2 +.latch Ng11528 Ng1052 re PCLK 2 +.latch Ng1052 Ng1053 re PCLK 2 +.latch Ng11529 Ng1054 re PCLK 2 +.latch Ng1054 Ng1055 re PCLK 2 +.latch Ng11530 Ng1059 re PCLK 2 +.latch Ng1059 Ng1066 re PCLK 2 +.latch Ng11531 Ng1067 re PCLK 2 +.latch Ng1067 Ng1068 re PCLK 2 +.latch Ng11532 Ng1069 re PCLK 2 +.latch Ng1069 Ng1070 re PCLK 2 +.latch Ng11533 Ng1074 re PCLK 2 +.latch Ng1074 Ng1081 re PCLK 2 +.latch Ng11534 Ng1082 re PCLK 2 +.latch Ng1082 Ng1083 re PCLK 2 +.latch Ng11535 Ng1084 re PCLK 2 +.latch Ng1084 Ng1011 re PCLK 2 +.latch Ng23198 Ng1240 re PCLK 2 +.latch Ng20560 Ng1243 re PCLK 2 +.latch Ng20561 Ng1196 re PCLK 2 +.latch Ng16469 Ng1199 re PCLK 2 +.latch Ng1199 Ng1209 re PCLK 2 +.latch Ng1209 Ng1210 re PCLK 2 +.latch Ng11539 Ng1250 re PCLK 2 +.latch Ng1250 Ng1255 re PCLK 2 +.latch Ng11542 Ng1256 re PCLK 2 +.latch Ng1256 Ng1257 re PCLK 2 +.latch Ng11543 Ng1258 re PCLK 2 +.latch Ng1258 Ng1259 re PCLK 2 +.latch Ng11544 Ng1260 re PCLK 2 +.latch Ng1260 Ng1251 re PCLK 2 +.latch Ng11540 Ng1252 re PCLK 2 +.latch Ng1252 Ng1253 re PCLK 2 +.latch Ng11541 Ng1254 re PCLK 2 +.latch Ng1254 Ng1176 re PCLK 2 +.latch Ng24333 Ng1173 re PCLK 2 +.latch Ng24334 Ng1174 re PCLK 2 +.latch Ng24335 Ng1175 re PCLK 2 +.latch Ng25150 Ng11539 re PCLK 2 +.latch Ng25142 Ng11542 re PCLK 2 +.latch Ng25143 Ng11543 re PCLK 2 +.latch Ng25147 Ng1164 re PCLK 2 +.latch Ng25148 Ng1165 re PCLK 2 +.latch Ng25149 Ng1166 re PCLK 2 +.latch Ng24330 Ng1167 re PCLK 2 +.latch Ng24331 Ng1171 re PCLK 2 +.latch Ng24332 Ng1151 re PCLK 2 +.latch Ng25144 Ng11544 re PCLK 2 +.latch Ng25145 Ng11540 re PCLK 2 +.latch Ng25146 Ng11541 re PCLK 2 +.latch Ng16470 Ng1214 re PCLK 2 +.latch Ng1214 Ng1221 re PCLK 2 +.latch Ng1221 Ng1228 re PCLK 2 +.latch Ng19033 Ng1229 re PCLK 2 +.latch Ng1229 Ng1230 re PCLK 2 +.latch Ng27217 Ng1234 re PCLK 2 +.latch Ng19034 Ng1235 re PCLK 2 +.latch Ng1235 Ng8293 re PCLK 2 +.latch Ng19035 Ng1244 re PCLK 2 +.latch Ng1244 Ng1245 re PCLK 2 +.latch Ng28245 Ng1262 re PCLK 2 +.latch Ng28246 Ng1263 re PCLK 2 +.latch Ng28247 Ng1261 re PCLK 2 +.latch Ng28248 Ng1265 re PCLK 2 +.latch Ng28249 Ng1266 re PCLK 2 +.latch Ng28250 Ng1264 re PCLK 2 +.latch Ng28251 Ng1268 re PCLK 2 +.latch Ng28252 Ng1269 re PCLK 2 +.latch Ng28253 Ng1267 re PCLK 2 +.latch Ng28254 Ng1271 re PCLK 2 +.latch Ng28255 Ng1272 re PCLK 2 +.latch Ng28256 Ng1270 re PCLK 2 +.latch Ng25994 Ng1273 re PCLK 2 +.latch Ng25995 Ng1276 re PCLK 2 +.latch Ng25996 Ng1279 re PCLK 2 +.latch Ng25997 Ng1282 re PCLK 2 +.latch Ng25998 Ng1285 re PCLK 2 +.latch Ng25999 Ng1288 re PCLK 2 +.latch Ng29143 Ng1300 re PCLK 2 +.latch Ng29144 Ng1303 re PCLK 2 +.latch Ng29145 Ng1306 re PCLK 2 +.latch Ng29140 Ng1291 re PCLK 2 +.latch Ng29141 Ng1294 re PCLK 2 +.latch Ng29142 Ng1297 re PCLK 2 +.latch Ng27209 Ng1177 re PCLK 2 +.latch Ng27210 Ng1180 re PCLK 2 +.latch Ng27211 Ng1183 re PCLK 2 +.latch Ng8293 Ng1192 re PCLK 2 +.latch Ng24336 Ng1193 re PCLK 2 +.latch Ng27212 Pg16355 re PCLK 2 +.latch Pg16355 Ng1211 re PCLK 2 +.latch Ng13426 Ng1215 re PCLK 2 +.latch Ng13427 Ng1216 re PCLK 2 +.latch Ng13428 Ng1217 re PCLK 2 +.latch Ng13429 Ng1218 re PCLK 2 +.latch Ng13430 Ng1219 re PCLK 2 +.latch Ng13431 Ng1220 re PCLK 2 +.latch Ng13432 Ng1222 re PCLK 2 +.latch Ng13433 Ng1223 re PCLK 2 +.latch Ng25993 Ng1224 re PCLK 2 +.latch Ng13434 Ng1227 re PCLK 2 +.latch Ng13475 [1605] re PCLK 2 +.latch [1605] [1603] re PCLK 2 +.latch [1603] Ng1315 re PCLK 2 +.latch Ng20562 Ng1316 re PCLK 2 +.latch Ng21944 Ng1345 re PCLK 2 +.latch Ng23199 Ng1326 re PCLK 2 +.latch Ng24337 Ng1319 re PCLK 2 +.latch Ng25151 Ng1339 re PCLK 2 +.latch Ng26000 Ng1332 re PCLK 2 +.latch Ng26708 Ng1346 re PCLK 2 +.latch Ng27218 Ng1358 re PCLK 2 +.latch Ng27698 Ng1352 re PCLK 2 +.latch Ng28257 Ng1365 re PCLK 2 +.latch Ng28682 Ng1372 re PCLK 2 +.latch Ng29146 Ng1378 re PCLK 2 +.latch Ng23200 Ng1385 re PCLK 2 +.latch Ng23201 Ng1386 re PCLK 2 +.latch Ng23202 Ng1384 re PCLK 2 +.latch Ng23203 Ng1388 re PCLK 2 +.latch Ng23204 Ng1389 re PCLK 2 +.latch Ng23205 Ng1387 re PCLK 2 +.latch Ng23206 Ng1391 re PCLK 2 +.latch Ng23207 Ng1392 re PCLK 2 +.latch Ng23208 Ng1390 re PCLK 2 +.latch Ng23209 Ng1394 re PCLK 2 +.latch Ng23210 Ng1395 re PCLK 2 +.latch Ng23211 Ng1393 re PCLK 2 +.latch Ng23212 Ng1397 re PCLK 2 +.latch Ng23213 Ng1398 re PCLK 2 +.latch Ng23214 Ng1396 re PCLK 2 +.latch Ng23215 Ng1400 re PCLK 2 +.latch Ng23216 Ng1401 re PCLK 2 +.latch Ng23217 Ng1399 re PCLK 2 +.latch Ng23218 Ng1403 re PCLK 2 +.latch Ng23219 Ng1404 re PCLK 2 +.latch Ng23220 Ng1402 re PCLK 2 +.latch Ng23221 Ng1406 re PCLK 2 +.latch Ng23222 Ng1407 re PCLK 2 +.latch Ng23223 Ng1405 re PCLK 2 +.latch Ng23224 Ng1409 re PCLK 2 +.latch Ng23225 Ng1410 re PCLK 2 +.latch Ng23226 Ng1408 re PCLK 2 +.latch Ng23227 Ng1412 re PCLK 2 +.latch Ng23228 Ng1413 re PCLK 2 +.latch Ng23229 Ng1411 re PCLK 2 +.latch Ng23230 Ng1415 re PCLK 2 +.latch Ng23231 Ng1416 re PCLK 2 +.latch Ng23232 Ng1414 re PCLK 2 +.latch Ng23233 Ng1418 re PCLK 2 +.latch Ng23234 Ng1419 re PCLK 2 +.latch Ng23235 Ng1417 re PCLK 2 +.latch Ng26709 Ng1421 re PCLK 2 +.latch Ng26710 Ng1422 re PCLK 2 +.latch Ng26711 Ng1420 re PCLK 2 +.latch Ng24338 Ng1424 re PCLK 2 +.latch Ng24339 Ng1425 re PCLK 2 +.latch Ng24340 Ng1423 re PCLK 2 +.latch Ng24341 Ng1512 re PCLK 2 +.latch Ng24342 Ng1513 re PCLK 2 +.latch Ng24343 Ng1511 re PCLK 2 +.latch Ng24344 Ng1515 re PCLK 2 +.latch Ng24345 Ng1516 re PCLK 2 +.latch Ng24346 Ng1514 re PCLK 2 +.latch Ng24347 Ng1524 re PCLK 2 +.latch Ng24348 Ng1525 re PCLK 2 +.latch Ng24349 Ng1523 re PCLK 2 +.latch Ng24350 Ng1527 re PCLK 2 +.latch Ng24351 Ng1528 re PCLK 2 +.latch Ng24352 Ng1526 re PCLK 2 +.latch Ng24353 Ng1530 re PCLK 2 +.latch Ng24354 Ng1531 re PCLK 2 +.latch Ng24355 Ng1529 re PCLK 2 +.latch Ng24356 Ng1533 re PCLK 2 +.latch Ng24357 Ng1534 re PCLK 2 +.latch Ng24358 Ng1532 re PCLK 2 +.latch Ng24359 Ng1536 re PCLK 2 +.latch Ng24360 Ng1537 re PCLK 2 +.latch Ng24361 Ng1535 re PCLK 2 +.latch Ng24362 Ng1539 re PCLK 2 +.latch Ng24363 Ng1540 re PCLK 2 +.latch Ng24364 Ng1538 re PCLK 2 +.latch Ng24365 Ng1542 re PCLK 2 +.latch Ng24366 Ng1543 re PCLK 2 +.latch Ng24367 Ng1541 re PCLK 2 +.latch Ng24368 Ng1545 re PCLK 2 +.latch Ng24369 Ng1546 re PCLK 2 +.latch Ng24370 Ng1544 re PCLK 2 +.latch Ng26713 Ng1551 re PCLK 2 +.latch Ng26714 Ng1552 re PCLK 2 +.latch Ng26715 Ng1550 re PCLK 2 +.latch Ng26716 Ng1554 re PCLK 2 +.latch Ng26717 Ng1555 re PCLK 2 +.latch Ng26718 Ng1553 re PCLK 2 +.latch Ng26719 Ng1557 re PCLK 2 +.latch Ng26720 Ng1558 re PCLK 2 +.latch Ng26721 Ng1556 re PCLK 2 +.latch Ng26722 Ng1560 re PCLK 2 +.latch Ng26723 Ng1561 re PCLK 2 +.latch Ng26724 Ng1559 re PCLK 2 +.latch Ng30536 Ng1567 re PCLK 2 +.latch Ng30537 Ng1570 re PCLK 2 +.latch Ng30538 Ng1573 re PCLK 2 +.latch Ng30878 Ng1612 re PCLK 2 +.latch Ng30879 Ng1615 re PCLK 2 +.latch Ng30880 Ng1618 re PCLK 2 +.latch Ng30872 Ng1576 re PCLK 2 +.latch Ng30873 Ng1579 re PCLK 2 +.latch Ng30874 Ng1582 re PCLK 2 +.latch Ng30881 Ng1621 re PCLK 2 +.latch Ng30882 Ng1624 re PCLK 2 +.latch Ng30883 Ng1627 re PCLK 2 +.latch Ng30539 Ng1585 re PCLK 2 +.latch Ng30540 Ng1588 re PCLK 2 +.latch Ng30541 Ng1591 re PCLK 2 +.latch Ng30545 Ng1630 re PCLK 2 +.latch Ng30546 Ng1633 re PCLK 2 +.latch Ng30547 Ng1636 re PCLK 2 +.latch Ng30542 Ng1594 re PCLK 2 +.latch Ng30543 Ng1597 re PCLK 2 +.latch Ng30544 Ng1600 re PCLK 2 +.latch Ng30548 Ng1639 re PCLK 2 +.latch Ng30549 Ng1642 re PCLK 2 +.latch Ng30550 Ng1645 re PCLK 2 +.latch Ng30875 Ng1603 re PCLK 2 +.latch Ng30876 Ng1606 re PCLK 2 +.latch Ng30877 Ng1609 re PCLK 2 +.latch Ng30884 Ng1648 re PCLK 2 +.latch Ng30885 Ng1651 re PCLK 2 +.latch Ng30886 Ng1654 re PCLK 2 +.latch Ng26001 Ng1466 re PCLK 2 +.latch Ng26712 Ng1462 re PCLK 2 +.latch Ng27219 Ng1457 re PCLK 2 +.latch Ng27699 Ng1453 re PCLK 2 +.latch Ng28258 Ng1448 re PCLK 2 +.latch Ng28683 Ng1444 re PCLK 2 +.latch Ng29147 Ng1439 re PCLK 2 +.latch Ng29427 Ng1435 re PCLK 2 +.latch Ng29641 Ng1430 re PCLK 2 +.latch Ng29802 Ng1426 re PCLK 2 +.latch Ng28259 Ng11551 re PCLK 2 +.latch Ng28260 Ng11552 re PCLK 2 +.latch Ng28261 Ng11553 re PCLK 2 +.latch Ng28262 Ng11554 re PCLK 2 +.latch Ng28263 Ng11555 re PCLK 2 +.latch Ng28264 Ng11556 re PCLK 2 +.latch Ng28265 Ng11557 re PCLK 2 +.latch Ng28266 Ng11558 re PCLK 2 +.latch Ng28267 Ng11559 re PCLK 2 +.latch Ng28268 Ng11560 re PCLK 2 +.latch Ng28269 Ng11561 re PCLK 2 +.latch Ng28270 Ng11562 re PCLK 2 +.latch Ng29434 Ng1789 re PCLK 2 +.latch Ng29435 Ng1792 re PCLK 2 +.latch Ng29436 Ng1795 re PCLK 2 +.latch Ng29645 Ng1798 re PCLK 2 +.latch Ng29646 Ng1801 re PCLK 2 +.latch Ng29647 Ng1804 re PCLK 2 +.latch Ng29437 Ng1808 re PCLK 2 +.latch Ng29438 Ng1809 re PCLK 2 +.latch Ng29439 Ng1807 re PCLK 2 +.latch Ng27700 Ng1810 re PCLK 2 +.latch Ng27701 Ng1813 re PCLK 2 +.latch Ng27702 Ng1816 re PCLK 2 +.latch Ng27703 Ng1819 re PCLK 2 +.latch Ng27704 Ng1822 re PCLK 2 +.latch Ng27705 Ng1825 re PCLK 2 +.latch Ng28684 Ng1829 re PCLK 2 +.latch Ng28685 Ng1830 re PCLK 2 +.latch Ng28686 Ng1828 re PCLK 2 +.latch Ng29803 Ng1693 re PCLK 2 +.latch Ng29804 Ng1694 re PCLK 2 +.latch Ng29805 Ng1695 re PCLK 2 +.latch Ng30887 Ng1696 re PCLK 2 +.latch Ng30888 Ng1697 re PCLK 2 +.latch Ng30889 Ng1698 re PCLK 2 +.latch Ng30716 Ng1699 re PCLK 2 +.latch Ng30717 Ng1700 re PCLK 2 +.latch Ng30718 Ng1701 re PCLK 2 +.latch Ng29642 Ng1703 re PCLK 2 +.latch Ng29643 Ng1704 re PCLK 2 +.latch Ng29644 Ng1702 re PCLK 2 +.latch Ng27221 Ng1784 re PCLK 2 +.latch Ng27222 Ng1785 re PCLK 2 +.latch Ng27223 Ng1783 re PCLK 2 +.latch Ng11563 Ng1831 re PCLK 2 +.latch Ng1831 Ng1832 re PCLK 2 +.latch Ng11564 Ng1833 re PCLK 2 +.latch Ng1833 Ng1834 re PCLK 2 +.latch Ng11565 Ng1835 re PCLK 2 +.latch Ng1835 Ng1660 re PCLK 2 +.latch Ng11545 Ng1661 re PCLK 2 +.latch Ng1661 Ng1662 re PCLK 2 +.latch Ng11546 Ng1663 re PCLK 2 +.latch Ng1663 Ng1664 re PCLK 2 +.latch Ng11547 Ng1665 re PCLK 2 +.latch Ng1665 Ng1666 re PCLK 2 +.latch Ng11548 Ng1667 re PCLK 2 +.latch Ng1667 Ng1668 re PCLK 2 +.latch Ng11549 Ng1669 re PCLK 2 +.latch Ng1669 Ng1670 re PCLK 2 +.latch Ng13439 Ng1671 re PCLK 2 +.latch Ng1671 Ng1672 re PCLK 2 +.latch Ng19036 Ng1680 re PCLK 2 +.latch Ng29428 Ng1686 re PCLK 2 +.latch Ng27220 Ng1679 re PCLK 2 +.latch Ng11551 Ng1723 re PCLK 2 +.latch Ng1723 Ng1730 re PCLK 2 +.latch Ng11552 Ng1731 re PCLK 2 +.latch Ng1731 Ng1732 re PCLK 2 +.latch Ng11553 Ng1733 re PCLK 2 +.latch Ng1733 Ng1734 re PCLK 2 +.latch Ng11554 Ng1738 re PCLK 2 +.latch Ng1738 Ng1745 re PCLK 2 +.latch Ng11555 Ng1746 re PCLK 2 +.latch Ng1746 Ng1747 re PCLK 2 +.latch Ng11556 Ng1748 re PCLK 2 +.latch Ng1748 Ng1749 re PCLK 2 +.latch Ng11557 Ng1753 re PCLK 2 +.latch Ng1753 Ng1760 re PCLK 2 +.latch Ng11558 Ng1761 re PCLK 2 +.latch Ng1761 Ng1762 re PCLK 2 +.latch Ng11559 Ng1763 re PCLK 2 +.latch Ng1763 Ng1764 re PCLK 2 +.latch Ng11560 Ng1768 re PCLK 2 +.latch Ng1768 Ng1775 re PCLK 2 +.latch Ng11561 Ng1776 re PCLK 2 +.latch Ng1776 Ng1777 re PCLK 2 +.latch Ng11562 Ng1778 re PCLK 2 +.latch Ng1778 Ng1705 re PCLK 2 +.latch Ng23236 Ng1934 re PCLK 2 +.latch Ng20564 Ng1937 re PCLK 2 +.latch Ng20565 Ng1890 re PCLK 2 +.latch Ng16471 Ng1893 re PCLK 2 +.latch Ng1893 Ng1903 re PCLK 2 +.latch Ng1903 Ng1904 re PCLK 2 +.latch Ng11566 Ng1944 re PCLK 2 +.latch Ng1944 Ng1949 re PCLK 2 +.latch Ng11569 Ng1950 re PCLK 2 +.latch Ng1950 Ng1951 re PCLK 2 +.latch Ng11570 Ng1952 re PCLK 2 +.latch Ng1952 Ng1953 re PCLK 2 +.latch Ng11571 Ng1954 re PCLK 2 +.latch Ng1954 Ng1945 re PCLK 2 +.latch Ng11567 Ng1946 re PCLK 2 +.latch Ng1946 Ng1947 re PCLK 2 +.latch Ng11568 Ng1948 re PCLK 2 +.latch Ng1948 Ng1870 re PCLK 2 +.latch Ng24374 Ng1867 re PCLK 2 +.latch Ng24375 Ng1868 re PCLK 2 +.latch Ng24376 Ng1869 re PCLK 2 +.latch Ng25161 Ng11566 re PCLK 2 +.latch Ng25153 Ng11569 re PCLK 2 +.latch Ng25154 Ng11570 re PCLK 2 +.latch Ng25158 Ng1858 re PCLK 2 +.latch Ng25159 Ng1859 re PCLK 2 +.latch Ng25160 Ng1860 re PCLK 2 +.latch Ng24371 Ng1861 re PCLK 2 +.latch Ng24372 Ng1865 re PCLK 2 +.latch Ng24373 Ng1845 re PCLK 2 +.latch Ng25155 Ng11571 re PCLK 2 +.latch Ng25156 Ng11567 re PCLK 2 +.latch Ng25157 Ng11568 re PCLK 2 +.latch Ng16472 Ng1908 re PCLK 2 +.latch Ng1908 Ng1915 re PCLK 2 +.latch Ng1915 Ng1922 re PCLK 2 +.latch Ng19045 Ng1923 re PCLK 2 +.latch Ng1923 Ng1924 re PCLK 2 +.latch Ng29445 Ng1928 re PCLK 2 +.latch Ng19046 Ng1929 re PCLK 2 +.latch Ng1929 Ng8302 re PCLK 2 +.latch Ng19047 Ng1938 re PCLK 2 +.latch Ng1938 Ng1939 re PCLK 2 +.latch Ng28271 Ng1956 re PCLK 2 +.latch Ng28272 Ng1957 re PCLK 2 +.latch Ng28273 Ng1955 re PCLK 2 +.latch Ng28274 Ng1959 re PCLK 2 +.latch Ng28275 Ng1960 re PCLK 2 +.latch Ng28276 Ng1958 re PCLK 2 +.latch Ng28277 Ng1962 re PCLK 2 +.latch Ng28278 Ng1963 re PCLK 2 +.latch Ng28279 Ng1961 re PCLK 2 +.latch Ng28280 Ng1965 re PCLK 2 +.latch Ng28281 Ng1966 re PCLK 2 +.latch Ng28282 Ng1964 re PCLK 2 +.latch Ng26003 Ng1967 re PCLK 2 +.latch Ng26004 Ng1970 re PCLK 2 +.latch Ng26005 Ng1973 re PCLK 2 +.latch Ng26006 Ng1976 re PCLK 2 +.latch Ng26007 Ng1979 re PCLK 2 +.latch Ng26008 Ng1982 re PCLK 2 +.latch Ng29151 Ng1994 re PCLK 2 +.latch Ng29152 Ng1997 re PCLK 2 +.latch Ng29153 Ng2000 re PCLK 2 +.latch Ng29148 Ng1985 re PCLK 2 +.latch Ng29149 Ng1988 re PCLK 2 +.latch Ng29150 Ng1991 re PCLK 2 +.latch Ng27224 Ng1871 re PCLK 2 +.latch Ng27225 Ng1874 re PCLK 2 +.latch Ng27226 Ng1877 re PCLK 2 +.latch Ng8302 Ng1886 re PCLK 2 +.latch Ng24377 Ng1887 re PCLK 2 +.latch Ng29440 Pg16399 re PCLK 2 +.latch Pg16399 Ng1905 re PCLK 2 +.latch Ng13442 Ng1909 re PCLK 2 +.latch Ng13443 Ng1910 re PCLK 2 +.latch Ng13444 Ng1911 re PCLK 2 +.latch Ng13445 Ng1912 re PCLK 2 +.latch Ng13446 Ng1913 re PCLK 2 +.latch Ng13447 Ng1914 re PCLK 2 +.latch Ng13448 Ng1916 re PCLK 2 +.latch Ng13449 Ng1917 re PCLK 2 +.latch Ng26002 Ng1918 re PCLK 2 +.latch Ng13450 Ng1921 re PCLK 2 +.latch Ng20566 Ng2010 re PCLK 2 +.latch Ng21945 Ng2039 re PCLK 2 +.latch Ng23237 Ng2020 re PCLK 2 +.latch Ng24378 Ng2013 re PCLK 2 +.latch Ng25162 Ng2033 re PCLK 2 +.latch Ng26009 Ng2026 re PCLK 2 +.latch Ng26725 Ng2040 re PCLK 2 +.latch Ng27227 Ng2052 re PCLK 2 +.latch Ng27706 Ng2046 re PCLK 2 +.latch Ng28283 Ng2059 re PCLK 2 +.latch Ng28687 Ng2066 re PCLK 2 +.latch Ng29154 Ng2072 re PCLK 2 +.latch Ng23238 Ng2079 re PCLK 2 +.latch Ng23239 Ng2080 re PCLK 2 +.latch Ng23240 Ng2078 re PCLK 2 +.latch Ng23241 Ng2082 re PCLK 2 +.latch Ng23242 Ng2083 re PCLK 2 +.latch Ng23243 Ng2081 re PCLK 2 +.latch Ng23244 Ng2085 re PCLK 2 +.latch Ng23245 Ng2086 re PCLK 2 +.latch Ng23246 Ng2084 re PCLK 2 +.latch Ng23247 Ng2088 re PCLK 2 +.latch Ng23248 Ng2089 re PCLK 2 +.latch Ng23249 Ng2087 re PCLK 2 +.latch Ng23250 Ng2091 re PCLK 2 +.latch Ng23251 Ng2092 re PCLK 2 +.latch Ng23252 Ng2090 re PCLK 2 +.latch Ng23253 Ng2094 re PCLK 2 +.latch Ng23254 Ng2095 re PCLK 2 +.latch Ng23255 Ng2093 re PCLK 2 +.latch Ng23256 Ng2097 re PCLK 2 +.latch Ng23257 Ng2098 re PCLK 2 +.latch Ng23258 Ng2096 re PCLK 2 +.latch Ng23259 Ng2100 re PCLK 2 +.latch Ng23260 Ng2101 re PCLK 2 +.latch Ng23261 Ng2099 re PCLK 2 +.latch Ng23262 Ng2103 re PCLK 2 +.latch Ng23263 Ng2104 re PCLK 2 +.latch Ng23264 Ng2102 re PCLK 2 +.latch Ng23265 Ng2106 re PCLK 2 +.latch Ng23266 Ng2107 re PCLK 2 +.latch Ng23267 Ng2105 re PCLK 2 +.latch Ng23268 Ng2109 re PCLK 2 +.latch Ng23269 Ng2110 re PCLK 2 +.latch Ng23270 Ng2108 re PCLK 2 +.latch Ng23271 Ng2112 re PCLK 2 +.latch Ng23272 Ng2113 re PCLK 2 +.latch Ng23273 Ng2111 re PCLK 2 +.latch Ng26726 Ng2115 re PCLK 2 +.latch Ng26727 Ng2116 re PCLK 2 +.latch Ng26728 Ng2114 re PCLK 2 +.latch Ng24379 Ng2118 re PCLK 2 +.latch Ng24380 Ng2119 re PCLK 2 +.latch Ng24381 Ng2117 re PCLK 2 +.latch Ng24382 Ng2206 re PCLK 2 +.latch Ng24383 Ng2207 re PCLK 2 +.latch Ng24384 Ng2205 re PCLK 2 +.latch Ng24385 Ng2209 re PCLK 2 +.latch Ng24386 Ng2210 re PCLK 2 +.latch Ng24387 Ng2208 re PCLK 2 +.latch Ng24388 Ng2218 re PCLK 2 +.latch Ng24389 Ng2219 re PCLK 2 +.latch Ng24390 Ng2217 re PCLK 2 +.latch Ng24391 Ng2221 re PCLK 2 +.latch Ng24392 Ng2222 re PCLK 2 +.latch Ng24393 Ng2220 re PCLK 2 +.latch Ng24394 Ng2224 re PCLK 2 +.latch Ng24395 Ng2225 re PCLK 2 +.latch Ng24396 Ng2223 re PCLK 2 +.latch Ng24397 Ng2227 re PCLK 2 +.latch Ng24398 Ng2228 re PCLK 2 +.latch Ng24399 Ng2226 re PCLK 2 +.latch Ng24400 Ng2230 re PCLK 2 +.latch Ng24401 Ng2231 re PCLK 2 +.latch Ng24402 Ng2229 re PCLK 2 +.latch Ng24403 Ng2233 re PCLK 2 +.latch Ng24404 Ng2234 re PCLK 2 +.latch Ng24405 Ng2232 re PCLK 2 +.latch Ng24406 Ng2236 re PCLK 2 +.latch Ng24407 Ng2237 re PCLK 2 +.latch Ng24408 Ng2235 re PCLK 2 +.latch Ng24409 Ng2239 re PCLK 2 +.latch Ng24410 Ng2240 re PCLK 2 +.latch Ng24411 Ng2238 re PCLK 2 +.latch Ng26730 Ng2245 re PCLK 2 +.latch Ng26731 Ng2246 re PCLK 2 +.latch Ng26732 Ng2244 re PCLK 2 +.latch Ng26733 Ng2248 re PCLK 2 +.latch Ng26734 Ng2249 re PCLK 2 +.latch Ng26735 Ng2247 re PCLK 2 +.latch Ng26736 Ng2251 re PCLK 2 +.latch Ng26737 Ng2252 re PCLK 2 +.latch Ng26738 Ng2250 re PCLK 2 +.latch Ng26739 Ng2254 re PCLK 2 +.latch Ng26740 Ng2255 re PCLK 2 +.latch Ng26741 Ng2253 re PCLK 2 +.latch Ng30551 Ng2261 re PCLK 2 +.latch Ng30552 Ng2264 re PCLK 2 +.latch Ng30553 Ng2267 re PCLK 2 +.latch Ng30896 Ng2306 re PCLK 2 +.latch Ng30897 Ng2309 re PCLK 2 +.latch Ng30898 Ng2312 re PCLK 2 +.latch Ng30890 Ng2270 re PCLK 2 +.latch Ng30891 Ng2273 re PCLK 2 +.latch Ng30892 Ng2276 re PCLK 2 +.latch Ng30899 Ng2315 re PCLK 2 +.latch Ng30900 Ng2318 re PCLK 2 +.latch Ng30901 Ng2321 re PCLK 2 +.latch Ng30554 Ng2279 re PCLK 2 +.latch Ng30555 Ng2282 re PCLK 2 +.latch Ng30556 Ng2285 re PCLK 2 +.latch Ng30560 Ng2324 re PCLK 2 +.latch Ng30561 Ng2327 re PCLK 2 +.latch Ng30562 Ng2330 re PCLK 2 +.latch Ng30557 Ng2288 re PCLK 2 +.latch Ng30558 Ng2291 re PCLK 2 +.latch Ng30559 Ng2294 re PCLK 2 +.latch Ng30563 Ng2333 re PCLK 2 +.latch Ng30564 Ng2336 re PCLK 2 +.latch Ng30565 Ng2339 re PCLK 2 +.latch Ng30893 Ng2297 re PCLK 2 +.latch Ng30894 Ng2300 re PCLK 2 +.latch Ng30895 Ng2303 re PCLK 2 +.latch Ng30902 Ng2342 re PCLK 2 +.latch Ng30903 Ng2345 re PCLK 2 +.latch Ng30904 Ng2348 re PCLK 2 +.latch Ng26010 Ng2160 re PCLK 2 +.latch Ng26729 Ng2156 re PCLK 2 +.latch Ng27228 Ng2151 re PCLK 2 +.latch Ng27707 Ng2147 re PCLK 2 +.latch Ng28284 Ng2142 re PCLK 2 +.latch Ng28688 Ng2138 re PCLK 2 +.latch Ng29155 Ng2133 re PCLK 2 +.latch Ng29446 Ng2129 re PCLK 2 +.latch Ng29648 Ng2124 re PCLK 2 +.latch Ng29806 Ng2120 re PCLK 2 +.latch Ng20567 Ng2256 re PCLK 2 +.latch Ng2256 [1609] re PCLK 2 +.latch [1609] Ng2257 re PCLK 2 +.latch Ng28285 Ng11578 re PCLK 2 +.latch Ng28286 Ng11579 re PCLK 2 +.latch Ng28287 Ng11580 re PCLK 2 +.latch Ng28288 Ng11581 re PCLK 2 +.latch Ng28289 Ng11582 re PCLK 2 +.latch Ng28290 Ng11583 re PCLK 2 +.latch Ng28291 Ng11584 re PCLK 2 +.latch Ng28292 Ng11585 re PCLK 2 +.latch Ng28293 Ng11586 re PCLK 2 +.latch Ng28294 Ng11587 re PCLK 2 +.latch Ng28295 Ng11588 re PCLK 2 +.latch Ng28296 Ng11589 re PCLK 2 +.latch Ng29447 Ng2483 re PCLK 2 +.latch Ng29448 Ng2486 re PCLK 2 +.latch Ng29449 Ng2489 re PCLK 2 +.latch Ng29652 Ng2492 re PCLK 2 +.latch Ng29653 Ng2495 re PCLK 2 +.latch Ng29654 Ng2498 re PCLK 2 +.latch Ng29450 Ng2502 re PCLK 2 +.latch Ng29451 Ng2503 re PCLK 2 +.latch Ng29452 Ng2501 re PCLK 2 +.latch Ng27708 Ng2504 re PCLK 2 +.latch Ng27709 Ng2507 re PCLK 2 +.latch Ng27710 Ng2510 re PCLK 2 +.latch Ng27711 Ng2513 re PCLK 2 +.latch Ng27712 Ng2516 re PCLK 2 +.latch Ng27713 Ng2519 re PCLK 2 +.latch Ng28689 Ng2523 re PCLK 2 +.latch Ng28690 Ng2524 re PCLK 2 +.latch Ng28691 Ng2522 re PCLK 2 +.latch Ng29807 Ng2387 re PCLK 2 +.latch Ng29808 Ng2388 re PCLK 2 +.latch Ng29809 Ng2389 re PCLK 2 +.latch Ng30905 Ng2390 re PCLK 2 +.latch Ng30906 Ng2391 re PCLK 2 +.latch Ng30907 Ng2392 re PCLK 2 +.latch Ng30719 Ng2393 re PCLK 2 +.latch Ng30720 Ng2394 re PCLK 2 +.latch Ng30721 Ng2395 re PCLK 2 +.latch Ng29649 Ng2397 re PCLK 2 +.latch Ng29650 Ng2398 re PCLK 2 +.latch Ng29651 Ng2396 re PCLK 2 +.latch Ng27230 Ng2478 re PCLK 2 +.latch Ng27231 Ng2479 re PCLK 2 +.latch Ng27232 Ng2477 re PCLK 2 +.latch Ng11590 Ng2525 re PCLK 2 +.latch Ng2525 Ng2526 re PCLK 2 +.latch Ng11591 Ng2527 re PCLK 2 +.latch Ng2527 Ng2528 re PCLK 2 +.latch Ng11592 Ng2529 re PCLK 2 +.latch Ng2529 Ng2354 re PCLK 2 +.latch Ng11572 Ng2355 re PCLK 2 +.latch Ng2355 Ng2356 re PCLK 2 +.latch Ng11573 Ng2357 re PCLK 2 +.latch Ng2357 Ng2358 re PCLK 2 +.latch Ng11574 Ng2359 re PCLK 2 +.latch Ng2359 Ng2360 re PCLK 2 +.latch Ng11575 Ng2361 re PCLK 2 +.latch Ng2361 Ng2362 re PCLK 2 +.latch Ng11576 Ng2363 re PCLK 2 +.latch Ng2363 Ng2364 re PCLK 2 +.latch Ng13455 Ng2365 re PCLK 2 +.latch Ng2365 Ng2366 re PCLK 2 +.latch Ng19048 Ng2374 re PCLK 2 +.latch Ng30314 Ng2380 re PCLK 2 +.latch Ng27229 Ng2373 re PCLK 2 +.latch Ng11578 Ng2417 re PCLK 2 +.latch Ng2417 Ng2424 re PCLK 2 +.latch Ng11579 Ng2425 re PCLK 2 +.latch Ng2425 Ng2426 re PCLK 2 +.latch Ng11580 Ng2427 re PCLK 2 +.latch Ng2427 Ng2428 re PCLK 2 +.latch Ng11581 Ng2432 re PCLK 2 +.latch Ng2432 Ng2439 re PCLK 2 +.latch Ng11582 Ng2440 re PCLK 2 +.latch Ng2440 Ng2441 re PCLK 2 +.latch Ng11583 Ng2442 re PCLK 2 +.latch Ng2442 Ng2443 re PCLK 2 +.latch Ng11584 Ng2447 re PCLK 2 +.latch Ng2447 Ng2454 re PCLK 2 +.latch Ng11585 Ng2455 re PCLK 2 +.latch Ng2455 Ng2456 re PCLK 2 +.latch Ng11586 Ng2457 re PCLK 2 +.latch Ng2457 Ng2458 re PCLK 2 +.latch Ng11587 Ng2462 re PCLK 2 +.latch Ng2462 Ng2469 re PCLK 2 +.latch Ng11588 Ng2470 re PCLK 2 +.latch Ng2470 Ng2471 re PCLK 2 +.latch Ng11589 Ng2472 re PCLK 2 +.latch Ng2472 Ng2399 re PCLK 2 +.latch Ng23274 Ng2628 re PCLK 2 +.latch Ng20568 Ng2631 re PCLK 2 +.latch Ng20569 Ng2584 re PCLK 2 +.latch Ng16473 Ng2587 re PCLK 2 +.latch Ng2587 Ng2597 re PCLK 2 +.latch Ng2597 Ng2598 re PCLK 2 +.latch Ng11593 Ng2638 re PCLK 2 +.latch Ng2638 Ng2643 re PCLK 2 +.latch Ng11596 Ng2644 re PCLK 2 +.latch Ng2644 Ng2645 re PCLK 2 +.latch Ng11597 Ng2646 re PCLK 2 +.latch Ng2646 Ng2647 re PCLK 2 +.latch Ng11598 Ng2648 re PCLK 2 +.latch Ng2648 Ng2639 re PCLK 2 +.latch Ng11594 Ng2640 re PCLK 2 +.latch Ng2640 Ng2641 re PCLK 2 +.latch Ng11595 Ng2642 re PCLK 2 +.latch Ng2642 Ng2564 re PCLK 2 +.latch Ng24415 Ng2561 re PCLK 2 +.latch Ng24416 Ng2562 re PCLK 2 +.latch Ng24417 Ng2563 re PCLK 2 +.latch Ng25172 Ng11593 re PCLK 2 +.latch Ng25164 Ng11596 re PCLK 2 +.latch Ng25165 Ng11597 re PCLK 2 +.latch Ng25169 Ng2552 re PCLK 2 +.latch Ng25170 Ng2553 re PCLK 2 +.latch Ng25171 Ng2554 re PCLK 2 +.latch Ng24412 Ng2555 re PCLK 2 +.latch Ng24413 Ng2559 re PCLK 2 +.latch Ng24414 Ng2539 re PCLK 2 +.latch Ng25166 Ng11598 re PCLK 2 +.latch Ng25167 Ng11594 re PCLK 2 +.latch Ng25168 Ng11595 re PCLK 2 +.latch Ng16474 Ng2602 re PCLK 2 +.latch Ng2602 Ng2609 re PCLK 2 +.latch Ng2609 Ng2616 re PCLK 2 +.latch Ng19057 Ng2617 re PCLK 2 +.latch Ng2617 Ng2618 re PCLK 2 +.latch Ng30325 Ng2622 re PCLK 2 +.latch Ng19058 Ng2623 re PCLK 2 +.latch Ng2623 Ng8311 re PCLK 2 +.latch Ng19059 Ng2632 re PCLK 2 +.latch Ng2632 Ng2633 re PCLK 2 +.latch Ng28297 Ng2650 re PCLK 2 +.latch Ng28298 Ng2651 re PCLK 2 +.latch Ng28299 Ng2649 re PCLK 2 +.latch Ng28300 Ng2653 re PCLK 2 +.latch Ng28301 Ng2654 re PCLK 2 +.latch Ng28302 Ng2652 re PCLK 2 +.latch Ng28303 Ng2656 re PCLK 2 +.latch Ng28304 Ng2657 re PCLK 2 +.latch Ng28305 Ng2655 re PCLK 2 +.latch Ng28306 Ng2659 re PCLK 2 +.latch Ng28307 Ng2660 re PCLK 2 +.latch Ng28308 Ng2658 re PCLK 2 +.latch Ng26012 Ng2661 re PCLK 2 +.latch Ng26013 Ng2664 re PCLK 2 +.latch Ng26014 Ng2667 re PCLK 2 +.latch Ng26015 Ng2670 re PCLK 2 +.latch Ng26016 Ng2673 re PCLK 2 +.latch Ng26017 Ng2676 re PCLK 2 +.latch Ng29159 Ng2688 re PCLK 2 +.latch Ng29160 Ng2691 re PCLK 2 +.latch Ng29161 Ng2694 re PCLK 2 +.latch Ng29156 Ng2679 re PCLK 2 +.latch Ng29157 Ng2682 re PCLK 2 +.latch Ng29158 Ng2685 re PCLK 2 +.latch Ng27233 Ng2565 re PCLK 2 +.latch Ng27234 Ng2568 re PCLK 2 +.latch Ng27235 Ng2571 re PCLK 2 +.latch Ng8311 Ng2580 re PCLK 2 +.latch Ng24418 Ng2581 re PCLK 2 +.latch Ng30320 Pg16437 re PCLK 2 +.latch Pg16437 Ng2599 re PCLK 2 +.latch Ng13458 Ng2603 re PCLK 2 +.latch Ng13459 Ng2604 re PCLK 2 +.latch Ng13460 Ng2605 re PCLK 2 +.latch Ng13461 Ng2606 re PCLK 2 +.latch Ng13462 Ng2607 re PCLK 2 +.latch Ng13463 Ng2608 re PCLK 2 +.latch Ng13464 Ng2610 re PCLK 2 +.latch Ng13465 Ng2611 re PCLK 2 +.latch Ng26011 Ng2612 re PCLK 2 +.latch Ng13466 Ng2615 re PCLK 2 +.latch Ng20570 Ng2704 re PCLK 2 +.latch Ng21946 Ng2733 re PCLK 2 +.latch Ng23275 Ng2714 re PCLK 2 +.latch Ng24419 Ng2707 re PCLK 2 +.latch Ng25173 Ng2727 re PCLK 2 +.latch Ng26018 Ng2720 re PCLK 2 +.latch Ng26742 Ng2734 re PCLK 2 +.latch Ng27236 Ng2746 re PCLK 2 +.latch Ng27714 Ng2740 re PCLK 2 +.latch Ng28309 Ng2753 re PCLK 2 +.latch Ng28692 Ng2760 re PCLK 2 +.latch Ng29162 Ng2766 re PCLK 2 +.latch Ng23276 Ng2773 re PCLK 2 +.latch Ng23277 Ng2774 re PCLK 2 +.latch Ng23278 Ng2772 re PCLK 2 +.latch Ng23279 Ng2776 re PCLK 2 +.latch Ng23280 Ng2777 re PCLK 2 +.latch Ng23281 Ng2775 re PCLK 2 +.latch Ng23282 Ng2779 re PCLK 2 +.latch Ng23283 Ng2780 re PCLK 2 +.latch Ng23284 Ng2778 re PCLK 2 +.latch Ng23285 Ng2782 re PCLK 2 +.latch Ng23286 Ng2783 re PCLK 2 +.latch Ng23287 Ng2781 re PCLK 2 +.latch Ng23288 Ng2785 re PCLK 2 +.latch Ng23289 Ng2786 re PCLK 2 +.latch Ng23290 Ng2784 re PCLK 2 +.latch Ng23291 Ng2788 re PCLK 2 +.latch Ng23292 Ng2789 re PCLK 2 +.latch Ng23293 Ng2787 re PCLK 2 +.latch Ng23294 Ng2791 re PCLK 2 +.latch Ng23295 Ng2792 re PCLK 2 +.latch Ng23296 Ng2790 re PCLK 2 +.latch Ng23297 Ng2794 re PCLK 2 +.latch Ng23298 Ng2795 re PCLK 2 +.latch Ng23299 Ng2793 re PCLK 2 +.latch Ng23300 Ng2797 re PCLK 2 +.latch Ng23301 Ng2798 re PCLK 2 +.latch Ng23302 Ng2796 re PCLK 2 +.latch Ng23303 Ng2800 re PCLK 2 +.latch Ng23304 Ng2801 re PCLK 2 +.latch Ng23305 Ng2799 re PCLK 2 +.latch Ng23306 Ng2803 re PCLK 2 +.latch Ng23307 Ng2804 re PCLK 2 +.latch Ng23308 Ng2802 re PCLK 2 +.latch Ng23309 Ng2806 re PCLK 2 +.latch Ng23310 Ng2807 re PCLK 2 +.latch Ng23311 Ng2805 re PCLK 2 +.latch Ng26743 Ng2809 re PCLK 2 +.latch Ng26744 Ng2810 re PCLK 2 +.latch Ng26745 Ng2808 re PCLK 2 +.latch Ng24420 Ng2812 re PCLK 2 +.latch Ng24421 Ng2813 re PCLK 2 +.latch Ng24422 Ng2811 re PCLK 2 +.latch Ng23317 Ng3054 re PCLK 2 +.latch Ng23318 Ng3079 re PCLK 2 +.latch Ng21965 Ng13475 re PCLK 2 +.latch Ng29453 Ng3043 re PCLK 2 +.latch Ng29454 Ng3044 re PCLK 2 +.latch Ng29455 Ng3045 re PCLK 2 +.latch Ng29456 Ng3046 re PCLK 2 +.latch Ng29457 Ng3047 re PCLK 2 +.latch Ng29458 Ng3048 re PCLK 2 +.latch Ng29459 Ng3049 re PCLK 2 +.latch Ng29460 Ng3050 re PCLK 2 +.latch Ng29655 Ng3051 re PCLK 2 +.latch Ng29972 Ng3052 re PCLK 2 +.latch Ng29973 Ng3053 re PCLK 2 +.latch Ng29974 Ng3055 re PCLK 2 +.latch Ng29975 Ng3056 re PCLK 2 +.latch Ng29976 Ng3057 re PCLK 2 +.latch Ng29977 Ng3058 re PCLK 2 +.latch Ng29978 Ng3059 re PCLK 2 +.latch Ng29979 Ng3060 re PCLK 2 +.latch Ng30119 Ng3061 re PCLK 2 +.latch Ng30908 Ng3062 re PCLK 2 +.latch Ng30909 Ng3063 re PCLK 2 +.latch Ng30910 Ng3064 re PCLK 2 +.latch Ng30911 Ng3065 re PCLK 2 +.latch Ng30912 Ng3066 re PCLK 2 +.latch Ng30913 Ng3067 re PCLK 2 +.latch Ng30914 Ng3068 re PCLK 2 +.latch Ng30915 Ng3069 re PCLK 2 +.latch Ng30940 Ng3070 re PCLK 2 +.latch Ng30980 Ng3071 re PCLK 2 +.latch Ng30981 Ng3072 re PCLK 2 +.latch Ng30982 Ng3073 re PCLK 2 +.latch Ng30983 Ng3074 re PCLK 2 +.latch Ng30984 Ng3075 re PCLK 2 +.latch Ng30985 Ng3076 re PCLK 2 +.latch Ng30986 Ng3077 re PCLK 2 +.latch Ng30987 Ng3078 re PCLK 2 +.latch Ng30989 Ng2997 re PCLK 2 +.latch Ng26748 Ng2993 re PCLK 2 +.latch Ng27238 Ng2998 re PCLK 2 +.latch Ng25177 Ng3006 re PCLK 2 +.latch Ng26021 Ng3002 re PCLK 2 +.latch Ng26750 Ng3013 re PCLK 2 +.latch Ng27239 Ng3010 re PCLK 2 +.latch Ng27716 Ng3024 re PCLK 2 +.latch Ng24425 Ng3018 re PCLK 2 +.latch Ng25176 Ng3028 re PCLK 2 +.latch Ng26022 Ng3036 re PCLK 2 +.latch Ng26749 Ng3032 re PCLK 2 +.latch Pg3234 Pg5388 re PCLK 2 +.latch Pg5388 Ng2986 re PCLK 2 +.latch Pg16496 Ng2987 re PCLK 2 +.latch Ng20595 Pg8275 re PCLK 2 +.latch Ng20596 Pg8274 re PCLK 2 +.latch Ng20597 Pg8273 re PCLK 2 +.latch Ng20598 Pg8272 re PCLK 2 +.latch Ng20599 Pg8268 re PCLK 2 +.latch Ng20600 Pg8269 re PCLK 2 +.latch Ng20601 Pg8270 re PCLK 2 +.latch Ng20602 Pg8271 re PCLK 2 +.latch Ng20603 Ng3083 re PCLK 2 +.latch Ng20604 Pg8267 re PCLK 2 +.latch Ng21966 Ng2992 re PCLK 2 +.latch Ng20605 Pg8266 re PCLK 2 +.latch Ng20606 Pg8265 re PCLK 2 +.latch Ng20607 Pg8264 re PCLK 2 +.latch Ng20608 Pg8262 re PCLK 2 +.latch Ng20589 Pg8263 re PCLK 2 +.latch Ng20590 Pg8260 re PCLK 2 +.latch Ng20591 Pg8261 re PCLK 2 +.latch Ng20592 Pg8259 re PCLK 2 +.latch Ng20593 Ng2990 re PCLK 2 +.latch Ng21964 Ng2991 re PCLK 2 +.latch Ng20594 Pg8258 re PCLK 2 +.names Ng29656 Pg27380 +0 1 +.names n1770 Pg26149 +0 1 +.names Ng29166 Pg26135 +0 1 +.names n1778 Pg26104 +0 1 +.names n3323 Pg25489 +0 1 +.names Pg3233 Pg3230 [1521] +0- 1 +-1 1 +.names Ng28696 Pg25435 +0 1 +.names Ng28313 Pg24734 +0 1 +.names n188 Pg16496 +0 1 +.names Pg8269 Pg8268 n1139 +01 1 +10 1 +.names Pg8271 Pg8270 n1138 +01 1 +10 1 +.names n1139 n1138 n1137 +01 1 +10 1 +.names Pg8262 Pg8264 n1142 +01 1 +10 1 +.names Pg8265 Pg8266 n1141 +01 1 +10 1 +.names n1142 n1141 n1140 +01 1 +10 1 +.names Pg8259 Pg8261 n1145 +01 1 +10 1 +.names Pg8260 Pg8263 n1144 +01 1 +10 1 +.names n1145 n1144 n1143 +01 1 +10 1 +.names Pg8272 Pg8273 n1148 +01 1 +10 1 +.names Pg8275 Pg8274 n1147 +01 1 +10 1 +.names n1148 n1147 n1146 +01 1 +10 1 +.names [1605] Ng1315 Ng324 Ng394 n69 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n69 Ng396 n66 +01- 1 +-10 1 +.names [1605] Ng1315 Ng383 Ng379 n72 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n72 Ng381 n70 +01- 1 +-10 1 +.names [1605] Ng1315 Ng1011 Ng1081 n75 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n75 Ng1083 n73 +01- 1 +-10 1 +.names [1605] Ng1315 Ng368 Ng364 n78 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n78 Ng366 n76 +01- 1 +-10 1 +.names [1605] Ng1315 Ng1070 Ng1066 n81 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n81 Ng1068 n79 +01- 1 +-10 1 +.names [1605] Ng1315 Ng1705 Ng1775 n84 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n84 Ng1777 n82 +01- 1 +-10 1 +.names [1605] Ng1315 Ng353 Ng349 n87 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n87 Ng351 n85 +01- 1 +-10 1 +.names [1605] Ng1315 Ng1055 Ng1051 n90 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n90 Ng1053 n88 +01- 1 +-10 1 +.names [1605] Ng1315 Ng1764 Ng1760 n93 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n93 Ng1762 n91 +01- 1 +-10 1 +.names [1605] Ng1315 Ng2399 Ng2469 n96 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n96 Ng2471 n94 +01- 1 +-10 1 +.names [1605] Ng1315 Ng1040 Ng1036 n99 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n99 Ng1038 n97 +01- 1 +-10 1 +.names [1605] Ng1315 Ng1749 Ng1745 n102 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n102 Ng1747 n100 +01- 1 +-10 1 +.names [1605] Ng1315 Ng2458 Ng2454 n105 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n105 Ng2456 n103 +01- 1 +-10 1 +.names [1605] Ng1315 Ng1734 Ng1730 n108 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n108 Ng1732 n106 +01- 1 +-10 1 +.names [1605] Ng1315 Ng2443 Ng2439 n111 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n111 Ng2441 n109 +01- 1 +-10 1 +.names [1605] Ng1315 Ng2428 Ng2424 n114 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n114 Ng2426 n112 +01- 1 +-10 1 +.names [1605] Ng1315 Ng496 Ng490 n117 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n117 Ng493 n115 +01- 1 +-10 1 +.names [1605] Ng1315 Ng1183 Ng1177 n120 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n120 Ng1180 n118 +01- 1 +-10 1 +.names [1605] Ng1315 Ng1877 Ng1871 n123 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n123 Ng1874 n121 +01- 1 +-10 1 +.names [1605] Ng1315 Ng2571 Ng2565 n126 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n126 Ng2568 n124 +01- 1 +-10 1 +.names [1612] Ng853 Ng448 Ng447 n129 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names [1594] n129 Ng449 n127 +01- 1 +-11 1 +.names [1612] Ng853 Ng402 Ng403 n131 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n131 Ng404 n130 +01- 1 +-11 1 +.names [1603] [1605] Ng479 Ng477 n133 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names Ng1315 n133 Ng478 Ng19021 +01- 1 +-11 1 +.names [1603] [1605] Ng464 Ng480 n134 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names Ng1315 n134 Ng484 Ng19022 +01- 1 +-11 1 +.names [1612] Ng853 Ng1135 Ng1134 n136 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names [1594] n136 Ng1136 n135 +01- 1 +-11 1 +.names [1612] Ng853 Ng1089 Ng1090 n138 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n138 Ng1091 n137 +01- 1 +-11 1 +.names [1603] [1605] Ng1166 Ng1164 n139 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names Ng1315 n139 Ng1165 Ng19033 +01- 1 +-11 1 +.names [1603] [1605] Ng488 Ng486 n140 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names Ng1315 n140 Ng487 Ng19023 +01- 1 +-11 1 +.names [1603] [1605] Ng1151 Ng1167 n141 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names Ng1315 n141 Ng1171 Ng19034 +01- 1 +-11 1 +.names [1612] Ng853 Ng1829 Ng1828 n143 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names [1594] n143 Ng1830 n142 +01- 1 +-11 1 +.names [1612] Ng853 Ng1783 Ng1784 n145 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n145 Ng1785 n144 +01- 1 +-11 1 +.names [1603] [1605] Ng1860 Ng1858 n146 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names Ng1315 n146 Ng1859 Ng19045 +01- 1 +-11 1 +.names [1605] Ng1315 Ng573 Ng569 n148 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n148 Ng571 Ng16467 +01- 1 +-10 1 +.names [1603] [1605] Ng1175 Ng1173 n149 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names Ng1315 n149 Ng1174 Ng19035 +01- 1 +-11 1 +.names [1603] [1605] Ng1845 Ng1861 n150 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names Ng1315 n150 Ng1865 Ng19046 +01- 1 +-11 1 +.names [1612] Ng853 Ng2523 Ng2522 n152 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names [1594] n152 Ng2524 n151 +01- 1 +-11 1 +.names [1612] Ng853 Ng2477 Ng2478 n154 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n154 Ng2479 n153 +01- 1 +-11 1 +.names [1603] [1605] Ng2554 Ng2552 n155 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names Ng1315 n155 Ng2553 Ng19057 +01- 1 +-11 1 +.names [1605] Ng1315 Ng1259 Ng1255 n157 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n157 Ng1257 Ng16469 +01- 1 +-10 1 +.names [1603] [1605] Ng1869 Ng1867 n158 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names Ng1315 n158 Ng1868 Ng19047 +01- 1 +-11 1 +.names [1603] [1605] Ng2539 Ng2555 n159 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names Ng1315 n159 Ng2559 Ng19058 +01- 1 +-11 1 +.names [1612] Ng853 Ng321 Ng322 n161 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n161 Ng323 n160 +01- 1 +-11 1 +.names [1605] Ng1315 Ng1953 Ng1949 n163 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n163 Ng1951 Ng16471 +01- 1 +-10 1 +.names [1603] [1605] Ng2563 Ng2561 n164 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names Ng1315 n164 Ng2562 Ng19059 +01- 1 +-11 1 +.names [1605] Ng1315 Ng489 Ng565 n166 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n166 Ng567 Ng16468 +01- 1 +-10 1 +.names [1612] Ng853 Ng1008 Ng1009 n168 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n168 Ng1010 n167 +01- 1 +-11 1 +.names [1605] Ng1315 Ng2647 Ng2643 n170 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n170 Ng2645 Ng16473 +01- 1 +-10 1 +.names [1605] Ng1315 Ng1176 Ng1251 n172 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n172 Ng1253 Ng16470 +01- 1 +-10 1 +.names [1612] Ng853 Ng1702 Ng1703 n174 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n174 Ng1704 n173 +01- 1 +-11 1 +.names [1605] Ng1315 Ng1870 Ng1945 n176 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n176 Ng1947 Ng16472 +01- 1 +-10 1 +.names [1612] Ng853 Ng2396 Ng2397 n178 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n178 Ng2398 n177 +01- 1 +-11 1 +.names [1605] Ng1315 Ng2564 Ng2639 n180 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1603] n180 Ng2641 Ng16474 +01- 1 +-10 1 +.names [1594] Ng853 Ng141 Ng143 n183 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1612] n183 Ng142 n181 +01- 1 +-11 1 +.names [1594] Ng853 Ng144 Ng146 n185 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1612] n185 Ng145 n184 +01- 1 +-11 1 +.names [1594] Ng853 Ng829 Ng831 n187 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1612] n187 Ng830 n186 +01- 1 +-11 1 +.names Pg5388 Ng2987 Ng2986 n188 +01- 1 +-11 1 +.names [1594] Ng853 Ng147 Ng149 n190 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1612] n190 Ng148 n189 +01- 1 +-11 1 +.names [1594] Ng853 Ng832 Ng834 n192 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1612] n192 Ng833 n191 +01- 1 +-11 1 +.names [1594] Ng853 Ng1523 Ng1525 n194 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1612] n194 Ng1524 n193 +01- 1 +-11 1 +.names [1594] Ng853 Ng150 Ng152 n196 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1612] n196 Ng151 n195 +01- 1 +-11 1 +.names [1594] Ng853 Ng216 Ng219 n199 +00-- 1 +-00- 1 +0--0 1 +--00 1 +.names [1612] n199 Ng213 n197 +01- 1 +-10 1 +.names [1594] Ng853 Ng835 Ng837 n201 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1612] n201 Ng836 n200 +01- 1 +-11 1 +.names [1594] Ng853 Ng1526 Ng1528 n203 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1612] n203 Ng1527 n202 +01- 1 +-11 1 +.names [1594] Ng853 Ng2217 Ng2219 n205 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1612] n205 Ng2218 n204 +01- 1 +-11 1 +.names [1612] Ng853 Ng153 Ng154 n207 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n207 Ng155 n206 +01- 1 +-11 1 +.names [1594] [1612] Ng222 Ng225 n211 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names Ng853 n211 Ng228 n208 +01- 1 +-10 1 +.names [1612] Ng853 Ng838 Ng839 n213 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n213 Ng840 n212 +01- 1 +-11 1 +.names [1594] [1612] Ng900 Ng903 n216 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names Ng853 n216 Ng906 n214 +01- 1 +-10 1 +.names [1612] Ng853 Ng1529 Ng1530 n218 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n218 Ng1531 n217 +01- 1 +-11 1 +.names [1612] Ng853 Ng2220 Ng2221 n220 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n220 Ng2222 n219 +01- 1 +-11 1 +.names [1612] Ng853 Ng156 Ng157 n222 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n222 Ng158 n221 +01- 1 +-11 1 +.names [1612] Ng853 Ng237 Ng231 n225 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n225 Ng234 n223 +01- 1 +-10 1 +.names [1605] Ng1315 Ng698 Ng699 n227 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1603] n227 Ng700 n226 +01- 1 +-11 1 +.names [1605] Ng1315 Ng725 Ng726 n229 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1603] n229 Ng727 n228 +01- 1 +-11 1 +.names [1612] Ng853 Ng841 Ng842 n231 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n231 Ng843 n230 +01- 1 +-11 1 +.names [1612] Ng853 Ng915 Ng909 n234 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n234 Ng912 n232 +01- 1 +-10 1 +.names [1612] Ng853 Ng1532 Ng1533 n236 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n236 Ng1534 n235 +01- 1 +-11 1 +.names [1612] Ng853 Ng1600 Ng1594 n239 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n239 Ng1597 n237 +01- 1 +-10 1 +.names [1612] Ng853 Ng2223 Ng2224 n241 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n241 Ng2225 n240 +01- 1 +-11 1 +.names [1612] Ng853 Ng159 Ng160 n243 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n243 Ng161 n242 +01- 1 +-11 1 +.names [1612] Ng853 Ng246 Ng240 n246 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n246 Ng243 n244 +01- 1 +-10 1 +.names [1605] Ng1315 Ng701 Ng702 n248 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1603] n248 Ng703 n247 +01- 1 +-11 1 +.names [1612] Ng853 Ng844 Ng845 n250 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n250 Ng846 n249 +01- 1 +-11 1 +.names [1612] Ng853 Ng924 Ng918 n253 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n253 Ng921 n251 +01- 1 +-10 1 +.names [1605] Ng1315 Ng1384 Ng1385 n255 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1603] n255 Ng1386 n254 +01- 1 +-11 1 +.names [1605] Ng1315 Ng1411 Ng1412 n257 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1603] n257 Ng1413 n256 +01- 1 +-11 1 +.names [1612] Ng853 Ng1535 Ng1536 n259 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n259 Ng1537 n258 +01- 1 +-11 1 +.names [1612] Ng853 Ng1609 Ng1603 n262 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n262 Ng1606 n260 +01- 1 +-10 1 +.names [1612] Ng853 Ng2226 Ng2227 n264 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n264 Ng2228 n263 +01- 1 +-11 1 +.names [1612] Ng853 Ng2294 Ng2288 n267 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n267 Ng2291 n265 +01- 1 +-10 1 +.names [1612] Ng853 Ng129 Ng130 n269 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n269 Ng131 n268 +01- 1 +-11 1 +.names [1612] Ng853 Ng162 Ng163 n271 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n271 Ng164 n270 +01- 1 +-11 1 +.names [1612] Ng853 Ng255 Ng249 n274 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n274 Ng252 n272 +01- 1 +-10 1 +.names [1605] Ng1315 Ng704 Ng705 n276 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1603] n276 Ng706 n275 +01- 1 +-11 1 +.names [1612] Ng853 Ng847 Ng848 n278 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n278 Ng849 n277 +01- 1 +-11 1 +.names [1612] Ng853 Ng933 Ng927 n281 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n281 Ng930 n279 +01- 1 +-10 1 +.names [1605] Ng1315 Ng1387 Ng1388 n283 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1603] n283 Ng1389 n282 +01- 1 +-11 1 +.names [1612] Ng853 Ng1538 Ng1539 n285 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n285 Ng1540 n284 +01- 1 +-11 1 +.names [1612] Ng853 Ng1618 Ng1612 n288 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n288 Ng1615 n286 +01- 1 +-10 1 +.names [1605] Ng1315 Ng2078 Ng2079 n290 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1603] n290 Ng2080 n289 +01- 1 +-11 1 +.names [1605] Ng1315 Ng2105 Ng2106 n292 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1603] n292 Ng2107 n291 +01- 1 +-11 1 +.names [1612] Ng853 Ng2229 Ng2230 n294 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n294 Ng2231 n293 +01- 1 +-11 1 +.names [1612] Ng853 Ng2303 Ng2297 n297 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n297 Ng2300 n295 +01- 1 +-10 1 +.names [1612] Ng853 Ng132 Ng133 n299 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n299 Ng134 n298 +01- 1 +-11 1 +.names [1612] Ng853 Ng264 Ng258 n302 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n302 Ng261 n300 +01- 1 +-10 1 +.names [1612] Ng853 Ng11499 Ng11497 n304 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n304 Ng11498 n303 +01- 1 +-11 1 +.names [1612] Ng853 Ng435 Ng429 n307 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n307 Ng432 n305 +01- 1 +-10 1 +.names [1605] Ng1315 Ng707 Ng708 n309 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1603] n309 Ng709 n308 +01- 1 +-11 1 +.names [1612] Ng853 Ng817 Ng818 n311 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n311 Ng819 n310 +01- 1 +-11 1 +.names [1612] Ng853 Ng850 Ng851 n313 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n313 Ng852 n312 +01- 1 +-11 1 +.names [1612] Ng853 Ng942 Ng936 n316 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n316 Ng939 n314 +01- 1 +-10 1 +.names [1605] Ng1315 Ng1390 Ng1391 n318 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1603] n318 Ng1392 n317 +01- 1 +-11 1 +.names [1612] Ng853 Ng1541 Ng1542 n320 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n320 Ng1543 n319 +01- 1 +-11 1 +.names [1612] Ng853 Ng1627 Ng1621 n323 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n323 Ng1624 n321 +01- 1 +-10 1 +.names [1605] Ng1315 Ng2081 Ng2082 n325 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1603] n325 Ng2083 n324 +01- 1 +-11 1 +.names [1612] Ng853 Ng2232 Ng2233 n327 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n327 Ng2234 n326 +01- 1 +-11 1 +.names [1612] Ng853 Ng2312 Ng2306 n330 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n330 Ng2309 n328 +01- 1 +-10 1 +.names [1605] Ng1315 Ng2772 Ng2773 n332 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1603] n332 Ng2774 n331 +01- 1 +-11 1 +.names [1605] Ng1315 Ng2799 Ng2800 n334 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1603] n334 Ng2801 n333 +01- 1 +-11 1 +.names [1612] Ng853 Ng192 Ng186 n337 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n337 Ng189 n335 +01- 1 +-10 1 +.names [1612] Ng853 Ng273 Ng267 n340 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n340 Ng270 n338 +01- 1 +-10 1 +.names [1612] Ng853 Ng11502 Ng11500 n342 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n342 Ng11501 n341 +01- 1 +-11 1 +.names [1612] Ng853 Ng444 Ng438 n345 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n345 Ng441 n343 +01- 1 +-10 1 +.names [1605] Ng1315 Ng710 Ng711 n347 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1603] n347 Ng712 n346 +01- 1 +-11 1 +.names [1612] Ng853 Ng820 Ng821 n349 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n349 Ng822 n348 +01- 1 +-11 1 +.names [1612] Ng853 Ng951 Ng945 n352 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n352 Ng948 n350 +01- 1 +-10 1 +.names [1612] Ng853 Ng11526 Ng11524 n354 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n354 Ng11525 n353 +01- 1 +-11 1 +.names [1612] Ng853 Ng1122 Ng1116 n357 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n357 Ng1119 n355 +01- 1 +-10 1 +.names [1605] Ng1315 Ng1393 Ng1394 n359 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1603] n359 Ng1395 n358 +01- 1 +-11 1 +.names [1612] Ng853 Ng1511 Ng1512 n361 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n361 Ng1513 n360 +01- 1 +-11 1 +.names [1612] Ng853 Ng1544 Ng1545 n363 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n363 Ng1546 n362 +01- 1 +-11 1 +.names [1612] Ng853 Ng1636 Ng1630 n366 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n366 Ng1633 n364 +01- 1 +-10 1 +.names [1605] Ng1315 Ng2084 Ng2085 n368 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1603] n368 Ng2086 n367 +01- 1 +-11 1 +.names [1612] Ng853 Ng2235 Ng2236 n370 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n370 Ng2237 n369 +01- 1 +-11 1 +.names [1612] Ng853 Ng2321 Ng2315 n373 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n373 Ng2318 n371 +01- 1 +-10 1 +.names [1605] Ng1315 Ng2775 Ng2776 n375 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1603] n375 Ng2777 n374 +01- 1 +-11 1 +.names [1612] Ng853 Ng201 Ng195 n378 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n378 Ng198 n376 +01- 1 +-10 1 +.names [1612] Ng853 Ng11505 Ng11503 n380 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n380 Ng11504 n379 +01- 1 +-11 1 +.names [1605] Ng1315 Ng713 Ng714 n382 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1603] n382 Ng715 n381 +01- 1 +-11 1 +.names [1605] Ng1315 Ng731 Ng732 n384 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1603] n384 Ng733 n383 +01- 1 +-11 1 +.names [1612] Ng853 Ng879 Ng873 n387 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n387 Ng876 n385 +01- 1 +-10 1 +.names [1612] Ng853 Ng960 Ng954 n390 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n390 Ng957 n388 +01- 1 +-10 1 +.names [1612] Ng853 Ng11529 Ng11527 n392 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n392 Ng11528 n391 +01- 1 +-11 1 +.names [1612] Ng853 Ng1131 Ng1125 n395 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n395 Ng1128 n393 +01- 1 +-10 1 +.names [1605] Ng1315 Ng1396 Ng1397 n397 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1603] n397 Ng1398 n396 +01- 1 +-11 1 +.names [1612] Ng853 Ng1514 Ng1515 n399 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n399 Ng1516 n398 +01- 1 +-11 1 +.names [1612] Ng853 Ng1645 Ng1639 n402 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names [1594] n402 Ng1642 n400 +01- 1 +-10 1 +.names [1612] Ng853 Ng11553 Ng11551 n404 +00-- 1 +0-1- 1 +-0-1 1 +--11 1 +.names [1594] n404 Ng11552 n403 +01- 1 +-11 1 +.names [1612] Ng853 Ng1816 Ng1810 n407 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 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n1481 +0-- 1 +-1- 1 +--0 1 +.names n272 n1437 n1481 n1479 +01- 1 +-11 1 +.names n1479 n1439 n1482 +11 1 +.names Ng125 n1448 n1483 +10 1 +.names Ng121 n1448 n1484 +10 1 +.names Ng113 n1448 n1485 +10 1 +.names Ng97 n1448 n1486 +10 1 +.names [1603] n497 Ng1425 n3824 n1488 +-1-0 1 +110- 1 +.names n254 n396 n431 n469 n1488 n3826 n1487 +111110 1 +.names Ng1243 n4032 n4034 n1491 +0-1 1 +-11 1 +.names n1167 n1172 n1490 +11 1 +00 1 +.names n669 n671 n1494 +1- 1 +-0 1 +.names n1056 n1494 n1497 +0- 1 +-1 1 +.names [1603] Ng1315 Ng1422 Ng1420 n1500 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names n555 n1457 n1546 n2320 n1507 +11-- 1 +-10- 1 +-1-0 1 +.names Ng2133 Ng2129 n1598 n1510 +111 1 +.names n1510 Ng2124 n1509 +11 1 +.names n546 n1465 n1556 n2355 n1511 +11-- 1 +-10- 1 +-1-0 1 +.names Ng1439 Ng1435 n1605 n1514 +111 1 +.names n1514 Ng1430 n1513 +11 1 +.names n540 n1473 n1566 n2390 n1515 +11-- 1 +-10- 1 +-1-0 1 +.names Ng753 Ng749 n1612 n1518 +111 1 +.names n1518 Ng744 n1517 +11 1 +.names n534 n1481 n1576 n2425 n1519 +11-- 1 +-10- 1 +-1-0 1 +.names Ng65 Ng61 n1619 n1522 +111 1 +.names n1522 Ng56 n1521 +11 1 +.names n2453 n1525 n1526 +1- 1 +-1 1 +.names Ng3135 n2460 n1524 +0- 1 +-1 1 +.names Ng3147 n1768 n1525 +0- 1 +-1 1 +.names n1526 n1524 n1525 n1523 +11- 1 +1-1 1 +.names Ng3120 Ng3135 n2497 n2954 n1529 +1-1- 1 +-01- 1 +--10 1 +.names Ng3147 n1768 n1524 n1527 +1-- 1 +-1- 1 +--1 1 +.names [1605] Ng8284 n1530 +10 1 +.names [1603] n462 Ng739 n3836 n1533 +-1-0 1 +110- 1 +.names n226 n346 n381 n424 n1533 n3838 n1532 +111110 1 +.names Ng557 n4055 n4057 n1536 +0-1 1 +-11 1 +.names n1153 n1158 n1535 +11 1 +00 1 +.names n629 n1215 Ng2257 n2324 n1541 +0--- 1 +-0-- 1 +--0- 1 +---0 1 +.names n629 n657 n1215 n1538 +11- 1 +1-0 1 +.names n629 n657 n1215 n1539 +01- 1 +0-1 1 +.names n620 Ng2257 n1540 +1- 1 +-0 1 +.names n1541 n1538 n1539 n1540 n1537 +11-- 1 +1-1- 1 +1--1 1 +.names n1994 n1995 n1329 n2295 n2296 n2297 n1545 +1----- 1 +-1---- 1 +--1--- 1 +---1-- 1 +----1- 1 +-----1 1 +.names n555 n562 n567 n1546 +1-- 1 +-0- 1 +--1 1 +.names n1343 n1344 n1545 n1546 n1542 +0-1- 1 +-01- 1 +0--1 1 +-0-1 1 +.names n615 n1212 Ng2257 n2359 n1551 +0--- 1 +-0-- 1 +--0- 1 +---0 1 +.names n615 n652 n1212 n1548 +11- 1 +1-0 1 +.names n615 n652 n1212 n1549 +01- 1 +0-1 1 +.names n606 Ng2257 n1550 +1- 1 +-0 1 +.names n1551 n1548 n1549 n1550 n1547 +11-- 1 +1-1- 1 +1--1 1 +.names n2027 n2028 n1362 n2330 n2331 n2332 n1555 +1----- 1 +-1---- 1 +--1--- 1 +---1-- 1 +----1- 1 +-----1 1 +.names n546 n553 n560 n1556 +1-- 1 +-0- 1 +--1 1 +.names n1376 n1377 n1555 n1556 n1552 +0-1- 1 +-01- 1 +0--1 1 +-0-1 1 +.names n601 n1209 Ng2257 n2394 n1561 +0--- 1 +-0-- 1 +--0- 1 +---0 1 +.names n601 n647 n1209 n1558 +11- 1 +1-0 1 +.names n601 n647 n1209 n1559 +01- 1 +0-1 1 +.names n592 Ng2257 n1560 +1- 1 +-0 1 +.names n1561 n1558 n1559 n1560 n1557 +11-- 1 +1-1- 1 +1--1 1 +.names n2060 n2061 n1395 n2365 n2366 n2367 n1565 +1----- 1 +-1---- 1 +--1--- 1 +---1-- 1 +----1- 1 +-----1 1 +.names n540 n544 n551 n1566 +1-- 1 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Ng2760 n1629 n1628 +11 1 +.names n103 n112 n599 n623 n1630 +10-- 1 +-00- 1 +1--0 1 +--00 1 +.names n109 n599 n623 n3850 n1634 +-1-0 1 +110- 1 +.names n103 n112 n611 n3848 n1636 +-1-0 1 +110- 1 +.names n623 n611 n1640 +11 1 +.names n94 n599 n1636 n1640 n1639 +-01- 1 +10-1 1 +.names n112 n632 n1634 n1654 n1641 +0-1- 1 +00-0 1 +.names n94 n109 n623 n1646 +1-- 1 +-1- 1 +--0 1 +.names n103 n109 n623 n1646 n1644 +0--1 1 +-101 1 +.names n112 n623 n632 n1647 +11- 1 +-10 1 +.names n103 n109 n632 n1640 n1648 +1-0- 1 +10-1 1 +.names n94 n599 n632 n1648 n1650 +1--0 1 +-1-0 1 +--10 1 +.names n112 n611 n623 n1653 +10- 1 +0-1 1 +-01 1 +.names n103 n109 n1654 +1- 1 +-1 1 +.names n94 n1647 n1653 n1654 n1652 +0-1- 1 +-11- 1 +0--1 1 +-1-1 1 +.names n611 n1644 n112 n1657 +1-- 1 +-1- 1 +--1 1 +.names n599 n1652 n3000 n1658 +11- 1 +0-0 1 +-10 1 +.names n112 n1650 n1657 n1658 n1656 +0-11 1 +-111 1 +.names Ng16474 Ng185 Ng2616 n1661 +1-- 1 +-0- 1 +--0 1 +.names [1603] [1605] Ng2673 Ng2670 n1662 +00-- 1 +-00- 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1 +-00 1 +.names n2832 Ng30712 +0 1 +.names [1594] Ng319 n904 n2833 +00- 1 +1-0 1 +-00 1 +.names n2833 Ng30711 +0 1 +.names [1612] n904 Ng318 n2834 +10- 1 +0-0 1 +-00 1 +.names n2834 Ng30710 +0 1 +.names n1351 n1459 n3993 n2836 +01- 1 +1-1 1 +-11 1 +.names Ng853 Ng2339 n2836 n2837 +00- 1 +1-0 1 +-00 1 +.names n2837 Ng30565 +0 1 +.names [1594] Ng2336 n2836 n2838 +00- 1 +1-0 1 +-00 1 +.names n2838 Ng30564 +0 1 +.names [1612] Ng2333 n2836 n2839 +00- 1 +1-0 1 +-00 1 +.names n2839 Ng30563 +0 1 +.names Ng853 n2120 Ng2330 n2840 +11- 1 +0-0 1 +-10 1 +.names n2840 Ng30562 +0 1 +.names [1594] n2120 Ng2327 n2841 +11- 1 +0-0 1 +-10 1 +.names n2841 Ng30561 +0 1 +.names [1612] n2120 Ng2324 n2842 +11- 1 +0-0 1 +-10 1 +.names n2842 Ng30560 +0 1 +.names n1351 n1460 n3994 n2844 +01- 1 +1-1 1 +-11 1 +.names Ng853 Ng2294 n2844 n2845 +00- 1 +1-0 1 +-00 1 +.names n2845 Ng30559 +0 1 +.names [1594] Ng2291 n2844 n2846 +00- 1 +1-0 1 +-00 1 +.names n2846 Ng30558 +0 1 +.names [1612] Ng2288 n2844 n2847 +00- 1 +1-0 1 +-00 1 +.names n2847 Ng30557 +0 1 +.names n1351 n1461 n3995 n2849 +01- 1 +1-1 1 +-11 1 +.names Ng853 Ng2285 n2849 n2850 +00- 1 +1-0 1 +-00 1 +.names n2850 Ng30556 +0 1 +.names [1594] Ng2282 n2849 n2851 +00- 1 +1-0 1 +-00 1 +.names n2851 Ng30555 +0 1 +.names [1612] Ng2279 n2849 n2852 +00- 1 +1-0 1 +-00 1 +.names n2852 Ng30554 +0 1 +.names n1351 n1462 n2710 n2854 +01- 1 +1-1 1 +-11 1 +.names Ng853 Ng2267 n2854 n2855 +00- 1 +1-0 1 +-00 1 +.names n2855 Ng30553 +0 1 +.names [1594] Ng2264 n2854 n2856 +00- 1 +1-0 1 +-00 1 +.names n2856 Ng30552 +0 1 +.names [1612] Ng2261 n2854 n2857 +00- 1 +1-0 1 +-00 1 +.names n2857 Ng30551 +0 1 +.names n1384 n1467 n3997 n2859 +01- 1 +1-1 1 +-11 1 +.names Ng853 Ng1645 n2859 n2860 +00- 1 +1-0 1 +-00 1 +.names n2860 Ng30550 +0 1 +.names [1594] Ng1642 n2859 n2861 +00- 1 +1-0 1 +-00 1 +.names n2861 Ng30549 +0 1 +.names [1612] Ng1639 n2859 n2862 +00- 1 +1-0 1 +-00 1 +.names n2862 Ng30548 +0 1 +.names Ng853 n2122 Ng1636 n2863 +11- 1 +0-0 1 +-10 1 +.names n2863 Ng30547 +0 1 +.names [1594] n2122 Ng1633 n2864 +11- 1 +0-0 1 +-10 1 +.names n2864 Ng30546 +0 1 +.names [1612] n2122 Ng1630 n2865 +11- 1 +0-0 1 +-10 1 +.names n2865 Ng30545 +0 1 +.names n1384 n1468 n3998 n2867 +01- 1 +1-1 1 +-11 1 +.names Ng853 Ng1600 n2867 n2868 +00- 1 +1-0 1 +-00 1 +.names n2868 Ng30544 +0 1 +.names [1594] Ng1597 n2867 n2869 +00- 1 +1-0 1 +-00 1 +.names n2869 Ng30543 +0 1 +.names [1612] Ng1594 n2867 n2870 +00- 1 +1-0 1 +-00 1 +.names n2870 Ng30542 +0 1 +.names n1384 n1469 n3999 n2872 +01- 1 +1-1 1 +-11 1 +.names Ng853 Ng1591 n2872 n2873 +00- 1 +1-0 1 +-00 1 +.names n2873 Ng30541 +0 1 +.names [1594] Ng1588 n2872 n2874 +00- 1 +1-0 1 +-00 1 +.names n2874 Ng30540 +0 1 +.names [1612] Ng1585 n2872 n2875 +00- 1 +1-0 1 +-00 1 +.names n2875 Ng30539 +0 1 +.names n1384 n1470 n2711 n2877 +01- 1 +1-1 1 +-11 1 +.names Ng853 Ng1573 n2877 n2878 +00- 1 +1-0 1 +-00 1 +.names n2878 Ng30538 +0 1 +.names [1594] Ng1570 n2877 n2879 +00- 1 +1-0 1 +-00 1 +.names n2879 Ng30537 +0 1 +.names [1612] Ng1567 n2877 n2880 +00- 1 +1-0 1 +-00 1 +.names n2880 Ng30536 +0 1 +.names n1417 n1475 n4001 n2882 +01- 1 +1-1 1 +-11 1 +.names Ng853 Ng951 n2882 n2883 +00- 1 +1-0 1 +-00 1 +.names n2883 Ng30535 +0 1 +.names [1594] Ng948 n2882 n2884 +00- 1 +1-0 1 +-00 1 +.names n2884 Ng30534 +0 1 +.names [1612] Ng945 n2882 n2885 +00- 1 +1-0 1 +-00 1 +.names n2885 Ng30533 +0 1 +.names Ng853 n2124 Ng942 n2886 +11- 1 +0-0 1 +-10 1 +.names n2886 Ng30532 +0 1 +.names [1594] n2124 Ng939 n2887 +11- 1 +0-0 1 +-10 1 +.names n2887 Ng30531 +0 1 +.names [1612] n2124 Ng936 n2888 +11- 1 +0-0 1 +-10 1 +.names n2888 Ng30530 +0 1 +.names n1417 n1476 n4002 n2890 +01- 1 +1-1 1 +-11 1 +.names Ng853 Ng906 n2890 n2891 +00- 1 +1-0 1 +-00 1 +.names n2891 Ng30529 +0 1 +.names [1594] Ng903 n2890 n2892 +00- 1 +1-0 1 +-00 1 +.names n2892 Ng30528 +0 1 +.names [1612] Ng900 n2890 n2893 +00- 1 +1-0 1 +-00 1 +.names n2893 Ng30527 +0 1 +.names n1417 n1477 n4003 n2895 +01- 1 +1-1 1 +-11 1 +.names Ng853 Ng897 n2895 n2896 +00- 1 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Ng2581 n2928 +10- 1 +1-0 1 +-10 1 +.names n2928 Ng30320 +0 1 +.names [1594] Ng305 Ng299 n4020 n2929 +1--1 1 +-0-1 1 +--01 1 +.names n2929 Ng23148 +0 1 +.names n4022 Ng986 Ng985 n2930 +11- 1 +1-1 1 +-01 1 +.names n2930 Ng27200 +0 1 +.names n4025 Ng1680 Ng1679 n2931 +11- 1 +1-1 1 +-01 1 +.names n2931 Ng29428 +0 1 +.names n4028 Ng2374 Ng2373 n2932 +11- 1 +1-1 1 +-01 1 +.names n2932 Ng30314 +0 1 +.names Ng1315 Ng3105 n2729 n2933 +00- 1 +1-1 1 +-01 1 +.names n2933 Ng30122 +0 1 +.names [1603] Ng3104 n2729 n2934 +00- 1 +1-1 1 +-01 1 +.names n2934 Ng30121 +0 1 +.names [1605] Ng3103 n2729 n2935 +00- 1 +1-1 1 +-01 1 +.names n2935 Ng30120 +0 1 +.names n515 n557 n1022 n2936 +10- 1 +0-0 1 +-00 1 +.names n256 n654 n3739 n2937 +10- 1 +0-1 1 +-01 1 +.names n282 n654 n3739 n2938 +10- 1 +0-1 1 +-01 1 +.names n358 n654 n3739 n2939 +10- 1 +0-1 1 +-01 1 +.names n317 n557 n1022 n2940 +10- 1 +0-0 1 +-00 1 +.names Ng853 Ng2389 n4037 n2941 +00- 1 +1-1 1 +-01 1 +.names n2941 Ng29809 +0 1 +.names [1594] Ng2388 n4037 n2942 +00- 1 +1-1 1 +-01 1 +.names n2942 Ng29808 +0 1 +.names [1612] Ng2387 n4037 n2943 +00- 1 +1-1 1 +-01 1 +.names n2943 Ng29807 +0 1 +.names Ng853 Ng1695 n4041 n2944 +00- 1 +1-1 1 +-01 1 +.names n2944 Ng29805 +0 1 +.names [1594] Ng1694 n4041 n2945 +00- 1 +1-1 1 +-01 1 +.names n2945 Ng29804 +0 1 +.names [1612] Ng1693 n4041 n2946 +00- 1 +1-1 1 +-01 1 +.names n2946 Ng29803 +0 1 +.names Ng853 Ng1001 n4045 n2947 +00- 1 +1-1 1 +-01 1 +.names n2947 Ng29801 +0 1 +.names [1594] Ng1000 n4045 n2948 +00- 1 +1-1 1 +-01 1 +.names n2948 Ng29800 +0 1 +.names [1612] Ng999 n4045 n2949 +00- 1 +1-1 1 +-01 1 +.names n2949 Ng29799 +0 1 +.names Ng853 Ng314 n4049 n2950 +00- 1 +1-1 1 +-01 1 +.names n2950 Ng29797 +0 1 +.names [1594] Ng313 n4049 n2951 +00- 1 +1-1 1 +-01 1 +.names n2951 Ng29796 +0 1 +.names [1612] Ng312 n4049 n2952 +00- 1 +1-1 1 +-01 1 +.names n2952 Ng29795 +0 1 +.names Ng3147 n1768 n1974 n2954 +00- 1 +1-1 1 +-01 1 +.names n493 n548 n993 n2955 +10- 1 +0-0 1 +-00 1 +.names n228 n649 n3738 n2956 +10- 1 +0-1 1 +-01 1 +.names n247 n649 n3738 n2957 +10- 1 +0-1 1 +-01 1 +.names n308 n649 n3738 n2958 +10- 1 +0-1 1 +-01 1 +.names n275 n548 n993 n2959 +10- 1 +0-0 1 +-00 1 +.names Ng853 Ng2498 n4059 n2960 +00- 1 +1-1 1 +-01 1 +.names n2960 Ng29654 +0 1 +.names [1594] Ng2495 n4059 n2961 +00- 1 +1-1 1 +-01 1 +.names n2961 Ng29653 +0 1 +.names [1612] Ng2492 n4059 n2962 +00- 1 +1-1 1 +-01 1 +.names n2962 Ng29652 +0 1 +.names n1542 Ng2396 n4062 n2963 +00- 1 +0-1 1 +-00 1 +.names n2963 Ng29651 +0 1 +.names Ng2398 n1542 n4066 n2964 +00- 1 +-01 1 +0-0 1 +.names n2964 Ng29650 +0 1 +.names n1542 Ng2397 n4069 n2965 +00- 1 +0-1 1 +-00 1 +.names n2965 Ng29649 +0 1 +.names Ng853 Ng1804 n4071 n2966 +00- 1 +1-1 1 +-01 1 +.names n2966 Ng29647 +0 1 +.names [1594] Ng1801 n4071 n2967 +00- 1 +1-1 1 +-01 1 +.names n2967 Ng29646 +0 1 +.names [1612] Ng1798 n4071 n2968 +00- 1 +1-1 1 +-01 1 +.names n2968 Ng29645 +0 1 +.names n1552 Ng1702 n4074 n2969 +00- 1 +0-1 1 +-00 1 +.names n2969 Ng29644 +0 1 +.names Ng1704 n1552 n4078 n2970 +00- 1 +-01 1 +0-0 1 +.names n2970 Ng29643 +0 1 +.names n1552 Ng1703 n4081 n2971 +00- 1 +0-1 1 +-00 1 +.names n2971 Ng29642 +0 1 +.names Ng853 Ng1110 n4083 n2972 +00- 1 +1-1 1 +-01 1 +.names n2972 Ng29640 +0 1 +.names [1594] Ng1107 n4083 n2973 +00- 1 +1-1 1 +-01 1 +.names n2973 Ng29639 +0 1 +.names [1612] Ng1104 n4083 n2974 +00- 1 +1-1 1 +-01 1 +.names n2974 Ng29638 +0 1 +.names n1562 Ng1008 n4086 n2975 +00- 1 +0-1 1 +-00 1 +.names n2975 Ng29637 +0 1 +.names Ng1010 n1562 n4090 n2976 +00- 1 +-01 1 +0-0 1 +.names n2976 Ng29636 +0 1 +.names n1562 Ng1009 n4093 n2977 +00- 1 +0-1 1 +-00 1 +.names n2977 Ng29635 +0 1 +.names Ng853 Ng423 n4095 n2978 +00- 1 +1-1 1 +-01 1 +.names n2978 Ng29633 +0 1 +.names [1594] Ng420 n4095 n2979 +00- 1 +1-1 1 +-01 1 +.names n2979 Ng29632 +0 1 +.names [1612] Ng417 n4095 n2980 +00- 1 +1-1 1 +-01 1 +.names n2980 Ng29631 +0 1 +.names n1572 Ng321 n4098 n2981 +00- 1 +0-1 1 +-00 1 +.names n2981 Ng29630 +0 1 +.names Ng323 n1572 n4102 n2982 +00- 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n2994 Ng29415 +0 1 +.names [1612] Ng408 n4113 n2995 +00- 1 +1-1 1 +-01 1 +.names n2995 Ng29414 +0 1 +.names Ng1315 Ng3102 n2728 n2996 +00- 1 +1-1 1 +-01 1 +.names n2996 Ng29165 +0 1 +.names [1603] Ng3101 n2728 n2997 +00- 1 +1-1 1 +-01 1 +.names n2997 Ng29164 +0 1 +.names [1605] Ng3100 n2728 n2998 +00- 1 +1-1 1 +-01 1 +.names n2998 Ng29163 +0 1 +.names n103 n109 n1647 n1653 n3000 +-1-0 1 +010- 1 +.names n693 n1656 n1659 n3003 +10- 1 +-01 1 +1-0 1 +.names Ng1315 Ng2694 n4116 n3004 +00- 1 +1-1 1 +-01 1 +.names n3004 Ng29161 +0 1 +.names [1603] Ng2691 n4116 n3005 +00- 1 +1-1 1 +-01 1 +.names n3005 Ng29160 +0 1 +.names [1605] Ng2688 n4116 n3006 +00- 1 +1-1 1 +-01 1 +.names n3006 Ng29159 +0 1 +.names n693 n1659 n3008 +1- 1 +-1 1 +.names n693 n1656 n2545 n3008 n3007 +01-1 1 +-111 1 +.names Ng1315 Ng2685 n4120 n3009 +00- 1 +1-1 1 +-01 1 +.names n3009 Ng29158 +0 1 +.names [1603] Ng2682 n4120 n3010 +00- 1 +1-1 1 +-01 1 +.names n3010 Ng29157 +0 1 +.names [1605] Ng2679 n4120 n3011 +00- 1 +1-1 1 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n1433 n2095 n2101 n3813 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n2097 n2101 n3811 n3813 n3815 +00-- 1 +0-0- 1 +-0-0 1 +--00 1 +.names n1424 n2102 n2104 n2105 n3818 +1-0- 1 +-10- 1 +1--1 1 +-1-1 1 +.names n1424 n2105 n2102 n2107 n3820 +1-1- 1 +-11- 1 +1--1 1 +-1-1 1 +.names n2104 n2107 n3818 n3820 n3822 +10-- 1 +1-0- 1 +-0-0 1 +--00 1 +.names [1605] Ng1315 Ng1424 Ng1423 n3824 +00-- 1 +-01- 1 +0--1 1 +--11 1 +.names n433 n358 n515 n282 n256 n317 n3826 +1----- 1 +-1---- 1 +--1--- 1 +---1-- 1 +----1- 1 +-----1 1 +.names n671 n1034 n2444 Ng1223 n3828 +1-1- 1 +-01- 1 +1--1 1 +-0-1 1 +.names n671 n1032 n2444 Ng1222 n3829 +1-1- 1 +-01- 1 +1--1 1 +-0-1 1 +.names n671 n1027 n2444 Ng1220 n3830 +1-1- 1 +-01- 1 +1--1 1 +-0-1 1 +.names n671 n1024 n2444 Ng1219 n3831 +1-1- 1 +-01- 1 +1--1 1 +-0-1 1 +.names n671 n1036 n2444 Ng1218 n3832 +1-1- 1 +-01- 1 +1--1 1 +-0-1 1 +.names n671 n1030 n2444 Ng1217 n3833 +1-1- 1 +-01- 1 +1--1 1 +-0-1 1 +.names n671 n1021 n2444 Ng1216 n3834 +1-1- 1 +-01- 1 +1--1 1 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Ng2802 n3871 +0- 1 +-1 1 +.names n2205 n2207 n2208 n3872 +1-- 1 +-1- 1 +--1 1 +.names n2214 n2215 n2217 n2219 n2220 n2210 n2212 n3872 n3873 +1------- 1 +-1------ 1 +--1----- 1 +---1---- 1 +----1--- 1 +-----1-- 1 +------1- 1 +-------1 1 +.names Ng1315 Ng2108 n3874 +0- 1 +-1 1 +.names n2221 n2223 n2225 n3875 +1-- 1 +-1- 1 +--1 1 +.names n2231 n2233 n2235 n2237 n2239 n2227 n2229 n3875 n3876 +1------- 1 +-1------ 1 +--1----- 1 +---1---- 1 +----1--- 1 +-----1-- 1 +------1- 1 +-------1 1 +.names Ng1315 Ng1414 n3877 +0- 1 +-1 1 +.names n2241 n2243 n2245 n3878 +1-- 1 +-1- 1 +--1 1 +.names n2251 n2253 n2255 n2257 n2259 n2247 n2249 n3878 n3879 +1------- 1 +-1------ 1 +--1----- 1 +---1---- 1 +----1--- 1 +-----1-- 1 +------1- 1 +-------1 1 +.names Ng1315 Ng728 n3880 +0- 1 +-1 1 +.names Ng3139 n2453 n4878 n3881 +11- 1 +-10 1 +.names [1605] Ng8284 Ng548 n3884 +1-- 1 +-1- 1 +--0 1 +.names [1605] n2727 Ng1234 n3886 +11- 1 +0-0 1 +-10 1 +.names [1605] n2728 Ng1928 n3889 +11- 1 +0-0 1 +-10 1 +.names [1605] n2729 Ng2622 n3892 +11- 1 +0-0 1 +-10 1 +.names n331 n569 n3742 n3895 +11- 1 +0-1 1 +-11 1 +.names Pg3229 Ng2612 Ng2615 n3897 +11- 1 +0-1 1 +-11 1 +.names n1191 n1193 n3898 +11 1 +00 1 +.names Ng2631 n2278 n3897 n3900 +1-- 1 +-1- 1 +--0 1 +.names Pg3229 Ng1918 Ng1921 n3904 +11- 1 +0-1 1 +-11 1 +.names n1177 n1179 n3905 +11 1 +00 1 +.names Ng1937 n2291 n3904 n3907 +1-- 1 +-1- 1 +--0 1 +.names n177 n567 n1545 n2324 n3909 +-0-1 1 +000- 1 +.names n562 n567 n1966 n3909 n3910 +1--1 1 +110- 1 +.names n555 n562 n1067 n3912 +10- 1 +-01 1 +.names n555 n562 n567 n1067 n3913 +01-0 1 +-110 1 +.names n923 n3912 n3913 n3916 +0-- 1 +-1- 1 +--1 1 +.names n173 n560 n1555 n2359 n3925 +-0-1 1 +000- 1 +.names n553 n560 n1968 n3925 n3926 +1--1 1 +110- 1 +.names n546 n553 n1064 n3928 +10- 1 +-01 1 +.names n546 n553 n560 n1064 n3929 +01-0 1 +-110 1 +.names n918 n3928 n3929 n3932 +0-- 1 +-1- 1 +--1 1 +.names n167 n551 n1565 n2394 n3941 +-0-1 1 +000- 1 +.names n544 n551 n1970 n3941 n3942 +1--1 1 +110- 1 +.names n540 n544 n1061 n3944 +10- 1 +-01 1 +.names n540 n544 n551 n1061 n3945 +01-0 1 +-110 1 +.names n913 n3944 n3945 n3948 +0-- 1 +-1- 1 +--1 1 +.names n160 n542 n1575 n2429 n3957 +-0-1 1 +000- 1 +.names n538 n542 n1972 n3957 n3958 +1--1 1 +110- 1 +.names n534 n538 n1058 n3960 +10- 1 +-01 1 +.names n534 n538 n542 n1058 n3961 +01-0 1 +-110 1 +.names n908 n3960 n3961 n3964 +0-- 1 +-1- 1 +--1 1 +.names n562 n567 Ng2257 n2320 n3973 +10-- 1 +1-0- 1 +1--1 1 +.names n553 n560 Ng2257 n2355 n3978 +10-- 1 +1-0- 1 +1--1 1 +.names n544 n551 Ng2257 n2390 n3983 +10-- 1 +1-0- 1 +1--1 1 +.names n538 n542 Ng2257 n2425 n3988 +10-- 1 +1-0- 1 +1--1 1 +.names n450 n1458 n3993 +11 1 +00 1 +.names n265 n1455 n3994 +11 1 +00 1 +.names n2327 n2020 n521 n3996 +1-- 1 +-1- 1 +--1 1 +.names n521 n2020 n2327 n3996 n3995 +0--1 1 +-001 1 +.names n400 n1466 n3997 +11 1 +00 1 +.names n237 n1463 n3998 +11 1 +00 1 +.names n2362 n2053 n499 n4000 +1-- 1 +-1- 1 +--1 1 +.names n499 n2053 n2362 n4000 n3999 +0--1 1 +-001 1 +.names n350 n1474 n4001 +11 1 +00 1 +.names n214 n1471 n4002 +11 1 +00 1 +.names n2397 n2086 n464 n4004 +1-- 1 +-1- 1 +--1 1 +.names n464 n2086 n2397 n4004 n4003 +0--1 1 +-001 1 +.names n300 n1482 n4005 +11 1 +00 1 +.names n197 n1479 n4006 +11 1 +00 1 +.names n2432 n2119 n419 n4008 +1-- 1 +-1- 1 +--1 1 +.names n419 n2119 n2432 n4008 n4007 +0--1 1 +-001 1 +.names [1603] Pg16297 Ng506 n4010 +1-- 1 +-1- 1 +--1 1 +.names Ng506 n4010 Ng507 Ng23154 +01- 1 +-11 1 +.names Pg16355 [1603] Ng23154 n4011 +10- 1 +1-1 1 +-11 1 +.names n4011 Ng1192 Ng1193 Ng27212 +10- 1 +1-1 1 +-11 1 +.names Pg16399 [1603] Ng27212 n4013 +10- 1 +1-1 1 +-11 1 +.names Pg16437 [1603] Ng29440 n4016 +00- 1 +0-0 1 +-10 1 +.names Ng298 Ng299 n4020 +1- 1 +-1 1 +.names [1594] n2929 Ng992 n4022 +11- 1 +0-0 1 +-10 1 +.names [1594] n2930 Ng1686 n4025 +11- 1 +0-0 1 +-10 1 +.names [1594] n2931 Ng2380 n4028 +11- 1 +0-0 1 +-10 1 +.names Pg3229 Ng1224 Ng1227 n4031 +11- 1 +0-1 1 +-11 1 +.names n1163 n1165 n4032 +11 1 +00 1 +.names Ng1243 n2444 n4031 n4034 +1-- 1 +-1- 1 +--0 1 +.names n923 n1507 n4037 +0- 1 +-1 1 +.names n918 n1511 n4041 +0- 1 +-1 1 +.names n913 n1515 n4045 +0- 1 +-1 1 +.names n908 n1519 n4049 +0- 1 +-1 1 +.names Pg3229 Ng538 Ng541 n4054 +11- 1 +0-1 1 +-11 1 +.names n1149 n1151 n4055 +11 1 +00 1 +.names Ng557 n2467 n4054 n4057 +1-- 1 +-1- 1 +--0 1 +.names n629 n1537 n4059 +11 1 +00 1 +.names n1546 Ng2257 n2323 n4060 +01- 1 +1-1 1 +-11 1 +.names Ng853 n4060 n4062 +11 1 +.names [1594] n4060 n4066 +11 1 +.names [1612] n4060 n4069 +11 1 +.names n615 n1547 n4071 +11 1 +00 1 +.names n1556 Ng2257 n2358 n4072 +01- 1 +1-1 1 +-11 1 +.names Ng853 n4072 n4074 +11 1 +.names [1594] n4072 n4078 +11 1 +.names [1612] n4072 n4081 +11 1 +.names n601 n1557 n4083 +11 1 +00 1 +.names n1566 Ng2257 n2393 n4084 +01- 1 +1-1 1 +-11 1 +.names Ng853 n4084 n4086 +11 1 +.names [1594] n4084 n4090 +11 1 +.names [1612] n4084 n4093 +11 1 +.names n587 n1567 n4095 +11 1 +00 1 +.names n1576 Ng2257 n2428 n4096 +01- 1 +1-1 1 +-11 1 +.names Ng853 n4096 n4098 +11 1 +.names [1594] n4096 n4102 +11 1 +.names [1612] n4096 n4105 +11 1 +.names n1593 n891 n4108 +1- 1 +-1 1 +.names n620 n4108 n4107 +01 1 +10 1 +.names n1600 n887 n4110 +1- 1 +-1 1 +.names n606 n4110 n4109 +01 1 +10 1 +.names n1607 n883 n4112 +1- 1 +-1 1 +.names n592 n4112 n4111 +01 1 +10 1 +.names n1614 n880 n4114 +1- 1 +-1 1 +.names n578 n4114 n4113 +01 1 +10 1 +.names n2547 n569 n4118 +1- 1 +-1 1 +.names n2545 n2547 n3003 n4118 n4116 +1--1 1 +-0-1 1 +--01 1 +.names n662 n2547 n3007 n4120 +10- 1 +1-0 1 +-10 1 +.names n2547 n564 n4123 +1- 1 +-1 1 +.names n2547 n2571 n3016 n4123 n4122 +0--1 1 +-1-1 1 +--01 1 +.names n659 n2547 n3020 n4125 +10- 1 +1-0 1 +-10 1 +.names n2547 n557 n4128 +1- 1 +-1 1 +.names n2547 n2595 n3029 n4128 n4127 +0--1 1 +-1-1 1 +--01 1 +.names n654 n2547 n3033 n4130 +10- 1 +1-0 1 +-10 1 +.names n2547 n548 n4133 +1- 1 +-1 1 +.names n2547 n2619 n3042 n4133 n4132 +0--1 1 +-1-1 1 +--01 1 +.names n649 n2547 n3046 n4135 +10- 1 +1-0 1 +-10 1 +.names n455 n488 n1786 n4136 +0-- 1 +-1- 1 +--1 1 +.names n405 n443 n1797 n4137 +0-- 1 +-1- 1 +--1 1 +.names n355 n393 n1807 n4138 +0-- 1 +-1- 1 +--1 1 +.names n305 n343 n1817 n4139 +0-- 1 +-1- 1 +--1 1 +.names Ng1315 n745 n4140 +0- 1 +-1 1 +.names n1640 n4150 n4142 +11 1 +.names [1603] n745 n4144 +0- 1 +-1 1 +.names [1605] n745 n4147 +0- 1 +-1 1 +.names Pg3229 n599 n4150 +11 1 +00 1 +.names n599 n611 n623 n632 n4158 +01-1 1 +0-01 1 +.names Ng853 n731 n4163 +11 1 +.names n509 n2138 n486 n4165 +111 1 +.names [1594] n731 n4167 +11 1 +.names [1612] n731 n4170 +11 1 +.names n453 n486 n509 n524 n4181 +01-1 1 +0-01 1 +.names Ng1315 n740 n4187 +0- 1 +-1 1 +.names n1675 n4197 n4189 +11 1 +.names [1603] n740 n4191 +0- 1 +-1 1 +.names [1605] n740 n4194 +0- 1 +-1 1 +.names Pg3229 n585 n4197 +11 1 +00 1 +.names n585 n597 n609 n618 n4205 +01-1 1 +0-01 1 +.names Ng853 n728 n4210 +11 1 +.names n474 n2139 n441 n4212 +111 1 +.names [1594] n728 n4214 +11 1 +.names [1612] n728 n4217 +11 1 +.names n403 n441 n474 n502 n4228 +01-1 1 +0-01 1 +.names Ng1315 n739 n4234 +0- 1 +-1 1 +.names n1710 n4244 n4236 +11 1 +.names [1603] n739 n4238 +0- 1 +-1 1 +.names [1605] n739 n4241 +0- 1 +-1 1 +.names Pg3229 n576 n4244 +11 1 +00 1 +.names n576 n583 n595 n604 n4252 +01-1 1 +0-01 1 +.names Ng853 n724 n4257 +11 1 +.names n429 n2140 n391 n4259 +111 1 +.names [1594] n724 n4261 +11 1 +.names [1612] n724 n4264 +11 1 +.names n353 n391 n429 n467 n4275 +01-1 1 +0-01 1 +.names Ng1315 n736 n4281 +0- 1 +-1 1 +.names n1745 n4291 n4283 +11 1 +.names [1603] n736 n4285 +0- 1 +-1 1 +.names [1605] n736 n4288 +0- 1 +-1 1 +.names Pg3229 n572 n4291 +11 1 +00 1 +.names n572 n574 n581 n590 n4299 +01-1 1 +0-01 1 +.names Ng853 n719 n4304 +11 1 +.names n379 n2141 n341 n4306 +111 1 +.names [1594] n719 n4308 +11 1 +.names [1612] n719 n4311 +11 1 +.names n303 n341 n379 n422 n4322 +01-1 1 +0-01 1 +.names n488 n4873 n4328 +11 1 +00 1 +.names n455 n4893 n4329 +11 1 +00 1 +.names n443 n4872 n4330 +11 1 +00 1 +.names n405 n4894 n4331 +11 1 +00 1 +.names n393 n4871 n4332 +11 1 +00 1 +.names n355 n4895 n4333 +11 1 +00 1 +.names n343 n4870 n4334 +11 1 +00 1 +.names n305 n4896 n4335 +11 1 +00 1 +.names n124 n569 Ng2584 n4336 +0-- 1 +-0- 1 +--0 1 +.names Ng853 Ng2257 n4337 +0- 1 +-0 1 +.names n153 n1545 n4339 +10 1 +.names [1594] Ng2257 n4341 +0- 1 +-0 1 +.names [1612] Ng2257 n4344 +0- 1 +-0 1 +.names n121 n564 Ng1890 n4347 +0-- 1 +-0- 1 +--0 1 +.names n144 n1555 n4349 +10 1 +.names n118 n557 Ng1196 n4352 +0-- 1 +-0- 1 +--0 1 +.names n137 n1565 n4354 +10 1 +.names n115 n548 Ng510 n4357 +0-- 1 +-0- 1 +--0 1 +.names n130 n1575 n4359 +10 1 +.names Ng13475 Ng2993 n4362 +11 1 +00 1 +.names Ng853 n2703 n4370 +0- 1 +-1 1 +.names [1594] n2703 n4373 +0- 1 +-1 1 +.names [1612] n2703 n4375 +0- 1 +-1 1 +.names Ng2185 Ng2190 Ng2195 Ng2200 n4385 +0--- 1 +-1-- 1 +--1- 1 +---0 1 +.names Ng1491 Ng1496 Ng1501 Ng1506 n4404 +0--- 1 +-1-- 1 +--1- 1 +---0 1 +.names Ng801 Ng805 Ng809 Ng813 n4423 +0--- 1 +-1-- 1 +--1- 1 +---0 1 +.names Ng113 Ng117 Ng121 Ng125 n4442 +0--- 1 +-1-- 1 +--1- 1 +---0 1 +.names n2547 n1659 n4445 +1- 1 +-1 1 +.names n2547 n693 n4446 +1- 1 +-1 1 +.names n1916 n792 n4447 +11 1 +.names n2547 n1694 n4449 +1- 1 +-1 1 +.names n2547 n689 n4450 +1- 1 +-1 1 +.names n2547 n1729 n4451 +1- 1 +-1 1 +.names n2547 n685 n4452 +1- 1 +-1 1 +.names n2547 n1764 n4453 +1- 1 +-1 1 +.names n2547 n681 n4454 +1- 1 +-1 1 +.names Ng2985 Ng2984 n4456 +1- 1 +-1 1 +.names Ng3147 Ng3120 n3881 n4456 n4455 +0-0- 1 +00-1 1 +.names [1594] Ng2257 n4503 +0- 1 +-0 1 +.names [1612] Ng2257 n4506 +0- 1 +-0 1 +.names n2724 n4897 n4644 +11 1 +00 1 +.names Ng3002 Ng3013 Ng3024 Ng3006 Ng3010 n4869 +1---- 1 +-1--- 1 +--1-- 1 +---1- 1 +----1 1 +.names n2703 Ng20567 +0 1 +.names n127 Ng2257 n2680 n4870 +1-- 1 +-0- 1 +--1 1 +.names n135 Ng2257 n2671 n4871 +1-- 1 +-0- 1 +--1 1 +.names n142 Ng2257 n2662 n4872 +1-- 1 +-0- 1 +--1 1 +.names n151 Ng2257 n2653 n4873 +1-- 1 +-0- 1 +--1 1 +.names Ng2991 Ng2992 n4878 +1- 1 +-1 1 +.names Ng2257 n2715 n4893 +0- 1 +-1 1 +.names Ng2257 n2716 n4894 +0- 1 +-1 1 +.names Ng2257 n2717 n4895 +0- 1 +-1 1 +.names Ng2257 n2718 n4896 +0- 1 +-1 1 +.names Pg3231 Ng3139 n4897 +1- 1 +-0 1 +.names Pg3231 Ng3120 n4898 +1- 1 +-0 1 +.names n2725 n4897 n4900 +01 1 +10 1 +.names n486 n524 n2138 n4904 +110 1 +.names n441 n502 n2139 n4905 +110 1 +.names n391 n467 n2140 n4906 +110 1 +.names n341 n422 n2141 n4907 +110 1 +.names [1521] Pg25442 +1 1 +.names [1521] Pg25420 +1 1 +.names [1594] Pg8167 +1 1 +.names [1605] Pg8106 +1 1 +.names [1612] Pg8087 +1 1 +.names [1594] Pg8082 +1 1 +.names [1603] Pg8030 +1 1 +.names [1612] Pg8012 +1 1 +.names [1594] Pg8007 +1 1 +.names [1612] Pg7961 +1 1 +.names [1594] Pg7956 +1 1 +.names [1612] Pg7909 +1 1 +.names [1603] Pg7487 +1 1 +.names [1605] Pg7425 +1 1 +.names [1603] Pg7390 +1 1 +.names [1603] Pg7357 +1 1 +.names [1605] Pg7302 +1 1 +.names [1594] Pg7264 +1 1 +.names [1605] Pg7229 +1 1 +.names [1603] Pg7194 +1 1 +.names [1603] Pg7161 +1 1 +.names [1594] Pg7084 +1 1 +.names [1605] Pg7052 +1 1 +.names [1594] Pg7014 +1 1 +.names [1605] Pg6979 +1 1 +.names [1603] Pg6944 +1 1 +.names [1603] Pg6911 +1 1 +.names [1612] Pg6837 +1 1 +.names [1594] Pg6782 +1 1 +.names [1605] Pg6750 +1 1 +.names [1594] Pg6712 +1 1 +.names [1605] Pg6677 +1 1 +.names [1603] Pg6642 +1 1 +.names [1612] Pg6573 +1 1 +.names [1594] Pg6518 +1 1 +.names [1605] Pg6485 +1 1 +.names [1594] Pg6447 +1 1 +.names [1612] Pg6368 +1 1 +.names [1594] Pg6313 +1 1 +.names [1612] Pg6231 +1 1 +.names [1603] Pg5796 +1 1 +.names [1605] Pg5747 +1 1 +.names [1603] Pg5738 +1 1 +.names [1605] Pg5695 +1 1 +.names [1603] Pg5686 +1 1 +.names [1605] Pg5657 +1 1 +.names [1603] Pg5648 +1 1 +.names [1609] Pg5637 +1 1 +.names [1605] Pg5629 +1 1 +.names [1609] Pg5612 +1 1 +.names [1609] Pg5595 +1 1 +.names [1612] Pg5555 +1 1 +.names [1609] Pg5549 +1 1 +.names [1612] Pg5511 +1 1 +.names [1612] Pg5472 +1 1 +.names [1612] Pg5437 +1 1 +.end diff --git a/fpga_flow/benchmarks/MCNC_big20/s38584.1.blif b/fpga_flow/benchmarks/MCNC_big20/s38584.1.blif new file mode 100644 index 000000000..a06e70db9 --- /dev/null +++ b/fpga_flow/benchmarks/MCNC_big20/s38584.1.blif @@ -0,0 +1,18005 @@ +.model TOP +.inputs Pg6753 Pg6752 Pg6751 Pg6750 Pg6749 Pg6748 Pg6747 Pg6746 Pg6745 Pg6744 \ +Pg135 Pg134 Pg127 Pg126 Pg125 Pg124 Pg120 Pg116 Pg115 Pg114 Pg113 Pg100 Pg99 \ +Pg92 Pg91 Pg90 Pg84 Pg73 Pg72 Pg64 Pg57 Pg56 Pg54 Pg53 Pg44 Pg36 Pg35 Pg5 PCLK +.outputs Pg34972 Pg34956 Pg34927 Pg34925 Pg34923 Pg34921 Pg34919 Pg34917 \ +Pg34915 Pg34913 Pg34839 Pg34788 Pg34597 Pg34437 Pg34436 Pg34435 Pg34425 \ +Pg34383 Pg34240 Pg34239 Pg34238 Pg34237 Pg34236 Pg34235 Pg34234 Pg34233 \ +Pg34232 Pg34221 Pg34201 Pg33959 Pg33950 Pg33949 Pg33948 Pg33947 Pg33946 \ +Pg33945 Pg33935 Pg33894 Pg33874 Pg33659 Pg33636 Pg33533 Pg33435 Pg33079 \ +Pg32975 Pg32454 Pg32429 Pg32185 Pg31863 Pg31862 Pg31861 Pg31860 Pg31793 \ +Pg31665 Pg31656 Pg31521 Pg30332 Pg30331 Pg30330 Pg30329 Pg30327 Pg29221 \ +Pg29220 Pg29219 Pg29218 Pg29217 Pg29216 Pg29215 Pg29214 Pg29213 Pg29212 \ +Pg29211 Pg29210 Pg28753 Pg28042 Pg28041 Pg28030 Pg27831 Pg26877 Pg26876 \ +Pg26875 Pg26801 Pg25590 Pg25589 Pg25588 Pg25587 Pg25586 Pg25585 Pg25584 \ +Pg25583 Pg25582 Pg25259 Pg25219 Pg25167 Pg25114 Pg24185 Pg24184 Pg24183 \ +Pg24182 Pg24181 Pg24180 Pg24179 Pg24178 Pg24177 Pg24176 Pg24175 Pg24174 \ +Pg24173 Pg24172 Pg24171 Pg24170 Pg24169 Pg24168 Pg24167 Pg24166 Pg24165 \ +Pg24164 Pg24163 Pg24162 Pg24161 Pg24151 Pg23759 Pg23683 Pg23652 Pg23612 \ +Pg23190 Pg23002 Pg21727 Pg21698 Pg21292 Pg21270 Pg21245 Pg21176 Pg20901 \ +Pg20899 Pg20763 Pg20654 Pg20652 Pg20557 Pg20049 Pg19357 Pg19334 Pg18881 \ +Pg18101 Pg18100 Pg18099 Pg18098 Pg18097 Pg18096 Pg18095 Pg18094 Pg18092 \ +Pg17871 Pg17845 Pg17819 Pg17813 Pg17787 Pg17778 Pg17764 Pg17760 Pg17743 \ +Pg17739 Pg17722 Pg17715 Pg17711 Pg17688 Pg17685 Pg17678 Pg17674 Pg17649 \ +Pg17646 Pg17639 Pg17607 Pg17604 Pg17580 Pg17577 Pg17519 Pg17423 Pg17404 \ +Pg17400 Pg17320 Pg17316 Pg17291 Pg16955 Pg16924 Pg16874 Pg16775 Pg16748 \ +Pg16744 Pg16722 Pg16718 Pg16693 Pg16686 Pg16659 Pg16656 Pg16627 Pg16624 \ +Pg16603 Pg14828 Pg14779 Pg14749 Pg14738 Pg14705 Pg14694 Pg14673 Pg14662 \ +Pg14635 Pg14597 Pg14518 Pg14451 Pg14421 Pg14217 Pg14201 Pg14189 Pg14167 \ +Pg14147 Pg14125 Pg14096 Pg13966 Pg13926 Pg13906 Pg13895 Pg13881 Pg13865 \ +Pg13272 Pg13259 Pg13099 Pg13085 Pg13068 Pg13049 Pg13039 Pg12923 Pg12919 \ +Pg12833 Pg12832 Pg12470 Pg12422 Pg12368 Pg12350 Pg12300 Pg12238 Pg12184 \ +Pg11770 Pg11678 Pg11447 Pg11418 Pg11388 Pg11349 Pg10527 Pg10500 Pg10306 \ +Pg10122 Pg9817 Pg9743 Pg9741 Pg9682 Pg9680 Pg9617 Pg9615 Pg9555 Pg9553 Pg9497 \ +Pg9251 Pg9048 Pg9019 Pg8920 Pg8919 Pg8918 Pg8917 Pg8916 Pg8915 Pg8870 Pg8839 \ +Pg8789 Pg8788 Pg8787 Pg8786 Pg8785 Pg8784 Pg8783 Pg8719 Pg8475 Pg8416 Pg8403 \ +Pg8398 Pg8358 Pg8353 Pg8344 Pg8342 Pg8291 Pg8283 Pg8279 Pg8277 Pg8235 Pg8215 \ +Pg8178 Pg8132 Pg7946 Pg7916 Pg7540 Pg7260 Pg7257 Pg7245 Pg7243 +.latch Ng33046 Ng5057 re PCLK 2 +.latch Ng34441 Ng2771 re PCLK 2 +.latch Ng33982 Ng1882 re PCLK 2 +.latch Ng34007 Ng2299 re PCLK 2 +.latch Ng24276 Ng4040 re PCLK 2 +.latch Ng30381 Ng2547 re PCLK 2 +.latch Pg9048 Ng559 re PCLK 2 +.latch Ng30405 Ng3243 re PCLK 2 +.latch Ng25604 Ng452 re PCLK 2 +.latch Ng30416 Ng3542 re PCLK 2 +.latch Ng30466 Ng5232 re PCLK 2 +.latch Ng25736 Ng5813 re PCLK 2 +.latch Ng34617 Ng2907 re PCLK 2 +.latch Ng33974 Ng1744 re PCLK 2 +.latch Ng30505 Ng5909 re PCLK 2 +.latch Ng33554 Ng1802 re PCLK 2 +.latch Ng30432 Ng3554 re PCLK 2 +.latch Ng33064 Ng6219 re PCLK 2 +.latch Ng34881 Ng807 re PCLK 2 +.latch Pg17715 Ng6031 re PCLK 2 +.latch Ng24216 Ng847 re PCLK 2 +.latch Ng24232 Ng976 re PCLK 2 +.latch Ng34733 Ng4172 re PCLK 2 +.latch Ng34882 Ng4372 re PCLK 2 +.latch Ng33026 Ng3512 re PCLK 2 +.latch Ng31867 Ng749 re PCLK 2 +.latch Ng25668 Ng3490 re PCLK 2 +.latch Ng24344 Pg12350 re PCLK 2 +.latch Pg8920 Ng4235 re PCLK 2 +.latch Ng33966 Ng1600 re PCLK 2 +.latch Ng33550 Ng1714 re PCLK 2 +.latch Pg16656 Pg14451 re PCLK 2 +.latch Ng30393 Ng3155 re PCLK 2 +.latch Ng29248 Ng2236 re PCLK 2 +.latch Ng4571 Ng4555 re PCLK 2 +.latch Ng24274 Ng3698 re PCLK 2 +.latch Ng33973 Ng1736 re PCLK 2 +.latch Ng30360 Ng1968 re PCLK 2 +.latch Ng34460 Ng4621 re PCLK 2 +.latch Ng30494 Ng5607 re PCLK 2 +.latch Ng30384 Ng2657 re PCLK 2 +.latch Ng24340 Pg12300 re PCLK 2 +.latch Ng29223 Ng490 re PCLK 2 +.latch Ng26881 Ng311 re PCLK 2 +.latch Ng34252 Ng772 re PCLK 2 +.latch Ng30489 Ng5587 re PCLK 2 +.latch Ng29301 Ng6177 re PCLK 2 +.latch Pg17743 Ng6377 re PCLK 2 +.latch Ng33022 Ng3167 re PCLK 2 +.latch Ng30496 Ng5615 re PCLK 2 +.latch Ng33043 Ng4567 re PCLK 2 +.latch Ng29263 Ng3457 re PCLK 2 +.latch Ng30533 Ng6287 re PCLK 2 +.latch Ng24256 Pg7946 re PCLK 2 +.latch Ng34015 Ng2563 re PCLK 2 +.latch Ng34031 Ng4776 re PCLK 2 +.latch Ng34452 Ng4593 re PCLK 2 +.latch Ng34646 Ng6199 re PCLK 2 +.latch Ng34001 Ng2295 re PCLK 2 +.latch Ng25633 Ng1384 re PCLK 2 +.latch Ng24259 Ng1339 re PCLK 2 +.latch Ng33049 Ng5180 re PCLK 2 +.latch Ng34609 Ng2844 re PCLK 2 +.latch Ng31869 Ng1024 re PCLK 2 +.latch Ng30490 Ng5591 re PCLK 2 +.latch Ng30427 Ng3598 re PCLK 2 +.latch Ng21894 Ng4264 re PCLK 2 +.latch Ng33965 Ng767 re PCLK 2 +.latch Ng34645 Ng5853 re PCLK 2 +.latch Pg16874 Pg13865 re PCLK 2 +.latch Ng33571 Ng2089 re PCLK 2 +.latch Ng34267 Ng4933 re PCLK 2 +.latch Ng26971 Ng4521 re PCLK 2 +.latch Ng34644 Ng5507 re PCLK 2 +.latch Pg16627 Pg16656 re PCLK 2 +.latch Ng30534 Ng6291 re PCLK 2 +.latch Ng33535 Ng294 re PCLK 2 +.latch Ng30498 Ng5559 re PCLK 2 +.latch Ng25728 Pg9617 re PCLK 2 +.latch Ng25743 Pg9741 re PCLK 2 +.latch Ng25684 Ng3813 re PCLK 2 +.latch Ng25613 Ng562 re PCLK 2 +.latch Ng34438 Ng608 re PCLK 2 +.latch Ng24244 Ng1205 re PCLK 2 +.latch Ng30439 Ng3909 re PCLK 2 +.latch Ng30541 Ng6259 re PCLK 2 +.latch Ng30519 Ng5905 re PCLK 2 +.latch Ng25621 Ng921 re PCLK 2 +.latch Ng34807 Ng2955 re PCLK 2 +.latch Ng25599 Ng203 re PCLK 2 +.latch Ng24235 Ng1099 re PCLK 2 +.latch Ng34036 Ng4878 re PCLK 2 +.latch Ng30476 Ng5204 re PCLK 2 +.latch Pg17580 Pg17604 re PCLK 2 +.latch Ng30429 Ng3606 re PCLK 2 +.latch Ng32997 Ng1926 re PCLK 2 +.latch Ng33063 Ng6215 re PCLK 2 +.latch Ng30424 Ng3586 re PCLK 2 +.latch Ng32977 Ng291 re PCLK 2 +.latch Ng34026 Ng4674 re PCLK 2 +.latch Ng30420 Ng3570 re PCLK 2 +.latch Pg12368 Pg9048 re PCLK 2 +.latch Pg17739 Pg17607 re PCLK 2 +.latch Ng33560 Ng1862 re PCLK 2 +.latch Ng29226 Ng676 re PCLK 2 +.latch Ng25619 Ng843 re PCLK 2 +.latch Ng34455 Ng4332 re PCLK 2 +.latch Ng30457 Ng4153 re PCLK 2 +.latch Pg14694 Pg17711 re PCLK 2 +.latch Ng33625 Ng6336 re PCLK 2 +.latch Ng34790 Ng622 re PCLK 2 +.latch Ng30414 Ng3506 re PCLK 2 +.latch Ng26966 Ng4558 re PCLK 2 +.latch Pg17649 Pg17685 re PCLK 2 +.latch Ng25656 Ng3111 re PCLK 2 +.latch Ng30390 [4430] re PCLK 2 +.latch Ng28079 Ng26936 re PCLK 2 +.latch Ng34727 Ng939 re PCLK 2 +.latch Ng25594 Ng278 re PCLK 2 +.latch Ng26963 Ng4492 re PCLK 2 +.latch Ng34034 Ng4864 re PCLK 2 +.latch Ng33541 Ng1036 re PCLK 2 +.latch Ng28093 [4427] re PCLK 2 +.latch Ng24236 Ng1178 re PCLK 2 +.latch Ng30404 Ng3239 re PCLK 2 +.latch Ng28051 Ng718 re PCLK 2 +.latch Ng29303 Ng6195 re PCLK 2 +.latch Ng26917 Ng1135 re PCLK 2 +.latch Ng33624 Ng6395 re PCLK 2 +.latch Ng24337 [4415] re PCLK 2 +.latch Ng34911 Ng554 re PCLK 2 +.latch Ng33963 Ng496 re PCLK 2 +.latch Ng34627 Ng3853 re PCLK 2 +.latch Ng29282 Ng5134 re PCLK 2 +.latch Pg17320 Pg17404 re PCLK 2 +.latch Ng25676 Pg8344 re PCLK 2 +.latch Ng33013 Ng2485 re PCLK 2 +.latch Ng32981 Ng925 re PCLK 2 +.latch Ng34993 Ng48 re PCLK 2 +.latch Ng30483 Ng5555 re PCLK 2 +.latch Pg14217 Pg14096 re PCLK 2 +.latch Ng32994 Ng1798 re PCLK 2 +.latch Ng28070 Ng4076 re PCLK 2 +.latch Ng34806 Ng2941 re PCLK 2 +.latch Ng30453 Ng3905 re PCLK 2 +.latch Ng33539 Ng763 re PCLK 2 +.latch Ng30526 Ng6255 re PCLK 2 +.latch Ng26951 Ng4375 re PCLK 2 +.latch Ng34035 Ng4871 re PCLK 2 +.latch Ng34636 Ng4722 re PCLK 2 +.latch Ng32978 Ng590 re PCLK 2 +.latch Pg17722 Pg13099 re PCLK 2 +.latch Ng30348 Ng1632 re PCLK 2 +.latch Ng24336 Pg12238 re PCLK 2 +.latch Pg8215 Ng3100 re PCLK 2 +.latch Ng24250 Ng1495 re PCLK 2 +.latch Ng29236 Ng1437 re PCLK 2 +.latch Ng29298 Ng6154 re PCLK 2 +.latch Pg10527 Ng1579 re PCLK 2 +.latch Ng30499 Ng5567 re PCLK 2 +.latch Ng33976 Ng1752 re PCLK 2 +.latch Ng32996 Ng1917 re PCLK 2 +.latch Ng30335 Ng744 re PCLK 2 +.latch Ng34637 Ng4737 re PCLK 2 +.latch Ng25694 [4661] re PCLK 2 +.latch Ng30528 Ng6267 re PCLK 2 +.latch Pg16775 Pg16659 re PCLK 2 +.latch Ng24251 Ng1442 re PCLK 2 +.latch Ng30521 Ng5965 re PCLK 2 +.latch Ng26960 Ng4477 re PCLK 2 +.latch Ng24239 Pg10500 re PCLK 2 +.latch Ng34259 Ng4643 re PCLK 2 +.latch Ng30474 Ng5264 re PCLK 2 +.latch Pg12422 Pg14779 re PCLK 2 +.latch Ng33016 Ng2610 re PCLK 2 +.latch Ng34643 Ng5160 re PCLK 2 +.latch Ng30510 Ng5933 re PCLK 2 +.latch Ng29239 Ng1454 re PCLK 2 +.latch Ng26897 Ng753 re PCLK 2 +.latch Ng34729 Ng1296 re PCLK 2 +.latch Ng34625 Ng3151 re PCLK 2 +.latch Ng34800 Ng2980 re PCLK 2 +.latch Ng24353 Ng6727 re PCLK 2 +.latch Ng33029 Ng3530 re PCLK 2 +.latch Ng33615 Ng4104 re PCLK 2 +.latch Ng24253 Ng1532 re PCLK 2 +.latch Ng24281 Pg9251 re PCLK 2 +.latch Ng33997 Ng2177 re PCLK 2 +.latch Ng34997 Ng52 re PCLK 2 +.latch Ng34263 Ng4754 re PCLK 2 +.latch Ng24237 Ng1189 re PCLK 2 +.latch Ng33584 Ng2287 re PCLK 2 +.latch Ng24280 Ng4273 re PCLK 2 +.latch Ng26920 Ng1389 re PCLK 2 +.latch Ng33548 Ng1706 re PCLK 2 +.latch Ng29296 Ng5835 re PCLK 2 +.latch Ng30338 Ng1171 re PCLK 2 +.latch Ng21895 Ng4269 re PCLK 2 +.latch Ng33588 Ng2399 re PCLK 2 +.latch Ng34041 Ng4983 re PCLK 2 +.latch Ng30495 Ng5611 re PCLK 2 +.latch Pg16744 Pg16627 re PCLK 2 +.latch Ng29279 Ng4572 re PCLK 2 +.latch Ng25655 Ng3143 re PCLK 2 +.latch Ng34795 Ng2898 re PCLK 2 +.latch Ng24269 Ng3343 re PCLK 2 +.latch Ng30403 Ng3235 re PCLK 2 +.latch Ng33042 Ng4543 re PCLK 2 +.latch Ng30419 Ng3566 re PCLK 2 +.latch Ng34023 Ng4534 re PCLK 2 +.latch Ng28090 Ng4961 re PCLK 2 +.latch Ng34642 Ng4927 re PCLK 2 +.latch Ng30370 Ng2259 re PCLK 2 +.latch Ng34448 Ng2819 re PCLK 2 +.latch Ng26946 Pg7257 re PCLK 2 +.latch Pg9617 Ng5802 re PCLK 2 +.latch Ng34610 Ng2852 re PCLK 2 +.latch Ng24209 Ng417 re PCLK 2 +.latch Ng28047 Ng681 re PCLK 2 +.latch Ng24206 Ng437 re PCLK 2 +.latch Ng26891 Ng351 re PCLK 2 +.latch Ng30504 Ng5901 re PCLK 2 +.latch Ng34798 Ng2886 re PCLK 2 +.latch Ng25669 Ng3494 re PCLK 2 +.latch Ng30480 Ng5511 re PCLK 2 +.latch Ng33027 Ng3518 re PCLK 2 +.latch Ng33972 Ng1604 re PCLK 2 +.latch Ng25697 Ng5092 re PCLK 2 +.latch Ng28099 Ng4831 re PCLK 2 +.latch Ng26947 Ng4382 re PCLK 2 +.latch Ng24350 Ng6386 re PCLK 2 +.latch Ng24210 Ng479 re PCLK 2 +.latch Ng30455 Ng3965 re PCLK 2 +.latch Ng28084 Ng4749 re PCLK 2 +.latch Ng33993 Ng2008 re PCLK 2 +.latch Pg11678 Ng736 re PCLK 2 +.latch Ng30444 Ng3933 re PCLK 2 +.latch Ng33537 Ng222 re PCLK 2 +.latch Ng25650 Ng3050 re PCLK 2 +.latch Ng25625 Ng1052 re PCLK 2 +.latch Pg17711 Pg17580 re PCLK 2 +.latch Ng30366 Ng2122 re PCLK 2 +.latch Ng33593 Ng2465 re PCLK 2 +.latch Ng30502 Ng5889 re PCLK 2 +.latch Ng33036 Ng4495 re PCLK 2 +.latch Ng25595 Pg8719 re PCLK 2 +.latch Ng34462 Ng4653 re PCLK 2 +.latch Ng33024 Ng3179 re PCLK 2 +.latch Ng33552 Ng1728 re PCLK 2 +.latch Ng34014 Ng2433 re PCLK 2 +.latch Ng29273 Ng3835 re PCLK 2 +.latch Ng25748 Ng6187 re PCLK 2 +.latch Ng34638 Ng4917 re PCLK 2 +.latch Ng30341 Ng1070 re PCLK 2 +.latch Ng26899 Ng822 re PCLK 2 +.latch Pg14673 Pg17715 re PCLK 2 +.latch Ng30336 Ng914 re PCLK 2 +.latch Pg17639 Ng5339 re PCLK 2 +.latch Ng26940 Ng4164 re PCLK 2 +.latch Ng25622 Ng969 re PCLK 2 +.latch Ng34447 Ng2807 re PCLK 2 +.latch Ng33613 Ng4054 re PCLK 2 +.latch Ng25749 Ng6191 re PCLK 2 +.latch Ng25704 Ng5077 re PCLK 2 +.latch Ng33053 Ng5523 re PCLK 2 +.latch Pg16722 Ng3680 re PCLK 2 +.latch Ng30555 Ng6637 re PCLK 2 +.latch Ng25601 Ng174 re PCLK 2 +.latch Ng33971 Ng1682 re PCLK 2 +.latch Ng26892 Ng355 re PCLK 2 +.latch Pg17400 Ng1087 re PCLK 2 +.latch Ng26915 Ng1105 re PCLK 2 +.latch Ng33008 Ng2342 re PCLK 2 +.latch Ng30538 Ng6307 re PCLK 2 +.latch Pg8344 Ng3802 re PCLK 2 +.latch Ng25750 Ng6159 re PCLK 2 +.latch Ng30369 Ng2255 re PCLK 2 +.latch Ng34446 Ng2815 re PCLK 2 +.latch Ng29230 Ng911 re PCLK 2 +.latch Ng34789 Ng43 re PCLK 2 +.latch Pg13966 Pg16775 re PCLK 2 +.latch Ng33975 Ng1748 re PCLK 2 +.latch Ng30497 Ng5551 re PCLK 2 +.latch Ng30418 Ng3558 re PCLK 2 +.latch Ng25721 Ng5499 re PCLK 2 +.latch Ng34622 Ng2960 re PCLK 2 +.latch Ng30438 Ng3901 re PCLK 2 +.latch Ng34266 Ng4888 re PCLK 2 +.latch Ng30540 Ng6251 re PCLK 2 +.latch Pg17760 Pg17649 re PCLK 2 +.latch Ng32986 Ng1373 re PCLK 2 +.latch Ng25648 Pg8215 re PCLK 2 +.latch Ng33960 Ng157 re PCLK 2 +.latch Ng34442 Ng2783 re PCLK 2 +.latch Pg8839 Ng4281 re PCLK 2 +.latch Ng30421 Ng3574 re PCLK 2 +.latch Ng33573 Ng2112 re PCLK 2 +.latch Ng34730 Ng1283 re PCLK 2 +.latch Ng24205 Ng433 re PCLK 2 +.latch Pg10122 Ng4297 re PCLK 2 +.latch Pg12350 Pg14738 re PCLK 2 +.latch Pg19357 Pg13272 re PCLK 2 +.latch Ng32979 Ng758 re PCLK 2 +.latch Ng34025 Ng4639 re PCLK 2 +.latch Ng25763 Ng6537 re PCLK 2 +.latch Ng30481 Ng5543 re PCLK 2 +.latch Pg7946 Pg8475 re PCLK 2 +.latch Ng30517 Ng5961 re PCLK 2 +.latch Ng30539 Ng6243 re PCLK 2 +.latch Ng34880 Ng632 re PCLK 2 +.latch Ng24242 Pg12919 re PCLK 2 +.latch Ng30436 Ng3889 re PCLK 2 +.latch Ng29265 Ng3476 re PCLK 2 +.latch Ng32990 Ng1664 re PCLK 2 +.latch Ng24245 Ng1246 re PCLK 2 +.latch Ng30553 Ng6629 re PCLK 2 +.latch Ng26907 Ng246 re PCLK 2 +.latch Ng24278 Ng4049 re PCLK 2 +.latch Ng26955 Pg7260 re PCLK 2 +.latch Ng24282 Ng2932 re PCLK 2 +.latch Ng29276 Ng4575 re PCLK 2 +.latch Ng31894 Ng4098 re PCLK 2 +.latch Ng33037 Ng4498 re PCLK 2 +.latch Ng26894 Ng528 re PCLK 2 +.latch Ng34994 Ng16 re PCLK 2 +.latch Ng25654 Ng3139 re PCLK 2 +.latch Ng33962 [4432] re PCLK 2 +.latch Ng34451 Ng4584 re PCLK 2 +.latch Ng34250 Ng142 re PCLK 2 +.latch Pg14597 Pg17639 re PCLK 2 +.latch Ng29295 Ng5831 re PCLK 2 +.latch Ng26905 Ng239 re PCLK 2 +.latch Ng25629 Ng1216 re PCLK 2 +.latch Ng34792 Ng2848 re PCLK 2 +.latch Ng25703 Ng5022 re PCLK 2 +.latch Pg14518 Pg16955 re PCLK 2 +.latch Ng32983 Ng1030 re PCLK 2 +.latch Pg16924 Pg13881 re PCLK 2 +.latch Ng30402 Ng3231 re PCLK 2 +.latch Ng25757 Pg9817 re PCLK 2 +.latch Pg17423 Ng1430 re PCLK 2 +.latch Pg7245 Ng4452 re PCLK 2 +.latch Ng33999 Ng2241 re PCLK 2 +.latch Ng24262 Ng1564 re PCLK 2 +.latch Ng25729 Pg9680 re PCLK 2 +.latch Pg9682 Ng6148 re PCLK 2 +.latch Ng30558 Ng6649 re PCLK 2 +.latch Ng34848 Ng110 re PCLK 2 +.latch Pg14125 Pg14147 re PCLK 2 +.latch Ng26901 Ng225 re PCLK 2 +.latch Ng26961 Ng4486 re PCLK 2 +.latch Ng33039 Ng4504 re PCLK 2 +.latch Ng33059 Ng5873 re PCLK 2 +.latch Ng31899 Ng5037 re PCLK 2 +.latch Ng33007 Ng2319 re PCLK 2 +.latch Ng25720 Ng5495 re PCLK 2 +.latch Ng21891 Pg11770 re PCLK 2 +.latch Ng30462 Ng5208 re PCLK 2 +.latch Ng30487 Ng5579 re PCLK 2 +.latch Ng33058 Ng5869 re PCLK 2 +.latch Ng24261 Ng1589 re PCLK 2 +.latch Ng25730 Ng5752 re PCLK 2 +.latch Ng30531 Ng6279 re PCLK 2 +.latch Ng30506 Ng5917 re PCLK 2 +.latch Ng34804 Ng2975 re PCLK 2 +.latch Ng25747 Ng6167 re PCLK 2 +.latch Pg11418 Pg13966 re PCLK 2 +.latch Ng33601 Ng2599 re PCLK 2 +.latch Ng26922 Ng1448 re PCLK 2 +.latch Pg14096 Pg14125 re PCLK 2 +.latch Ng29250 Ng2370 re PCLK 2 +.latch Ng30459 Ng5164 re PCLK 2 +.latch Pg8475 Ng1333 re PCLK 2 +.latch Ng33534 Ng153 re PCLK 2 +.latch Ng30543 Ng6549 re PCLK 2 +.latch Ng29275 Ng4087 re PCLK 2 +.latch Ng34030 Ng4801 re PCLK 2 +.latch Ng34980 Ng2984 re PCLK 2 +.latch Ng30451 Ng3961 re PCLK 2 +.latch Ng25627 Ng962 re PCLK 2 +.latch Ng34787 Ng101 re PCLK 2 +.latch Pg8870 Pg8918 re PCLK 2 +.latch Ng30552 Ng6625 re PCLK 2 +.latch Ng34996 Ng51 re PCLK 2 +.latch Ng30337 Ng1018 re PCLK 2 +.latch Ng24254 Pg17320 re PCLK 2 +.latch Ng24277 Ng4045 re PCLK 2 +.latch Ng29237 Ng1467 re PCLK 2 +.latch Ng30378 Ng2461 re PCLK 2 +.latch Ng33019 Ng2756 re PCLK 2 +.latch Ng33623 Ng5990 re PCLK 2 +.latch Ng29235 Ng1256 re PCLK 2 +.latch Ng31902 Ng5029 re PCLK 2 +.latch Ng29306 Ng6519 re PCLK 2 +.latch Ng33978 Ng1816 re PCLK 2 +.latch Ng26970 Ng4369 re PCLK 2 +.latch Ng29278 Ng4578 re PCLK 2 +.latch Ng34253 Ng4459 re PCLK 2 +.latch Ng29272 Ng3831 re PCLK 2 +.latch Ng33595 Ng2514 re PCLK 2 +.latch Ng33610 Ng3288 re PCLK 2 +.latch Ng33589 Ng2403 re PCLK 2 +.latch Ng34605 Ng2145 re PCLK 2 +.latch Ng30350 Ng1700 re PCLK 2 +.latch Ng25611 Ng513 re PCLK 2 +.latch Ng26936 Ng2841 re PCLK 2 +.latch Ng33619 Ng5297 re PCLK 2 +.latch Ng34022 Ng2763 re PCLK 2 +.latch Ng34033 Ng4793 re PCLK 2 +.latch Ng34726 Ng952 re PCLK 2 +.latch Ng31870 Ng1263 re PCLK 2 +.latch Ng33985 Ng1950 re PCLK 2 +.latch Ng29283 Ng5138 re PCLK 2 +.latch Ng34003 Ng2307 re PCLK 2 +.latch Pg9497 Ng5109 re PCLK 2 +.latch Ng25677 Pg8398 re PCLK 2 +.latch Ng34463 Ng4664 re PCLK 2 +.latch Ng33006 Ng2223 re PCLK 2 +.latch Ng29292 Ng5808 re PCLK 2 +.latch Ng30557 Ng6645 re PCLK 2 +.latch Ng33989 Ng2016 re PCLK 2 +.latch Ng33033 Ng3873 re PCLK 2 +.latch Pg11388 Pg13926 re PCLK 2 +.latch Ng34005 Ng2315 re PCLK 2 +.latch Ng26932 Ng2811 re PCLK 2 +.latch Ng30516 Ng5957 re PCLK 2 +.latch Ng33575 Ng2047 re PCLK 2 +.latch Ng33032 Ng3869 re PCLK 2 +.latch Pg14779 Pg17760 re PCLK 2 +.latch Ng30486 Ng5575 re PCLK 2 +.latch Ng34991 Ng46 re PCLK 2 +.latch Ng25678 Ng3752 re PCLK 2 +.latch Ng30440 Ng3917 re PCLK 2 +.latch Pg11447 Pg8783 re PCLK 2 +.latch Pg12923 Ng1585 re PCLK 2 +.latch Ng26949 Ng4388 re PCLK 2 +.latch Ng30530 Ng6275 re PCLK 2 +.latch Ng30542 Ng6311 re PCLK 2 +.latch Pg8915 Pg8916 re PCLK 2 +.latch Ng25624 Ng1041 re PCLK 2 +.latch Ng30383 Ng2595 re PCLK 2 +.latch Ng33597 Ng2537 re PCLK 2 +.latch Ng34598 [4426] re PCLK 2 +.latch Ng26957 Ng4430 re PCLK 2 +.latch Ng26967 Ng4564 re PCLK 2 +.latch Ng28102 Ng4826 re PCLK 2 +.latch Ng30524 Ng6239 re PCLK 2 +.latch Ng26903 Ng232 re PCLK 2 +.latch Ng30475 Ng5268 re PCLK 2 +.latch Ng34647 Ng6545 re PCLK 2 +.latch Ng30377 Ng2417 re PCLK 2 +.latch Ng33553 Ng1772 re PCLK 2 +.latch Ng31903 Ng5052 re PCLK 2 +.latch Ng25715 Pg9615 re PCLK 2 +.latch Ng33984 Ng1890 re PCLK 2 +.latch Ng33602 Ng2629 re PCLK 2 +.latch Ng28045 Ng572 re PCLK 2 +.latch Ng34603 Ng2130 re PCLK 2 +.latch Ng33035 Ng4108 re PCLK 2 +.latch Pg9251 Ng4308 re PCLK 2 +.latch Ng24208 Ng475 re PCLK 2 +.latch Pg8416 Ng990 re PCLK 2 +.latch Ng34990 Ng45 re PCLK 2 +.latch Ng24213 Pg12184 re PCLK 2 +.latch Ng33614 Ng3990 re PCLK 2 +.latch Ng33060 Ng5881 re PCLK 2 +.latch Ng30362 Ng1992 re PCLK 2 +.latch Ng33023 Ng3171 re PCLK 2 +.latch Ng26898 Ng812 re PCLK 2 +.latch Ng25618 Ng832 re PCLK 2 +.latch Ng30518 Ng5897 re PCLK 2 +.latch Ng6974 Ng4571 re PCLK 2 +.latch Pg11349 Pg13895 re PCLK 2 +.latch Ng26959 Ng4455 re PCLK 2 +.latch Ng34801 Ng2902 re PCLK 2 +.latch Ng26884 Ng333 re PCLK 2 +.latch Ng25600 Ng168 re PCLK 2 +.latch Ng26933 Ng2823 re PCLK 2 +.latch Ng28066 Ng3684 re PCLK 2 +.latch Ng33612 Ng3639 re PCLK 2 +.latch Pg17787 Pg14597 re PCLK 2 +.latch Ng24268 Ng3338 re PCLK 2 +.latch Ng25716 Ng5406 re PCLK 2 +.latch Ng26906 Ng269 re PCLK 2 +.latch Ng24203 Ng401 re PCLK 2 +.latch Ng24346 Ng6040 re PCLK 2 +.latch Ng24207 Ng441 re PCLK 2 +.latch Ng25701 Pg9553 re PCLK 2 +.latch Ng29269 Ng3808 re PCLK 2 +.latch Ng34255 Ng10384 re PCLK 2 +.latch Ng30450 Ng3957 re PCLK 2 +.latch Ng30456 Ng4093 re PCLK 2 +.latch Ng32991 Ng1760 re PCLK 2 +.latch Ng24348 Pg12422 re PCLK 2 +.latch Ng34249 Ng160 re PCLK 2 +.latch Ng30371 Ng2279 re PCLK 2 +.latch Ng29268 Ng3498 re PCLK 2 +.latch Ng29224 Ng586 re PCLK 2 +.latch Pg14189 Pg14201 re PCLK 2 +.latch Ng33017 Ng2619 re PCLK 2 +.latch Ng30339 Ng1183 re PCLK 2 +.latch Ng33967 Ng1608 re PCLK 2 +.latch Pg8784 Pg8785 re PCLK 2 +.latch Pg17519 Pg17577 re PCLK 2 +.latch Ng33559 Ng1779 re PCLK 2 +.latch Ng29255 Ng2652 re PCLK 2 +.latch Ng30368 Ng2193 re PCLK 2 +.latch Ng30375 Ng2393 re PCLK 2 +.latch Ng28052 Ng661 re PCLK 2 +.latch Ng28089 Ng4950 re PCLK 2 +.latch Ng33055 Ng5535 re PCLK 2 +.latch Ng30392 Ng2834 re PCLK 2 +.latch Ng30343 Ng1361 re PCLK 2 +.latch Ng30523 Ng6235 re PCLK 2 +.latch Ng24233 Ng1146 re PCLK 2 +.latch Ng33018 Ng2625 re PCLK 2 +.latch Ng32976 Ng150 re PCLK 2 +.latch Ng30349 Ng1696 re PCLK 2 +.latch Ng33067 Ng6555 re PCLK 2 +.latch Ng26900 Pg14189 re PCLK 2 +.latch Ng33034 Ng3881 re PCLK 2 +.latch Ng30551 Ng6621 re PCLK 2 +.latch Ng25667 Ng3470 re PCLK 2 +.latch Ng30452 Ng3897 re PCLK 2 +.latch Ng25612 Ng518 re PCLK 2 +.latch Ng34719 Ng538 re PCLK 2 +.latch Ng33607 Ng2606 re PCLK 2 +.latch Ng26923 Ng1472 re PCLK 2 +.latch Ng24211 Ng542 re PCLK 2 +.latch Ng33050 Ng5188 re PCLK 2 +.latch Ng24341 Ng5689 re PCLK 2 +.latch Pg19334 Pg13259 re PCLK 2 +.latch Ng24201 Ng405 re PCLK 2 +.latch Ng30463 Ng5216 re PCLK 2 +.latch Pg9743 Ng6494 re PCLK 2 +.latch Ng34464 Ng4669 re PCLK 2 +.latch Ng24243 Ng996 re PCLK 2 +.latch Ng24335 Ng4531 re PCLK 2 +.latch Ng34611 Ng2860 re PCLK 2 +.latch Ng34262 Ng4743 re PCLK 2 +.latch Ng30546 Ng6593 re PCLK 2 +.latch Ng25591 Pg8291 re PCLK 2 +.latch Pg7257 Ng4411 re PCLK 2 +.latch Ng30347 Ng1413 re PCLK 2 +.latch Ng10384 Ng26960 re PCLK 2 +.latch Pg17577 Pg13039 re PCLK 2 +.latch Ng30556 Ng6641 re PCLK 2 +.latch Ng33562 Ng1936 re PCLK 2 +.latch Ng35002 Ng55 re PCLK 2 +.latch Ng25610 Ng504 re PCLK 2 +.latch Ng33015 Ng2587 re PCLK 2 +.latch Ng31896 Ng4480 re PCLK 2 +.latch Ng34004 Ng2311 re PCLK 2 +.latch Ng30428 Ng3602 re PCLK 2 +.latch Ng30485 Ng5571 re PCLK 2 +.latch Ng30422 Ng3578 re PCLK 2 +.latch Ng25714 Pg9555 re PCLK 2 +.latch Ng29294 Ng5827 re PCLK 2 +.latch Ng30423 Ng3582 re PCLK 2 +.latch Ng30529 Ng6271 re PCLK 2 +.latch Ng34028 Ng4688 re PCLK 2 +.latch Ng33587 Ng2380 re PCLK 2 +.latch Ng30460 Ng5196 re PCLK 2 +.latch Ng30401 Ng3227 re PCLK 2 +.latch Ng33990 Ng2020 re PCLK 2 +.latch Pg16693 Pg14518 re PCLK 2 +.latch Pg17291 Pg17316 re PCLK 2 +.latch Ng29309 Ng6541 re PCLK 2 +.latch Ng30411 Ng3203 re PCLK 2 +.latch Ng33546 Ng1668 re PCLK 2 +.latch Ng28085 Ng4760 re PCLK 2 +.latch Ng26904 Ng262 re PCLK 2 +.latch Ng33556 Ng1840 re PCLK 2 +.latch Ng25722 Ng5467 re PCLK 2 +.latch Ng25605 Ng460 re PCLK 2 +.latch Ng33062 Ng6209 re PCLK 2 +.latch Ng26893 [4436] re PCLK 2 +.latch Pg12238 Pg14662 re PCLK 2 +.latch Ng28050 Ng655 re PCLK 2 +.latch Ng34626 Ng3502 re PCLK 2 +.latch Ng33583 Ng2204 re PCLK 2 +.latch Ng30472 Ng5256 re PCLK 2 +.latch Ng34454 Ng4608 re PCLK 2 +.latch Ng34850 Ng794 re PCLK 2 +.latch Pg16955 Pg13906 re PCLK 2 +.latch Pg10306 Ng4423 re PCLK 2 +.latch Ng24272 Ng3689 re PCLK 2 +.latch Pg17678 Ng5685 re PCLK 2 +.latch Ng24214 Ng703 re PCLK 2 +.latch Ng26909 Ng862 re PCLK 2 +.latch Ng30406 Ng3247 re PCLK 2 +.latch Ng33569 Ng2040 re PCLK 2 +.latch Ng34628 Ng4146 re PCLK 2 +.latch Ng34458 Ng4633 re PCLK 2 +.latch Ng24240 Pg7916 re PCLK 2 +.latch Ng34634 Ng4732 re PCLK 2 +.latch Ng25700 Pg9497 re PCLK 2 +.latch Ng29293 Ng5817 re PCLK 2 +.latch Ng33009 Ng2351 re PCLK 2 +.latch Ng33603 Ng2648 re PCLK 2 +.latch Ng24355 Ng6736 re PCLK 2 +.latch Ng34268 Ng4944 re PCLK 2 +.latch Ng25691 Ng4072 re PCLK 2 +.latch Ng26890 Pg7540 re PCLK 2 +.latch Pg7260 Ng4443 re PCLK 2 +.latch Ng29264 Ng3466 re PCLK 2 +.latch Ng28072 Ng4116 re PCLK 2 +.latch Ng31900 Ng5041 re PCLK 2 +.latch Ng26956 Ng4434 re PCLK 2 +.latch Ng29271 Ng3827 re PCLK 2 +.latch Ng29304 Ng6500 re PCLK 2 +.latch Pg13049 Pg17813 re PCLK 2 +.latch Ng29261 Ng3133 re PCLK 2 +.latch Ng28063 Ng3333 re PCLK 2 +.latch Pg13259 Ng979 re PCLK 2 +.latch Ng34027 Ng4681 re PCLK 2 +.latch Ng33961 Ng298 re PCLK 2 +.latch Ng33604 Ng2667 re PCLK 2 +.latch Pg8788 Pg8789 re PCLK 2 +.latch Ng32995 Ng1894 re PCLK 2 +.latch Ng34624 Ng2988 re PCLK 2 +.latch Ng30415 Ng3538 re PCLK 2 +.latch Ng33536 Ng301 re PCLK 2 +.latch Ng26888 Ng341 re PCLK 2 +.latch Ng28055 Ng827 re PCLK 2 +.latch Ng24238 Pg17291 re PCLK 2 +.latch Ng33600 Ng2555 re PCLK 2 +.latch Ng28105 Ng5011 re PCLK 2 +.latch Ng34721 Ng199 re PCLK 2 +.latch Ng29307 Ng6523 re PCLK 2 +.latch Ng30345 Ng1526 re PCLK 2 +.latch Ng34453 Ng4601 re PCLK 2 +.latch Ng32980 Ng854 re PCLK 2 +.latch Ng29238 Ng1484 re PCLK 2 +.latch Ng34639 Ng4922 re PCLK 2 +.latch Ng25695 Ng5080 re PCLK 2 +.latch Ng33057 Ng5863 re PCLK 2 +.latch Ng26969 Ng4581 re PCLK 2 +.latch Ng29253 Ng2518 re PCLK 2 +.latch Ng34021 Ng2567 re PCLK 2 +.latch Ng26895 Ng568 re PCLK 2 +.latch Ng30413 Ng3263 re PCLK 2 +.latch Ng30549 Ng6613 re PCLK 2 +.latch Ng24347 Ng6044 re PCLK 2 +.latch Ng25758 Ng6444 re PCLK 2 +.latch Ng34808 Ng2965 re PCLK 2 +.latch Ng30501 Ng5857 re PCLK 2 +.latch Ng33969 Ng1616 re PCLK 2 +.latch Ng34440 Ng890 re PCLK 2 +.latch Pg17607 Pg17646 re PCLK 2 +.latch Ng30433 Ng3562 re PCLK 2 +.latch Ng21900 Pg10122 re PCLK 2 +.latch Ng26921 Ng1404 re PCLK 2 +.latch Ng29270 Ng3817 re PCLK 2 +.latch Ng34878 Ng93 re PCLK 2 +.latch Ng33038 Ng4501 re PCLK 2 +.latch Ng31865 Ng287 re PCLK 2 +.latch Ng26926 Ng2724 re PCLK 2 +.latch Ng28083 Ng4704 re PCLK 2 +.latch Ng29209 Ng22 re PCLK 2 +.latch Ng34797 Ng2878 re PCLK 2 +.latch Ng30478 Ng5220 re PCLK 2 +.latch Ng34724 Ng617 re PCLK 2 +.latch Ng24212 Pg12368 re PCLK 2 +.latch Ng26883 Ng316 re PCLK 2 +.latch Ng32985 Ng1277 re PCLK 2 +.latch Ng25761 Ng6513 re PCLK 2 +.latch Ng26886 Ng336 re PCLK 2 +.latch Ng34796 Ng2882 re PCLK 2 +.latch Ng32982 Ng933 re PCLK 2 +.latch Ng33561 Ng1906 re PCLK 2 +.latch Ng26880 Ng305 re PCLK 2 +.latch Ng34992 Ng8 re PCLK 2 +.latch Ng26931 Ng2799 re PCLK 2 +.latch Pg14147 Pg14167 re PCLK 2 +.latch Pg13039 Pg17787 re PCLK 2 +.latch Ng34641 Ng4912 re PCLK 2 +.latch Ng34629 Ng4157 re PCLK 2 +.latch Ng33598 Ng2541 re PCLK 2 +.latch Ng33576 Ng2153 re PCLK 2 +.latch Ng34720 Ng550 re PCLK 2 +.latch Ng26902 Ng255 re PCLK 2 +.latch Ng29244 Ng1945 re PCLK 2 +.latch Ng30468 Ng5240 re PCLK 2 +.latch Ng26924 Ng1478 re PCLK 2 +.latch Ng33031 Ng3863 re PCLK 2 +.latch Ng29245 Ng1959 re PCLK 2 +.latch Ng29266 Ng3480 re PCLK 2 +.latch Ng30559 Ng6653 re PCLK 2 +.latch Pg14749 Pg17764 re PCLK 2 +.latch Ng34794 Ng2864 re PCLK 2 +.latch Ng28087 Ng4894 re PCLK 2 +.latch Pg14635 Pg17678 re PCLK 2 +.latch Ng30435 Ng3857 re PCLK 2 +.latch Pg16659 Pg16693 re PCLK 2 +.latch Ng25609 Ng499 re PCLK 2 +.latch Ng28057 Ng1002 re PCLK 2 +.latch Ng34439 Ng776 re PCLK 2 +.latch Pg10500 Ng1236 re PCLK 2 +.latch Ng34260 Ng4646 re PCLK 2 +.latch Ng33012 Ng2476 re PCLK 2 +.latch Ng32989 Ng1657 re PCLK 2 +.latch Ng34006 Ng2375 re PCLK 2 +.latch Ng34847 Ng63 re PCLK 2 +.latch Pg14738 Pg17739 re PCLK 2 +.latch Pg8719 Ng358 re PCLK 2 +.latch Ng26910 Ng896 re PCLK 2 +.latch Ng28043 Ng283 re PCLK 2 +.latch Ng33021 Ng3161 re PCLK 2 +.latch Ng29251 Ng2384 re PCLK 2 +.latch Pg12470 Pg14828 re PCLK 2 +.latch Ng34456 Ng4616 re PCLK 2 +.latch Ng26968 Ng4561 re PCLK 2 +.latch Ng33991 Ng2024 re PCLK 2 +.latch Pg8279 Ng3451 re PCLK 2 +.latch Ng26930 Ng2795 re PCLK 2 +.latch Ng34599 Ng613 re PCLK 2 +.latch Ng28082 Ng4527 re PCLK 2 +.latch Ng33557 Ng1844 re PCLK 2 +.latch Ng30511 Ng5937 re PCLK 2 +.latch Ng33045 Ng4546 re PCLK 2 +.latch Ng30379 Ng2523 re PCLK 2 +.latch Ng24267 Pg11349 re PCLK 2 +.latch Ng34020 Ng2643 re PCLK 2 +.latch Ng24249 Ng1489 re PCLK 2 +.latch Ng25592 Pg8358 re PCLK 2 +.latch Ng30382 Ng2551 re PCLK 2 +.latch Ng29285 Ng5156 re PCLK 2 +.latch Pg12919 [4421] re PCLK 2 +.latch Ng25662 Pg8279 re PCLK 2 +.latch Ng21896 Pg8839 re PCLK 2 +.latch Ng33563 Ng1955 re PCLK 2 +.latch Ng33622 Ng6049 re PCLK 2 +.latch Ng33582 Ng2273 re PCLK 2 +.latch Pg17871 Pg14749 re PCLK 2 +.latch Ng28086 Ng4771 re PCLK 2 +.latch Ng25744 Ng6098 re PCLK 2 +.latch Ng29262 Ng3147 re PCLK 2 +.latch Ng24270 Ng3347 re PCLK 2 +.latch Ng33581 Ng2269 re PCLK 2 +.latch Pg8358 Ng191 re PCLK 2 +.latch Ng26937 Ng2712 re PCLK 2 +.latch Ng34849 Ng626 re PCLK 2 +.latch Ng28060 Ng2729 re PCLK 2 +.latch Ng33618 Ng5357 re PCLK 2 +.latch Ng34038 Ng4991 re PCLK 2 +.latch Pg13068 Pg17819 re PCLK 2 +.latch Ng34032 Ng4709 re PCLK 2 +.latch Ng34803 Ng2927 re PCLK 2 +.latch Ng34459 Ng4340 re PCLK 2 +.latch Ng30509 Ng5929 re PCLK 2 +.latch Ng34640 Ng4907 re PCLK 2 +.latch Pg14421 Pg16874 re PCLK 2 +.latch Ng28069 Ng4035 re PCLK 2 +.latch Ng21899 Ng2946 re PCLK 2 +.latch Ng31868 Ng918 re PCLK 2 +.latch Ng26938 Ng4082 re PCLK 2 +.latch Ng25756 Pg9743 re PCLK 2 +.latch Ng30363 Ng2036 re PCLK 2 +.latch Ng30334 Ng577 re PCLK 2 +.latch Ng33970 Ng1620 re PCLK 2 +.latch Ng30391 Ng2831 re PCLK 2 +.latch Ng25615 Ng667 re PCLK 2 +.latch Ng33540 Ng930 re PCLK 2 +.latch Ng30445 Ng3937 re PCLK 2 +.latch Ng25617 Ng817 re PCLK 2 +.latch Ng24247 Ng1249 re PCLK 2 +.latch Ng24215 Ng837 re PCLK 2 +.latch Pg14451 Pg16924 re PCLK 2 +.latch Ng33964 Ng599 re PCLK 2 +.latch Ng25719 Ng5475 re PCLK 2 +.latch Ng29228 Ng739 re PCLK 2 +.latch Ng30514 Ng5949 re PCLK 2 +.latch Ng33627 Ng6682 re PCLK 2 +.latch Ng24231 Ng904 re PCLK 2 +.latch Ng34615 Ng2873 re PCLK 2 +.latch Ng30356 Ng1854 re PCLK 2 +.latch Ng25696 Ng5084 re PCLK 2 +.latch Ng30493 Ng5603 re PCLK 2 +.latch Pg8917 Pg8870 re PCLK 2 +.latch Ng33594 Ng2495 re PCLK 2 +.latch Ng34009 Ng2437 re PCLK 2 +.latch Ng30365 Ng2102 re PCLK 2 +.latch Ng33004 Ng2208 re PCLK 2 +.latch Ng34018 Ng2579 re PCLK 2 +.latch Ng25685 Ng4064 re PCLK 2 +.latch Ng34040 Ng4899 re PCLK 2 +.latch Ng25639 Ng2719 re PCLK 2 +.latch Ng34029 Ng4785 re PCLK 2 +.latch Ng30488 Ng5583 re PCLK 2 +.latch Ng34600 Ng781 re PCLK 2 +.latch Ng29300 Ng6173 re PCLK 2 +.latch Pg14705 Pg17743 re PCLK 2 +.latch Ng34802 Ng2917 re PCLK 2 +.latch Ng25614 Ng686 re PCLK 2 +.latch Ng28058 Ng1252 re PCLK 2 +.latch Ng29225 Ng671 re PCLK 2 +.latch Ng33580 Ng2265 re PCLK 2 +.latch Ng30532 Ng6283 re PCLK 2 +.latch Pg17845 Pg14705 re PCLK 2 +.latch Pg17674 Pg17519 re PCLK 2 +.latch Pg8783 Pg8784 re PCLK 2 +.latch Ng33054 Ng5527 re PCLK 2 +.latch Ng26962 Ng4489 re PCLK 2 +.latch Ng33564 Ng1974 re PCLK 2 +.latch Ng32984 Ng1270 re PCLK 2 +.latch Ng34039 Ng4966 re PCLK 2 +.latch Ng33065 Ng6227 re PCLK 2 +.latch Ng30443 Ng3929 re PCLK 2 +.latch Ng29291 Ng5503 re PCLK 2 +.latch Ng24279 Ng4242 re PCLK 2 +.latch Ng30508 Ng5925 re PCLK 2 +.latch Ng29232 Ng1124 re PCLK 2 +.latch Ng34269 Ng4955 re PCLK 2 +.latch Ng30464 Ng5224 re PCLK 2 +.latch Ng33988 Ng2012 re PCLK 2 +.latch Ng30522 Ng6203 re PCLK 2 +.latch Ng25708 Ng5120 re PCLK 2 +.latch Pg14662 Pg17674 re PCLK 2 +.latch Ng30374 Ng2389 re PCLK 2 +.latch Ng26953 Ng4438 re PCLK 2 +.latch Ng34008 Ng2429 re PCLK 2 +.latch Ng34444 Ng2787 re PCLK 2 +.latch Ng34731 Ng1287 re PCLK 2 +.latch Ng33606 Ng2675 re PCLK 2 +.latch Ng24334 [4507] re PCLK 2 +.latch Ng34265 Ng4836 re PCLK 2 +.latch Ng30340 Ng1199 re PCLK 2 +.latch Ng24257 Pg19357 re PCLK 2 +.latch Ng30482 Ng5547 re PCLK 2 +.latch Ng34604 Ng2138 re PCLK 2 +.latch Pg13926 Pg16744 re PCLK 2 +.latch Ng33591 Ng2338 re PCLK 2 +.latch Pg8918 Pg8919 re PCLK 2 +.latch Ng30525 Ng6247 re PCLK 2 +.latch Ng26929 Ng2791 re PCLK 2 +.latch Ng30448 Ng3949 re PCLK 2 +.latch Ng34602 Ng1291 re PCLK 2 +.latch Ng30513 Ng5945 re PCLK 2 +.latch Ng30469 Ng5244 re PCLK 2 +.latch Ng33608 Ng2759 re PCLK 2 +.latch Ng33626 Ng6741 re PCLK 2 +.latch Ng34725 Ng785 re PCLK 2 +.latch Ng30342 Ng1259 re PCLK 2 +.latch Ng29267 Ng3484 re PCLK 2 +.latch Ng25593 Ng209 re PCLK 2 +.latch Ng30548 Ng6609 re PCLK 2 +.latch Ng33052 Ng5517 re PCLK 2 +.latch Ng34012 Ng2449 re PCLK 2 +.latch Ng34017 Ng2575 re PCLK 2 +.latch [4507] Ng65 re PCLK 2 +.latch Ng24263 Ng2715 re PCLK 2 +.latch Ng26912 Ng936 re PCLK 2 +.latch Ng30364 Ng2098 re PCLK 2 +.latch Ng34254 Ng4462 re PCLK 2 +.latch Ng34251 Ng604 re PCLK 2 +.latch Ng30560 Ng6589 re PCLK 2 +.latch Ng33983 Ng1886 re PCLK 2 +.latch Pg13085 Pg17845 re PCLK 2 +.latch Pg13099 Pg17871 re PCLK 2 +.latch Ng24204 Ng429 re PCLK 2 +.latch Ng33980 Ng1870 re PCLK 2 +.latch Ng34631 Ng4249 re PCLK 2 +.latch Ng29243 Ng1825 re PCLK 2 +.latch Ng25623 Ng1008 re PCLK 2 +.latch Ng26950 Ng4392 re PCLK 2 +.latch Ng30431 Ng3546 re PCLK 2 +.latch Ng30467 Ng5236 re PCLK 2 +.latch Ng30353 Ng1768 re PCLK 2 +.latch Ng34467 Ng4854 re PCLK 2 +.latch Ng30442 Ng3925 re PCLK 2 +.latch Ng29305 Ng6509 re PCLK 2 +.latch Ng25616 Ng732 re PCLK 2 +.latch Ng29252 Ng2504 re PCLK 2 +.latch Pg13272 Ng1322 re PCLK 2 +.latch Ng6972 Ng4520 re PCLK 2 +.latch Pg8916 Pg8917 re PCLK 2 +.latch Ng33003 Ng2185 re PCLK 2 +.latch Ng34613 Ng37 re PCLK 2 +.latch Pg16748 Ng4031 re PCLK 2 +.latch Ng33570 Ng2070 re PCLK 2 +.latch [4661] [4658] re PCLK 2 +.latch Ng34734 Ng4176 re PCLK 2 +.latch Ng24275 Pg11418 re PCLK 2 +.latch Pg7243 Ng4405 re PCLK 2 +.latch Pg14167 Ng872 re PCLK 2 +.latch Ng29302 Ng6181 re PCLK 2 +.latch Ng24349 Ng6381 re PCLK 2 +.latch Ng34264 Ng4765 re PCLK 2 +.latch Ng30484 Ng5563 re PCLK 2 +.latch Ng25634 Ng1395 re PCLK 2 +.latch Ng33567 Ng1913 re PCLK 2 +.latch Ng33585 Ng2331 re PCLK 2 +.latch Ng30527 Ng6263 re PCLK 2 +.latch Ng34995 Ng50 re PCLK 2 +.latch Ng30447 Ng3945 re PCLK 2 +.latch Pg7540 Ng347 re PCLK 2 +.latch Ng34256 Ng4473 re PCLK 2 +.latch Ng25630 Ng1266 re PCLK 2 +.latch Ng29290 Ng5489 re PCLK 2 +.latch Ng29227 Ng714 re PCLK 2 +.latch Ng31872 Ng2748 re PCLK 2 +.latch Ng29287 Ng5471 re PCLK 2 +.latch Ng31897 Ng4540 re PCLK 2 +.latch Pg17764 Ng6723 re PCLK 2 +.latch Ng30562 Ng6605 re PCLK 2 +.latch Ng34011 Ng2445 re PCLK 2 +.latch Ng33996 Ng2173 re PCLK 2 +.latch Ng21898 Pg9019 re PCLK 2 +.latch Ng33014 Ng2491 re PCLK 2 +.latch Ng34465 Ng4849 re PCLK 2 +.latch Ng33995 Ng2169 re PCLK 2 +.latch Ng30372 Ng2283 re PCLK 2 +.latch Ng30545 Ng6585 re PCLK 2 +.latch Ng30389 [4428] re PCLK 2 +.latch Ng33590 Ng2407 re PCLK 2 +.latch Ng34616 Ng2868 re PCLK 2 +.latch Ng26927 Ng2767 re PCLK 2 +.latch Ng32992 Ng1783 re PCLK 2 +.latch Pg13895 Pg16718 re PCLK 2 +.latch Ng25631 Ng1312 re PCLK 2 +.latch Ng30477 Ng5212 re PCLK 2 +.latch Ng34632 Ng4245 re PCLK 2 +.latch Ng28046 Ng645 re PCLK 2 +.latch Pg9019 Ng4291 re PCLK 2 +.latch Ng26896 [4435] re PCLK 2 +.latch Ng25602 Ng182 re PCLK 2 +.latch Ng26916 Ng1129 re PCLK 2 +.latch Ng33578 Ng2227 re PCLK 2 +.latch Pg8787 Pg8788 re PCLK 2 +.latch Ng33579 Ng2246 re PCLK 2 +.latch Ng30354 Ng1830 re PCLK 2 +.latch Ng30425 Ng3590 re PCLK 2 +.latch Ng24200 Ng392 re PCLK 2 +.latch Ng33544 Ng1592 re PCLK 2 +.latch Ng25764 Ng6505 re PCLK 2 +.latch Ng24246 Ng1221 re PCLK 2 +.latch Ng30507 Ng5921 re PCLK 2 +.latch Ng26889 [4431] re PCLK 2 +.latch Ng30333 Ng146 re PCLK 2 +.latch Pg8291 Ng218 re PCLK 2 +.latch Ng32998 Ng1932 re PCLK 2 +.latch Ng32987 Ng1624 re PCLK 2 +.latch Ng25702 Ng5062 re PCLK 2 +.latch Ng29286 Ng5462 re PCLK 2 +.latch Ng34606 Ng2689 re PCLK 2 +.latch Ng33070 Ng6573 re PCLK 2 +.latch Ng29240 Ng1677 re PCLK 2 +.latch Ng32999 Ng2028 re PCLK 2 +.latch Ng33605 Ng2671 re PCLK 2 +.latch Ng24255 Pg10527 re PCLK 2 +.latch Ng26945 Pg7243 re PCLK 2 +.latch Ng33558 Ng1848 re PCLK 2 +.latch Ng25699 [4434] re PCLK 2 +.latch Ng29289 Ng5485 re PCLK 2 +.latch Ng30388 Ng2741 re PCLK 2 +.latch Pg12184 Pg11678 re PCLK 2 +.latch Ng29254 Ng2638 re PCLK 2 +.latch Ng28074 Ng4122 re PCLK 2 +.latch Ng34450 Ng4322 re PCLK 2 +.latch Ng30512 Ng5941 re PCLK 2 +.latch Ng33572 Ng2108 re PCLK 2 +.latch Pg17646 Pg13068 re PCLK 2 +.latch Ng25 Ng25 re PCLK 2 +.latch Ng33551 Ng1644 re PCLK 2 +.latch Ng33538 Ng595 re PCLK 2 +.latch Ng33005 Ng2217 re PCLK 2 +.latch Ng24248 Ng1319 re PCLK 2 +.latch Ng33002 Ng2066 re PCLK 2 +.latch Ng24234 Ng1152 re PCLK 2 +.latch Ng30471 Ng5252 re PCLK 2 +.latch Ng34000 Ng2165 re PCLK 2 +.latch Ng34016 Ng2571 re PCLK 2 +.latch Ng33048 Ng5176 re PCLK 2 +.latch Pg17819 Pg14673 re PCLK 2 +.latch Ng25628 Ng1211 re PCLK 2 +.latch Ng26934 Ng2827 re PCLK 2 +.latch Pg14201 Pg14217 re PCLK 2 +.latch Ng34468 Ng4859 re PCLK 2 +.latch Ng24202 Ng424 re PCLK 2 +.latch Ng33542 Ng1274 re PCLK 2 +.latch Pg17404 Pg17423 re PCLK 2 +.latch Pg33435 Ng85 re PCLK 2 +.latch Ng34445 Ng2803 re PCLK 2 +.latch Ng33555 Ng1821 re PCLK 2 +.latch Ng34013 Ng2509 re PCLK 2 +.latch Ng28091 Ng5073 re PCLK 2 +.latch Ng26919 Ng1280 re PCLK 2 +.latch [4658] [4651] re PCLK 2 +.latch Pg17685 Pg13085 re PCLK 2 +.latch Ng30554 Ng6633 re PCLK 2 +.latch Ng29281 Ng5124 re PCLK 2 +.latch Pg17316 Pg17400 re PCLK 2 +.latch Ng30537 Ng6303 re PCLK 2 +.latch Ng28092 Ng5069 re PCLK 2 +.latch Ng34732 Ng2994 re PCLK 2 +.latch Ng28049 Ng650 re PCLK 2 +.latch Ng33545 Ng1636 re PCLK 2 +.latch Ng30441 Ng3921 re PCLK 2 +.latch Ng29247 Ng2093 re PCLK 2 +.latch Ng24354 Ng6732 re PCLK 2 +.latch Ng25636 Ng1306 re PCLK 2 +.latch Ng26914 Ng1061 re PCLK 2 +.latch Ng25670 Ng3462 re PCLK 2 +.latch Ng33998 Ng2181 re PCLK 2 +.latch Ng25626 Ng956 re PCLK 2 +.latch Ng33977 Ng1756 re PCLK 2 +.latch Ng29297 Ng5849 re PCLK 2 +.latch Ng28071 Ng4112 re PCLK 2 +.latch Ng30387 Ng2685 re PCLK 2 +.latch Ng33577 Ng2197 re PCLK 2 +.latch Ng33592 Ng2421 re PCLK 2 +.latch Ng26913 Ng1046 re PCLK 2 +.latch Ng28044 Ng482 re PCLK 2 +.latch Ng26948 Ng4401 re PCLK 2 +.latch Ng30344 Ng1514 re PCLK 2 +.latch Ng26885 Ng329 re PCLK 2 +.latch Ng33069 Ng6565 re PCLK 2 +.latch Ng34621 Ng2950 re PCLK 2 +.latch Ng28059 Ng1345 re PCLK 2 +.latch Ng25762 Ng6533 re PCLK 2 +.latch Pg16624 Pg14421 re PCLK 2 +.latch Ng34633 Ng4727 re PCLK 2 +.latch Ng24352 Pg12470 re PCLK 2 +.latch Ng26925 Ng1536 re PCLK 2 +.latch Ng30446 Ng3941 re PCLK 2 +.latch Ng25597 Ng370 re PCLK 2 +.latch Ng24342 Ng5694 re PCLK 2 +.latch Ng30357 Ng1858 re PCLK 2 +.latch Ng26908 Ng446 re PCLK 2 +.latch Ng30399 Ng3219 re PCLK 2 +.latch Ng29242 Ng1811 re PCLK 2 +.latch Ng30547 Ng6601 re PCLK 2 +.latch Ng34010 Ng2441 re PCLK 2 +.latch Ng33986 Ng1874 re PCLK 2 +.latch Ng34257 Ng4349 re PCLK 2 +.latch Ng30544 Ng6581 re PCLK 2 +.latch Ng30561 Ng6597 re PCLK 2 +.latch Ng30430 Ng3610 re PCLK 2 +.latch Ng34799 Ng2890 re PCLK 2 +.latch Ng33565 Ng1978 re PCLK 2 +.latch Ng33968 Ng1612 re PCLK 2 +.latch Ng34879 Ng112 re PCLK 2 +.latch Ng34793 Ng2856 re PCLK 2 +.latch Ng33566 Ng1982 re PCLK 2 +.latch Pg17688 Pg17722 re PCLK 2 +.latch Ng30465 Ng5228 re PCLK 2 +.latch Ng28073 Ng4119 re PCLK 2 +.latch Ng24351 Ng6390 re PCLK 2 +.latch Ng30346 Ng1542 re PCLK 2 +.latch Ng21893 Ng4258 re PCLK 2 +.latch [4651] Ng4818 re PCLK 2 +.latch Ng31904 Ng5033 re PCLK 2 +.latch Ng34635 Ng4717 re PCLK 2 +.latch Ng25637 Ng1554 re PCLK 2 +.latch Ng29274 Ng3849 re PCLK 2 +.latch Pg14828 Pg17778 re PCLK 2 +.latch Ng30396 Ng3199 re PCLK 2 +.latch Ng25735 Ng5845 re PCLK 2 +.latch Ng34037 Ng4975 re PCLK 2 +.latch Ng34791 Ng790 re PCLK 2 +.latch Ng30520 Ng5913 re PCLK 2 +.latch Ng30358 Ng1902 re PCLK 2 +.latch Ng29299 Ng6163 re PCLK 2 +.latch Ng28081 Ng4125 re PCLK 2 +.latch Ng28096 Ng4821 re PCLK 2 +.latch Ng28088 Ng4939 re PCLK 2 +.latch Ng24241 Pg19334 re PCLK 2 +.latch Ng30397 Ng3207 re PCLK 2 +.latch Ng4520 Ng4483 re PCLK 2 +.latch Ng30409 Ng3259 re PCLK 2 +.latch Ng29284 Ng5142 re PCLK 2 +.latch Ng30470 Ng5248 re PCLK 2 +.latch Ng30367 Ng2126 re PCLK 2 +.latch Ng24273 Ng3694 re PCLK 2 +.latch Ng29288 Ng5481 re PCLK 2 +.latch Ng30359 Ng1964 re PCLK 2 +.latch Ng25698 Ng5097 re PCLK 2 +.latch Ng30398 Ng3215 re PCLK 2 +.latch Pg13906 Pg16748 re PCLK 2 +.latch Pg33079 Ng111 re PCLK 2 +.latch Ng26952 Ng4427 re PCLK 2 +.latch Ng26928 Ng2779 re PCLK 2 +.latch Pg8785 Pg8786 re PCLK 2 +.latch Ng26954 Pg7245 re PCLK 2 +.latch Ng30351 Ng1720 re PCLK 2 +.latch Ng31871 Ng1367 re PCLK 2 +.latch Pg9553 Ng5112 re PCLK 2 +.latch Ng26939 Ng4145 re PCLK 2 +.latch Ng33994 Ng2161 re PCLK 2 +.latch Ng25596 Ng376 re PCLK 2 +.latch Ng33586 Ng2361 re PCLK 2 +.latch Ng21901 Pg11447 re PCLK 2 +.latch Ng31866 Ng582 re PCLK 2 +.latch Ng33000 Ng2051 re PCLK 2 +.latch Ng26918 Ng1193 re PCLK 2 +.latch Ng30373 Ng2327 re PCLK 2 +.latch Ng28056 Ng907 re PCLK 2 +.latch Ng34601 Ng947 re PCLK 2 +.latch Ng30355 Ng1834 re PCLK 2 +.latch Ng30426 Ng3594 re PCLK 2 +.latch Ng34805 Ng2999 re PCLK 2 +.latch Ng34002 Ng2303 re PCLK 2 +.latch Pg17778 Pg17688 re PCLK 2 +.latch Ng28053 Ng699 re PCLK 2 +.latch Ng29229 Ng723 re PCLK 2 +.latch Ng33620 Ng5703 re PCLK 2 +.latch Ng34722 Ng546 re PCLK 2 +.latch Ng33599 Ng2472 re PCLK 2 +.latch Ng30515 Ng5953 re PCLK 2 +.latch Ng25649 Pg8277 re PCLK 2 +.latch Ng33979 Ng1740 re PCLK 2 +.latch Ng30417 Ng3550 re PCLK 2 +.latch Ng25683 Ng3845 re PCLK 2 +.latch Ng33574 Ng2116 re PCLK 2 +.latch Pg17813 Pg14635 re PCLK 2 +.latch Ng30410 Ng3195 re PCLK 2 +.latch Ng30454 Ng3913 re PCLK 2 +.latch Ng34024 Pg10306 re PCLK 2 +.latch Ng33547 Ng1687 re PCLK 2 +.latch Ng30386 Ng2681 re PCLK 2 +.latch Ng33596 Ng2533 re PCLK 2 +.latch Ng26887 Ng324 re PCLK 2 +.latch Ng34607 Ng2697 re PCLK 2 +.latch Ng31895 Ng4417 re PCLK 2 +.latch Ng33068 Ng6561 re PCLK 2 +.latch Ng29233 Ng1141 re PCLK 2 +.latch Ng24258 Pg12923 re PCLK 2 +.latch Ng30376 Ng2413 re PCLK 2 +.latch Ng33549 Ng1710 re PCLK 2 +.latch Ng29308 Ng6527 re PCLK 2 +.latch Ng30408 Ng3255 re PCLK 2 +.latch Ng29241 Ng1691 re PCLK 2 +.latch Ng34620 Ng2936 re PCLK 2 +.latch Ng33621 Ng5644 re PCLK 2 +.latch Ng25707 Ng5152 re PCLK 2 +.latch Ng24339 Ng5352 re PCLK 2 +.latch Pg11770 Pg8915 re PCLK 2 +.latch Ng34443 Ng2775 re PCLK 2 +.latch Ng34619 Ng2922 re PCLK 2 +.latch Ng29234 Ng1111 re PCLK 2 +.latch Ng30503 Ng5893 re PCLK 2 +.latch Pg16718 Pg16603 re PCLK 2 +.latch Ng30550 Ng6617 re PCLK 2 +.latch Ng33001 Ng2060 re PCLK 2 +.latch Ng33040 Ng4512 re PCLK 2 +.latch Ng30492 Ng5599 re PCLK 2 +.latch Ng25664 Ng3401 re PCLK 2 +.latch Ng26944 Ng4366 re PCLK 2 +.latch Pg13881 Pg16722 re PCLK 2 +.latch Ng34614 [4433] re PCLK 2 +.latch Ng29260 Ng3129 re PCLK 2 +.latch Pg16686 Ng3329 re PCLK 2 +.latch Ng33047 Ng5170 re PCLK 2 +.latch Ng25692 Ng26959 re PCLK 2 +.latch Ng25733 Ng5821 re PCLK 2 +.latch Ng30536 Ng6299 re PCLK 2 +.latch Pg7916 Pg8416 re PCLK 2 +.latch Ng29246 Ng2079 re PCLK 2 +.latch Ng34261 Ng4698 re PCLK 2 +.latch Ng33611 Ng3703 re PCLK 2 +.latch Ng25638 Ng1559 re PCLK 2 +.latch Ng34728 Ng943 re PCLK 2 +.latch Ng29222 Ng411 re PCLK 2 +.latch Ng25742 Pg9682 re PCLK 2 +.latch Ng30449 Ng3953 re PCLK 2 +.latch Ng34608 Ng2704 re PCLK 2 +.latch Ng24345 Ng6035 re PCLK 2 +.latch Ng25635 Ng1300 re PCLK 2 +.latch Ng25686 Ng4057 re PCLK 2 +.latch Ng30461 Ng5200 re PCLK 2 +.latch Ng34466 Ng4843 re PCLK 2 +.latch Ng31901 Ng5046 re PCLK 2 +.latch Ng29249 Ng2250 re PCLK 2 +.latch Ng26882 Ng26885 re PCLK 2 +.latch Ng33041 Ng4549 re PCLK 2 +.latch Ng33011 Ng2453 re PCLK 2 +.latch Ng25734 Ng5841 re PCLK 2 +.latch Pg12300 Pg14694 re PCLK 2 +.latch Ng34618 Ng2912 re PCLK 2 +.latch Ng33010 Ng2357 re PCLK 2 +.latch Pg8919 Pg8920 re PCLK 2 +.latch Ng31864 Ng164 re PCLK 2 +.latch Ng34630 Ng4253 re PCLK 2 +.latch Ng31898 Ng5016 re PCLK 2 +.latch Ng25653 Ng3119 re PCLK 2 +.latch Ng25632 Ng1351 re PCLK 2 +.latch Ng32988 Ng1648 re PCLK 2 +.latch Ng33616 Ng6972 re PCLK 2 +.latch Ng29280 Ng5115 re PCLK 2 +.latch Ng33609 Ng3352 re PCLK 2 +.latch Ng30563 Ng6657 re PCLK 2 +.latch Ng33044 Ng4552 re PCLK 2 +.latch Ng30437 Ng3893 re PCLK 2 +.latch Ng30412 Ng3211 re PCLK 2 +.latch Pg17604 Pg13049 re PCLK 2 +.latch Pg16603 Pg16624 re PCLK 2 +.latch Ng30491 Ng5595 re PCLK 2 +.latch Ng30434 Ng3614 re PCLK 2 +.latch Ng34612 Ng2894 re PCLK 2 +.latch Ng29259 Ng3125 re PCLK 2 +.latch Pg13865 Pg16686 re PCLK 2 +.latch Ng25681 Ng3821 re PCLK 2 +.latch Ng25687 Ng4141 re PCLK 2 +.latch Ng33617 Ng6974 re PCLK 2 +.latch Ng30479 Ng5272 re PCLK 2 +.latch Ng29256 Ng2735 re PCLK 2 +.latch Ng28054 Ng728 re PCLK 2 +.latch Ng30535 Ng6295 re PCLK 2 +.latch Ng30385 Ng2661 re PCLK 2 +.latch Ng30361 Ng1988 re PCLK 2 +.latch Ng25705 Ng5128 re PCLK 2 +.latch Ng24260 Ng1548 re PCLK 2 +.latch Ng29257 Ng3106 re PCLK 2 +.latch Ng34461 Ng4659 re PCLK 2 +.latch Ng34258 Ng4358 re PCLK 2 +.latch Ng32993 Ng1792 re PCLK 2 +.latch Ng33992 Ng2084 re PCLK 2 +.latch Ng30394 Ng3187 re PCLK 2 +.latch Ng34449 Ng4311 re PCLK 2 +.latch Ng34019 Ng2583 re PCLK 2 +.latch Ng21726 Ng3003 re PCLK 2 +.latch Ng29231 Ng1094 re PCLK 2 +.latch Ng25682 Ng3841 re PCLK 2 +.latch Ng21897 Ng4284 re PCLK 2 +.latch Ng30395 Ng3191 re PCLK 2 +.latch Ng21892 Ng4239 re PCLK 2 +.latch Pg8789 Ng4180 re PCLK 2 +.latch Ng28048 Ng691 re PCLK 2 +.latch Ng34723 Ng534 re PCLK 2 +.latch Ng25598 Ng385 re PCLK 2 +.latch Ng33987 Ng2004 re PCLK 2 +.latch Ng30380 Ng2527 re PCLK 2 +.latch Pg9555 Ng5456 re PCLK 2 +.latch Ng26965 Ng4420 re PCLK 2 +.latch Ng25706 Ng5148 re PCLK 2 +.latch Ng30458 Ng4507 re PCLK 2 +.latch Ng24338 Ng5348 re PCLK 2 +.latch Ng30400 Ng3223 re PCLK 2 +.latch Ng34623 Ng2970 re PCLK 2 +.latch Ng24343 Ng5698 re PCLK 2 +.latch Ng30473 Ng5260 re PCLK 2 +.latch Ng24252 Ng1521 re PCLK 2 +.latch Ng33028 Ng3522 re PCLK 2 +.latch Ng29258 Ng3115 re PCLK 2 +.latch Ng30407 Ng3251 re PCLK 2 +.latch Ng26958 Pg12832 re PCLK 2 +.latch Ng34457 Ng4628 re PCLK 2 +.latch Ng33568 Ng1996 re PCLK 2 +.latch Ng25663 Pg8342 re PCLK 2 +.latch Ng26964 Ng4515 re PCLK 2 +.latch Pg8786 Pg8787 re PCLK 2 +.latch Ng34735 Ng4300 re PCLK 2 +.latch Ng30352 Ng1724 re PCLK 2 +.latch Ng33543 Ng1379 re PCLK 2 +.latch Ng24271 Pg11388 re PCLK 2 +.latch Ng33981 Ng1878 re PCLK 2 +.latch Ng30500 Ng5619 re PCLK 2 +.latch Ng34786 Ng71 re PCLK 2 +.latch Ng29277 [4437] re PCLK 2 +.names n4486 Ng22 Pg34972 +0- 1 +-0 1 +.names Ng4369 Ng4366 n1368 [4366] +11- 1 +1-1 1 +.names n1121 Ng22 Pg34927 +0- 1 +-0 1 +.names n1141 Ng22 Pg34925 +0- 1 +-0 1 +.names n204 Ng22 Pg34923 +0- 1 +-0 1 +.names n1119 Ng22 Pg34921 +0- 1 +-0 1 +.names n1092 Ng22 Pg34919 +0- 1 +-0 1 +.names n981 Ng22 Pg34917 +0- 1 +-0 1 +.names n1132 Ng22 Pg34915 +0- 1 +-0 1 +.names n569 Ng22 Pg34913 +0- 1 +-0 1 +.names Ng890 Ng528 n1170 Ng479 [4376] +11-- 1 +1-1- 1 +1--0 1 +.names Pg34597 +.names Pg113 Ng2868 [4378] +0- 1 +-0 1 +.names Pg113 Ng2873 [4379] +0- 1 +-0 1 +.names n6112 Pg34435 +0 1 +.names n1189 n1636 Pg34425 +0- 1 +-0 1 +.names n1129 n1169 n1638 Pg34383 +1-- 1 +-0- 1 +--0 1 +.names Pg34240 +.names Pg34239 +.names Pg34238 +.names Pg34237 +.names Pg34236 +.names Pg34235 +.names Pg34234 +.names Pg34233 +.names Pg34232 +.names n1168 n1636 Pg34221 +0- 1 +-0 1 +.names n1178 n1401 n1638 Pg34201 +1-- 1 +-0- 1 +--0 1 +.names Ng4646 n1100 n1145 [4394] +11- 1 +1-1 1 +.names Pg33950 +.names Pg33949 +.names Pg33948 +.names Pg33947 +.names Pg33946 +.names Pg33945 +.names n1175 Pg33935 +0 1 +.names [4507] n1160 Ng4507 Pg33874 +1-- 1 +-1- 1 +--0 1 +.names n1191 n1638 n6113 Pg33659 +1-- 1 +-0- 1 +--0 1 +.names n1194 Pg33636 +0 1 +.names Pg17291 Ng1171 n1142 [4406] +10- 1 +1-1 1 +.names Ng2729 n5700 n5701 Pg33435 +01- 1 +1-1 1 +-11 1 +.names Ng2729 n5698 n5699 Pg33079 +01- 1 +1-1 1 +-11 1 +.names n3401 Pg32975 +0 1 +.names Pg32454 +.names Pg32429 +.names n2489 n2490 n2491 n2492 Pg32185 +1111 1 +.names n4553 Pg31863 +0 1 +.names n4321 Pg31862 +0 1 +.names n4527 Pg31860 +0 1 +.names n186 Pg31793 +0 1 +.names n6112 Pg31521 +0 1 +.names Ng2831 Pg30331 +0 1 +.names Ng2834 Pg30330 +0 1 +.names [4426] Pg30329 +0 1 +.names Ng37 Pg30327 +0 1 +.names n184 n185 Pg28042 +1- 1 +-1 1 +.names n182 n5079 Pg28041 +1- 1 +-0 1 +.names n180 n181 Pg28030 +1- 1 +-1 1 +.names n177 Pg26877 +0 1 +.names n174 Pg26876 +0 1 +.names n171 Pg26875 +0 1 +.names n3401 Pg26801 +0 1 +.names Pg25590 +.names Pg25589 +.names Pg25588 +.names Pg25587 +.names Pg25586 +.names Pg25585 +.names Pg25584 +.names Pg25583 +.names Pg25582 +.names n4321 Pg25259 +0 1 +.names n4553 Pg25167 +0 1 +.names n4527 Pg25114 +0 1 +.names Pg24151 +.names Ng2831 Pg23759 +0 1 +.names Ng2834 Pg23652 +0 1 +.names [4426] Pg23612 +0 1 +.names Ng25 Ng22 Pg23190 +00 1 +.names Ng37 Pg23002 +0 1 +.names Pg35 Ng3003 Pg21727 +01 1 +.names Pg5 Pg12833 +0 1 +.names Pg35 n4887 n160 +0- 1 +-1 1 +.names Ng1830 Ng2098 Ng1696 Ng1964 n172 +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names n1410 Pg35 n173 +11 1 +.names n172 n173 n171 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n2310 +1- 1 +-0 1 +.names n2309 n2310 n2308 +11 1 +.names [4437] n2521 n2312 +0- 1 +-1 1 +.names Pg35 Ng4108 n2316 n5799 n2317 +0--1 1 +-0-1 1 +--01 1 +.names Ng4098 n4791 n2316 +0- 1 +-1 1 +.names Ng3869 n4855 n2320 +0- 1 +-1 1 +.names Pg35 Ng3881 n2319 +0- 1 +-0 1 +.names n2320 n2319 Ng3869 Ng3873 n2318 +11-- 1 +1-11 1 +.names n4585 n4835 n2321 +11 1 +.names Pg35 Ng3873 n2321 n2323 +11- 1 +1-1 1 +.names Pg35 Ng3869 n2321 n2325 +0-- 1 +-1- 1 +--1 1 +.names Ng3857 Ng3863 n2326 +0- 1 +-0 1 +.names Ng3857 Ng3863 n2330 +0- 1 +-1 1 +.names Ng3857 Ng3863 n2329 +1- 1 +-0 1 +.names Pg35 n2330 n2329 n2328 +01- 1 +-11 1 +.names Ng3518 n4856 n2333 +0- 1 +-1 1 +.names Pg35 Ng3530 n2332 +0- 1 +-0 1 +.names n2333 n2332 Ng3518 Ng3522 n2331 +11-- 1 +1-11 1 +.names n4585 n4832 n2334 +11 1 +.names Pg35 Ng3522 n2334 n2336 +11- 1 +1-1 1 +.names Pg35 Ng3518 n2334 n2338 +0-- 1 +-1- 1 +--1 1 +.names Ng3512 Ng3506 n2339 +0- 1 +-0 1 +.names Ng3512 Ng3506 n2343 +1- 1 +-0 1 +.names Ng3512 Ng3506 n2342 +0- 1 +-1 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n2396 n2393 n2395 +11 1 +.names Ng2351 n4866 n4954 n2397 +1-- 1 +-1- 1 +--0 1 +.names Pg35 n2388 Ng2319 Ng2327 n2398 +11-- 1 +1-0- 1 +-1-0 1 +--00 1 +.names Pg35 n1104 n2401 +0- 1 +-1 1 +.names Pg35 n1699 n2027 n2401 n2399 +0-11 1 +-011 1 +.names n1104 n1699 n4330 n4794 n2403 +0--- 1 +-1-- 1 +--1- 1 +---0 1 +.names Pg35 Ng2208 n2404 +1- 1 +-0 1 +.names n1699 n4859 n4870 n2406 +1-- 1 +-0- 1 +--1 1 +.names Pg35 Ng2223 Ng2208 n4870 n2407 +1-0- 1 +-00- 1 +1--1 1 +-0-1 1 +.names n2401 Ng2208 Ng2185 n2409 +00- 1 +1-0 1 +-00 1 +.names n2409 n2406 n2408 +11 1 +.names Ng2217 n4870 n4957 n2410 +1-- 1 +-1- 1 +--0 1 +.names Pg35 n2401 Ng2185 Ng2193 n2411 +11-- 1 +1-0- 1 +-1-0 1 +--00 1 +.names Pg35 n1146 n2414 +0- 1 +-1 1 +.names Pg35 n1701 n2027 n2414 n2412 +0-11 1 +-011 1 +.names n1146 n1701 n4332 n4794 n2416 +0--- 1 +-1-- 1 +--1- 1 +---0 1 +.names Pg35 Ng2051 n2417 +1- 1 +-0 1 +.names n1701 n4859 n4873 n2419 +1-- 1 +-0- 1 +--1 1 +.names Pg35 Ng2066 Ng2051 n4873 n2420 +1-0- 1 +-00- 1 +1--1 1 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Pg29221 +1 1 +.names [4427] Pg29220 +1 1 +.names [4428] Pg29219 +1 1 +.names [4507] Pg29218 +1 1 +.names [4430] Pg29217 +1 1 +.names [4431] Pg29216 +1 1 +.names [4432] Pg29215 +1 1 +.names [4433] Pg29214 +1 1 +.names [4434] Pg29213 +1 1 +.names [4435] Pg29212 +1 1 +.names [4436] Pg29211 +1 1 +.names [4437] Pg29210 +1 1 +.names [4394] Pg28753 +1 1 +.names [4406] Pg27831 +1 1 +.names [4415] Pg25219 +1 1 +.names Pg44 Pg24185 +1 1 +.names Pg135 Pg24184 +1 1 +.names Pg134 Pg24183 +1 1 +.names Pg127 Pg24182 +1 1 +.names Pg126 Pg24181 +1 1 +.names Pg125 Pg24180 +1 1 +.names Pg124 Pg24179 +1 1 +.names Pg120 Pg24178 +1 1 +.names Pg116 Pg24177 +1 1 +.names Pg115 Pg24176 +1 1 +.names Pg114 Pg24175 +1 1 +.names Pg113 Pg24174 +1 1 +.names Pg100 Pg24173 +1 1 +.names Pg99 Pg24172 +1 1 +.names Pg92 Pg24171 +1 1 +.names Pg91 Pg24170 +1 1 +.names Pg90 Pg24169 +1 1 +.names Pg84 Pg24168 +1 1 +.names Pg73 Pg24167 +1 1 +.names Pg72 Pg24166 +1 1 +.names Pg64 Pg24165 +1 1 +.names Pg57 Pg24164 +1 1 +.names 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index 000000000..586efcbf7 --- /dev/null +++ b/fpga_flow/benchmarks/MCNC_big20/seq.blif @@ -0,0 +1,3422 @@ +.model TOP +.inputs i_0_ i_1_ i_2_ i_3_ i_4_ i_5_ i_6_ i_7_ i_8_ i_9_ i_10_ i_11_ i_12_ \ +i_13_ i_14_ i_15_ i_16_ i_17_ i_18_ i_19_ i_20_ i_21_ i_22_ i_23_ i_24_ i_25_ \ +i_26_ i_27_ i_28_ i_29_ i_30_ i_31_ i_32_ i_33_ i_34_ i_35_ i_36_ i_37_ i_38_ \ +i_39_ i_40_ +.outputs o_0_ o_1_ o_2_ o_3_ o_4_ o_5_ o_6_ o_7_ o_8_ o_9_ o_10_ o_11_ o_12_ \ +o_13_ o_14_ o_15_ o_16_ o_17_ o_18_ o_19_ o_20_ o_21_ o_22_ o_23_ o_24_ o_25_ \ +o_26_ o_27_ o_28_ o_29_ o_30_ o_31_ o_32_ o_33_ o_34_ +.names n1011 o_0_ +0 1 +.names n881 o_1_ +0 1 +.names n672 o_2_ +0 1 +.names n504 o_3_ +0 1 +.names n417 o_4_ +0 1 +.names n104 n105 n106 n107 n1176 n1178 n1183 n1188 o_5_ +1------- 1 +-1------ 1 +--1----- 1 +---1---- 1 +----0--- 1 +-----0-- 1 +------0- 1 +-------0 1 +.names n262 o_6_ +0 1 +.names n100 o_7_ +0 1 +.names n1 o_8_ +0 1 +.names n96 o_9_ +0 1 +.names n86 n94 n95 n972 n983 o_10_ +0---- 1 +-1--- 1 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n1235 n1205 n2514 +11 1 +.names n1334 n1326 n2515 +11 1 +.names n1313 n431 n2516 +11 1 +.names n638 n312 n2517 +11 1 +.names n922 n1423 n2518 +01 1 +.end diff --git a/fpga_flow/benchmarks/MCNC_big20/tseng.blif b/fpga_flow/benchmarks/MCNC_big20/tseng.blif new file mode 100644 index 000000000..ce29cffa7 --- /dev/null +++ b/fpga_flow/benchmarks/MCNC_big20/tseng.blif @@ -0,0 +1,3696 @@ +.model top +.inputs tin_pv10_4_4_ tin_pv11_4_4_ tin_pv6_7_7_ tin_pv2_0_0_ tin_pv10_3_3_ \ +tin_pv1_2_2_ tin_pv11_3_3_ tin_pv4_3_3_ tin_pv10_2_2_ tin_pv11_2_2_ \ +tin_pv6_0_0_ tin_pv2_1_1_ tin_pv10_1_1_ tin_pv1_3_3_ preset_0_0_ tin_pv11_1_1_ \ +tin_pv4_4_4_ tin_pready_0_0_ tin_pv10_0_0_ tin_pv11_0_0_ tin_pv6_1_1_ \ +tin_pv2_2_2_ tin_pv1_4_4_ tin_pv4_5_5_ tin_pv6_2_2_ tin_pv2_3_3_ tin_pv1_5_5_ \ +tin_pv4_6_6_ tin_pv6_3_3_ tin_pv2_4_4_ tin_pv1_6_6_ pclk tin_pv4_7_7_ \ +tin_pv6_4_4_ tin_pv2_5_5_ tin_pv1_7_7_ tin_pv4_0_0_ tin_pv6_5_5_ tin_pv2_6_6_ \ +tin_pv10_7_7_ tin_pv1_0_0_ tin_pv11_7_7_ tin_pv4_1_1_ tin_pv10_6_6_ \ +tin_pv11_6_6_ tin_pv6_6_6_ tin_pv2_7_7_ preset tin_pv10_5_5_ tin_pv1_1_1_ \ +tin_pv11_5_5_ tin_pv4_2_2_ +.outputs pv14_2_2_ pv12_3_3_ pv10_4_4_ pv7_5_5_ pv3_6_6_ pv15_2_2_ pv13_3_3_ \ +pv11_4_4_ pv6_7_7_ pv2_0_0_ pv14_1_1_ pv12_2_2_ pv10_3_3_ pv9_0_0_ pv5_1_1_ \ +pv1_2_2_ pv15_1_1_ pv13_2_2_ pv11_3_3_ pv8_2_2_ pv4_3_3_ pv14_0_0_ pv12_1_1_ \ +pv10_2_2_ pv7_6_6_ pv3_7_7_ pv15_0_0_ pv13_1_1_ pv11_2_2_ pv6_0_0_ pv2_1_1_ \ +pv12_0_0_ pv10_1_1_ pv9_1_1_ pv5_2_2_ pv1_3_3_ pv13_0_0_ pv11_1_1_ pv8_3_3_ \ +pv4_4_4_ pready_0_0_ pv10_0_0_ pv7_7_7_ pv3_0_0_ pv11_0_0_ pv6_1_1_ pv2_2_2_ \ +pv9_2_2_ pv5_3_3_ pv1_4_4_ pv8_4_4_ pv4_5_5_ pv7_0_0_ pv3_1_1_ pv6_2_2_ \ +pv2_3_3_ pv9_3_3_ pv5_4_4_ pv1_5_5_ pv8_5_5_ pv4_6_6_ pv7_1_1_ pv3_2_2_ \ +pv6_3_3_ pv2_4_4_ pv9_4_4_ pv5_5_5_ pv1_6_6_ pv8_6_6_ pv4_7_7_ pv7_2_2_ \ +pv3_3_3_ pv6_4_4_ pv2_5_5_ pv14_7_7_ pv9_5_5_ pv5_6_6_ pv1_7_7_ pv15_7_7_ \ +pv8_7_7_ pv4_0_0_ pv14_6_6_ pv12_7_7_ pv7_3_3_ pv3_4_4_ pv15_6_6_ pv13_7_7_ \ +pv6_5_5_ pv2_6_6_ pdn pv14_5_5_ pv12_6_6_ pv10_7_7_ pv9_6_6_ pv5_7_7_ pv1_0_0_ \ +pv15_5_5_ pv13_6_6_ pv11_7_7_ pv8_0_0_ pv4_1_1_ pv14_4_4_ pv12_5_5_ pv10_6_6_ \ +pv7_4_4_ pv3_5_5_ pv15_4_4_ pv13_5_5_ pv11_6_6_ pv6_6_6_ pv2_7_7_ pv14_3_3_ \ +pv12_4_4_ pv10_5_5_ pv9_7_7_ pv5_0_0_ pv1_1_1_ pv15_3_3_ pv13_4_4_ pv11_5_5_ \ +pv8_1_1_ pv4_2_2_ +.latch n_n4140 n_n4142 re pclk 2 +.latch n_n3935 n_n3936 re pclk 2 +.latch n_n3444 n_n3574 re pclk 2 +.latch n_n3007 n_n3008 re pclk 2 +.latch n_n3725 n_n3726 re pclk 2 +.latch n_n3399 n_n3604 re pclk 2 +.latch n_n3143 n_n3144 re pclk 2 +.latch n_n3781 n_n3782 re pclk 2 +.latch n_n3066 n_n3067 re pclk 2 +.latch n_n3507 n_n4258 re pclk 2 +.latch n_n3224 n_n3225 re pclk 2 +.latch n_n3179 n_n3180 re pclk 2 +.latch n_n3273 n_n3274 re pclk 2 +.latch n_n3166 n_n3475 re pclk 2 +.latch n_n3686 n_n3687 re pclk 2 +.latch n_n3380 n_n3381 re pclk 2 +.latch n_n3096 n_n3098 re pclk 2 +.latch n_n4106 n_n4108 re pclk 2 +.latch n_n3496 n_n3497 re pclk 2 +.latch n_n3791 n_n3793 re pclk 2 +.latch n_n3518 n_n4316 re pclk 2 +.latch n_n4348 n_n4349 re pclk 2 +.latch n_n3028 n_n3029 re pclk 2 +.latch n_n3618 n_n3619 re pclk 2 +.latch n_n3263 n_n3264 re pclk 2 +.latch n_n3778 n_n3780 re pclk 2 +.latch n_n3227 ndn3_4 re pclk 2 +.latch n_n4113 n_n4114 re pclk 2 +.latch n_n3145 n_n3146 re pclk 2 +.latch n_n3510 n_n3511 re pclk 2 +.latch n_n3151 n_n3152 re pclk 2 +.latch n_n129 n_n3833 re pclk 2 +.latch n_n4280 n_n4282 re pclk 2 +.latch n_n3304 n_n3305 re pclk 2 +.latch n_n3309 n_n4392 re pclk 2 +.latch n_n3490 n_n4224 re pclk 2 +.latch n_n3377 n_n3198 re pclk 2 +.latch n_n3203 n_n3204 re pclk 2 +.latch n_n3023 n_n3024 re pclk 2 +.latch n_n4137 n_n4139 re pclk 2 +.latch n_n3084 ndn3_15 re pclk 2 +.latch n_n3131 n_n3133 re pclk 2 +.latch n_n4073 n_n4074 re pclk 2 +.latch n_n3269 n_n3270 re pclk 2 +.latch n_n3181 n_n3858 re pclk 2 +.latch n_n3455 n_n3456 re pclk 2 +.latch n_n3520 n_n3521 re pclk 2 +.latch n_n3080 n_n3081 re pclk 2 +.latch n_n3296 n_n4381 re pclk 2 +.latch n_n3668 n_n3670 re pclk 2 +.latch n_n4210 n_n4211 re pclk 2 +.latch n_n3076 n_n3493 re pclk 2 +.latch n_n3148 n_n3495 re pclk 2 +.latch n_n3226 n_n3916 re pclk 2 +.latch n_n3194 n_n3195 re pclk 2 +.latch n_n3523 n_n3525 re pclk 2 +.latch n_n3727 n_n3729 re pclk 2 +.latch n_n3875 n_n3876 re pclk 2 +.latch n_n3614 ndn3_5 re pclk 2 +.latch n_n3547 n_n3549 re pclk 2 +.latch n_n3488 n_n3489 re pclk 2 +.latch n_n3762 n_n3764 re pclk 2 +.latch n_n3256 n_n3281 re pclk 2 +.latch n_n124 n_n3707 re pclk 2 +.latch n_n3515 n_n3517 re pclk 2 +.latch n_n3016 n_n4160 re pclk 2 +.latch n_n3168 n_n4222 re pclk 2 +.latch n_n3011 n_n3012 re pclk 2 +.latch n_n3373 n_n4071 re pclk 2 +.latch n_n3371 n_n3372 re pclk 2 +.latch n_n3343 n_n3344 re pclk 2 +.latch n_n3018 n_n3688 re pclk 2 +.latch n_n3077 n_n3079 re pclk 2 +.latch n_n3312 n_n3313 re pclk 2 +.latch n_n3410 n_n3411 re pclk 2 +.latch n_n3230 n_n3231 re pclk 2 +.latch n_n3395 n_n3396 re pclk 2 +.latch n_n3431 n_n3432 re pclk 2 +.latch n_n3605 n_n3606 re pclk 2 +.latch n_n3732 n_n3733 re pclk 2 +.latch n_n3063 n_n3556 re pclk 2 +.latch n_n3913 n_n4040 re pclk 2 +.latch n_n3119 n_n3120 re pclk 2 +.latch n_n3220 n_n3221 re pclk 2 +.latch n_n3172 n_n3173 re pclk 2 +.latch n_n3070 n_n3851 re pclk 2 +.latch n_n3112 n_n3113 re pclk 2 +.latch n_n3241 n_n3242 re pclk 2 +.latch n_n3117 n_n3118 re pclk 2 +.latch n_n3375 n_n3376 re pclk 2 +.latch n_n4088 n_n4089 re pclk 2 +.latch n_n3043 n_n3044 re pclk 2 +.latch n_n3625 n_n3627 re pclk 2 +.latch n_n3027 n_n3035 re pclk 2 +.latch n_n3110 n_n3111 re pclk 2 +.latch n_n3320 n_n3321 re pclk 2 +.latch n_n3442 n_n3443 re pclk 2 +.latch n_n3214 n_n3215 re pclk 2 +.latch n_n3751 ndn3_10 re pclk 2 +.latch n_n4170 n_n4172 re pclk 2 +.latch n_n3982 nlc1_2 re pclk 2 +.latch n_n3589 n_n3590 re pclk 2 +.latch n_n4109 n_n4110 re pclk 2 +.latch n_n3941 nlc3_3 re pclk 2 +.latch n_n3575 n_n3576 re pclk 2 +.latch n_n4128 n_n4129 re pclk 2 +.latch n_n4186 n_n4189 re pclk 2 +.latch n_n4283 n_n4286 re pclk 2 +.latch n_n3022 n_n4383 re pclk 2 +.latch n_n3437 pdn re pclk 2 +.latch n_n3566 n_n3567 re pclk 2 +.latch n_n3032 n_n3892 re pclk 2 +.latch n_n3074 n_n3075 re pclk 2 +.latch n_n3353 n_n3354 re pclk 2 +.latch n_n3464 n_n3465 re pclk 2 +.latch n_n4321 ndn3_6 re pclk 2 +.latch n_n3616 n_n3617 re pclk 2 +.latch n_n4161 n_n4162 re pclk 2 +.latch n_n3206 n_n3207 re pclk 2 +.latch n_n4119 n_n4120 re pclk 2 +.latch n_n3064 n_n3065 re pclk 2 +.latch n_n4004 n_n4005 re pclk 2 +.latch n_n3265 n_n3266 re pclk 2 +.latch n_n3216 n_n4337 re pclk 2 +.latch n_n3599 n_n3600 re pclk 2 +.latch n_n3414 n_n3415 re pclk 2 +.latch n_n4242 n_n4243 re pclk 2 +.latch n_n3871 n_n3872 re pclk 2 +.latch n_n3647 n_n3648 re pclk 2 +.latch n_n3357 n_n3358 re pclk 2 +.latch n_n3349 n_n3350 re pclk 2 +.latch n_n3675 ndn3_7 re pclk 2 +.latch n_n3115 n_n3116 re pclk 2 +.latch n_n3582 n_n3583 re pclk 2 +.latch n_n3904 n_n3906 re pclk 2 +.latch n_n4130 n_n4131 re pclk 2 +.latch n_n3314 n_n3316 re pclk 2 +.latch n_n3060 n_n3061 re pclk 2 +.latch n_n3047 n_n3048 re pclk 2 +.latch n_n3837 n_n3886 re pclk 2 +.latch n_n3508 n_n3919 re pclk 2 +.latch n_n3127 n_n3128 re pclk 2 +.latch n_n3235 n_n3995 re pclk 2 +.latch n_n4212 n_n4213 re pclk 2 +.latch n_n3759 n_n3761 re pclk 2 +.latch n_n4218 ndn3_8 re pclk 2 +.latch n_n3251 n_n3252 re pclk 2 +.latch n_n3382 n_n4366 re pclk 2 +.latch n_n3327 n_n3328 re pclk 2 +.latch n_n3987 n_n3988 re pclk 2 +.latch n_n3347 n_n3348 re pclk 2 +.latch n_n3543 n_n3544 re pclk 2 +.latch n_n3100 n_n3101 re pclk 2 +.latch n_n4276 n_n4279 re pclk 2 +.latch n_n3895 n_n3896 re pclk 2 +.latch n_n3735 n_n3736 re pclk 2 +.latch n_n3049 n_n4251 re pclk 2 +.latch n_n3649 n_n3650 re pclk 2 +.latch n_n3306 n_n3307 re pclk 2 +.latch n_n4293 n_n4294 re pclk 2 +.latch n_n3907 n_n4334 re pclk 2 +.latch n_n3579 n_n3955 re pclk 2 +.latch n_n4163 n_n4164 re pclk 2 +.latch n_n3154 n_n3155 re pclk 2 +.latch n_n3748 n_n3749 re pclk 2 +.latch n_n3271 n_n4233 re pclk 2 +.latch n_n4346 n_n4347 re pclk 2 +.latch n_n3825 n_n3826 re pclk 2 +.latch n_n3359 n_n3360 re pclk 2 +.latch n_n3147 n_n3458 re pclk 2 +.latch n_n3092 n_n3093 re pclk 2 +.latch n_n3156 n_n3157 re pclk 2 +.latch n_n3505 n_n3506 re pclk 2 +.latch n_n3160 n_n3161 re pclk 2 +.latch n_n3318 n_n3319 re pclk 2 +.latch n_n3428 n_n3429 re pclk 2 +.latch n_n3969 n_n3971 re pclk 2 +.latch n_n3447 n_n3449 re pclk 2 +.latch n_n4081 n_n4270 re pclk 2 +.latch n_n3302 n_n4288 re pclk 2 +.latch n_n3182 n_n3183 re pclk 2 +.latch n_n3129 n_n3130 re pclk 2 +.latch n_n3430 nlak4_2 re pclk 2 +.latch n_n4046 n_n4047 re pclk 2 +.latch n_n3123 n_n3978 re pclk 2 +.latch n_n3238 n_n3239 re pclk 2 +.latch n_n3972 n_n4145 re pclk 2 +.latch n_n3889 n_n3890 re pclk 2 +.latch n_n4001 n_n4003 re pclk 2 +.latch n_n3090 n_n3091 re pclk 2 +.latch n_n3983 n_n3985 re pclk 2 +.latch n_n3325 n_n3326 re pclk 2 +.latch n_n3540 n_n4052 re pclk 2 +.latch n_n125 nsr4_2 re pclk 2 +.latch n_n3693 n_n4099 re pclk 2 +.latch n_n4373 n_n4375 re pclk 2 +.latch n_n3866 n_n4067 re pclk 2 +.latch n_n4289 n_n4290 re pclk 2 +.latch n_n3459 n_n3898 re pclk 2 +.latch n_n4121 n_n4122 re pclk 2 +.latch n_n3773 n_n3774 re pclk 2 +.latch n_n3013 n_n3014 re pclk 2 +.latch n_n4239 n_n4241 re pclk 2 +.latch n_n3950 n_n3952 re pclk 2 +.latch n_n3236 n_n3237 re pclk 2 +.latch n_n3530 n_n3968 re pclk 2 +.latch n_n3033 n_n3922 re pclk 2 +.latch n_n3550 n_n3551 re pclk 2 +.latch n_n3378 n_n3379 re pclk 2 +.latch n_n3009 n_n4275 re pclk 2 +.latch n_n3569 n_n3570 re pclk 2 +.latch n_n3853 n_n3854 re pclk 2 +.latch n_n131 n_n4057 re pclk 2 +.latch n_n3450 n_n3451 re pclk 2 +.latch n_n4036 n_n4037 re pclk 2 +.latch n_n3406 n_n3408 re pclk 2 +.latch n_n4228 n_n4229 re pclk 2 +.latch n_n3701 n_n4201 re pclk 2 +.latch n_n3338 n_n3339 re pclk 2 +.latch n_n4361 n_n4362 re pclk 2 +.latch n_n3466 n_n3483 re pclk 2 +.latch n_n3355 n_n3557 re pclk 2 +.latch n_n4184 n_n4185 re pclk 2 +.latch n_n3068 n_n3069 re pclk 2 +.latch n_n3642 n_n3643 re pclk 2 +.latch n_n3402 n_n3404 re pclk 2 +.latch n_n3056 n_n3057 re pclk 2 +.latch n_n3019 n_n3020 re pclk 2 +.latch n_n3827 n_n3828 re pclk 2 +.latch n_n3629 n_n3631 re pclk 2 +.latch n_n3137 n_n3138 re pclk 2 +.latch n_n126 nsr1_2 re pclk 2 +.latch n_n4063 n_n4065 re pclk 2 +.latch n_n3677 n_n3679 re pclk 2 +.latch n_n3285 n_n3287 re pclk 2 +.latch n_n3308 n_n4351 re pclk 2 +.latch n_n4058 n_n4059 re pclk 2 +.latch n_n3435 n_n3436 re pclk 2 +.latch n_n3635 nen3_10 re pclk 2 +.latch n_n3460 n_n3461 re pclk 2 +.latch n_n4011 n_n4012 re pclk 2 +.latch n_n3050 n_n3051 re pclk 2 +.latch n_n3072 n_n3073 re pclk 2 +.latch n_n3775 n_n3777 re pclk 2 +.latch n_n3199 n_n3709 re pclk 2 +.latch n_n3025 n_n3946 re pclk 2 +.latch n_n3058 n_n3085 re pclk 2 +.latch n_n3258 n_n3259 re pclk 2 +.latch n_n3503 n_n3504 re pclk 2 +.latch n_n130 n_n4045 re pclk 2 +.latch n_n121 n_n3954 re pclk 2 +.latch n_n3134 n_n3136 re pclk 2 +.latch n_n4370 n_n4372 re pclk 2 +.latch n_n4234 n_n4236 re pclk 2 +.latch n_n3039 n_n3040 re pclk 2 +.latch n_n3873 n_n3874 re pclk 2 +.latch n_n3998 n_n3999 re pclk 2 +.latch n_n3222 n_n3223 re pclk 2 +.latch n_n3036 ndn1_34 re pclk 2 +.latch n_n3062 n_n3743 re pclk 2 +.latch n_n3017 n_n3657 re pclk 2 +.latch n_n3212 n_n3213 re pclk 2 +.latch n_n3094 n_n3095 re pclk 2 +.latch n_n3662 n_n3663 re pclk 2 +.latch n_n3217 n_n3724 re pclk 2 +.latch n_n3037 n_n3038 re pclk 2 +.latch n_n3368 n_n3370 re pclk 2 +.latch n_n3030 n_n3624 re pclk 2 +.latch n_n3494 n_n3578 re pclk 2 +.latch n_n3711 n_n3713 re pclk 2 +.latch n_n3088 n_n3089 re pclk 2 +.latch n_n3210 n_n3211 re pclk 2 +.latch n_n3366 n_n3367 re pclk 2 +.latch n_n3433 n_n3434 re pclk 2 +.latch n_n3125 n_n3126 re pclk 2 +.latch n_n4190 n_n4192 re pclk 2 +.latch n_n4134 n_n4136 re pclk 2 +.latch n_n3052 n_n3053 re pclk 2 +.latch n_n3937 n_n3938 re pclk 2 +.latch n_n3632 n_n3769 re pclk 2 +.latch n_n4387 n_n4390 re pclk 2 +.latch n_n127 nsr3_17 re pclk 2 +.latch n_n3902 n_n3903 re pclk 2 +.latch n_n3684 n_n3658 re pclk 2 +.latch n_n3046 nrq3_11 re pclk 2 +.latch n_n3817 n_n3818 re pclk 2 +.latch n_n3374 n_n3533 re pclk 2 +.latch n_n3462 n_n3463 re pclk 2 +.latch n_n3174 n_n3175 re pclk 2 +.latch n_n3054 n_n3055 re pclk 2 +.latch n_n3200 n_n3202 re pclk 2 +.latch n_n3383 n_n3385 re pclk 2 +.latch n_n4076 n_n4077 re pclk 2 +.latch n_n3141 n_n3142 re pclk 2 +.latch n_n3289 n_n3901 re pclk 2 +.latch n_n3552 n_n3934 re pclk 2 +.latch n_n3821 n_n3823 re pclk 2 +.latch n_n3721 n_n3722 re pclk 2 +.latch n_n4307 n_n4309 re pclk 2 +.latch n_n3229 n_n4159 re pclk 2 +.latch n_n3021 n_n4330 re pclk 2 +.latch n_n3835 n_n3836 re pclk 2 +.latch n_n3469 n_n3470 re pclk 2 +.latch n_n3329 n_n3331 re pclk 2 +.latch n_n3881 n_n3883 re pclk 2 +.latch n_n3031 n_n4299 re pclk 2 +.latch n_n4156 n_n4157 re pclk 2 +.latch n_n4086 ndn3_9 re pclk 2 +.latch n_n3045 n_n3208 re pclk 2 +.latch n_n3189 n_n3190 re pclk 2 +.latch n_n4028 n_n4029 re pclk 2 +.latch n_n3041 n_n3042 re pclk 2 +.latch n_n133 nsr3_14 re pclk 2 +.latch n_n122 n_n4151 re pclk 2 +.latch n_n3187 n_n3188 re pclk 2 +.latch n_n4300 n_n4303 re pclk 2 +.latch n_n3249 n_n3250 re pclk 2 +.latch n_n3169 n_n3170 re pclk 2 +.latch n_n3757 n_n3758 re pclk 2 +.latch n_n3908 n_n3910 re pclk 2 +.latch n_n3106 n_n3108 re pclk 2 +.latch n_n3149 n_n3150 re pclk 2 +.latch n_n4317 n_n4320 re pclk 2 +.latch n_n4359 n_n4360 re pclk 2 +.latch n_n4245 n_n4247 re pclk 2 +.latch n_n4196 n_n4199 re pclk 2 +.latch n_n3964 n_n3966 re pclk 2 +.latch n_n3184 n_n3766 re pclk 2 +.latch n_n3010 n_n4021 re pclk 2 +.latch n_n3122 n_n4062 re pclk 2 +.latch n_n3512 n_n3514 re pclk 2 +.latch n_n3571 n_n3572 re pclk 2 +.latch n_n4165 n_n4166 re pclk 2 +.latch n_n3519 n_n3976 re pclk 2 +.latch n_n3392 n_n3394 re pclk 2 +.latch n_n4094 n_n4095 re pclk 2 +.latch n_n3862 n_n3863 re pclk 2 +.latch n_n3719 n_n3720 re pclk 2 +.latch n_n3810 ngfdn_3 re pclk 2 +.latch n_n3755 n_n3756 re pclk 2 +.latch n_n3665 n_n3667 re pclk 2 +.latch n_n3340 n_n3342 re pclk 2 +.latch n_n3528 n_n3529 re pclk 2 +.latch n_n4207 n_n4209 re pclk 2 +.latch n_n3585 n_n4324 re pclk 2 +.latch n_n3336 n_n3337 re pclk 2 +.latch n_n3026 n_n4227 re pclk 2 +.latch n_n4152 n_n4153 re pclk 2 +.latch n_n128 n_n3831 re pclk 2 +.latch n_n3232 n_n3233 re pclk 2 +.latch n_n4262 n_n4263 re pclk 2 +.latch n_n3412 n_n3413 re pclk 2 +.latch n_n3015 n_n4182 re pclk 2 +.latch n_n3526 n_n3841 re pclk 2 +.latch n_n3440 n_n3441 re pclk 2 +.latch n_n3140 n_n4026 re pclk 2 +.latch n_n4339 n_n4342 re pclk 2 +.latch n_n4100 n_n4102 re pclk 2 +.latch n_n3275 n_n3277 re pclk 2 +.latch n_n4178 n_n4180 re pclk 2 +.latch n_n3877 n_n3878 re pclk 2 +.latch n_n3538 n_n3931 re pclk 2 +.latch n_n3680 n_n3845 re pclk 2 +.latch n_n3104 n_n3865 re pclk 2 +.latch n_n3484 n_n3486 re pclk 2 +.latch n_n3473 n_n4056 re pclk 2 +.latch n_n3673 n_n3674 re pclk 2 +.latch n_n3592 n_n3959 re pclk 2 +.latch n_n3607 n_n3608 re pclk 2 +.latch n_n3292 n_n4080 re pclk 2 +.latch n_n4017 n_n4018 re pclk 2 +.latch n_n4352 n_n4354 re pclk 2 +.latch n_n3796 n_n3797 re pclk 2 +.latch n_n3737 n_n3739 re pclk 2 +.latch n_n3644 n_n3646 re pclk 2 +.latch n_n3059 n_n3099 re pclk 2 +.latch n_n3535 n_n3537 re pclk 2 +.latch n_n3804 n_n3806 re pclk 2 +.latch n_n3086 n_n3087 re pclk 2 +.latch n_n4104 n_n4105 re pclk 2 +.latch n_n3261 n_n3262 re pclk 2 +.latch n_n4124 n_n4125 re pclk 2 +.latch n_n3813 n_n3814 re pclk 2 +.latch n_n132 n_n4093 re pclk 2 +.latch n_n123 nsr3_3 re pclk 2 +.names n_n3358 n_n4153 pv14_2_2_ +11 1 +.names n_n3631 n_n3367 pv12_3_3_ +11 1 +.names tin_pv10_4_4_ n_n4136 n_n3042 pv10_4_4_ +-11 1 +1-0 1 +.names n_n3130 n_n3679 pv7_5_5_ +11 1 +.names n_n3252 n_n3057 pv3_6_6_ +11 1 +.names n_n3113 n_n4037 pv15_2_2_ +11 1 +.names n_n3600 n_n3404 pv13_3_3_ +11 1 +.names tin_pv11_4_4_ n_n4120 n_n3966 pv11_4_4_ +10- 1 +-11 1 +.names tin_pv6_7_7_ n_n4164 n_n3370 pv6_7_7_ +10- 1 +-11 1 +.names tin_pv2_0_0_ n_n3211 n_n3910 pv2_0_0_ +10- 1 +-11 1 +.names n_n3012 n_n3038 pv14_1_1_ +11 1 +.names n_n3067 n_n3576 pv12_2_2_ +11 1 +.names tin_pv10_3_3_ n_n4129 n_n3213 pv10_3_3_ +10- 1 +-11 1 +.names n_n3128 n_n3890 pv9_0_0_ +11 1 +.names n_n3443 n_n3287 pv5_1_1_ +11 1 +.names tin_pv1_2_2_ n_n3470 n_n3537 pv1_2_2_ +10- 1 +-11 1 +.names n_n3606 n_n3108 pv15_1_1_ +11 1 +.names n_n3379 n_n3463 pv13_2_2_ +11 1 +.names tin_pv11_3_3_ n_n3432 n_n3583 pv11_3_3_ +10- 1 +-11 1 +.names n_n3456 n_n3055 pv8_2_2_ +11 1 +.names tin_pv4_3_3_ n_n3489 n_n4309 pv4_3_3_ +10- 1 +-11 1 +.names n_n3761 n_n3903 pv14_0_0_ +11 1 +.names n_n3264 n_n4390 pv12_1_1_ +11 1 +.names tin_pv10_2_2_ n_n3549 n_n3065 pv10_2_2_ +-11 1 +1-0 1 +.names n_n3670 n_n3617 pv7_6_6_ +11 1 +.names n_n3590 n_n4102 pv3_7_7_ +11 1 +.names n_n4003 n_n3188 pv15_0_0_ +11 1 +.names n_n3221 n_n3150 pv13_1_1_ +11 1 +.names tin_pv11_2_2_ n_n3152 n_n3823 pv11_2_2_ +10- 1 +-11 1 +.names tin_pv6_0_0_ n_n3029 n_n3506 pv6_0_0_ +10- 1 +-11 1 +.names tin_pv2_1_1_ n_n3999 n_n3646 pv2_1_1_ +10- 1 +-11 1 +.names n_n3098 n_n3339 pv12_0_0_ +11 1 +.names tin_pv10_1_1_ n_n3270 n_n3872 pv10_1_1_ +-11 1 +1-0 1 +.names n_n3024 n_n3044 pv9_1_1_ +11 1 +.names n_n4286 n_n3350 pv5_2_2_ +11 1 +.names tin_pv1_3_3_ n_n3441 n_n4180 pv1_3_3_ +10- 1 +-11 1 +.names n_n3061 n_n3434 pv13_0_0_ +11 1 +.names tin_pv11_1_1_ n_n4142 n_n4185 pv11_1_1_ +-11 1 +1-0 1 +.names n_n3146 n_n3091 pv8_3_3_ +11 1 +.names tin_pv4_4_4_ n_n3627 n_n4110 pv4_4_4_ +-11 1 +1-0 1 +.names tin_pready_0_0_ n_n4108 n_n3354 pready_0_0_ +10- 1 +-11 1 +.names tin_pv10_0_0_ n_n4282 n_n4209 pv10_0_0_ +10- 1 +-11 1 +.names n_n3136 n_n4077 pv7_7_7_ +11 1 +.names n_n3173 n_n3828 pv3_0_0_ +11 1 +.names tin_pv11_0_0_ n_n3514 n_n3233 pv11_0_0_ +-11 1 +1-0 1 +.names tin_pv6_1_1_ n_n3144 n_n3952 pv6_1_1_ +10- 1 +-11 1 +.names tin_pv2_2_2_ n_n3202 n_n4354 pv2_2_2_ +-11 1 +1-0 1 +.names n_n3736 n_n3157 pv9_2_2_ +11 1 +.names n_n3321 n_n4236 pv5_3_3_ +11 1 +.names tin_pv1_4_4_ n_n3863 n_n3806 pv1_4_4_ +10- 1 +-11 1 +.names n_n3344 n_n3095 pv8_4_4_ +11 1 +.names tin_pv4_5_5_ n_n3733 n_n3087 pv4_5_5_ +-11 1 +1-0 1 +.names n_n3161 n_n3069 pv7_0_0_ +11 1 +.names n_n3048 n_n3461 pv3_1_1_ +11 1 +.names tin_pv6_2_2_ n_n3307 n_n3138 pv6_2_2_ +10- 1 +-11 1 +.names tin_pv2_3_3_ n_n3465 n_n3874 pv2_3_3_ +-11 1 +1-0 1 +.names n_n3906 n_n3749 pv9_3_3_ +11 1 +.names n_n3793 n_n4213 pv5_4_4_ +11 1 +.names tin_pv1_5_5_ n_n3313 n_n3101 pv1_5_5_ +-11 1 +1-0 1 +.names n_n3116 n_n3331 pv8_5_5_ +11 1 +.names tin_pv4_6_6_ n_n3774 n_n3413 pv4_6_6_ +10- 1 +-11 1 +.names n_n3415 n_n3971 pv7_1_1_ +11 1 +.names n_n3190 n_n3739 pv3_2_2_ +11 1 +.names tin_pv6_3_3_ n_n3204 n_n3486 pv6_3_3_ +10- 1 +-11 1 +.names tin_pv2_4_4_ n_n3133 n_n3643 pv2_4_4_ +-11 1 +1-0 1 +.names n_n3687 n_n3650 pv9_4_4_ +11 1 +.names n_n3266 n_n3408 pv5_5_5_ +11 1 +.names tin_pv1_6_6_ n_n3118 n_n4018 pv1_6_6_ +-11 1 +1-0 1 +.names n_n3180 n_n3223 pv8_6_6_ +11 1 +.names tin_pv4_7_7_ n_n4114 n_n4166 pv4_7_7_ +10- 1 +-11 1 +.names n_n3497 n_n4105 pv7_2_2_ +11 1 +.names n_n3274 n_n4342 pv3_3_3_ +11 1 +.names tin_pv6_4_4_ n_n3093 n_n4065 pv6_4_4_ +10- 1 +-11 1 +.names tin_pv2_5_5_ n_n3780 n_n4059 pv2_5_5_ +-11 1 +1-0 1 +.names n_n3449 n_n4241 pv14_7_7_ +11 1 +.names n_n3985 n_n4290 pv9_5_5_ +11 1 +.names n_n3567 n_n3237 pv5_6_6_ +11 1 +.names tin_pv1_7_7_ n_n3544 n_n4199 pv1_7_7_ +10- 1 +-11 1 +.names n_n3079 n_n3648 pv15_7_7_ +11 1 +.names n_n3525 n_n3529 pv8_7_7_ +11 1 +.names tin_pv4_0_0_ n_n3517 n_n3826 pv4_0_0_ +-11 1 +1-0 1 +.names n_n3713 n_n3262 pv14_6_6_ +11 1 +.names n_n3764 n_n3720 pv12_7_7_ +11 1 +.names n_n3411 n_n4303 pv7_3_3_ +11 1 +.names n_n3729 n_n4162 pv3_4_4_ +11 1 +.names n_n4375 n_n3020 pv15_6_6_ +11 1 +.names n_n3372 n_n3394 pv13_7_7_ +11 1 +.names tin_pv6_5_5_ n_n4189 n_n3348 pv6_5_5_ +-11 1 +1-0 1 +.names tin_pv2_6_6_ n_n3120 n_n3385 pv2_6_6_ +10- 1 +-11 1 +.names n_n3008 n_n3663 pv14_5_5_ +11 1 +.names n_n3782 n_n3896 pv12_6_6_ +11 1 +.names tin_pv10_7_7_ n_n3225 n_n3521 pv10_7_7_ +-11 1 +1-0 1 +.names n_n4243 n_n3239 pv9_6_6_ +11 1 +.names n_n3111 n_n4005 pv5_7_7_ +11 1 +.names tin_pv1_0_0_ n_n3551 n_n4192 pv1_0_0_ +10- 1 +-11 1 +.names n_n3277 n_n3674 pv15_5_5_ +11 1 +.names n_n3155 n_n3797 pv13_6_6_ +11 1 +.names tin_pv11_7_7_ n_n3376 n_n3360 pv11_7_7_ +-11 1 +1-0 1 +.names n_n3014 n_n4320 pv8_0_0_ +11 1 +.names tin_pv4_1_1_ n_n4089 n_n3722 pv4_1_1_ +10- 1 +-11 1 +.names n_n3326 n_n3089 pv14_4_4_ +11 1 +.names n_n3619 n_n3337 pv12_5_5_ +11 1 +.names tin_pv10_6_6_ n_n3570 n_n3342 pv10_6_6_ +10- 1 +-11 1 +.names n_n3073 n_n3053 pv7_4_4_ +11 1 +.names n_n3436 n_n3142 pv3_5_5_ +11 1 +.names n_n3305 n_n3667 pv15_4_4_ +11 1 +.names n_n4139 n_n3777 pv13_5_5_ +11 1 +.names tin_pv11_6_6_ n_n4279 n_n3504 pv11_6_6_ +-11 1 +1-0 1 +.names tin_pv6_6_6_ n_n3429 n_n3836 pv6_6_6_ +-11 1 +1-0 1 +.names tin_pv2_7_7_ n_n4131 n_n3126 pv2_7_7_ +10- 1 +-11 1 +.names n_n3396 n_n3316 pv14_3_3_ +11 1 +.names n_n3231 n_n3175 pv12_4_4_ +11 1 +.names tin_pv10_5_5_ n_n3381 n_n4247 pv10_5_5_ +10- 1 +-11 1 +.names n_n3319 n_n3040 pv9_7_7_ +11 1 +.names n_n3195 n_n3572 pv5_0_0_ +11 1 +.names tin_pv1_1_1_ n_n3215 n_n3183 pv1_1_1_ +10- 1 +-11 1 +.names n_n4172 n_n3051 pv15_3_3_ +11 1 +.names n_n3075 n_n3758 pv13_4_4_ +11 1 +.names tin_pv11_5_5_ n_n3081 n_n3207 pv11_5_5_ +10- 1 +-11 1 +.names n_n3938 n_n3883 pv8_1_1_ +11 1 +.names tin_pv4_2_2_ n_n4347 n_n4372 pv4_2_2_ +10- 1 +-11 1 +.names n_n3724 n_n3830 [2275] [6252] n_n4140 +--1- 1 +10-1 1 +.names pv11_1_1_ [988] [2270] n_n3935 +--1 1 +11- 1 +.names [2261] [2262] [2263] n_n3444 +1-- 1 +-1- 1 +--1 1 +.names n_n3035 n_n4157 [894] [2259] n_n3007 +---1 1 +111- 1 +.names [2240] [2241] [2242] n_n3725 +1-- 1 +-1- 1 +--1 1 +.names preset [1016] n_n3399 +01 1 +.names preset pdn n_n3144 nrq1_3 n_n3143 +0-1- 1 +00-1 1 +.names preset pdn n_n3782 nrq1_3 n_n3781 +0-1- 1 +00-1 1 +.names preset pdn n_n3067 nrq1_3 n_n3066 +0-1- 1 +00-1 1 +.names pv10_3_3_ [992] [2226] n_n3507 +--1 1 +11- 1 +.names n_n4360 [894] [2224] n_n3224 +--1 1 +11- 1 +.names preset pdn n_n3180 nrq1_3 n_n3179 +0-1- 1 +00-1 1 +.names preset pdn n_n3274 nrq1_3 n_n3273 +0-1- 1 +00-1 1 +.names n_n3475 [916] [934] [1019] n_n3166 +1-1- 1 +11-1 1 +01-0 1 +.names n_n3458 [894] [2202] n_n3686 +--1 1 +11- 1 +.names preset pdn n_n3381 nrq1_3 n_n3380 +0-1- 1 +00-1 1 +.names n_n3688 n_n3624 [894] [2198] n_n3096 +---1 1 +111- 1 +.names preset [1020] n_n4106 +01 1 +.names n_n3901 [894] n_n4367 [2195] n_n3496 +---1 1 +111- 1 +.names n_n3916 [894] [1096] [2192] n_n3791 +---1 1 +111- 1 +010- 1 +.names n_n4015 [1004] [2166] n_n3518 +--1 1 +11- 1 +.names pv6_0_0_ [990] [2162] n_n4348 +--1 1 +11- 1 +.names preset pdn n_n3029 nrq1_3 n_n3028 +0-1- 1 +00-1 1 +.names preset pdn n_n3619 nrq1_3 n_n3618 +0-1- 1 +00-1 1 +.names preset pdn n_n3264 nrq1_3 n_n3263 +0-1- 1 +00-1 1 +.names n_n4288 [894] [2153] [6259] n_n3778 +--1- 1 +11-- 1 +-1-1 1 +.names preset ngfdn_3 [1021] n_n3227 +001 1 +.names preset pdn n_n4114 nrq1_3 n_n4113 +0-1- 1 +00-1 1 +.names preset pdn n_n3146 nrq1_3 n_n3145 +0-1- 1 +00-1 1 +.names pv1_5_5_ [994] [2141] n_n3510 +--1 1 +11- 1 +.names preset pdn n_n3152 nrq1_3 n_n3151 +0-1- 1 +00-1 1 +.names preset n_n3833 n_n3563 [1022] n_n129 +1--- 1 +-1-1 1 +--00 1 +.names preset pdn n_n4282 nrq1_3 n_n4280 +0-1- 1 +00-1 1 +.names preset pdn n_n3305 nrq1_3 n_n3304 +0-1- 1 +00-1 1 +.names [1002] n_n3363 [1128] [2126] n_n3309 +---1 1 +111- 1 +100- 1 +.names pv4_5_5_ [997] [2122] n_n3490 +--1 1 +11- 1 +.names preset [1137] [1136] [6290] n_n3377 +00-1 1 +0-01 1 +.names preset pdn n_n3204 nrq1_3 n_n3203 +0-1- 1 +00-1 1 +.names preset pdn n_n3024 nrq1_3 n_n3023 +0-1- 1 +00-1 1 +.names preset pdn n_n4139 nrq1_3 n_n4137 +0-1- 1 +00-1 1 +.names preset ndn3_15 ngfdn_3 n_n3084 +010 1 +.names n_n3458 [894] [2051] [6291] n_n3131 +--1- 1 +11-- 1 +-1-1 1 +.names n_n3810 n_n4345 [1122] [2029] n_n4073 +---1 1 +111- 1 +100- 1 +.names n_n3743 [894] [2027] n_n3269 +--1 1 +11- 1 +.names pv1_2_2_ [994] [2023] n_n3181 +--1 1 +11- 1 +.names preset pdn n_n3456 nrq1_3 n_n3455 +0-1- 1 +00-1 1 +.names preset pdn n_n3521 nrq1_3 n_n3520 +0-1- 1 +00-1 1 +.names preset pdn n_n3081 nrq1_3 n_n3080 +0-1- 1 +00-1 1 +.names [1006] [2007] [2009] [6300] n_n3296 +-1-- 1 +1-1- 1 +1--1 1 +.names n_n3475 [894] n_n4367 [2005] n_n3668 +---1 1 +111- 1 +.names pv11_2_2_ [988] [2000] n_n4210 +--1 1 +11- 1 +.names n_n4045 n_n4367 [6299] [6302] n_n3076 +11-1 1 +1-01 1 +.names n_n4015 [1002] [1998] n_n3148 +--1 1 +11- 1 +.names [1004] n_n4345 [1122] [1996] n_n3226 +---1 1 +111- 1 +100- 1 +.names preset pdn n_n3195 nrq1_3 n_n3194 +0-1- 1 +00-1 1 +.names n_n3242 [894] [1992] n_n3523 +--1 1 +11- 1 +.names n_n3916 [894] [1990] n_n3727 +--1 1 +11- 1 +.names pv10_4_4_ [992] [1986] n_n3875 +--1 1 +11- 1 +.names preset ndn3_4 ndn3_5 ngfdn_3 n_n3614 +01-0 1 +0-10 1 +.names n_n3946 [894] [1984] n_n3547 +--1 1 +11- 1 +.names preset pdn n_n3489 nrq1_3 n_n3488 +0-1- 1 +00-1 1 +.names n_n3242 n_n3170 [894] [1980] n_n3762 +---1 1 +111- 1 +.names pv2_3_3_ [999] [1976] n_n3256 +--1 1 +11- 1 +.names preset nak3_17 [1971] n_n124 +1-- 1 +-1- 1 +--1 1 +.names n_n4159 [894] [1969] n_n3515 +--1 1 +11- 1 +.names pv4_1_1_ [997] [1965] n_n3016 +--1 1 +11- 1 +.names [1004] n_n3363 [1128] [1963] n_n3168 +---1 1 +111- 1 +100- 1 +.names n_n3936 n_n3099 [894] [1961] n_n3011 +---1 1 +111- 1 +.names pv6_5_5_ [990] [1957] n_n3373 +--1 1 +11- 1 +.names preset pdn n_n3372 nrq1_3 n_n3371 +0-1- 1 +00-1 1 +.names n_n4074 [894] [1953] n_n3343 +--1 1 +11- 1 +.names n_n3810 n_n3975 n_n3974 [1949] n_n3018 +---1 1 +101- 1 +110- 1 +.names n_n4233 [894] [1946] [6303] n_n3077 +--1- 1 +11-- 1 +-1-1 1 +.names n_n3035 n_n4157 [894] [1944] n_n3312 +---1 1 +111- 1 +.names preset pdn n_n3411 nrq1_3 n_n3410 +0-1- 1 +00-1 1 +.names n_n4074 n_n3578 [894] [1940] n_n3230 +---1 1 +111- 1 +.names preset pdn n_n3396 nrq1_3 n_n3395 +0-1- 1 +00-1 1 +.names preset pdn n_n3432 nrq1_3 n_n3431 +0-1- 1 +00-1 1 +.names preset pdn n_n3606 nrq1_3 n_n3605 +0-1- 1 +00-1 1 +.names n_n4224 [894] [1932] n_n3732 +--1 1 +11- 1 +.names pv11_6_6_ [988] [1928] n_n3063 +--1 1 +11- 1 +.names [1925] [1926] [1927] n_n3913 +1-- 1 +-1- 1 +--1 1 +.names preset pdn n_n3120 nrq1_3 n_n3119 +0-1- 1 +00-1 1 +.names n_n4222 [894] [1921] n_n3220 +--1 1 +11- 1 +.names n_n3976 [894] [1919] n_n3172 +--1 1 +11- 1 +.names preset n_n3851 n_n3852 [936] n_n3070 +01-1 1 +0-10 1 +.names n_n3495 [894] [1914] [6310] n_n3112 +--1- 1 +11-- 1 +-1-1 1 +.names [1884] [1885] n_n3241 +1- 1 +-1 1 +.names n_n3556 n_n4122 [894] [1882] n_n3117 +---1 1 +111- 1 +.names n_n3483 n_n3830 [1881] [6252] n_n3375 +--1- 1 +10-1 1 +.names preset pdn n_n4089 nrq1_3 n_n4088 +0-1- 1 +00-1 1 +.names n_n4392 [894] [1876] n_n3043 +--1 1 +11- 1 +.names n_n4330 [894] [1874] n_n3625 +--1 1 +11- 1 +.names pv11_5_5_ [988] [1870] n_n3027 +--1 1 +11- 1 +.names n_n3841 [894] [1078] [1868] n_n3110 +---1 1 +111- 1 +010- 1 +.names preset pdn n_n3321 nrq1_3 n_n3320 +0-1- 1 +00-1 1 +.names preset pdn n_n3443 nrq1_3 n_n3442 +0-1- 1 +00-1 1 +.names preset pdn n_n3215 nrq1_3 n_n3214 +0-1- 1 +00-1 1 +.names preset ndn3_10 nen3_10 ngfdn_3 n_n3751 +01-0 1 +0-10 1 +.names n_n4351 [894] [1859] [6322] n_n4170 +--1- 1 +11-- 1 +-1-1 1 +.names preset pdn [1028] n_n3982 +001 1 +.names preset pdn n_n3590 nrq1_3 n_n3589 +0-1- 1 +00-1 1 +.names preset pdn n_n4110 nrq1_3 n_n4109 +0-1- 1 +00-1 1 +.names nlc3_3 [944] nrq3_2 [6324] n_n3941 +10-- 1 +-011 1 +.names n_n4211 n_n3657 [894] [1853] n_n3575 +---1 1 +111- 1 +.names preset pdn n_n4129 nrq1_3 n_n4128 +0-1- 1 +00-1 1 +.names n_n4071 [894] [1849] n_n4186 +--1 1 +11- 1 +.names [894] n_n4116 [1847] n_n4283 +--1 1 +11- 1 +.names pv4_2_2_ [997] [1843] n_n3022 +--1 1 +11- 1 +.names preset pdn nrq1_3 n_n3437 +001 1 +.names preset pdn n_n3567 nrq1_3 n_n3566 +0-1- 1 +00-1 1 +.names pv6_6_6_ [990] [1837] n_n3032 +--1 1 +11- 1 +.names preset pdn n_n3075 nrq1_3 n_n3074 +0-1- 1 +00-1 1 +.names preset pdn nrq1_3 [1833] n_n3353 +---1 1 +001- 1 +.names n_n4351 [894] [1830] [6322] n_n3464 +--1- 1 +11-- 1 +-1-1 1 +.names preset ndn3_5 ndn3_6 ngfdn_3 n_n4321 +01-0 1 +0-10 1 +.names preset pdn n_n3617 nrq1_3 n_n3616 +0-1- 1 +00-1 1 +.names preset pdn n_n4162 nrq1_3 n_n4161 +0-1- 1 +00-1 1 +.names n_n4012 n_n3830 [1825] [6252] n_n3206 +--1- 1 +10-1 1 +.names preset pdn n_n4120 nrq1_3 n_n4119 +0-1- 1 +00-1 1 +.names preset pdn n_n3065 nrq1_3 n_n3064 +0-1- 1 +00-1 1 +.names preset pdn n_n4005 nrq1_3 n_n4004 +0-1- 1 +00-1 1 +.names preset pdn n_n3266 nrq1_3 n_n3265 +0-1- 1 +00-1 1 +.names pv6_7_7_ [990] [1812] n_n3216 +--1 1 +11- 1 +.names preset pdn n_n3600 nrq1_3 n_n3599 +0-1- 1 +00-1 1 +.names preset pdn n_n3415 nrq1_3 n_n3414 +0-1- 1 +00-1 1 +.names n_n4095 [894] [1806] n_n4242 +--1 1 +11- 1 +.names preset pdn n_n3872 nrq1_3 n_n3871 +0-1- 1 +00-1 1 +.names preset pdn n_n3648 nrq1_3 n_n3647 +0-1- 1 +00-1 1 +.names n_n4211 n_n3657 [894] [1800] n_n3357 +---1 1 +111- 1 +.names preset pdn n_n3350 nrq1_3 n_n3349 +0-1- 1 +00-1 1 +.names preset ndn3_6 ndn3_7 ngfdn_3 n_n3675 +01-0 1 +0-10 1 +.names preset pdn n_n3116 nrq1_3 n_n3115 +0-1- 1 +00-1 1 +.names n_n3766 n_n3830 [1795] [6252] n_n3582 +--1- 1 +10-1 1 +.names n_n4351 [894] [1792] n_n3904 +--1 1 +11- 1 +.names preset pdn n_n4131 nrq1_3 n_n4130 +0-1- 1 +00-1 1 +.names n_n3085 n_n3250 [894] [1788] n_n3314 +---1 1 +111- 1 +.names n_n3976 [894] [1786] n_n3060 +--1 1 +11- 1 +.names n_n4222 [894] [1784] n_n3047 +--1 1 +11- 1 +.names pv1_4_4_ [994] [1780] n_n3837 +--1 1 +11- 1 +.names pv1_6_6_ [994] [1776] n_n3508 +--1 1 +11- 1 +.names n_n3608 [894] [1774] n_n3127 +--1 1 +11- 1 +.names [1771] [1772] [1773] n_n3235 +1-- 1 +-1- 1 +--1 1 +.names preset pdn n_n4213 nrq1_3 n_n4212 +0-1- 1 +00-1 1 +.names n_n3688 n_n3624 [894] [1767] n_n3759 +---1 1 +111- 1 +.names preset ndn3_7 ndn3_8 ngfdn_3 n_n4218 +01-0 1 +0-10 1 +.names preset pdn n_n3252 nrq1_3 n_n3251 +0-1- 1 +00-1 1 +.names n_n4366 [916] [934] [1034] n_n3382 +1-1- 1 +11-1 1 +01-0 1 +.names pv2_1_1_ [999] [1755] n_n3327 +--1 1 +11- 1 +.names [1752] [1753] [1754] n_n3987 +1-- 1 +-1- 1 +--1 1 +.names preset pdn n_n3348 nrq1_3 n_n3347 +0-1- 1 +00-1 1 +.names preset pdn n_n3544 nrq1_3 n_n3543 +0-1- 1 +00-1 1 +.names preset pdn n_n3101 nrq1_3 n_n3100 +0-1- 1 +00-1 1 +.names n_n4334 n_n3830 [1745] [6252] n_n4276 +--1- 1 +10-1 1 +.names n_n3556 n_n4122 [894] [1742] n_n3895 +---1 1 +111- 1 +.names n_n3495 [894] [1740] n_n3735 +--1 1 +11- 1 +.names pv4_6_6_ [997] [1736] n_n3049 +--1 1 +11- 1 +.names preset pdn n_n3650 nrq1_3 n_n3649 +0-1- 1 +00-1 1 +.names preset pdn n_n3307 nrq1_3 n_n3306 +0-1- 1 +00-1 1 +.names pv1_3_3_ [994] [1728] n_n4293 +--1 1 +11- 1 +.names n_n4334 [1014] [982] [1724] n_n3907 +01-- 1 +1-1- 1 +1--1 1 +.names [1006] [1716] [1719] [6332] n_n3579 +-1-- 1 +1-1- 1 +1--1 1 +.names preset pdn n_n4164 nrq1_3 n_n4163 +0-1- 1 +00-1 1 +.names n_n4145 [894] [1711] n_n3154 +--1 1 +11- 1 +.names preset pdn n_n3749 nrq1_3 n_n3748 +0-1- 1 +00-1 1 +.names [1707] [1708] n_n3271 +1- 1 +-1 1 +.names preset pdn n_n4347 nrq1_3 n_n4346 +0-1- 1 +00-1 1 +.names preset pdn n_n3826 nrq1_3 n_n3825 +0-1- 1 +00-1 1 +.names preset pdn n_n3360 nrq1_3 n_n3359 +0-1- 1 +00-1 1 +.names [1002] n_n4345 [1122] [1699] n_n3147 +---1 1 +111- 1 +100- 1 +.names preset pdn n_n3093 nrq1_3 n_n3092 +0-1- 1 +00-1 1 +.names preset pdn n_n3157 nrq1_3 n_n3156 +0-1- 1 +00-1 1 +.names n_n4349 [894] [1693] n_n3505 +--1 1 +11- 1 +.names preset pdn n_n3161 nrq1_3 n_n3160 +0-1- 1 +00-1 1 +.names n_n4233 [894] [1689] n_n3318 +--1 1 +11- 1 +.names n_n3892 [894] [1687] n_n3428 +--1 1 +11- 1 +.names n_n4125 [894] n_n4367 [1686] n_n3969 +---1 1 +111- 1 +.names n_n3242 n_n3170 [894] [1683] n_n3447 +---1 1 +111- 1 +.names pv4_7_7_ [997] [1679] n_n4081 +--1 1 +11- 1 +.names [1002] n_n4158 [1673] n_n3302 +--1 1 +11- 1 +.names n_n3936 n_n3099 [894] [1671] n_n3182 +---1 1 +111- 1 +.names preset pdn n_n3130 nrq1_3 n_n3129 +0-1- 1 +00-1 1 +.names preset nsr4_2 [973] n_n3430 +010 1 +.names preset n_n4047 n_n4126 [1659] n_n4046 +---1 1 +010- 1 +.names pv2_2_2_ [999] [1655] n_n3123 +--1 1 +11- 1 +.names preset pdn n_n3239 nrq1_3 n_n3238 +0-1- 1 +00-1 1 +.names [1647] [1648] n_n3972 +1- 1 +-1 1 +.names preset pdn n_n3890 nrq1_3 n_n3889 +0-1- 1 +00-1 1 +.names n_n3608 [894] [1642] [6272] n_n4001 +--1- 1 +11-- 1 +-1-1 1 +.names n_n3085 [894] [1640] n_n3090 +--1 1 +11- 1 +.names n_n4288 [894] [1638] n_n3983 +--1 1 +11- 1 +.names preset pdn n_n3326 nrq1_3 n_n3325 +0-1- 1 +00-1 1 +.names [1006] [1630] [1633] [6337] n_n3540 +-1-- 1 +1-1- 1 +1--1 1 +.names preset pdn nsr4_2 [973] n_n125 +1--- 1 +-1-- 1 +--11 1 +.names [1006] [1621] [1623] [6338] n_n3693 +-1-- 1 +1-1- 1 +1--1 1 +.names preset pdn n_n4375 nrq1_3 n_n4373 +0-1- 1 +00-1 1 +.names preset nak3_17 [1041] n_n3866 +001 1 +.names preset pdn n_n4290 nrq1_3 n_n4289 +0-1- 1 +00-1 1 +.names [1004] n_n4158 [1614] n_n3459 +--1 1 +11- 1 +.names [1612] [1613] n_n4121 +1- 1 +-1 1 +.names preset pdn n_n3774 nrq1_3 n_n3773 +0-1- 1 +00-1 1 +.names preset pdn n_n3014 nrq1_3 n_n3013 +0-1- 1 +00-1 1 +.names preset pdn n_n4241 nrq1_3 n_n4239 +0-1- 1 +00-1 1 +.names n_n4201 [894] [1604] n_n3950 +--1 1 +11- 1 +.names n_n4145 [894] [1075] [1602] n_n3236 +---1 1 +111- 1 +010- 1 +.names pv6_2_2_ [990] [1598] n_n3530 +--1 1 +11- 1 +.names pv6_4_4_ [990] [1594] n_n3033 +--1 1 +11- 1 +.names preset pdn n_n3551 nrq1_3 n_n3550 +0-1- 1 +00-1 1 +.names preset pdn n_n3379 nrq1_3 n_n3378 +0-1- 1 +00-1 1 +.names n_n4275 [1042] [1580] n_n3009 +--1 1 +11- 1 +.names preset pdn n_n3570 nrq1_3 n_n3569 +0-1- 1 +00-1 1 +.names pv2_5_5_ [999] [1574] n_n3853 +--1 1 +11- 1 +.names [1565] [6350] n_n131 +1- 1 +-1 1 +.names pv2_7_7_ [999] [1561] n_n3450 +--1 1 +11- 1 +.names preset pdn n_n4037 nrq1_3 n_n4036 +0-1- 1 +00-1 1 +.names n_n3898 [894] [1076] [1557] n_n3406 +---1 1 +111- 1 +010- 1 +.names [1551] [1552] n_n4228 +1- 1 +-1 1 +.names pv6_1_1_ [990] [1547] n_n3701 +--1 1 +11- 1 +.names preset pdn n_n3339 nrq1_3 n_n3338 +0-1- 1 +00-1 1 +.names pv10_5_5_ [992] [1541] n_n4361 +--1 1 +11- 1 +.names n_n4334 n_n3483 [1014] [1538] n_n3466 +---1 1 +101- 1 +.names preset n_n4099 [1119] [6349] n_n3355 +0011 1 +0101 1 +.names preset pdn n_n4185 nrq1_3 n_n4184 +0-1- 1 +00-1 1 +.names n_n3934 [894] n_n4367 [1534] n_n3068 +---1 1 +111- 1 +.names preset pdn n_n3643 nrq1_3 n_n3642 +0-1- 1 +00-1 1 +.names n_n4229 [894] [1529] n_n3402 +--1 1 +11- 1 +.names n_n4145 [894] [1527] n_n3056 +--1 1 +11- 1 +.names n_n4095 [894] [1524] [6321] n_n3019 +--1- 1 +11-- 1 +-1-1 1 +.names preset pdn n_n3828 nrq1_3 n_n3827 +0-1- 1 +00-1 1 +.names n_n3085 n_n3250 [894] [1520] n_n3629 +---1 1 +111- 1 +.names n_n3968 [894] [1518] n_n3137 +--1 1 +11- 1 +.names preset pdn ngfdn_3 nrq1_3 n_n126 +1--- 1 +-1-- 1 +--00 1 +.names n_n3922 [894] [1514] n_n4063 +--1 1 +11- 1 +.names n_n4366 [894] n_n4367 [1513] n_n3677 +---1 1 +111- 1 +.names [894] n_n3741 [1510] n_n3285 +--1 1 +11- 1 +.names [1508] [1509] n_n3308 +1- 1 +-1 1 +.names preset pdn n_n4059 nrq1_3 n_n4058 +0-1- 1 +00-1 1 +.names n_n3898 [894] [1504] n_n3435 +--1 1 +11- 1 +.names preset nen3_10 ndn3_9 ngfdn_3 n_n3635 +01-0 1 +0-10 1 +.names preset pdn n_n3461 nrq1_3 n_n3460 +0-1- 1 +00-1 1 +.names n_n4012 [982] [1500] n_n4011 +--1 1 +11- 1 +.names preset pdn n_n3051 nrq1_3 n_n3050 +0-1- 1 +00-1 1 +.names n_n4047 [894] n_n4367 [1497] n_n3072 +---1 1 +111- 1 +.names n_n3898 [894] [1494] n_n3775 +--1 1 +11- 1 +.names n_n3832 [1492] [6255] [6354] n_n3199 +-1-1 1 +1-11 1 +.names pv10_2_2_ [992] [1488] n_n3025 +--1 1 +11- 1 +.names [1486] [1487] n_n3058 +1- 1 +-1 1 +.names pv1_7_7_ [994] [1482] n_n3258 +--1 1 +11- 1 +.names preset pdn n_n3504 nrq1_3 n_n3503 +0-1- 1 +00-1 1 +.names n_n4045 [1477] [6356] [6357] n_n130 +---1 1 +11-- 1 +1-1- 1 +.names [1006] [1470] [1472] [6358] n_n121 +00-- 1 +-000 1 +.names n_n4324 [894] n_n4367 [1468] n_n3134 +---1 1 +111- 1 +.names n_n4383 [894] [1465] n_n4370 +--1 1 +11- 1 +.names n_n4229 [894] [1079] [1463] n_n4234 +---1 1 +111- 1 +010- 1 +.names preset pdn n_n3040 nrq1_3 n_n3039 +0-1- 1 +00-1 1 +.names preset pdn n_n3874 nrq1_3 n_n3873 +0-1- 1 +00-1 1 +.names preset pdn n_n3999 nrq1_3 n_n3998 +0-1- 1 +00-1 1 +.names n_n4122 [894] [1455] n_n3222 +--1 1 +11- 1 +.names preset pdn ndn1_34 n_n3036 +001 1 +.names pv10_1_1_ [992] [1451] n_n3062 +--1 1 +11- 1 +.names n_n3810 n_n4015 [1449] n_n3017 +--1 1 +11- 1 +.names n_n4258 [894] [1447] n_n3212 +--1 1 +11- 1 +.names preset pdn n_n3095 nrq1_3 n_n3094 +0-1- 1 +00-1 1 +.names preset pdn n_n3663 nrq1_3 n_n3662 +0-1- 1 +00-1 1 +.names n_n3724 n_n3814 [896] [947] n_n3217 +1--1 1 +011- 1 +.names preset pdn n_n3038 nrq1_3 n_n3037 +0-1- 1 +00-1 1 +.names n_n4337 [894] [1437] n_n3368 +--1 1 +11- 1 +.names pv11_0_0_ [988] [1433] n_n3030 +--1 1 +11- 1 +.names pv11_4_4_ [988] [1429] n_n3494 +--1 1 +11- 1 +.names n_n3556 n_n4122 [894] [1427] n_n3711 +---1 1 +111- 1 +.names n_n4074 n_n3578 [894] [1425] n_n3088 +---1 1 +111- 1 +.names preset pdn n_n3211 nrq1_3 n_n3210 +0-1- 1 +00-1 1 +.names preset pdn n_n3367 nrq1_3 n_n3366 +0-1- 1 +00-1 1 +.names preset pdn n_n3434 nrq1_3 n_n3433 +0-1- 1 +00-1 1 +.names n_n4233 [894] [1416] [6303] n_n3125 +--1- 1 +11-- 1 +-1-1 1 +.names n_n3688 n_n3624 [894] [1414] n_n4190 +---1 1 +111- 1 +.names n_n3876 [894] [1412] n_n4134 +--1 1 +11- 1 +.names preset pdn n_n3053 nrq1_3 n_n3052 +0-1- 1 +00-1 1 +.names preset pdn n_n3938 nrq1_3 n_n3937 +0-1- 1 +00-1 1 +.names preset n_n3769 n_n4126 [1402] n_n3632 +---1 1 +010- 1 +.names n_n3936 n_n3099 [894] [1400] n_n4387 +---1 1 +111- 1 +.names nen3_10 nsr3_17 nak3_17 [944] n_n127 +---1 1 +01-- 1 +-10- 1 +.names preset pdn n_n3903 nrq1_3 n_n3902 +0-1- 1 +00-1 1 +.names n_n3658 n_n4367 [6268] [6361] n_n3684 +1--1 1 +-111 1 +.names preset nrq3_11 nsr3_14 ngfdn_3 n_n3046 +01-0 1 +0-00 1 +.names [1391] [1392] [1393] n_n3817 +1-- 1 +-1- 1 +--1 1 +.names pv6_3_3_ [990] [1387] n_n3374 +--1 1 +11- 1 +.names n_n4316 [894] [1385] n_n3462 +--1 1 +11- 1 +.names preset pdn n_n3175 nrq1_3 n_n3174 +0-1- 1 +00-1 1 +.names n_n3657 [894] [1381] n_n3054 +--1 1 +11- 1 +.names n_n3495 [894] [1378] [6310] n_n3200 +--1- 1 +11-- 1 +-1-1 1 +.names n_n4095 [894] [1375] [6321] n_n3383 +--1- 1 +11-- 1 +-1-1 1 +.names preset pdn n_n4077 nrq1_3 n_n4076 +0-1- 1 +00-1 1 +.names preset pdn n_n3142 nrq1_3 n_n3141 +0-1- 1 +00-1 1 +.names preset n_n3901 n_n4126 [1365] n_n3289 +---1 1 +010- 1 +.names n_n3934 n_n3976 [916] [1362] n_n3552 +---1 1 +011- 1 +.names n_n4227 n_n3830 [1360] [6252] n_n3821 +--1- 1 +10-1 1 +.names n_n4160 [894] [1357] n_n3721 +--1 1 +11- 1 +.names n_n4182 [894] [1355] n_n4307 +--1 1 +11- 1 +.names pv4_0_0_ [997] [1351] n_n3229 +--1 1 +11- 1 +.names pv4_4_4_ [997] [1347] n_n3021 +--1 1 +11- 1 +.names preset pdn n_n3836 nrq1_3 n_n3835 +0-1- 1 +00-1 1 +.names preset pdn n_n3470 nrq1_3 n_n3469 +0-1- 1 +00-1 1 +.names n_n4157 [894] [1341] n_n3329 +--1 1 +11- 1 +.names n_n3099 [894] [1339] n_n3881 +--1 1 +11- 1 +.names pv10_6_6_ [992] [1335] n_n3031 +--1 1 +11- 1 +.names n_n3810 n_n4158 [1333] n_n4156 +--1 1 +11- 1 +.names preset ndn3_8 ndn3_9 ngfdn_3 n_n4086 +01-0 1 +0-10 1 +.names pv1_1_1_ [994] [1329] n_n3045 +--1 1 +11- 1 +.names preset pdn n_n3190 nrq1_3 n_n3189 +0-1- 1 +00-1 1 +.names [1006] [1323] [1325] [6366] n_n4028 +-1-- 1 +1-1- 1 +1--1 1 +.names preset pdn n_n3042 nrq1_3 n_n3041 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[1271] n_n3122 +--1 1 +11- 1 +.names n_n3814 n_n3830 [1270] [6252] n_n3512 +--1- 1 +10-1 1 +.names n_n4159 n_n3976 [894] [1267] n_n3571 +---1 1 +011- 1 +101- 1 +.names n_n4270 [894] [1265] n_n4165 +--1 1 +11- 1 +.names [1004] n_n3975 n_n3974 [1263] n_n3519 +---1 1 +101- 1 +110- 1 +.names n_n3841 [894] [1261] n_n3392 +--1 1 +11- 1 +.names [1259] [1260] n_n4094 +1- 1 +-1 1 +.names preset pdn n_n3863 nrq1_3 n_n3862 +0-1- 1 +00-1 1 +.names preset pdn n_n3720 nrq1_3 n_n3719 +0-1- 1 +00-1 1 +.names preset nrq3_11 ngfdn_3 n_n3810 +010 1 +.names pv10_0_0_ [992] [1251] n_n3755 +--1 1 +11- 1 +.names n_n3458 [894] [1248] [6291] n_n3665 +--1- 1 +11-- 1 +-1-1 1 +.names n_n4299 [894] [1246] n_n3340 +--1 1 +11- 1 +.names preset pdn n_n3529 nrq1_3 n_n3528 +0-1- 1 +00-1 1 +.names n_n3756 [894] [1242] n_n4207 +--1 1 +11- 1 +.names n_n4324 [916] [934] [1062] n_n3585 +1-1- 1 +11-1 1 +01-0 1 +.names n_n3035 n_n4157 [894] [1232] n_n3336 +---1 1 +111- 1 +.names n_n4227 [947] [1230] [1586] n_n3026 +--1- 1 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+.names preset n_n4057 [1068] n_n3473 +011 1 +.names preset pdn n_n3674 nrq1_3 n_n3673 +0-1- 1 +00-1 1 +.names n_n3959 [1069] [1171] [1172] n_n3592 +--1- 1 +---1 1 +11-- 1 +.names [1002] n_n3975 n_n3974 [1168] n_n3607 +---1 1 +101- 1 +110- 1 +.names [1165] [1166] [1167] n_n3292 +1-- 1 +-1- 1 +--1 1 +.names preset pdn n_n4018 nrq1_3 n_n4017 +0-1- 1 +00-1 1 +.names preset pdn n_n4354 nrq1_3 n_n4352 +0-1- 1 +00-1 1 +.names preset pdn n_n3797 nrq1_3 n_n3796 +0-1- 1 +00-1 1 +.names n_n4316 [894] [983] n_n3737 +--1 1 +11- 1 +.names n_n4392 [894] [978] [6306] n_n3644 +--1- 1 +11-- 1 +-1-1 1 +.names n_n3810 n_n3363 [1128] [976] n_n3059 +---1 1 +111- 1 +100- 1 +.names n_n4211 n_n3657 [894] [974] n_n3535 +---1 1 +111- 1 +.names n_n4074 n_n3578 [894] [971] n_n3804 +---1 1 +111- 1 +.names preset pdn n_n3087 nrq1_3 n_n3086 +0-1- 1 +00-1 1 +.names preset pdn n_n4105 nrq1_3 n_n4104 +0-1- 1 +00-1 1 +.names preset pdn n_n3262 nrq1_3 n_n3261 +0-1- 1 +00-1 1 +.names preset n_n4125 n_n4126 [6385] n_n4124 +--11 1 +010- 1 +.names n_n3814 [896] [946] n_n3813 +--1 1 +01- 1 +.names n_n3832 [921] [6386] [6389] n_n132 +---0 1 +00-- 1 +-00- 1 +.names nsr3_3 [944] nrq3_2 [911] n_n123 +-1-- 1 +1-0- 1 +1--1 1 +.names preset ndn3_8 ndn3_9 [988] +010 1 +.names preset n_n3198 n_n3707 n_n3709 [896] +0011 1 +.names n_n3604 n_n3658 n_n4335 [6268] [1016] +11-- 1 +1--0 1 +100- 1 +-011 1 +.names preset ndn3_7 ndn3_8 [992] +010 1 +.names preset pdn nsr1_2 n_n3765 [894] +0000 1 +.names preset n_n4057 n_n3557 n_n4056 [916] +0101 1 +.names preset n_n4126 [934] +00 1 +.names pdn n_n4108 ndn1_34 nrq1_3 [1020] +-1-- 1 +1-0- 1 +0--1 1 +.names n_n3916 [1096] n_n4069 +11 1 +00 1 +.names n_n3363 n_n3362 [941] [1129] n_n4015 +11-1 1 +1-01 1 +-101 1 +00-0 1 +0-10 1 +-010 1 +.names preset ndn3_10 nen3_10 [1004] +001 1 +.names preset ndn3_6 ndn3_7 [990] +010 1 +.names pready_0_0_ ndn3_4 nsr3_3 nrq3_2 [1021] +-1-- 1 +--0- 1 +1--1 1 +.names pready_0_0_ nsr3_3 nrq3_2 [6284] [994] +-0-1 1 +1-11 1 +.names n_n4360 n_n3653 [905] [906] n_n3563 +0--1 1 +-1-1 1 +011- 1 +.names n_n4067 n_n3788 n_n3830 [6254] [1022] +1--- 1 +-1-- 1 +---0 1 +0-1- 1 +.names preset ndn3_15 ngfdn_3 [1002] +001 1 +.names preset ndn3_5 ndn3_6 [997] +010 1 +.names preset n_n4126 n_n3500 [1006] +01- 1 +0-1 1 +.names preset ndn3_4 ndn3_5 [999] +010 1 +.names n_n4093 n_n3788 [1013] [2264] nak3_17 +0--- 1 +-11- 1 +--11 1 +.names n_n3916 n_n4040 n_n4039 [1096] n_n4038 +0111 1 +1011 1 +1101 1 +0001 1 +1110 1 +0010 1 +0100 1 +1000 1 +.names n_n3841 [1078] n_n3653 +11 1 +00 1 +.names preset pdn [944] +1- 1 +-1 1 +.names preset_0_0_ nlc1_2 nsr1_2 n_n4151 [1028] +-1-- 1 +001- 1 +0-11 1 +.names n_n4316 n_n4315 n_n4155 n_n4116 +111 1 +001 1 +010 1 +100 1 +.names n_n3988 n_n3898 [1076] n_n3622 n_n3689 +0111 1 +1011 1 +1101 1 +0001 1 +1110 1 +0010 1 +0100 1 +1000 1 +.names n_n4012 [896] [1012] [6330] [1014] +1111 1 +.names n_n4345 n_n4019 n_n3884 [1086] n_n4158 +11-1 1 +1-11 1 +-111 1 +00-0 1 +0-00 1 +-000 1 +.names pready_0_0_ nsr3_3 nrq3_2 [6333] [973] +1--- 1 +0--- 1 +-0-- 1 +--0- 1 +---1 1 +.names n_n4067 n_n3788 n_n3830 [6254] [1041] +1--- 1 +-001 1 +.names n_n4145 [1075] n_n4079 +11 1 +00 1 +.names n_n3724 n_n4227 n_n3814 [1012] +111 1 +.names [947] [1582] [1584] [1586] [1042] +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names n_n3898 [1076] n_n3745 +11 1 +00 1 +.names preset_0_0_ nlc1_2 nsr1_2 n_n4151 nrq1_3 +--0- 1 +10-- 1 +-1-0 1 +.names n_n4160 n_n4222 n_n4159 n_n3976 n_n3741 +010- 1 +100- 1 +0111 1 +1011 1 +1110 1 +0010 1 +.names n_n3832 [1726] [6255] [6257] [982] +-1-- 1 +0--1 1 +--01 1 +.names n_n4229 [1079] n_n4256 +11 1 +00 1 +.names n_n3832 [1588] [6255] [6257] [947] +-1-- 1 +0--1 1 +--01 1 +.names n_n4229 n_n3818 [1079] n_n3595 n_n4084 +0111 1 +1011 1 +1101 1 +0001 1 +1110 1 +0010 1 +0100 1 +1000 1 +.names n_n4159 n_n3976 n_n4133 +01 1 +10 1 +.names nrq3_11 ngfdn_3 nrq3_12 +10 1 +.names n_n3788 [2264] [6254] n_n3832 +001 1 +.names n_n3851 n_n3831 n_n4026 n_n3852 [1015] +111- 1 +11-1 1 +-101 1 +.names n_n3709 [1137] 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1 +.names preset pdn n_n3091 nrq1_3 [1640] +011- 1 +0-10 1 +.names preset pdn n_n4003 nrq1_3 [1642] +011- 1 +0-10 1 +.names preset ndn3_10 n_n4145 nen3_10 [1647] +011- 1 +0-10 1 +.names [1004] [1094] [1898] [1899] [1648] +111- 1 +11-1 1 +1000 1 +.names preset ndn3_4 ndn3_5 n_n3978 [1655] +00-1 1 +0-11 1 +.names n_n3916 [916] [1038] [1659] +111 1 +010 1 +.names preset pdn n_n3183 nrq1_3 [1671] +011- 1 +0-10 1 +.names preset ndn3_15 n_n4288 ngfdn_3 [1673] +011- 1 +0-10 1 +.names preset ndn3_5 ndn3_6 n_n4270 [1679] +00-1 1 +0-11 1 +.names preset pdn n_n3449 nrq1_3 [1683] +011- 1 +0-10 1 +.names preset pdn n_n3971 nrq1_3 [1686] +011- 1 +0-10 1 +.names preset pdn n_n3429 nrq1_3 [1687] +011- 1 +0-10 1 +.names preset pdn n_n3319 nrq1_3 [1689] +011- 1 +0-10 1 +.names preset pdn n_n3506 nrq1_3 [1693] +011- 1 +0-10 1 +.names preset ndn3_15 n_n3458 ngfdn_3 [1699] +011- 1 +0-10 1 +.names preset ndn3_15 n_n4233 ngfdn_3 [1707] +011- 1 +0-10 1 +.names [1002] n_n3324 n_n3243 [914] [1708] +1011 1 +1101 1 +1110 1 +1000 1 +.names preset pdn n_n3155 nrq1_3 [1711] +011- 1 +0-10 1 +.names preset n_n3955 n_n4126 n_n3500 [1716] +0100 1 +.names n_n4201 n_n3656 [2011] [1719] +11- 1 +1-1 1 +.names n_n4012 [896] [1724] +01 1 +.names n_n4275 n_n3766 [896] [1012] [1726] +0-1- 1 +-01- 1 +--10 1 +.names preset n_n4294 [1155] [1728] +011 1 +.names preset ndn3_5 ndn3_6 n_n4251 [1736] +00-1 1 +0-11 1 +.names preset pdn n_n3736 nrq1_3 [1740] +011- 1 +0-10 1 +.names preset pdn n_n3896 nrq1_3 [1742] +011- 1 +0-10 1 +.names preset pdn n_n4279 nrq1_3 [1745] +011- 1 +0-10 1 +.names preset n_n4362 n_n3832 [6255] [1752] +0111 1 +.names n_n3988 n_n3832 [6255] [6257] [1753] +10-1 1 +1-01 1 +.names n_n3988 [896] n_n3745 n_n3622 [1754] +0111 1 +1101 1 +1110 1 +0100 1 +.names preset ndn3_4 ndn3_5 n_n3328 [1755] +00-1 1 +0-11 1 +.names preset pdn n_n3761 nrq1_3 [1767] +011- 1 +0-10 1 +.names preset n_n3946 n_n3832 [6255] [1771] +0111 1 +.names n_n3995 n_n3832 [6255] [6257] [1772] +10-1 1 +1-01 1 +.names n_n3995 [896] n_n4116 n_n3994 [1773] +0111 1 +1101 1 +1110 1 +0100 1 +.names preset pdn n_n3128 nrq1_3 [1774] +011- 1 +0-10 1 +.names preset n_n3919 [1155] [1776] +011 1 +.names preset n_n3886 [1155] [1780] +011 1 +.names preset pdn n_n3048 nrq1_3 [1784] +011- 1 +0-10 1 +.names preset pdn n_n3061 nrq1_3 [1786] +011- 1 +0-10 1 +.names preset pdn n_n3316 nrq1_3 [1788] +011- 1 +0-10 1 +.names preset pdn n_n3906 nrq1_3 [1792] +011- 1 +0-10 1 +.names preset pdn n_n3583 nrq1_3 [1795] +011- 1 +0-10 1 +.names preset pdn n_n3358 nrq1_3 [1800] +011- 1 +0-10 1 +.names preset pdn n_n4243 nrq1_3 [1806] +011- 1 +0-10 1 +.names preset ndn3_6 n_n4337 ndn3_7 [1812] +001- 1 +0-11 1 +.names preset pdn n_n3207 nrq1_3 [1825] +011- 1 +0-10 1 +.names preset pdn n_n3465 nrq1_3 [1830] +011- 1 +0-10 1 +.names pdn ndn1_34 nrq1_3 [6325] [1833] +11-1 1 +0-01 1 +-101 1 +.names preset n_n3892 ndn3_6 ndn3_7 [1837] +010- 1 +01-1 1 +.names preset ndn3_5 n_n4383 ndn3_6 [1843] +001- 1 +0-11 1 +.names preset pdn n_n4286 nrq1_3 [1847] +011- 1 +0-10 1 +.names preset pdn n_n4189 nrq1_3 [1849] +011- 1 +0-10 1 +.names preset pdn n_n3576 nrq1_3 [1853] +011- 1 +0-10 1 +.names preset pdn n_n4172 nrq1_3 [1859] +011- 1 +0-10 1 +.names preset pdn n_n3111 nrq1_3 [1868] +011- 1 +0-10 1 +.names preset n_n3035 ndn3_8 ndn3_9 [1870] +010- 1 +01-1 1 +.names preset pdn n_n3627 nrq1_3 [1874] +011- 1 +0-10 1 +.names preset pdn n_n3044 nrq1_3 [1876] +011- 1 +0-10 1 +.names preset pdn n_n3376 nrq1_3 [1881] +011- 1 +0-10 1 +.names preset pdn n_n3118 nrq1_3 [1882] +011- 1 +0-10 1 +.names preset n_n3242 nrq3_11 ngfdn_3 [1884] +010- 1 +01-1 1 +.names n_n3810 n_n3324 n_n3243 [914] [1885] +1011 1 +1101 1 +1110 1 +1000 1 +.names ndn3_15 n_n3556 n_n4122 ngfdn_3 [1892] +0111 1 +.names ndn3_10 n_n3919 nen3_10 [1893] +011 1 +.names n_n4145 nrq3_11 ngfdn_3 [1894] +110 1 +.names ndn3_10 nen3_10 n_n4062 [1896] +011 1 +.names n_n4345 n_n4019 n_n3884 [1104] [1898] +11-1 1 +1-11 1 +-111 1 +.names n_n3334 [1903] [1904] [1905] [1899] +11-- 1 +1-1- 1 +1--1 1 +.names ndn3_10 n_n3854 nen3_10 [1901] +011 1 +.names ndn3_15 n_n3035 n_n4157 ngfdn_3 [1903] +0111 1 +.names n_n3511 ndn3_10 nen3_10 [1904] +101 1 +.names n_n3898 nrq3_11 ngfdn_3 [1905] +110 1 +.names ndn3_15 n_n3242 n_n3170 ngfdn_3 [1908] +0111 1 +.names ndn3_10 nen3_10 n_n3259 [1909] +011 1 +.names nrq3_11 ngfdn_3 n_n3841 [1910] +101 1 +.names ndn3_10 n_n3451 nen3_10 [1912] +011 1 +.names preset pdn n_n3113 nrq1_3 [1914] +011- 1 +0-10 1 +.names preset pdn n_n3173 nrq1_3 [1919] +011- 1 +0-10 1 +.names preset pdn n_n3221 nrq1_3 [1921] +011- 1 +0-10 1 +.names preset n_n3876 n_n3832 [6255] [1925] +0111 1 +.names n_n4040 n_n3832 [6255] [6257] [1926] +10-1 1 +1-01 1 +.names n_n4040 [896] n_n4069 n_n4039 [1927] +0111 1 +1101 1 +1110 1 +0100 1 +.names preset n_n3556 ndn3_8 ndn3_9 [1928] +010- 1 +01-1 1 +.names preset pdn n_n3733 nrq1_3 [1932] +011- 1 +0-10 1 +.names preset pdn n_n3231 nrq1_3 [1940] +011- 1 +0-10 1 +.names preset pdn n_n3313 nrq1_3 [1944] +011- 1 +0-10 1 +.names preset pdn n_n3079 nrq1_3 [1946] +011- 1 +0-10 1 +.names preset n_n3688 nrq3_11 ngfdn_3 [1949] +010- 1 +01-1 1 +.names preset pdn n_n3344 nrq1_3 [1953] +011- 1 +0-10 1 +.names preset n_n4071 ndn3_6 ndn3_7 [1957] +010- 1 +01-1 1 +.names preset pdn n_n3012 nrq1_3 [1961] +011- 1 +0-10 1 +.names preset n_n4222 ndn3_10 nen3_10 [1963] +011- 1 +01-0 1 +.names preset ndn3_5 n_n4160 ndn3_6 [1965] +001- 1 +0-11 1 +.names preset pdn n_n3517 nrq1_3 [1969] +011- 1 +0-10 1 +.names n_n3707 n_n3709 n_n135 [6290] [1971] +10-- 1 +1-1- 1 +1--0 1 +.names preset ndn3_4 ndn3_5 n_n3281 [1976] +00-1 1 +0-11 1 +.names preset pdn n_n3764 nrq1_3 [1980] +011- 1 +0-10 1 +.names preset pdn n_n3549 nrq1_3 [1984] +011- 1 +0-10 1 +.names preset n_n3876 ndn3_7 ndn3_8 [1986] +010- 1 +01-1 1 +.names preset pdn n_n3729 nrq1_3 [1990] +011- 1 +0-10 1 +.names preset pdn n_n3525 nrq1_3 [1992] +011- 1 +0-10 1 +.names preset n_n3916 ndn3_10 nen3_10 [1996] +011- 1 +01-0 1 +.names preset ndn3_15 n_n3495 ngfdn_3 [1998] +011- 1 +0-10 1 +.names preset n_n4211 ndn3_8 ndn3_9 [2000] +010- 1 +01-1 1 +.names preset pdn n_n3670 nrq1_3 [2005] +011- 1 +0-10 1 +.names preset n_n4381 n_n4126 n_n3500 [2007] +0100 1 +.names n_n3892 n_n3656 [2011] [2009] +11- 1 +1-1 1 +.names n_n3493 n_n4045 n_n4367 [6299] [2011] +000- 1 +0-01 1 +.names preset n_n3858 [1155] [2023] +011 1 +.names preset pdn n_n3270 nrq1_3 [2027] +011- 1 +0-10 1 +.names preset n_n4074 nrq3_11 ngfdn_3 [2029] +010- 1 +01-1 1 +.names ndn3_15 n_n4074 n_n3578 ngfdn_3 [2035] +0111 1 +.names ndn3_10 n_n3886 nen3_10 [2036] +011 1 +.names n_n3916 nrq3_11 ngfdn_3 [2037] +110 1 +.names ndn3_10 nen3_10 n_n4021 [2039] +011 1 +.names n_n3281 ndn3_10 nen3_10 [2044] +101 1 +.names n_n4229 nrq3_11 ngfdn_3 [1079] [2045] +1101 1 +0100 1 +.names ndn3_15 n_n3085 n_n3250 ngfdn_3 [2046] +0111 1 +.names ndn3_10 n_n4294 nen3_10 [2047] +011 1 +.names n_n4229 nrq3_11 ngfdn_3 [2048] +110 1 +.names n_n3363 n_n3362 [1088] [941] [2049] +111- 1 +1-10 1 +-110 1 +.names n_n3981 [2174] [6281] [2050] +11- 1 +1-1 1 +.names preset pdn n_n3133 nrq1_3 [2051] +011- 1 +0-10 1 +.names n_n3786 n_n3785 [6287] [2060] +00- 1 +0-1 1 +.names n_n4145 n_n4080 [1075] n_n4078 [2061] +0111 1 +1101 1 +0010 1 +1000 1 +.names preset n_n4224 ndn3_5 ndn3_6 [2122] +010- 1 +01-1 1 +.names preset n_n4392 ndn3_15 ngfdn_3 [2126] +011- 1 +01-0 1 +.names preset n_n3511 [1155] [2141] +011 1 +.names preset pdn n_n3780 nrq1_3 [2153] +011- 1 +0-10 1 +.names preset n_n4349 ndn3_6 ndn3_7 [2162] +010- 1 +01-1 1 +.names preset n_n4316 ndn3_10 nen3_10 [2166] +011- 1 +01-0 1 +.names ndn3_10 n_n3978 nen3_10 [2173] +011 1 +.names n_n4316 nrq3_12 n_n4315 n_n4155 [2174] +1111 1 +0101 1 +0110 1 +1100 1 +.names ndn3_15 n_n4211 n_n3657 ngfdn_3 [2175] +0111 1 +.names n_n3858 ndn3_10 nen3_10 [2176] +101 1 +.names n_n4316 nrq3_11 ngfdn_3 [2177] +110 1 +.names nrq3_11 n_n4159 n_n3976 ngfdn_3 [2182] +1010 1 +1100 1 +.names ndn3_15 n_n3688 n_n3624 ngfdn_3 [2183] +0111 1 +.names ndn3_10 nen3_10 n_n3878 [2184] +011 1 +.names nrq3_11 n_n3976 ngfdn_3 [2185] +110 1 +.names ndn3_10 n_n3328 nen3_10 [2187] +011 1 +.names nrq3_11 ngfdn_3 n_n3741 [2188] +101 1 +.names n_n3936 ndn3_15 ngfdn_3 n_n3099 [2189] +1011 1 +.names ndn3_10 nen3_10 n_n3208 [2190] +011 1 +.names n_n4222 nrq3_11 ngfdn_3 [2191] +110 1 +.names preset pdn n_n3793 nrq1_3 [2192] +011- 1 +0-10 1 +.names preset pdn n_n3497 nrq1_3 [2195] +011- 1 +0-10 1 +.names preset pdn n_n3098 nrq1_3 [2198] +011- 1 +0-10 1 +.names preset pdn n_n3687 nrq1_3 [2202] +011- 1 +0-10 1 +.names preset pdn n_n3225 nrq1_3 [2224] +011- 1 +0-10 1 +.names preset n_n4258 ndn3_7 ndn3_8 [2226] +010- 1 +01-1 1 +.names preset n_n4360 n_n3832 [6255] [2240] +0111 1 +.names n_n3726 n_n3832 [6255] [6257] [2241] +10-1 1 +1-01 1 +.names n_n3726 [896] n_n3653 n_n3888 [2242] +0111 1 +1101 1 +1110 1 +0100 1 +.names preset pdn n_n3008 nrq1_3 [2259] +011- 1 +0-10 1 +.names preset n_n3743 n_n3832 [6255] [2261] +0111 1 +.names n_n3574 n_n3832 [6255] [6257] [2262] +10-1 1 +1-01 1 +.names n_n3574 [896] n_n3741 [923] [2263] +0111 1 +1101 1 +1110 1 +0100 1 +.names n_n3851 n_n4067 n_n4026 n_n3852 [2264] +001- 1 +-000 1 +.names preset n_n3936 ndn3_8 ndn3_9 [2270] +010- 1 +01-1 1 +.names preset pdn n_n4142 nrq1_3 [2275] +011- 1 +0-10 1 +.names n_n4159 n_n3976 n_n3756 [6250] +010 1 +100 1 +.names n_n4182 n_n4330 [6251] +00 1 +.names n_n3833 n_n4067 [894] n_n3563 [6252] +111- 1 +1-10 1 +-010 1 +.names nen3_10 nsr3_17 n_n4093 [6254] +111 1 +.names [1015] n_n3709 [6255] +10 1 +.names preset n_n3198 n_n3707 n_n3709 [6257] +01-- 1 +0-0- 1 +0--0 1 +.names n_n4157 n_n3035 [6259] +11 1 +.names n_n4349 n_n4071 n_n3892 n_n4337 [6265] +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names n_n3968 n_n3922 n_n4201 n_n3533 [6266] +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names n_n4045 nsr3_17 nsr3_14 [6268] +101 1 +.names n_n3557 n_n4057 [6270] +01 1 +.names n_n3624 n_n3688 [6272] +11 1 +.names n_n4125 n_n4367 nrq3_15 [2187] [6275] +---1 1 +111- 1 +.names ndn3_10 nen3_10 n_n3931 [2182] [6278] +---1 1 +011- 1 +.names n_n3901 n_n4367 nrq3_15 [2173] [6281] +---1 1 +111- 1 +.names ndn3_4 preset [6284] +00 1 +.names n_n4145 n_n4080 [1075] n_n4078 [6287] +0-1- 1 +1-0- 1 +1011 1 +0001 1 +1110 1 +0100 1 +.names n_n3726 n_n3653 n_n3888 [2061] [6289] +-1-- 1 +---1 1 +001- 1 +100- 1 +.names n_n4296 [2060] [6289] [6290] +11- 1 +1-1 1 +.names n_n3578 n_n4074 [6291] +11 1 +.names n_n3769 n_n4367 nrq3_15 [2044] [6295] +---1 1 +111- 1 +.names n_n4047 n_n4367 nrq3_15 [2039] [6296] +---1 1 +111- 1 +.names nsr3_14 nsr3_17 [6299] +10 1 +.names n_n4381 n_n4305 n_n4357 [1008] [6300] +-11- 1 +1--1 1 +.names n_n3493 preset [6302] +10 1 +.names n_n3170 n_n3242 [6303] +11 1 +.names n_n3099 n_n3936 [6306] +11 1 +.names n_n3831 n_n4026 n_n3852 [6309] +0-- 1 +-1- 1 +-00 1 +.names n_n3657 n_n4211 [6310] +11 1 +.names n_n4324 n_n4367 nrq3_15 [1912] [6312] +---1 1 +111- 1 +.names n_n4366 n_n4367 nrq3_15 [1901] [6317] +---1 1 +111- 1 +.names n_n3475 n_n4367 nrq3_15 [1896] [6318] +---1 1 +111- 1 +.names n_n4122 n_n3556 [6321] +11 1 +.names n_n3250 n_n3085 [6322] +11 1 +.names tin_pready_0_0_ n_n4108 n_n3354 nsr3_3 [6324] +00-1 1 +0-01 1 +-101 1 +.names n_n3354 preset [6325] +10 1 +.names n_n3766 n_n4275 [6330] +11 1 +.names n_n3955 n_n3954 n_n4305 [1008] [6332] +1--1 1 +011- 1 +101- 1 +.names nlc3_3 nlak4_2 n_n4263 [6333] +-1- 1 +1-0 1 +.names n_n4052 [1008] [1632] [6337] +--1 1 +11- 1 +.names n_n4099 n_n4305 [1119] [1008] [6338] +1--1 1 +111- 1 +010- 1 +.names n_n4275 n_n3766 [896] [1012] [6342] +0111 1 +.names n_n3954 n_n3955 [6343] +00 1 +.names n_n4305 n_n4006 n_n3848 [6343] [6346] +1001 1 +.names n_n3294 n_n4357 [942] [6346] [6349] +0011 1 +.names preset n_n4045 n_n4367 [6299] [6350] +1--- 1 +-0-- 1 +--01 1 +.names n_n3707 preset [6354] +10 1 +.names n_n4367 n_n4057 [6355] +11 1 +.names nsr3_14 nsr3_17 [6356] +0- 1 +-1 1 +.names preset n_n4045 n_n4367 [6299] [6357] +1--- 1 +-0-- 1 +--01 1 +.names n_n3954 n_n4305 [1008] [6358] +11- 1 +0-1 1 +.names preset n_n4045 n_n4367 [6299] [6361] +011- 1 +01-0 1 +.names n_n4029 n_n4305 n_n4006 [1008] [6366] +-11- 1 +1--1 1 +.names n_n3724 n_n3766 n_n4227 n_n3814 [6370] +1011 1 +.names [1015] n_n3707 [6374] +11 1 +.names preset nak3_17 [1063] [6374] [6376] +1--- 1 +-1-- 1 +--11 1 +.names n_n3845 n_n4305 n_n3848 [1008] [6379] +-11- 1 +1--1 1 +.names n_n3865 [984] n_n4305 [1008] [6380] +1--1 1 +111- 1 +001- 1 +.names [1070] [916] [6385] +11 1 +.names preset n_n3709 n_n135 [6290] [6386] +0101 1 +.names n_n3563 n_n4067 [6387] +10 1 +.names n_n4093 n_n3788 [1013] [2264] [6389] +1010 1 +.end diff --git a/fpga_flow/benchmarks/fpga_spice_bench.txt b/fpga_flow/benchmarks/fpga_spice_bench.txt new file mode 100644 index 000000000..3b445d6e9 --- /dev/null +++ b/fpga_flow/benchmarks/fpga_spice_bench.txt @@ -0,0 +1,31 @@ +# Circuit Names, fixed routint channel width, +s298.blif, 60 +elliptic.blif, 60 +simple_spi.blif, 60 +i2c.blif, 60 +pci_conf_cyc_addr_dec.blif, 60 +sasc.blif, 60 +usb_phy.blif, 60 +steppermotordrive.blif, 60 +stereovision3.blif, 60 +dalu.blif, 60 +C1355.blif, 60 +alu4.blif, 60 +priority.blif, 60 +apex7.blif, 60 +int2float.blif, 60 +planet.blif, 60 +alu2.blif, 60 +mult32a.blif, 60 +tbk.blif, 60 +sqrt8ml.blif, 60 +ss_pcm.blif, 60 +scf.blif, 60 +s820.blif, 60 +ctrl.blif, 60 +cavlc.blif, 60 +router.blif, 60 +traffic.blif, 60 +e64.blif, 60 +s1488.blif, 60 +fsm8_8_13.blif, 60 diff --git a/fpga_flow/benchmarks/mcnc_big20.txt b/fpga_flow/benchmarks/mcnc_big20.txt new file mode 100644 index 000000000..165dd084f --- /dev/null +++ b/fpga_flow/benchmarks/mcnc_big20.txt @@ -0,0 +1,22 @@ +# Circuit Names, fixed routint channel width, +#alu4.blif, 120 +#apex2.blif, 120 +#apex4.blif, 120 +#bigkey.blif, 120 +#clma.blif, 120 +#des.blif, 120 +#diffeq.blif, 120 +#dsip.blif, 120 +#elliptic.blif, 120 +#ex1010.blif, 120 +#ex5p.blif, 120 +#frisc.blif, 120 +#mcnc_big20.txt +#misex3.blif, 120 +#pdc.blif, 120 +s298.blif, 30 +#s38417.blif, 120 +#s38584.1.blif, 120 +#seq.blif, 120 +#spla.blif, 120 +#tseng.blif, 120 diff --git a/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_FF.conf b/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_FF.conf new file mode 100644 index 000000000..cec9420ff --- /dev/null +++ b/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_FF.conf @@ -0,0 +1,33 @@ +# Standard Configuration Example +[dir_path] +#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_verilog +#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_blif +#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/MCNC_big20 +benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/FPGA_SPICE_bench +odin2_path = /research/ece/lnis/USERS/tang/research/vtr7_release/ODIN_II/odin_II.exe +cirkit_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/FPGA_MIG/abc_majccmap/abc +abc_path = /research/ece/lnis/USERS/tang/research/ABC/abc70930/abc +abc_mccl_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/FPGA_MIG/abc_vtrccmap/abc +abc_with_bb_support_path = /research/ece/lnis/USERS/tang/research/vtr7_release/abc_with_bb_support/abc +mpack1_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/MPACK_v1.5b/mpack +m2net_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/scripts/m2net.pl +mpack2_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/MPACK_v2/mpack2 +#vpr_path = /research/ece/lnis/USERS/tang/research/vtr7_release/vpr/vpr +vpr_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/vpr +rpt_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/results +ace_path = /research/ece/lnis/USERS/tang/research/vtr7_release/ace2/ace + +[flow_conf] +flow_type = standard #standard|mpack2|mpack1|vtr_standard|vtr +#flow_type = vtr #standard|mpack2|mpack1|vtr_standard|vtr +vpr_arch = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_FF.xml # Use relative path under VPR folder is OK +mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK +m2net_conf = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/m2net_conf/m2x2_SiNWFET.conf +mpack2_arch = K6_pattern7_I24.arch +power_tech_xml = /research/ece/lnis/USERS/tang/research/vtr7_release/vtr_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK + +[csv_tags] +mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf: +mpack2_tags = BLE Number:|BLE Fill Rate: +vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took +vpr_power_tags = PB Types|Routing diff --git a/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_MC.conf b/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_MC.conf new file mode 100644 index 000000000..c989e5479 --- /dev/null +++ b/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_MC.conf @@ -0,0 +1,33 @@ +# Standard Configuration Example +[dir_path] +#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_verilog +#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_blif +#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/MCNC_big20 +benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/FPGA_SPICE_bench +odin2_path = /research/ece/lnis/USERS/tang/research/vtr7_release/ODIN_II/odin_II.exe +cirkit_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/FPGA_MIG/abc_majccmap/abc +abc_path = /research/ece/lnis/USERS/tang/research/ABC/abc70930/abc +abc_mccl_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/FPGA_MIG/abc_vtrccmap/abc +abc_with_bb_support_path = /research/ece/lnis/USERS/tang/research/vtr7_release/abc_with_bb_support/abc +mpack1_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/MPACK_v1.5b/mpack +m2net_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/scripts/m2net.pl +mpack2_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/MPACK_v2/mpack2 +#vpr_path = /research/ece/lnis/USERS/tang/research/vtr7_release/vpr/vpr +vpr_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/vpr +rpt_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/results +ace_path = /research/ece/lnis/USERS/tang/research/vtr7_release/ace2/ace + +[flow_conf] +flow_type = standard #standard|mpack2|mpack1|vtr_standard|vtr +#flow_type = vtr #standard|mpack2|mpack1|vtr_standard|vtr +vpr_arch = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_MC.xml # Use relative path under VPR folder is OK +mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK +m2net_conf = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/m2net_conf/m2x2_SiNWFET.conf +mpack2_arch = K6_pattern7_I24.arch +power_tech_xml = /research/ece/lnis/USERS/tang/research/vtr7_release/vtr_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK + +[csv_tags] +mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf: +mpack2_tags = BLE Number:|BLE Fill Rate: +vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took +vpr_power_tags = PB Types|Routing diff --git a/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_SS.conf b/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_SS.conf new file mode 100644 index 000000000..2a0c64f80 --- /dev/null +++ b/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_SS.conf @@ -0,0 +1,33 @@ +# Standard Configuration Example +[dir_path] +#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_verilog +#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_blif +#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/MCNC_big20 +benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/FPGA_SPICE_bench +odin2_path = /research/ece/lnis/USERS/tang/research/vtr7_release/ODIN_II/odin_II.exe +cirkit_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/FPGA_MIG/abc_majccmap/abc +abc_path = /research/ece/lnis/USERS/tang/research/ABC/abc70930/abc +abc_mccl_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/FPGA_MIG/abc_vtrccmap/abc +abc_with_bb_support_path = /research/ece/lnis/USERS/tang/research/vtr7_release/abc_with_bb_support/abc +mpack1_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/MPACK_v1.5b/mpack +m2net_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/scripts/m2net.pl +mpack2_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/MPACK_v2/mpack2 +#vpr_path = /research/ece/lnis/USERS/tang/research/vtr7_release/vpr/vpr +vpr_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/vpr +rpt_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/results +ace_path = /research/ece/lnis/USERS/tang/research/vtr7_release/ace2/ace + +[flow_conf] +flow_type = standard #standard|mpack2|mpack1|vtr_standard|vtr +#flow_type = vtr #standard|mpack2|mpack1|vtr_standard|vtr +vpr_arch = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_SS.xml # Use relative path under VPR folder is OK +mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK +m2net_conf = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/m2net_conf/m2x2_SiNWFET.conf +mpack2_arch = K6_pattern7_I24.arch +power_tech_xml = /research/ece/lnis/USERS/tang/research/vtr7_release/vtr_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK + +[csv_tags] +mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf: +mpack2_tags = BLE Number:|BLE Fill Rate: +vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took +vpr_power_tags = PB Types|Routing diff --git a/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_TT.conf b/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_TT.conf new file mode 100644 index 000000000..5f9fedcac --- /dev/null +++ b/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_TT.conf @@ -0,0 +1,33 @@ +# Standard Configuration Example +[dir_path] +#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_verilog +#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_blif +#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/MCNC_big20 +benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/FPGA_SPICE_bench +odin2_path = /research/ece/lnis/USERS/tang/research/vtr7_release/ODIN_II/odin_II.exe +cirkit_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/FPGA_MIG/abc_majccmap/abc +abc_path = /research/ece/lnis/USERS/tang/research/ABC/abc70930/abc +abc_mccl_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/FPGA_MIG/abc_vtrccmap/abc +abc_with_bb_support_path = /research/ece/lnis/USERS/tang/research/vtr7_release/abc_with_bb_support/abc +mpack1_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/MPACK_v1.5b/mpack +m2net_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/scripts/m2net.pl +mpack2_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/MPACK_v2/mpack2 +#vpr_path = /research/ece/lnis/USERS/tang/research/vtr7_release/vpr/vpr +vpr_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/vpr +rpt_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/results +ace_path = /research/ece/lnis/USERS/tang/research/vtr7_release/ace2/ace + +[flow_conf] +flow_type = standard #standard|mpack2|mpack1|vtr_standard|vtr +#flow_type = vtr #standard|mpack2|mpack1|vtr_standard|vtr +vpr_arch = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml # Use relative path under VPR folder is OK +mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK +m2net_conf = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/m2net_conf/m2x2_SiNWFET.conf +mpack2_arch = K6_pattern7_I24.arch +power_tech_xml = /research/ece/lnis/USERS/tang/research/vtr7_release/vtr_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK + +[csv_tags] +mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf: +mpack2_tags = BLE Number:|BLE Fill Rate: +vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took +vpr_power_tags = PB Types|Routing diff --git a/fpga_flow/configs/sample.conf b/fpga_flow/configs/sample.conf new file mode 100644 index 000000000..4c9cfbd73 --- /dev/null +++ b/fpga_flow/configs/sample.conf @@ -0,0 +1,34 @@ +# Standard Configuration Example +[dir_path] +#benchmark_dir = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_verilog +#benchmark_dir = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_blif +#benchmark_dir = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/MCNC_big20 +benchmark_dir = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/fpga_spice_test_bench +odin2_path = /home/xitang/research/vtr_release/ODIN_II/odin_II.exe +cirkit_path = /home/xitang/tangxifan-eda-tools/branches/FPGA_MIG/abc_majccmap/abc +abc_path = /home/xitang/research/ABC/abc70930/abc +abc_mccl_path = /home/xitang/tangxifan-eda-tools/branches/FPGA_MIG/abc_vtrccmap/abc +abc_with_bb_support_path = /home/xitang/research/vtr_release/abc_with_bb_support/abc +mpack1_path = /home/xitang/tangxifan-eda-tools/branches/MPACK_v1.5b/mpack +m2net_path = /home/xitang/tangxifan-eda-tools/branches/scripts/m2net.pl +mpack2_path = /home/xitang/tangxifan-eda-tools/branches/MPACK_v2/mpack2 +#vpr_path = /home/xitang/research/vtr_release/vpr/vpr +vpr_path = /home/xitang/tangxifan-eda-tools/branches/vpr7_rram/vpr/vpr +rpt_dir = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/results +ace_path = /home/xitang/research/vtr_release/ace2/ace + +[flow_conf] +flow_type = standard #standard|mpack2|mpack1|vtr_standard|vtr +#flow_type = vtr #standard|mpack2|mpack1|vtr_standard|vtr +vpr_arch = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm.xml # Use relative path under VPR folder is OK +mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK +m2net_conf = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/m2net_conf/m2x2_SiNWFET.conf +mpack2_arch = K6_pattern7_I24.arch +#power_tech_xml = /home/xitang/research/vtr_release/vtr_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK +power_tech_xml = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/power_tech_properties/tsmc40nm.xml # Use relative path under VPR folder is OK + +[csv_tags] +mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf: +mpack2_tags = BLE Number:|BLE Fill Rate: +vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles: +vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff diff --git a/fpga_flow/scripts/convert_blif.pl b/fpga_flow/scripts/convert_blif.pl new file mode 100755 index 000000000..86df2a529 --- /dev/null +++ b/fpga_flow/scripts/convert_blif.pl @@ -0,0 +1,105 @@ +#!usr/bin/perl -w +use strict; +#use Shell; +#Use the time +use Time::gmtime; + +#Get Date +my $mydate = gmctime(); + +my ($fname,$frpt); + +sub print_usage() +{ + print "Usage:\n"; + print " perl [-options]\n"; + print " Options:(Mandatory!)\n"; + print " -i \n"; + print " -o \n"; + print "\n"; + return 1; +} + +sub opts_read() +{ + if (-1 == $#ARGV) + { + print "Error: No input argument!\n"; + &print_usage(); + exit(1); + } + else + { + for (my $iargv = 0; $iargv < $#ARGV+1; $iargv++) + { + if ("-i" eq $ARGV[$iargv]) + {$fname = $ARGV[$iargv+1];} + elsif ("-o" eq $ARGV[$iargv]) + {$frpt = $ARGV[$iargv+1];} + } + } + return 1; +} + +sub scan_blif() +{ + my ($line,$lines); + my @tokens; + + # Open src file + open(FIN, "< $fname") or die "Fail to open $fname!\n"; + # Open des file + open(FOUT, "> $frpt") or die "Fail to open $frpt!\n"; + while(defined($line = )) { + chomp $line; + # Replace the < and > with [ and ], VPR does not support... + $line =~ s//]/g; + # Check if this line start with ".latch", which we cares only + if ($line =~ m/\.names/) { + # check the continue line + $lines = $line; # empty the buffer + while($lines =~ m/\\$/) { + $line = ; + chomp $line; + $lines =~ s/\\$//; + $lines = $lines.$line; + } + @tokens = split('\s+',$lines); + if (($#tokens - 1) == 3) { + print FOUT ".gate CARRY a=$tokens[1] b=$tokens[2] c=$tokens[3] O=$tokens[4]\n"; + } elsif (($#tokens - 1) == 2) { + print FOUT ".gate AND a=$tokens[1] b=$tokens[2] O=$tokens[3]\n"; + } elsif (($#tokens - 1) == 1) { + $line = ; + if ($line =~ m/^0/) { + print FOUT ".gate INV a=$tokens[1] O=$tokens[2]\n"; + } else { + print FOUT ".gate BUF a=$tokens[1] O=$tokens[2]\n"; + } + } elsif (($#tokens - 1) == 0) { # constant generator + $line = ; + if ($line =~ m/^0/) { + print FOUT ".gate ZERO O=$tokens[1]\n"; + } else { + print FOUT ".gate ONE O=$tokens[1]\n"; + } + } + } else { + print FOUT "$line\n"; + } + } + close(FIN); + close(FOUT); + return 1; +} + +sub main() +{ + &opts_read(); + &scan_blif(); + return 1; +} + +&main(); +exit(1); diff --git a/fpga_flow/scripts/fpga_arch_gen.pl b/fpga_flow/scripts/fpga_arch_gen.pl new file mode 100644 index 000000000..dbda80108 --- /dev/null +++ b/fpga_flow/scripts/fpga_arch_gen.pl @@ -0,0 +1,111 @@ +#!usr/bin/perl -w +use strict; +#use Shell; +use Time::gmtime; +use Switch; +use File::Path; +use Cwd; + +my $mydate = gmctime(); +my $cwd = getcwd(); + +sub gen_fpga_arch($ $) +{ + my ($k,$n) = @_; + my ($arch_file) = ("tmp.xml"); + my ($i) = int(0.5+$k*($n+1)/2); + print "K=$k N=$n I=$i\n"; + + my ($seq_out_up) = (2*$n-1); + + my %ble_h; + my $ble_ptr = \%ble_h; + + my @comb; + my @seq; + my ($j); + + for ($j=0; $j<$k*$n; $j++) { + my ($idx) = int($j/$k); + print "idx=$idx"; + my ($input) = $j%$k; + print " input=$input\n"; + $ble_ptr->{"ble_in$j"}->{ble_idx} = $idx; + $ble_ptr->{"ble_in$j"}->{ble_input_idx} = $input; + if ($input < $idx) { + $ble_ptr->{"ble_in$j"}->{comb_in} = $input; + } + else { + $ble_ptr->{"ble_in$j"}->{comb_in} = -1; + } + $ble_ptr->{"ble$idx"}->{"input$input"}->{idx} = $j; + } + + my ($iseq,$icomb) = (0,0); + for (my $ible=0; $ible<$n; $ible++) { + for (my $in=0; $in<$ible; $in++) { + if ($in < $ible) { + $comb[$icomb] = $ble_ptr->{"ble$ible"}->{"input$in"}->{idx}; + $icomb++; + } + } + for (my $in=$ible; $in<$k; $in++) { + if ($in < $k) { + $seq[$iseq] = $ble_ptr->{"ble$ible"}->{"input$in"}->{idx}; + $iseq++; + } + } + } + + open (FARCH," > $arch_file") or die "Fail to create $arch_file"; + print FARCH "\n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH "\n"; + + my ($imux) = (0); + foreach my $tmp(@comb) { + print FARCH " {"ble_in$tmp"}->{comb_in}."]\" output=\"ble.in[$tmp]\">\n"; + print FARCH " \n"; + print FARCH " {\"ble_in$tmp\"}->{comb_in}] \" out_port=\"ble.in[$tmp]\"/>\n"; + print FARCH " \n"; + $imux++; + } + for (my $i=0; $i<$n; $i++) { + my $j = $i + $n; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + $imux++; + } + print FARCH " \n"; + + +} + +sub main() +{ + my ($k,$n) = (6,7); + &gen_fpga_arch($k,$n); +} + +&main(); diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl new file mode 100644 index 000000000..cbd05a700 --- /dev/null +++ b/fpga_flow/scripts/fpga_flow.pl @@ -0,0 +1,3252 @@ +#!usr/bin/perl -w +# use the strict mode +use strict; +# Use the Shell enviornment +#use Shell; +# Use the time +use Time::gmtime; +# Use switch module +#use Switch; +use File::Path; +use Cwd; +use FileHandle; +# Multi-thread support +use threads; +use threads::shared; + +# Date +my $mydate = gmctime(); +# Current Path +my $cwd = getcwd(); + +# Global Variants +# input Option Hash +my %opt_h; +my $opt_ptr = \%opt_h; +# configurate file hash +my %conf_h; +my $conf_ptr = \%conf_h; +# reports has +my %rpt_h; +my $rpt_ptr = \%rpt_h; + +# Benchmarks +my @benchmark_names; +my %benchmarks; +my $benchmarks_ptr = \%benchmarks; + +# Supported flows +my @supported_flows = ("standard", + "vtr_mccl", + "mccl", + "mig_mccl", + "mpack2", + "mpack1", + "vtr", + "vtr_standard"); +my %selected_flows; + +# Configuration file keywords list +# Category for conf file. +# main category : 1st class +my @mctgy; +# sub category : 2nd class +my @sctgy; +# Initialize these categories +@mctgy = ("dir_path", + "flow_conf", + "csv_tags", + ); +# refer to the keywords of dir_path +@{$sctgy[0]} = ("benchmark_dir", + "odin2_path", + "cirkit_path", + "abc_mccl_path", + "abc_path", + "abc_with_bb_support_path", + "mpack1_path", + "m2net_path", + "mpack2_path", + "vpr_path", + "rpt_dir", + "ace_path", + ); +# refer to the keywords of flow_type +@{$sctgy[1]} = ("flow_type", + "vpr_arch", + "mpack2_arch", + "m2net_conf", + "mpack1_abc_stdlib", + "power_tech_xml", + ); +# refer to the keywords of csv_tags +@{$sctgy[2]} = ("mpack1_tags", + "mpack2_tags", + "vpr_tags", + "vpr_power_tags" + ); + +# ----------Subrountines------------# +# Print TABs and strings +sub tab_print($ $ $) +{ + my ($FILE,$str,$num_tab) = @_; + my ($my_tab) = (" "); + + for (my $i = 0; $i < $num_tab; $i++) { + print $FILE "$my_tab"; + } + print $FILE "$str"; +} + +# Create paths if it does not exist. +sub generate_path($) +{ + my ($mypath) = @_; + if (!(-e "$mypath")) + { + mkpath "$mypath"; + print "Path($mypath) does not exist...Create it.\n"; + } + return 1; +} + +# Print the usage +sub print_usage() +{ + print "Usage:\n"; + print " fpga_flow [-options ]\n"; + print " Mandatory options: \n"; + print " -conf : specify the basic configuration files for fpga_flow\n"; + print " -benchmark : the configuration file contains benchmark file names\n"; + print " -rpt : CSV file consists of data\n"; + print " -N : N-LUT/Matrix\n"; + print " Other Options:\n"; + print " -I : Number of inputs of a CLB, mandatory when mpack1 flow is chosen\n"; + print " -K : K-LUT, mandatory when standard flow is chosen\n"; + print " -M : M-Matrix, mandatory when mpack1 flow is chosen\n"; + print " -power : run power estimation oriented flow\n"; + print " -black_box_ace: run activity estimation with black box support. It increase the power.\n"; + print " -remove_designs: remove all the old results.\n"; + print " -abc_scl : run ABC optimization for sequential circuits, mandatory when VTR flow is selected.\n"; + print " -abc_verilog_rewrite : run ABC to convert a blif netlist to a Verilog netlist.\n"; + print " -ace_p : specify the default signal probablity of PIs in ACE2.\n"; + print " -ace_d : specify the default signal density of PIs in ACE2.\n"; + print " -vpr_timing_pack_off : turn off the timing-driven pack for vpr.\n"; + print " -vpr_place_clb_pin_remap: turn on place_clb_pin_remap in VPR.\n"; + print " -vpr_max_router_iteration : specify the max router iteration in VPR.\n"; + print " -vpr_route_breadthfirst : use the breadth-first routing algorithm of VPR.\n"; + print " -min_route_chan_width : turn on routing with * min_route_chan_width.\n"; + print " -fix_route_chan_width : turn on routing with a fixed route_chan_width, defined in benchmark configuration file.\n"; + print " -multi_task : turn on the mutli-task mode\n"; + print " -vpr_fpga_spice : turn on SPICE netlists print-out in VPR, specify a task file\n"; + print " -vpr_fpga_spice_print_component_tb : print component-level testbenches in VPR FPGA SPICE\n"; + print " -vpr_fpga_spice_print_grid_tb : print Grid-level testbenches in VPR FPGA SPICE\n"; + print " -vpr_fpga_spice_print_top_tb : print full-chip testbench in VPR FPGA SPICE\n"; + print " -vpr_fpga_spice_leakage_only : turn on leakage_only mode in VPR FPGA SPICE\n"; + print " -vpr_fpga_spice_parasitic_net_estimation_off : turn off parasitic_net_estimation in VPR FPGA SPICE\n"; + print " -vpr_fpga_spice_testbench_load_extraction_off : turn off testbench_load_extraction in VPR FPGA SPICE\n"; + print " -vpr_fpga_spice_verilog_generator : turn on Verilog Generator of VPR FPGA SPICE\n"; + print " -vpr_fpga_spice_rename_illegal_port : turn on renaming illegal ports option of VPR FPGA SPICE\n"; + print " -vpr_fpga_spice_signal_density_weight : specify the option signal_density_weight of VPR FPGA SPICE\n"; + print " -vpr_fpga_spice_sim_window_size : specify the option sim_window_size of VPR FPGA SPICE\n"; + print " -vpr_fpga_spice_sim_mt_num : specify the option sim_mt_num of VPR FPGA SPICE\n"; + print " -multi_thread : turn on the mutli-thread mode, specify the number of threads\n"; + print " -parse_results_only : only parse the flow results and write CSV report.\n"; + print " -min_hard_adder_size: min. size of hard adder in carry chain defined in Arch XML.(Default:1)\n"; + print " -mem_size: size of memory, mandatory when VTR/VTR_MCCL/VTR_MIG_MCCL flow is chosen\n"; + print " -odin2_carry_chain_support: turn on the carry_chain support only valid for VTR_MCCL/VTR_MIG_MCCL flow \n"; + print " -debug : debug mode\n"; + print " -help : print usage\n"; + exit(1); + return 1; +} + +sub spot_option($ $) +{ + my ($start,$target) = @_; + my ($arg_no,$flag) = (-1,"unfound"); + for (my $iarg = $start; $iarg < $#ARGV+1; $iarg++) + { + if ($ARGV[$iarg] eq $target) + { + if ("found" eq $flag) + { + print "Error: Repeated Arguments!(IndexA: $arg_no,IndexB: $iarg)\n"; + &print_usage(); + } + else + { + $flag = "found"; + $arg_no = $iarg; + } + } + } + # return the arg_no if target is found + # or return -1 when target is missing + return $arg_no; +} + +# Specify in the input list, +# 1. Option Name +# 2. Whether Option with value. if yes, choose "on" +# 3. Whether Option is mandatory. If yes, choose "on" +sub read_opt_into_hash($ $ $) +{ + my ($opt_name,$opt_with_val,$mandatory) = @_; + # Check the -$opt_name + my ($opt_fact) = ("-".$opt_name); + my ($cur_arg) = (0); + my ($argfd) = (&spot_option($cur_arg,"$opt_fact")); + if ($opt_with_val eq "on") + { + if (-1 != $argfd) + { + if ($ARGV[$argfd+1] =~ m/^-/) + { + print "The next argument cannot start with '-'!\n"; + print "it implies an option!\n"; + } + else + { + $opt_ptr->{"$opt_name\_val"} = $ARGV[$argfd+1]; + $opt_ptr->{"$opt_name"} = "on"; + } + } + else + { + $opt_ptr->{"$opt_name"} = "off"; + if ($mandatory eq "on") + { + print "Mandatory option: $opt_fact is missing!\n"; + &print_usage(); + } + } + } + else + { + if (-1 != $argfd) + { + $opt_ptr->{"$opt_name"} = "on"; + } + else + { + $opt_ptr->{"$opt_name"} = "off"; + if ($mandatory eq "on") + { + print "Mandatory option: $opt_fact is missing!\n"; + &print_usage(); + } + } + } + return 1; +} + +# Read options +sub opts_read() +{ + # if no arguments detected, print the usage. + if (-1 == $#ARGV) + { + print "Error : No input arguments!\n"; + print "Help desk:\n"; + &print_usage(); + exit(1); + } + # Read in the options + my ($cur_arg,$arg_found); + $cur_arg = 0; + print "Analyzing your options...\n"; + # Read the options with internal options + my $argfd; + # Check help fist + $argfd = &spot_option($cur_arg,"-help"); + if (-1 != $argfd) + { + print "Help desk:\n"; + &print_usage(); + } + # Then Check the debug with highest priority + $argfd = &spot_option($cur_arg,"-debug"); + if (-1 != $argfd) + { + $opt_ptr->{"debug"} = "on"; + } + else + { + $opt_ptr->{"debug"} = "off"; + } + # Check mandatory options + # Check the -conf + # Read Opt into Hash(opt_ptr) : "opt_name","with_val","mandatory" + &read_opt_into_hash("conf","on","on"); + &read_opt_into_hash("benchmark","on","on"); + &read_opt_into_hash("rpt","on","on"); + &read_opt_into_hash("N","on","on"); + &read_opt_into_hash("K","on","off"); + &read_opt_into_hash("I","on","off"); + &read_opt_into_hash("M","on","off"); + &read_opt_into_hash("power","off","off"); + &read_opt_into_hash("vpr_place_clb_pin_remap","off","off"); + &read_opt_into_hash("black_box_ace","off","off"); + &read_opt_into_hash("remove_designs","off","off"); + &read_opt_into_hash("abc_scl","off","off"); + &read_opt_into_hash("abc_verilog_rewrite","off","off"); + &read_opt_into_hash("ace_p","on","off"); + &read_opt_into_hash("ace_d","on","off"); + &read_opt_into_hash("vpr_timing_pack_off","off","off"); + &read_opt_into_hash("vpr_route_breadthfirst","off","off"); + &read_opt_into_hash("min_route_chan_width","on","off"); + &read_opt_into_hash("fix_route_chan_width","off","off"); + &read_opt_into_hash("vpr_max_router_iteration","on","off"); + &read_opt_into_hash("multi_task","on","off"); + &read_opt_into_hash("multi_thread","on","off"); + &read_opt_into_hash("parse_results_only","off","off"); + + # VTR/VTR_MCCL/VTR_MIG_MCCL flow options + # Read Opt into Hash(opt_ptr) : "opt_name","with_val","mandatory" + &read_opt_into_hash("min_hard_adder_size","on","off"); + &read_opt_into_hash("mem_size","on","off"); + &read_opt_into_hash("odin2_carry_chain_support","off","off"); + + # FPGA-SPICE options + # Read Opt into Hash(opt_ptr) : "opt_name","with_val","mandatory" + &read_opt_into_hash("vpr_fpga_spice","on","off"); + &read_opt_into_hash("vpr_fpga_spice_print_component_tb","off","off"); + &read_opt_into_hash("vpr_fpga_spice_print_grid_tb","off","off"); + &read_opt_into_hash("vpr_fpga_spice_print_top_tb","off","off"); + &read_opt_into_hash("vpr_fpga_spice_leakage_only","off","off"); + &read_opt_into_hash("vpr_fpga_spice_parasitic_net_estimation_off","off","off"); + &read_opt_into_hash("vpr_fpga_spice_testbench_load_extraction_off","off","off"); + &read_opt_into_hash("vpr_fpga_spice_verilog_generator","off","off"); + &read_opt_into_hash("vpr_fpga_spice_rename_illegal_port","off","off"); + &read_opt_into_hash("vpr_fpga_spice_signal_density_weight","on","off"); + &read_opt_into_hash("vpr_fpga_spice_sim_window_size","on","off"); + &read_opt_into_hash("vpr_fpga_spice_sim_mt_num","on","off"); + + &print_opts(); + + return 1; +} + +# List the options +sub print_opts() +{ + print "List your options\n"; + + while(my ($key,$value) = each(%opt_h)) + {print "$key : $value\n";} + + return 1; +} + + +# Read each line and ignore the comments which starts with given arg +# return the valid information of line +sub read_line($ $) +{ + my ($line,$com) = @_; + my @chars; + if (defined($line)) + { + @chars = split/$com/,$line; + if (!($line =~ m/[\w\d]/)) + {$chars[0] = undef;} + if ($line =~ m/^\s*$com/) + {$chars[0] = undef;} + } + else + {$chars[0] = undef;} + if (defined($chars[0])) + { + $chars[0] =~ s/^(\s+)//g; + $chars[0] =~ s/(\s+)$//g; + } + return $chars[0]; +} + +# Check each keywords has been defined in configuration file +sub check_keywords_conf() +{ + for (my $imcg = 0; $imcg<$#mctgy+1; $imcg++) + { + for (my $iscg = 0; $iscg<$#{$sctgy[$imcg]}+1; $iscg++) + { + if (defined($conf_ptr->{$mctgy[$imcg]}->{$sctgy[$imcg]->[$iscg]}->{val})) + { + if ("on" eq $opt_ptr->{debug}) + { + print "Keyword($mctgy[$imcg],$sctgy[$imcg]->[$iscg]) = "; + print "$conf_ptr->{$mctgy[$imcg]}->{$sctgy[$imcg]->[$iscg]}->{val}"; + print "\n"; + } + } + else + {die "Error: Keyword($mctgy[$imcg],$sctgy[$imcg]->[$iscg]) is missing!\n";} + } + } + return 1; +} + +# Read the configuration file +sub read_conf() +{ + # Read in these key words + my ($line,$post_line); + my @equation; + my $cur = "unknown"; + open (CONF, "< $opt_ptr->{conf_val}") or die "Fail to open $opt_ptr->{conf_val}!\n"; + print "Reading $opt_ptr->{conf_val}...\n"; + while(defined($line = )) + { + chomp $line; + $post_line = &read_line($line,"#"); + if (defined($post_line)) + { + if ($post_line =~ m/\[(\w+)\]/) + {$cur = $1;} + elsif ("unknown" eq $cur) + { + die "Error: Unknown tags for this line!\n$post_line\n"; + } + else + { + $post_line =~ s/\s//g; + @equation = split /=/,$post_line; + $conf_ptr->{$cur}->{$equation[0]}->{val} = $equation[1]; + } + } + } + # Check these key words + print "Read complete!\n"; + &check_keywords_conf(); + print "Checking these keywords..."; + print "Successfully\n"; + close(CONF); + return 1; +} + +sub read_benchmarks() +{ + # Read in file names + my ($line,$post_line,$cur); + $cur = 0; + open (FCONF,"< $opt_ptr->{benchmark_val}") or die "Fail to open $opt_ptr->{benchmark_val}!\n"; + print "Reading $opt_ptr->{benchmark_val}...\n"; + while(defined($line = )) + { + chomp $line; + $post_line = &read_line($line,"#"); + if (defined($post_line)) { + $post_line =~ s/\s+//g; + my @tokens = split(",",$post_line); + # first is the benchmark name, + #the second is the channel width, if applicable + if ($tokens[0]) { + $benchmark_names[$cur] = $tokens[0]; + } else { + die "ERROR: invalid definition for benchmarks!\n"; + } + $benchmarks_ptr->{"$benchmark_names[$cur]"}->{fix_route_chan_width} = $tokens[1]; + $cur++; + } + } + print "Benchmarks(total $cur):\n"; + foreach my $temp(@benchmark_names) + {print "$temp\n";} + close(FCONF); + return 1; +} + +# Input program path is like "~/program_dir/program_name" +# We split it from the scalar +sub split_prog_path($) +{ + my ($prog_path) = @_; + my @path_elements = split /\//,$prog_path; + my ($prog_dir,$prog_name); + + $prog_name = $path_elements[$#path_elements]; + $prog_dir = $prog_path; + $prog_dir =~ s/$prog_name$//g; + + return ($prog_dir,$prog_name); +} + +sub check_blif_type($) +{ + my ($blif) = @_; + my ($line); + open (BLIF, "< $blif") or die "Fail to open $blif!\n"; + while(defined($line = )) { + chomp $line; + if ($line =~ /^\.latch/) { + close(BLIF); + return "seq"; + } + } + close(BLIF); + return "comb"; +} + +# Check Options +sub check_opts() { + # Task 1: min_chan_width > 1 + if (("on" eq $opt_ptr->{min_route_chan_width}) + &&(1. > $opt_ptr->{min_route_chan_width_val})) { + die "ERROR: Invalid -min_chan_width, should be at least 1.0!\n"; + } + # Task 2: check mandatory option when flow mpack1 is chosen + if ("on" eq $selected_flows{"mpack1"}->{flow_status}) { + if ("off" eq $opt_ptr->{M}) { + die "ERROR: Option -M should be specified when flow mpack1 is selected!\n"; + } + if ("off" eq $opt_ptr->{I}) { + die "ERROR: Option -I should be specified when flow mpack1 is selected!\n"; + } + } + # Task 3: check mandatory options when flow vtr is chosen + if ("on" eq $selected_flows{"vtr"}->{flow_status}) { + if ("off" eq $opt_ptr->{mem_size}) { + die "ERROR: Option -mem_size should be specified when flow vtr is selected\n"; + } + if ("off" eq $opt_ptr->{K}) { + die "ERROR: Option -K should be specified when flow vtr is selected\n"; + } + if ("off" eq $opt_ptr->{abc_scl}) { + die "ERROR: Option -abc_scl should be specified when flow vtr is selected\n"; + } + } + # Task 3: check mandatory options when flow vtr_standard or standard is chosen + if (("on" eq $selected_flows{"standard"}->{flow_status}) + ||("on" eq $selected_flows{"vtr_standard"}->{flow_status})) { + if ("off" eq $opt_ptr->{K}) { + die "ERROR: Option -K should be specified when flow vtr_standard|standard is selected\n"; + } + } +} + +# Run ABC with standard library mapping +sub run_abc_libmap($ $ $) +{ + my ($bm,$blif_out,$log) = @_; + # Get ABC path + my ($abc_dir,$abc_name) = &split_prog_path($conf_ptr->{dir_path}->{abc_path}->{val}); + + chdir $abc_dir; + my ($mpack1_stdlib) = ($conf_ptr->{flow_conf}->{mpack1_abc_stdlib}->{val}); + # Run MPACK ABC + my ($abc_seq_optimize) = (""); + if (("on" eq $opt_ptr->{abc_scl})&&("seq" eq &check_blif_type($bm))) { + ($abc_seq_optimize) = ("scl -l;"); + } + # !!! For standard library, we cannot use sweep ??? + system("/bin/csh -cx './$abc_name -c \"read_blif $bm; resyn2; read_library $mpack1_stdlib; $abc_seq_optimize map -v; write_blif $blif_out; quit;\" > $log'"); + chdir $cwd; +} + +# Run ABC by FPGA-oriented synthesis +sub run_abc_fpgamap($ $ $) +{ + my ($bm,$blif_out,$log) = @_; + my ($cmd_log) = ($log."cmd"); + # Get ABC path + my ($abc_dir,$abc_name) = &split_prog_path($conf_ptr->{dir_path}->{abc_path}->{val}); + + print "Entering $abc_dir\n"; + chdir $abc_dir; + my ($lut_num) = $opt_ptr->{K_val}; + # Before we run this blif, identify it is a combinational or sequential + my ($abc_seq_optimize) = (""); + if (("on" eq $opt_ptr->{abc_scl})&&("seq" eq &check_blif_type($bm))) { + ($abc_seq_optimize) = ("scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;"); + } + my ($fpga_synthesis_method) = ("if"); + #my ($fpga_synthesis_method) = ("fpga"); + # + my ($dump_verilog) = (""); + if ("on" eq $opt_ptr->{abc_verilog_rewrite}) { + $dump_verilog = "write_verilog $bm.v"; + } + # Run FPGA ABC + #`csh -cx './$abc_name -c \"read $bm; resyn2; $fpga_synthesis_method -K $lut_num; $abc_seq_optimize $abc_seq_optimize sweep; write_blif $blif_out; quit\" > $log'`; + my ($ABC_CMD_FH) = (FileHandle->new); + if ($ABC_CMD_FH->open("> $cmd_log")) { + print "INFO: auto generating cmds for ABC ($cmd_log) ...\n"; + } else { + die "ERROR: fail to auto generating cmds for ABC ($cmd_log) ...\n"; + } + # Output the standard format (refer to VTR_flow script) + print $ABC_CMD_FH "read $bm; resyn; resyn2; $fpga_synthesis_method -K $lut_num; $abc_seq_optimize write_blif $blif_out; $dump_verilog; quit\n"; + + close($ABC_CMD_FH); + # + # Create a local copy for the commands + + system("/bin/tcsh -cx './$abc_name -F $cmd_log > $log'"); + + if (!(-e $blif_out)) { + die "ERROR: Fail ABC for benchmark $bm.\n"; + } + + if (("on" eq $opt_ptr->{abc_verilog_rewrite})&&(!(-e "$bm.v"))) { + die "ERROR: ABC verilog rewrite failed for benchmark $bm!\n"; + } + + print "Leaving $abc_dir\n"; + chdir $cwd; +} + +# Run ABC by FPGA-oriented synthesis +sub run_abc_bb_fpgamap($ $ $) { + my ($bm,$blif_out,$log) = @_; + # Get ABC path + my ($abc_dir,$abc_name) = &split_prog_path($conf_ptr->{dir_path}->{abc_with_bb_support_path}->{val}); + my ($lut_num) = $opt_ptr->{K_val}; + # Before we run this blif, identify it is a combinational or sequential + my ($abc_seq_optimize) = (""); + if (("on" eq $opt_ptr->{abc_scl})&&("seq" eq &check_blif_type($bm))) { + ($abc_seq_optimize) = ("scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;"); + } + my ($fpga_synthesis_method) = ("if"); + #my ($fpga_synthesis_method) = ("fpga"); + # + my ($dump_verilog) = (""); + if ("on" eq $opt_ptr->{abc_verilog_rewrite}) { + $dump_verilog = "write_verilog $bm.v"; + } + + chdir $abc_dir; + # Run FPGA ABC + system("/bin/csh -cx './$abc_name -c \"read $bm; resyn; resyn2; $fpga_synthesis_method -K $lut_num; $abc_seq_optimize sweep; write_hie $bm $blif_out; $dump_verilog; quit;\" > $log'"); + + if (!(-e $blif_out)) { + die "ERROR: Fail ABC_with_bb_support for benchmark $bm.\n"; + } + + if (("on" eq $opt_ptr->{abc_verilog_rewrite})&&(!(-e "$bm.v"))) { + die "ERROR: ABC verilog rewrite failed for benchmark $bm!\n"; + } + + chdir $cwd; +} + +# Run ABC Carry-chain premapping by FPGA-oriented synthesis +sub run_abc_mccl_fpgamap($ $ $) +{ + my ($bm,$blif_out,$log) = @_; + # Get ABC path + my ($abc_mccl_dir,$abc_mccl_name) = &split_prog_path($conf_ptr->{dir_path}->{abc_mccl_path}->{val}); + my ($abc_bb_dir,$abc_bb_name) = &split_prog_path($conf_ptr->{dir_path}->{abc_with_bb_support_path}->{val}); + my ($lut_num) = $opt_ptr->{K_val}; + # Before we run this blif, identify it is a combinational or sequential + my ($abc_seq_optimize) = (""); + if (("on" eq $opt_ptr->{abc_scl})&&("seq" eq &check_blif_type($bm))) { + ($abc_seq_optimize) = ("scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;"); + } + my ($fpga_synthesis_method) = ("if"); + #my ($fpga_synthesis_method) = ("fpga"); + + # Name the intermediate file + my ($fadds_blif, $interm_blif) = ($blif_out, $blif_out); + $fadds_blif =~ s/\.blif$/_fadds.blif/; + $interm_blif =~ s/\.blif$/_interm.blif/; + + my ($min_chain_length) = (4); + my ($mccl_opt_A, $mccl_opt_B, $mccl_opt_S) = (3, 3, 2); + + chdir $abc_mccl_dir; + print "INFO: entering abc_mccl directory: $abc_mccl_dir \n"; + + # Run ABC three times: + # 1st time: run abc_with_mccl: read the $bm and do carry-chain detection + system("/bin/csh -cx './$abc_mccl_name -c \"read $bm; strash; &get; &fadds -nv -N $min_chain_length; \&getspec; \&put; wfadds $fadds_blif; quit;\" > $log.ccdetect'"); + + # Repeat chdir for multi-thread supporting! + chdir $abc_mccl_dir; + print "INFO: entering abc_mccl directory: $abc_mccl_dir \n"; + + # 2nd time: run abc_with_mccl: read the $fadds_blif and do carry-chain LUT premapping + system("/bin/csh -cx './$abc_mccl_name -c \"read $fadds_blif; resyn; resyn2; mccl -A $mccl_opt_A -B $mccl_opt_B -S $mccl_opt_S -K $lut_num -O 1 -r -o $interm_blif; quit;\" > $log.mccl'"); + + chdir $abc_bb_dir; + print "INFO: entering abc_with_bb_support directory: $abc_bb_dir \n"; + # 3rd time: run abc_with_bb_support: read the pre-processed blif and do cleanup and recover + system("/bin/csh -cx './$abc_bb_name -c \"read $interm_blif; $abc_seq_optimize sweep; write_hie $interm_blif $blif_out; quit;\" > $log'"); + + if (!(-e $blif_out)) { + die "ERROR: Fail ABC_mccl_FPGA_mapping for benchmark $bm.\n"; + } + + chdir $cwd; +} + +# Run ABC MIG Carry-chain premapping by FPGA-oriented synthesis +sub run_abc_mig_mccl_fpgamap($ $ $) +{ + my ($bm,$blif_out,$log) = @_; + # Get ABC path + my ($abc_mig_mccl_dir,$abc_mig_mccl_name) = &split_prog_path($conf_ptr->{dir_path}->{cirkit_path}->{val}); + my ($abc_mccl_dir,$abc_mccl_name) = &split_prog_path($conf_ptr->{dir_path}->{abc_mccl_path}->{val}); + my ($abc_bb_dir,$abc_bb_name) = &split_prog_path($conf_ptr->{dir_path}->{abc_with_bb_support_path}->{val}); + my ($lut_num) = $opt_ptr->{K_val}; + # Before we run this blif, identify it is a combinational or sequential + my ($abc_seq_optimize) = (""); + if (("on" eq $opt_ptr->{abc_scl})&&("seq" eq &check_blif_type($bm))) { + ($abc_seq_optimize) = ("scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;"); + } + my ($fpga_synthesis_method) = ("if"); + #my ($fpga_synthesis_method) = ("fpga"); + + # Name the intermediate file + my ($fadds_blif, $interm_blif) = ($bm, $bm); + $fadds_blif =~ s/\.blif$/_fadds.blif/; + $interm_blif =~ s/\.blif$/_interm.blif/; + + my ($min_chain_length) = (4); + my ($mccl_opt_A, $mccl_opt_B, $mccl_opt_S) = (3, 3, 2); + + chdir $abc_mccl_dir; + print "INFO: entering abc_mig_mccl directory: $abc_mccl_dir \n"; + + # Run ABC three times: + # 1st time: run abc_with_mig_mccl: read the $bm and do carry-chain detection + # TODO: unfinished!!!! + system("/bin/csh -cx './$abc_mig_mccl_name -c \"readv $bm; chains -C ; quit;\" > $log.ccdetect'"); + + # Repeat chdir for multi-thread supporting! + chdir $abc_mccl_dir; + print "INFO: entering abc_mccl directory: $abc_mccl_dir \n"; + + # 2nd time: run abc_with_mccl: read the $fadds_blif and do carry-chain LUT premapping + system("/bin/csh -cx './$abc_mccl_name -c \"read $fadds_blif; resyn; resyn2; mccl -A $mccl_opt_A -B $mccl_opt_B -S $mccl_opt_S -K $lut_num -O 1 -r -o $interm_blif; quit;\" > $log.mccl'"); + + chdir $abc_bb_dir; + print "INFO: entering abc_with_bb_support directory: $abc_bb_dir \n"; + # 3rd time: run abc_with_bb_support: read the pre-processed blif and do cleanup and recover + system("/bin/csh -cx './$abc_bb_name -c \"read $interm_blif; $abc_seq_optimize sweep; write_hie $interm_blif $blif_out; quit;\" > $log'"); + + if (!(-e $blif_out)) { + die "ERROR: Fail ABC_mccl_FPGA_mapping for benchmark $bm.\n"; + } + + chdir $cwd; +} + +sub run_mpack1p5($ $ $ $ $) +{ + my ($blif_in,$blif_prefix,$matrix_size,$cell_size,$log) = @_; + # Get MPACK path + my ($mpack1_dir,$mpack1_name) = &split_prog_path($conf_ptr->{dir_path}->{mpack1_path}->{val}); + chdir $mpack1_dir; + # Run MPACK + system("/bin/csh -cx './$mpack1_name $blif_in $blif_prefix -matrix_depth $matrix_size -matrix_width $matrix_size -cell_size $cell_size > $log'"); + chdir $cwd; + +} + +sub run_mpack2($ $ $ $ $ $ $) +{ + my ($blif_in,$blif_out,$mpack2_arch,$net,$stats,$vpr_arch,$log) = @_; + # Get MPACK path + my ($mpack2_dir,$mpack2_name) = &split_prog_path($conf_ptr->{dir_path}->{mpack2_path}->{val}); + chdir $mpack2_dir; + #my ($ble_arch) = ($conf_ptr->{flow_conf}->{mpack_ble_arch}->{val}); + # Run MPACK + system("/bin/csh -cx './$mpack2_name -blif $blif_in -mpack_blif $blif_out -net $net -ble_arch $mpack2_arch -stats $stats -vpr_arch $vpr_arch > $log'"); + chdir $cwd; +} + +# Extract Mpack2 stats +sub extract_mpack2_stats($ $ $) +{ + my ($tag,$bm,$mstats) = @_; + my ($line); + my @keywords = split /\|/,$conf_ptr->{csv_tags}->{mpack2_tags}->{val}; + open (MSTATS, "< $mstats") or die "ERROR: Fail to open $mstats!\n"; + while(defined($line = )) { + chomp $line; + $line =~ s/\s//g; + foreach my $tmp(@keywords) { + $tmp =~ s/\s//g; + if ($line =~ m/$tmp\s*([0-9E\-\+.]+)/i) { + $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$opt_ptr->{K_val}}->{$tmp} = $1; + } + } + } + close(MSTATS); +} + +# Extract Mpack1 stats +sub extract_mpack1_stats($ $ $) +{ + my ($tag,$bm,$mstats) = @_; + my ($line); + my @keywords = split /\|/,$conf_ptr->{csv_tags}->{mpack1_tags}->{val}; + open (MSTATS, "< $mstats") or die "ERROR: Fail to open $mstats!\n"; + while(defined($line = )) { + chomp $line; + $line =~ s/\s//g; + foreach my $tmp(@keywords) { + $tmp =~ s/\s//g; + if ($line =~ m/$tmp\s*([0-9E\-\+.]+)/i) { + $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$opt_ptr->{M_val}}->{$tmp} = $1; + } + } + } + close(MSTATS); +} + +# Black Box blif for ACE +sub black_box_blif($ $) +{ + my ($blif_in,$blif_out) = @_; + my ($line); + + open (BF, "< $blif_in") or die "Fail to open $blif_in!\n"; + open (NBF, "> $blif_out") or die "Fail to open $blif_out!\n"; + while(defined($line = )) { + chomp $line; + my @components; + if ($line =~ m/^\.names/) { + @components = split /\s+/,$line; + $line = ".subckt CELL "; + for (my $i=1; $i < ($opt_ptr->{K_val}+1); $i++) { + my $i1 = $i - 1; + if ($i < $#components) { + $line = $line."I[$i1]=$components[$i] "; + } + else { + $line = $line."I[$i1]=unconn "; + } + } + $line = $line."O[0]=$components[$#components] "; + } + print NBF "$line\n"; + } + # definition of Black box + print NBF "\n"; + print NBF ".model CELL\n"; + print NBF ".inputs "; + for (my $i=0; $i < $opt_ptr->{K_val}; $i++) { + print NBF "I[$i] "; + } + print NBF "\n"; + print NBF ".outputs O[0]\n"; + print NBF ".blackbox\n"; + print NBF ".end\n"; + close(BF); + close(NBF); +} + +# Extract VPR Power Esti +sub extract_vpr_power_esti($ $ $ $) +{ + my ($tag,$ace_vpr_blif,$bm,$type) = @_; + my ($line,$tmp,$line_num); + my @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; + my ($vpr_power_stats) = $ace_vpr_blif; + + $line_num = 0; + $vpr_power_stats =~ s/blif$/power/; + open (VSTATS, "< $vpr_power_stats") or die "Fail to open $vpr_power_stats!\n"; + while(defined($line = )) { + chomp $line; + $line_num++; + if ($line =~ m/^Total/i) { + my @power_info = split /\s+/,$line; + if ($#power_info < 3) { + print "Error: (vpr_power_stats:$vpr_power_stats)ilegal definition at LINE[$line_num]!\n"; + die "Format should be [tag] [Power] [Proposition] [Dynamic Proposition] [Method](Optional)\n"; + } + if ($power_info[3] > 1) { + die "Error: (vpr_power_stats:$vpr_power_stats)Dynamic Power Proposition should not be greater than 1 at LINE[$line_num]!\n"; + } + $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{power}->{total} = $power_info[1]; + $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{power}->{dynamic} = $power_info[1]*$power_info[3]; + $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{power}->{leakage} = $power_info[1]*(1-$power_info[3]); + next; + } + $line =~ s/\s//g; + foreach my $tmpkw(@keywords) { + $tmp = $tmpkw; + $tmp =~ s/\s//g; + $tmp =~ s/\(/\\\(/g; + $tmp =~ s/\)/\\\)/g; + #print "$tmp\n"; + if ($line =~ m/$tmp\s*([0-9E\-+.]+)/i) { + $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{power}->{$tmpkw} = $1; + my @tempdata = split /\./,$rpt_ptr->{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{power}->{$tmpkw}; + $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{power}->{$tmpkw} = join('.',$tempdata[0],$tempdata[1]); + $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{power}->{$tmpkw} =~ s/0$//; + } + } + } + close(VSTATS); +} + +# Extract AAPack stats +sub extract_aapack_stats($ $ $ $ $) +{ + my ($tag,$bm,$vstats,$type,$keywords) = @_; + my ($line,$tmp); + open (VSTATS, "< $vstats") or die "Fail to open $vstats!\n"; + while(defined($line = )) { + chomp $line; + #$line =~ s/\s//g; + foreach my $tmpkw(@{$keywords}) { + $tmp = $tmpkw; + $tmp =~ s/\(/\\\(/g; + $tmp =~ s/\)/\\\)/g; + if ($line =~ m/\s*([0-9E\-+.]+)\s+of\s+type\s+$tmpkw/i) { + $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{$tmpkw} = $1; + $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{$tmpkw} =~ s/\.$//; + } + } + } + close(VSTATS); +} + +# Extract min_channel_width VPR stats +sub extract_min_chan_width_vpr_stats($ $ $ $ $ $) +{ + my ($tag,$bm,$vstats,$type,$min_route_chan_width,$parse_results) = @_; + my ($line,$tmp, $min_chan_width, $chan_width_tag); + my @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; + + if ("on" eq $min_route_chan_width) { + $tmp = "Best routing used a channel width factor of"; + $chan_width_tag = "min_route_chan_width"; + } else { + $tmp = "Circuit successfully routed with a channel width factor of"; + $chan_width_tag = "fix_route_chan_width"; + } + $tmp =~ s/\s//g; + + open (VSTATS, "< $vstats") or die "ERROR: Fail to open $vstats!\n"; + while(defined($line = )) { + chomp $line; + if (($line =~ m/\s+([0-9]+)\s+of\s+type\s+names/i) + &&(1 == $parse_results)) { + $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{LUTs} = $1; + $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{LUTs} =~ s/\.$//; + } + $line =~ s/\s//g; + if ($line =~ m/$tmp\s*([0-9E\-+.]+)/i) { + $min_chan_width = $1; + $min_chan_width =~ s/\.$//; + if (1 == $parse_results) { + $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{$chan_width_tag} = $min_chan_width; + } + } + } + close(VSTATS); + return $min_chan_width; +} + + +# Extract VPR stats +sub extract_vpr_stats($ $ $ $) +{ + my ($tag,$bm,$vstats,$type) = @_; + my ($line,$tmp); + my @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; + open (VSTATS, "< $vstats") or die "Fail to open $vstats!\n"; + while(defined($line = )) { + chomp $line; + if ($line =~ m/\s+([0-9]+)\s+of\s+type\s+names/i) { + $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{LUTs} = $1; + $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{LUTs} =~ s/\.$//; + } + $line =~ s/\s//g; + foreach my $tmpkw(@keywords) { + $tmp = $tmpkw; + $tmp =~ s/\s//g; + $tmp =~ s/\(/\\\(/g; + $tmp =~ s/\)/\\\)/g; + #print "$tmp\n"; + if ($line =~ m/$tmp\s*([0-9E\-+.]+)/i) { + $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{$tmpkw} = $1; + $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{$tmpkw} =~ s/\.$//; + } + } + } + close(VSTATS); +} + +sub gen_odin2_config_xml($ $ $ $ $ $) { + my ($config_xml, $odin2_verilog, $odin2_blif_out, $vpr_arch, $mem_size, $min_hard_adder_size) = @_; + + # Open a filehandle + my ($XMLFH) = (FileHandle->new); + if ($XMLFH->open("> $config_xml")) { + print "INFO: auto generating configuration XML for ODIN_II($config_xml) ...\n"; + } else { + die "ERROR: fail to auto generate configuration XML for ODIN_II($config_xml) ...\n"; + } + # Output the standard format (refer to VTR_flow script) + print $XMLFH "\n"; + print $XMLFH " \n"; + print $XMLFH " $odin2_verilog\n"; + print $XMLFH " \n"; + print $XMLFH " \n"; + print $XMLFH " blif\n"; + print $XMLFH " $odin2_blif_out\n"; + print $XMLFH " \n"; + print $XMLFH " $vpr_arch\n"; + print $XMLFH " \n"; + print $XMLFH " \n"; + print $XMLFH " \n"; + print $XMLFH " \n"; + print $XMLFH " \n"; + print $XMLFH " \n"; + print $XMLFH " \n"; + print $XMLFH " \n"; + print $XMLFH " .\n"; + print $XMLFH " 1\n"; + print $XMLFH " 1\n"; + print $XMLFH " \n"; + print $XMLFH "\n"; + + close($XMLFH); +} + +sub run_odin2($ $ $) { + my ($config_xml, $carry_chain_support, $log) = @_; + my ($odin2_dir, $odin2_name) = &split_prog_path($conf_ptr->{dir_path}->{odin2_path}->{val}); + my ($options) = (""); + + if ("on" eq $carry_chain_support) { + $options = $options." -Z"; + } + + chdir $odin2_dir; + system("/bin/csh -cx './$odin2_name -c $config_xml $options > $log'"); + chdir $cwd; +} + +# Run Acitivity Estimation +sub run_ace($ $ $ $) { + my ($mpack_vpr_blif,$act_file,$ace_new_blif,$log) = @_; + my ($ace_dir,$ace_name) = &split_prog_path($conf_ptr->{dir_path}->{ace_path}->{val}); + my ($ace_customized_opts) = (""); + + if ("on" eq $opt_ptr->{ace_d}) { + $ace_customized_opts .= " -d $opt_ptr->{ace_d_val}"; + } + + if ("on" eq $opt_ptr->{ace_p}) { + $ace_customized_opts .= " -p $opt_ptr->{ace_p_val}"; + } + + print "Entering $ace_dir\n"; + chdir $ace_dir; + system("/bin/csh -cx './$ace_name -b $mpack_vpr_blif -o $act_file -n $ace_new_blif $ace_customized_opts > $log'"); + + if (!(-e $ace_new_blif)) { + die "ERROR: Fail ACE for benchmark $mpack_vpr_blif.\n"; + } + + print "Leaving $ace_dir\n"; + + chdir $cwd; +} + +sub run_std_vpr($ $ $ $ $ $ $ $ $) +{ + my ($blif,$bm,$arch,$net,$place,$route,$fix_chan_width,$log,$act_file) = @_; + my ($vpr_dir,$vpr_name) = &split_prog_path($conf_ptr->{dir_path}->{vpr_path}->{val}); + chdir $vpr_dir; + + my ($power_opts); + if ("on" eq $opt_ptr->{power}) { + $power_opts = "--power --activity_file $act_file --tech_properties $conf_ptr->{flow_conf}->{power_tech_xml}->{val}"; + } else { + $power_opts = ""; + } + my ($packer_opts) = (""); + if ("on" eq $opt_ptr->{vpr_timing_pack_off}) { + $packer_opts = "--timing_driven_clustering off"; + } + + my ($chan_width_opt) = (""); + if (($fix_chan_width > 0)||($fix_chan_width == 0)) { + $chan_width_opt = "-route_chan_width $fix_chan_width"; + } + + my ($vpr_spice_opts) = (""); + if (("on" eq $opt_ptr->{power})&&("on" eq $opt_ptr->{vpr_fpga_spice})) { + $vpr_spice_opts = "--fpga_spice"; + + if ("on" eq $opt_ptr->{vpr_fpga_spice_signal_density_weight}) { + $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_signal_density_weight $opt_ptr->{vpr_fpga_spice_signal_density_weight_val}"; + } + if ("on" eq $opt_ptr->{vpr_fpga_spice_sim_window_size}) { + $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_sim_window_size $opt_ptr->{vpr_fpga_spice_sim_window_size_val}"; + } + if ("on" eq $opt_ptr->{vpr_fpga_spice_sim_mt_num}) { + $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_sim_mt_num $opt_ptr->{vpr_fpga_spice_sim_mt_num_val}"; + } + if ("on" eq $opt_ptr->{vpr_fpga_spice_print_component_tb}) { + $vpr_spice_opts = $vpr_spice_opts." --spice_print_lut_testbench"; + $vpr_spice_opts = $vpr_spice_opts." --spice_print_hardlogic_testbench"; + $vpr_spice_opts = $vpr_spice_opts." --spice_print_pb_mux_testbench"; + $vpr_spice_opts = $vpr_spice_opts." --spice_print_cb_mux_testbench"; + $vpr_spice_opts = $vpr_spice_opts." --spice_print_sb_mux_testbench"; + } + if ("on" eq $opt_ptr->{vpr_fpga_spice_print_grid_tb}) { + $vpr_spice_opts = $vpr_spice_opts." --spice_print_grid_testbench"; + $vpr_spice_opts = $vpr_spice_opts." --spice_print_cb_testbench"; + $vpr_spice_opts = $vpr_spice_opts." --spice_print_sb_testbench"; + } + if ("on" eq $opt_ptr->{vpr_fpga_spice_print_top_tb}) { + $vpr_spice_opts = $vpr_spice_opts." --spice_print_top_testbench"; + } + if ("on" eq $opt_ptr->{vpr_fpga_spice_leakage_only}) { + $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_leakage_only"; + } + if ("on" eq $opt_ptr->{vpr_fpga_spice_parasitic_net_estimation_off}) { + $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_parasitic_net_estimation_off"; + } + if ("on" eq $opt_ptr->{vpr_fpga_spice_testbench_load_extraction_off}) { + $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_testbench_load_extraction_off"; + } + } + if (("on" eq $opt_ptr->{power})&&("on" eq $opt_ptr->{vpr_fpga_spice_verilog_generator})) { + $vpr_spice_opts = $vpr_spice_opts." --fpga_syn_verilog"; + } + + if ("on" eq $opt_ptr->{vpr_fpga_spice_rename_illegal_port}) { + $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_rename_illegal_port"; + } + + my ($other_opt) = (""); + if ("on" eq $opt_ptr->{vpr_place_clb_pin_remap}) { + $other_opt = "--place_clb_pin_remap "; + } + if ("on" eq $opt_ptr->{vpr_route_breadthfirst}) { + $other_opt .= "--router_algorithm breadth_first "; + } + if ("on" eq $opt_ptr->{vpr_max_router_iteration}) { + $other_opt .= "--max_router_iterations $opt_ptr->{vpr_max_router_iteration_val} "; + } + + system("/bin/csh -cx './$vpr_name $arch $blif --net_file $net --place_file $place --route_file $route --full_stats --nodisp $power_opts $packer_opts $chan_width_opt $vpr_spice_opts $other_opt > $log'"); + + chdir $cwd; +} + +sub run_vpr_route($ $ $ $ $ $ $ $ $) +{ + my ($blif,$bm,$arch,$net,$place,$route,$fix_chan_width,$log,$act_file) = @_; + my ($vpr_dir,$vpr_name) = &split_prog_path($conf_ptr->{dir_path}->{vpr_path}->{val}); + chdir $vpr_dir; + + my ($power_opts); + if ("on" eq $opt_ptr->{power}) { + $power_opts = "--power --activity_file $act_file --tech_properties $conf_ptr->{flow_conf}->{power_tech_xml}->{val}"; + } else { + $power_opts = ""; + } + + my ($chan_width_opt) = (""); + if (($fix_chan_width > 0)||($fix_chan_width == 0)) { + $chan_width_opt = "-route_chan_width $fix_chan_width"; + } + + my ($vpr_spice_opts) = (""); + if (("on" eq $opt_ptr->{power})&&("on" eq $opt_ptr->{vpr_fpga_spice})) { + $vpr_spice_opts = "--fpga_spice"; + if ("on" eq $opt_ptr->{vpr_fpga_spice_print_cbsbtb}) { + $vpr_spice_opts = $vpr_spice_opts." --print_spice_cb_mux_testbench"; + $vpr_spice_opts = $vpr_spice_opts." --print_spice_sb_mux_testbench"; + } + if ("on" eq $opt_ptr->{vpr_fpga_spice_print_pbtb}) { + $vpr_spice_opts = $vpr_spice_opts." --print_spice_pb_mux_testbench"; + $vpr_spice_opts = $vpr_spice_opts." --print_spice_lut_testbench"; + $vpr_spice_opts = $vpr_spice_opts." --print_spice_hardlogic_testbench"; + } + if ("on" eq $opt_ptr->{vpr_fpga_spice_print_gridtb}) { + $vpr_spice_opts = $vpr_spice_opts." --print_spice_grid_testbench"; + } + if ("on" eq $opt_ptr->{vpr_fpga_spice_print_toptb}) { + $vpr_spice_opts = $vpr_spice_opts." --print_spice_top_testbench"; + } + if ("on" eq $opt_ptr->{vpr_fpga_spice_leakage_only}) { + $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_leakage_only"; + } + if ("on" eq $opt_ptr->{vpr_fpga_spice_parasitic_net_estimation_off}) { + $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_parasitic_net_estimation_off"; + } + } + if ("on" eq $opt_ptr->{vpr_fpga_spice_verilog_generator}) { + $vpr_spice_opts = $vpr_spice_opts." --fpga_syn_verilog"; + if ("on" eq $opt_ptr->{vpr_fpga_spice_rename_illegal_port}) { + $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_rename_illegal_port"; + } + } + + my ($other_opt) = (""); + if ("on" eq $opt_ptr->{vpr_max_router_iteration}) { + $other_opt .= "--max_router_iterations $opt_ptr->{vpr_max_router_iteration_val} "; + } + if ("on" eq $opt_ptr->{vpr_route_breadthfirst}) { + $other_opt .= "--router_algorithm breadth_first "; + } + + system("/bin/csh -cx './$vpr_name $arch $blif --route --blif_file $blif --net_file $net --place_file $place --route_file $route --full_stats --nodisp $power_opts $chan_width_opt $vpr_spice_opts $other_opt > $log'"); + + chdir $cwd; +} + +sub run_mpack1_vpr($ $ $ $ $ $ $) +{ + my ($blif,$arch,$net,$place,$route,$log,$act_file) = @_; + my ($vpr_dir,$vpr_name) = &split_prog_path($conf_ptr->{dir_path}->{vpr_path}->{val}); + my ($power_opts) = (""); + if ("on" eq $opt_ptr->{power}) { + $power_opts = "--power --activity_file $act_file --tech_properties $conf_ptr->{flow_conf}->{power_tech_xml}->{val}"; + } + chdir $vpr_dir; + system("/bin/csh -cx './$vpr_name $arch $blif --net_file $net --place_file $place --route_file $route --place --route --full_stats --nodisp $power_opts > $log'"); + chdir $cwd; +} + +sub run_mpack2_vpr($ $ $ $ $ $ $) +{ + my ($blif,$arch,$net,$place,$route,$min_chan_width,$log) = @_; + my ($vpr_dir,$vpr_name) = &split_prog_path($conf_ptr->{dir_path}->{vpr_path}->{val}); + + my ($power_opts) = (""); + if ("on" eq $opt_ptr->{power}) { + # $power_opts = "--power --activity_file $act_file --tech_properties $conf_ptr->{flow_conf}->{power_tech_xml}->{val}"; + } + my ($chan_width_opt) = (""); + if (($min_chan_width > 0)||($min_chan_width == 0)) { + $min_chan_width = int($min_chan_width*1.2); + if (0 != $min_chan_width%2) { + $min_chan_width += 1; + } + $chan_width_opt = "-route_chan_width $min_chan_width"; + } + + chdir $vpr_dir; + system("/bin/csh -cx './$vpr_name $arch $blif --net_file $net --place_file $place --route_file $route --place --route --full_stats --nodisp $power_opts $chan_width_opt > $log'"); + chdir $cwd; +} + + +sub run_aapack($ $ $ $) +{ + my ($blif,$arch,$net,$aapack_log) = @_; + my ($vpr_dir,$vpr_name) = &split_prog_path($conf_ptr->{dir_path}->{vpr_path}->{val}); + + chdir $vpr_dir; + + system("/bin/csh -cx './$vpr_name $arch $blif --net_file $net --pack --timing_analysis off --nodisp > $aapack_log'"); + + chdir $cwd; +} + +sub run_m2net_pack_arch($ $ $ $ $ $) +{ + my ($m2net_conf,$mpack1_rpt,$pack_arch,$N,$I,$m2net_pack_arch_log) = @_; + my ($m2net_dir,$m2net_name) = &split_prog_path($conf_ptr->{dir_path}->{m2net_path}->{val}); + + chdir $m2net_dir; + + system("/bin/csh -cx 'perl $m2net_name -conf $m2net_conf -mpack1_rpt $mpack1_rpt -mode pack_arch -N $N -I $I -arch_file_pack $pack_arch > $m2net_pack_arch_log'"); + + chdir $cwd; +} + +sub run_m2net_m2net($ $ $ $ $) +{ + my ($m2net_conf,$mpack1_rpt,$aapack_net,$vpr_net,$vpr_arch,$N,$I,$m2net_m2net_log) = @_; + my ($m2net_dir,$m2net_name) = &split_prog_path($conf_ptr->{dir_path}->{m2net_path}->{val}); + + chdir $m2net_dir; + + my ($power_opt) = (""); + + if ("on" eq $opt_ptr->{power}) { + $power_opt = "-power"; + } + + system("/bin/csh -cx 'perl $m2net_name -conf $m2net_conf -mpack1_rpt $mpack1_rpt -mode m2net -N $N -I $I -net_file_in $aapack_net -net_file_out $vpr_net -arch_file_vpr $vpr_arch $power_opt > $m2net_m2net_log'"); + + chdir $cwd; +} + +sub run_cirkit_mig_mccl_map($ $ $) { + my ($bm,$blif_out,$log) = @_; + my ($bm_aig, $bm_v) = ($blif_out, $blif_out); + $bm_aig =~ s/blif$/aig/; + $bm_v =~ s/blif$/v/; + + # Get ABC path + my ($abc_dir,$abc_name) = &split_prog_path($conf_ptr->{dir_path}->{abc_path}->{val}); + # Get Cirkit path + my ($cirkit_dir,$cirkit_name) = &split_prog_path($conf_ptr->{dir_path}->{cirkit_path}->{val}); + my ($lut_num) = $opt_ptr->{K_val}; + # Before we run this blif, identify it is a combinational or sequential + my ($abc_seq_optimize) = (""); + if (("on" eq $opt_ptr->{abc_scl})&&("seq" eq &check_blif_type($bm))) { + ($abc_seq_optimize) = ("scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;"); + } + my ($fpga_synthesis_method) = ("if"); + #my ($fpga_synthesis_method) = ("fpga"); + + # Run ABC to rewrite blif to AIG in verilog format + chdir $abc_dir; + system("/bin/csh -cx './$abc_name -c \"read_blif $bm; strash writ $bm_aig; quit;\" > $log'"); + if (!(-e $bm_aig)) { + die "ERROR: Fail ABC for benchmark $bm.\n"; + } + + chdir $cirkit_dir; + # Run FPGA ABC + system("/bin/csh -cx './$cirkit_name -c \"read_aiger $bm_aig; xmglut -k 4; write_verilog -x $bm_v; read_verilog -x --as_mig $bm_v; fpga -c 2 --blif_name $blif_out; quit;\" >> $log'"); + + if (!(-e $blif_out)) { + die "ERROR: Fail Cirkit for benchmark $bm.\n"; + } + + chdir $cwd; +} + +sub init_fpga_spice_task($) { + my ($task_file) = @_; + # Open the task file handler + my ($TASKFH) = (FileHandle->new); + if ($TASKFH->open("> $task_file")) { + print "Initializing FPGA SPICE task file($task_file)...\n"; + } else { + die "ERROR: fail to create task file ($task_file)!\n"; + } + + print $TASKFH "# FPGA SPICE TASKs to run\n"; + print $TASKFH "# Task line format:\n"; + print $TASKFH "# ,,\n"; + + # Close the file handler + close($TASKFH); +} + +# Print a line into task file which contains task info of FPGA SPICE. +sub output_fpga_spice_task($ $ $ $) { + my ($task_file, $benchmark, $blif_name, $rpt_dir) = @_; + my ($blif_path, $blif_prefix, $spice_dir); + + # Open the task file handler + my ($TASKFH) = (FileHandle->new); + if ($TASKFH->open(">> $task_file")) { + } else { + die "ERROR: fail to generate a line for task($benchmark) in task file ($task_file) ...\n"; + } + + ($blif_path,$blif_prefix) = &split_prog_path($blif_name); + $blif_prefix =~ s/\.blif$//; + $spice_dir = $rpt_dir; + $spice_dir =~ s/\/$//; + $spice_dir = $spice_dir."/spice_netlists/"; + # Output a line + print $TASKFH "# TaskInfo: $benchmark\n"; + print $TASKFH "$benchmark,$blif_prefix,$spice_dir\n"; + + # Close the file handler + close($TASKFH); +} + +sub run_ace_in_flow($ $ $ $ $ $ $) { + my ($prefix, $abc_blif_out, $act_file,$ace_new_blif,$ace_log) = @_; + + if ("on" eq $opt_ptr->{power}) { + if ("on" eq $opt_ptr->{black_box_ace}) { + my ($tmp_blif) = ($prefix."ace_new.blif"); + &black_box_blif($abc_blif_out,$tmp_blif); + &run_ace($tmp_blif,$act_file,$ace_new_blif ,$ace_log); + } else { + &run_ace($abc_blif_out,$act_file,$ace_new_blif,$ace_log); + $abc_blif_out = $ace_new_blif; + } + } + + if (!(-e $act_file)) { + die "ERROR: Fail ACE2 for benchmark $act_file.\n"; + } +} + +sub run_vpr_in_flow($ $ $ $ $ $ $ $ $ $ $ $) { + my ($tag, $benchmark,$benchmark_file, $abc_blif_out, $vpr_arch, $act_file, $vpr_net, $vpr_place, $vpr_route, $vpr_log, $vpr_reroute_log, $parse_results) = @_; + + if ("on" eq $opt_ptr->{min_route_chan_width}) { + &run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,-1,$vpr_log.".min_chan_width",$act_file); + # Get the Minimum channel width + my ($min_chan_width) = (&extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val}, $opt_ptr->{min_route_chan_width}, $parse_results)); + $min_chan_width = int($min_chan_width*$opt_ptr->{min_route_chan_width_val}); + if (0 != $min_chan_width%2) { + $min_chan_width += 1; + } + # Remove previous route results + if (-e $vpr_route) { + `rm $vpr_route`; + } + # Keep increase min_chan_width until route success + # Extract data from VPR stats + #&run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$min_chan_width,$vpr_log,$act_file); + while (1) { + &run_vpr_route($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$min_chan_width,$vpr_reroute_log,$act_file); + # TODO: Only run the routing stage + if (-e $vpr_route) { + print "INFO: try route_chan_width($min_chan_width) success!\n"; + last; #Jump out + } else { + print "INFO: try route_chan_width($min_chan_width) failed! Retry with +2...\n"; + $min_chan_width += 2; + } + } + if (1 == $parse_results) { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}, "off", $parse_results); + &extract_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val}); + &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); + } + } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { + my ($fix_chan_width) = ($benchmarks_ptr->{$benchmark_file}->{fix_route_chan_width}); + # Remove previous route results + if (-e $vpr_route) { + `rm $vpr_route`; + } + # Keep increase min_chan_width until route success + &run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$fix_chan_width,$vpr_log,$act_file); + while (1) { + # TODO: Only run the routing stage + if (-e $vpr_route) { + print "INFO: try route_chan_width($fix_chan_width) success!\n"; + last; #Jump out + } else { + print "INFO: try route_chan_width($fix_chan_width) failed! Retry with +2...\n"; + $fix_chan_width += 2; + &run_vpr_route($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$fix_chan_width,$vpr_reroute_log,$act_file); + } + } + # Extract data from VPR stats + if (1 == $parse_results) { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}, "off", $parse_results); + &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); + if (-e $vpr_reroute_log) { + &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); + } + } + } else { + &run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,-1,$vpr_log,$act_file); + if (!(-e $vpr_route)) { + die "ERROR: Route Fail for $abc_blif_out!\n"; + } + # Get the Minimum channel width + my ($min_chan_width) = (&extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val},"on",$parse_results)); + if (1 == $parse_results) { + &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); + } + } + + # Extract data from VPR Power stats + if (("on" eq $opt_ptr->{power}) + &&(1 == $parse_results)) { + &extract_vpr_power_esti($tag,$abc_blif_out,$benchmark,$opt_ptr->{K_val}); + } + + return; +} + + +sub run_mig_mccl_flow($ $ $ $) { + my ($tag,$benchmark_file,$vpr_arch, $parse_results) = @_; + my ($benchmark, $rpt_dir,$prefix); + my ($cirkit_bm,$cirkit_blif_out,$cirkit_log,$cirkit_blif_out_bak); + + $benchmark = $benchmark_file; + $benchmark =~ s/\.blif$//g; + # Run Standard flow + $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; + &generate_path($rpt_dir); + $cirkit_bm = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".blif"; + $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; + $cirkit_blif_out = "$prefix"."cirkit.blif"; + $cirkit_blif_out_bak = "$prefix"."cirkit_bak.blif"; + $cirkit_log = "$prefix"."cirkit.log"; + + my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace.blif","$prefix"."ace.log"); + + my ($vpr_net,$vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log); + + $vpr_net = "$prefix"."vpr.net"; + $vpr_place = "$prefix"."vpr.place"; + $vpr_route = "$prefix"."vpr.route"; + $vpr_log = "$prefix"."vpr.log"; + $vpr_reroute_log = "$prefix"."vpr_reroute.log"; + + &run_cirkit_mig_mccl_map($cirkit_bm,$cirkit_blif_out,$cirkit_log); + if (!(-e $cirkit_blif_out)) { + die "ERROR: Fail Cirkit for benchmark $cirkit_blif_out.\n"; + } + + #`perl pro_blif.pl -i $abc_blif_out_bak -o $abc_blif_out`; + #if (!(-e $abc_blif_out)) { + # die "ERROR: Fail pro_blif.pl for benchmark $abc_blif_out.\n"; + #} + + &run_ace_in_flow($prefix, $cirkit_blif_out, $act_file, $ace_new_blif, $ace_log); + + &run_vpr_in_flow($tag, $benchmark, $benchmark_file, $cirkit_blif_out, $vpr_arch, $act_file, $vpr_net, $vpr_place, $vpr_route, $vpr_log, $vpr_reroute_log, $parse_results); + + return; +} + + +sub run_standard_flow($ $ $ $ $) +{ + my ($tag,$benchmark_file,$vpr_arch,$flow_enhance, $parse_results) = @_; + my ($benchmark, $rpt_dir,$prefix); + my ($abc_bm,$abc_blif_out,$abc_log,$abc_blif_out_bak); + my ($mpack_blif_out,$mpack_stats,$mpack_log); + my ($vpr_net,$vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log); + + $benchmark = $benchmark_file; + $benchmark =~ s/\.blif$//g; + # Run Standard flow + $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; + &generate_path($rpt_dir); + $abc_bm = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".blif"; + $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; + $abc_blif_out = "$prefix"."abc.blif"; + $abc_blif_out_bak = "$prefix"."abc_bak.blif"; + $abc_log = "$prefix"."abc.log"; + + if ("abc_black_box" eq $flow_enhance) { + my ($pre_abc_blif) = ("$prefix"."pre_abc.blif"); + `perl pro_blif.pl -i $abc_bm -o $pre_abc_blif`; + &run_abc_bb_fpgamap($pre_abc_blif,$abc_blif_out_bak,$abc_log); + } elsif ("classic" eq $flow_enhance) { + &run_abc_fpgamap($abc_bm,$abc_blif_out_bak,$abc_log); + } + + `perl pro_blif.pl -i $abc_blif_out_bak -o $abc_blif_out`; + + if (!(-e $abc_blif_out)) { + die "ERROR: Fail pro_blif.pl for benchmark $abc_blif_out.\n"; + } + + my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace.blif","$prefix"."ace.log"); + if ("on" eq $opt_ptr->{power}) { + if ("on" eq $opt_ptr->{black_box_ace}) { + &black_box_blif($abc_blif_out,$ace_new_blif); + &run_ace($ace_new_blif,$act_file,$prefix."ace_new.blif",$ace_log); + } else { + &run_ace($abc_blif_out,$act_file,$ace_new_blif,$ace_log); + $abc_blif_out = $ace_new_blif; + } + + if (!(-e $act_file)) { + die "ERROR: Fail ACE2 for benchmark $act_file.\n"; + } + } + + $vpr_net = "$prefix"."vpr.net"; + $vpr_place = "$prefix"."vpr.place"; + $vpr_route = "$prefix"."vpr.route"; + $vpr_log = "$prefix"."vpr.log"; + $vpr_reroute_log = "$prefix"."vpr_reroute.log"; + + if ("on" eq $opt_ptr->{min_route_chan_width}) { + &run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,-1,$vpr_log.".min_chan_width",$act_file); + # Get the Minimum channel width + my ($min_chan_width) = (&extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val}, $opt_ptr->{min_route_chan_width}, $parse_results)); + $min_chan_width = int($min_chan_width*$opt_ptr->{min_route_chan_width_val}); + if (0 != $min_chan_width%2) { + $min_chan_width += 1; + } + # Remove previous route results + if (-e $vpr_route) { + `rm $vpr_route`; + } + # Keep increase min_chan_width until route success + # Extract data from VPR stats + #&run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$min_chan_width,$vpr_log,$act_file); + while (1) { + &run_vpr_route($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$min_chan_width,$vpr_reroute_log,$act_file); + # TODO: Only run the routing stage + if (-e $vpr_route) { + print "INFO: try route_chan_width($min_chan_width) success!\n"; + last; #Jump out + } else { + print "INFO: try route_chan_width($min_chan_width) failed! Retry with +2...\n"; + $min_chan_width += 2; + } + } + if (1 == $parse_results) { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}, "off", $parse_results); + &extract_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val}); + &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); + } + } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { + my ($fix_chan_width) = ($benchmarks_ptr->{$benchmark_file}->{fix_route_chan_width}); + # Remove previous route results + if (-e $vpr_route) { + `rm $vpr_route`; + } + # Keep increase min_chan_width until route success + &run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$fix_chan_width,$vpr_log,$act_file); + while (1) { + # TODO: Only run the routing stage + if (-e $vpr_route) { + print "INFO: try route_chan_width($fix_chan_width) success!\n"; + last; #Jump out + } else { + print "INFO: try route_chan_width($fix_chan_width) failed! Retry with +2...\n"; + $fix_chan_width += 2; + &run_vpr_route($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$fix_chan_width,$vpr_reroute_log,$act_file); + } + } + # Extract data from VPR stats + if (1 == $parse_results) { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}, "off", $parse_results); + &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); + if (-e $vpr_reroute_log) { + &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); + } + } + } else { + &run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,-1,$vpr_log,$act_file); + if (!(-e $vpr_route)) { + die "ERROR: Route Fail for $abc_blif_out!\n"; + } + # Get the Minimum channel width + my ($min_chan_width) = (&extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val},"on",$parse_results)); + if (1 == $parse_results) { + &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); + } + } + + # Extract data from VPR Power stats + if (("on" eq $opt_ptr->{power}) + &&(1 == $parse_results)) { + &extract_vpr_power_esti($tag,$abc_blif_out,$benchmark,$opt_ptr->{K_val}); + } + + return; +} + +sub parse_standard_flow_results($ $ $ $) +{ + my ($tag,$benchmark_file,$vpr_arch,$flow_enhance) = @_; + my ($rpt_dir,$prefix); + my ($abc_bm,$abc_blif_out,$abc_log); + my ($mpack_blif_out,$mpack_stats,$mpack_log); + my ($vpr_net,$vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log); + + my ($benchmark) = ($benchmark_file); + $benchmark =~ s/\.blif$//g; + # Run Standard flow + $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; + &generate_path($rpt_dir); + $abc_bm = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".blif"; + $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; + $abc_blif_out = "$prefix"."abc.blif"; + $abc_log = "$prefix"."abc.log"; + + if ("abc_black_box" eq $flow_enhance) { + rename $abc_blif_out,"$abc_blif_out".".bak"; + } elsif ("classic" eq $flow_enhance) { + } + + my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace.blif","$prefix"."ace.log"); + if ("on" eq $opt_ptr->{power}) { + if ("on" eq $opt_ptr->{black_box_ace}) { + } else { + $abc_blif_out = $ace_new_blif; + } + } + + $vpr_net = "$prefix"."vpr.net"; + $vpr_place = "$prefix"."vpr.place"; + $vpr_route = "$prefix"."vpr.route"; + $vpr_log = "$prefix"."vpr.log"; + $vpr_reroute_log = "$prefix"."vpr_reroute.log"; + + if ("on" eq $opt_ptr->{min_route_chan_width}) { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val},"on",1); + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val},"off",1); + &extract_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val}); + &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); + } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val},"off",1); + &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); + if (-e $vpr_reroute_log) { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val},"off",1); + &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); + } + } else { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val},"on",1); + &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); + } + + # Extract data from VPR Power stats + if ("on" eq $opt_ptr->{power}) { + &extract_vpr_power_esti($tag,$abc_blif_out,$benchmark,$opt_ptr->{K_val}); + } + + # TODO: HOW TO DEAL WITH SPICE NETLISTS??? + # Output a file contain information of SPICE Netlists + if ("on" eq $opt_ptr->{vpr_fpga_spice}) { + &output_fpga_spice_task("$opt_ptr->{vpr_fpga_spice_val}"."_standard.txt", $benchmark, $abc_blif_out, $rpt_dir); + } + + return; +} + +sub run_mpack2_flow($ $ $ $) +{ + my ($tag,$benchmark_file,$mpack2_arch,$parse_results) = @_; + my ($rpt_dir,$prefix); + my ($abc_bm,$abc_blif_out,$abc_log,$abc_blif_out_bak); + my ($mpack2_blif_out,$mpack2_vpr_net,$mpack2_stats,$mpack2_log,$mpack2_vpr_arch); + my ($vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log,$act_file); + + # Check necessary options + if (!($opt_ptr->{N_val})) { + die "ERROR: (mpack2_flow) -N should be specified!\n"; + } + if (!($opt_ptr->{K_val})) { + die "ERROR: (mpack2_flow) -K should be specified!\n"; + } + + my ($benchmark) = ($benchmark_file); + $benchmark =~ s/\.blif$//g; + # Run MPACK2-oriented flow + $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; + &generate_path($rpt_dir); + $abc_bm = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".blif"; + $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; + $abc_blif_out = "$prefix"."abc.blif"; + $abc_blif_out_bak = "$prefix"."abc_bak.blif"; + $abc_log = "$prefix"."abc.log"; + + # RUN ABC + #&run_abc_libmap($abc_bm,"$abc_blif_out\.bak",$abc_log); + &run_abc_fpgamap($abc_bm,$abc_blif_out_bak,$abc_log); + + # Pre-process the blif netlist + #`perl convert_blif.pl -i $abc_blif_out\.bak -o $abc_blif_out\.conv`; + `perl pro_blif.pl -i $abc_blif_out_bak -o $abc_blif_out`; + + # RUN MPACK2 + $mpack2_blif_out = "$prefix"."mpack2.blif"; + $mpack2_vpr_net = "$prefix"."mpack2.net"; + $mpack2_stats = "$prefix"."mpack2.stats"; + $mpack2_log = "$prefix"."mpack2.log"; + $mpack2_vpr_arch = "$prefix"."mpack2_vpr_arch.xml"; + &run_mpack2($abc_blif_out,$mpack2_blif_out,$mpack2_arch,$mpack2_vpr_net,$mpack2_stats,$mpack2_vpr_arch,$mpack2_log); + # Extract data from MPACK stats + if (1 == $parse_results) { + &extract_mpack2_stats($tag,$benchmark,$mpack2_stats); + } + + # RUN VPR + $vpr_place = "$prefix"."vpr.place"; + $vpr_route = "$prefix"."vpr.route"; + $vpr_log = "$prefix"."vpr.log"; + $vpr_reroute_log = "$prefix"."vpr_reroute.log"; + + if ("on" eq $opt_ptr->{min_route_chan_width}) { + &run_mpack2_vpr($mpack2_blif_out,$mpack2_vpr_arch,$mpack2_vpr_net,$vpr_place,$vpr_route,-1,$vpr_log.".min_chan_width"); + # Get the Minimum channel width + my ($min_chan_width) = (&extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val}, $opt_ptr->{min_route_chan_width}, $parse_results)); + $min_chan_width = int($min_chan_width*$opt_ptr->{min_route_chan_width_val}); + if (0 != $min_chan_width%2) { + $min_chan_width += 1; + } + + # Remove previous route results + `rm $vpr_route`; + # Keep increase min_chan_width until route success + # Extract data from VPR stats + while (1) { + &run_vpr_route($mpack2_blif_out,$benchmark,$mpack2_vpr_arch,$mpack2_vpr_net,$vpr_place,$vpr_route,$min_chan_width,$vpr_reroute_log,$act_file); + if (-e $vpr_route) { + print "INFO: try route_chan_width($min_chan_width) Success!\n"; + last; #Jump out + } else { + print "INFO: try route_chan_width($min_chan_width) failed! Retry with +2...\n"; + $min_chan_width += 2; + } + } + # Extract data from VPR stats + if (1 == $parse_results) { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}, "off", $parse_results); + &extract_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val}); + &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); + } + } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { + my ($fix_chan_width) = ($benchmarks_ptr->{$benchmark_file}->{fix_route_chan_width}); + # Remove previous route results + if (-e $vpr_route) { + `rm $vpr_route`; + } + # Keep increase min_chan_width until route success + # Extract data from VPR stats + &run_mpack2_vpr($mpack2_blif_out,$mpack2_vpr_arch,$mpack2_vpr_net,$vpr_place,$vpr_route,$fix_chan_width,$vpr_log); + while (1) { + if (-e $vpr_route) { + print "INFO: try route_chan_width($fix_chan_width) success!\n"; + last; #Jump out + } else { + print "INFO: try route_chan_width($fix_chan_width) failed! Retry with +2...\n"; + $fix_chan_width += 2; + &run_vpr_route($mpack2_blif_out,$benchmark,$mpack2_vpr_arch,$mpack2_vpr_net,$vpr_place,$vpr_route,$fix_chan_width,$vpr_reroute_log,$act_file); + } + } + if (1 == $parse_results) { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}, "off", $parse_results); + &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); + if (-e $vpr_reroute_log) { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}, "off", $parse_results); + &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); + } + } + } else { + &run_mpack2_vpr($mpack2_blif_out,$mpack2_vpr_arch,$mpack2_vpr_net,$vpr_place,$vpr_route,-1,$vpr_log); + if (!(-e $vpr_route)) { + die "ERROR: Route Fail for $mpack2_blif_out!\n"; + } + my ($min_chan_width) = (&extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}, $parse_results)); + # Extract data from VPR stats + if (1 == $parse_results) { + &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); + } + } + return; +} + +sub parse_mpack2_flow_results($ $ $) +{ + my ($tag,$benchmark_file,$mpack2_arch) = @_; + my ($rpt_dir,$prefix); + my ($abc_bm,$abc_blif_out,$abc_log); + my ($mpack2_blif_out,$mpack2_vpr_net,$mpack2_stats,$mpack2_log,$mpack2_vpr_arch); + my ($vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log); + + # Check necessary options + if (!($opt_ptr->{N_val})) { + die "ERROR: (mpack2_flow) -N should be specified!\n"; + } + if (!($opt_ptr->{K_val})) { + die "ERROR: (mpack2_flow) -K should be specified!\n"; + } + + my ($benchmark) = ($benchmark_file); + $benchmark =~ s/\.blif$//g; + # Run MPACK2-oriented flow + $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; + &generate_path($rpt_dir); + $abc_bm = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".blif"; + $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; + $abc_blif_out = "$prefix"."abc.blif"; + $abc_log = "$prefix"."abc.log"; + + # Pre-process the blif netlist + + # RUN MPACK2 + $mpack2_blif_out = "$prefix"."mpack2.blif"; + $mpack2_vpr_net = "$prefix"."mpack2.net"; + $mpack2_stats = "$prefix"."mpack2.stats"; + $mpack2_log = "$prefix"."mpack2.log"; + $mpack2_vpr_arch = "$prefix"."mpack2_vpr_arch.xml"; + # Extract data from MPACK stats + &extract_mpack2_stats($tag,$benchmark,$mpack2_stats); + + # RUN VPR + $vpr_place = "$prefix"."vpr.place"; + $vpr_route = "$prefix"."vpr.route"; + $vpr_log = "$prefix"."vpr.log"; + $vpr_reroute_log = "$prefix"."vpr_reroute.log"; + + if ("on" eq $opt_ptr->{min_route_chan_width}) { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val},"on",1); + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val},"off",1); + &extract_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val}); + &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); + } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { + &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); + if (-e $vpr_reroute_log) { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val},"off",1); + &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); + } else { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val},"off",1); + } + &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); + } else { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}, "on", 1); + &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); + } + + return; +} + +sub run_mpack1_flow($ $ $) +{ + my ($tag,$benchmark_file, $parse_results) = @_; + my ($rpt_dir,$prefix); + my ($abc_bm,$abc_blif_out,$abc_log); + my ($vpr_net,$vpr_place,$vpr_route,$vpr_log); + my ($I_val,$M_val,$N_val) = ($opt_ptr->{I_val},$opt_ptr->{M_val},$opt_ptr->{N_val}); + my ($m2net_conf) = ($conf_ptr->{flow_conf}->{m2net_conf}->{val}); + my ($cell_size) = (2); + + if ($I_val) { + } else { + $I_val = int($cell_size*$M_val*($N_val+1)/2); + print "INFO: I isn't defined. Auto-sized to 2*M*(N+1)/2 = $I_val\n"; + } + + my ($benchmark) = ($benchmark_file); + $benchmark =~ s/\.blif$//g; + # Run MPACK1-oriented flow + $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; + &generate_path($rpt_dir); + $abc_bm = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".blif"; + $prefix = "$rpt_dir/$benchmark\_"."M$M_val\_"."N$N_val\_"; + $abc_blif_out = "$prefix"."abc.blif"; + $abc_log = "$prefix"."abc.log"; + + &run_abc_libmap($abc_bm,"$abc_blif_out\.bak",$abc_log); + `perl pro_blif.pl -i "$abc_blif_out\.bak" -o $abc_blif_out`; + + my ($mpack1_pack_blif_out) = ("$prefix"."_matrix.blif"); + my ($mpack1_vpr_blif_out) = ("$prefix"."_formatted.blif"); + my ($mpack1_rpt) = ("$prefix"."_mapped.net"); + my ($mpack1_log) = ("$prefix"."mpack1p5.log"); + &run_mpack1p5("$abc_blif_out","$prefix",$M_val,$cell_size,$mpack1_log); + + # Extract data from MPACK stats + if (1 == $parse_results) { + &extract_mpack1_stats($tag,$benchmark,$mpack1_log); + } + + # Generate Architecture XML + my ($aapack_arch) = ("$prefix"."aapack_arch.xml"); + my ($m2net_pack_arch_log) = ("$prefix"."m2net_pack_arch.log"); + &run_m2net_pack_arch($m2net_conf,$mpack1_rpt,$aapack_arch,$N_val,$I_val,$m2net_pack_arch_log); + + # Run AAPACK + my ($aapack_log) = ("$prefix"."aapack.log"); + my ($aapack_net) = ("$prefix"."aapack.net"); + &run_aapack($mpack1_pack_blif_out,$aapack_arch,$aapack_net,$aapack_log); + my @aapack_stats = ("MATRIX"); + if (1 == $parse_results) { + &extract_aapack_stats($tag,$benchmark,$aapack_log,$M_val,\@aapack_stats); + } + + $vpr_net = "$prefix"."mpack.net"; + $vpr_place = "$prefix"."vpr.place"; + $vpr_route = "$prefix"."vpr.route"; + $vpr_log = "$prefix"."vpr.log"; + + # Run m2net.pl + my ($vpr_arch) = ("$prefix"."vpr_arch.xml"); + my ($m2net_m2net_log) = ("$prefix"."m2net_m2net.log"); + &run_m2net_m2net($m2net_conf,$mpack1_rpt,$aapack_net,$vpr_net,$vpr_arch,$N_val,$I_val,$m2net_m2net_log); + + my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace_new.blif","$prefix"."ace.log"); + # Turn on Power Estimation and Run ace + if ("on" eq $opt_ptr->{power}) { + &run_ace($mpack1_vpr_blif_out,$act_file,$ace_new_blif,$ace_log); + } + + &run_mpack1_vpr($mpack1_vpr_blif_out,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$vpr_log,$act_file); + if (!(-e $vpr_route)) { + die "ERROR: Route Fail for $mpack1_vpr_blif_out!\n"; + } + + # Extract data from VPR stats + if (1 == $parse_results) { + &extract_vpr_stats($tag,$benchmark,$vpr_log,$M_val); + } + + if (("on" eq $opt_ptr->{power}) + &&(1 == $parse_results)) { + &extract_vpr_power_esti($tag,$mpack1_vpr_blif_out,$benchmark,$M_val); + } +} + +sub parse_mpack1_flow_results($ $) { + my ($tag,$benchmark_file) = @_; + my ($rpt_dir,$prefix); + my ($abc_bm,$abc_blif_out,$abc_log); + my ($vpr_net,$vpr_place,$vpr_route,$vpr_log); + my ($I_val,$M_val,$N_val) = ($opt_ptr->{I_val},$opt_ptr->{M_val},$opt_ptr->{N_val}); + my ($m2net_conf) = ($conf_ptr->{flow_conf}->{m2net_conf}->{val}); + my ($cell_size) = (2); + + if ($I_val) { + } else { + $I_val = int($cell_size*$M_val*($N_val+1)/2); + print "INFO: I isn't defined. Auto-sized to 2*M*(N+1)/2 = $I_val\n"; + } + + my ($benchmark) = ($benchmark_file); + $benchmark =~ s/\.blif$//g; + # Run MPACK1-oriented flow + $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; + &generate_path($rpt_dir); + $abc_bm = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".blif"; + $prefix = "$rpt_dir/$benchmark\_"."M$M_val\_"."N$N_val\_"; + $abc_blif_out = "$prefix"."abc.blif"; + $abc_log = "$prefix"."abc.log"; + + my ($mpack1_pack_blif_out) = ("$prefix"."_matrix.blif"); + my ($mpack1_vpr_blif_out) = ("$prefix"."_formatted.blif"); + my ($mpack1_rpt) = ("$prefix"."_mapped.net"); + my ($mpack1_log) = ("$prefix"."mpack1p5.log"); + + # Extract data from MPACK stats + &extract_mpack1_stats($tag,$benchmark,$mpack1_log); + + # Generate Architecture XML + my ($aapack_arch) = ("$prefix"."aapack_arch.xml"); + my ($m2net_pack_arch_log) = ("$prefix"."m2net_pack_arch.log"); + + # Run AAPACK + my ($aapack_log) = ("$prefix"."aapack.log"); + my ($aapack_net) = ("$prefix"."aapack.net"); + my @aapack_stats = ("MATRIX"); + &extract_aapack_stats($tag,$benchmark,$aapack_log,$M_val,\@aapack_stats); + + $vpr_net = "$prefix"."mpack.net"; + $vpr_place = "$prefix"."vpr.place"; + $vpr_route = "$prefix"."vpr.route"; + $vpr_log = "$prefix"."vpr.log"; + + # Run m2net.pl + my ($vpr_arch) = ("$prefix"."vpr_arch.xml"); + my ($m2net_m2net_log) = ("$prefix"."m2net_m2net.log"); + my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace_new.blif","$prefix"."ace.log"); + + # Extract data from VPR stats + &extract_vpr_stats($tag,$benchmark,$vpr_log,$M_val); + + if ("on" eq $opt_ptr->{power}) { + &extract_vpr_power_esti($tag,$mpack1_vpr_blif_out,$benchmark,$M_val); + } +} + + +sub run_vtr_flow($ $ $ $) { + my ($tag,$benchmark_file,$vpr_arch,$parse_results) = @_; + my ($rpt_dir,$prefix); + my ($min_hard_adder_size, $mem_size, $odin2_verilog, $odin2_config, $odin2_log); + my ($abc_bm,$abc_blif_out,$abc_log,$abc_blif_out_bak); + my ($vpr_net,$vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log); + + # The input of VTR flow is verilog file + my ($benchmark) = ($benchmark_file); + $benchmark =~ s/\.v$//g; + # Run Verilog To Routiing flow + $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; + &generate_path($rpt_dir); + # ODIN II output blif + $odin2_verilog = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".v"; + $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; + # ODIN II config XML + $odin2_config = "$prefix"."odin2_config.xml"; + $odin2_log = "$prefix"."odin2.log"; + # ODIN II output blif + $abc_bm = "$prefix"."odin2.blif"; + # ABC II output blif + $abc_blif_out = "$prefix"."abc.blif"; + $abc_blif_out_bak = "$prefix"."abc_bak.blif"; + $abc_log = "$prefix"."abc.log"; + + # Initialize min_hard_adder_size + $min_hard_adder_size = 1; # Default value + if ("on" eq $opt_ptr->{min_hard_adder_size}) { + if (1 > $opt_ptr->{min_hard_adder_size_val}) { + die "ERROR: Invalid min_hard_adder_size($opt_ptr->{min_hard_adder_size})!Should be no less than 1!"; + } else { + $min_hard_adder_size = $opt_ptr->{min_hard_adder_size_val}; + } + } + # TODO: Initialize the mem_size by parsing the ARCH XML? + if ("on" eq $opt_ptr->{mem_size}) { + $mem_size = $opt_ptr->{mem_size_val}; + } else { + die "ERROR: -mem_size is mandatory when vtr flow is chosen!\n"; + } + # Auto-generate a configuration XML for ODIN2 + &gen_odin2_config_xml($odin2_config, $odin2_verilog, $abc_bm, $vpr_arch, $mem_size, $min_hard_adder_size); + # RUN ODIN II + &run_odin2($odin2_config, "off", $odin2_log); + + if (!(-e $abc_bm)) { + die "ERROR: Fail ODIN II for benchmark $benchmark.\n"; + } + + # RUN ABC + &run_abc_bb_fpgamap($abc_bm,$abc_blif_out_bak,$abc_log); + + `perl pro_blif.pl -i $abc_blif_out_bak -o $abc_blif_out`; + if (!(-e $abc_blif_out_bak)) { + die "ERROR: Fail pro_blif for benchmark $benchmark.\n"; + } + + my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace.blif","$prefix"."ace.log"); + if ("on" eq $opt_ptr->{power}) { + &run_ace($abc_blif_out,$act_file,$ace_new_blif,$ace_log); + $abc_blif_out = $ace_new_blif; + } + + $vpr_net = "$prefix"."vpr.net"; + $vpr_place = "$prefix"."vpr.place"; + $vpr_route = "$prefix"."vpr.route"; + $vpr_log = "$prefix"."vpr.log"; + $vpr_reroute_log = "$prefix"."vpr_reroute.log"; + + if ("on" eq $opt_ptr->{min_route_chan_width}) { + &run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,-1,$vpr_log.".min_chan_width",$act_file); + # Get the Minimum channel width + my ($min_chan_width) = (&extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val}, $opt_ptr->{min_route_chan_width}, $parse_results)); + $min_chan_width = int($min_chan_width*$opt_ptr->{min_route_chan_width_val}); + if (0 != $min_chan_width%2) { + $min_chan_width += 1; + } + # Remove previous route results + `rm $vpr_route`; + # Keep increase min_chan_width until route success + # Extract data from VPR stats + while (1) { + &run_vpr_route($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$min_chan_width,$vpr_reroute_log,$act_file); + if (-e $vpr_route) { + print "INFO: try route_chan_width($min_chan_width) Success!\n"; + last; #Jump out + } else { + print "INFO: try route_chan_width($min_chan_width) failed! Retry with +2...\n"; + $min_chan_width += 2; + } + } + # Extract data from VPR stats + if (1 == $parse_results) { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}, "off", $parse_results); + &extract_vpr_stats($tag,$benchmark,$vpr_log."min_chan_width",$opt_ptr->{K_val}); + &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); + } + } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { + my ($fix_chan_width) = ($benchmarks_ptr->{$benchmark_file}->{fix_route_chan_width}); + # Remove previous route results + `rm $vpr_route`; + # Keep increase min_chan_width until route success + &run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$fix_chan_width,$vpr_log,$act_file); + # Extract data from VPR stats + while (1) { + if (-e $vpr_route) { + print "INFO: try route_chan_width($fix_chan_width) Success!\n"; + last; #Jump out + } else { + print "INFO: try route_chan_width($fix_chan_width) failed! Retry with +2...\n"; + $fix_chan_width += 2; + &run_vpr_route($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$fix_chan_width,$vpr_reroute_log,$act_file); + } + } + if (1 == $parse_results) { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}, "off", $parse_results); + &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); + if (-e $vpr_reroute_log) { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}, "off", $parse_results); + &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); + } + } + } else { + &run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,-1,$vpr_log,$act_file); + if (!(-e $vpr_route)) { + die "ERROR: Route Fail for $abc_blif_out!\n"; + } + # Get the Minimum channel width + my ($min_chan_width) = (&extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val},$parse_results)); + if (1 == $parse_results) { + &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); + } + } + + # Extract data from VPR Power stats + if (("on" eq $opt_ptr->{power}) + &&(1 == $parse_results)) { + &extract_vpr_power_esti($tag,$abc_blif_out,$benchmark,$opt_ptr->{K_val}); + } + return; +} + +sub parse_vtr_flow_results($ $ $) { + my ($tag,$benchmark,$vpr_arch) = @_; + my ($min_hard_adder_size, $mem_size, $odin2_verilog, $odin2_config, $odin2_log); + my ($rpt_dir,$prefix); + my ($abc_bm,$abc_blif_out,$abc_log); + my ($mpack_blif_out,$mpack_stats,$mpack_log); + my ($vpr_net,$vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log); + + $benchmark =~ s/\.v$//g; + # Run Standard flow + $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; + &generate_path($rpt_dir); + # ODIN II output blif + $odin2_verilog = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".v"; + $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; + # ODIN II config XML + $odin2_config = "$prefix"."odin2_config.xml"; + $odin2_log = "$prefix"."odin2.log"; + # ODIN II output blif + $abc_bm = "$prefix"."odin2.blif"; + # ABC output blif + $abc_blif_out = "$prefix"."abc.blif"; + $abc_log = "$prefix"."abc.log"; + + rename $abc_blif_out,"$abc_blif_out".".bak"; + + my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace.blif","$prefix"."ace.log"); + if ("on" eq $opt_ptr->{power}) { + if ("on" eq $opt_ptr->{black_box_ace}) { + } else { + $abc_blif_out = $ace_new_blif; + } + } + + $vpr_net = "$prefix"."vpr.net"; + $vpr_place = "$prefix"."vpr.place"; + $vpr_route = "$prefix"."vpr.route"; + $vpr_log = "$prefix"."vpr.log"; + $vpr_reroute_log = "$prefix"."vpr_reroute.log"; + + if ("on" eq $opt_ptr->{min_route_chan_width}) { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val},"on",1); + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val},"off",1); + &extract_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val}); + &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); + } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { + &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); + if (-e $vpr_reroute_log) { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val},"off",1); + &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); + } else { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val},"off",1); + } + } else { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}, "on", 1); + &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); + } + + # Extract data from VPR Power stats + if ("on" eq $opt_ptr->{power}) { + &extract_vpr_power_esti($tag,$abc_blif_out,$benchmark,$opt_ptr->{K_val}); + } + + # TODO: HOW TO DEAL WITH SPICE NETLISTS??? + # Output a file contain information of SPICE Netlists + if ("on" eq $opt_ptr->{vpr_fpga_spice}) { + &output_fpga_spice_task("$opt_ptr->{vpr_fpga_spice_val}"."_vtr.txt", $benchmark, $abc_blif_out, $rpt_dir); + } + + return; +} + +# VTR_MCCL_flow: +# Differences from vtr_flow: +# 1. Need to turn off the carry-chain support for ODIN II +# 2. Use Carry-chain detection and Carry-chain LUTs pre-mapping in ABC scripts +sub run_vtr_mccl_flow($ $ $ $) { + my ($tag,$benchmark_file,$vpr_arch,$parse_results) = @_; + my ($rpt_dir,$prefix); + my ($min_hard_adder_size, $mem_size, $odin2_verilog, $odin2_config, $odin2_log); + my ($abc_bm,$abc_blif_out,$abc_log,$abc_blif_out_bak); + my ($vpr_net,$vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log); + my ($odin2_carry_chain_support) = ("on"); + + # The input of VTR flow is verilog file + my ($benchmark) = ($benchmark_file); + $benchmark =~ s/\.v$//g; + # Run Verilog To Routiing flow + $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; + &generate_path($rpt_dir); + # ODIN II output blif + $odin2_verilog = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".v"; + $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; + # ODIN II config XML + $odin2_config = "$prefix"."odin2_config.xml"; + $odin2_log = "$prefix"."odin2.log"; + # ODIN II output blif + $abc_bm = "$prefix"."odin2.blif"; + # ABC II output blif + $abc_blif_out = "$prefix"."abc.blif"; + $abc_blif_out_bak = "$prefix"."abc_bak.blif"; + $abc_log = "$prefix"."abc.log"; + + # Initialize min_hard_adder_size + $min_hard_adder_size = 1; # Default value + if ("on" eq $opt_ptr->{min_hard_adder_size}) { + if (1 > $opt_ptr->{min_hard_adder_size_val}) { + die "ERROR: Invalid min_hard_adder_size($opt_ptr->{min_hard_adder_size})!Should be no less than 1!"; + } else { + $min_hard_adder_size = $opt_ptr->{min_hard_adder_size_val}; + } + } + # TODO: Initialize the mem_size by parsing the ARCH XML? + if ("on" eq $opt_ptr->{mem_size}) { + $mem_size = $opt_ptr->{mem_size_val}; + } else { + die "ERROR: -mem_size is mandatory when vtr flow is chosen!\n"; + } + # Auto-generate a configuration XML for ODIN2 + &gen_odin2_config_xml($odin2_config, $odin2_verilog, $abc_bm, $vpr_arch, $mem_size, $min_hard_adder_size); + + if ("on" eq $opt_ptr->{odin2_carry_chain_support}) { + $odin2_carry_chain_support = ("on"); + } + # RUN ODIN II + &run_odin2($odin2_config, $odin2_carry_chain_support, $odin2_log); + + if (!(-e $abc_bm)) { + die "ERROR: Fail ODIN II for benchmark $benchmark.\n"; + } + + # RUN ABC + &run_abc_mccl_fpgamap($abc_bm,$abc_blif_out_bak,$abc_log); + + `perl pro_blif.pl -i $abc_blif_out_bak -o $abc_blif_out`; + if (!(-e $abc_blif_out_bak)) { + die "ERROR: Fail pro_blif for benchmark $benchmark.\n"; + } + + my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace.blif","$prefix"."ace.log"); + if ("on" eq $opt_ptr->{power}) { + &run_ace($abc_blif_out,$act_file,$ace_new_blif,$ace_log); + $abc_blif_out = $ace_new_blif; + } + + $vpr_net = "$prefix"."vpr.net"; + $vpr_place = "$prefix"."vpr.place"; + $vpr_route = "$prefix"."vpr.route"; + $vpr_log = "$prefix"."vpr.log"; + $vpr_reroute_log = "$prefix"."vpr_reroute.log"; + + if ("on" eq $opt_ptr->{min_route_chan_width}) { + &run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,-1,$vpr_log.".min_chan_width",$act_file); + # Get the Minimum channel width + my ($min_chan_width) = (&extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val}, $opt_ptr->{min_route_chan_width}, $parse_results)); + $min_chan_width = int($min_chan_width*$opt_ptr->{min_route_chan_width_val}); + if (0 != $min_chan_width%2) { + $min_chan_width += 1; + } + # Remove previous route results + `rm $vpr_route`; + # Keep increase min_chan_width until route success + # Extract data from VPR stats + while (1) { + &run_vpr_route($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$min_chan_width,$vpr_reroute_log,$act_file); + if (-e $vpr_route) { + print "INFO: try route_chan_width($min_chan_width) Success!\n"; + last; #Jump out + } else { + print "INFO: try route_chan_width($min_chan_width) failed! Retry with +2...\n"; + $min_chan_width += 2; + } + } + # Extract data from VPR stats + if (1 == $parse_results) { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}, "off", $parse_results); + &extract_vpr_stats($tag,$benchmark,$vpr_log."min_chan_width",$opt_ptr->{K_val}); + &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); + } + } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { + my ($fix_chan_width) = ($benchmarks_ptr->{$benchmark_file}->{fix_route_chan_width}); + # Remove previous route results + `rm $vpr_route`; + # Keep increase min_chan_width until route success + &run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$fix_chan_width,$vpr_log,$act_file); + # Extract data from VPR stats + while (1) { + if (-e $vpr_route) { + print "INFO: try route_chan_width($fix_chan_width) Success!\n"; + last; #Jump out + } else { + print "INFO: try route_chan_width($fix_chan_width) failed! Retry with +2...\n"; + $fix_chan_width += 2; + &run_vpr_route($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$fix_chan_width,$vpr_reroute_log,$act_file); + } + } + if (1 == $parse_results) { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}, "off", $parse_results); + &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); + if (-e $vpr_reroute_log) { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}, "off", $parse_results); + &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); + } + } + } else { + &run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,-1,$vpr_log,$act_file); + if (!(-e $vpr_route)) { + die "ERROR: Route Fail for $abc_blif_out!\n"; + } + # Get the Minimum channel width + my ($min_chan_width) = (&extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val},$parse_results)); + if (1 == $parse_results) { + &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); + } + } + + # Extract data from VPR Power stats + if (("on" eq $opt_ptr->{power}) + &&(1 == $parse_results)) { + &extract_vpr_power_esti($tag,$abc_blif_out,$benchmark,$opt_ptr->{K_val}); + } + return; +} + +sub run_mccl_flow($ $ $ $ $) +{ + my ($tag,$benchmark_file,$vpr_arch,$flow_enhance, $parse_results) = @_; + my ($benchmark, $rpt_dir,$prefix); + my ($abc_bm,$abc_blif_out,$abc_log,$abc_blif_out_bak); + my ($mpack_blif_out,$mpack_stats,$mpack_log); + my ($vpr_net,$vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log); + + $benchmark = $benchmark_file; + $benchmark =~ s/\.v$//g; # We use verilog format in mccl + # Run Standard flow + $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; + &generate_path($rpt_dir); + $abc_bm = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".v"; + $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; + $abc_blif_out = "$prefix"."abc.blif"; + $abc_blif_out_bak = "$prefix"."abc_bak.blif"; + $abc_log = "$prefix"."abc.log"; + + # RUN ABC + &run_abc_mccl_fpgamap($abc_bm,$abc_blif_out_bak,$abc_log); + + `perl pro_blif.pl -i $abc_blif_out_bak -o $abc_blif_out`; + + if (!(-e $abc_blif_out)) { + die "ERROR: Fail pro_blif.pl for benchmark $abc_blif_out.\n"; + } + + my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace.blif","$prefix"."ace.log"); + if ("on" eq $opt_ptr->{power}) { + if ("on" eq $opt_ptr->{black_box_ace}) { + &black_box_blif($abc_blif_out,$ace_new_blif); + &run_ace($ace_new_blif,$act_file,$prefix."ace_new.blif",$ace_log); + } else { + &run_ace($abc_blif_out,$act_file,$ace_new_blif,$ace_log); + $abc_blif_out = $ace_new_blif; + } + } + + if (!(-e $act_file)) { + die "ERROR: Fail ACE2 for benchmark $act_file.\n"; + } + + $vpr_net = "$prefix"."vpr.net"; + $vpr_place = "$prefix"."vpr.place"; + $vpr_route = "$prefix"."vpr.route"; + $vpr_log = "$prefix"."vpr.log"; + $vpr_reroute_log = "$prefix"."vpr_reroute.log"; + + if ("on" eq $opt_ptr->{min_route_chan_width}) { + &run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,-1,$vpr_log.".min_chan_width",$act_file); + # Get the Minimum channel width + my ($min_chan_width) = (&extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val}, $opt_ptr->{min_route_chan_width}, $parse_results)); + $min_chan_width = int($min_chan_width*$opt_ptr->{min_route_chan_width_val}); + if (0 != $min_chan_width%2) { + $min_chan_width += 1; + } + # Remove previous route results + if (-e $vpr_route) { + `rm $vpr_route`; + } + # Keep increase min_chan_width until route success + # Extract data from VPR stats + #&run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$min_chan_width,$vpr_log,$act_file); + while (1) { + &run_vpr_route($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$min_chan_width,$vpr_reroute_log,$act_file); + # TODO: Only run the routing stage + if (-e $vpr_route) { + print "INFO: try route_chan_width($min_chan_width) success!\n"; + last; #Jump out + } else { + print "INFO: try route_chan_width($min_chan_width) failed! Retry with +2...\n"; + $min_chan_width += 2; + } + } + if (1 == $parse_results) { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}, "off", $parse_results); + &extract_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val}); + &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); + } + } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { + my ($fix_chan_width) = ($benchmarks_ptr->{$benchmark_file}->{fix_route_chan_width}); + # Remove previous route results + if (-e $vpr_route) { + `rm $vpr_route`; + } + # Keep increase min_chan_width until route success + &run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$fix_chan_width,$vpr_log,$act_file); + while (1) { + # TODO: Only run the routing stage + if (-e $vpr_route) { + print "INFO: try route_chan_width($fix_chan_width) success!\n"; + last; #Jump out + } else { + print "INFO: try route_chan_width($fix_chan_width) failed! Retry with +2...\n"; + $fix_chan_width += 2; + &run_vpr_route($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$fix_chan_width,$vpr_reroute_log,$act_file); + } + } + # Extract data from VPR stats + if (1 == $parse_results) { + &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}, "off", $parse_results); + &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); + if (-e $vpr_reroute_log) { + &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); + } + } + } else { + &run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,-1,$vpr_log,$act_file); + if (!(-e $vpr_route)) { + die "ERROR: Route Fail for $abc_blif_out!\n"; + } + # Get the Minimum channel width + my ($min_chan_width) = (&extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val},"on",$parse_results)); + if (1 == $parse_results) { + &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); + } + } + + # Extract data from VPR Power stats + if (("on" eq $opt_ptr->{power}) + &&(1 == $parse_results)) { + &extract_vpr_power_esti($tag,$abc_blif_out,$benchmark,$opt_ptr->{K_val}); + } + + return; +} + +sub run_benchmark_selected_flow($ $ $) +{ + my ($flow_type,$benchmark, $parse_results) = @_; + + if ($flow_type eq "standard") { + &run_standard_flow("standard",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val},"classic", $parse_results); + } elsif ($flow_type eq "mpack2") { + &run_mpack2_flow("mpack2",$benchmark,$conf_ptr->{flow_conf}->{mpack2_arch}->{val}, $parse_results); + } elsif ($flow_type eq "mpack1") { + &run_mpack1_flow("mpack1",$benchmark, $parse_results); + } elsif ($flow_type eq "vtr_standard") { + &run_standard_flow("vtr_standard",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val},"abc_black_box", $parse_results); + } elsif ($flow_type eq "vtr") { + &run_vtr_flow("vtr",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val}, $parse_results); + } elsif ($flow_type eq "vtr_mccl") { + &run_vtr_mccl_flow("vtr_mccl",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val}, $parse_results); + } elsif ($flow_type eq "mccl") { + &run_mccl_flow("mccl",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val}, $parse_results); + } elsif ($flow_type eq "mig_mccl") { + &run_mig_mccl_flow("mig_mccl",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val}, $parse_results); + } else { + die "ERROR: unsupported flow type ($flow_type) is chosen!\n"; + } + + return; +} + +sub parse_benchmark_selected_flow($ $) { + my ($flow_type,$benchmark) = @_; + + if ($flow_type eq "standard") { + &parse_standard_flow_results("standard",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val},"classic"); + } elsif ($flow_type eq "mpack2") { + &parse_mpack2_flow_results("mpack2",$benchmark,$conf_ptr->{flow_conf}->{mpack2_arch}->{val}); + } elsif ($flow_type eq "mpack1") { + &parse_mpack1_flow_results("mpack1",$benchmark); + } elsif ($flow_type eq "vtr_standard") { + &parse_standard_flow_results("vtr_standard",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val},"abc_black_box"); + } elsif ($flow_type eq "vtr") { + &parse_vtr_flow_results("vtr", $benchmark, $conf_ptr->{flow_conf}->{vpr_arch}->{val}); + } elsif ($flow_type eq "vtr_mccl") { + &parse_vtr_flow_results("vtr_mccl", $benchmark, $conf_ptr->{flow_conf}->{vpr_arch}->{val}); + } elsif ($flow_type eq "mccl") { + &parse_standard_flow_results("mccl", $benchmark, $conf_ptr->{flow_conf}->{vpr_arch}->{val}); + } elsif ($flow_type eq "mig_mccl") { + &parse_standard_flow_results("mig_mccl", $benchmark, $conf_ptr->{flow_conf}->{vpr_arch}->{val}); + } else { + die "ERROR: unsupported flow type ($flow_type) is chosen!\n"; + } +} + +# Run EDA flow +sub run_flows() { + my @flows = split('\|',$conf_ptr->{flow_conf}->{flow_type}->{val}); + # Run Benchmark one by one + foreach my $benchmark(@benchmark_names) { + foreach my $flow_to_run(@flows) { + if (("off" eq $selected_flows{$flow_to_run}->{flow_status}) + ||("done" eq $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status})) { + next; + } + print "FLOW TO RUN: $flow_to_run, Benchmark: $benchmark\n"; + &run_benchmark_selected_flow($flow_to_run,$benchmark, 0); + # Mark finished benchmarks + $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status} = "done"; + } + } + &parse_flows_benchmarks_results(); +} + +# Run EDA flow with multi task support +sub multitask_run_flows() { + my @flows = split('\|',$conf_ptr->{flow_conf}->{flow_type}->{val}); + # Run Benchmark one by one + foreach my $benchmark(@benchmark_names) { + foreach my $flow_to_run(@flows) { + if (("off" eq $selected_flows{$flow_to_run}->{flow_status}) + ||("running" eq $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status}) + ||("done" eq $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status})) { + next; + } + print "FLOW TO RUN: $flow_to_run, Benchmark: $benchmark\n"; + # Mutli thread push + if ("on" eq $opt_ptr->{multi_task}) { + my $pid = fork(); + if (defined $pid) { + if ($pid) { + $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status} = "running"; + &run_benchmark_selected_flow($flow_to_run,$benchmark, 1); + # Mark finished benchmarks + $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status} = "done"; + } else { + exit; + } + } else { + print "INFO: fail to create a thread for "; + print "FLOW TO RUN: $flow_to_run, Benchmark: $benchmark\n"; + print "Relauch later...\n"; + } + } else { + &run_benchmark_selected_flow($flow_to_run,$benchmark, 1); + # Mark finished benchmarks + $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status} = "done"; + } + } + } + + return; +} + +# Run EDA flow with multi thread support +sub multithread_run_flows($) { + my ($num_threads) = @_; + my @flows = split('\|',$conf_ptr->{flow_conf}->{flow_type}->{val}); + # Evaluate include threads ok + my ($can_use_threads) = (eval 'use threads; 1'); + if (!($can_use_threads)) { + die "ERROR: cannot use threads package in Perl! Please check the installation of package...\n"; + } + + # Lauch threads up to the limited number of threads number + if ($num_threads < 2) { + $num_threads = 2; + } + my ($num_thread_running) = (0); + + # Iterate until all the tasks has been assigned, finished + while (1 != &check_all_flows_all_benchmarks_done()) { + foreach my $benchmark(@benchmark_names) { + foreach my $flow_to_run(@flows) { + # Bypass unselected flows or finished job + if (("off" eq $selected_flows{$flow_to_run}->{flow_status}) + ||("done" eq $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status})) { + next; + } + # Check if the thread is still not start, running, or finished. + my ($thr_id) = ($selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{thread_id}); + if ($thr_id) { + # Check if there is any error + if ($thr_id->error()) { + die "Thread(ID:$thr_id) exit abnormally!\n"; + } + # We have a thread id, check running or finished + if ($thr_id->is_running()) { + # Update status + $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status} = "running"; + } + if ($thr_id->is_joinable()) { + $num_thread_running--; + $thr_id->join(); # Join the thread results + # Update status + $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status} = "done"; + print "FLOW: $flow_to_run, Benchmark: $benchmark, Finished!\n"; + print "INFO: current running thread number = $num_thread_running.\n"; + &print_jobs_status(); + } + } else { + # Not start a thread for this task, + if (($num_thread_running == $num_threads) + ||($num_thread_running > $num_threads)) { + next; + } + #if there are still threads available, we try to start one + # Mutli thread push + my $thr_new = threads->create(\&run_benchmark_selected_flow,$flow_to_run,$benchmark, 0); + # We have a valid thread... + if ($thr_new) { + print "INFO: a new thread is lauched!\n"; + print "FLOW RUNNING: $flow_to_run, Benchmark: $benchmark\n"; + # Check if it is running... + if ($thr_new->is_running()) { + $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status} = "running"; + $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{thread_id} = $thr_new; + $num_thread_running++; + print "INFO: current running thread number = $num_thread_running.\n"; + &print_jobs_status(); + } + # Check if it is detached... + if ($thr_new->is_joinable()) { + # Mark finished benchmarks + $num_thread_running--; + $thr_new->join(); # Join the thread results + $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status} = "done"; + print "FLOW: $flow_to_run, Benchmark: $benchmark, Finished!\n"; + print "INFO: current running thread number = $num_thread_running.\n"; + &print_jobs_status(); + } + } else { + # Fail to create a new thread, wait... + print "INFO: Fail to alloc a new thread, wait...!"; + } + } + } + } + } + &print_jobs_status(); + + &parse_flows_benchmarks_results(); + + return; +} + +sub parse_flows_benchmarks_results() { + # Parse all the results + foreach my $benchmark(@benchmark_names) { + foreach my $flow_to_run(@supported_flows) { + # Bypass unselected flows or finished job + if (("on" eq $selected_flows{$flow_to_run}->{flow_status}) + &&("done" eq $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status})) { + &parse_benchmark_selected_flow($flow_to_run, $benchmark); + } + } + } + + return; +} + +sub print_jobs_status() { + my ($num_jobs_running, $num_jobs_to_run, $num_jobs_finish, $num_jobs) = (0, 0, 0, 0); + + foreach my $benchmark(@benchmark_names) { + foreach my $flow_to_run(@supported_flows) { + if ("on" eq $selected_flows{$flow_to_run}->{flow_status}) { + # Count the number of jobs + $num_jobs++; + # Count to do jobs + if ("off" eq $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status}) { + $num_jobs_to_run++; + next; + } + # Count running jobs + if ("running" eq $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status}) { + $num_jobs_running++; + next; + } + # Count finished jobs + if ("done" eq $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status}) { + $num_jobs_finish++; + next; + } + } + } + } + if ($num_jobs == ($num_jobs_running + $num_jobs_finish + $num_jobs_to_run)) { + print "Jobs Progress: (Finish rate = ".sprintf("%.2f",100*$num_jobs_finish/$num_jobs) ."%)\n"; + print "Total No. of Jobs: $num_jobs.\n"; + print "No. of Running Jobs: $num_jobs_running.\n"; + print "No. of Finished Jobs: $num_jobs_finish.\n"; + print "No. of To Run Jobs: $num_jobs_to_run.\n"; + } else { + print "Internal problem: num_jobs($num_jobs) != num_jobs_running($num_jobs_running)\n"; + print " +num_jobs_finish($num_jobs_finish)\n"; + die " +num_jobs_to_run($num_jobs_to_run)\n"; + } + return; +} + +sub check_all_flows_all_benchmarks_done() { + my ($all_done) = (1); + foreach my $flow_to_run(@supported_flows) { + if ("off" eq $selected_flows{$flow_to_run}->{flow_status}) { + next; + } + if (1 != &check_flow_all_benchmarks_done($flow_to_run)) { + $all_done = 0; + last; + } + } + return $all_done; +} + +sub check_flow_all_benchmarks_done($) { + my ($flow_name) = @_; + my ($all_done) = (0); + # If this flow has not been chosen, return 0 + if ("off" eq $selected_flows{$flow_name}->{flow_status}) { + return $all_done; + } elsif ("on" eq $selected_flows{$flow_name}->{flow_status}) { + $all_done = 1; + } + # Check if every benchmark has finished in this flow. + foreach my $bm(@benchmark_names) { + if ("done" ne $selected_flows{$flow_name}->{benchmarks}->{$bm}->{status}) { + $all_done = 0; + last; + } + } + + return $all_done; +} + +sub gen_csv_rpt_vtr_flow($ $) +{ + my ($tag,$CSVFH) = @_; + my ($tmp,$ikw,$tmpkw); + my @keywords; + my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val}); + + # Print out Standard Stats First + print $CSVFH "$tag"; + print $CSVFH ",LUTs"; + if ("on" eq $opt_ptr->{min_route_chan_width}) { + print $CSVFH ",min_route_chan_width"; + print $CSVFH ",fix_route_chan_width"; + } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { + print $CSVFH ",fix_route_chan_width"; + } else { + print $CSVFH ",min_route_chan_width"; + } + @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; + #foreach $tmpkw(@keywords) { + for($ikw=0; $ikw < ($#keywords+1); $ikw++) { + print $CSVFH ",$keywords[$ikw]"; + } + if ("on" eq $opt_ptr->{power}) { + @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; + #foreach $tmpkw(@keywords) { + for($ikw=0; $ikw < ($#keywords+1); $ikw++) { + print $CSVFH ",$keywords[$ikw]"; + } + print $CSVFH ",Total Power,Total Dynamic Power,Total Leakage Power"; + } + print $CSVFH "\n"; + # Check log/stats one by one + foreach $tmp(@benchmark_names) { + $tmp =~ s/\.v$//g; + print $CSVFH "$tmp"; + print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{LUTs}"; + if ("on" eq $opt_ptr->{min_route_chan_width}) { + print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{min_route_chan_width}"; + print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{fix_route_chan_width}"; + } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { + print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{fix_route_chan_width}"; + } else { + print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{min_route_chan_width}"; + } + #foreach $tmpkw(@keywords) { + @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; + for($ikw=0; $ikw < ($#keywords+1); $ikw++) { + $tmpkw = $keywords[$ikw]; + $tmpkw =~ s/\s//g; + print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{$keywords[$ikw]}"; + } + if ("on" eq $opt_ptr->{power}) { + @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; + for($ikw=0; $ikw < ($#keywords+1); $ikw++) { + $tmpkw = $keywords[$ikw]; + $tmpkw =~ s/\s//g; + print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{$keywords[$ikw]}"; + } + print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{total}"; + print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{dynamic}"; + print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{leakage}"; + } + print $CSVFH "\n"; + } +} + +sub gen_csv_rpt_standard_flow($ $) +{ + my ($tag,$CSVFH) = @_; + my ($tmp,$ikw,$tmpkw); + my @keywords; + my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val}); + + # Print out Standard Stats First + print $CSVFH "$tag"; + print $CSVFH ",LUTs"; + if ("on" eq $opt_ptr->{min_route_chan_width}) { + print $CSVFH ",min_route_chan_width"; + print $CSVFH ",fix_route_chan_width"; + } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { + print $CSVFH ",fix_route_chan_width"; + } else { + print $CSVFH ",min_route_chan_width"; + } + @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; + #foreach $tmpkw(@keywords) { + for($ikw=0; $ikw < ($#keywords+1); $ikw++) { + print $CSVFH ",$keywords[$ikw]"; + } + if ("on" eq $opt_ptr->{power}) { + @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; + #foreach $tmpkw(@keywords) { + for($ikw=0; $ikw < ($#keywords+1); $ikw++) { + print $CSVFH ",$keywords[$ikw]"; + } + print $CSVFH ",Total Power,Total Dynamic Power,Total Leakage Power"; + } + print $CSVFH "\n"; + # Check log/stats one by one + foreach $tmp(@benchmark_names) { + $tmp =~ s/\.blif$//g; + print $CSVFH "$tmp"; + print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{LUTs}"; + if ("on" eq $opt_ptr->{min_route_chan_width}) { + print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{min_route_chan_width}"; + print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{fix_route_chan_width}"; + } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { + print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{fix_route_chan_width}"; + } else { + print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{min_route_chan_width}"; + } + #foreach $tmpkw(@keywords) { + @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; + for($ikw=0; $ikw < ($#keywords+1); $ikw++) { + $tmpkw = $keywords[$ikw]; + $tmpkw =~ s/\s//g; + print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{$keywords[$ikw]}"; + } + if ("on" eq $opt_ptr->{power}) { + @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; + for($ikw=0; $ikw < ($#keywords+1); $ikw++) { + $tmpkw = $keywords[$ikw]; + $tmpkw =~ s/\s//g; + print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{$keywords[$ikw]}"; + } + print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{total}"; + print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{dynamic}"; + print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{leakage}"; + } + print $CSVFH "\n"; + } +} + +sub gen_csv_rpt_mpack2_flow($ $) +{ + my ($tag,$CSVFH) = @_; + my ($tmp,$ikw,$tmpkw); + my @keywords; + my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val}); + + # Print out Mpack stats Second + print $CSVFH "$tag"; + if ("on" eq $opt_ptr->{min_route_chan_width}) { + print $CSVFH ",min_route_chan_width"; + print $CSVFH ",fix_route_chan_width"; + } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { + print $CSVFH ",fix_route_chan_width"; + } else { + print $CSVFH ",min_route_chan_width"; + } + + @keywords = split /\|/,$conf_ptr->{csv_tags}->{mpack2_tags}->{val}; + #foreach $tmpkw(@keywords) { + for($ikw=0; $ikw < ($#keywords+1); $ikw++) { + print $CSVFH ",$keywords[$ikw]"; + } + @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; + #foreach $tmpkw(@keywords) { + for($ikw=0; $ikw < ($#keywords+1); $ikw++) { + print $CSVFH ",$keywords[$ikw]"; + } + if ("on" eq $opt_ptr->{power}) { + @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; + #foreach $tmpkw(@keywords) { + for($ikw=0; $ikw < ($#keywords+1); $ikw++) { + print $CSVFH ",$keywords[$ikw]"; + } + print $CSVFH ",Total Power,Total Dynamic Power,Total Leakage Power"; + } + print $CSVFH "\n"; + # Check log/stats one by one + foreach $tmp(@benchmark_names) { + $tmp =~ s/\.blif$//g; + print $CSVFH "$tmp"; + if ("on" eq $opt_ptr->{min_route_chan_width}) { + print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{min_route_chan_width}"; + print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{fix_route_chan_width}"; + } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { + print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{fix_route_chan_width}"; + } else { + print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{min_route_chan_width}"; + } + #foreach $tmpkw(@keywords) { + @keywords = split /\|/,$conf_ptr->{csv_tags}->{mpack2_tags}->{val}; + for($ikw=0; $ikw < ($#keywords+1); $ikw++) { + $tmpkw = $keywords[$ikw]; + $tmpkw =~ s/\s//g; + print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{$keywords[$ikw]}"; + } + @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; + for($ikw=0; $ikw < ($#keywords+1); $ikw++) { + $tmpkw = $keywords[$ikw]; + $tmpkw =~ s/\s//g; + print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{$keywords[$ikw]}"; + } + if ("on" eq $opt_ptr->{power}) { + @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; + for($ikw=0; $ikw < ($#keywords+1); $ikw++) { + $tmpkw = $keywords[$ikw]; + $tmpkw =~ s/\s//g; + print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{$keywords[$ikw]}"; + } + print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{total}"; + print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{dynamic}"; + print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{leakage}"; + } + print $CSVFH "\n"; + } +} + +sub gen_csv_rpt_mpack1_flow($ $) +{ + my ($tag,$CSVFH) = @_; + my ($tmp,$ikw,$tmpkw); + my @keywords; + my ($N_val,$M_val) = ($opt_ptr->{N_val},$opt_ptr->{M_val}); + + # Print out Mpack stats Second + print $CSVFH "$tag"; + print $CSVFH ",MATRIX"; + @keywords = split /\|/,$conf_ptr->{csv_tags}->{mpack_tags}->{val}; + for($ikw=0; $ikw < ($#keywords+1); $ikw++) { + print $CSVFH ",$keywords[$ikw]"; + } + @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; + #foreach $tmpkw(@keywords) { + for($ikw=0; $ikw < ($#keywords+1); $ikw++) { + print $CSVFH ",$keywords[$ikw]"; + } + # Print Power Tags + @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; + #foreach $tmpkw(@keywords) { + for($ikw=0; $ikw < ($#keywords+1); $ikw++) { + print $CSVFH ",$keywords[$ikw]"; + } + print $CSVFH ",Total Power,Total Dynamic Power, Total Leakage Power"; + print $CSVFH "\n"; + # Check log/stats one by one + foreach $tmp(@benchmark_names) { + $tmp =~ s/\.blif$//g; + print $CSVFH "$tmp"; + #foreach $tmpkw(@keywords) { + print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{MATRIX}"; + @keywords = split /\|/,$conf_ptr->{csv_tags}->{mpack_tags}->{val}; + for($ikw=0; $ikw < ($#keywords+1); $ikw++) { + $tmpkw = $keywords[$ikw]; + $tmpkw =~ s/\s//g; + print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{$keywords[$ikw]}"; + } + @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; + for($ikw=0; $ikw < ($#keywords+1); $ikw++) { + $tmpkw = $keywords[$ikw]; + $tmpkw =~ s/\s//g; + print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{$keywords[$ikw]}"; + } + # Print Power Results + @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; + for($ikw=0; $ikw < ($#keywords+1); $ikw++) { + $tmpkw = $keywords[$ikw]; + $tmpkw =~ s/\s//g; + print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{power}->{$keywords[$ikw]}"; + } + print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{power}->{total}"; + print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{power}->{dynamic}"; + print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{power}->{leakage}"; + print $CSVFH "\n"; + } +} + +sub init_selected_flows() { + # For each flow type, mark the status to off + foreach my $flow_type(@supported_flows) { + $selected_flows{$flow_type}->{flow_status} = "off"; + # For each benchmark, init the status to "off" + foreach my $benchmark(@benchmark_names) { + $selected_flows{$flow_type}->{benchmarks}->{$benchmark}->{status} = "off"; + $selected_flows{$flow_type}->{benchmarks}->{$benchmark}->{thread_id} = undef; + } + } +} + +sub mark_selected_flows() +{ + # Mark what flows are selected + my @flows = split('\|',$conf_ptr->{flow_conf}->{flow_type}->{val}); + foreach my $flow_type(@flows) { + if (exists $selected_flows{$flow_type}->{flow_status}) { + $selected_flows{$flow_type}->{flow_status} = "on"; + print "INFO: FLOW TYPE: $flow_type is turned $selected_flows{$flow_type}->{flow_status}\n"; + # Initial FPGA SPICE TASK FILE + if ("on" eq $opt_ptr->{vpr_fpga_spice}) { + &init_fpga_spice_task($opt_ptr->{vpr_fpga_spice_val}."_$flow_type.txt"); + } + } else { + die "ERROR: flow_type: $flow_type is not supported!\n"; + } + } +} + +sub mark_flows_benchmarks() { + foreach my $flow_type(@supported_flows) { + if ("on" eq $selected_flows{$flow_type}->{flow_status}) { + # For each benchmark, init the status to "off" + foreach my $benchmark(@benchmark_names) { + $selected_flows{$flow_type}->{benchmarks}->{$benchmark}->{status} = "done"; + } + } + } +} + +sub gen_csv_rpt($) +{ + my ($csv_file) = @_; + + my ($csv_dir_path, $csv_filename) = &split_prog_path($csv_file); + &generate_path($csv_dir_path); + + # Open a filehandle + my ($CSVFH) = (FileHandle->new); + if ($CSVFH->open("> $csv_file")) { + print "INFO: writing CSV report ($csv_file) ...\n"; + } else { + die "ERROR: fail to create CSV report ($csv_file) ...\n"; + } + + foreach my $flow_type(@supported_flows) { + if ($selected_flows{$flow_type}->{flow_status} eq "on") { + # Print the report only all the benchmarks in this flow finished + if ($flow_type eq "standard") { + if (1 == &check_flow_all_benchmarks_done("standard")) { + print "INFO: writing standard flow results ...\n"; + &gen_csv_rpt_standard_flow("standard",$CSVFH); + } + } elsif ($flow_type eq "mpack2") { + if (1 == &check_flow_all_benchmarks_done("mpack2")) { + print "INFO: writing mpack2 flow results ...\n"; + &gen_csv_rpt_mpack2_flow("mpack2",$CSVFH); + } + } elsif ($flow_type eq "mpack1") { + if (1 == &check_flow_all_benchmarks_done("mpack1")) { + print "INFO: writing mpack1 flow results ...\n"; + &gen_csv_rpt_mpack1_flow("mpack1",$CSVFH); + } + } elsif ($flow_type eq "vtr_standard") { + if (1 == &check_flow_all_benchmarks_done("vtr")) { + print "INFO: writing vtr flow results ...\n"; + &gen_csv_rpt_standard_flow("vtr_standard",$CSVFH); + } + } elsif ($flow_type eq "vtr") { + if (1 == &check_flow_all_benchmarks_done("vtr")) { + print "INFO: writing vtr flow results ...\n"; + &gen_csv_rpt_vtr_flow("vtr",$CSVFH); + } + } elsif ($flow_type eq "vtr_mccl") { + if (1 == &check_flow_all_benchmarks_done("vtr_mccl")) { + print "INFO: writing vtr_mccl flow results ...\n"; + &gen_csv_rpt_standard_flow("vtr_mccl",$CSVFH); + } + } elsif ($flow_type eq "mccl") { + if (1 == &check_flow_all_benchmarks_done("mccl")) { + print "INFO: writing mccl flow results ...\n"; + &gen_csv_rpt_standard_flow("mccl",$CSVFH); + } + } elsif ($flow_type eq "mig_mccl") { + if (1 == &check_flow_all_benchmarks_done("mig_mccl")) { + print "INFO: writing mig_mccl flow results ...\n"; + &gen_csv_rpt_standard_flow("mig_mccl",$CSVFH); + } + } else { + die "ERROR: flow_type: $flow_type is not supported!\n"; + } + } + } + + close($CSVFH); +} + +sub remove_designs() +{ + if ("on" eq $opt_ptr->{remove_designs}) { + `rm -rf $conf_ptr->{dir_path}->{rpt_dir}->{val}`; + } +} + +sub plan_run_flows() { + + if ("on" eq $opt_ptr->{multi_task}) { + &multitask_run_flows(); + } elsif (("on" eq $opt_ptr->{multi_thread}) + &&($opt_ptr->{multi_thread_val} > 1) + &&(0 < $#benchmark_names)) { + &multithread_run_flows($opt_ptr->{multi_thread_val}); + } else { + if ("on" eq $opt_ptr->{multi_thread}) { + print "INFO: multi_thread is selected but only 1 processor can be used or 1 benchmark to run...\n"; + print "INFO: switch to single thread mode.\n"; + } + &run_flows(); + } +} + +# Main Program +sub main() +{ + &opts_read(); + &read_conf(); + &read_benchmarks(); + &init_selected_flows(); + &mark_selected_flows(); + &check_opts(); + if ("on" eq $opt_ptr->{parse_results_only}) { + &mark_flows_benchmarks(); + &parse_flows_benchmarks_results(); + } else { + &remove_designs(); + &plan_run_flows(); + } + &gen_csv_rpt($opt_ptr->{rpt_val}); +} + +&main(); +exit(0); diff --git a/fpga_flow/scripts/m2net.pl b/fpga_flow/scripts/m2net.pl new file mode 100644 index 000000000..469e78ffc --- /dev/null +++ b/fpga_flow/scripts/m2net.pl @@ -0,0 +1,1354 @@ +#!usr/bin/perl -w +# Perl Script to convert MPACK1 netlist for VPR and generate architecture file +# use the strict mode +use strict; +# Use the Shell enviornment +#use Shell; +# Use the time +use Time::gmtime; +# Use switch module +use Switch; +use File::Path; +use Cwd; + +# Date +my $mydate = gmctime(); +# Current Path +my $cwd = getcwd(); + +# Global Variants +# input Option Hash +my %opt_h; +my $opt_ptr = \%opt_h; +# configurate file hash +my %conf_h; +my $conf_ptr = \%conf_h; +# reports has +my %rpt_h; +my $rpt_ptr = \%rpt_h; + +# Matrix informations +my %mclusters; +my ($mclusters_ptr) = (\%mclusters); + +# Configuration file keywords list +# Category for conf file. +# main category : 1st class +my @mctgy; +# sub category : 2nd class +my @sctgy; +# Initialize these categories +@mctgy = ("arch_model", + "arch_device", + "arch_complexblocks", + ); +# refer to the keywords of arch_model +@{$sctgy[0]} = ("matrix_model_name", + "matrix_inport_name", + "matrix_outport_name", + "cell_model_name", + "cell_inport_name", + "cell_outport_name", + ); +# refer to the keywords of arch_device +# Support uni-directional routing architecture and +# single type segment only +@{$sctgy[1]} = ("R_minW_nmos", + "R_minW_pmos", + "ipin_mux_trans_size", + "C_ipin_cblock", + "T_ipin_cblock", + "grid_logic_tile_area", + "mux_R", + "mux_Cin", + "mux_Cout", + "mux_Tdel", + "mux_trans_size", + "mux_buf_size", + "segment_length", + "segment_Rmetal", + "segment_Cmetal", + "local_interconnect_C_wire", + "clock_buffer_size", + "clock_C_wire", + ); +# refer to the keywords of arch_complexblocks +@{$sctgy[2]} = (#"io_capacity", should be automatically optimized as 2*sqrt(N) + "CLB_logic_equivalent", + #"matrix_name", + #"matrix_cell_name", + "matrix_delay", + "cell_delay", + "dff_tsetup", + "dff_tclk2q", + "mux2to1_delay", # Delay of a 2:1 multiplexer, script can estimate N:1 multiplexer + "cell_dynamic_power", + "cell_static_power", + ); + +my ($SiNW_area_ratio) = (1.5); +# ----------Subrountines------------# + +# Print TABs +sub print_tabs($ $) +{ + my ($num_tab,$FILE) = @_; + my ($my_tab) = (" "); + + for (my $i = 0; $i < $num_tab; $i++) { + print $FILE "$my_tab"; + } +} + +# Create paths if it does not exist. +sub generate_path($) +{ + my ($mypath) = @_; + if (!(-e "$mypath")) + { + mkpath "$mypath"; + print "Path($mypath) does not exist...Create it.\n"; + } + return 1; +} + +# Print the usage +sub print_usage() +{ + print "Usage:\n"; + print " perl m2net.pl [-options ]\n"; + print " Mandatory options: \n"; + print " -conf : specify the basic configuration files for m2net\n"; + print " -mpack1_rpt : MPACK1 report file\n"; + print " -mode : select mode\n"; + print " 1. pack_arch : only output XML architecture file for AApack\n"; + print " 2. m2net : output XML architecture file for VPR, convert *.net file for VPR\n"; + print " -N : Number of MCluster inside a CLB\n"; + print " -I : Number of input of a CLB\n"; + #print " -rpt : m2net running log\n"; + print " Mandatory options for -mode pack_arch:\n"; + print " -arch_file_pack : filename of output XML format architecture file for AAPack\n"; + print " Mandatory options for -mode m2net:\n"; + print " -net_file_in : filename of input *.net file from AAPack\n"; + print " -net_file_out : filename of output *.net file for VPR\n"; + print " -arch_file_vpr : filename of output XML format architecture file for VPR\n"; + print " Other Options:\n"; + print " -power : add power estimation information to VPR ARCH XML\n"; + print " -debug : debug mode\n"; + print " -help : print usage\n"; + exit(1); + return 1; +} + +sub spot_option($ $) +{ + my ($start,$target) = @_; + my ($arg_no,$flag) = (-1,"unfound"); + for (my $iarg = $start; $iarg < $#ARGV+1; $iarg++) + { + if ($ARGV[$iarg] eq $target) + { + if ("found" eq $flag) + { + print "Error: Repeated Arguments!(IndexA: $arg_no,IndexB: $iarg)\n"; + &print_usage(); + } + else + { + $flag = "found"; + $arg_no = $iarg; + } + } + } + # return the arg_no if target is found + # or return -1 when target is missing + return $arg_no; +} + +# Specify in the input list, +# 1. Option Name +# 2. Whether Option with value. if yes, choose "on" +# 3. Whether Option is mandatory. If yes, choose "on" +sub read_opt_into_hash($ $ $) +{ + my ($opt_name,$opt_with_val,$mandatory) = @_; + # Check the -$opt_name + my ($opt_fact) = ("-".$opt_name); + my ($cur_arg) = (0); + my ($argfd) = (&spot_option($cur_arg,"$opt_fact")); + if ($opt_with_val eq "on") + { + if (-1 != $argfd) + { + if ($ARGV[$argfd+1] =~ m/^-/) + { + print "The next argument cannot start with '-'!\n"; + print "it implies an option!\n"; + } + else + { + $opt_ptr->{"$opt_name\_val"} = $ARGV[$argfd+1]; + $opt_ptr->{"$opt_name"} = "on"; + } + } + else + { + $opt_ptr->{"$opt_name"} = "off"; + if ($mandatory eq "on") + { + print "Mandatory option: $opt_fact is missing!\n"; + &print_usage(); + } + } + } + else + { + if (-1 != $argfd) + { + $opt_ptr->{"$opt_name"} = "on"; + } + else + { + $opt_ptr->{"$opt_name"} = "off"; + if ($mandatory eq "on") + { + print "Mandatory option: $opt_fact is missing!\n"; + &print_usage(); + } + } + } + return 1; +} + +# Read options +sub opts_read() +{ + # if no arguments detected, print the usage. + if (-1 == $#ARGV) + { + print "Error : No input arguments!\n"; + print "Try: -help for usage.\n"; + exit(1); + } + # Read in the options + my ($cur_arg,$arg_found); + $cur_arg = 0; + print "Analyzing your options...\n"; + # Read the options with internal options + my $argfd; + # Check help fist + $argfd = &spot_option($cur_arg,"-help"); + if (-1 != $argfd) { + print "Help desk:\n"; + &print_usage(); + } + # Then Check the debug with highest priority + $argfd = &spot_option($cur_arg,"-debug"); + if (-1 != $argfd) { + $opt_ptr->{"debug"} = "on"; + } + else { + $opt_ptr->{"debug"} = "off"; + } + + # Read Opt into Hash(opt_ptr) : "opt_name","with_val","mandatory" + + # Check mode first + &read_opt_into_hash("mode","on","on"); + + # Check mandatory options + &read_opt_into_hash("conf","on","on"); # Check -conf + &read_opt_into_hash("mpack1_rpt","on","on"); # Check -mpack1_rpt + &read_opt_into_hash("N","on","on"); # Check -N + &read_opt_into_hash("I","on","on"); # Check -I + #&read_opt_into_hash("rpt","on","on"); # Check -rpt + + # Check mandatory options by mode selected + if ("pack_arch" eq $opt_ptr->{"mode_val"}) { + &read_opt_into_hash("arch_file_pack","on","on"); # Check -arch_file_mpack + } + elsif ("m2net" eq $opt_ptr->{"mode_val"}) { + &read_opt_into_hash("arch_file_vpr","on","on"); # Check -arch_file_vpr + &read_opt_into_hash("net_file_in","on","on"); # Check -net_file_in + &read_opt_into_hash("net_file_out","on","on"); # Check -net_file_out + } + else { + print "Error: unknown mode!\n"; + print "Help desk:\n"; + &print_usage(); + } + &read_opt_into_hash("power","off","off"); # Check -power + + &opts_echo(); + + return 1; +} + +# List the options +sub opts_echo() +{ + print "Echo your options:\n"; + + while(my ($key,$value) = each(%opt_h)) + {print "$key : $value\n";} + + return 1; +} + + +# Read each line and ignore the comments which starts with given arg +# return the valid information of line +sub read_line($ $) +{ + my ($line,$com) = @_; + my @chars; + if (defined($line)) + { + @chars = split/$com/,$line; + if (!($line =~ m/[\w\d]/)) + {$chars[0] = undef;} + if ($line =~ m/^\s*$com/) + {$chars[0] = undef;} + } + else + {$chars[0] = undef;} + if (defined($chars[0])) + { + $chars[0] =~ s/^(\s+)//g; + $chars[0] =~ s/(\s+)$//g; + } + return $chars[0]; +} + +# Check each keywords has been defined in configuration file +sub check_keywords_conf() +{ + for (my $imcg = 0; $imcg<$#mctgy+1; $imcg++) + { + for (my $iscg = 0; $iscg<$#{$sctgy[$imcg]}+1; $iscg++) + { + if (defined($conf_ptr->{$mctgy[$imcg]}->{$sctgy[$imcg]->[$iscg]}->{val})) + { + if ("on" eq $opt_ptr->{debug}) + { + print "Keyword($mctgy[$imcg],$sctgy[$imcg]->[$iscg]) = "; + print "$conf_ptr->{$mctgy[$imcg]}->{$sctgy[$imcg]->[$iscg]}->{val}"; + print "\n"; + } + } + else + {die "Error: Keyword($mctgy[$imcg],$sctgy[$imcg]->[$iscg]) is missing!\n";} + } + } + return 1; +} + +# Read the configuration file +sub read_conf() +{ + # Read in these key words + my ($line,$post_line); + my @equation; + my $cur = "unknown"; + open (CONF, "< $opt_ptr->{conf_val}") or die "Fail to open $opt_ptr->{conf}!\n"; + print "Reading $opt_ptr->{conf_val}..."; + while(defined($line = )) + { + chomp $line; + $post_line = &read_line($line,"#"); + if (defined($post_line)) + { + if ($post_line =~ m/\[(\w+)\]/) + {$cur = $1;} + elsif ("unknown" eq $cur) + { + die "Error: Unknown tags for this line!\n$post_line\n"; + } + else + { + $post_line =~ s/\s//g; + @equation = split /=/,$post_line; + $conf_ptr->{$cur}->{$equation[0]}->{val} = $equation[1]; + } + } + } + # Check these key words + print "complete!\n"; + print "Checking these keywords..."; + &check_keywords_conf(); + print "Successfully\n"; + close(CONF); + return 1; +} + +# Input program path is like "~/program_dir/program_name" +# We split it from the scalar +sub split_prog_path($) +{ + my ($prog_path) = @_; + my @path_elements = split /\//,$prog_path; + my ($prog_dir,$prog_name); + + $prog_name = $path_elements[$#path_elements]; + $prog_dir = $prog_path; + $prog_dir =~ s/$prog_name$//g; + + return ($prog_dir,$prog_name); +} + +# Read MPACK1 Report +# Determine matrix width, matrix height +# Determine matrix internal connections +# Store pack information for each cell +sub read_mpack1_rpt() +{ + # Read in these key words + my ($line,$post_line,$line_no); + my ($layer_line_cnt,$mcluster_line_cnt,$mcluster_cnt); + my ($checking_layer,$checking_mclusters,$expected_layer_line_no,$expected_mcluster_line_no) = (0,0,-1,-1); + my ($x,$y); + my @split_line; + # Define keywords + my ($matrix_width,$matrix_depth,$cell_size,$layer,$layer_matrix,$mcluster,$mcluster_cell,$unconn,$conn,$open_net,$end,$mcluster_num) = ("matrix_width","matrix_depth","cell_size","layer_detailed","X","MCluster","cell","unconn","conn","open","end","mclusters_number"); + + open (MRPT, "< $opt_ptr->{mpack1_rpt_val}") or die "Fail to open mpack1_rpt: $opt_ptr->{mpack1_rpt_val}!\n"; + print "Reading $opt_ptr->{mpack1_rpt_val}..."; + + $line_no = 0; + $mcluster_cnt = 0; + + while(defined($line = )) + { + chomp $line; + $post_line = &read_line($line,"#"); + $line_no = $line_no + 1; + if (defined($post_line)) + { + # Remove all spaces... + $post_line =~ s/\s//g; + # This case should not happen! + if ((1 == $checking_layer)&&(1 == $checking_mclusters)) { + die "Error: checking_layer and checking_mclusters both turn on!\n"; + } + # TODO List: + if ((0 == $checking_layer)&&(0 == $checking_mclusters)) { + # Check Width + if ($post_line =~ m/^$matrix_width/) { + undef @split_line; + @split_line = split /=/,$post_line; + # Double check + if ($matrix_width eq $split_line[0]) { + $mclusters_ptr->{matrix_width} = $split_line[1]; + next; + } + else { + print "Warning:Invalid definition for matrix width at LINE[$line_no]!\n"; + } + } + # Check Depth + if ($post_line =~ m/^$matrix_depth/) { + undef @split_line; + @split_line = split /=/,$post_line; + # Double check + if ($matrix_depth eq $split_line[0]) { + $mclusters_ptr->{matrix_depth} = $split_line[1]; + next; + } + else { + print "Warning:Invalid definition for matrix depth at LINE[$line_no]!\n"; + } + } + # Check cell_size + if ($post_line =~ m/^$cell_size/) { + undef @split_line; + @split_line = split /=/,$post_line; + # Double check + if ($cell_size eq $split_line[0]) { + $mclusters_ptr->{cell_size} = $split_line[1]; + next; + } + else { + print "Warning:Invalid definition for cell size at LINE[$line_no]!\n"; + } + } + # Check defined MCluster Number + if ($post_line =~ m/^$mcluster_num/) { + undef @split_line; + @split_line = split /=/,$post_line; + # Double check + if ($mcluster_num eq $split_line[0]) { + $mclusters_ptr->{MCluster_num} = $split_line[1]; + next; + } + else { + print "Warning:Invalid definition for $mcluster_num at LINE[$line_no]!\n"; + } + } + # Check layer + # TODO: We should check layer should only defined ONCE!!! + if ($post_line =~ m/^$layer/) { + $checking_layer = 1; + # Clear Counter + $layer_line_cnt = 0; + # Check valid expected_layer_line_no + $expected_layer_line_no = $mclusters_ptr->{matrix_width}*($mclusters_ptr->{matrix_depth}-1)*$mclusters_ptr->{cell_size}; + if (($expected_layer_line_no < 1)&&(1 != $mclusters_ptr->{matrix_width}*$mclusters_ptr->{matrix_depth})) { + die "Error: Invalid expected_layer_line_no($expected_layer_line_no)!\nProbably caused by missing definition of $matrix_width, $matrix_depth, $cell_size before defining $layer...\n"; + } + next; + } + # Check MClusters + if ($post_line =~ m/^$mcluster/) { + $checking_mclusters = 1; + # Clear Counter + $mcluster_line_cnt = 0; + # Check valid expected_mcluster_line_no + $expected_mcluster_line_no = $mclusters_ptr->{matrix_width}*$mclusters_ptr->{matrix_depth}; + if ($expected_mcluster_line_no < 1) { + die "Error: Invalid expected_mcluster_line_no($expected_mcluster_line_no)!\nProbably caused by missing definition of $matrix_width, $matrix_depth, $cell_size before defining $mcluster...\n"; + } + next; + } + } + + # Layer FSM + if (1 == $checking_layer) { + # Check expected_layer_line_no + if ($expected_layer_line_no < $layer_line_cnt) { + die "Error: expected_layer_line_no($expected_layer_line_no) unmatch layer_line_cnt($layer_line_cnt)! Missing information for layer definition!\n"; + } + if ($post_line =~ m/^$end/) { + $checking_layer = 0; + # Check expected_layer_line_no + if ($expected_layer_line_no != $layer_line_cnt) { + die "Error: expected_layer_line_no($expected_layer_line_no) unmatch layer_line_cnt($layer_line_cnt)! Missing information for layer definition!\n"; + } + next; + } + if ($post_line =~ m/^$layer_matrix/) { + undef @split_line; + my ($pin) = ("I"); + #@split_line = split /=/,$post_line; + # Get layer x,y, and double check + if ($post_line =~ m/^$layer_matrix\[(\d+)\]\.$pin\[(\d+)\]=(\d+)/) { + # Record des_idx, pin_idx, src_idx + my ($des_idx,$pin_idx,$src_idx) = ($1,$2,$3); + # Record X and Y + my ($des_y,$des_x) = (($des_idx)%($mclusters_ptr->{matrix_width}),int($des_idx/$mclusters_ptr->{matrix_width})); + my ($src_y,$src_x) = (($src_idx)%($mclusters_ptr->{matrix_width}),int($src_idx/$mclusters_ptr->{matrix_width})); + # Check X range. Should be 0 < X < matrix_depth + if (0 == $des_x) { + print "Warning: there is no need to define zero layer at LINE[$line_no]!\n"; + next; + } + if ((0 > $des_x)||($des_x > ($mclusters_ptr->{matrix_depth}-1))) { + die "Error: Invalid des_x($des_x) in LINE[$line_no]!\n"; + } + # Check Y range. Should be 0 <= Y < matrix_width + if ((0 > $des_y)||($des_y > ($mclusters_ptr->{matrix_width}-1))) { + die "Error: Invalid des_y($des_y) in LINE[$line_no]!\n"; + } + # Check X range. Should be 0 < X < matrix_depth + if ((0 > $src_x)||($src_x > ($mclusters_ptr->{matrix_depth}-1))) { + die "Error: Invalid src_x($src_x) in LINE[$line_no]!\n"; + } + # Check Y range. Should be 0 <= Y < matrix_width + if ((0 > $src_y)||($src_y > ($mclusters_ptr->{matrix_width}-1))) { + die "Error: Invalid src_y($src_y) in LINE[$line_no]!\n"; + } + $mclusters_ptr->{"arch"}->{"cell[$des_x][$des_y]"}->{"I[$pin_idx]"} = $src_y; + # Check matrix content, chomp the last "," and length should be matrix_width + #$split_line[1] =~ s/,$//; # Chomp last "," + #my @tmp = split /,/,$split_line[1]; + #if ($#tmp != ($mclusters_ptr->{matrix_width}-1)) { + # die "Error: Invalid length of cross-connectivity matrix!\n"; + #} + #my $j = 0; + #for (my $i=0; $i<$mclusters_ptr->{matrix_width}; $i++) { + # Valid $tmp[$i] is either 0 or 1 + # if ((0 != $tmp[$i])&&(1 != $tmp[$i])) { + # die "Error: Invalid value of cross-connectivity matrix at LINE[$line_no]!\n"; + # } + # if (1 == $tmp[$i]) { + # $mclusters_ptr->{"arch"}->{"cell[$x][$y]"}->{"I[$j]"} = $i; + # $j = $j + 1; + # } + #} + # Check $j (number of input) + #if ($j != $mclusters_ptr->{cell_size}) { + # die "Error: cross-connectivity matrix exceeds cell_size at LINE[$line_no]!\n"; + #} + + $layer_line_cnt = $layer_line_cnt + 1; + } + else { + print "Warning: Invalid definition of $layer_matrix in $layer at LINE($line_no)!\n"; + } + } + next; + } + + # Mcluster FSM + if (1 == $checking_mclusters) { + # Check expected_mcluster_line_no + if ($expected_mcluster_line_no < $mcluster_line_cnt) { + die "Error: expected_mcluster_line_no($expected_mcluster_line_no) unmatch mcluster_line_cnt($mcluster_line_cnt)! Missing information for MCluster definition!\n"; + } + if ($post_line =~ m/^$end/) { + $checking_mclusters = 0; + # Check expected_mcluster_line_no + if ($expected_mcluster_line_no != $mcluster_line_cnt) { + die "Error: expected_mcluster_line_no($expected_mcluster_line_no) unmatch mcluster_line_cnt($mcluster_line_cnt)! Missing information for MCluster definition!\n"; + } + # Incremental Mcluster counter + $mcluster_cnt = $mcluster_cnt + 1; + next; + } + if ($post_line =~ m/^$mcluster_cell/) { + undef @split_line; + @split_line = split /=/,$post_line; + # Get layer x,y, and double check + if ($split_line[0] =~ m/^$mcluster_cell\[(\d+)\]\[(\d+)\]/) { + # Record X and Y + ($x,$y) = ($1,$2); + # Check X range. Should be 0 <= X < matrix_depth + if ((0 > $x)||($x > ($mclusters_ptr->{matrix_depth}-1))) { + die "Error: Invalid x($x) in LINE[$line_no]!\n"; + } + # Check Y range. Should be 0 <= Y < matrix_width + if ((0 > $y)||($y > ($mclusters_ptr->{matrix_width}-1))) { + die "Error: Invalid y($y) in LINE[$line_no]!\n"; + } + # Check matrix content, chomp the last "," and length should be matrix_width + $split_line[1] =~ s/,$//; # Chomp last "," + my @tmp = split /,/,$split_line[1]; + if ($#tmp != ($mclusters_ptr->{cell_size})) { + die "Error: Invalid length of MCluster cell definition at LINE[$line_no]!\n"; + } + for (my $i=0; $i<$mclusters_ptr->{cell_size}; $i++) { + # Valid $tmp[$i] is either $unconn or $conn + if (($unconn ne $tmp[$i])&&($conn ne $tmp[$i])) { + die "Error: Invalid value of MCluster cell definition at LINE[$line_no]!\n"; + } + $mclusters_ptr->{"MCluster$mcluster_cnt"}->{"cell[$x][$y]"}->{"I[$i]"} = $tmp[$i]; + } + $mclusters_ptr->{"MCluster$mcluster_cnt"}->{"cell[$x][$y]"}->{"net"} = $tmp[$mclusters_ptr->{cell_size}]; + + $mcluster_line_cnt = $mcluster_line_cnt + 1; + } + else { + print "Warning: Invalid definition of $mcluster_cell in $mcluster at LINE($line_no)!\n"; + } + } + next; + } + } + } + print "complete!\n"; + + # Check mcluster_number match + if ($mcluster_cnt != $mclusters_ptr->{MCluster_num}) { + die "Error: Mismatch!(Expect $mclusters_ptr->{MCluster_num} MClusters, Actual $mcluster_cnt)\n"; + } + + close(MRPT); + + # Update Number of MClusters + #$mclusters_ptr->{MCluster_num} = $mcluster_cnt; + + print "Number of MCluster: $mclusters_ptr->{MCluster_num}\n"; + + return 1; +} + +# Print models for AApack Architecture +sub gen_arch_models_pack() +{ + my ($minput_num,$moutput_num) = ($mclusters_ptr->{cell_size}*$mclusters_ptr->{matrix_width},$mclusters_ptr->{matrix_width}); + + print FARCH " \n"; + print FARCH " {arch_model}->{matrix_model_name}->{val}\">\n"; + print FARCH " \n"; + print FARCH " {arch_model}->{matrix_inport_name}->{val}\"/>\n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " {arch_model}->{matrix_outport_name}->{val}\"/>\n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; +} + +sub gen_arch_device() +{ + my ($power_buf_size,$power_mux_trans_size); + ($power_buf_size) = ($conf_ptr->{arch_device}->{mux_buf_size}->{val}/$SiNW_area_ratio); + ($power_mux_trans_size) = ($conf_ptr->{arch_device}->{mux_trans_size}->{val}/$SiNW_area_ratio); + + print FARCH " \n"; + print FARCH " \n"; + print FARCH " {arch_device}->{R_minW_nmos}->{val}\" R_minW_pmos=\"$conf_ptr->{arch_device}->{R_minW_pmos}->{val}\" ipin_mux_trans_size=\"$conf_ptr->{arch_device}->{ipin_mux_trans_size}->{val}\"/>\n"; + print FARCH " {arch_device}->{C_ipin_cblock}->{val}\" T_ipin_cblock=\"$conf_ptr->{arch_device}->{T_ipin_cblock}->{val}\"/>\n"; + print FARCH " {arch_device}->{grid_logic_tile_area}->{val}\"/>\n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " {arch_device}->{mux_R}->{val}\" Cin=\"$conf_ptr->{arch_device}->{mux_Cin}->{val}\" Cout=\"$conf_ptr->{arch_device}->{mux_Cout}->{val}\" Tdel=\"$conf_ptr->{arch_device}->{mux_Tdel}->{val}\" mux_trans_size=\"$conf_ptr->{arch_device}->{mux_trans_size}->{val}\" buf_size=\"$conf_ptr->{arch_device}->{mux_buf_size}->{val}\" power_buf_size=\"$power_buf_size\"/>\n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " {arch_device}->{segment_length}->{val}\" type=\"unidir\" Rmetal=\"$conf_ptr->{arch_device}->{segment_Rmetal}->{val}\" Cmetal=\"$conf_ptr->{arch_device}->{segment_Cmetal}->{val}\">\n"; + print FARCH " \n"; + print FARCH " "; + + for (my $i=0; $i<($conf_ptr->{arch_device}->{segment_length}->{val}+1); $i++) { + print FARCH "1 "; + } + + print FARCH "\n"; + + print FARCH " "; + + for (my $i=0; $i<$conf_ptr->{arch_device}->{segment_length}->{val}; $i++) { + print FARCH "1 "; + } + + print FARCH "\n"; + print FARCH " \n"; + print FARCH " \n"; + +} + +sub gen_arch_complexblocks_io() +{ + my ($io_optimal) = int(2*sqrt($opt_ptr->{N_val}*$mclusters_ptr->{matrix_width})+0.5); + + # Print I/O pad first(Constraint of VPR 7) + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " io.outpad io.inpad io.clock\n"; + print FARCH " io.outpad io.inpad io.clock\n"; + print FARCH " io.outpad io.inpad io.clock\n"; + print FARCH " io.outpad io.inpad io.clock\n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + if ("on" eq $opt_ptr->{power}) { + print FARCH " \n"; + } + print FARCH " \n"; + # I/O pad print over + + + print FARCH "\n"; +} + +sub gen_arch_complexblocks_dffs() +{ + # Print DFFs + print FARCH " {matrix_width}\" class=\"flipflop\">\n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " {arch_complexblocks}->{dff_tsetup}->{val}\" port=\"ff.D\" clock=\"clk\"/>\n"; + print FARCH " {arch_complexblocks}->{dff_tclk2q}->{val}\" port=\"ff.Q\" clock=\"clk\"/>\n"; + print FARCH " \n"; + + print FARCH "\n"; +} + +# Print Complex Block for Matrix Marco +sub gen_arch_complexblocks_matrix_marco() +{ + my ($mcluster_input_num,$mcluster_output_num); + $mcluster_input_num = $mclusters_ptr->{matrix_width}*$mclusters_ptr->{cell_size}; + $mcluster_output_num = $mclusters_ptr->{matrix_width}; + + # Print Matrix Marco Pb_type + print FARCH " {arch_model}->{matrix_model_name}->{val}\" num_pb=\"1\">\n"; + print FARCH " {arch_model}->{matrix_inport_name}->{val}\" num_pins=\"$mcluster_input_num\"/>\n"; + print FARCH " {arch_model}->{matrix_outport_name}->{val}\" num_pins=\"$mcluster_output_num\"/>\n"; + print FARCH " {arch_model}->{matrix_inport_name}->{val}\" out_port=\"matrix.$conf_ptr->{arch_model}->{matrix_outport_name}->{val}\">\n"; + + for (my $i=0; $i<$mcluster_input_num; $i++) { + print FARCH " "; + for (my $j=0; $j<$mcluster_output_num; $j++) { + print FARCH "$conf_ptr->{arch_complexblocks}->{matrix_delay}->{val} "; + } + print FARCH "\n"; + } + + print FARCH " \n"; + print FARCH " \n"; + +} + +# Print Complex Blocks for CLB, only for AAPack +sub gen_arch_complexblocks_clb_pack() +{ + my ($clb_input_num,$clb_output_num); + my ($mcluster_input_num,$mcluster_output_num); + + $mcluster_input_num = $mclusters_ptr->{matrix_width}*$mclusters_ptr->{cell_size}; + $mcluster_output_num = $mclusters_ptr->{matrix_width}; + $clb_input_num = $opt_ptr->{I_val}; + $clb_output_num = $opt_ptr->{N_val}*$mclusters_ptr->{matrix_width}; + + # Print CLB general information + print FARCH " \n"; + print FARCH " {arch_complexblocks}->{CLB_logic_equivalent}->{val}\"/>\n"; + print FARCH " \n"; + print FARCH " \n"; + + # Print Sub Complex Block "BLE" + print FARCH " {N_val}\">\n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + + &gen_arch_complexblocks_matrix_marco(); + + &gen_arch_complexblocks_dffs(); + + # Print interconnections for BLE + my ($ff_idx) = ($mcluster_output_num-1); + print FARCH " \n"; + # Clock + print FARCH " \n"; + print FARCH " {arch_model}->{matrix_inport_name}->{val}\"/>\n"; + print FARCH " {arch_model}->{matrix_outport_name}->{val}\" output=\"ff[$ff_idx:0].D\"/>\n"; + + for (my $i=0; $i<$mclusters_ptr->{matrix_width}; $i++) { + print FARCH " {arch_model}->{matrix_outport_name}->{val}\[$i\]\" output=\"mble.O\[$i\]\">\n"; + print FARCH " {arch_complexblocks}->{mux2to1_delay}->{val}\" in_port=\"ff[$i].Q matrix.$conf_ptr->{arch_model}->{matrix_outport_name}->{val}\[$i\]\" out_port=\"mble.O\[$i\]\"/>\n"; + print FARCH " \n"; + } + + print FARCH " \n"; + print FARCH " \n"; + + # Print interconnection for CLB + my ($crossbar_delay) = ($conf_ptr->{arch_complexblocks}->{mux2to1_delay}->{val}*int(log($clb_input_num+$opt_ptr->{N_val}*$mcluster_output_num-1)/log(2)+1)); + my ($mble_idx) = ($opt_ptr->{N_val}-1); + print FARCH " \n"; + # Crossbar + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + # Clock + print FARCH " \n"; + print FARCH " \n"; + + print FARCH " \n"; + + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + + print FARCH "\n"; +} + +# Print Complex Blocks for AAPack usage +sub gen_arch_complexblocks_pack() +{ + print FARCH " \n"; + + # Print I/O pad first + &gen_arch_complexblocks_io(); + + # Print Matrix-based Pb_type + &gen_arch_complexblocks_clb_pack(); + print FARCH " \n"; +} + +sub gen_arch_pack() +{ + my ($line,$post_line,$line_no); + + print "Generating Architecture XML($opt_ptr->{arch_file_pack_val}) for AAPack..."; + + open (FARCH, "> $opt_ptr->{arch_file_pack_val}") or die "Fail to open arch_pack: $opt_ptr->{arch_file_pack_val}!\n"; + + print FARCH "\n"; + print FARCH "\n"; + print FARCH "\n"; + print FARCH "\n"; + print FARCH "\n"; + print FARCH "\n"; + print FARCH "\n"; + print FARCH "\n"; + print FARCH "\n"; + print FARCH "\n"; + print FARCH "\n"; + + # Write + &gen_arch_models_pack(); + + # Write + &gen_arch_device(); + + # Write + &gen_arch_complexblocks_pack(); + + print FARCH "\n"; + + close(FARCH); + + print "Complete.\n"; +} + +# Print models for VPR Architecture +sub gen_arch_models_vpr() +{ + my ($minput_num,$moutput_num) = ($mclusters_ptr->{cell_size},1); + + print FARCH " \n"; + print FARCH " {arch_model}->{cell_model_name}->{val}\">\n"; + print FARCH " \n"; + print FARCH " {arch_model}->{cell_inport_name}->{val}\"/>\n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " {arch_model}->{cell_outport_name}->{val}\"/>\n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; +} + +# Print Complex Block for Matrix Cells +sub gen_arch_complexblocks_matrix_cells() +{ + my ($num_cell) = ($mclusters_ptr->{matrix_width}*$mclusters_ptr->{matrix_depth}); + # Print Matrix Cell Pb_type + print FARCH " {arch_model}->{cell_model_name}->{val}\" num_pb=\"$num_cell\">\n"; + print FARCH " {arch_model}->{cell_inport_name}->{val}\" num_pins=\"$mclusters_ptr->{cell_size}\"/>\n"; + print FARCH " {arch_model}->{cell_outport_name}->{val}\" num_pins=\"1\"/>\n"; + print FARCH " {arch_model}->{cell_inport_name}->{val}\" out_port=\"cell.$conf_ptr->{arch_model}->{cell_outport_name}->{val}\">\n"; + + for (my $i=0; $i<$mclusters_ptr->{cell_size}; $i++) { + print FARCH " "; + print FARCH "$conf_ptr->{arch_complexblocks}->{cell_delay}->{val} "; + print FARCH "\n"; + } + + print FARCH " \n"; + if ("on" eq $opt_ptr->{power}) { + print FARCH " \n"; + print FARCH " {arch_complexblocks}->{cell_dynamic_power}->{val}\"/>\n"; + print FARCH " {arch_complexblocks}->{cell_static_power}->{val}\"/>\n"; + print FARCH " \n"; + } + print FARCH " \n"; + +} + +# Print Complex Blocks for CLB, only for VPR +sub gen_arch_complexblocks_clb_vpr() +{ + my ($clb_input_num,$clb_output_num); + my ($mcluster_input_num,$mcluster_output_num); + + $mcluster_input_num = $mclusters_ptr->{matrix_width}*$mclusters_ptr->{cell_size}; + $mcluster_output_num = $mclusters_ptr->{matrix_width}; + $clb_input_num = $opt_ptr->{I_val}; + $clb_output_num = $opt_ptr->{N_val}*$mclusters_ptr->{matrix_width}; + + # Print CLB general information + print FARCH " \n"; + print FARCH " {arch_complexblocks}->{CLB_logic_equivalent}->{val}\"/>\n"; + print FARCH " \n"; + print FARCH " \n"; + + # Print Sub Complex Block "BLE" + print FARCH " {N_val}\">\n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " {arch_model}->{matrix_inport_name}->{val}\" num_pins=\"$mcluster_input_num\"/>\n"; + print FARCH " {arch_model}->{matrix_outport_name}->{val}\" num_pins=\"$mcluster_output_num\"/>\n"; + + &gen_arch_complexblocks_matrix_cells(); + + print FARCH " \n"; + # Print Interconnection Scheme(Internal Matrix), cell[$i][$j], $i->row $j->column + for (my $i=0; $i<$mclusters_ptr->{matrix_depth}; $i++) { + for (my $j=0; $j<$mclusters_ptr->{matrix_width}; $j++) { + my ($cell_num) = ($i*$mclusters_ptr->{matrix_width} + $j); + for (my $k=0; $k<$mclusters_ptr->{cell_size}; $k++) { + if (0 == $i) { + my ($input_idx) = ($j*$mclusters_ptr->{cell_size}+$k); + print FARCH " {arch_model}->{matrix_inport_name}->{val}\[$input_idx\]\" output=\"cell[$cell_num].$conf_ptr->{arch_model}->{cell_inport_name}->{val}\[$k\]\"/>\n"; + } + else { + my ($pred_idx) = ($mclusters_ptr->{"arch"}->{"cell[$i][$j]"}->{"I[$k]"}+($i-1)*$mclusters_ptr->{matrix_width}); + print FARCH " {arch_model}->{cell_outport_name}->{val}\" output=\"cell[$cell_num].$conf_ptr->{arch_model}->{cell_inport_name}->{val}\[$k\]\"/>\n"; + } + } + } + } + # Print Output direct interconnections, cells.O -> matrix.O + for (my $j=0; $j<$mclusters_ptr->{matrix_width}; $j++) { + my ($last_layer) = ($mclusters_ptr->{matrix_depth}-1); + my ($pred_idx) = ($mclusters_ptr->{matrix_width}*$last_layer + $j); + print FARCH " {arch_model}->{cell_outport_name}->{val}\" output=\"matrix.$conf_ptr->{arch_model}->{matrix_outport_name}->{val}\[$j\]\"/>\n"; + } + + print FARCH " \n"; + print FARCH " \n"; + + &gen_arch_complexblocks_dffs(); + + # Print interconnections for BLE + my ($ff_idx) = ($mcluster_output_num-1); + print FARCH " \n"; + # Clock + print FARCH " \n"; + print FARCH " {arch_model}->{matrix_inport_name}->{val}\"/>\n"; + print FARCH " {arch_model}->{matrix_outport_name}->{val}\" output=\"ff[$ff_idx:0].D\"/>\n"; + + # Print MUX for DFFs + for (my $i=0; $i<$mclusters_ptr->{matrix_width}; $i++) { + my ($cur_cell_idx) = ($i+$mclusters_ptr->{matrix_width}*($mclusters_ptr->{matrix_depth}-1)); + print FARCH " \n"; + print FARCH " {arch_complexblocks}->{mux2to1_delay}->{val}\" in_port=\"ff[$i].Q matrix.O[$i]\" out_port=\"mble.O[$i]\"/>\n"; + print FARCH " \n"; + } + + print FARCH " \n"; + print FARCH " \n"; + + # Print interconnection for CLB + my ($crossbar_delay) = ($conf_ptr->{arch_complexblocks}->{mux2to1_delay}->{val}*int(log($clb_input_num+$opt_ptr->{N_val}*$mcluster_output_num-1)/log(2)+1)); + my ($mble_idx) = ($opt_ptr->{N_val}-1); + print FARCH " \n"; + # Crossbar + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + # Clock + print FARCH " \n"; + print FARCH " \n"; + + print FARCH " \n"; + + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + #print FARCH " \n"; + #print FARCH " \n"; + print FARCH " \n"; + + print FARCH "\n"; +} + +# Print Complex Blocks for VPR usage +sub gen_arch_complexblocks_vpr() +{ + print FARCH " \n"; + + # Print I/O pad first + &gen_arch_complexblocks_io(); + + # Print Matrix-based Pb_type + &gen_arch_complexblocks_clb_vpr(); + print FARCH " \n"; +} + +sub gen_arch_vpr() +{ + my ($line,$post_line,$line_no); + + print "Generating Architecture XML($opt_ptr->{arch_file_vpr_val}) for VPR 7..."; + + open (FARCH, "> $opt_ptr->{arch_file_vpr_val}") or die "Fail to open arch_vpr: $opt_ptr->{arch_file_vpr_val}!\n"; + + print FARCH "\n"; + print FARCH "\n"; + print FARCH "\n"; + print FARCH "\n"; + print FARCH "\n"; + print FARCH "\n"; + print FARCH "\n"; + print FARCH "\n"; + print FARCH "\n"; + print FARCH "\n"; + print FARCH "\n"; + + # Write + &gen_arch_models_vpr(); + + # Write + &gen_arch_device(); + + # Write + &gen_arch_complexblocks_vpr(); + + if ("on" eq $opt_ptr->{power}) { + my ($power_buf_size,$power_mux_trans_size); + ($power_buf_size) = ($conf_ptr->{arch_device}->{mux_buf_size}->{val}/$SiNW_area_ratio); + ($power_mux_trans_size) = ($conf_ptr->{arch_device}->{mux_trans_size}->{val}/$SiNW_area_ratio); + print FARCH " \n"; + print FARCH " {arch_device}->{local_interconnect_C_wire}->{val}\"/>\n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " \n"; + print FARCH " {arch_device}->{clock_buffer_size}->{val}\" C_wire=\"$conf_ptr->{arch_device}->{clock_C_wire}->{val}\"/>\n"; + print FARCH " \n"; + } + + print FARCH "\n"; + + close(FARCH); + + print "Complete\n"; +} + +sub gen_net_vpr() +{ + my ($mytab) = (" "); + my %net_map; + my ($net_map_ptr) = (\%net_map); + my ($line); + my ($state,$next_state,$mcluster_index) = ("ST_NORMAL","ST_NORMAL",-1); + my ($nets); + + print "Building Hash mapping nets names to MCluster Index...\n"; + + # 1. Build a hash map net names to MCluster index + for (my $i=0; $i<$mclusters_ptr->{MCluster_num}; $i++) { + my (@net_names); + for (my $j=0; $j<$mclusters_ptr->{matrix_width}; $j++) { + my ($last_layer) = ($mclusters_ptr->{matrix_depth}-1); + $net_names[$j] = $mclusters_ptr->{"MCluster$i"}->{"cell[$last_layer][$j]"}->{net}; + } + my ($nets) = join($mytab,@net_names); + + $nets = $nets.$mytab; + #print "DEBUG: NETs($nets)\n"; + $net_map_ptr->{"$nets"}->{"Mcluster_index"} = $i; + } + + print "Generating Net_file_VPR ($opt_ptr->{net_file_out_val}) from Net_file_AAPACK ($opt_ptr->{net_file_in_val})..."; + # 2. Replace Part of *.net format file + # Open net_file_in, read-only + open (FNETI, "< $opt_ptr->{net_file_in_val}") or die "Fail to open input *net formate file: $opt_ptr->{net_file_in_val}!\n"; + # Open net_file_out, write-only + open (FNETO, "> $opt_ptr->{net_file_out_val}") or die "Fail to open output *net formate file: $opt_ptr->{net_file_out_val}!\n"; + + # Copy & Paste from FNETI to FNETO + $state = "ST_NORMAL"; + while (defined($line = )) { + chomp $line; + # States : ST_NORMAL, ST_SKIP_INPUTS, ST_MODIFY_OUTPUTS, ST_SKIP_CLOCK + # ST_NORAML: Try to match instance = "matrix" + # ST_SKIP_INPUTS: We got matched "matrix", skip the + # ST_MODIFT_OUTPUTS: We got matched "matrix and skip the , modify + # ST_SKIP_CLOCK: We got matched matrix, skip and modify , skip and add subblocks + if ("ST_NORMAL" eq $state) { + # Regular expression to match block name="" instance="" + if ($line =~ m/block(\s+)name(\s*)=(\s*)\"([\w\d\[\]\_\-\&\^\;]+)\"(\s+)instance(\s*)=(\s*)\"([\w\d\[\]\_\-\&\^\;]+)\"/) { + my ($name,$instance) = ($4,$8); + # Change state only when name != open + # Replace the outputs of instance = matrix + if (("open" ne $name)&&($instance =~ m/matrix/)) { + # Inside a matrix, skip inputs, switch to state = ST_SKIP_INPUTS + print FNETO " "; + print FNETO "\n"; + $next_state = "ST_SKIP_INPUTS"; + next; + } + } + print FNETO "$line\n"; + } + elsif ("ST_SKIP_INPUTS" eq $state) { + # Match , DEBUG + if (($line =~ m/\/)&&("on" eq $opt_ptr->{debug})) { + print "DEBUG: Match \n"; + } + # Match + if ($line =~ m/\<\/inputs\>/) { + $next_state = "ST_MODIFY_OUTPUTS"; + $mcluster_index = -1; + } + print FNETO "$line\n"; + } + elsif ("ST_MODIFY_OUTPUTS" eq $state) { + my ($line_copy) = ($line); + # Determine the index of MCluster by comparing net_names! + # Match net_names + if ($line_copy =~ m/{arch_model}->{matrix_outport_name}->{val}\">([\d\w\_\s\-\^\&\;\[\]]+)<\/port>/) { + ($nets) = ($4); + } + $line_copy = $line; + # Match and print modified outputs + if ($line_copy =~ m/\<\/outputs\>/) { + my ($format_nets); + $next_state = "ST_SKIP_CLOCK"; + # Check Valid MCluster_index + my @net_names = split /\s+/,$nets; + for (my $i = 0; $i < ($#net_names+1); $i++) { + $format_nets = $format_nets."$net_names[$i]$mytab"; + } + if (exists($net_map_ptr->{"$format_nets"}->{"Mcluster_index"})) { + $mcluster_index = $net_map_ptr->{"$format_nets"}->{"Mcluster_index"}; + } + else { + die "Error: Invalid Net names($format_nets)\n"; + } + + print FNETO " "; + print FNETO "\n"; + my ($last_layer) = ($mclusters_ptr->{matrix_depth}-1); + print FNETO " "; + for (my $i = 0; $i < $mclusters_ptr->{matrix_width}; $i++) { + my ($pred_idx) = ($mclusters_ptr->{matrix_width}*$last_layer + $i); + print FNETO "cell[$pred_idx].$conf_ptr->{arch_model}->{cell_outport_name}->{val}\-\>matrix_output[$i] "; + } + print FNETO "\n"; + print FNETO " "; + print FNETO "\n"; + print FNETO " "; + print FNETO "\n"; + print FNETO " "; + print FNETO "\n"; + } + } + elsif ("ST_SKIP_CLOCK" eq $state) { + # Match and print subblocks + if ($line =~ m/\<\/clocks\>/) { + $next_state = "ST_NORMAL"; + + # Check mcluster_index + if (-1 == $mcluster_index) { + die "Error: Invalid mcluster index: $mcluster_index!\n"; + } + # Print subblocks + my ($num_cell) = ($mclusters_ptr->{matrix_width}*$mclusters_ptr->{matrix_depth}); + for (my $i = 0; $i < $mclusters_ptr->{matrix_depth}; $i++) { + for (my $j = 0; $j < $mclusters_ptr->{matrix_width}; $j++) { + my ($cell_idx) = $i*$mclusters_ptr->{matrix_width} + $j; + # Fill block_name and instance_name + my ($block_name,$instance_name) = ($mclusters_ptr->{"MCluster$mcluster_index"}->{"cell[$i][$j]"}->{net},"cell[$cell_idx]"); + print FNETO " "; + print FNETO "\n"; + # Check if this block has been used. + if ("open" ne $block_name) { + # Print Input Ports, Output Ports, ignore clocks + print FNETO " "; + print FNETO " \n"; + print FNETO " "; + print FNETO " {arch_model}->{cell_inport_name}->{val}\">"; + for (my $k = 0; $k < $mclusters_ptr->{cell_size}; $k++) { + if ("unconn" eq $mclusters_ptr->{"MCluster$mcluster_index"}->{"cell[$i][$j]"}->{"I[$k]"}) { + print FNETO "open "; + } + elsif (0 == $i) { + my ($tmp_idx) = ($j*$mclusters_ptr->{cell_size}+$k); + print FNETO "matrix[0].I[$tmp_idx]\-\>cell[$i][$j]_input[$k] "; + } + else { + my ($pred_idx) = ($mclusters_ptr->{"arch"}->{"cell[$i][$j]"}->{"I[$k]"}+($i-1)*$mclusters_ptr->{matrix_width}); + print FNETO "cell[$pred_idx].$conf_ptr->{arch_model}->{cell_outport_name}->{val}\-\>cell[$i][$j]_input[$k] "; + } + } + print FNETO "\n"; + print FNETO " "; + print FNETO " \n"; + print FNETO " "; + print FNETO " \n"; + print FNETO " "; + print FNETO " {arch_model}->{cell_outport_name}->{val}\">"; + print FNETO "$block_name "; + print FNETO "\n"; + print FNETO " "; + print FNETO " \n"; + print FNETO " "; + print FNETO " \n"; + print FNETO " "; + print FNETO " \n"; + } + print FNETO " "; + print FNETO "\n"; + } + } + } + } + $state = $next_state; + if ("on" eq $opt_ptr->{debug}) { + print "DEBUG: Current State=$state\n"; + } + } + + # Close files + close(FNETI); + close(FNETO); + + #print "Generate Net_file_VPR \($opt_ptr->{net_file_out_val}\) from Net_file_AAPACK \($opt_ptr->{net_file_in_val}\) Complete\n"; + print "Complete\n"; +} + +# Main Program +sub main() +{ + # Read Options. All options stored in opt_ptr + &opts_read(); + + # Read basic configuration file. All confs stored in conf_ptr + &read_conf(); + + # Read mpack report file + &read_mpack1_rpt(); + + # Complete tasks according to selected mode + if ("pack_arch" eq $opt_ptr->{"mode_val"}) { + # Generate Architecture XML for AAPack + &gen_arch_pack(); + } + elsif ("m2net" eq $opt_ptr->{"mode_val"}) { + # Generate Architecture XML for VPR + &gen_arch_vpr(); + # Generate Net for VPR + &gen_net_vpr(); + } + else { + die "Error: Invalid mode selected!\n"; + } + +} + +&main(); +exit(0); diff --git a/fpga_flow/scripts/pro_blif.pl b/fpga_flow/scripts/pro_blif.pl new file mode 100644 index 000000000..281c5dffa --- /dev/null +++ b/fpga_flow/scripts/pro_blif.pl @@ -0,0 +1,412 @@ +#!usr/bin/perl -w +use strict; +#use Shell; +use FileHandle; +#Use the time +use Time::gmtime; + +#Get Date +my $mydate = gmctime(); +my ($char_per_line) = (80); + +my ($fname,$frpt); +my ($remove_buffers) = (0); +my ($default_clk_name) = ("clk"); +my @buffers_to_remove; +my @buffers_to_rename; + +sub print_usage() +{ + print "Usage:\n"; + print " perl [-options]\n"; + print " Options:(Mandatory!)\n"; + print " -i \n"; + print " -o \n"; + print " Options: (Optional)\n"; + print " -remove_buffers\n"; + print "\n"; + return 1; +} + +sub opts_read() +{ + if (-1 == $#ARGV) + { + print "Error: No input argument!\n"; + &print_usage(); + exit(1); + } + else + { + for (my $iargv = 0; $iargv < $#ARGV+1; $iargv++) + { + if ("-i" eq $ARGV[$iargv]) + {$fname = $ARGV[$iargv+1];} + elsif ("-o" eq $ARGV[$iargv]) + {$frpt = $ARGV[$iargv+1];} + elsif ("-remove_buffers" eq $ARGV[$iargv]) { + $remove_buffers = 1; + } + } + } + return 1; +} + +# Print a line of blif netlist +sub fprint_blifln($ $ $) { + my ($FH, $tokens_ref, $char_per_line) = @_; + my ($cur_line_len) = (0); + my @tokens = @$tokens_ref; + + if ($char_per_line < 1) { + die "ERROR: (fprint_blifln) minimum acceptable number of chars in a line is 1!\n"; + } + # if the length of current line exceed the char_per_line, + # A continue line '\' is added and start a new line + for (my $itok = 0; $itok < ($#tokens+1); $itok++) { + if (!($tokens[$itok])) { + next; + } + # Contain any buffer names to be removed won't show up + if (1 == $remove_buffers) { + for (my $ibuf = 0; $ibuf < $#buffers_to_remove + 1; $ibuf++) { + if ($tokens[$itok] eq $buffers_to_remove[$ibuf]) { + $tokens[$itok] = $buffers_to_rename[$ibuf]; + } + } + } + $cur_line_len += length($tokens[$itok]); + if ($cur_line_len > $char_per_line) { + print $FH "\\"."\n"; + $cur_line_len = 0; + } + print $FH "$tokens[$itok] "; + $cur_line_len += length($tokens[$itok]); + } + print $FH "\n"; + +} + +sub read_blifline($ $) { + my ($FIN, $line_no_ptr) = @_; + my ($lines,$line) = ("",""); + + # Get one line + if (defined($line = <$FIN>)) { + chomp $line; + $lines = $line; + # Replace the < and > with [ and ], VPR does not support... + $lines =~ s//]/g; + while($lines =~ m/\\$/) { + $lines =~ s/\\$//; + if (defined($line = <$FIN>)) { + chomp $line; + $lines = $lines.$line; + $line =~ s//]/g; + } else { + return $lines; + } + } + return $lines; + } else { + return $lines; + } + +} + +sub process_blifmodel($ $) { + my ($FIN,$line_no_ptr) = @_; + my ($blackbox) = (0); + my ($lines); + my ($clk_num,$have_default_clk,$need_default_clk,$clk_recorded) = (0,0,0,0); + my @model_input_tokens; + my ($input_lines); + + while(!eof($FIN)) { + # Get one line + $lines = &read_blifline($FIN,$line_no_ptr); + # Check the tokens + if (!defined($lines)) { + next; + } + my @tokens = split('\s+',$lines); + # .end -> return + if (!defined($tokens[0])) { + next; + } + if (".end" eq $tokens[0]) { + return (\@model_input_tokens,$blackbox,$clk_num,$have_default_clk,$need_default_clk); + } elsif (".inputs" eq $tokens[0]) { + foreach my $temp(@tokens) { + if ($temp eq $default_clk_name) { + $have_default_clk = 1; + $clk_num++; + last; + } + } + @model_input_tokens = @tokens; + } elsif (".blackbox" eq $tokens[0]) { + $blackbox = 1; + } elsif (".latch" eq $tokens[0]) { + # illegal definition exit + if ((3 != $#tokens)&&(5 != $#tokens)) { + die "ERROR: [LINE: $$line_no_ptr]illegal definition of latch!\n"; + } elsif (3 == $#tokens) { + # We need a default clock + if ($need_default_clk == 0) { + $need_default_clk = 1; + $clk_num++; + } + } elsif (5 == $#tokens) { + $clk_recorded = 0; + # Check if we have this clk names already + foreach my $tmp(@model_input_tokens) { + if ($tmp eq $tokens[4]) { + $clk_recorded = 1; + last; + } + } + # if have been recorded, we push it into the array + if (0 == $clk_recorded) { + $clk_num++; + push @model_input_tokens,$tokens[4]; + } + } + # Could be subckt or .names + } elsif (".names" eq $tokens[0]) { + if ((3 == ($#tokens + 1))&&(1 == $remove_buffers)) { + # We want to know is this a buffer??? + my $lut_lines = &read_blifline($FIN,$line_no_ptr); + my @lut_lines_tokens = split('\s+',$lut_lines); + if ((2 == ($#lut_lines_tokens + 1))&&("1" eq $lut_lines_tokens[0])&&("1" eq $lut_lines_tokens[1])) { + # push it to the array: buffers_to_remove + push @buffers_to_remove,$tokens[1]; + push @buffers_to_rename,$tokens[2]; + } + } + } + } + # Re-organise the input lines + #print @model_input_tokens; + $input_lines = ".inputs "; + foreach my $temp(@model_input_tokens) { + if (".inputs" ne $temp) { + $input_lines .= $temp." "; + } + } + $input_lines =~ s/\s+$//; + @model_input_tokens = split('\s+',$input_lines); + + return (\@model_input_tokens,$blackbox,$clk_num,$have_default_clk,$need_default_clk); +} + +sub scan_blif() +{ + my ($line,$lines); + my @tokens; + my ($clk_num,$have_default_clk,$need_default_clk,$clk_recorded); + my ($blackbox,$model_clk_num); + my @input_tokens; + my $input_lines; + my (@input_buffer); + my ($line_no) = (0); + + # Pre-process the netlist + # Open src file first-scan to check if we have clock + my ($FIN) = FileHandle->new; + if ($FIN->open("< $fname")) { + print "INFO: Parsing $fname...\n"; + } else { + die "ERROR: Fail to open $fname!\n"; + } + while(!eof($FIN)) { + # Get one line + $lines = &read_blifline($FIN); + if (!defined($lines)) { + next; + } + @tokens = split('\s+',$lines); + if (!defined($tokens[0])) { + next; + } + # When we found .model we should check it. until .end comes. + # Check if it is a black box + if (".model" eq $tokens[0]) { + ($input_lines,$blackbox,$model_clk_num,$have_default_clk,$need_default_clk) = &process_blifmodel($FIN,\$line_no); + if (0 == $blackbox) { + @input_tokens = @$input_lines; + } + $clk_num += $model_clk_num; + } + } + close($FIN); + + # Add default clock + print "INFO: $clk_num clock ports need to be added.\n"; + print "INFO: have_default_clk: $have_default_clk, need_default_clk: $need_default_clk\n"; + if ((0 == $have_default_clk)&&(1 == $need_default_clk)) { + push @input_tokens,$default_clk_name; + } + # Bypass some sensitive tokens + for(my $itok = 0; $itok < $#input_tokens+1; $itok++) { + if ("unconn" eq $input_tokens[$itok]) { + delete $input_tokens[$itok]; + } + } + # Print Buffer names to be removed + my $num_buffer_to_remove = $#buffers_to_remove + 1; + print "INFO: $num_buffer_to_remove buffer to be removed:\n"; + for(my $itok = 0; $itok < $#buffers_to_remove+1; $itok++) { + print $buffers_to_remove[$itok]." will be renamed to ".$buffers_to_rename[$itok]."\n"; + } + + + # Second scan - write + my ($inputs_written) = (0); + my ($FIN2) = FileHandle->new; + if ($FIN2->open("< $fname")) { + print "INFO: Parsing $fname the second time...\n"; + } else { + die "ERROR: Fail to open $fname!\n"; + } + # Open des file + my ($FOUT) = (FileHandle->new); + if (!($FOUT->open("> $frpt"))) { + die "Fail to create output file: $frpt!\n"; + } + while(!eof($FIN2)) { + $line = <$FIN2>; + chomp $line; + if ($line eq "") { + print $FOUT "\n"; + next; + } + # Replace the < and > with [ and ], VPR does not support... + $line =~ s//]/g; + # Check if this line start with ".latch", which we cares only + @tokens = split('\s+',$line); + if ((".inputs" eq $tokens[0])&&(0 == $inputs_written)) { + $lines = $line; + while($lines =~ m/\\$/) { + $line = <$FIN2>; + chomp $line; + # Replace the < and > with [ and ], VPR does not support... + $line =~ s//]/g; + $lines =~ s/\\$//; + $lines = $lines.$line; + } + #print @input_tokens."\n"; + &fprint_blifln($FOUT,\@input_tokens,$char_per_line); + $inputs_written = 1; + next; + } + if (".outputs" eq $tokens[0]) { + $lines = $line; + while($lines =~ m/\\$/) { + $line = <$FIN2>; + chomp $line; + # Replace the < and > with [ and ], VPR does not support... + $line =~ s//]/g; + $lines =~ s/\\$//; + $lines = $lines.$line; + } + my @output_tokens = split('\s',$lines); + for(my $itok = 0; $itok < $#output_tokens+1; $itok++) { + if ("unconn" eq $output_tokens[$itok]) { + delete $output_tokens[$itok]; + } + } + &fprint_blifln($FOUT,\@output_tokens,$char_per_line); + next; + + } + if (".latch" eq $tokens[0]) { + # check if we need complete it + if ($#tokens == 3) { + # Complete it + for (my $i=0; $i<3; $i++) { + print $FOUT "$tokens[$i] "; + } + print $FOUT "re clk $tokens[3]\n"; + } elsif ($#tokens == 5) { + # replace the clock name with clk + for (my $i=0; $i < ($#tokens+1); $i++) { + # if (4 == $i) { + # print $FOUT "clk "; + # } else { + print $FOUT "$tokens[$i] "; + # } + } + print $FOUT "\n"; + } else { + die "ERROR: [LINE: $line_no]illegal definition of latch!\n"; + } + next; + } elsif (".names" eq $tokens[0]) { + if ((3 == ($#tokens + 1))&&(1 == $remove_buffers)) { + # We want to know is this a buffer??? + my $lut_lines = &read_blifline($FIN2,\$line_no); + my @lut_lines_tokens = split('\s+',$lut_lines); + if ((2 == ($#lut_lines_tokens + 1))&&("1" eq $lut_lines_tokens[0])&&("1" eq $lut_lines_tokens[1])) { + # pass it. + next; + } else { + print $FOUT "$line\n"; + print $FOUT "$lut_lines\n"; + } + } else { + print $FOUT "$line\n"; + } + next; + } elsif ((".subckt" eq $tokens[0])&&(1 == $remove_buffers)) { + $lines = $line; + $lines =~ s/\s+$//; + while($lines =~ m/\\$/) { + $line = <$FIN2>; + chomp $line; + # Replace the < and > with [ and ], VPR does not support... + $line =~ s//]/g; + $lines =~ s/\\$//; + $lines = $lines.$line; + $lines =~ s/\s+$//; #ODIN II has some shit space after \ !!!!! + } + my @subckt_tokens = split('\s+',$lines); + for(my $itok = 0; $itok < $#subckt_tokens+1; $itok++) { + if (($itok > 1)&&("" ne $subckt_tokens[$itok])) { + my @port_tokens = split('=',$subckt_tokens[$itok]); + for (my $ibuf = 0; $ibuf < $#buffers_to_remove + 1; $ibuf++) { + if ($port_tokens[1] eq $buffers_to_remove[$ibuf]) { + $port_tokens[1] = $buffers_to_rename[$ibuf]; + } + } + $subckt_tokens[$itok] = join ('=',$port_tokens[0],$port_tokens[1]); + #print "See:".$subckt_tokens[$itok]."\n"; + } + } + &fprint_blifln($FOUT,\@subckt_tokens,$char_per_line); + + next; + } + + print $FOUT "$line\n"; + } + close($FIN2); + close($FOUT); + return 1; +} + +sub main() +{ + &opts_read(); + &scan_blif(); + return 1; +} + +&main(); +exit(1); diff --git a/fpga_flow/scripts/run_fpga_spice.pl b/fpga_flow/scripts/run_fpga_spice.pl new file mode 100644 index 000000000..8fede08da --- /dev/null +++ b/fpga_flow/scripts/run_fpga_spice.pl @@ -0,0 +1,1699 @@ +#!usr/bin/perl -w +# use the strict mode +use strict; +# Use the Shell enviornment +#use Shell; +# Use the time +use Time::gmtime; +# Use switch module +#use Switch; +use File::Path; +use Cwd; +use FileHandle; +# Multi-thread support +use threads; +use threads::shared; +# use ceil and floor numeric function +use POSIX; + +# Date +my $mydate = gmctime(); +# Current Path +my $cwd = getcwd(); + +# Global Variants +# input Option Hash +my %opt_h; +my $opt_ptr = \%opt_h; +# configurate file hash +my %conf_h; +my $conf_ptr = \%conf_h; +# reports hash +my %rpt_h; +my $rpt_ptr = \%rpt_h; +# tb_names hash +my %tb_names_h; +my $tb_names_ptr = \%tb_names_h; + +# Benchmarks +my @benchmark_names; +my %benchmarks; +my $benchmarks_ptr = \%benchmarks; +my %task_status; +my $task_status_ptr = \%task_status; + +# Testbench names +my @pb_mux_tb_names; +my @cb_mux_tb_names; +my @sb_mux_tb_names; +my @lut_tb_names; +my @hardlogic_tb_names; +my @grid_tb_names; +my @cb_tb_names; +my @sb_tb_names; +my @top_tb_name; + +# Configuration file keywords list +# Category for conf file. +# main category : 1st class +my @mctgy; +# sub category : 2nd class +my @sctgy; +# Initialize these categories +@mctgy = ("dir_path", + "task_conf", + "csv_tags", + ); +# refer to the keywords of dir_path +@{$sctgy[0]} = ("result_dir", + "shell_script_name", + "top_tb_dir_name", + "grid_tb_dir_name", + "lut_tb_dir_name", + "hardlogic_tb_dir_name", + "pb_mux_tb_dir_name", + "cb_mux_tb_dir_name", + "sb_mux_tb_dir_name", + "cb_tb_dir_name", + "sb_tb_dir_name", + "top_tb_prefix", + "pb_mux_tb_prefix", + "cb_mux_tb_prefix", + "sb_mux_tb_prefix", + "lut_tb_prefix", + "hardlogic_tb_prefix", + "grid_tb_prefix", + "cb_tb_prefix", + "sb_tb_prefix", + "top_tb_postfix", + "pb_mux_tb_postfix", + "cb_mux_tb_postfix", + "sb_mux_tb_postfix", + "lut_tb_postfix", + "hardlogic_tb_postfix", + "grid_tb_postfix", + "cb_tb_postfix", + "sb_tb_postfix", + ); +# refer to the keywords of flow_type +@{$sctgy[1]} = ("auto_check", + "num_pb_mux_tb", + "num_cb_mux_tb", + "num_sb_mux_tb", + "num_lut_mux_tb", + "num_hardlogic_tb", + "num_grid_mux_tb", + "num_top_tb", + "num_cb_tb", + "num_sb_tb", + ); +# refer to the keywords of csv_tags +@{$sctgy[2]} = ("top_tb_leakage_power_tags", + "top_tb_dynamic_power_tags", + "pb_mux_tb_leakage_power_tags", + "pb_mux_tb_dynamic_power_tags", + "cb_mux_tb_leakage_power_tags", + "cb_mux_tb_dynamic_power_tags", + "sb_mux_tb_leakage_power_tags", + "sb_mux_tb_dynamic_power_tags", + "lut_tb_leakage_power_tags", + "lut_tb_dynamic_power_tags", + "hardlogic_tb_leakage_power_tags", + "hardlogic_tb_dynamic_power_tags", + "grid_tb_leakage_power_tags", + "grid_tb_dynamic_power_tags", + "cb_tb_leakage_power_tags", + "cb_tb_dynamic_power_tags", + "sb_tb_leakage_power_tags", + "sb_tb_dynamic_power_tags", + ); + +# ----------Subrountines------------# +# Print TABs and strings +sub tab_print($ $ $) +{ + my ($FILE,$str,$num_tab) = @_; + my ($my_tab) = (" "); + + for (my $i = 0; $i < $num_tab; $i++) { + print $FILE "$my_tab"; + } + print $FILE "$str"; +} + +# Create paths if it does not exist. +sub generate_path($) +{ + my ($mypath) = @_; + if (!(-e "$mypath")) + { + mkpath "$mypath"; + print "Path($mypath) does not exist...Create it.\n"; + } + return 1; +} + +# Print the usage +sub print_usage() +{ + print "Usage:\n"; + print " run_fpga_spice.pl [-options ]\n"; + print " Mandatory options: \n"; + print " -conf : specify the basic configuration files for run_fpga_spice\n"; + print " -task : the configuration file contains benchmark file names\n"; + print " -rpt : CSV file consists of data\n"; + print " Other Options:\n"; + print " -monte_carlo : Specify Monte Carlo simulation is enabled in FPGA-SPICE, specify the type of reports. (Simple: only max/min/avg is reported; Detail: every MC case is reported.\n"; + print " -parse_pb_mux_tb: parse the results in pb_mux_testbench\n"; + print " -parse_cb_mux_tb: parse the results in cb_mux_testbench\n"; + print " -parse_sb_mux_tb: parse the results in sb_mux_testbench\n"; + print " -parse_lut_tb: parse the results in lut_testbench\n"; + print " -parse_hardlogic_tb: parse the results in hardlogic_testbench\n"; + print " -parse_grid_tb: parse the results in grid_testbench\n"; + print " -parse_cb_tb: parse the results in cb_testbench\n"; + print " -parse_sb_tb: parse the results in sb_testbench\n"; + print " -parse_top_tb: parse the results in top_testbench\n"; + print " -multi_thread : turn on multi-thread mode, specify the number of processors could be pushed\n"; + print " -sim_leakage_power_only : simulate leakage power only.\n"; + print " -parse_results_only : only parse HSPICE simulation results\n"; + print " -debug : debug mode\n"; + print " -help : print usage\n"; + exit(1); + return 1; +} + +sub spot_option($ $) { + my ($start,$target) = @_; + my ($arg_no,$flag) = (-1,"unfound"); + for (my $iarg = $start; $iarg < $#ARGV+1; $iarg++) { + if ($ARGV[$iarg] eq $target) { + if ("found" eq $flag) { + print "Error: Repeated Arguments!(IndexA: $arg_no,IndexB: $iarg)\n"; + &print_usage(); + } else { + $flag = "found"; + $arg_no = $iarg; + } + } + } + # return the arg_no if target is found + # or return -1 when target is missing + return $arg_no; +} + +# Specify in the input list, +# 1. Option Name +# 2. Whether Option with value. if yes, choose "on" +# 3. Whether Option is mandatory. If yes, choose "on" +sub read_opt_into_hash($ $ $) { + my ($opt_name,$opt_with_val,$mandatory) = @_; + # Check the -$opt_name + my ($opt_fact) = ("-".$opt_name); + my ($cur_arg) = (0); + my ($argfd) = (&spot_option($cur_arg,"$opt_fact")); + if ($opt_with_val eq "on") { + if (-1 != $argfd) { + if ($ARGV[$argfd+1] =~ m/^-/) { + print "The next argument cannot start with '-'!\n"; + print "it implies an option!\n"; + } else { + $opt_ptr->{"$opt_name\_val"} = $ARGV[$argfd+1]; + $opt_ptr->{"$opt_name"} = "on"; + } + } else { + $opt_ptr->{"$opt_name"} = "off"; + if ($mandatory eq "on") { + print "Mandatory option: $opt_fact is missing!\n"; + &print_usage(); + } + } + } else { + if (-1 != $argfd) { + $opt_ptr->{"$opt_name"} = "on"; + } else { + $opt_ptr->{"$opt_name"} = "off"; + if ($mandatory eq "on") { + print "Mandatory option: $opt_fact is missing!\n"; + &print_usage(); + } + } + } + return 1; +} + +# Read options +sub opts_read() { + # if no arguments detected, print the usage. + if (-1 == $#ARGV) { + print "Error : No input arguments!\n"; + &print_usage(); + exit(1); + } + # Read in the options + my ($cur_arg,$arg_found); + $cur_arg = 0; + print "Analyzing your options...\n"; + # Read the options with internal options + my $argfd; + # Check help fist + $argfd = &spot_option($cur_arg,"-help"); + if (-1 != $argfd) { + print "Help desk:\n"; + &print_usage(); + } + # Then Check the debug with highest priority + $argfd = &spot_option($cur_arg,"-debug"); + if (-1 != $argfd) { + $opt_ptr->{"debug"} = "on"; + } else { + $opt_ptr->{"debug"} = "off"; + } + # Check mandatory options + # Check the -conf + # Read Opt into Hash(opt_ptr) : "opt_name","with_val","mandatory" + &read_opt_into_hash("conf","on","on"); + &read_opt_into_hash("task","on","on"); + &read_opt_into_hash("rpt","on","on"); + + # Optional options + &read_opt_into_hash("monte_carlo","on","off"); + &read_opt_into_hash("sim_leakage_power_only","off","off"); + &read_opt_into_hash("parse_results_only","off","off"); + &read_opt_into_hash("multi_thread","on","off"); + &read_opt_into_hash("parse_pb_mux_tb","off","off"); + &read_opt_into_hash("parse_cb_mux_tb","off","off"); + &read_opt_into_hash("parse_sb_mux_tb","off","off"); + &read_opt_into_hash("parse_lut_tb","off","off"); + &read_opt_into_hash("parse_hardlogic_tb","off","off"); + &read_opt_into_hash("parse_grid_tb","off","off"); + &read_opt_into_hash("parse_cb_tb","off","off"); + &read_opt_into_hash("parse_sb_tb","off","off"); + &read_opt_into_hash("parse_top_tb","off","off"); + + &print_opts(); + + return 1; +} + +# List the options +sub print_opts() { + print "List your options\n"; + + while(my ($key,$value) = each(%opt_h)) { + print "$key : $value\n"; + } + + return 1; +} + + +# Read each line and ignore the comments which starts with given arg +# return the valid information of line +sub read_line($ $) { + my ($line,$com) = @_; + my @chars; + if (defined($line)) { + @chars = split/$com/,$line; + if (!($line =~ m/[\w\d]/)) { + $chars[0] = undef; + } + if ($line =~ m/^\s*$com/) { + $chars[0] = undef; + } + } else { + $chars[0] = undef; + } + if (defined($chars[0])) { + $chars[0] =~ s/^(\s+)//g; + $chars[0] =~ s/(\s+)$//g; + } + return $chars[0]; +} + +# Check each keywords has been defined in configuration file +sub check_keywords_conf() { + for (my $imcg = 0; $imcg<$#mctgy+1; $imcg++) { + for (my $iscg = 0; $iscg<$#{$sctgy[$imcg]}+1; $iscg++) { + if (defined($conf_ptr->{$mctgy[$imcg]}->{$sctgy[$imcg]->[$iscg]}->{val})) { + if ("on" eq $opt_ptr->{debug}) { + print "Keyword($mctgy[$imcg],$sctgy[$imcg]->[$iscg]) = "; + print "$conf_ptr->{$mctgy[$imcg]}->{$sctgy[$imcg]->[$iscg]}->{val}"; + print "\n"; + } + } else { + die "Error: Keyword($mctgy[$imcg],$sctgy[$imcg]->[$iscg]) is missing!\n"; + } + } + } + return 1; +} + +# Read the configuration file +sub read_conf() { + # Read in these key words + my ($line,$post_line); + my @equation; + my $cur = "unknown"; + open (CONF, "< $opt_ptr->{conf_val}") or die "Fail to open $opt_ptr->{conf_val}!\n"; + print "Reading $opt_ptr->{conf_val}...\n"; + while(defined($line = )) { + chomp $line; + $post_line = &read_line($line,"#"); + if (defined($post_line)) { + if ($post_line =~ m/\[(\w+)\]/) { + $cur = $1; + } elsif ("unknown" eq $cur) { + die "Error: Unknown tags for this line!\n$post_line\n"; + } else { + $post_line =~ s/\s//g; + @equation = split /=/,$post_line; + if (!(defined($equation[1]))) { + $equation[1] = ""; + } + $conf_ptr->{$cur}->{$equation[0]}->{val} = $equation[1]; + } + } + } + # Check these key words + print "Read complete!\n"; + &check_keywords_conf(); + print "Checking these keywords..."; + print "Successfully\n"; + close(CONF); + return 1; +} + +sub read_benchmarks() { + # Read in file names + my ($line,$post_line,$cur); + $cur = 0; + open (FCONF,"< $opt_ptr->{task_val}") or die "Fail to open $opt_ptr->{task}!\n"; + print "Reading $opt_ptr->{task_val}...\n"; + while(defined($line = )) { + chomp $line; + $post_line = &read_line($line,"#"); + if (defined($post_line)) { + $post_line =~ s/\s+//g; + my @tokens = split(",",$post_line); + # first is the benchmark name, + #the second is the channel width, if applicable + if ($#tokens < 2) { + die "ERROR: invalid definition for a benchmark! At least include 3 tokens!\n"; + } + if ($tokens[0]) { + $benchmark_names[$cur] = $tokens[0]; + } else { + die "ERROR: invalid definition for benchmarks!\n"; + } + $benchmarks_ptr->{"$benchmark_names[$cur]"}->{spice_netlist_prefix} = $tokens[1]; + $benchmarks_ptr->{"$benchmark_names[$cur]"}->{spice_dir} = $tokens[2]; + $cur++; + } + } + print "Benchmarks(total $cur):\n"; + foreach my $temp(@benchmark_names) { + print "$temp\n"; + } + close(FCONF); + return 1; +} + +# Input program path is like "~/program_dir/program_name" +# We split it from the scalar +sub split_prog_path($) { + my ($prog_path) = @_; + my @path_elements = split /\//,$prog_path; + my ($prog_dir,$prog_name); + + $prog_name = $path_elements[$#path_elements]; + $prog_dir = $prog_path; + $prog_dir =~ s/$prog_name$//g; + + return ($prog_dir,$prog_name); +} + +# Detect and convert unit, NO Case Insentive. +sub process_unit($ $) +{ + my ($unit,$type) = @_; + my ($ret,$coeff) = (0,0); + + # Check type, can be + if ("time" eq $type) { + $unit =~ s/s$//i; + } elsif ("current" eq $type) { + $unit =~ s/A$//; # Special should not mix with "a" = 1e-18 + } elsif ("power" eq $type) { + $unit =~ s/W$//; + } elsif ("voltage" eq $type) { + $unit =~ s/V$//; + } elsif ("capacitance" eq $type) { + $unit =~ s/F$//; # Special should not mix with "f" = 1e-15 + } elsif ("empty" ne $type) { + die "Error: (process_unit)Unknown type!Should be \n"; + } + + # Accepte unit: m = 1e-3, u = 1e-6, n = 1e-9, p = 1e-12, f = 1e-15, a = 1e-18 + if ($unit =~ m/a$/) { + $unit =~ s/a$//; + $coeff = 1e-18; + } elsif ($unit =~ m/f$/) { + $unit =~ s/f$//; + $coeff = 1e-15; + } elsif ($unit =~ m/p$/) { + $unit =~ s/p$//; + $coeff = 1e-12; + } elsif ($unit =~ m/n$/) { + $unit =~ s/n$//; + $coeff = 1e-9; + } elsif ($unit =~ m/u$/) { + $unit =~ s/u$//; + $coeff = 1e-6; + } elsif ($unit =~ m/m$/) { + $unit =~ s/m$//; + $coeff = 1e-3; + } elsif ($unit =~ m/k$/) { + $unit =~ s/k$//; + $coeff = 1e3; + } elsif ($unit =~ m/Meg$/) { + $unit =~ s/Meg$//; + $coeff = 1e6; + } elsif ($unit =~ m/\d$/i) { + $coeff = 1; + } + # Chomp the possible point at the end + $unit =~ s/\.$//; + + # Quick check, there should be only numbers in remaining + if (!($unit =~ m/\d$/)) { + die "Error: (process_unit) Invalid number($unit)!\n"; + } + + return $ret = $unit*$coeff; +} + +# TODO: Check settings +sub check_fpga_spice() { + # Format the dir_path + # Format SPICE prefix +} + +# Initialize the status of all tasks +sub init_tasks_status() { + foreach my $bm(@benchmark_names) { + $task_status_ptr->{$bm}->{status} = "wait"; + $task_status_ptr->{$bm}->{thread_id} = undef; + } +} + +sub check_all_fpga_spice_tasks_done() { + foreach my $bm(@benchmark_names) { + if ("done" ne $task_status_ptr->{$bm}->{status}) { + return 0; + } + } + return 1; +} + +sub mark_all_fpga_spice_tasks_done() { + foreach my $bm(@benchmark_names) { + $task_status_ptr->{$bm}->{status} = "done"; + } + return 1; +} + +sub print_tasks_status() { + my ($num_jobs_running, $num_jobs_to_run, $num_jobs_finish, $num_jobs) = (0, 0, 0, 0); + + foreach my $benchmark(@benchmark_names) { + # Count the number of jobs + $num_jobs++; + # Count to do jobs + if ("wait" eq $task_status_ptr->{$benchmark}->{status}) { + $num_jobs_to_run++; + next; + } + if ("running" eq $task_status_ptr->{$benchmark}->{status}) { + # Count running jobs + $num_jobs_running++; + next; + } + # Count finished jobs + if ("done" eq $task_status_ptr->{$benchmark}->{status}) { + $num_jobs_finish++; + next; + } + } + if ($num_jobs == ($num_jobs_running + $num_jobs_finish + $num_jobs_to_run)) { + print "Jobs Progress: (Finish rate = ".sprintf("%.2f",100*$num_jobs_finish/$num_jobs) ."%)\n"; + print "Thead utilization rate = ".sprintf("%.2f",100*$num_jobs_running/$opt_ptr->{multi_thread_val})."%\n"; + print "Total No. of Jobs: $num_jobs.\n"; + print "No. of Running Jobs: $num_jobs_running.\n"; + print "No. of Finished Jobs: $num_jobs_finish.\n"; + print "No. of To Run Jobs: $num_jobs_to_run.\n"; + } else { + print "Internal problem: num_jobs($num_jobs) != num_jobs_running($num_jobs_running)\n"; + print " +num_jobs_finish($num_jobs_finish)\n"; + die " +num_jobs_to_run($num_jobs_to_run)\n"; + } + return; +} + +sub format_dir_path($) { + my ($dir_path) = @_; + my ($formatted_dir_path) = ($dir_path); + + if (!($formatted_dir_path =~ m/\/$/)) { + $formatted_dir_path = $formatted_dir_path."/"; + } + + return $formatted_dir_path; +} + +sub gen_fpga_spice_netlists_path($ $ $) { + my ($spice_dir, $sp_prefix, $sp_postfix) = @_; + my ($formatted_spice_dir) = &format_dir_path($spice_dir); + + my ($sp_path) = ($formatted_spice_dir.$sp_prefix.$sp_postfix); + + return ($sp_path); +} + +sub determine_fpga_grid_nx_ny($) { + my ($grid_no) = @_; + + my ($nx, $ny) = (ceil(sqrt($grid_no)), ceil(sqrt($grid_no))); + + return ($nx, $ny); +} + +sub gen_fpga_tb_spice_netlist_path($ $ $ $ $ $) { + my ($spice_dir, $sp_prefix, $tb_prefix, $ix, $iy, $sp_postfix) = @_; + my ($formatted_spice_dir) = &format_dir_path($spice_dir); + + my ($sp_path) = ($formatted_spice_dir.$sp_prefix.$tb_prefix.$ix."_".$iy.$sp_postfix); + + return ($sp_path); +} + +sub gen_fpga_spice_measure_results_path($ $ $) { + my ($spice_dir, $sp_prefix, $sp_postfix) = @_; + my ($formatted_spice_dir) = &format_dir_path($spice_dir); + my ($formatted_result_dir) = &format_dir_path($conf_ptr->{dir_path}->{result_dir}->{val}); + + my ($mt_path) = ($formatted_spice_dir.$formatted_result_dir.$sp_prefix.$sp_postfix); + + $mt_path =~ s/\.sp/.mt0/; + + return ($mt_path); +} + +sub gen_fpga_tb_spice_measure_results_path($ $ $ $ $) { + my ($spice_dir, $sp_prefix, $tb_prefix, $no, $sp_postfix) = @_; + my ($formatted_spice_dir) = &format_dir_path($spice_dir); + my ($formatted_result_dir) = &format_dir_path($conf_ptr->{dir_path}->{result_dir}->{val}); + + my ($mt_path) = ($formatted_spice_dir.$formatted_result_dir.$sp_prefix.$tb_prefix.$no.$sp_postfix); + + $mt_path =~ s/\.sp/.mt0/; + + return ($mt_path); +} + +sub convert_fpga_tb_names_to_measure_names($) { + my ($tb_sp_path, $spice_dir) = @_; + my ($mt_path); + + my ($formatted_spice_dir) = &format_dir_path($spice_dir); + my ($formatted_result_dir) = &format_dir_path($conf_ptr->{dir_path}->{result_dir}->{val}); + + # Split tb_sp_path + my @sp_parts = split('/', $tb_sp_path); + my ($mt_name) = ($sp_parts[$#sp_parts]); + $mt_name =~ s/\.sp$/\.mt0/g; + + ($mt_path) = ($formatted_spice_dir.$formatted_result_dir.$mt_name); + + return $mt_path; +} + +sub remove_fpga_spice_results($) { + my ($spice_dir) = @_; + my ($formatted_spice_dir) = &format_dir_path($spice_dir); + my ($formatted_result_dir) = &format_dir_path($conf_ptr->{dir_path}->{result_dir}->{val}); + + my ($result_dir_path) = ($formatted_spice_dir.$formatted_result_dir); + + #rmtree($result_dir_path,1,1); + `rm -rf $result_dir_path/`; + print "INFO: Simulation Results($result_dir_path) are removed...\n"; + + #`rm -rf $spice_dir/`; + #print "INFO: Spice Directory($spice_dir) is removed...\n"; + + return; +} + +sub check_one_spice_lis_error($) { + my ($lis_path) = @_; + my ($line, $line_no, $warn_no, $err_no) = (undef,0,0,0); + my ($LISFH) = FileHandle->new; + + print "INFO: Checking LIS file($lis_path)...\n"; + + if (!(-e $lis_path)) { + die "ERROR: Fail to find SPICE lis file($lis_path)!\n"; + } + if ($LISFH->open("< $lis_path")) { + while(defined($line = <$LISFH>)) { + chomp $line; + $line_no++; + if ($line =~ m/error/i) { + $err_no++; + print "ERROR($err_no),LIS FILE[LINE$line_no]: ".$line."\n"; + } + if ($line =~ m/warning/i) { + $warn_no++; + print "WARNING($warn_no),LIS FILE[LINE$line_no]: ".$line."\n"; + } + } + } else { + die "ERROR: fail to open $lis_path!\n"; + } + # Close the lis file + close($LISFH); + # Print HSPICE ERROR and Warning Stats + print "HSPICE Sim. reports $err_no errors and $warn_no warnings.\n"; + if ($err_no > 0) { + die "ERROR: Terminate due to errors in HSPICE Sim. reports.\n"; + } + + return; +} + +sub check_one_fpga_spice_task_lis($ $ $) { + my ($benchmark, $spice_netlist_prefix, $spice_dir) = @_; + my ($formatted_spice_dir) = &format_dir_path($spice_dir); + my ($shell_script_path) = $formatted_spice_dir.$conf_ptr->{dir_path}->{shell_script_name}->{val}; + my ($itb, $lis_file_path); + + if ("on" eq $opt_ptr->{parse_top_tb}) { + my ($top_lis_path) = &gen_fpga_spice_measure_results_path($formatted_spice_dir, $spice_netlist_prefix,$conf_ptr->{dir_path}->{top_tb_postfix}->{val}); + $top_lis_path =~ s/\.mt0/.lis/; + &check_one_spice_lis_error($top_lis_path); + } + + if ("on" eq $opt_ptr->{parse_pb_mux_tb}) { + # generate measure results paths + @pb_mux_tb_names = split (',', $tb_names_ptr->{$benchmark}->{pb_mux_tb_names}); + foreach my $tb_sp_filename (@pb_mux_tb_names) { + $lis_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); + $lis_file_path =~ s/\.mt0/.lis/; + &check_one_spice_lis_error($lis_file_path); + } + } + + if ("on" eq $opt_ptr->{parse_cb_mux_tb}) { + # generate measure results paths + @cb_mux_tb_names = split (',', $tb_names_ptr->{$benchmark}->{cb_mux_tb_names}); + foreach my $tb_sp_filename (@cb_mux_tb_names) { + $lis_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); + $lis_file_path =~ s/\.mt0/.lis/; + &check_one_spice_lis_error($lis_file_path); + } + } + + if ("on" eq $opt_ptr->{parse_sb_mux_tb}) { + # generate measure results paths + @sb_mux_tb_names = split (',', $tb_names_ptr->{$benchmark}->{sb_mux_tb_names}); + foreach my $tb_sp_filename (@sb_mux_tb_names) { + $lis_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); + $lis_file_path =~ s/\.mt0/.lis/; + &check_one_spice_lis_error($lis_file_path); + } + } + + if ("on" eq $opt_ptr->{parse_lut_tb}) { + # generate measure results paths + @lut_tb_names = split (',', $tb_names_ptr->{$benchmark}->{lut_tb_names}); + foreach my $tb_sp_filename (@lut_tb_names) { + $lis_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); + $lis_file_path =~ s/\.mt0/.lis/; + &check_one_spice_lis_error($lis_file_path); + } + } + + if (0 == $conf_ptr->{task_conf}->{num_hardlogic_tb}->{val}) { + } elsif ("on" eq $opt_ptr->{parse_hardlogic_tb}) { + # generate measure results paths + @hardlogic_tb_names = split (',', $tb_names_ptr->{$benchmark}->{hardlogic_tb_names}); + foreach my $tb_sp_filename (@hardlogic_tb_names) { + $lis_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); + $lis_file_path =~ s/\.mt0/.lis/; + &check_one_spice_lis_error($lis_file_path); + } + } + + if ("on" eq $opt_ptr->{parse_grid_tb}) { + # generate measure results paths + @grid_tb_names = split (',', $tb_names_ptr->{$benchmark}->{grid_tb_names}); + foreach my $tb_sp_filename (@grid_tb_names) { + $lis_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); + $lis_file_path =~ s/\.mt0/.lis/; + &check_one_spice_lis_error($lis_file_path); + } + } + + if ("on" eq $opt_ptr->{parse_cb_tb}) { + # generate measure results paths + @cb_tb_names = split (',', $tb_names_ptr->{$benchmark}->{cb_tb_names}); + foreach my $tb_sp_filename (@cb_tb_names) { + $lis_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); + $lis_file_path =~ s/\.mt0/.lis/; + &check_one_spice_lis_error($lis_file_path); + } + } + + if ("on" eq $opt_ptr->{parse_sb_tb}) { + # generate measure results paths + @sb_tb_names = split (',', $tb_names_ptr->{$benchmark}->{sb_tb_names}); + foreach my $tb_sp_filename (@sb_tb_names) { + $lis_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); + $lis_file_path =~ s/\.mt0/.lis/; + &check_one_spice_lis_error($lis_file_path); + } + } + + return; +} + +sub init_one_fpga_spice_task_one_tb_results($ $ $ $) { + my ($benchmark, $tbname_tag, $tb_leakage_tags, $tb_dynamic_tags) = @_; + my (@leakage_tags) = split('\|', $tb_leakage_tags); + my (@dynamic_tags) = split('\|', $tb_dynamic_tags); + my ($temp); + + # Check if there is any conflict to reserved words + foreach my $tag(@leakage_tags) { + if (("peak_mem_used" eq $tag)||("total_elapsed_time" eq $tag)) { + die "ERROR: $tbname_tag leakage_power_tags has a conflict word($tag)!\n"; + } + } + if ("off" eq $opt_ptr->{sim_leakage_power_only}) { + foreach my $tag(@dynamic_tags) { + if (("peak_mem_used" eq $tag)||("total_elapsed_time" eq $tag)) { + die "ERROR: $tbname_tag dynamic_power_tags has a conflict word($tag)!\n"; + } + } + } + + $rpt_ptr->{$benchmark}->{$tbname_tag}->{peak_mem_used} = 0; + $rpt_ptr->{$benchmark}->{$tbname_tag}->{total_elapsed_time} = 0; + foreach my $tag(@leakage_tags) { + $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag} = 0; + } + if ("off" eq $opt_ptr->{sim_leakage_power_only}) { + foreach my $tag(@dynamic_tags) { + $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag} = 0; + } + } + + return; +} + +sub parse_one_fpga_spice_task_one_regular_tb_results($ $ $ $ $ $) { + my ($benchmark, $tbname_tag, $tb_lispath, $tb_mtpath, $tb_leakage_tags, $tb_dynamic_tags) = @_; + my (@leakage_tags) = split('\|', $tb_leakage_tags); + my (@dynamic_tags) = split('\|', $tb_dynamic_tags); + my ($line, $found_tran_analysis); + my ($LISFH) = FileHandle->new; + my ($temp); + + # Check if there is any conflict to reserved words + foreach my $tag(@leakage_tags) { + if (("peak_mem_used" eq $tag)||("total_elapsed_time" eq $tag)) { + die "ERROR: $tbname_tag leakage_power_tags has a conflict word($tag)!\n"; + } + } + if ("off" eq $opt_ptr->{sim_leakage_power_only}) { + foreach my $tag(@dynamic_tags) { + if (("peak_mem_used" eq $tag)||("total_elapsed_time" eq $tag)) { + die "ERROR: $tbname_tag dynamic_power_tags has a conflict word($tag)!\n"; + } + } + } + + if (!(-e $tb_lispath)) { + die "ERROR: Fail to find SPICE lis file($tb_lispath)!\n"; + } + if ($LISFH->open("< $tb_lispath")) { + $found_tran_analysis = 0; + while(defined($line = <$LISFH>)) { + chomp $line; + if ((0 == $found_tran_analysis)&&($line =~ m/transient\s+analysis/)) { + $found_tran_analysis = 1; + } + if (0 == $found_tran_analysis) { + next; + } + # Special: get peak memory used and total elapsed time + if ($line =~ m/peak\s+memory\s+used\s+([\d.]+)\s+megabytes/i) { + $temp = $1; + if ((!defined($rpt_ptr->{$benchmark}->{$tbname_tag}->{peak_mem_used})) + ||($rpt_ptr->{$benchmark}->{$tbname_tag}->{peak_mem_used} < $temp)) { + $rpt_ptr->{$benchmark}->{$tbname_tag}->{peak_mem_used} = $temp; + } + next; # We find a match, ignore the rest + } + # Special: get peak memory used and total elapsed time + if ($line =~ m/total\s+elapsed\s+time\s+([\d.]+)\s+seconds/i) { + $temp = $1; + $rpt_ptr->{$benchmark}->{$tbname_tag}->{total_elapsed_time} += $temp; + next; # We find a match, ignore the rest + } + # For leakage power + foreach my $tag(@leakage_tags) { + if ($line =~ m/$tag\s*=\s*([\d.\w\-\+]+)/i) { + $temp = $1; + $temp = &process_unit($temp, "empty"); + $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{avg} += $temp; + next; # We find a match, ignore the rest + } + } + # Bypass dynamic tags if leakage_only is enabled + if ("on" eq $opt_ptr->{sim_leakage_power_only}) { + next; + } + # For dynamic power + foreach my $tag(@dynamic_tags) { + if ($line =~ m/$tag\s*=\s*([\d.\w\-\+]+)/i) { + $temp = $1; + $temp = &process_unit($temp, "empty"); + $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{avg} += $temp; + next; # We find a match, ignore the rest + } + } + } + } else { + die "ERROR: fail to open $tb_lispath!\n"; + } + # Close file + close($LISFH); + + return; +} + + +sub parse_one_fpga_spice_task_one_mc_tb_results($ $ $ $ $ $ $) { + my ($benchmark, $tbname_tag, $tb_lispath, $tb_mtpath, $tb_leakage_tags, $tb_dynamic_tags) = @_; + my (@leakage_tags) = split('\|', $tb_leakage_tags); + my (@dynamic_tags) = split('\|', $tb_dynamic_tags); + my ($line, $found_tran_analysis); + my ($LISFH) = FileHandle->new; + my ($temp, $mc_cnt) = ("", 0); + + # Check if there is any conflict to reserved words + foreach my $tag(@leakage_tags) { + if (("peak_mem_used" eq $tag)||("total_elapsed_time" eq $tag)) { + die "ERROR: $tbname_tag leakage_power_tags has a conflict word($tag)!\n"; + } + # for a clear start + $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{mc_cnt} = 0; + } + if ("off" eq $opt_ptr->{sim_leakage_power_only}) { + foreach my $tag(@dynamic_tags) { + if (("peak_mem_used" eq $tag)||("total_elapsed_time" eq $tag) + ||("mc_min" eq $tag)||("mc_max" eq $tag)||("mc_avg" eq $tag) + ||("mc_total" eq $tag)||("mc_cnt" eq $tag)) { + die "ERROR: $tbname_tag dynamic_power_tags has a conflict word($tag)!\n"; + } + # for a clear start + $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{mc_cnt} = 0; + } + } + + if (!(-e $tb_lispath)) { + die "ERROR: Fail to find SPICE lis file($tb_lispath)!\n"; + } + if ($LISFH->open("< $tb_lispath")) { + $found_tran_analysis = 0; + while(defined($line = <$LISFH>)) { + chomp $line; + if ((0 == $found_tran_analysis)&&($line =~ m/transient\s+analysis/)) { + $found_tran_analysis = 1; + } + if (0 == $found_tran_analysis) { + next; + } + # Special: get peak memory used and total elapsed time + if ($line =~ m/peak\s+memory\s+used\s+([\d.]+)\s+megabytes/i) { + $temp = $1; + if ((!defined($rpt_ptr->{$benchmark}->{$tbname_tag}->{peak_mem_used})) + ||($rpt_ptr->{$benchmark}->{$tbname_tag}->{peak_mem_used} < $temp)) { + $rpt_ptr->{$benchmark}->{$tbname_tag}->{peak_mem_used} = $temp; + } + next; # We find a match, ignore the rest + } + # Special: get peak memory used and total elapsed time + if ($line =~ m/total\s+elapsed\s+time\s+([\d.]+)\s+seconds/i) { + $temp = $1; + $rpt_ptr->{$benchmark}->{$tbname_tag}->{total_elapsed_time} += $temp; + next; # We find a match, ignore the rest + } + # For leakage power + foreach my $tag(@leakage_tags) { + if ($line =~ m/$tag\s*=\s*([\d.\w\-\+]+)/i) { + $temp = $1; + $temp = &process_unit($temp, "empty"); + $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{mc_cnt} += 1; + $mc_cnt = $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{mc_cnt}; + if (defined($rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{"mc".$mc_cnt})) { + $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{"mc".$mc_cnt} += $temp; + } else { + $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{"mc".$mc_cnt} = $temp; + } + next; # We find a match, ignore the rest + } + } + # Bypass dynamic tags if leakage_only is enabled + if ("on" eq $opt_ptr->{sim_leakage_power_only}) { + next; + } + # For dynamic power + foreach my $tag(@dynamic_tags) { + if ($line =~ m/$tag\s*=\s*([\d.\w\-\+]+)/i) { + $temp = $1; + $temp = &process_unit($temp, "empty"); + $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{mc_cnt} += 1; + $mc_cnt = $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{mc_cnt}; + if (defined($rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{"mc".$mc_cnt})) { + $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{"mc".$mc_cnt} += $temp; + } else { + $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{"mc".$mc_cnt} = $temp; + } + next; # We find a match, ignore the rest + } + } + } + } else { + die "ERROR: fail to open $tb_lispath!\n"; + } + # Close file + close($LISFH); + + return; +} + +sub parse_one_fpga_spice_task_one_tb_results($ $ $ $ $ $) { + my ($benchmark, $tbname_tag, $tb_lispath, $tb_mtpath, $tb_leakage_tags, $tb_dynamic_tags) = @_; + + if ("on" eq $opt_ptr->{monte_carlo}) { + &parse_one_fpga_spice_task_one_mc_tb_results($benchmark, $tbname_tag, $tb_lispath, $tb_mtpath, + $tb_leakage_tags, $tb_dynamic_tags); + } else { + &parse_one_fpga_spice_task_one_regular_tb_results($benchmark, $tbname_tag, $tb_lispath, $tb_mtpath, + $tb_leakage_tags, $tb_dynamic_tags); + } + + return; +} + +sub count_num_tb_one_folder($) { + my ($dir) = @_; + my (@files) = <$dir/*.sp>; + my ($count) = $#files + 1; + return $count; +} + +sub get_tb_file_names($) { + my ($tb_dir) = @_; + my @ret_file_names; + my ($dh); + + # Search all the sp files matching the name + opendir($dh, $tb_dir) || die "Fail to open directory of $tb_dir\n"; + @ret_file_names = grep(/\.sp$/, readdir($dh)); + print "Getting testbench file names for $tb_dir ...\n"; + closedir($dh); + + # join the names together + my ($ret) = join(",", @ret_file_names); + + return $ret; +} + +sub auto_check_tb_num($ $ $) { + my ($benchmark, $spice_netlist_prefix, $spice_dir) = @_; + my ($formatted_spice_dir) = &format_dir_path($spice_dir); + my ($tb_dir); + + print "Autocheck Results:\n"; + + # count pb_mux_tb + $conf_ptr->{task_conf}->{num_pb_mux_tb}->{val} = &count_num_tb_one_folder($formatted_spice_dir.$conf_ptr->{dir_path}->{pb_mux_tb_dir_name}->{val}); + print "INFO: No. of CLB MUXes testbenches = $conf_ptr->{task_conf}->{num_pb_mux_tb}->{val}\n"; + + # count sb_mux_tb + $conf_ptr->{task_conf}->{num_sb_mux_tb}->{val} = &count_num_tb_one_folder($formatted_spice_dir.$conf_ptr->{dir_path}->{sb_mux_tb_dir_name}->{val}); + print "INFO: No. of Switch Box MUXes testbenches = $conf_ptr->{task_conf}->{num_sb_mux_tb}->{val}\n"; + + # count cb_mux_tb + $conf_ptr->{task_conf}->{num_cb_mux_tb}->{val} = &count_num_tb_one_folder($formatted_spice_dir.$conf_ptr->{dir_path}->{cb_mux_tb_dir_name}->{val}); + print "INFO: No. of Connection Box MUXes testbenches = $conf_ptr->{task_conf}->{num_cb_mux_tb}->{val}\n"; + + # count lut_tb + $conf_ptr->{task_conf}->{num_lut_tb}->{val} = &count_num_tb_one_folder($formatted_spice_dir.$conf_ptr->{dir_path}->{lut_tb_dir_name}->{val}); + print "INFO: No. of LUT testbenches = $conf_ptr->{task_conf}->{num_lut_tb}->{val}\n"; + + # count hardlogic_tb + $conf_ptr->{task_conf}->{num_hardlogic_tb}->{val} = &count_num_tb_one_folder($formatted_spice_dir.$conf_ptr->{dir_path}->{hardlogic_tb_dir_name}->{val}); + print "INFO: No. of FF testbenches = $conf_ptr->{task_conf}->{num_hardlogic_tb}->{val}\n"; + + # count grid_tb + $conf_ptr->{task_conf}->{num_grid_tb}->{val} = &count_num_tb_one_folder($formatted_spice_dir.$conf_ptr->{dir_path}->{grid_tb_dir_name}->{val}); + print "INFO: No. of Grid testbenches = $conf_ptr->{task_conf}->{num_grid_tb}->{val}\n"; + + # count cb_tb + $conf_ptr->{task_conf}->{num_cb_tb}->{val} = &count_num_tb_one_folder($formatted_spice_dir.$conf_ptr->{dir_path}->{cb_tb_dir_name}->{val}); + print "INFO: No. of CB testbenches = $conf_ptr->{task_conf}->{num_cb_tb}->{val}\n"; + + # count sb_tb + $conf_ptr->{task_conf}->{num_sb_tb}->{val} = &count_num_tb_one_folder($formatted_spice_dir.$conf_ptr->{dir_path}->{sb_tb_dir_name}->{val}); + print "INFO: No. of SB testbenches = $conf_ptr->{task_conf}->{num_sb_tb}->{val}\n"; + + # count top_tb + $conf_ptr->{task_conf}->{num_top_tb}->{val} = &count_num_tb_one_folder($formatted_spice_dir.$conf_ptr->{dir_path}->{top_tb_dir_name}->{val}); + print "INFO: No. of Top-level testbench = $conf_ptr->{task_conf}->{num_top_tb}->{val}\n"; + + my ($toptb_sp_path) = &gen_fpga_spice_netlists_path($formatted_spice_dir.$conf_ptr->{dir_path}->{top_tb_dir_name}->{val}, $spice_netlist_prefix, $conf_ptr->{dir_path}->{top_tb_postfix}->{val}); + + if (("on" eq $opt_ptr->{parse_top_tb})&&(!(-e $toptb_sp_path))) { + die "ERROR: File($toptb_sp_path) does not exist!"; + } + + if ("on" eq $opt_ptr->{parse_pb_mux_tb}) { + $tb_dir = $formatted_spice_dir.$conf_ptr->{dir_path}->{pb_mux_tb_dir_name}->{val}; + $tb_names_ptr->{$benchmark}->{pb_mux_tb_names} = &get_tb_file_names($tb_dir); + } + + if ("on" eq $opt_ptr->{parse_cb_mux_tb}) { + # Search all the sp files matching the name + $tb_dir = $formatted_spice_dir.$conf_ptr->{dir_path}->{cb_mux_tb_dir_name}->{val}; + $tb_names_ptr->{$benchmark}->{cb_mux_tb_names} = &get_tb_file_names($tb_dir); + } + + if ("on" eq $opt_ptr->{parse_sb_mux_tb}) { + $tb_dir = $formatted_spice_dir.$conf_ptr->{dir_path}->{sb_mux_tb_dir_name}->{val}; + $tb_names_ptr->{$benchmark}->{sb_mux_tb_names} = &get_tb_file_names($tb_dir); + } + + if ("on" eq $opt_ptr->{parse_lut_tb}) { + # Search all the sp files matching the name + $tb_dir = $formatted_spice_dir.$conf_ptr->{dir_path}->{lut_tb_dir_name}->{val}; + $tb_names_ptr->{$benchmark}->{lut_tb_names} = &get_tb_file_names($tb_dir); + } + + # Special, if there is no hardlogic, this is comb circuit, we don't collect the information + if (0 == $conf_ptr->{task_conf}->{num_hardlogic_tb}->{val}) { + print "INFO: None DFF testbenches detected... This may caused by a combinational circuit!\n"; + } elsif ("on" eq $opt_ptr->{parse_hardlogic_tb}) { + # Search all the sp files matching the name + $tb_dir = $formatted_spice_dir.$conf_ptr->{dir_path}->{hardlogic_tb_dir_name}->{val}; + $tb_names_ptr->{$benchmark}->{hardlogic_tb_names} = &get_tb_file_names($tb_dir); + } + + if ("on" eq $opt_ptr->{parse_grid_tb}) { + # Search all the sp files matching the name + $tb_dir = $formatted_spice_dir.$conf_ptr->{dir_path}->{grid_tb_dir_name}->{val}; + $tb_names_ptr->{$benchmark}->{grid_tb_names} = &get_tb_file_names($tb_dir); + } + + if ("on" eq $opt_ptr->{parse_cb_tb}) { + # Search all the sp files matching the name + $tb_dir = $formatted_spice_dir.$conf_ptr->{dir_path}->{cb_tb_dir_name}->{val}; + $tb_names_ptr->{$benchmark}->{cb_tb_names} = &get_tb_file_names($tb_dir); + } + + if ("on" eq $opt_ptr->{parse_sb_tb}) { + # Search all the sp files matching the name + $tb_dir = $formatted_spice_dir.$conf_ptr->{dir_path}->{sb_tb_dir_name}->{val}; + $tb_names_ptr->{$benchmark}->{sb_tb_names} = &get_tb_file_names($tb_dir); + } + + + return; +} + +sub parse_one_fpga_spice_task_results($ $ $) { + my ($benchmark, $spice_netlist_prefix, $spice_dir) = @_; + my ($formatted_spice_dir) = &format_dir_path($spice_dir); + my ($shell_script_path) = $formatted_spice_dir.$conf_ptr->{dir_path}->{shell_script_name}->{val}; + my ($itb, $mt_file_path, $lis_file_path); + + &auto_check_tb_num($benchmark, $spice_netlist_prefix, $spice_dir); + + if ("on" eq $opt_ptr->{parse_top_tb}) { + my ($top_mt_path) = &gen_fpga_spice_measure_results_path($spice_dir, $spice_netlist_prefix,$conf_ptr->{dir_path}->{top_tb_postfix}->{val}); + my ($top_lis_path) = ($top_mt_path); + $top_lis_path =~ s/\.mt0$/.lis/; + &parse_one_fpga_spice_task_one_tb_results($benchmark,"top_tb", $top_lis_path, $top_mt_path, $conf_ptr->{csv_tags}->{top_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{top_tb_dynamic_power_tags}->{val}); + } + + if ("on" eq $opt_ptr->{parse_pb_mux_tb}) { + # generate measure results paths + @pb_mux_tb_names = split (',', $tb_names_ptr->{$benchmark}->{pb_mux_tb_names}); + foreach my $tb_sp_filename (@pb_mux_tb_names) { + $mt_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); + $lis_file_path = $mt_file_path; + $lis_file_path =~ s/\.mt0$/.lis/; + &parse_one_fpga_spice_task_one_tb_results($benchmark,"pb_mux_tb", $lis_file_path, $mt_file_path, $conf_ptr->{csv_tags}->{pb_mux_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{pb_mux_tb_dynamic_power_tags}->{val}); + } + } + + if ("on" eq $opt_ptr->{parse_cb_mux_tb}) { + # generate measure results paths + @cb_mux_tb_names = split (',', $tb_names_ptr->{$benchmark}->{cb_mux_tb_names}); + foreach my $tb_sp_filename (@cb_mux_tb_names) { + $mt_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); + $lis_file_path = $mt_file_path; + $lis_file_path =~ s/\.mt0$/.lis/; + &parse_one_fpga_spice_task_one_tb_results($benchmark,"cb_mux_tb", $lis_file_path, $mt_file_path, $conf_ptr->{csv_tags}->{cb_mux_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{cb_mux_tb_dynamic_power_tags}->{val}); + } + } + + if ("on" eq $opt_ptr->{parse_sb_mux_tb}) { + # generate measure results paths + @sb_mux_tb_names = split (',', $tb_names_ptr->{$benchmark}->{sb_mux_tb_names}); + foreach my $tb_sp_filename (@sb_mux_tb_names) { + $mt_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); + $lis_file_path = $mt_file_path; + $lis_file_path =~ s/\.mt0$/.lis/; + &parse_one_fpga_spice_task_one_tb_results($benchmark,"sb_mux_tb", $lis_file_path, $mt_file_path, $conf_ptr->{csv_tags}->{sb_mux_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{sb_mux_tb_dynamic_power_tags}->{val}); + } + } + + if ("on" eq $opt_ptr->{parse_lut_tb}) { + # generate measure results paths + @lut_tb_names = split (',', $tb_names_ptr->{$benchmark}->{lut_tb_names}); + foreach my $tb_sp_filename (@lut_tb_names) { + $mt_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); + $lis_file_path = $mt_file_path; + $lis_file_path =~ s/\.mt0$/.lis/; + &parse_one_fpga_spice_task_one_tb_results($benchmark,"lut_tb", $lis_file_path, $mt_file_path, $conf_ptr->{csv_tags}->{lut_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{lut_tb_dynamic_power_tags}->{val}); + } + } + + if (0 == $conf_ptr->{task_conf}->{num_hardlogic_tb}->{val}) { + &init_one_fpga_spice_task_one_tb_results($benchmark,"hardlogic_tb",$conf_ptr->{csv_tags}->{hardlogic_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{hardlogic_tb_dynamic_power_tags}->{val}); + } elsif ("on" eq $opt_ptr->{parse_hardlogic_tb}) { + # generate measure results paths + @hardlogic_tb_names = split (',', $tb_names_ptr->{$benchmark}->{hardlogic_tb_names}); + foreach my $tb_sp_filename (@hardlogic_tb_names) { + $mt_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); + $lis_file_path = $mt_file_path; + $lis_file_path =~ s/\.mt0$/.lis/; + &parse_one_fpga_spice_task_one_tb_results($benchmark,"hardlogic_tb", $lis_file_path, $mt_file_path, $conf_ptr->{csv_tags}->{hardlogic_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{hardlogic_tb_dynamic_power_tags}->{val}); + } + } + + if ("on" eq $opt_ptr->{parse_grid_tb}) { + # generate measure results paths + @grid_tb_names = split (',', $tb_names_ptr->{$benchmark}->{grid_tb_names}); + foreach my $tb_sp_filename (@grid_tb_names) { + $mt_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); + $lis_file_path = $mt_file_path; + $lis_file_path =~ s/\.mt0$/.lis/; + &parse_one_fpga_spice_task_one_tb_results($benchmark,"grid_tb", $lis_file_path, $mt_file_path, $conf_ptr->{csv_tags}->{grid_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{grid_tb_dynamic_power_tags}->{val}); + } + } + + if ("on" eq $opt_ptr->{parse_cb_tb}) { + # generate measure results paths + @cb_tb_names = split (',', $tb_names_ptr->{$benchmark}->{cb_tb_names}); + foreach my $tb_sp_filename (@cb_tb_names) { + $mt_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); + $lis_file_path = $mt_file_path; + $lis_file_path =~ s/\.mt0$/.lis/; + &parse_one_fpga_spice_task_one_tb_results($benchmark,"cb_tb", $lis_file_path, $mt_file_path, $conf_ptr->{csv_tags}->{cb_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{cb_tb_dynamic_power_tags}->{val}); + } + } + + if ("on" eq $opt_ptr->{parse_sb_tb}) { + # generate measure results paths + @sb_tb_names = split (',', $tb_names_ptr->{$benchmark}->{sb_tb_names}); + foreach my $tb_sp_filename (@sb_tb_names) { + $mt_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); + $lis_file_path = $mt_file_path; + $lis_file_path =~ s/\.mt0$/.lis/; + &parse_one_fpga_spice_task_one_tb_results($benchmark,"sb_tb", $lis_file_path, $mt_file_path, $conf_ptr->{csv_tags}->{sb_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{sb_tb_dynamic_power_tags}->{val}); + } + } + + return; +} + +# Run a fpga_spice_task +sub run_one_fpga_spice_task($ $ $) { + my ($benchmark, $spice_netlist_prefix, $spice_dir) = @_; + my ($formatted_spice_dir) = &format_dir_path($spice_dir); + my ($shell_script_path) = $formatted_spice_dir.$conf_ptr->{dir_path}->{shell_script_name}->{val}; + my ($itb, $ix, $iy, $dh, $tb_dir); + + # change to the spice_dir + chdir $spice_dir; + # Check all the SPICE netlists and shell scripts exist + + &auto_check_tb_num($benchmark, $spice_netlist_prefix, $spice_dir); + + if (!(-e $shell_script_path)) { + die "ERROR: File($shell_script_path) does not exist!"; + } + + # Call the shell script + print "INFO: Running shell script ($shell_script_path)...\n"; + `csh -cx 'source $shell_script_path'` + or die "ERROR: fail in executing $shell_script_path!\n"; + + # return to current dir + chdir $cwd; + + &check_one_fpga_spice_task_lis($benchmark, $spice_netlist_prefix, $spice_dir); + print "INFO: Check LIS file finished.\n"; + + return; +} + +sub parse_all_tasks_results() { + print "Parsing all the results...\n"; + foreach my $benchmark(@benchmark_names) { + if ("done" eq $task_status_ptr->{$benchmark}->{status}) { + print "Parsing simulation results for benchmark($benchmark)...\n"; + &parse_one_fpga_spice_task_results($benchmark,$benchmarks_ptr->{$benchmark}->{spice_netlist_prefix},$benchmarks_ptr->{$benchmark}->{spice_dir}); + } else { + die "ERROR: found unfinished tasks when try to parse results!\n"; + } + # Remove results to avoid storage overflow + #&remove_fpga_spice_results($benchmarks_ptr->{$benchmark}->{spice_dir}); + } +} + +# Multi-thread Running FPGA SPICE tasks +sub multi_thread_run_fpga_spice_tasks($) { + my ($num_threads) = @_; + + # Evaluate include threads ok + if (!(eval 'use threads; 1')) { + die "ERROR: cannot use threads package in Perl! Please check the installation of package...\n"; + } + # Lauch threads up to the limited number of threads number + if ($num_threads < 2) { + $num_threads = 2; + } + my ($num_thread_running) = (0); + + # Iterate until all the tasks has been assigned, finished + while (1 != &check_all_fpga_spice_tasks_done()) { + foreach my $benchmark(@benchmark_names) { + # Bypass finished job + if ("done" eq $task_status_ptr->{$benchmark}->{status}) { + next; + } + # Check running job + if ("running" eq $task_status_ptr->{$benchmark}->{status}) { + my ($thr_id) = ($task_status_ptr->{$benchmark}->{thread_id}); + if (!($thr_id)) { + die "INTERNAL ERROR: invalid thread_id for task: $benchmark!\n"; + } + # Check if there is any error + if ($thr_id->error()) { + die "ERROR: Task: $benchmark, Thread(ID:$thr_id) exit abnormally!\n"; + } + if ($thr_id->is_running()) { + $task_status_ptr->{$benchmark}->{status} = "running"; + } + if ($thr_id->is_joinable()) { + $num_thread_running--; + $thr_id->join(); # Join the thread results + # Update task status + $task_status_ptr->{$benchmark}->{status} = "done"; + print "INFO: task: $benchmark finished!\n"; + &print_tasks_status(); + } + next; + } + # If we reach the thread number limit, we have to wait... + if (($num_thread_running == $num_threads) + ||($num_thread_running > $num_threads)) { + next; + } + # Start a new thread for a waiting task + if ("wait" eq $task_status_ptr->{$benchmark}->{status}) { + # We try to start a new thread since there are still threads available + my ($thr_new) = (threads->create(\&run_one_fpga_spice_task, $benchmark,$benchmarks_ptr->{$benchmark}->{spice_netlist_prefix},$benchmarks_ptr->{$benchmark}->{spice_dir})); + if ($thr_new) { + print "INFO: a new thread for task (benchmark: $benchmark) is lauched!\n"; + # Update status + $task_status_ptr->{$benchmark}->{status} = "running"; + $task_status_ptr->{$benchmark}->{thread_id} = $thr_new; + $num_thread_running++; + &print_tasks_status(); + } else { + # Fail to create a new thread, wait... + print "INFO: fail to lauch a new thread for task (benchmark: $benchmark)!\n"; + } + } + } + } + &print_tasks_status(); + + # Parse_results + &parse_all_tasks_results(); +} + +# Single-thread mode Running FPGA SPICE tasks +sub single_thread_run_fpga_spice_tasks() { + # Iterate until all the tasks has been assigned, finished + while (1 != &check_all_fpga_spice_tasks_done()) { + foreach my $benchmark(@benchmark_names) { + # Bypass finished job + if ("done" eq $task_status_ptr->{$benchmark}->{status}) { + next; + } + &run_one_fpga_spice_task($benchmark,$benchmarks_ptr->{$benchmark}->{spice_netlist_prefix},$benchmarks_ptr->{$benchmark}->{spice_dir}); + &parse_one_fpga_spice_task_results($benchmark,$benchmarks_ptr->{$benchmark}->{spice_netlist_prefix},$benchmarks_ptr->{$benchmark}->{spice_dir}); + $task_status_ptr->{$benchmark}->{status} = "done"; + # Remove results to avoid storage overflow + &remove_fpga_spice_results($benchmarks_ptr->{$benchmark}->{spice_dir}); + } + } + # Parse_results + #&parse_all_tasks_results(); + return; +} + +# Plan to run tasks +sub plan_run_tasks() { + &init_tasks_status(); + + if (("on" eq $opt_ptr->{multi_thread}) + &&(1 < $opt_ptr->{multi_thread_val}) + &&(1 < ($#benchmark_names + 1))) { + &multi_thread_run_fpga_spice_tasks($opt_ptr->{multi_thread_val}); + } else { + if ("on" eq $opt_ptr->{multi_thread}) { + print "INFO: multi_thread is selected but only 1 processor can be used or 1 benchmark to run...\n"; + print "INFO: switch to single thread mode.\n"; + } + &single_thread_run_fpga_spice_tasks(); + } +} + +sub gen_csv_rpt_one_tb_one_case($ $ $ $ $) { + my ($RPTFH, $tbname_tag, $tb_leakage_tags, $tb_dynamic_tags, $case_tag) = @_; + my (@leakage_tags) = split('\|', $tb_leakage_tags); + my (@dynamic_tags) = split('\|', $tb_dynamic_tags); + + # Print Title line + print $RPTFH "Benchmark,SimElapseTime,SimPeakMemUsed,"; + foreach my $tag(@leakage_tags) { + print $RPTFH "$tag,"; + } + if ("off" eq $opt_ptr->{sim_leakage_power_only}) { + foreach my $tag(@dynamic_tags) { + print $RPTFH "$tag,"; + } + } + print $RPTFH "\n"; + foreach my $benchmark(@benchmark_names) { + print $RPTFH "$benchmark,"; + print $RPTFH "$rpt_ptr->{$benchmark}->{$tbname_tag}->{total_elapsed_time},"; + print $RPTFH "$rpt_ptr->{$benchmark}->{$tbname_tag}->{peak_mem_used},"; + foreach my $tag(@leakage_tags) { + print $RPTFH "$rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{$case_tag},"; + } + if ("off" eq $opt_ptr->{sim_leakage_power_only}) { + foreach my $tag(@dynamic_tags) { + print $RPTFH "$rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{$case_tag},"; + } + } + print $RPTFH "\n"; + } + return; +} + +sub gen_csv_rpt_one_case($ $) { + my ($RPTFH, $case_tag) = @_; + + print $RPTFH "Monte Carlo case tag of the results: $case_tag\n"; + + if ("on" eq $opt_ptr->{parse_pb_mux_tb}) { + print $RPTFH "***** pb_mux_tb Results Table *****\n"; + &gen_csv_rpt_one_tb_one_case($RPTFH, "pb_mux_tb", $conf_ptr->{csv_tags}->{pb_mux_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{pb_mux_tb_dynamic_power_tags}->{val}, $case_tag); + print $RPTFH "\n"; + } + + if ("on" eq $opt_ptr->{parse_cb_mux_tb}) { + print $RPTFH "***** cb_mux_tb Results Table *****\n"; + &gen_csv_rpt_one_tb_one_case($RPTFH, "cb_mux_tb", $conf_ptr->{csv_tags}->{cb_mux_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{cb_mux_tb_dynamic_power_tags}->{val}, $case_tag); + print $RPTFH "\n"; + } + + if ("on" eq $opt_ptr->{parse_sb_mux_tb}) { + print $RPTFH "***** sb_mux_tb Results Table *****\n"; + &gen_csv_rpt_one_tb_one_case($RPTFH, "sb_mux_tb", $conf_ptr->{csv_tags}->{sb_mux_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{sb_mux_tb_dynamic_power_tags}->{val}, $case_tag); + print $RPTFH "\n"; + } + + if ("on" eq $opt_ptr->{parse_lut_tb}) { + print $RPTFH "***** lut_tb Results Table *****\n"; + &gen_csv_rpt_one_tb_one_case($RPTFH, "lut_tb", $conf_ptr->{csv_tags}->{lut_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{lut_tb_dynamic_power_tags}->{val}, $case_tag); + print $RPTFH "\n"; + } + + if ("on" eq $opt_ptr->{parse_hardlogic_tb}) { + print $RPTFH "***** hardlogic_tb Results Table *****\n"; + &gen_csv_rpt_one_tb_one_case($RPTFH, "hardlogic_tb", $conf_ptr->{csv_tags}->{hardlogic_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{hardlogic_tb_dynamic_power_tags}->{val}, $case_tag); + print $RPTFH "\n"; + } + + if ("on" eq $opt_ptr->{parse_grid_tb}) { + print $RPTFH "***** grid_tb Results Table *****\n"; + &gen_csv_rpt_one_tb_one_case($RPTFH, "grid_tb", $conf_ptr->{csv_tags}->{grid_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{grid_tb_dynamic_power_tags}->{val}, $case_tag); + print $RPTFH "\n"; + } + + if ("on" eq $opt_ptr->{parse_cb_tb}) { + print $RPTFH "***** cb_tb Results Table *****\n"; + &gen_csv_rpt_one_tb_one_case($RPTFH, "cb_tb", $conf_ptr->{csv_tags}->{cb_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{cb_tb_dynamic_power_tags}->{val}, $case_tag); + print $RPTFH "\n"; + } + + if ("on" eq $opt_ptr->{parse_sb_tb}) { + print $RPTFH "***** sb_tb Results Table *****\n"; + &gen_csv_rpt_one_tb_one_case($RPTFH, "sb_tb", $conf_ptr->{csv_tags}->{sb_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{sb_tb_dynamic_power_tags}->{val}, $case_tag); + print $RPTFH "\n"; + } + + if ("on" eq $opt_ptr->{parse_top_tb}) { + print $RPTFH "***** top_tb Results Table *****\n"; + &gen_csv_rpt_one_tb_one_case($RPTFH, "top_tb", $conf_ptr->{csv_tags}->{top_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{top_tb_dynamic_power_tags}->{val}, $case_tag); + print $RPTFH "\n"; + } + + return; +} + +sub process_mc_data_one_tag($) { + my ($cur_mc_hash_ref) = @_; + + $cur_mc_hash_ref->{mc_total} = 0; + $cur_mc_hash_ref->{mc_avg} = "na"; + $cur_mc_hash_ref->{mc_max} = "na"; + $cur_mc_hash_ref->{mc_min} = "na"; + for (my $i = 1; + $i < $cur_mc_hash_ref->{mc_cnt} + 1; + $i++) { + $cur_mc_hash_ref->{mc_total} += $cur_mc_hash_ref->{"mc".$i}; + # Update max + if (("na" eq $cur_mc_hash_ref->{mc_max}) + ||($cur_mc_hash_ref->{mc_max} < $cur_mc_hash_ref->{"mc".$i})) { + $cur_mc_hash_ref->{mc_max} = $cur_mc_hash_ref->{"mc".$i}; + } + # Update min + if (("na" eq $cur_mc_hash_ref->{mc_min}) + ||($cur_mc_hash_ref->{mc_min} > $cur_mc_hash_ref->{"mc".$i})) { + $cur_mc_hash_ref->{mc_min} = $cur_mc_hash_ref->{"mc".$i}; + } + } + # Get average + if ( 0 < $cur_mc_hash_ref->{mc_cnt}) { + $cur_mc_hash_ref->{mc_avg} = $cur_mc_hash_ref->{mc_total} / $cur_mc_hash_ref->{mc_cnt}; + } + + return $cur_mc_hash_ref->{mc_cnt}; +} + +# Count the number of Monte Carlo simulations, +# and calculate the average, max and min +sub process_mc_data_one_tb($ $ $) { + my ($tbname_tag, $tb_leakage_tags, $tb_dynamic_tags) = @_; + my (@leakage_tags) = split('\|', $tb_leakage_tags); + my (@dynamic_tags) = split('\|', $tb_dynamic_tags); + my ($mc_cnt, $mc_cnt_temp) = (0, 0); + + # Check each benchmark + foreach my $benchmark(@benchmark_names) { + foreach my $tag(@leakage_tags) { + $mc_cnt_temp = &process_mc_data_one_tag($rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}); + if (0 == $mc_cnt_temp) { + print "Warning: zero results found in Monte Carlo simulations for $tag!\n"; + } + if (0 == $mc_cnt) { + $mc_cnt = $mc_cnt_temp; + } elsif ($mc_cnt != $mc_cnt_temp) { + print "Warning: Inconsistent Monte Carlo Counter for (Benchmark:$benchmark; Testbench: $tbname_tag, Tag:$tag)\n"; + } + } + + # Only do the next part when sim_leakage is disabled + if ("on" eq $opt_ptr->{sim_leakage_power_only}) { + next; + } + foreach my $tag(@dynamic_tags) { + $mc_cnt_temp = &process_mc_data_one_tag($rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}); + if (0 == $mc_cnt) { + $mc_cnt = $mc_cnt_temp; + } elsif ($mc_cnt != $mc_cnt_temp) { + print "Warning: Inconsistent Monte Carlo Counter for (Benchmark:$benchmark; Testbench: $tbname_tag, Tag:$tag)\n"; + } + } + } + return $mc_cnt; +} + + +sub process_mc_results() { + my ($mc_cnt) = (0); + + if ("on" eq $opt_ptr->{parse_pb_mux_tb}) { + $mc_cnt = + &process_mc_data_one_tb("pb_mux_tb", + $conf_ptr->{csv_tags}->{pb_mux_tb_leakage_power_tags}->{val}, + $conf_ptr->{csv_tags}->{pb_mux_tb_dynamic_power_tags}->{val}); + } + + if ("on" eq $opt_ptr->{parse_cb_mux_tb}) { + $mc_cnt = + &process_mc_data_one_tb("cb_mux_tb", + $conf_ptr->{csv_tags}->{cb_mux_tb_leakage_power_tags}->{val}, + $conf_ptr->{csv_tags}->{cb_mux_tb_dynamic_power_tags}->{val}); + } + + if ("on" eq $opt_ptr->{parse_sb_mux_tb}) { + $mc_cnt = + &process_mc_data_one_tb("sb_mux_tb", + $conf_ptr->{csv_tags}->{sb_mux_tb_leakage_power_tags}->{val}, + $conf_ptr->{csv_tags}->{sb_mux_tb_dynamic_power_tags}->{val}); + } + + if ("on" eq $opt_ptr->{parse_lut_tb}) { + $mc_cnt = + &process_mc_data_one_tb("lut_tb", + $conf_ptr->{csv_tags}->{lut_tb_leakage_power_tags}->{val}, + $conf_ptr->{csv_tags}->{lut_tb_dynamic_power_tags}->{val}); + } + + if ("on" eq $opt_ptr->{parse_hardlogic_tb}) { + $mc_cnt = + &process_mc_data_one_tb("hardlogic_tb", + $conf_ptr->{csv_tags}->{hardlogic_tb_leakage_power_tags}->{val}, + $conf_ptr->{csv_tags}->{hardlogic_tb_dynamic_power_tags}->{val}); + } + + if ("on" eq $opt_ptr->{parse_grid_tb}) { + $mc_cnt = + &process_mc_data_one_tb("grid_tb", + $conf_ptr->{csv_tags}->{grid_tb_leakage_power_tags}->{val}, + $conf_ptr->{csv_tags}->{grid_tb_dynamic_power_tags}->{val}); + } + + if ("on" eq $opt_ptr->{parse_cb_tb}) { + $mc_cnt = + &process_mc_data_one_tb("cb_tb", + $conf_ptr->{csv_tags}->{cb_tb_leakage_power_tags}->{val}, + $conf_ptr->{csv_tags}->{cb_tb_dynamic_power_tags}->{val}); + } + + if ("on" eq $opt_ptr->{parse_sb_tb}) { + $mc_cnt = + &process_mc_data_one_tb("sb_tb", + $conf_ptr->{csv_tags}->{sb_tb_leakage_power_tags}->{val}, + $conf_ptr->{csv_tags}->{sb_tb_dynamic_power_tags}->{val}); + } + + if ("on" eq $opt_ptr->{parse_top_tb}) { + $mc_cnt = + &process_mc_data_one_tb("top_tb", + $conf_ptr->{csv_tags}->{top_tb_leakage_power_tags}->{val}, + $conf_ptr->{csv_tags}->{top_tb_dynamic_power_tags}->{val}); + } + + return $mc_cnt; +} + +sub gen_csv_rpt($) { + my ($rpt_file) = @_; + my ($RPTFH) = FileHandle->new; + my ($mc_num) = (0); + + my ($rpt_dir_path, $rpt_filename) = &split_prog_path($rpt_file); + &generate_path($rpt_dir_path); + + if ($RPTFH->open("> $rpt_file")) { + print "INFO: print CVS report($rpt_file)...\n"; + } else { + die "ERROR: fail to create $rpt_file!\n"; + } + + if ("on" eq $opt_ptr->{monte_carlo}) { + # Preprocess the data + $mc_num = &process_mc_results(); + # Output starts + if ("simple_rpt" eq $opt_ptr->{monte_carlo_val}) { + &gen_csv_rpt_one_case($RPTFH, "mc_avg"); + &gen_csv_rpt_one_case($RPTFH, "mc_max"); + &gen_csv_rpt_one_case($RPTFH, "mc_min"); + } else { # Output full report + print $RPTFH "Number of Monte Carlo simulations: $mc_num\n\n"; + &gen_csv_rpt_one_case($RPTFH, "mc_avg"); + &gen_csv_rpt_one_case($RPTFH, "mc_max"); + &gen_csv_rpt_one_case($RPTFH, "mc_min"); + for (my $i = 1; $i < $mc_num + 1; $i++) { + &gen_csv_rpt_one_case($RPTFH, "mc".$i); + } + } + } else { + &gen_csv_rpt_one_case($RPTFH, "avg"); + } + + close($RPTFH); + return; +} + +# Main Program +sub main() { + &opts_read(); + &read_conf(); + &read_benchmarks(); + &check_fpga_spice(); + # Auto check the number tbs + if ("on" eq $opt_ptr->{parse_results_only}) { + &mark_all_fpga_spice_tasks_done(); + &parse_all_tasks_results(); + } else { + &plan_run_tasks(); + } + &gen_csv_rpt($opt_ptr->{rpt_val}); +} +&main(); +exit(0); diff --git a/fpga_flow/scripts/run_multi.pl b/fpga_flow/scripts/run_multi.pl new file mode 100644 index 000000000..193a449d2 --- /dev/null +++ b/fpga_flow/scripts/run_multi.pl @@ -0,0 +1,38 @@ +#!/usr/bin/perl -w +use strict; +#use Shell; + +my $i; + +sub main{ + for ($i=3;$i<7;$i++) { + my $pid = fork(); + if (0 == $pid) { + my $n = $i + 1; + return `perl fpga_flow.pl -conf ./configs/K$i\_N$n\_22nm_new.conf -benchmark ./benchmarks/circuits.txt -rpt K$i\_N$n\_22nm_new_full.csv -N $n -K $i`; + } + } + #for ($i=3;$i<7;$i++) { + # my $pid = fork(); + # if (0 == $pid) { + # my $n = $i + 1; + # return `perl fpga_flow.pl -conf ./configs/K$i\_N$n\_22nm.conf -benchmark ./benchmarks/circuits.txt -rpt K$i\_N$n\_22nm.csv -N $n -K $i`; + # } + #} + #for ($i=1;$i<7;$i++) { + # my $pid = fork(); + # if (0 == $pid) { + # return `perl fpga_flow.pl -conf ./configs/K3M2_N$i\_22nm.conf -benchmark ./benchmarks/circuits.txt -rpt K3M2_N$i\_22nm.csv -N $i -K 3`; + # } + #} + #for ($i=1;$i<11;$i++) { + # my $pid = fork(); + # if (0 == $pid) { + # return `perl fpga_flow.pl -conf ./configs/K6_N$i\_22nm.conf -benchmark ./benchmarks/circuits.txt -rpt K6_N$i\_22nm.csv -N $i -K 6`; + # } + #} + #wait(-1); +} + +&main(); + diff --git a/fpga_flow/vpr_fpga_spice_conf/sample.conf b/fpga_flow/vpr_fpga_spice_conf/sample.conf new file mode 100644 index 000000000..92d477f60 --- /dev/null +++ b/fpga_flow/vpr_fpga_spice_conf/sample.conf @@ -0,0 +1,68 @@ +[dir_path] +result_dir = results +shell_script_name = run_hspice_sim.sh +# dir names +pb_mux_tb_dir_name = pb_mux_tb +cb_mux_tb_dir_name = cb_mux_tb +sb_mux_tb_dir_name = sb_mux_tb +top_tb_dir_name = top_tb +grid_tb_dir_name = grid_tb +lut_tb_dir_name = lut_tb +hardlogic_tb_dir_name = hardlogic_tb +cb_tb_dir_name = cb_tb +sb_tb_dir_name = sb_tb +# Prefix +top_tb_prefix = +pb_mux_tb_prefix = _grid +cb_mux_tb_prefix = _cb +sb_mux_tb_prefix = _sb +lut_tb_prefix = _grid +hardlogic_tb_prefix = _grid +grid_tb_prefix = _grid +cb_tb_prefix = _cb +sb_tb_prefix = _sb +# Postfix +top_tb_postfix = _top.sp +pb_mux_tb_postfix = _pbmux_testbench.sp +cb_mux_tb_postfix = _cbmux_testbench.sp +sb_mux_tb_postfix = _sbmux_testbench.sp +lut_tb_postfix = _lut_testbench.sp +hardlogic_tb_postfix = _hardlogic_testbench.sp +grid_tb_postfix = _grid_testbench.sp +cb_tb_postfix = _cb_testbench.sp +sb_tb_postfix = _sb_testbench.sp + +[task_conf] +auto_check = on +num_pb_mux_tb = +num_cb_mux_tb = +num_sb_mux_tb = +num_lut_mux_tb = +num_hardlogic_tb = +num_grid_mux_tb = +num_top_tb = +num_cb_tb = +num_sb_tb = + +[csv_tags] +#top_tb_leakage_power_tags = leakage_power_sram_local_routing|leakage_power_sram_luts|leakage_power_sram_cbs|leakage_power_sram_sbs|leakage_power_io|leakage_power_local_interc|total_leakage_power_lut5|total_leakage_power_lut6|total_leakage_power_dff|leakage_power_cbs|leakage_power_sbs +top_tb_leakage_power_tags = leakage_power_sram_local_routing|leakage_power_sram_luts|leakage_power_sram_cbs|leakage_power_sram_sbs|leakage_power_local_interc|total_leakage_power_lut6|total_leakage_power_dff|leakage_power_cbs|leakage_power_sbs +#top_tb_dynamic_power_tags = energy_per_cycle_sram_local_routing|energy_per_cycle_sram_luts|energy_per_cycle_sram_cbs|energy_per_cycle_sram_sbs|energy_per_cycle_io|energy_per_cycle_local_routing|total_energy_per_cycle_lut5|total_energy_per_cycle_lut6|total_energy_per_cycle_dff|energy_per_cycle_cbs|energy_per_cycle_sbs +top_tb_dynamic_power_tags = energy_per_cycle_sram_local_routing|energy_per_cycle_sram_luts|energy_per_cycle_sram_cbs|energy_per_cycle_sram_sbs|energy_per_cycle_local_routing|total_energy_per_cycle_lut6|total_energy_per_cycle_dff|energy_per_cycle_cbs|energy_per_cycle_sbs #|crit_path_delay +pb_mux_tb_leakage_power_tags = total_leakage_srams|total_leakage_power_pb_mux +cb_mux_tb_leakage_power_tags = total_leakage_srams|total_leakage_power_cb_mux +sb_mux_tb_leakage_power_tags = total_leakage_srams|total_leakage_power_sb_mux +pb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams|total_energy_per_cycle_pb_mux +cb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams|total_energy_per_cycle_cb_mux +sb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams|total_energy_per_cycle_sb_mux +lut_tb_leakage_power_tags = leakage_power_sram_luts|total_leakage_power_lut6 +lut_tb_dynamic_power_tags = energy_per_cycle_sram_luts|total_energy_per_cycle_lut6 +hardlogic_tb_leakage_power_tags = total_leakage_power_dff +hardlogic_tb_dynamic_power_tags = total_energy_per_cycle_dff +grid_tb_leakage_power_tags = leakage_power_sram_local_routing|leakage_power_sram_luts|leakage_power_local_routing|total_leakage_power_lut6|total_leakage_power_dff +grid_tb_dynamic_power_tags = total_energy_per_cycle_sram_local_routing|total_energy_per_cycle_sram_luts|total_energy_per_cycle_local_routing|total_energy_per_cycle_lut6|total_energy_per_cycle_dff +cb_tb_leakage_power_tags = leakage_power_cb|leakage_power_sram_cb +cb_tb_dynamic_power_tags = energy_per_cycle_cb|energy_per_cycle_sram_cb +sb_tb_leakage_power_tags = leakage_power_sb|leakage_power_sram_sb +sb_tb_dynamic_power_tags = energy_per_cycle_sb|energy_per_cycle_sram_sb + diff --git a/fpga_flow/vpr_fpga_spice_testbench_study.sh b/fpga_flow/vpr_fpga_spice_testbench_study.sh new file mode 100644 index 000000000..0a3d19b00 --- /dev/null +++ b/fpga_flow/vpr_fpga_spice_testbench_study.sh @@ -0,0 +1,23 @@ +# Make sure a clear start + +# Sweep Corner Cases +set corner_list = (TT) +#set corner_list = (TT FF SS MC) + +foreach j ($corner_list) + #rm -rf ./results + cd ./scripts + + if ($j == MC) then + set mc_opt = (-monte_carlo detail_rpt) + else + set mc_opt = () + endif + + perl fpga_flow.pl -conf ../configs/fpga_spice/k6_N10_sram_tsmc40nm_$j\.conf -benchmark ../benchmarks/fpga_spice_bench.txt -rpt ../csv_rpts/fpga_spice/k6_N10_sram_tsmc40nm_bench_$j\.csv -N 10 -K 6 -power -remove_designs -multi_thread 1 -vpr_fpga_spice ../vpr_fpga_spice_task_lists/k6_N10_sram_tsmc40nm -vpr_fpga_spice_rename_illegal_port -vpr_fpga_spice_sim_mt_num 16 -vpr_fpga_spice_print_top_tb #-vpr_fpga_spice_parasitic_net_estimation_off #-vpr_fpga_spice_leakage_only -vpr_fpga_spice_print_component_tb -vpr_fpga_spice_print_grid_tb + + perl run_fpga_spice.pl -conf ../vpr_fpga_spice_conf/sample.conf -task ../vpr_fpga_spice_task_lists/k6_N10_sram_tsmc40nm_standard.txt -rpt ../vpr_fpga_spice_csv_rpts/k6_N10_sram_tsmc40_spice_bench_$j\.csv $mc_opt -parse_top_tb -multi_thread 6 #-parse_pb_mux_tb -parse_cb_mux_tb -parse_sb_mux_tb -parse_lut_tb -parse_hardlogic_tb -parse_grid_tb -parse_cb_tb -parse_sb_tb + + cd .. + +end diff --git a/tangxifan-eda-tools b/tangxifan-eda-tools deleted file mode 160000 index 2d51da57b..000000000 --- a/tangxifan-eda-tools +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 2d51da57b826d6984fd3141c1b36fd64d63c2256 diff --git a/vpr7_rram/Makefile b/vpr7_rram/Makefile new file mode 100755 index 000000000..ba23931e3 --- /dev/null +++ b/vpr7_rram/Makefile @@ -0,0 +1,44 @@ +##################################################################### +# Makefile to build CAD tools in Verilog-to-Routing (VTR) Framework # +##################################################################### + +SUBDIRS = vpr libarchfpga pcre printhandler + +all: notifications subdirs + +subdirs: $(SUBDIRS) + +$(SUBDIRS): + @ $(MAKE) -C $@ --no-print-directory + +notifications: +# checks if required packages are installed, and notifies the user if not + @ if cat /etc/issue | grep Ubuntu -c >>/dev/null; then if ! dpkg -l | grep exuberant-ctags -c >>/dev/null; then echo "\n\n\n\n***************************************************************\n* Required package 'ctags' not found. *\n* Type 'make packages' to install all packages, or *\n* 'sudo apt-get install exuberant-ctags' to install manually. *\n***************************************************************\n\n\n\n"; fi; fi + @ if cat /etc/issue | grep Ubuntu -c >>/dev/null; then if ! dpkg -l | grep bison -c >>/dev/null; then echo "\n\n\n\n*****************************************************\n* Required package 'bison' not found. *\n* Type 'make packages' to install all packages, or *\n* 'sudo apt-get install bison' to install manually. *\n*****************************************************\n\n\n\n"; fi; fi + @ if cat /etc/issue | grep Ubuntu -c >>/dev/null; then if ! dpkg -l | grep flex -c >>/dev/null; then echo "\n\n\n\n*****************************************************\n* Required package 'flex' not found. *\n* Type 'make packages' to install all packages, or *\n* 'sudo apt-get install flex' to install manually. *\n*****************************************************\n\n\n\n"; fi; fi + @ if cat /etc/issue | grep Ubuntu -c >>/dev/null; then if ! dpkg -l | grep g++ -c >>/dev/null; then echo "\n\n\n\n*****************************************************\n* Required package 'g++' not found. * \n* Type 'make packages' to install all packages, or *\n* 'sudo apt-get install g++' to install manually. *\n*****************************************************\n\n\n\n"; fi; fi + +packages: +# checks if required packages are installed, and installs them if not + @ if cat /etc/issue | grep Ubuntu -c >>/dev/null; then if ! dpkg -l | grep exuberant-ctags -c >>/dev/null; then sudo apt-get install exuberant-ctags; fi; fi + @ if cat /etc/issue | grep Ubuntu -c >>/dev/null; then if ! dpkg -l | grep bison -c >>/dev/null; then sudo apt-get install bison; fi; fi + @ if cat /etc/issue | grep Ubuntu -c >>/dev/null; then if ! dpkg -l | grep flex -c >>/dev/null; then sudo apt-get install flex; fi; fi + @ if cat /etc/issue | grep Ubuntu -c >>/dev/null; then if ! dpkg -l | grep g++ -c >>/dev/null; then sudo apt-get install g++; fi; fi + @ cd vpr && make packages + +vpr: libarchfpga + +libarchfpga: printhandler + +printhandler: pcre + +clean: + @ cd vpr && make clean + @ cd libarchfpga && make clean + @ cd printhandler && make clean + @ cd pcre && make clean + +clean_vpr: + @ cd vpr && make clean + +.PHONY: packages subdirs $(SUBDIRS) diff --git a/vpr7_rram/libarchfpga/Makefile b/vpr7_rram/libarchfpga/Makefile new file mode 100644 index 000000000..457066da5 --- /dev/null +++ b/vpr7_rram/libarchfpga/Makefile @@ -0,0 +1,64 @@ +################################ MAKEFILE OPTIONS #################################### + +# By default, libarchfpga's build type (debug/release) is inherited from VPR's makefile. +# However, by uncommenting out the line BUILD_TYPE = debug, you can override this +# and set libarchfpga's build type independently. + +# BUILD_TYPE = release + +# (can be debug or release) + +############################################################################################# + +CC = g++ +AR = ar + +WARN_FLAGS = -Wall -Wpointer-arith -Wcast-qual -D__USE_FIXED_PROTOTYPES__ -pedantic -Wshadow -Wcast-align -D_POSIX_SOURCE -Wno-write-strings +DEBUG_FLAGS = -g +OPT_FLAGS = -O3 +INC_FLAGS = -Iinclude -Ifpga_spice_include -I../printhandler/SRC/TIO_InputOutputHandlers +LIB_FLAGS = rcs + +EXE = read_arch + +FLAGS = $(INC_FLAGS) $(WARN_FLAGS) -MD -MP + +ifneq (,$(findstring release, $(BUILD_TYPE))) + FLAGS := $(FLAGS) $(OPT_FLAGS) +else # DEBUG build + FLAGS := $(FLAGS) $(DEBUG_FLAGS) +endif + +SRC = read_xml_mrfpga.c linkedlist.c read_xml_spice_util.c read_xml_spice.c read_xml_arch_file.c read_xml_util.c ezxml.c ReadLine.c util.c +OBJS = $(SRC:.c=.o) + +DEPS = $(OBJS:.o=.d) main.d + +# Standalone executable to test architecture reader +$(EXE): main.o libarchfpga.a + $(CC) main.o -o $(EXE) $(INC_FLAGS) -L. -lm -larchfpga + + +libarchfpga.a: $(OBJS) ../pcre/libpcre.a ../printhandler/libprinthandler.a + cp ../printhandler/libprinthandler.a $@ + ar rcs $@ $(OBJS) + +../pcre/libpcre.a: + @ cd ../pcre && make + +../printhandler/libprinthandler.a: + @ cd ../printhandler && make + +%.o: %.c + $(CC) $(FLAGS) -c $< -o $@ + +-include $(DEPS) + + + +clean : + @ rm -f libarchfpga.a + @ rm -f $(OBJS) $(OBJS:.o=.d) + @ rm -f read_arch + @ rm -f main.o main.d + diff --git a/vpr7_rram/libarchfpga/ReadLine.c b/vpr7_rram/libarchfpga/ReadLine.c new file mode 100644 index 000000000..e02444ef8 --- /dev/null +++ b/vpr7_rram/libarchfpga/ReadLine.c @@ -0,0 +1,189 @@ +#include +#include +#include +#include +#include "util.h" +#include "ReadLine.h" + +/* Pass in a pointer to a token list. Is freed and then set to null */ +void FreeTokens(INOUTP char ***TokensPtr) { + assert(*TokensPtr); + assert(**TokensPtr); + + free(**TokensPtr); /* Free the string data */ + free(*TokensPtr); /* Free token list */ + *TokensPtr = NULL; /* Invalidate pointer since mem is gone */ +} + +/* Returns number of tokens in list. Zero if null list */ +int CountTokens(INP char **Tokens) { + int count = 0; + + if (NULL == Tokens) { + return 0; + }; + while (Tokens[count]) { + ++count; + }; + return count; +} + +/* Reads in a single line from file, splits into tokens and allocates + * a list of tokens. Returns the an array of character arrays with the + * final item being marked by an empty string. + * Returns NULL on EOF + * NB: Token list is does as two allocations, one for pointer list + * and one for character array. Free what pointer points to and then + * free the pointer itself */ +char ** +ReadLineTokens(INOUTP FILE * InFile, INOUTP int *LineNum) { + + enum { + BUFFSIZE = 65536 + }; + /* This is much more than enough */ + char Buffer[BUFFSIZE]; /* Must match BUFFSIZE */ + char *Res; + char *Last; + char *Cur; + char *Dst; + char **Tokens; + int TokenCount; + int Len; + int CurToken; + boolean InToken; + + do { + /* Read the string */ + Res = fgets(Buffer, BUFFSIZE, InFile); + if (NULL == Res) { + if (feof(InFile)) { + return NULL; /* Return NULL on EOF */ + } else { + vpr_printf(TIO_MESSAGE_ERROR, "Unexpected error reading file\n"); + exit(1); + } + } + ++(*LineNum); + + /* Strip newline if any */ + Last = Buffer + strlen(Buffer); + if ((Last > Buffer) && ('\n' == Last[-1])) { + --Last; + } + if ((Last > Buffer) && ('\r' == Last[-1])) { + --Last; + } + + /* Handle continued lines */ + while ((Last > Buffer) && ('\\' == Last[-1])) { + /* Strip off the backslash */ + --Last; + + /* Read next line by giving pointer to null-char as start for next */ + Res = fgets(Last, (BUFFSIZE - (Last - Buffer)), InFile); + if (NULL == Res) { + if (feof(InFile)) { + return NULL; /* Return NULL on EOF */ + } else { + vpr_printf(TIO_MESSAGE_ERROR, + "Unexpected error reading file\n"); + exit(1); + } + } + ++(*LineNum); + + /* Strip newline */ + Last = Buffer + strlen(Buffer); + if ((Last > Buffer) && ('\n' == Last[-1])) { + --Last; + } + if ((Last > Buffer) && ('\r' == Last[-1])) { + --Last; + } + } + + /* Strip comment if any */ + Cur = Buffer; + while (Cur < Last) { + if ('#' == *Cur) { + Last = Cur; + break; + } + ++Cur; + } + + /* Count tokens and find size */ + assert(Last < (Buffer + BUFFSIZE)); + Len = 0; + TokenCount = 0; + Cur = Buffer; + InToken = FALSE; + while (Cur < Last) { + if (InToken) { + if ((' ' == *Cur) || ('\t' == *Cur)) { + InToken = FALSE; + } else { + ++Len; + } + } else { + if ((' ' != *Cur) && ('\t' != *Cur)) { + ++TokenCount; + ++Len; + InToken = TRUE; + } + } + ++Cur; /* Advance pointer */ + } + } while (0 == TokenCount); + + /* Find the size of mem to alloc. Use a contiguous block so is + * easy to deallocate */ + Len = (sizeof(char) * Len) + /* Length of actual data */ + (sizeof(char) * TokenCount); /* Null terminators */ + + /* Alloc the pointer list and data list. Count the final + * empty string we will use as list terminator */ + Tokens = (char **) my_malloc(sizeof(char *) * (TokenCount + 1)); + *Tokens = (char *) my_malloc(sizeof(char) * Len); + + /* Copy tokens to result */ + Cur = Buffer; + Dst = *Tokens; + InToken = FALSE; + CurToken = 0; + while (Cur < Last) { + if (InToken) { + if ((' ' == *Cur) || ('\t' == *Cur)) { + InToken = FALSE; + *Dst = '\0'; /* Null term token */ + ++Dst; + ++CurToken; + } else { + *Dst = *Cur; /* Copy char */ + ++Dst; + } + } else { + if ((' ' != *Cur) && ('\t' != *Cur)) { + Tokens[CurToken] = Dst; /* Set token start pointer */ + *Dst = *Cur; /* Copy char */ + ++Dst; + InToken = TRUE; + } + } + ++Cur; /* Advance pointer */ + } + if (InToken) { + *Dst = '\0'; /* Null term final token */ + ++Dst; + ++CurToken; + } + assert(CurToken == TokenCount); + + /* Set the final empty string entry */ + Tokens[CurToken] = NULL; + + /* Return the string list */ + return Tokens; +} + diff --git a/vpr7_rram/libarchfpga/arch/README.txt b/vpr7_rram/libarchfpga/arch/README.txt new file mode 100644 index 000000000..88e5886d9 --- /dev/null +++ b/vpr7_rram/libarchfpga/arch/README.txt @@ -0,0 +1,11 @@ +This directory contains sample architecture files that are used in testing +libarchfpga. In addition, the architecture files in this directory are used by +the regression testing facilities of Odin II. + +Please be sure to retain sample_arch.xml and update it with any changes that +are made to the libvpr library. + +Ken Kent +ken@unb.ca +06.18.2009 + diff --git a/vpr7_rram/libarchfpga/arch/mult_luts_arch.xml b/vpr7_rram/libarchfpga/arch/mult_luts_arch.xml new file mode 100644 index 000000000..69b3e5d7c --- /dev/null +++ b/vpr7_rram/libarchfpga/arch/mult_luts_arch.xml @@ -0,0 +1,716 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/vpr7_rram/libarchfpga/arch/sample_arch.xml b/vpr7_rram/libarchfpga/arch/sample_arch.xml new file mode 100644 index 000000000..31047be29 --- /dev/null +++ b/vpr7_rram/libarchfpga/arch/sample_arch.xml @@ -0,0 +1,815 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2.690e-10 + 2.690e-10 + 2.690e-10 + 2.690e-10 + 2.690e-10 + 2.690e-10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2.690e-10 + 2.690e-10 + 2.690e-10 + 2.690e-10 + 2.690e-10 + 2.690e-10 + + + + + 2.690e-10 + + + + + 1.690e-10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/vpr7_rram/libarchfpga/config_basic_arch.xml b/vpr7_rram/libarchfpga/config_basic_arch.xml new file mode 100644 index 000000000..9ebd135f0 --- /dev/null +++ b/vpr7_rram/libarchfpga/config_basic_arch.xml @@ -0,0 +1,27 @@ + + + + multiply72.v + + + + blif_all_soft + ./multiply72.blif + + + fpga_arch_models.xml + + + + + + + + + + + . + 1 + 1 + + diff --git a/vpr7_rram/libarchfpga/ctags_libarchfpga_src.sh b/vpr7_rram/libarchfpga/ctags_libarchfpga_src.sh new file mode 100644 index 000000000..572a82712 --- /dev/null +++ b/vpr7_rram/libarchfpga/ctags_libarchfpga_src.sh @@ -0,0 +1 @@ +ctags ./*.c ./*.h ./include/*.h diff --git a/vpr7_rram/libarchfpga/ezxml.c b/vpr7_rram/libarchfpga/ezxml.c new file mode 100644 index 000000000..46cce5535 --- /dev/null +++ b/vpr7_rram/libarchfpga/ezxml.c @@ -0,0 +1,1285 @@ +/* ezxml.c + * + * Copyright 2004-2006 Aaron Voisine + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef EZXML_NOMMAP +#define EZXML_NOMMAP +#endif /* EXXML_NOMMAP */ + +/* Ted Campbell, Aug 14 2007 */ +#if defined(WIN32) || defined(_WIN32) +#include +#endif /* WIN32 */ + +#include +#include +#include +#include +#include + +/* Ted Campbell, Aug 14 2007 */ +#if !defined(WIN32) && !defined(_WIN32) +#include +#endif + +#include +#ifndef EZXML_NOMMAP +#include +#endif /* EZXML_NOMMAP */ +#include +#include "ezxml.h" + +/* Ted Campbell, Aug 14, 2007 */ +#include "util.h" + +/* Ted Campbell, Aug 14, 2007 */ +#if defined(WIN32) || defined(_WIN32) +#define snprintf _snprintf +#define open _open +#define read _read +#define write _write +#define close _close +#endif /* WIN32 */ + +#define EZXML_WS "\t\r\n " /* whitespace */ +char *EZXML_NIL[] = { NULL }; /* empty, null terminated array of strings */ + +static ezxml_t ezxml_vget(ezxml_t xml, va_list ap); +static char *ezxml_decode(char *s, char **ent, char t); +static void ezxml_open_tag(ezxml_root_t root, int line, char *name, char **attr); +static void ezxml_char_content(ezxml_root_t root, char *s, + size_t len, char t); +static ezxml_t ezxml_close_tag(ezxml_root_t root, char *name, char *s); +static int ezxml_ent_ok(char *name, char *s, char **ent); +static void ezxml_proc_inst(ezxml_root_t root, char *s, size_t len); +static short ezxml_internal_dtd(ezxml_root_t root, char *s, + size_t len); +static char *ezxml_str2utf8(char **s, size_t * len); +static void ezxml_free_attr(char **attr); +static char *ezxml_ampencode(const char *s, size_t len, char **dst, + size_t * dlen, size_t * max, short a); +static char *ezxml_toxml_r(ezxml_t xml, char **s, size_t * len, size_t * max, + size_t start, char ***attr); + +/* returns the first child tag with the given name or NULL if not found */ +ezxml_t ezxml_child(ezxml_t xml, const char *name) { + xml = (xml) ? xml->child : NULL; + while (xml && strcmp(name, xml->name)) + xml = xml->sibling; + return xml; +} + +/* returns the Nth tag with the same name in the same subsection or NULL if not */ +/* found */ +ezxml_t ezxml_idx(ezxml_t xml, int idx) { + for (; xml && idx; idx--) + xml = xml->next; + return xml; +} + +/* returns the value of the requested tag attribute or NULL if not found */ +const char * +ezxml_attr(ezxml_t xml, const char *attr) { + int i = 0, j = 1; + ezxml_root_t root = (ezxml_root_t) xml; + + if (!xml || !xml->attr) + return NULL; + while (xml->attr[i] && strcmp(attr, xml->attr[i])) + i += 2; + if (xml->attr[i]) + return xml->attr[i + 1]; /* found attribute */ + + while (root->xml.parent) + root = (ezxml_root_t) root->xml.parent; /* root tag */ + for (i = 0; root->attr[i] && strcmp(xml->name, root->attr[i][0]); i++) + ; + if (!root->attr[i]) + return NULL; /* no matching default attributes */ + while (root->attr[i][j] && strcmp(attr, root->attr[i][j])) + j += 3; + return (root->attr[i][j]) ? root->attr[i][j + 1] : NULL; /* found default */ +} + +/* same as ezxml_get but takes an already initialized va_list */ +ezxml_t ezxml_vget(ezxml_t xml, va_list ap) { + char *name = va_arg(ap, char *); + int idx = -1; + + if (name && *name) { + idx = va_arg(ap, int); + + xml = ezxml_child(xml, name); + } + return (idx < 0) ? xml : ezxml_vget(ezxml_idx(xml, idx), ap); +} + +/* Traverses the xml tree to retrieve a specific subtag. Takes a variable */ +/* length list of tag names and indexes. The argument list must be terminated */ +/* by either an index of -1 or an empty string tag name. Example: */ +/* title = ezxml_get(library, "shelf", 0, "book", 2, "title", -1); */ +/* This retrieves the title of the 3rd book on the 1st shelf of library. */ +/* Returns NULL if not found. */ +ezxml_t ezxml_get(ezxml_t xml, ...) { + va_list ap; + ezxml_t r; + + va_start(ap, xml); + r = ezxml_vget(xml, ap); + va_end(ap); + return r; +} + +/* returns a null terminated array of processing instructions for the given */ +/* target */ +char ** +ezxml_pi(ezxml_t xml, const char *target) { + ezxml_root_t root = (ezxml_root_t) xml; + int i = 0; + + if (!root) + return EZXML_NIL; + while (root->xml.parent) + root = (ezxml_root_t) root->xml.parent; /* root tag */ + while (root->pi[i] && strcmp(target, root->pi[i][0])) + i++; /* find target */ + return ((root->pi[i]) ? root->pi[i] + 1 : EZXML_NIL); +} + +/* set an error string and return root */ +static ezxml_t ezxml_err(ezxml_root_t root, char *s, const char *err, ...) { + va_list ap; + int line = 1; + char *t, fmt[EZXML_ERRL]; + + for (t = root->s; t < s; t++) + if (*t == '\n') + line++; + snprintf(fmt, EZXML_ERRL, "[error near line %d]: %s", line, err); + + va_start(ap, err); + vsnprintf(root->err, EZXML_ERRL, fmt, ap); + va_end(ap); + + return &root->xml; +} + +/* Recursively decodes entity and character references and normalizes new lines */ +/* ent is a null terminated array of alternating entity names and values. set t */ +/* to '&' for general entity decoding, '%' for parameter entity decoding, 'c' */ +/* for cdata sections, ' ' for attribute normalization, or '*' for non-cdata */ +/* attribute normalization. Returns s, or if the decoded string is longer than */ +/* s, returns a malloced string that must be freed. */ +/* Jason Luu June 22, 2010, Added line number support */ +static char * +ezxml_decode(char *s, char **ent, char t) { + char *e, *r = s, *m = s; + long b, c, d, l; + + for (; *s; s++) { /* normalize line endings */ + while (*s == '\r') { + *(s++) = '\n'; + if (*s == '\n') { + memmove(s, (s + 1), strlen(s)); + } + } + } + + for (s = r;;) { + while (*s && *s != '&' && (*s != '%' || t != '%') && !isspace(*s)) + s++; + if (!*s) + break; + else if (t != 'c' && !strncmp(s, "&#", 2)) { /* character reference */ + if (s[2] == 'x') + c = strtol(s + 3, &e, 16); /* base 16 */ + else + c = strtol(s + 2, &e, 10); /* base 10 */ + if (!c || *e != ';') { + s++; + continue; + } + /* not a character ref */ + if (c < 0x80) + *(s++) = (char) c; /* US-ASCII subset */ + else { /* multi-byte UTF-8 sequence */ + for (b = 0, d = c; d; d /= 2) + b++; /* number of bits in c */ + b = (b - 2) / 5; /* number of bytes in payload */ + *(s++) = (char)((0xFF << (7 - b)) | (c >> (6 * b))); /* head */ + while (b) + *(s++) = 0x80 | ((c >> (6 * --b)) & 0x3F); /* payload */ + } + + memmove(s, strchr(s, ';') + 1, strlen(strchr(s, ';'))); + } else if ((*s == '&' && (t == '&' || t == ' ' || t == '*')) + || (*s == '%' && t == '%')) { /* entity reference */ + for (b = 0; ent[b] && strncmp(s + 1, ent[b], strlen(ent[b])); b += + 2) + ; /* find entity in entity list */ + + if (ent[b++]) { /* found a match */ + if ((c = strlen(ent[b])) - 1 > (e = strchr(s, ';')) - s) { + l = (d = (s - r)) + c + strlen(e); /* new length */ + r = (r == m) ? strcpy((char*)malloc(l), r) : (char*)realloc(r, l); + e = strchr((s = r + d), ';'); /* fix up pointers */ + } + + memmove(s + c, e + 1, strlen(e)); /* shift rest of string */ + strncpy(s, ent[b], c); /* copy in replacement text */ + } else + s++; /* not a known entity */ + } else if ((t == ' ' || t == '*') && isspace(*s)) + *(s++) = ' '; + else + s++; /* no decoding needed */ + } + + if (t == '*') { /* normalize spaces for non-cdata attributes */ + for (s = r; *s; s++) { + /* Jason Luu, Aug 29, 2007. Removed assignment in conditional statement */ + l = strspn(s, " "); + if (l) + memmove(s, s + l, strlen(s + l) + 1); + while (*s && *s != ' ') + s++; + } + if (--s >= r && *s == ' ') + *s = '\0'; /* trim any trailing space */ + } + return r; +} + +/* called when parser finds start of new tag */ +/* Jason Luu June 22, 2010, Added line number support */ +static void ezxml_open_tag(ezxml_root_t root, int line, char *name, char **attr) { + ezxml_t xml = root->cur; + + if (xml->name) + xml = ezxml_add_child(xml, name, strlen(xml->txt)); + else + xml->name = name; /* first open tag */ + xml->line = line; + xml->attr = attr; + + root->cur = xml; /* update tag insertion point */ +} + +/* called when parser finds character content between open and closing tag */ +/* Jason Luu June 22, 2010, Added line number support */ +static void ezxml_char_content(ezxml_root_t root, char *s, + size_t len, char t) { + ezxml_t xml = root->cur; + char *m = s; + size_t l; + + if (!xml || !xml->name || !len) + return; /* sanity check */ + + s[len] = '\0'; /* null terminate text (calling functions anticipate this) */ + len = strlen(s = ezxml_decode(s, root->ent, t)) + 1; + + if (!*(xml->txt)) + xml->txt = s; /* initial character content */ + else { /* allocate our own memory and make a copy */ + xml->txt = (xml->flags & EZXML_TXTM) /* allocate some space */ + ? (char*)realloc(xml->txt, (l = strlen(xml->txt)) + len) : strcpy((char*)malloc((l = + strlen(xml->txt)) + len), xml->txt); + strcpy(xml->txt + l, s); /* add new char content */ + if (s != m) + free(s); /* free s if it was malloced by ezxml_decode() */ + } + + if (xml->txt != m) + ezxml_set_flag(xml, EZXML_TXTM); +} + +/* called when parser finds closing tag */ +static ezxml_t ezxml_close_tag(ezxml_root_t root, char *name, char *s) { + if (!root->cur || !root->cur->name || strcmp(name, root->cur->name)) + return ezxml_err(root, s, "unexpected closing tag ", name); + + root->cur = root->cur->parent; + return NULL; +} + +/* checks for circular entity references, returns non-zero if no circular */ +/* references are found, zero otherwise */ +static int ezxml_ent_ok(char *name, char *s, char **ent) { + int i; + + for (;; s++) { + while (*s && *s != '&') + s++; /* find next entity reference */ + if (!*s) + return 1; + if (!strncmp(s + 1, name, strlen(name))) + return 0; /* circular ref. */ + for (i = 0; ent[i] && strncmp(ent[i], s + 1, strlen(ent[i])); i += 2) + ; + if (ent[i] && !ezxml_ent_ok(name, ent[i + 1], ent)) + return 0; + } +} + +/* called when the parser finds a processing instruction */ +static void ezxml_proc_inst(ezxml_root_t root, char *s, size_t len) { + int i = 0, j = 1; + char *target = s; + + s[len] = '\0'; /* null terminate instruction */ + if (*(s += strcspn(s, EZXML_WS))) { + *s = '\0'; /* null terminate target */ + s += strspn(s + 1, EZXML_WS) + 1; /* skip whitespace after target */ + } + + if (!strcmp(target, "xml")) { /* */ + /* Jason Luu, Aug 29, 2007. Removed assignment in conditional statement */ + s = strstr(s, "standalone"); + if (s && !strncmp(s + strspn(s + 10, EZXML_WS "='\"") + 10, "yes", 3)) + root->standalone = 1; + return; + } + + if (!root->pi[0]) + *(root->pi = (char***)malloc(sizeof(char **))) = NULL; /*first pi */ + + while (root->pi[i] && strcmp(target, root->pi[i][0])) + i++; /* find target */ + if (!root->pi[i]) { /* new target */ + root->pi = (char***)realloc(root->pi, sizeof(char **) * (i + 2)); + root->pi[i] = (char**)malloc(sizeof(char *) * 3); + root->pi[i][0] = target; + root->pi[i][1] = (char *) (root->pi[i + 1] = NULL); /* terminate pi list */ + /* Ted Campbell, Aug 14, 2007. Changed to use 'my_strdup' */ + root->pi[i][2] = my_strdup(""); /* empty document position list */ + } + + while (root->pi[i][j]) + j++; /* find end of instruction list for this target */ + root->pi[i] = (char**)realloc(root->pi[i], sizeof(char *) * (j + 3)); + root->pi[i][j + 2] = (char*)realloc(root->pi[i][j + 1], j + 1); + strcpy(root->pi[i][j + 2] + j - 1, (root->xml.name) ? ">" : "<"); + root->pi[i][j + 1] = NULL; /* null terminate pi list for this target */ + root->pi[i][j] = s; /* set instruction */ +} + +/* called when the parser finds an internal doctype subset */ +/* Jason Luu June 22, 2010, Added line number support */ +static short ezxml_internal_dtd(ezxml_root_t root, char *s, + size_t len) { + char q, *c, *t, *n = NULL, *v, **ent, **pe; + char temp[] = {'\0','\0','\0'}; + int i, j; + + pe = (char**)memcpy(malloc(sizeof(EZXML_NIL)), EZXML_NIL, sizeof(EZXML_NIL)); + + for (s[len] = '\0'; s;) { + while (*s && *s != '<' && *s != '%') + s++; /* find next declaration */ + + if (!*s) + break; + else if (!strncmp(s, "'); + continue; + } + + for (i = 0, ent = (*c == '%') ? pe : root->ent; ent[i]; i++) + ; + ent = (char**)realloc(ent, (i + 3) * sizeof(char *)); /* space for next ent */ + if (*c == '%') + pe = ent; + else + root->ent = ent; + + *(++s) = '\0'; /* null terminate name */ + /* Jason Luu, Aug 29, 2007. Removed assignment in conditional statement */ + s = strchr(v, q); + if (s) + *(s++) = '\0'; /* null terminate value */ + ent[i + 1] = ezxml_decode(v, pe, '%'); /* set value */ + ent[i + 2] = NULL; /* null terminate entity list */ + if (!ezxml_ent_ok(n, ent[i + 1], ent)) { /* circular reference */ + if (ent[i + 1] != v) + free(ent[i + 1]); + ezxml_err(root, v, "circular entity declaration &%s", n); + break; + } else + ent[i] = n; /* set entity name */ + } else if (!strncmp(s, "")) == '>') + continue; + else + *s = '\0'; /* null terminate tag name */ + for (i = 0; root->attr[i] && strcmp(n, root->attr[i][0]); i++) + ; + + ++s; + while (*(n = s + strspn(s, EZXML_WS)) && *n != '>') { + if (*(s = n + strcspn(n, EZXML_WS))) + *s = '\0'; /* attr name */ + else { + ezxml_err(root, t, "malformed ") - 1; + if (*c == ' ') + continue; /* cdata is default, nothing to do */ + v = NULL; + } else { + /* Jason Luu, Aug 29, 2007. Removed assignment in conditional statement */ + s = strchr(v = s + 1, *s); + if ((*s == '"' || *s == '\'') && /* default value */ + s) + *s = '\0'; + else { + ezxml_err(root, t, "malformed attr[i]) { /* new tag name */ + root->attr = + (!i) ? (char***)malloc(2 * sizeof(char **)) : (char***)realloc( + root->attr, + (i + 2) * sizeof(char **)); + root->attr[i] = (char**)malloc(2 * sizeof(char *)); + root->attr[i][0] = t; /* set tag name */ + root->attr[i][1] = (char *) (root->attr[i + 1] = NULL); + } + + for (j = 1; root->attr[i][j]; j += 3) + ; /* find end of list */ + root->attr[i] = (char**)realloc(root->attr[i], + (j + 4) * sizeof(char *)); + + root->attr[i][j + 3] = NULL; /* null terminate list */ + root->attr[i][j + 2] = c; /* is it cdata? */ + root->attr[i][j + 1] = + (v) ? ezxml_decode(v, root->ent, *c) : NULL; + root->attr[i][j] = n; /* attribute name */ + + ++s; + } + } else if (!strncmp(s, ""); /* comments */ + } + else if (!strncmp(s, ""); + if (s) + ezxml_proc_inst(root, c, s++ - c); + } else if (*s == '<') + s = strchr(s, '>'); /* skip other declarations */ + else if (*(s++) == '%' && !root->standalone) + break; + } + + free(pe); + return !*root->err; +} + +/* Converts a UTF-16 string to UTF-8. Returns a new string that must be freed */ +/* or NULL if no conversion was needed. */ +static char * +ezxml_str2utf8(char **s, size_t * len) { + char *u; + size_t l = 0, sl, max = *len; + long c, d; + int b, be = (**s == '\xFE') ? 1 : (**s == '\xFF') ? 0 : -1; + + if (be == -1) + return NULL; /* not UTF-16 */ + + u = (char*)malloc(max); + for (sl = 2; sl < *len - 1; sl += 2) { + c = (be) ? (((*s)[sl] & 0xFF) << 8) | ((*s)[sl + 1] & 0xFF) /*UTF-16BE */ + : + (((*s)[sl + 1] & 0xFF) << 8) | ((*s)[sl] & 0xFF); /*UTF-16LE */ + if (c >= 0xD800 && c <= 0xDFFF && (sl += 2) < *len - 1) { /* high-half */ + d = (be) ? + (((*s)[sl] & 0xFF) << 8) | ((*s)[sl + 1] & 0xFF) : + (((*s)[sl + 1] & 0xFF) << 8) | ((*s)[sl] & 0xFF); + c = (((c & 0x3FF) << 10) | (d & 0x3FF)) + 0x10000; + } + + while (l + 6 > max) + u = (char*)realloc(u, max += EZXML_BUFSIZE); + if (c < 0x80) + u[l++] = (char)c; /* US-ASCII subset */ + else { /* multi-byte UTF-8 sequence */ + for (b = 0, d = c; d; d /= 2) + b++; /* bits in c */ + b = (b - 2) / 5; /* bytes in payload */ + u[l++] = (char)((0xFF << (7 - b)) | (c >> (6 * b))); /* head */ + while (b) + u[l++] = 0x80 | ((c >> (6 * --b)) & 0x3F); /* payload */ + } + } + return *s = (char*)realloc(u, *len = l); +} + +/* frees a tag attribute list */ +static void ezxml_free_attr(char **attr) { + int i = 0; + char *m; + + if (!attr || attr == EZXML_NIL) + return; /* nothing to free */ + while (attr[i]) + i += 2; /* find end of attribute list */ + m = attr[i + 1]; /* list of which names and values are malloced */ + for (i = 0; m[i]; i++) { + if (m[i] & EZXML_NAMEM) + free(attr[i * 2]); + if (m[i] & EZXML_TXTM) + free(attr[(i * 2) + 1]); + } + free(m); + free(attr); +} + +/* parse the given xml string and return an ezxml structure */ +/* Jason Luu June 22, 2010, Added line number support */ +ezxml_t ezxml_parse_str(char *s, size_t len) { + ezxml_root_t root = (ezxml_root_t) ezxml_new(0); + char q, e, *d, *temp, **attr, **a = NULL; /* initialize a to avoid compile warning */ + int l, i, j; + int line = 1; + + root->m = s; + if (!len) + return ezxml_err(root, NULL, "root tag missing"); + root->u = ezxml_str2utf8(&s, &len); /* convert utf-16 to utf-8 */ + root->e = (root->s = s) + len; /* record start and end of work area */ + + e = s[len - 1]; /* save end char */ + s[len - 1] = '\0'; /* turn end char into null terminator */ + + while (*s && *s != '<') + s++; /* find first tag */ + if (!*s) + return ezxml_err(root, s, "root tag missing"); + + for (;;) { + attr = (char **) EZXML_NIL; + d = ++s; + + if (isalpha(*s) || *s == '_' || *s == ':' || *s < '\0') { /* new tag */ + if (!root->cur) + return ezxml_err(root, d, "markup outside of root element"); + + s += strcspn(s, EZXML_WS "/>"); + while (isspace(*s)) { + if (*s == '\n') + line++; + *(s++) = '\0'; /* null terminate tag name */ + } + + if (*s && *s != '/' && *s != '>') { /* find tag in default attr list */ + /* Jason Luu, Aug 29, 2007. Removed assignment in conditional statement */ + a = root->attr[0]; + for (i = 0; a && strcmp(a[0], d); i++) { + a = root->attr[i]; + } + } + + for (l = 0; *s && *s != '/' && *s != '>'; l += 2) { /* new attrib */ + attr = (l) ? + (char**)realloc(attr, (l + 4) * sizeof(char *)) : + (char**)malloc(4 * sizeof(char *)); /* allocate space */ + attr[l + 3] = + (l) ? (char*)realloc(attr[l + 1], (l / 2) + 2) : (char*)malloc(2); /* mem for list of maloced vals */ + strcpy(attr[l + 3] + (l / 2), " "); /* value is not malloced */ + attr[l + 2] = NULL; /* null terminate list */ + attr[l + 1] = ""; /* temporary attribute value */ + attr[l] = s; /* set attribute name */ + + s += strcspn(s, EZXML_WS "=/>"); + if (*s == '=' || isspace(*s)) { + if (*s == '\n') + line++; + *(s++) = '\0'; /* null terminate tag attribute name */ + q = *(s += strspn(s, EZXML_WS "=")); + if (q == '"' || q == '\'') { /* attribute value */ + attr[l + 1] = ++s; + while (*s && *s != q) + s++; + if (*s) + *(s++) = '\0'; /* null terminate attribute val */ + else { + ezxml_free_attr(attr); + return ezxml_err(root, d, "missing %c", q); + } + + for (j = 1; a && a[j] && strcmp(a[j], attr[l]); j += 3) + ; + attr[l + 1] = ezxml_decode(attr[l + 1], + root->ent, (a && a[j]) ? *a[j + 2] : ' '); + if (attr[l + 1] < d || attr[l + 1] > s) + attr[l + 3][l / 2] = EZXML_TXTM; /* value malloced */ + } + } + while (isspace(*s)) { + if (*s == '\n') + line++; + s++; + } + } + + if (*s == '/') { /* self closing tag */ + *(s++) = '\0'; + if ((*s && *s != '>') || (!*s && e != '>')) { + if (l) + ezxml_free_attr(attr); + return ezxml_err(root, d, "missing >"); + } + ezxml_open_tag(root, line, d, attr); + ezxml_close_tag(root, d, s); + } else if ((q = *s) == '>' || (!*s && e == '>')) { /* open tag */ + *s = '\0'; /* temporarily null terminate tag name */ + ezxml_open_tag(root, line, d, attr); + *s = q; + } else { + if (l) + ezxml_free_attr(attr); + return ezxml_err(root, d, "missing >"); + } + } else if (*s == '/') { /* close tag */ + s += strcspn(d = s + 1, EZXML_WS ">") + 1; + /* Jason Luu, Aug 29, 2007. Removed assignment in conditional statement */ + q = *s; + if (!q && e != '>') + return ezxml_err(root, d, "missing >"); + *s = '\0'; /* temporarily null terminate tag name */ + if (ezxml_close_tag(root, d, s)) + return &root->xml; + if (isspace(*s = q)) { + if (*s == '\n') + line++; + s += strspn(s, EZXML_WS); + } + } else if (!strncmp(s, "!--", 3)) { /* xml comment */ + temp = s; + s = strstr(s + 3, "--"); + if (!s || (*(s += 2) != '>' && *s) || (!*s && e != '>')) + return ezxml_err(root, d, "unclosed | Des2 | + * | | | | | | | | + * -------- | -------- | -------- + * /|\ | /|\ | /|\ + * |------------|-------------| + * \|/ | | | \|/ + * -------- | -------- | -------- + * | | | | | | | | + * | Des3 |<-| | SRC | |->| Des4 | + * | | | | | | | | + * -------- | -------- | -------- + * | | + * -------------|-------------- + * \|/ | \|/ | \|/ + * -------- | -------- | -------- + * | | | | | | | | + * | Des5 |<--->| Des6 |<--->| Des7 | + * | | | | | | + * -------- -------- -------- + */ +void set_src_top_side_net_one_sink_prefer_side(int* prefer_side, + t_block src_blk, t_block des_blk) { + /* TODO: for none IO_TYPE, there should be no self connections*/ + assert(!((des_blk.x == src_blk.x)&&(des_blk.y == src_blk.y)&&(des_blk.z == src_blk.z))); + /* Identify which position the des_blk, based on src_blk */ + if ((des_blk.x < src_blk.x)&&(des_blk.y > src_blk.y)) { + /* Des 0 */ + prefer_side[RIGHT] = 1; + prefer_side[BOTTOM] = 1; + } else if ((des_blk.x == src_blk.x)&&(des_blk.y > src_blk.y)) { + /* Des 1 */ + prefer_side[BOTTOM] = 1; + } else if ((des_blk.x > src_blk.x)&&(des_blk.y > src_blk.y)) { + /* Des 2 */ + prefer_side[LEFT] = 1; + prefer_side[BOTTOM] = 1; + } else if ((des_blk.x < src_blk.x)&&(des_blk.y == src_blk.y)) { + /* Des 3 */ + prefer_side[TOP] = 1; + prefer_side[RIGHT] = 1; + } else if ((des_blk.x > src_blk.x)&&(des_blk.y == src_blk.y)) { + /* Des 4 */ + prefer_side[TOP] = 1; + prefer_side[LEFT] = 1; + } else if ((des_blk.x < src_blk.x)&&(des_blk.y < src_blk.y)) { + /* Des 5 */ + prefer_side[TOP] = 1; + prefer_side[RIGHT] = 1; + } else if ((des_blk.x == src_blk.x)&&(des_blk.y < src_blk.y)) { + /* Des 6 */ + prefer_side[TOP] = 1; + //prefer_side[RIGHT] = 1; + //prefer_side[LEFT] = 1; + } else if ((des_blk.x > src_blk.x)&&(des_blk.y < src_blk.y)) { + /* Des 7 */ + prefer_side[TOP] = 1; + prefer_side[LEFT] = 1; + } + + return; +} + +/* Find prefered side for one sink pin when the source pin is on RIGHT side + * Refer to this graph, src block locates the center + * -------- -------- -------- + * | | | | | | + * | Des0 |<-- | Des1 |<--->| Des2 | + * | | | | | | | | + * -------- | -------- | -------- + * /|\ | /|\ | /|\ + * |--------------------------| + * \|/ | | + * -------- | -------- | -------- + * | | | | | | | | + * | Des3 |<-| | SRC |--|->| Des4 | + * | | | | | | | | + * -------- | -------- | -------- + * /|\ | | + * |--------------------------| + * \|/ | \|/ | \|/ + * -------- | -------- | -------- + * | | | | | | | | + * | Des5 |<-- | Des6 |<--->| Des7 | + * | | | | | | + * -------- -------- -------- + */ +void set_src_right_side_net_one_sink_prefer_side(int* prefer_side, + t_block src_blk, t_block des_blk) { + /* TODO: for none IO_TYPE, there should be no self connections*/ + assert(!((des_blk.x == src_blk.x)&&(des_blk.y == src_blk.y)&&(des_blk.z == src_blk.z))); + /* Identify which position the des_blk, based on src_blk */ + if ((des_blk.x < src_blk.x)&&(des_blk.y > src_blk.y)) { + /* Des 0 */ + prefer_side[RIGHT] = 1; + prefer_side[BOTTOM] = 1; + } else if ((des_blk.x == src_blk.x)&&(des_blk.y > src_blk.y)) { + /* Des 1 */ + prefer_side[RIGHT] = 1; + prefer_side[BOTTOM] = 1; + } else if ((des_blk.x > src_blk.x)&&(des_blk.y > src_blk.y)) { + /* Des 2 */ + prefer_side[LEFT] = 1; + prefer_side[BOTTOM] = 1; + } else if ((des_blk.x < src_blk.x)&&(des_blk.y == src_blk.y)) { + /* Des 3 */ + //prefer_side[TOP] = 1; + prefer_side[RIGHT] = 1; + //prefer_side[BOTTOM] = 1; + } else if ((des_blk.x > src_blk.x)&&(des_blk.y == src_blk.y)) { + /* Des 4 */ + prefer_side[LEFT] = 1; + } else if ((des_blk.x < src_blk.x)&&(des_blk.y < src_blk.y)) { + /* Des 5 */ + prefer_side[TOP] = 1; + prefer_side[RIGHT] = 1; + } else if ((des_blk.x == src_blk.x)&&(des_blk.y < src_blk.y)) { + /* Des 6 */ + prefer_side[TOP] = 1; + prefer_side[RIGHT] = 1; + } else if ((des_blk.x > src_blk.x)&&(des_blk.y < src_blk.y)) { + /* Des 7 */ + prefer_side[TOP] = 1; + prefer_side[LEFT] = 1; + } + + return; +} + +/* Find prefered side for one sink pin when the source pin is on BOTTOM side + * Refer to this graph, src block locates the center + * -------- -------- -------- + * | | | | | | + * | Des0 |<-- | Des1 |<--->| Des2 | + * | | | | | | | | + * -------- | -------- | -------- + * /|\ | /|\ | /|\ + * |--------------------------| + * | | + * -------- | -------- | -------- + * | | | | | | | | + * | Des3 |<-| | SRC | |->| Des4 | + * | | | | | | | | + * -------- | -------- | -------- + * /|\ | | | /|\ + * |------------|-------------| + * \|/ | \|/ | \|/ + * -------- | -------- | -------- + * | | | | | | | | + * | Des5 |<-- | Des6 | -->| Des7 | + * | | | | | | + * -------- -------- -------- + */ +void set_src_bottom_side_net_one_sink_prefer_side(int* prefer_side, + t_block src_blk, t_block des_blk) { + /* TODO: for none IO_TYPE, there should be no self connections*/ + assert(!((des_blk.x == src_blk.x)&&(des_blk.y == src_blk.y)&&(des_blk.z == src_blk.z))); + /* Identify which position the des_blk, based on src_blk */ + if ((des_blk.x < src_blk.x)&&(des_blk.y > src_blk.y)) { + /* Des 0 */ + prefer_side[RIGHT] = 1; + prefer_side[BOTTOM] = 1; + } else if ((des_blk.x == src_blk.x)&&(des_blk.y > src_blk.y)) { + /* Des 1 */ + //prefer_side[RIGHT] = 1; + prefer_side[BOTTOM] = 1; + //prefer_side[LEFT] = 1; + } else if ((des_blk.x > src_blk.x)&&(des_blk.y > src_blk.y)) { + /* Des 2 */ + prefer_side[LEFT] = 1; + prefer_side[BOTTOM] = 1; + } else if ((des_blk.x < src_blk.x)&&(des_blk.y == src_blk.y)) { + /* Des 3 */ + prefer_side[RIGHT] = 1; + prefer_side[BOTTOM] = 1; + } else if ((des_blk.x > src_blk.x)&&(des_blk.y == src_blk.y)) { + /* Des 4 */ + prefer_side[LEFT] = 1; + prefer_side[BOTTOM] = 1; + } else if ((des_blk.x < src_blk.x)&&(des_blk.y < src_blk.y)) { + /* Des 5 */ + prefer_side[TOP] = 1; + prefer_side[RIGHT] = 1; + } else if ((des_blk.x == src_blk.x)&&(des_blk.y < src_blk.y)) { + /* Des 6 */ + prefer_side[TOP] = 1; + } else if ((des_blk.x > src_blk.x)&&(des_blk.y < src_blk.y)) { + /* Des 7 */ + prefer_side[TOP] = 1; + prefer_side[LEFT] = 1; + } + + return; +} + +/* Find prefered side for one sink pin when the source pin is on LEFT side + * Refer to this graph, src block locates the center + * -------- -------- -------- + * | | | | | | + * | Des0 |<--->| Des1 | -->| Des2 | + * | | | | | | | | + * -------- | -------- | -------- + * /|\ | /|\ | /|\ + * |--------------------------| + * | | \|/ + * -------- | -------- | -------- + * | | | | | | | | + * | Des3 |<-|--| SRC | |->| Des4 | + * | | | | | | | | + * -------- | -------- | -------- + * | | /|\ + * |--------------------------| + * \|/ | \|/ | \|/ + * -------- | -------- | -------- + * | | | | | | | | + * | Des5 |<--->| Des6 | -->| Des7 | + * | | | | | | + * -------- -------- -------- + */ +void set_src_left_side_net_one_sink_prefer_side(int* prefer_side, + t_block src_blk, t_block des_blk) { + /* TODO: for none IO_TYPE, there should be no self connections*/ + assert(!((des_blk.x == src_blk.x)&&(des_blk.y == src_blk.y)&&(des_blk.z == src_blk.z))); + /* Identify which position the des_blk, based on src_blk */ + if ((des_blk.x < src_blk.x)&&(des_blk.y > src_blk.y)) { + /* Des 0 */ + prefer_side[RIGHT] = 1; + prefer_side[BOTTOM] = 1; + } else if ((des_blk.x == src_blk.x)&&(des_blk.y > src_blk.y)) { + /* Des 1 */ + prefer_side[BOTTOM] = 1; + prefer_side[LEFT] = 1; + } else if ((des_blk.x > src_blk.x)&&(des_blk.y > src_blk.y)) { + /* Des 2 */ + prefer_side[LEFT] = 1; + prefer_side[BOTTOM] = 1; + } else if ((des_blk.x < src_blk.x)&&(des_blk.y == src_blk.y)) { + /* Des 3 */ + prefer_side[RIGHT] = 1; + } else if ((des_blk.x > src_blk.x)&&(des_blk.y == src_blk.y)) { + /* Des 4 */ + //prefer_side[TOP] = 1; + prefer_side[LEFT] = 1; + //prefer_side[BOTTOM] = 1; + } else if ((des_blk.x < src_blk.x)&&(des_blk.y < src_blk.y)) { + /* Des 5 */ + prefer_side[TOP] = 1; + prefer_side[RIGHT] = 1; + } else if ((des_blk.x == src_blk.x)&&(des_blk.y < src_blk.y)) { + /* Des 6 */ + prefer_side[TOP] = 1; + prefer_side[LEFT] = 1; + } else if ((des_blk.x > src_blk.x)&&(des_blk.y < src_blk.y)) { + /* Des 7 */ + prefer_side[TOP] = 1; + prefer_side[LEFT] = 1; + } + + return; +} + +/* Try to satify the prefer side of all the pins of all the blocks */ +int sat_blks_pins_prefer_side(int n_nets, t_net* nets, + int n_blks, t_block* blk, + float** net_delay, float** expected_net_delay, t_slack* slack) { + int num_pin_remapped = 0; + int iblk; + + /* For each block, try to satify the prefer side of each pin */ + for (iblk = 0; iblk < n_blks; iblk++) { + /* Bypass IO_TYPE */ + if (IO_TYPE == blk[iblk].type) { + continue; + } + num_pin_remapped += sat_one_blk_pins_prefer_side(n_nets, nets, &(blk[iblk]), + net_delay, expected_net_delay, slack); + } + + return num_pin_remapped; +} + +/* For one block, try to satify the prefer side of each pin */ +int sat_one_blk_pins_prefer_side(int n_nets, t_net* nets, + t_block* target_blk, + float** net_delay, float** expected_net_delay, t_slack* slack) { + int num_pin_remapped = 0; + int ipin, num_pins; + int iclass; + int* is_pin_conflict = NULL; + int* cur_pin_side = NULL; + + assert(NULL != target_blk); + assert(NULL != target_blk->type); + num_pins = target_blk->type->num_pins; + + /* Bypass IO_TYPE */ + if (IO_TYPE == target_blk->type) { + return 0; + } + + /* Malloc */ + cur_pin_side = (int*)my_malloc(sizeof(int*)*num_pins); + /* Find current pin sides*/ + for (ipin = 0; ipin < num_pins; ipin++) { + /* Make sure each pin appear at only one side!*/ + cur_pin_side[ipin] = find_blk_net_pin_side((*target_blk), target_blk->z, ipin); + } + /* Check the number of conflicts: + * pin_side not in prefer side + */ + /* Malloc and Initialize */ + is_pin_conflict = (int*)my_calloc(num_pins, sizeof(int)); + for (ipin = 0; ipin < num_pins; ipin++) { + if (0 == target_blk->pin_prefer_side[ipin][cur_pin_side[ipin]]) { + is_pin_conflict[ipin] = 1; + } + } + for (iclass = 0; iclass < target_blk->type->num_class; iclass++) { + /* We care RECEIVER class only */ + if (RECEIVER != target_blk->type->class_inf[iclass].type) { + continue; + } + num_pin_remapped += try_sat_one_blk_pin_class_prefer_side(target_blk, n_nets, nets, + iclass, is_pin_conflict, cur_pin_side, + net_delay, expected_net_delay, slack); + } + + /* Free */ + my_free(cur_pin_side); + my_free(is_pin_conflict); + + return num_pin_remapped; +} + +int try_sat_one_blk_pin_class_prefer_side(t_block* target_blk, + int n_nets, t_net* nets, + int class_index, + int* is_pin_conflict, int* cur_pin_side, + float** net_delay, float** expected_net_delay, t_slack* slack) { + int num_pin_remapped = 0; + int ipin, class_num_pins, blk_pin_index; + int net_index, net_sink_index; + int num_conflict = 0; + int sorted_list_len = 0; + int* sorted_conflict_pin_list = NULL; + float* esti_delay_gain = NULL; + + assert(NULL != target_blk); + assert(NULL != target_blk->type); + + /* We care RECEIVER class only */ + if (RECEIVER != target_blk->type->class_inf[class_index].type) { + return num_pin_remapped; + } + + class_num_pins = target_blk->type->class_inf[class_index].num_pins; + /* If there is only one pin in this class, there is no need to remap */ + assert(0 < class_num_pins); + if (2 > class_num_pins) { + return num_pin_remapped; + } + /* Count the number of conflict in this class */ + num_conflict = count_blk_one_class_num_conflict(target_blk, class_index, is_pin_conflict); + /* There is no conflict, directly return */ + if (0 == num_conflict) { + return num_pin_remapped; + } + + /* Now we try to solve all the conflicts */ + /* See the estimated delay gain */ + esti_delay_gain = (float*)my_malloc(sizeof(float)*class_num_pins); + for (ipin = 0; ipin < class_num_pins; ipin++) { + blk_pin_index = target_blk->type->class_inf[class_index].pinlist[ipin]; + /* unroute net, bypass not conflict pins */ + if (0 == is_pin_conflict[blk_pin_index]) { + esti_delay_gain[ipin] = -1.; + continue; + } + /* Estimate delay gain on conflicted pins */ + net_index = target_blk->nets[blk_pin_index]; + net_sink_index = target_blk->nets_sink_index[blk_pin_index]; + assert(OPEN != net_index); + assert(OPEN != net_sink_index); + esti_delay_gain[ipin] = expected_net_delay[net_index][net_sink_index]/net_delay[net_index][net_sink_index] - 1; + assert(!(esti_delay_gain[ipin] > 0)); /* Expected_net_delay should be smaller! */ + } + + /* Sort the conflict pins in the class by lowest slack */ + sorted_conflict_pin_list = sort_one_class_conflict_pins_by_low_slack(target_blk, class_index, + is_pin_conflict, &sorted_list_len, slack); + assert(sorted_list_len == num_conflict); + + /* Try to solve each conflict pin */ + num_pin_remapped = 0; + for (ipin = 0; ipin < num_conflict; ipin++) { + blk_pin_index = target_blk->type->class_inf[class_index].pinlist[sorted_conflict_pin_list[ipin]]; + if (1 == is_pin_conflict[blk_pin_index]) { + num_pin_remapped += try_remap_blk_class_one_conflict_pin(target_blk, class_index, blk_pin_index, + n_nets, nets, cur_pin_side, is_pin_conflict, + esti_delay_gain, slack); + } + } + + /* Free */ + my_free(sorted_conflict_pin_list); + my_free(esti_delay_gain); + + return num_pin_remapped; +} + +/* Successful remap, return 1. Fail, return 0. + * 1. Try to swap with a conflicted pin in the same class + * 2. Try to swap with an unrouted pin in the same class + * 3. Try to swap with a unconflicted pin in the same class + */ +int try_remap_blk_class_one_conflict_pin(t_block* target_blk, int class_index, int pin_index, + int n_nets, t_net* nets, + int* cur_pin_side, int* is_pin_conflict, + float* esti_delay_gain, t_slack* slack) { + int* prefer_sides = NULL; + int num_pins; + int ipin, blk_pin_index, side_swap; + + assert(NULL != target_blk); + assert(NULL != target_blk->type); + assert((!(0 > pin_index))&&(pin_index < target_blk->type->num_pins)); + assert((!(0 > class_index))&&(class_index < target_blk->type->num_class)); + /* ONLY support INPUT PINs */ + assert(RECEIVER == target_blk->type->class_inf[class_index].type); + + prefer_sides = target_blk->pin_prefer_side[pin_index]; + num_pins = target_blk->type->class_inf[class_index].num_pins; + + if (!(1 == is_type_pin_in_class(target_blk->type, class_index, pin_index))) { + printf("num_pin_in_class = %d\n", is_type_pin_in_class(target_blk->type, class_index, pin_index)); + assert(1 == is_type_pin_in_class(target_blk->type, class_index, pin_index)); + } + assert(1 == is_pin_conflict[pin_index]); + + /* Try to swap with conflicted pins */ + for (ipin = 0; ipin < num_pins; ipin++) { + blk_pin_index = target_blk->type->class_inf[class_index].pinlist[ipin]; + assert((!(0 >cur_pin_side[blk_pin_index]))&&(cur_pin_side[blk_pin_index] < 4)); + /* conflicted_pin match prefer_side */ + if ((pin_index != blk_pin_index)&&(1 == is_pin_conflict[blk_pin_index]) + &&(1 == is_swap2pins_match_prefer_side(cur_pin_side[pin_index], prefer_sides, + cur_pin_side[blk_pin_index], target_blk->pin_prefer_side[blk_pin_index]))) { + /* Swap 2 CLB IPIN */ + swap_blk_same_class_2pins(target_blk, n_nets, nets, pin_index, blk_pin_index); + /* Print DEBUG info */ + vpr_printf(TIO_MESSAGE_INFO, + "SwapCase1: PIN(block x=%d, y=%d, z=%d, index=%d, net[%s].sink[%d])\n", + target_blk->x, target_blk->y, target_blk->z, pin_index, + nets[target_blk->nets[pin_index]].name, target_blk->nets_sink_index[pin_index]); + vpr_printf(TIO_MESSAGE_INFO, + " with PIN(block x=%d, y=%d, z=%d, index=%d, net[%s].sink[%d]).\n", + target_blk->x, target_blk->y, target_blk->z, blk_pin_index, + nets[target_blk->nets[blk_pin_index]].name, target_blk->nets_sink_index[blk_pin_index]); + vpr_printf(TIO_MESSAGE_INFO, "ipin=%d\n", ipin); + /* Update is_conflict list */ + is_pin_conflict[blk_pin_index] = 0; + is_pin_conflict[pin_index] = 0; + /* Update cur_pin_side list */ + side_swap = cur_pin_side[blk_pin_index]; + cur_pin_side[blk_pin_index] = cur_pin_side[pin_index]; + cur_pin_side[pin_index] = side_swap; + /* Finish, we can return */ + return 2; + } + } + + /* Find all unrounted pins, try to swap */ + for (ipin = 0; ipin < num_pins; ipin++) { + blk_pin_index = target_blk->type->class_inf[class_index].pinlist[ipin]; + assert((!(0 >cur_pin_side[blk_pin_index]))&&(cur_pin_side[blk_pin_index] < 4)); + /* conflicted_pin match prefer_side */ + if ((pin_index != blk_pin_index)&&(0 == is_pin_conflict[blk_pin_index])&&(OPEN == target_blk->nets[blk_pin_index]) + &&(1 == is_swap2pins_match_prefer_side(cur_pin_side[pin_index], prefer_sides, + cur_pin_side[blk_pin_index], target_blk->pin_prefer_side[blk_pin_index]))) { + /* Swap 2 CLB IPIN */ + swap_blk_same_class_2pins(target_blk, n_nets, nets, pin_index, blk_pin_index); + /* Print DEBUG info */ + vpr_printf(TIO_MESSAGE_INFO, + "SwapCase2: PIN(block x=%d, y=%d, z=%d, index=%d, net[%s].sink[%d])\n", + target_blk->x, target_blk->y, target_blk->z, pin_index, + nets[target_blk->nets[pin_index]].name, target_blk->nets_sink_index[pin_index]); + vpr_printf(TIO_MESSAGE_INFO, + " with PIN(block x=%d, y=%d, z=%d, index=%d, net[%s].sink[%d]).\n", + target_blk->x, target_blk->y, target_blk->z, blk_pin_index, + nets[target_blk->nets[blk_pin_index]].name, target_blk->nets_sink_index[blk_pin_index]); + vpr_printf(TIO_MESSAGE_INFO, "ipin=%d\n", ipin); + /* Update is_conflict list */ + is_pin_conflict[blk_pin_index] = 0; + is_pin_conflict[pin_index] = 0; + /* Update cur_pin_side list */ + side_swap = cur_pin_side[blk_pin_index]; + cur_pin_side[blk_pin_index] = cur_pin_side[pin_index]; + cur_pin_side[pin_index] = side_swap; + /* Finish, we can return */ + return 1; + } + } + + /* Find unconflicted routed pins, try to swap */ + for (ipin = 0; ipin < num_pins; ipin++) { + blk_pin_index = target_blk->type->class_inf[class_index].pinlist[ipin]; + assert((!(0 >cur_pin_side[blk_pin_index]))&&(cur_pin_side[blk_pin_index] < 4)); + /* conflicted_pin match prefer_side */ + if ((pin_index != blk_pin_index)&&(0 == is_pin_conflict[blk_pin_index])&&(OPEN != target_blk->nets[blk_pin_index]) + /* TODO: if pin_index slack overwhelms blk_pin_index, shall we swap??? */ + &&(1 == 0) + &&(1 == is_swap2pins_match_prefer_side(cur_pin_side[pin_index], prefer_sides, + cur_pin_side[blk_pin_index], target_blk->pin_prefer_side[blk_pin_index]))) { + /* Swap 2 CLB IPIN */ + swap_blk_same_class_2pins(target_blk, n_nets, nets, pin_index, blk_pin_index); + /* Print DEBUG info */ + vpr_printf(TIO_MESSAGE_INFO, + "SwapCase3: PIN(block x=%d, y=%d, z=%d, index=%d, net[%s].sink[%d])\n", + target_blk->x, target_blk->y, target_blk->z, pin_index, + nets[target_blk->nets[pin_index]].name, target_blk->nets_sink_index[pin_index]); + vpr_printf(TIO_MESSAGE_INFO, + " with PIN(block x=%d, y=%d, z=%d, index=%d, net[%s].sink[%d]).\n", + target_blk->x, target_blk->y, target_blk->z, blk_pin_index, + nets[target_blk->nets[blk_pin_index]].name, target_blk->nets_sink_index[blk_pin_index]); + vpr_printf(TIO_MESSAGE_INFO, "ipin=%d\n", ipin); + /* Update is_conflict list */ + is_pin_conflict[blk_pin_index] = 0; + is_pin_conflict[pin_index] = 0; + /* Update cur_pin_side list */ + side_swap = cur_pin_side[blk_pin_index]; + cur_pin_side[blk_pin_index] = cur_pin_side[pin_index]; + cur_pin_side[pin_index] = side_swap; + /* Finish, we can return */ + return 2; + } + } + + return 0; +} + diff --git a/vpr7_rram/vpr/SRC/clb_pin_remap/place_clb_pin_remap.h b/vpr7_rram/vpr/SRC/clb_pin_remap/place_clb_pin_remap.h new file mode 100644 index 000000000..9992f65da --- /dev/null +++ b/vpr7_rram/vpr/SRC/clb_pin_remap/place_clb_pin_remap.h @@ -0,0 +1,47 @@ + +void try_clb_pin_remap_after_placement(t_det_routing_arch det_routing_arch, + t_segment_inf* segment_inf, + t_timing_inf timing_inf, + int num_directs, + t_direct_inf* directs); + +int generate_nets_sinks_prefer_sides(int n_nets, t_net* nets, + int n_blks, t_block* blk); + +int set_unroute_blk_pins_prefer_sides(int n_blk, t_block* blk); + +void set_blk_net_one_sink_prefer_side(int* prefer_side, /* [0..3] array, should be allocated before */ + enum e_side src_pin_side, + t_block src_blk, + t_block des_blk); + +void set_src_top_side_net_one_sink_prefer_side(int* prefer_side, + t_block src_blk, t_block des_blk); + +void set_src_right_side_net_one_sink_prefer_side(int* prefer_side, + t_block src_blk, t_block des_blk); + +void set_src_bottom_side_net_one_sink_prefer_side(int* prefer_side, + t_block src_blk, t_block des_blk); + +void set_src_left_side_net_one_sink_prefer_side(int* prefer_side, + t_block src_blk, t_block des_blk); + +int sat_blks_pins_prefer_side(int n_nets, t_net* nets, + int n_blks, t_block* blk, + float** net_delay, float** expected_net_delay, t_slack* slack); + +int sat_one_blk_pins_prefer_side(int n_nets, t_net* nets, + t_block* target_blk, + float** net_delay, float** expected_net_delay, t_slack* slack); + +int try_sat_one_blk_pin_class_prefer_side(t_block* target_blk, + int n_nets, t_net* nets, + int class_index, + int* is_pin_conflict, int* cur_pin_side, + float** net_delay, float** expected_net_delay, t_slack* slack); + +int try_remap_blk_class_one_conflict_pin(t_block* target_blk, int class_index, int pin_index, + int n_nets, t_net* nets, + int* cur_pin_side, int* is_pin_conflict, + float* esti_delay_gain, t_slack* slack); diff --git a/vpr7_rram/vpr/SRC/clb_pin_remap/post_place_timing.c b/vpr7_rram/vpr/SRC/clb_pin_remap/post_place_timing.c new file mode 100644 index 000000000..e5bb1896f --- /dev/null +++ b/vpr7_rram/vpr/SRC/clb_pin_remap/post_place_timing.c @@ -0,0 +1,367 @@ +#include +#include +#include +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "net_delay_types.h" +#include "net_delay_local_void.h" +#include "net_delay.h" +#include "path_delay.h" +/* CLB PIN REMAP */ +#include "clb_pin_remap_util.h" +#include "post_place_timing.h" + +/* Xifan TANG: Copied from place.c */ +/* Expected crossing counts for nets with different #'s of pins. From * + * ICCAD 94 pp. 690 - 695 (with linear interpolation applied by me). * + * Multiplied to bounding box of a net to better estimate wire length * + * for higher fanout nets. Each entry is the correction factor for the * + * fanout index-1 */ +static const float local_cross_count[50] = { /* [0..49] */1.0, 1.0, 1.0, 1.0828, 1.1536, 1.2206, 1.2823, 1.3385, 1.3991, 1.4493, 1.4974, + 1.5455, 1.5937, 1.6418, 1.6899, 1.7304, 1.7709, 1.8114, 1.8519, 1.8924, + 1.9288, 1.9652, 2.0015, 2.0379, 2.0743, 2.1061, 2.1379, 2.1698, 2.2016, + 2.2334, 2.2646, 2.2958, 2.3271, 2.3583, 2.3895, 2.4187, 2.4479, 2.4772, + 2.5064, 2.5356, 2.5610, 2.5864, 2.6117, 2.6371, 2.6625, 2.6887, 2.7148, + 2.7410, 2.7671, 2.7933 }; + +/* Load and estimate post-placement net delays according to the PIN locations */ +void load_post_place_net_delay(float** net_delay, + int n_blks, + t_block* blk, + int n_nets, + t_net* nets, + t_det_routing_arch det_routing_arch, + t_segment_inf* segment_inf, + t_timing_inf timing_inf, + int num_directs, + t_direct_inf* directs) { + int inet, isink; + int src_blk_index, /*src_blk_port_index,*/ src_blk_pin_index; + int des_blk_index, /*des_blk_port_index,*/ des_blk_pin_index; + float penalty = 0.; + + /* Search each clb net, find the driver (OPIN) and all the receivers (IPINs) */ + for (inet = 0; inet < n_nets; inet++) { + /* Global nets, we don't optimize */ + if (TRUE == nets[inet].is_global) { + load_one_constant_net_delay(net_delay, inet, nets, 0.); + } else { + penalty = get_crossing_penalty(nets[inet].num_sinks); + /* Spot driver (OPIN) location */ + src_blk_index = nets[inet].node_block[0]; + //src_blk_port_index = nets[inet].node_block_port[0]; + src_blk_pin_index = nets[inet].node_block_pin[0]; + /* Check the driver OPIN */ + check_src_blk_pin(n_blks, blk, inet, + src_blk_index, + //src_blk_port_index, + src_blk_pin_index); + /* Search all the sinks and estimate route delay */ + for (isink = 1; isink < (nets[inet].num_sinks + 1); isink++) { + des_blk_index = nets[inet].node_block[isink]; + //des_blk_port_index = nets[inet].node_block_port[isink]; + des_blk_pin_index = nets[inet].node_block_pin[isink]; + check_des_blk_pin(n_blks, blk, inet, + des_blk_index, + //des_blk_port_index, + des_blk_pin_index); + /* Estimate the net delay */ + net_delay[inet][isink] = penalty * + estimate_post_place_one_net_sink_delay(inet, n_blks, blk, src_blk_index, des_blk_index, + det_routing_arch, segment_inf, timing_inf, + num_directs, directs); + } + } + } + + return; +} + +float estimate_post_place_one_net_sink_delay(int net_index, + int n_blks, + t_block* blk, + int src_blk_index, + int des_blk_index, + t_det_routing_arch det_routing_arch, + t_segment_inf* segment_inf, + t_timing_inf timing_inf, + int num_directs, + t_direct_inf* directs) { + float esti_net_delay = -1.; + int num_src_pins = 0; + enum e_side* src_pin_side = NULL; + int* src_pin_index = NULL; + + int num_des_pins = 0; + enum e_side* des_pin_side; + int* des_pin_index = NULL; + + int isrc, ides; + float pin2pin_net_delay = 0.; + + /* ONLY APPLICABLE TO UNI_DIRECITONAL ROUTING ARCH. !!!*/ + if (UNI_DIRECTIONAL != det_routing_arch.directionality) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d])Estimate post-placement net delay is ONLY applicable to uni-directional routint arch!\n", __FILE__, __LINE__); + exit(1); + } + /* Find the driver OPINs location */ + find_blk_net_type_pins(n_blks, blk, net_index, src_blk_index, + &num_src_pins, &src_pin_side, &src_pin_index); + /* Find the receiver IPINs location */ + find_blk_net_type_pins(n_blks, blk, net_index, des_blk_index, + &num_des_pins, &des_pin_side, &des_pin_index); + /* Search all possible path */ + assert(0 < num_src_pins); + assert(0 < num_des_pins); + /* Should be only 1 destination pin */ + assert(1 == num_des_pins); + for (ides = 0; ides < num_des_pins; ides++) { + /* Should be only 1 source pin */ + assert(1 == num_src_pins); + /* Possible paths from sources */ + for (isrc = 0; isrc < num_src_pins; isrc++) { + pin2pin_net_delay = esti_pin2pin_one_net_delay(blk[src_blk_index], src_pin_side[isrc], src_pin_index[isrc], + blk[des_blk_index], des_pin_side[ides], des_pin_index[ides], + det_routing_arch, segment_inf, timing_inf, num_directs, directs); + /* Consider the worst case src->des pin delay*/ + if ((-1. == esti_net_delay)||(pin2pin_net_delay > esti_net_delay)) { + esti_net_delay = pin2pin_net_delay; + } + } + } + + return esti_net_delay; +} + +float esti_pin2pin_one_net_delay(t_block src_blk, + int src_pin_side, + int src_pin_index, + t_block des_blk, + int des_pin_side, + int des_pin_index, + t_det_routing_arch det_routing_arch, + t_segment_inf* segment_inf, + t_timing_inf timing_inf, + int num_directs, + t_direct_inf* directs) { + int src_pin_x, src_pin_y; + int des_pin_x, des_pin_y; + int delta_x, delta_y; + float horizen_delay, vertical_delay, path_delay; + + /* ONLY APPLICABLE TO UNI_DIRECITONAL ROUTING ARCH. !!!*/ + if (UNI_DIRECTIONAL != det_routing_arch.directionality) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d])Estimate post-placement net delay is ONLY applicable to uni-directional routint arch!\n", __FILE__, __LINE__); + exit(1); + } + + /* Estimate the channel location of src and des pins */ + esti_pin_chan_coordinate(&src_pin_x, &src_pin_y, + src_blk, src_pin_side, src_pin_index); + esti_pin_chan_coordinate(&des_pin_x, &des_pin_y, + des_blk, des_pin_side, des_pin_index); + + /* TODO: Special for direct connection, delayless switch is used !!!*/ + + /* Search a possible path from SRC PIN to DES PIN */ + switch (src_pin_side) { + case TOP: + case BOTTOM: + /* 1st step: go horizentally */ + delta_x = abs(src_pin_x - des_pin_x); + /* Pass through a number of SB MUX */ + horizen_delay = esti_distance_num_seg_delay(delta_x, det_routing_arch.num_segment, segment_inf, 1); + /* 2nd step: go vertically */ + delta_y = abs(src_pin_y - des_pin_y); + /* Pass through a number of SB MUX */ + vertical_delay = esti_distance_num_seg_delay(delta_y, det_routing_arch.num_segment, segment_inf, 1); + /* 3rd step: go through a CB MUX */ + path_delay = horizen_delay + vertical_delay + + switch_inf[det_routing_arch.wire_to_ipin_switch].R * switch_inf[det_routing_arch.wire_to_ipin_switch].Cout + switch_inf[det_routing_arch.wire_to_ipin_switch].Tdel; + break; + case LEFT: + case RIGHT: + /* 1st step: go vertically */ + delta_y = abs(src_pin_y - des_pin_y); + /* Pass through a number of SB MUX */ + vertical_delay = esti_distance_num_seg_delay(delta_y, det_routing_arch.num_segment, segment_inf, 1); + /* 2nd step: go horizentally */ + delta_x = abs(src_pin_x - des_pin_x); + /* Pass through a number of SB MUX */ + horizen_delay = esti_distance_num_seg_delay(delta_x, det_routing_arch.num_segment, segment_inf, 1); + /* 3rd step: go through a CB MUX */ + path_delay = horizen_delay + vertical_delay + + switch_inf[det_routing_arch.wire_to_ipin_switch].R * switch_inf[det_routing_arch.wire_to_ipin_switch].Cout + switch_inf[det_routing_arch.wire_to_ipin_switch].Tdel; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, LINE[%d])Invalid side!\n", __FILE__, __LINE__); + exit(1); + } + + return path_delay; +} + +void load_expected_remapped_net_delay(float** net_delay, + int n_blks, + t_block* blk, + int n_nets, + t_net* nets, + t_det_routing_arch det_routing_arch, + t_segment_inf* segment_inf, + t_timing_inf timing_inf, + int num_directs, + t_direct_inf* directs) { + int inet, isink, i; + int src_blk_index, src_blk_pin_index, src_blk_pin_side; + int des_blk_index, des_blk_pin_index, des_blk_pin_side; + float esti_path_delay = -1.; + float pin2pin_one_sink_delay = 0.; + float penalty = 0.; + + /* Search each clb net, find the driver (OPIN) and all the receivers (IPINs) */ + for (inet = 0; inet < n_nets; inet++) { + /* Global nets, we don't optimize */ + if (TRUE == nets[inet].is_global) { + load_one_constant_net_delay(net_delay, inet, nets, 0.); + } else { + penalty = get_crossing_penalty(nets[inet].num_sinks); + /* Spot driver (OPIN) location */ + src_blk_index = nets[inet].node_block[0]; + src_blk_pin_index = nets[inet].node_block_pin[0]; + assert(NULL != blk[src_blk_index].type); + src_blk_pin_side = find_blk_net_pin_side(blk[src_blk_index], blk[src_blk_index].type->pin_height[src_blk_pin_index], src_blk_pin_index); + /* Search all the sinks and estimate route delay */ + for (isink = 1; isink < (nets[inet].num_sinks + 1); isink++) { + des_blk_index = nets[inet].node_block[isink]; + des_blk_pin_index = nets[inet].node_block_pin[isink]; + assert(NULL != blk[des_blk_index].type); + des_blk_pin_side = find_blk_net_pin_side(blk[des_blk_index], blk[des_blk_index].type->pin_height[des_blk_pin_index], des_blk_pin_index); + for (i = 0; i < 4; i++) { + if (0 == blk[des_blk_index].pin_prefer_side[des_blk_pin_index][i]) { + continue; /* Bypass non-preferred side */ + } + pin2pin_one_sink_delay = penalty * + esti_pin2pin_one_net_delay(blk[src_blk_index], src_blk_pin_side, src_blk_pin_index, + blk[des_blk_index], des_blk_pin_side, des_blk_pin_index, + det_routing_arch, segment_inf, timing_inf, num_directs, directs); + if ((-1. == esti_path_delay)||(esti_path_delay < pin2pin_one_sink_delay)) { + esti_path_delay = pin2pin_one_sink_delay; + } + } + assert(0. < esti_path_delay); + net_delay[inet][isink] = esti_path_delay; + } + } + } + + return; +} + +float esti_distance_num_seg_delay(int distance, + int num_segment, + t_segment_inf* segment_inf, + int allow_long_segment) { + int actual_distance; + float esti_delay = 0.; + float min_out_range_esti_delay = 0.; + float max_in_range_esti_delay = 0.; + int iseg, min_out_range_seg, max_in_range_seg; + + /* Min-distance should be 1 */ + if (distance < 1) { + actual_distance = 1; + } else { + actual_distance = distance; + } + + /* Find the min-length segment whose length is larger than distance */ + min_out_range_seg = -1; + for (iseg = 0; iseg < num_segment; iseg++) { + if (segment_inf[iseg].length > distance) { + if (-1 == min_out_range_seg) { + min_out_range_seg = iseg; + } else if (segment_inf[iseg].length < segment_inf[min_out_range_seg].length) { + min_out_range_seg = iseg; + } + } + } + /* Find the max-length segment whose length is larger than distance */ + max_in_range_seg = -1; + for (iseg = 0; iseg < num_segment; iseg++) { + if ((segment_inf[iseg].length < distance) + ||(segment_inf[iseg].length == distance)) { + if (-1 == max_in_range_seg) { + max_in_range_seg = iseg; + } else if (segment_inf[iseg].length > segment_inf[max_in_range_seg].length) { + max_in_range_seg = iseg; + } + } + } + + /* Estimate the delay */ + if (-1 != max_in_range_seg) { + max_in_range_esti_delay = esti_one_segment_net_delay(distance, segment_inf[max_in_range_seg]); + } + if (-1 != min_out_range_seg) { + min_out_range_esti_delay = esti_one_segment_net_delay(distance, segment_inf[min_out_range_seg]); + } + + /* If allow longer segment, we should consider in making decision */ + if (allow_long_segment) { + if (min_out_range_esti_delay < max_in_range_esti_delay) { + esti_delay = min_out_range_esti_delay; + } + } else { + esti_delay = max_in_range_esti_delay; + } + + return esti_delay; +} + +float esti_one_segment_net_delay(int distance, t_segment_inf segment_inf) { + int num_sb_mux = 0; + int switch_index = segment_inf.opin_switch; + float one_switch_delay = 0.; + float one_segment_delay = 0.; + float total_delay = 0.; + int i; + + /* If segment length >= distance, only 1 SB MUX is required, + * If segment length < distance, then distance/segment_length SB MUX needed + */ + if (segment_inf.length < distance) { + num_sb_mux = distance/segment_inf.length; + if (0 != distance%segment_inf.length) { + num_sb_mux++; + } + } else { + num_sb_mux = 1; + } + /* Find the driver switch */ + one_switch_delay = switch_inf[switch_index].R * switch_inf[switch_index].Cout + switch_inf[switch_index].Tdel; + for (i = 0; i < segment_inf.length; i++) { + one_segment_delay = segment_inf.Rmetal + *((segment_inf.length - i)*(segment_inf.Cmetal + 2*switch_inf[switch_index].Cin) + switch_inf[switch_index].Cin); + } + + total_delay = num_sb_mux * (one_segment_delay + one_switch_delay); + + return total_delay; +} + +float get_crossing_penalty(int num_sinks) { + float crossing; + if (((num_sinks + 1) > 50) + && ((num_sinks + 1) < 85)) { + crossing = 2.7933 + 0.02616 * (num_sinks + 1) - 50; + } else if ((num_sinks + 1) >= 85) { + crossing = 2.7933 + 0.011 * (num_sinks + 1) + - 0.0000018 * (num_sinks + 1) + * (num_sinks + 1); + } else { + crossing = local_cross_count[(num_sinks + 1) - 1]; + } + + return crossing; +} diff --git a/vpr7_rram/vpr/SRC/clb_pin_remap/post_place_timing.h b/vpr7_rram/vpr/SRC/clb_pin_remap/post_place_timing.h new file mode 100644 index 000000000..cfae911d0 --- /dev/null +++ b/vpr7_rram/vpr/SRC/clb_pin_remap/post_place_timing.h @@ -0,0 +1,54 @@ + +void load_post_place_net_delay(float** net_delay, + int n_blks, + t_block* blk, + int n_nets, + t_net* nets, + t_det_routing_arch det_routing_arch, + t_segment_inf* segment_inf, + t_timing_inf timing_inf, + int num_directs, + t_direct_inf* directs); + +float estimate_post_place_one_net_sink_delay(int net_index, + int n_blks, + t_block* blk, + int src_blk_index, + int des_blk_index, + t_det_routing_arch det_routing_arch, + t_segment_inf* segment_inf, + t_timing_inf timing_inf, + int num_directs, + t_direct_inf* directs); + +float esti_pin2pin_one_net_delay(t_block src_blk, + int src_pin_side, + int src_pin_index, + t_block des_blk, + int des_pin_side, + int des_pin_index, + t_det_routing_arch det_routing_arch, + t_segment_inf* segment_inf, + t_timing_inf timing_inf, + int num_directs, + t_direct_inf* directs); + +void load_expected_remapped_net_delay(float** net_delay, + int n_blks, + t_block* blk, + int n_nets, + t_net* nets, + t_det_routing_arch det_routing_arch, + t_segment_inf* segment_inf, + t_timing_inf timing_inf, + int num_directs, + t_direct_inf* directs); + +float esti_distance_num_seg_delay(int distance, + int num_segment, + t_segment_inf* segment_inf, + int allow_long_segment); + +float esti_one_segment_net_delay(int distance, t_segment_inf segment_inf); + +float get_crossing_penalty(int num_sinks); diff --git a/vpr7_rram/vpr/SRC/ctags_vpr_src.sh b/vpr7_rram/vpr/SRC/ctags_vpr_src.sh new file mode 100644 index 000000000..3b5bc9cd5 --- /dev/null +++ b/vpr7_rram/vpr/SRC/ctags_vpr_src.sh @@ -0,0 +1 @@ +ctags main.c base/* draw/* pack/* place/* power/* route/* timing/* util/* spice/* mrfpga/* clb_pin_remap/* syn_verilog/* fpga_spice/* ../../libarchfpga/include/*.[ch] ../../libarchfpga/fpga_spice_include/*.[ch] ../../libarchfpga/*.[ch] diff --git a/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_api.c b/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_api.c new file mode 100644 index 000000000..717397f22 --- /dev/null +++ b/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_api.c @@ -0,0 +1,62 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph.h" +#include "vpr_utils.h" +#include "path_delay.h" +#include "stats.h" + +/* Include spice support headers*/ +#include "linkedlist.h" +#include "fpga_spice_utils.h" +#include "fpga_spice_backannotate_utils.h" +#include "fpga_spice_setup.h" +#include "spice_api.h" +#include "syn_verilog_api.h" + +/* Top-level API of FPGA-SPICE */ +void vpr_fpga_spice_tool_suites(t_vpr_setup vpr_setup, + t_arch Arch) { + /* Common initializations and malloc operations */ + /* If FPGA-SPICE is not called, we should initialize the spice_models */ + if (TRUE == vpr_setup.FPGA_SPICE_Opts.do_fpga_spice) { + fpga_spice_setup(vpr_setup, &Arch); + } + + /* Xifan TANG: SPICE Modeling, SPICE Netlist Output */ + if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.do_spice) { + vpr_print_spice_netlists(vpr_setup, Arch, vpr_setup.FileNameOpts.CircuitName); + } + + /* Xifan TANG: Synthesizable verilog dumping */ + if (vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_syn_verilog) { + vpr_dump_syn_verilog(vpr_setup, Arch, vpr_setup.FileNameOpts.CircuitName); + } + + /* Free */ + if (TRUE == vpr_setup.FPGA_SPICE_Opts.do_fpga_spice) { + /* Free all the backannotation containing post routing information */ + free_backannotate_vpr_post_route_info(); + /* TODO: free other linked lists ! */ + fpga_spice_free(&Arch); + } + + + return; +} + diff --git a/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_api.h b/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_api.h new file mode 100644 index 000000000..37a3986d8 --- /dev/null +++ b/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_api.h @@ -0,0 +1,5 @@ + + +void vpr_fpga_spice_tool_suites(t_vpr_setup vpr_setup, + t_arch Arch); + diff --git a/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_backannotate_utils.c b/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_backannotate_utils.c new file mode 100644 index 000000000..b23f52d68 --- /dev/null +++ b/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_backannotate_utils.c @@ -0,0 +1,2436 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph_util.h" +#include "rr_graph.h" +#include "rr_graph2.h" +#include "vpr_utils.h" +#include "path_delay.h" +#include "stats.h" + +/* Include spice support headers*/ +#include "read_xml_spice_util.h" +#include "linkedlist.h" +#include "fpga_spice_globals.h" +#include "spice_globals.h" +#include "fpga_spice_utils.h" +#include "spice_lut.h" + +/* Alloc, initialize and free functions for sb_info & cb_info */ +/* Initialize a SB_info */ +void init_one_sb_info(t_sb* cur_sb) { + cur_sb->x = -1; /* give an invalid value, which means OPEN */ + cur_sb->y = -1; /* give an invalid value, which means OPEN */ + cur_sb->directionality = UNI_DIRECTIONAL; + cur_sb->fs = -1; /* give an invalid value, which means OPEN */ + cur_sb->fc_out = -1; /* give an invalid value, which means OPEN */ + cur_sb->num_sides = 4; /* Should be fixed to 4 */ + cur_sb->chan_width = NULL; + cur_sb->num_ipin_rr_nodes = NULL; + cur_sb->num_opin_rr_nodes = NULL; + cur_sb->chan_rr_node = NULL; + cur_sb->chan_rr_node_direction = NULL; + cur_sb->ipin_rr_node = NULL; + cur_sb->ipin_rr_node_grid_side = NULL; + cur_sb->opin_rr_node = NULL; + cur_sb->opin_rr_node_grid_side = NULL; + cur_sb->num_reserved_conf_bits = 0; + cur_sb->conf_bits_lsb = 0; + cur_sb->conf_bits_msb = 0; + + return; +} + +/* Free everything (lists) inside a sb_info */ +void free_one_sb_info(t_sb* cur_sb) { + int i; + + if ((-1 == cur_sb->x)||(-1 == cur_sb->y)) { + /*NULL struct: bypass free */ + return; + } + + /* Free chan_width, input/output_rr_nodes, rr_nodes */ + my_free(cur_sb->chan_width); + for (i = 0; i < cur_sb->num_sides; i++) { + my_free(cur_sb->chan_rr_node_direction[i]); + my_free(cur_sb->chan_rr_node[i]); + my_free(cur_sb->ipin_rr_node[i]); + my_free(cur_sb->ipin_rr_node_grid_side[i]); + my_free(cur_sb->opin_rr_node[i]); + my_free(cur_sb->opin_rr_node_grid_side[i]); + } + my_free(cur_sb->num_ipin_rr_nodes); + my_free(cur_sb->num_opin_rr_nodes); + my_free(cur_sb->chan_rr_node_direction); + my_free(cur_sb->chan_rr_node); + my_free(cur_sb->ipin_rr_node); + my_free(cur_sb->ipin_rr_node_grid_side); + my_free(cur_sb->opin_rr_node); + my_free(cur_sb->opin_rr_node_grid_side); + + return; +} + +/* Alloc sb_info */ +t_sb** alloc_sb_info_array(int LL_nx, int LL_ny) { + int ix, iy; + t_sb** LL_sb_info = NULL; + + /* Allocate a two-dimension array for sb_info */ + LL_sb_info = (t_sb**)my_malloc(sizeof(t_sb*) * (LL_nx+1)); /* [0 ... nx] */ + for (ix = 0; ix < (LL_nx + 1); ix++) { + LL_sb_info[ix] = (t_sb*)my_malloc(sizeof(t_sb) * (LL_ny+1)); /* [0 ... ny] */ + for (iy = 0; iy < (LL_ny + 1); iy++) { + init_one_sb_info(&(LL_sb_info[ix][iy])); /* Initialize to NULL pointer */ + } + } + + return LL_sb_info; +} + +/* Free an sb_info_array */ +void free_sb_info_array(t_sb*** LL_sb_info, int LL_nx, int LL_ny) { + int ix, iy; + + if (NULL == (*LL_sb_info)) { + return; + } + + for (ix = 0; ix < (LL_nx + 1); ix++) { + for (iy = 0; iy < (LL_ny + 1); iy++) { + free_one_sb_info(&((*LL_sb_info)[ix][iy])); + } + my_free((*LL_sb_info)[ix]); + (*LL_sb_info)[ix] = NULL; + } + + (*LL_sb_info) = NULL; + + return; +} + +/* Initialize a CB_info */ +void init_one_cb_info(t_cb* cur_cb) { + cur_cb->x = -1; /* give an invalid value, which means OPEN */ + cur_cb->y = -1; /* give an invalid value, which means OPEN */ + cur_cb->type = NUM_RR_TYPES; + cur_cb->directionality = UNI_DIRECTIONAL; + cur_cb->fc_in = -1; /* give an invalid value, which means OPEN */ + cur_cb->num_sides = 4; /* Should be fixed to 4 */ + cur_cb->chan_width = NULL; + cur_cb->num_ipin_rr_nodes = NULL; + cur_cb->num_opin_rr_nodes = NULL; + cur_cb->chan_rr_node = NULL; + cur_cb->chan_rr_node_direction = NULL; + cur_cb->ipin_rr_node = NULL; + cur_cb->ipin_rr_node_grid_side = NULL; + cur_cb->opin_rr_node = NULL; + cur_cb->opin_rr_node_grid_side = NULL; + cur_cb->num_reserved_conf_bits = 0; + cur_cb->conf_bits_lsb = 0; + cur_cb->conf_bits_msb = 0; + + return; +} + +/* Free everything (lists) inside a sb_info */ +void free_one_cb_info(t_cb* cur_cb) { + int i; + + if ((-1 == cur_cb->x)||(-1 == cur_cb->y)) { + /*NULL struct: bypass free */ + return; + } + + /* Free chan_width, input/output_rr_nodes, rr_nodes */ + my_free(cur_cb->chan_width); + for (i = 0; i < cur_cb->num_sides; i++) { + my_free(cur_cb->chan_rr_node[i]); + my_free(cur_cb->chan_rr_node_direction[i]); + my_free(cur_cb->ipin_rr_node[i]); + my_free(cur_cb->ipin_rr_node_grid_side[i]); + my_free(cur_cb->opin_rr_node[i]); + my_free(cur_cb->opin_rr_node_grid_side[i]); + } + my_free(cur_cb->chan_rr_node); + my_free(cur_cb->num_ipin_rr_nodes); + my_free(cur_cb->num_opin_rr_nodes); + my_free(cur_cb->chan_rr_node_direction); + my_free(cur_cb->ipin_rr_node); + my_free(cur_cb->ipin_rr_node_grid_side); + my_free(cur_cb->opin_rr_node); + my_free(cur_cb->opin_rr_node_grid_side); + + return; +} + +/* Alloc cb_info: need to call this function twice for X-channel and Y-channel */ +t_cb** alloc_cb_info_array(int LL_nx, int LL_ny) { + int ix, iy; + t_cb** LL_cb_info = NULL; + + /* Allocate a two-dimension array for cb_info */ + LL_cb_info = (t_cb**)my_malloc(sizeof(t_cb*) * (LL_nx+1)); /* [0 ... nx] */ + for (ix = 0; ix < (LL_nx + 1); ix++) { + LL_cb_info[ix] = (t_cb*)my_malloc(sizeof(t_cb) * (LL_ny+1)); /* [0 ... ny] */ + for (iy = 0; iy < (LL_ny + 1); iy++) { + init_one_cb_info(&(LL_cb_info[ix][iy])); /* Initialize to NULL pointer */ + } + } + + return LL_cb_info; +} + +/* Free an sb_info_array */ +void free_cb_info_array(t_cb*** LL_cb_info, int LL_nx, int LL_ny) { + int ix, iy; + + if (NULL == (*LL_cb_info)) { + return; + } + + for (ix = 0; ix < (LL_nx + 1); ix++) { + for (iy = 0; iy < (LL_ny + 1); iy++) { + free_one_cb_info(&((*LL_cb_info)[ix][iy])); + } + my_free((*LL_cb_info)[ix]); + (*LL_cb_info)[ix] = NULL; + } + + (*LL_cb_info) = NULL; + + return; +} + +/* Get the index of a given rr_node in a SB_info */ +int get_rr_node_index_in_sb_info(t_rr_node* cur_rr_node, + t_sb cur_sb_info, + int chan_side, enum PORTS rr_node_direction) { + int inode, cnt, ret; + + cnt = 0; + ret = -1; + + /* Depending on the type of rr_node, we search different arrays */ + switch (cur_rr_node->type) { + case CHANX: + case CHANY: + for (inode = 0; inode < cur_sb_info.chan_width[chan_side]; inode++) { + if ((cur_rr_node == cur_sb_info.chan_rr_node[chan_side][inode]) + /* Check if direction meets specification */ + &&(rr_node_direction == cur_sb_info.chan_rr_node_direction[chan_side][inode])) { + cnt++; + ret = inode; + } + } + break; + case IPIN: + for (inode = 0; inode < cur_sb_info.num_ipin_rr_nodes[chan_side]; inode++) { + if (cur_rr_node == cur_sb_info.ipin_rr_node[chan_side][inode]) { + cnt++; + ret = inode; + } + } + break; + case OPIN: + for (inode = 0; inode < cur_sb_info.num_opin_rr_nodes[chan_side]; inode++) { + if (cur_rr_node == cur_sb_info.opin_rr_node[chan_side][inode]) { + cnt++; + ret = inode; + } + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid cur_rr_node type! Should be [CHANX|CHANY|IPIN|OPIN]\n", __FILE__, __LINE__); + exit(1); + } + + assert((0 == cnt)||(1 == cnt)); + + return ret; /* Return an invalid value: nonthing is found*/ +} + +/* Get the side and index of a given rr_node in a SB_info + * Return cur_rr_node_side & cur_rr_node_index + */ +void get_rr_node_side_and_index_in_sb_info(t_rr_node* cur_rr_node, + t_sb cur_sb_info, + enum PORTS rr_node_direction, + OUTP int* cur_rr_node_side, + OUTP int* cur_rr_node_index) { + int index, side; + + /* Count the number of existence of cur_rr_node in cur_sb_info + * It could happen that same cur_rr_node appears on different sides of a SB + * For example, a routing track go vertically across the SB. + * Then its corresponding rr_node appears on both TOP and BOTTOM sides of this SB. + * We need to ensure that the found rr_node has the same direction as user want. + * By specifying the direction of rr_node, There should be only one rr_node can satisfy! + */ + index = -1; + + for (side = 0; side < cur_sb_info.num_sides; side++) { + index = get_rr_node_index_in_sb_info(cur_rr_node, cur_sb_info, side, rr_node_direction); + if (-1 != index) { + break; + } + } + + if (side == cur_sb_info.num_sides) { + /* we find nothing */ + side = -1; + } + + (*cur_rr_node_side) = side; + (*cur_rr_node_index) = index; + + return; +} + +/* Get the index of a given rr_node in a CB_info */ +int get_rr_node_index_in_cb_info(t_rr_node* cur_rr_node, + t_cb cur_cb_info, + int chan_side, enum PORTS rr_node_direction) { + int inode, cnt, ret; + + cnt = 0; + ret = -1; + + /* Depending on the type of rr_node, we search different arrays */ + switch (cur_rr_node->type) { + case CHANX: + case CHANY: + for (inode = 0; inode < cur_cb_info.chan_width[chan_side]; inode++) { + if ((cur_rr_node == cur_cb_info.chan_rr_node[chan_side][inode]) + /* Check if direction meets specification */ + &&(rr_node_direction == cur_cb_info.chan_rr_node_direction[chan_side][inode])) { + cnt++; + ret = inode; + } + } + break; + case IPIN: + for (inode = 0; inode < cur_cb_info.num_ipin_rr_nodes[chan_side]; inode++) { + if (cur_rr_node == cur_cb_info.ipin_rr_node[chan_side][inode]) { + cnt++; + ret = inode; + } + } + break; + case OPIN: + for (inode = 0; inode < cur_cb_info.num_opin_rr_nodes[chan_side]; inode++) { + if (cur_rr_node == cur_cb_info.opin_rr_node[chan_side][inode]) { + cnt++; + ret = inode; + } + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid cur_rr_node type! Should be [CHANX|CHANY|IPIN|OPIN]\n", __FILE__, __LINE__); + exit(1); + } + + assert((0 == cnt)||(1 == cnt)); + + return ret; /* Return an invalid value: nonthing is found*/ +} + +/* Determine the coordinate of a chan_rr_node in a SB_info + * Return chan_type & chan_rr_node_x & chan_rr_node_y + */ +void get_chan_rr_node_coorindate_in_sb_info(t_sb cur_sb_info, + int chan_rr_node_side, + t_rr_type* chan_type, + int* chan_rr_node_x, int* chan_rr_node_y) { + int sb_x = cur_sb_info.x; + int sb_y = cur_sb_info.y; + + switch (chan_rr_node_side) { + case 0: /*TOP*/ + (*chan_type) = CHANY; + (*chan_rr_node_x) = sb_x; + (*chan_rr_node_y) = sb_y + 1; + break; + case 1: /*RIGHT*/ + (*chan_type) = CHANX; + (*chan_rr_node_x) = sb_x + 1; + (*chan_rr_node_y) = sb_y; + break; + case 2: /*BOTTOM*/ + (*chan_type) = CHANY; + (*chan_rr_node_x) = sb_x; + (*chan_rr_node_y) = sb_y; + break; + case 3: /*LEFT*/ + (*chan_type) = CHANX; + (*chan_rr_node_x) = sb_x; + (*chan_rr_node_y) = sb_y; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s, [LINE%d])Invalid side!\n", __FILE__, __LINE__); + exit(1); + } + + return; +} + +/* Get the side and index of a given rr_node in a SB_info + * Return cur_rr_node_side & cur_rr_node_index + */ +void get_rr_node_side_and_index_in_cb_info(t_rr_node* cur_rr_node, + t_cb cur_cb_info, + enum PORTS rr_node_direction, + OUTP int* cur_rr_node_side, + OUTP int* cur_rr_node_index) { + int index, side; + + index = -1; + + for (side = 0; side < cur_cb_info.num_sides; side++) { + index = get_rr_node_index_in_cb_info(cur_rr_node, cur_cb_info, side, rr_node_direction); + if (-1 != index) { + break; + } + } + + if (side == cur_cb_info.num_sides) { + /* we find nothing */ + side = -1; + } + + (*cur_rr_node_side) = side; + (*cur_rr_node_index) = index; + + return; +} + + +/***** Recursively Backannotate parasitic_net_num for a rr_node*****/ +void rec_backannotate_rr_node_net_num(int LL_num_rr_nodes, + t_rr_node* LL_rr_node, + int src_node_index) { + int iedge, to_node; + + /* Traversal until + * 1. we meet a sink + * 2. None of the edges propagates this net_num + */ + for (iedge = 0; iedge < LL_rr_node[src_node_index].num_edges; iedge++) { + to_node = LL_rr_node[src_node_index].edges[iedge]; + assert(OPEN != LL_rr_node[to_node].prev_node); + if (src_node_index == LL_rr_node[to_node].prev_node) { + assert(iedge == LL_rr_node[to_node].prev_edge); + /* assert(LL_rr_node[src_node_index].net_num == LL_rr_node[to_node].net_num); */ + /* Propagate the net_num */ + LL_rr_node[to_node].net_num = LL_rr_node[src_node_index].net_num; + /* Make the flag which indicates a changing has been made */ + if (LL_rr_node[to_node].vpack_net_num != LL_rr_node[src_node_index].vpack_net_num) { + LL_rr_node[to_node].vpack_net_num_changed = TRUE; + } + LL_rr_node[to_node].vpack_net_num = LL_rr_node[src_node_index].vpack_net_num; + /* Go recursively */ + rec_backannotate_rr_node_net_num(LL_num_rr_nodes, LL_rr_node, to_node); + } + } + + return; +} + +/***** Backannotate activity information to nets *****/ +/* Mark mapped rr_nodes with net_num*/ +static +void backannotate_rr_nodes_parasitic_net_info() { + int inode; + + /* Start from all the SOURCEs */ + for (inode = 0; inode < num_rr_nodes; inode++) { + /* We care only OPINs + * or a contant generator */ + if ((OPIN != rr_node[inode].type) + || (!(SOURCE != rr_node[inode].type) + && (0 == rr_node[inode].num_drive_rr_nodes))) { + continue; + } + /* Bypass unmapped pins */ + if (OPEN == rr_node[inode].vpack_net_num) { + continue; + } + /* Forward to all the downstream rr_nodes */ + rec_backannotate_rr_node_net_num(num_rr_nodes, rr_node, inode); + } + + return; +} + +static +void backannotate_clb_nets_init_val() { + int inet, iblk, isink; + int iter_cnt, iter_end; + + /* Analysis init values !!! */ + for (inet = 0; inet < num_logical_nets; inet++) { + assert (NULL != vpack_net[inet].spice_net_info); + /* if the source is a inpad or dff, we update the initial value */ + iblk = vpack_net[inet].node_block[0]; + switch (logical_block[iblk].type) { + case VPACK_INPAD: + logical_block[iblk].init_val = vpack_net[inet].spice_net_info->init_val; + assert((0 == logical_block[iblk].init_val)||(1 == logical_block[iblk].init_val)); + break; + case VPACK_LATCH: + vpack_net[inet].spice_net_info->init_val = 0; + /*TODO:may be more flexible, for ff, set or reset may be used in first cock cycle */ + logical_block[iblk].init_val = vpack_net[inet].spice_net_info->init_val; + assert((0 == logical_block[iblk].init_val)||(1 == logical_block[iblk].init_val)); + break; + case VPACK_OUTPAD: + case VPACK_COMB: + case VPACK_EMPTY: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid logical block type!\n", + __FILE__, __LINE__); + exit(1); + } + } + /* Iteratively Update LUT init_val */ + iter_cnt = 0; + while(1) { + iter_end = 1; + for (inet = 0; inet < num_logical_nets; inet++) { + assert(NULL != vpack_net[inet].spice_net_info); + /* if the source is a inpad or dff, we update the initial value */ + iblk = vpack_net[inet].node_block[0]; + switch (logical_block[iblk].type) { + case VPACK_COMB: + vpack_net[inet].spice_net_info->init_val = get_lut_output_init_val(&(logical_block[iblk])); + if (logical_block[iblk].init_val != vpack_net[inet].spice_net_info->init_val) { + iter_end = 0; + } + logical_block[iblk].init_val = vpack_net[inet].spice_net_info->init_val; + break; + case VPACK_INPAD: + case VPACK_LATCH: + case VPACK_OUTPAD: + case VPACK_EMPTY: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid logical block type!\n", + __FILE__, __LINE__); + exit(1); + } + } + iter_cnt++; + if (1 == iter_end) { + break; + } + } + vpr_printf(TIO_MESSAGE_INFO,"Determine LUTs initial outputs ends in %d iterations.\n", iter_cnt); + /* Update OUTPAD init_val */ + for (inet = 0; inet < num_logical_nets; inet++) { + assert(NULL != vpack_net[inet].spice_net_info); + /* if the source is a inpad or dff, we update the initial value */ + for (isink = 0; isink < vpack_net[inet].num_sinks; isink++) { + iblk = vpack_net[inet].node_block[isink]; + switch (logical_block[iblk].type) { + case VPACK_OUTPAD: + logical_block[iblk].init_val = vpack_net[inet].spice_net_info->init_val; + break; + case VPACK_COMB: + case VPACK_INPAD: + case VPACK_LATCH: + case VPACK_EMPTY: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid logical block type!\n", + __FILE__, __LINE__); + exit(1); + } + } + } + + /* Initial values for clb nets !!! */ + for (inet = 0; inet < num_nets; inet++) { + assert (NULL != clb_net[inet].spice_net_info); + /* if the source is a inpad or dff, we update the initial value */ + clb_net[inet].spice_net_info->init_val = vpack_net[clb_to_vpack_net_mapping[inet]].spice_net_info->init_val; + } + + return; +} + +static +void backannotate_clb_nets_act_info() { + int inet; + + /* Free all spice_net_info and reallocate */ + for (inet = 0; inet < num_logical_nets; inet++) { + if (NULL == vpack_net[inet].spice_net_info) { + /* Allocate */ + vpack_net[inet].spice_net_info = (t_spice_net_info*)my_malloc(sizeof(t_spice_net_info)); + } + /* Initialize to zero */ + init_spice_net_info(vpack_net[inet].spice_net_info); + /* Load activity info */ + vpack_net[inet].spice_net_info->probability = vpack_net[inet].net_power->probability; + vpack_net[inet].spice_net_info->density = vpack_net[inet].net_power->density; + /* SPECIAL for SPICE simulator: init_value is opposite to probability + * when density is not zero. + */ + /* + if (0. != vpack_net[inet].spice_net_info->density) { + vpack_net[inet].spice_net_info->init_val = 1 - vpack_net[inet].spice_net_info->probability; + } + */ + } + + /* Free all spice_net_info and reallocate */ + for (inet = 0; inet < num_nets; inet++) { + if (NULL == clb_net[inet].spice_net_info) { + /* Allocate */ + clb_net[inet].spice_net_info = (t_spice_net_info*)my_malloc(sizeof(t_spice_net_info)); + } + /* Initialize to zero */ + init_spice_net_info(clb_net[inet].spice_net_info); + /* Load activity info */ + clb_net[inet].spice_net_info->probability = vpack_net[clb_to_vpack_net_mapping[inet]].spice_net_info->probability; + clb_net[inet].spice_net_info->density = vpack_net[clb_to_vpack_net_mapping[inet]].spice_net_info->density; + clb_net[inet].spice_net_info->init_val = vpack_net[clb_to_vpack_net_mapping[inet]].spice_net_info->init_val; + } + + return; +} + +void free_clb_nets_spice_net_info() { + int inet; + + /* Free all spice_net_info and reallocate */ + for (inet = 0; inet < num_nets; inet++) { + my_free(clb_net[inet].spice_net_info); + } + + for (inet = 0; inet < num_logical_nets; inet++) { + my_free(vpack_net[inet].spice_net_info); + } + + return; +} + +static +void build_prev_node_list_rr_nodes(int LL_num_rr_nodes, + t_rr_node* LL_rr_node) { + int inode, iedge, to_node, cur; + /* int jnode, switch_box_x, switch_box_y, chan_side, switch_index; */ + int* cur_index = (int*)my_malloc(sizeof(int)*LL_num_rr_nodes); + + /* This function is not timing-efficient, I comment it */ + /* + for (inode = 0; inode < LL_num_rr_nodes; inode++) { + find_prev_rr_nodes_with_src(&(LL_rr_nodes[inode]), + &(LL_rr_nodes[inode].num_drive_rr_nodes), + &(LL_rr_nodes[inode].drive_rr_nodes), + &(LL_rr_nodes[inode].drive_switches)); + } + */ + for (inode = 0; inode < LL_num_rr_nodes; inode++) { + /* Malloc */ + LL_rr_node[inode].num_drive_rr_nodes = LL_rr_node[inode].fan_in; + if (0 == LL_rr_node[inode].fan_in) { + continue; + } + LL_rr_node[inode].drive_rr_nodes = (t_rr_node**)my_malloc(sizeof(t_rr_node*)*LL_rr_node[inode].num_drive_rr_nodes); + LL_rr_node[inode].drive_switches = (int*)my_malloc(sizeof(int)*LL_rr_node[inode].num_drive_rr_nodes); + } + /* Initialize */ + for (inode = 0; inode < LL_num_rr_nodes; inode++) { + cur_index[inode] = 0; + for (iedge = 0; iedge < LL_rr_node[inode].num_drive_rr_nodes; iedge++) { + LL_rr_node[inode].drive_rr_nodes[iedge] = NULL; + LL_rr_node[inode].drive_switches[iedge] = -1; + } + } + /* Fill */ + for (inode = 0; inode < LL_num_rr_nodes; inode++) { + for (iedge = 0; iedge < LL_rr_node[inode].num_edges; iedge++) { + to_node = LL_rr_node[inode].edges[iedge]; + cur = cur_index[to_node]; + LL_rr_node[to_node].drive_rr_nodes[cur] = &(LL_rr_node[inode]); + LL_rr_node[to_node].drive_switches[cur] = LL_rr_node[inode].switches[iedge]; + /* Update cur_index[to_node]*/ + assert(NULL != LL_rr_node[to_node].drive_rr_nodes[cur]); + cur_index[to_node]++; + } + } + /* Check */ + for (inode = 0; inode < LL_num_rr_nodes; inode++) { + assert(cur_index[inode] == LL_rr_node[inode].num_drive_rr_nodes); + } + + /* TODO: fill the sb_drive_rr_nodes */ + //for (inode = 0; inode < LL_num_rr_nodes; inode++) { + // /* Initial */ + // LL_rr_node[inode].sb_num_drive_rr_nodes = 0; + // LL_rr_node[inode].sb_drive_rr_nodes = NULL; + // LL_rr_node[inode].sb_drive_switches = NULL; + // /* Find SB source rr nodes: channels*/ + // switch (LL_rr_node[inode].type) { + // case CHANX: + // assert(LL_rr_node[inode].ylow == LL_rr_node[inode].yhigh); + // switch (LL_rr_node[inode].direction) { + // case INC_DIRECTION: + // switch_box_x = LL_rr_node[inode].xlow-1; + // switch_box_y = LL_rr_node[inode].ylow; + // chan_side = RIGHT; + // break; + // case DEC_DIRECTION: + // switch_box_x = LL_rr_node[inode].xhigh; + // switch_box_y = LL_rr_node[inode].yhigh; + // chan_side = LEFT; + // break; + // case BI_DIRECTION: + // vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Bidirectional routing wires are not supported!\n", + // __FILE__, __LINE__); + // exit(1); + // default: + // vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid rr_node direction!\n", + // __FILE__, __LINE__); + // exit(1); + // } + // find_drive_rr_nodes_switch_box(switch_box_x, switch_box_y, &(LL_rr_node[inode]), chan_side, 0, + // &(LL_rr_node[inode].sb_num_drive_rr_nodes), + // &(LL_rr_node[inode].sb_drive_rr_nodes), &switch_index); + // /* fill the sb_drive_switches */ + // LL_rr_node[inode].sb_drive_switches = (int*)my_malloc(sizeof(int)*LL_rr_node[inode].sb_num_drive_rr_nodes); + // for (jnode = 0; jnode < LL_rr_node[inode].sb_num_drive_rr_nodes; jnode++) { + // LL_rr_node[inode].sb_drive_switches[jnode] = switch_index; + // } + // break; + // case CHANY: + // /* TODO: fill the sb_drive_rr_nodes */ + // assert(LL_rr_node[inode].xlow == LL_rr_node[inode].xhigh); + // switch (LL_rr_node[inode].direction) { + // case INC_DIRECTION: + // switch_box_x = LL_rr_node[inode].xlow; + // switch_box_y = LL_rr_node[inode].ylow-1; + // chan_side = TOP; + // break; + // case DEC_DIRECTION: + // switch_box_x = LL_rr_node[inode].xhigh; + // switch_box_y = LL_rr_node[inode].yhigh; + // chan_side = BOTTOM; + // break; + // case BI_DIRECTION: + // vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Bidirectional routing wires are not supported!\n", + // __FILE__, __LINE__); + // exit(1); + // default: + // vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid rr_node direction!\n", + // __FILE__, __LINE__); + // exit(1); + // } + // find_drive_rr_nodes_switch_box(switch_box_x, switch_box_y, &(LL_rr_node[inode]), chan_side, 0, + // &(LL_rr_node[inode].sb_num_drive_rr_nodes), + // &(LL_rr_node[inode].sb_drive_rr_nodes), &switch_index); + // /* fill the sb_drive_switches */ + // LL_rr_node[inode].sb_drive_switches = (int*)my_malloc(sizeof(int)*LL_rr_node[inode].sb_num_drive_rr_nodes); + // for (jnode = 0; jnode < LL_rr_node[inode].sb_num_drive_rr_nodes; jnode++) { + // LL_rr_node[inode].sb_drive_switches[jnode] = switch_index; + // } + // break; + // case SOURCE: + // case OPIN: + // case SINK: + // case IPIN: + // case NUM_RR_TYPES: + // break; + // default: + // vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid rr_node type!\n", + // __FILE__, __LINE__); + // exit(1); + // } + //} + + return; +} + +static +void set_one_pb_rr_node_default_prev_node_edge(t_rr_node* pb_rr_graph, + t_pb_graph_pin* des_pb_graph_pin, + int mode_index) { + int iedge, node_index, prev_node, prev_edge; + + assert(NULL != des_pb_graph_pin); + assert(NULL != pb_rr_graph); + + node_index = des_pb_graph_pin->pin_count_in_cluster; + assert(OPEN == pb_rr_graph[node_index].net_num); + + /* if this pin has 0 driver, return OPEN */ + if (0 == des_pb_graph_pin->num_input_edges) { + pb_rr_graph[node_index].prev_node = OPEN; + pb_rr_graph[node_index].prev_edge = OPEN; + return; + } + + prev_node = OPEN; + prev_edge = OPEN; + + /* Set default prev_node */ + for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { + if (mode_index != des_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode_index) { + continue; + } + prev_node = des_pb_graph_pin->input_edges[iedge]->input_pins[0]->pin_count_in_cluster; + break; + } + + /* Find prev_edge */ + for (iedge = 0; iedge < pb_rr_graph[prev_node].pb_graph_pin->num_output_edges; iedge++) { + check_pb_graph_edge(*(pb_rr_graph[prev_node].pb_graph_pin->output_edges[iedge])); + if (node_index == pb_rr_graph[prev_node].pb_graph_pin->output_edges[iedge]->output_pins[0]->pin_count_in_cluster) { + prev_edge = iedge; + break; + } + } + /* Make sure we succeed */ + assert(OPEN != prev_node); + assert(OPEN != prev_edge); + /* backannotate */ + pb_rr_graph[node_index].prev_node = prev_node; + pb_rr_graph[node_index].prev_edge = prev_edge; + + return; +} + +/* Mark the prev_edge and prev_node of all the rr_nodes in complex blocks */ +static +void back_annotate_one_pb_rr_node_map_info_rec(t_pb* cur_pb) { + int ipb, jpb, select_mode_index; + int iport, ipin, node_index; + t_rr_node* pb_rr_nodes = NULL; + t_pb_graph_node* child_pb_graph_node; + + /* Return when we meet a null pb */ + if (NULL == cur_pb) { + return; + } + + /* Reach a leaf, return */ + if ((0 == cur_pb->pb_graph_node->pb_type->num_modes) + ||(NULL == cur_pb->child_pbs)) { + return; + } + + select_mode_index = cur_pb->mode; + + /* For all the input/output/clock pins of this pb, + * check the net_num and assign default prev_node, prev_edge + */ + + /* We check output_pins of cur_pb_graph_node and its the input_edges + * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node + * child_pb_graph_node.output_pins -----------------> cur_pb_graph_node.outpins + * /|\ + * | + * input_pins, edges, output_pins + */ + for (iport = 0; iport < cur_pb->pb_graph_node->num_output_ports; iport++) { + for (ipin = 0; ipin < cur_pb->pb_graph_node->num_output_pins[iport]; ipin++) { + /* Get the selected edge of current pin*/ + pb_rr_nodes = cur_pb->rr_graph; + node_index = cur_pb->pb_graph_node->output_pins[iport][ipin].pin_count_in_cluster; + /* If we find an OPEN net, try to find the parasitic net_num*/ + if (OPEN == pb_rr_nodes[node_index].net_num) { + set_one_pb_rr_node_default_prev_node_edge(pb_rr_nodes, + &(cur_pb->pb_graph_node->output_pins[iport][ipin]), + select_mode_index); + } else { + pb_rr_nodes[node_index].vpack_net_num = pb_rr_nodes[node_index].net_num; + } + } + } + + /* We check input_pins of child_pb_graph_node and its the input_edges + * Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node + * cur_pb_graph_node.input_pins -----------------> child_pb_graph_node.input_pins + * /|\ + * | + * input_pins, edges, output_pins + */ + for (ipb = 0; ipb < cur_pb->pb_graph_node->pb_type->modes[select_mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb->pb_graph_node->pb_type->modes[select_mode_index].pb_type_children[ipb].num_pb; jpb++) { + child_pb_graph_node = &(cur_pb->pb_graph_node->child_pb_graph_nodes[select_mode_index][ipb][jpb]); + /* For each child_pb_graph_node input pins*/ + for (iport = 0; iport < child_pb_graph_node->num_input_ports; iport++) { + for (ipin = 0; ipin < child_pb_graph_node->num_input_pins[iport]; ipin++) { + /* Get the selected edge of current pin*/ + pb_rr_nodes = cur_pb->rr_graph; + node_index = child_pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster; + /* If we find an OPEN net, try to find the parasitic net_num*/ + if (OPEN == pb_rr_nodes[node_index].net_num) { + set_one_pb_rr_node_default_prev_node_edge(pb_rr_nodes, + &(child_pb_graph_node->input_pins[iport][ipin]), + select_mode_index); + } else { + pb_rr_nodes[node_index].vpack_net_num = pb_rr_nodes[node_index].net_num; + } + } + } + /* For each child_pb_graph_node clock pins*/ + for (iport = 0; iport < child_pb_graph_node->num_clock_ports; iport++) { + for (ipin = 0; ipin < child_pb_graph_node->num_clock_pins[iport]; ipin++) { + /* Get the selected edge of current pin*/ + pb_rr_nodes = cur_pb->rr_graph; + node_index = child_pb_graph_node->clock_pins[iport][ipin].pin_count_in_cluster; + /* If we find an OPEN net, try to find the parasitic net_num*/ + if (OPEN == pb_rr_nodes[node_index].net_num) { + set_one_pb_rr_node_default_prev_node_edge(pb_rr_nodes, + &(child_pb_graph_node->clock_pins[iport][ipin]), + select_mode_index); + } else { + pb_rr_nodes[node_index].vpack_net_num = pb_rr_nodes[node_index].net_num; + } + } + } + } + } + + /* Go recursively */ + for (ipb = 0; ipb < cur_pb->pb_graph_node->pb_type->modes[select_mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb->pb_graph_node->pb_type->modes[select_mode_index].pb_type_children[ipb].num_pb; jpb++) { + if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { + back_annotate_one_pb_rr_node_map_info_rec(&(cur_pb->child_pbs[ipb][jpb])); + } + } + } + + return; +} + +/* Mark all prev_node & prev_edge for pb_rr_nodes */ +static +void back_annotate_pb_rr_node_map_info() { + int iblk; + + /* Foreach grid */ + for (iblk = 0; iblk < num_blocks; iblk++) { + /* By pass IO */ + if (IO_TYPE == block[iblk].type) { + continue; + } + back_annotate_one_pb_rr_node_map_info_rec(block[iblk].pb); + } + + return; +} + +/* Set the net_num for one pb_rr_node according to prev_node */ +static +void set_one_pb_rr_node_net_num(t_rr_node* pb_rr_graph, + t_pb_graph_pin* des_pb_graph_pin) { + + int node_index, prev_node, prev_edge; + + assert(NULL != des_pb_graph_pin); + assert(NULL != pb_rr_graph); + + node_index = des_pb_graph_pin->pin_count_in_cluster; + assert(OPEN == pb_rr_graph[node_index].net_num); + + /* if this pin has 0 driver, return OPEN */ + if (0 == des_pb_graph_pin->num_input_edges) { + pb_rr_graph[node_index].net_num= OPEN; + pb_rr_graph[node_index].vpack_net_num= OPEN; + return; + } + + prev_node = pb_rr_graph[node_index].prev_node; + prev_edge = pb_rr_graph[node_index].prev_edge; + assert(OPEN != prev_node); + assert(OPEN != prev_edge); + + /* Set default prev_node */ + check_pb_graph_edge(*(pb_rr_graph[prev_node].pb_graph_pin->output_edges[prev_edge])); + assert(node_index == pb_rr_graph[prev_node].pb_graph_pin->output_edges[prev_edge]->output_pins[0]->pin_count_in_cluster); + pb_rr_graph[node_index].net_num = pb_rr_graph[prev_node].net_num; + pb_rr_graph[node_index].vpack_net_num = pb_rr_graph[prev_node].net_num; + + return; +} + +/* Mark the net_num of all the rr_nodes in complex blocks */ +static +void backannotate_one_pb_rr_nodes_net_info_rec(t_pb* cur_pb) { + int ipb, jpb, select_mode_index; + int iport, ipin, node_index; + t_rr_node* pb_rr_nodes = NULL; + t_pb_graph_node* child_pb_graph_node = NULL; + + /* Return when we meet a null pb */ + assert (NULL != cur_pb); + + /* Reach a leaf, return */ + if ((0 == cur_pb->pb_graph_node->pb_type->num_modes) + ||(NULL == cur_pb->child_pbs)) { + return; + } + + select_mode_index = cur_pb->mode; + + /* For all the input/output/clock pins of this pb, + * check the net_num and assign default prev_node, prev_edge + */ + + /* We check input_pins of child_pb_graph_node and its the input_edges + * Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node + * cur_pb_graph_node.input_pins -----------------> child_pb_graph_node.input_pins + * /|\ + * | + * input_pins, edges, output_pins + */ + for (ipb = 0; ipb < cur_pb->pb_graph_node->pb_type->modes[select_mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb->pb_graph_node->pb_type->modes[select_mode_index].pb_type_children[ipb].num_pb; jpb++) { + child_pb_graph_node = &(cur_pb->pb_graph_node->child_pb_graph_nodes[select_mode_index][ipb][jpb]); + /* For each child_pb_graph_node input pins*/ + for (iport = 0; iport < child_pb_graph_node->num_input_ports; iport++) { + for (ipin = 0; ipin < child_pb_graph_node->num_input_pins[iport]; ipin++) { + /* Get the selected edge of current pin*/ + pb_rr_nodes = cur_pb->rr_graph; + node_index = child_pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster; + /* If we find an OPEN net, try to find the parasitic net_num*/ + if (OPEN == pb_rr_nodes[node_index].net_num) { + set_one_pb_rr_node_net_num(pb_rr_nodes, &(child_pb_graph_node->input_pins[iport][ipin])); + } else { + assert(pb_rr_nodes[node_index].net_num == pb_rr_nodes[node_index].vpack_net_num); + } + } + } + /* For each child_pb_graph_node clock pins*/ + for (iport = 0; iport < child_pb_graph_node->num_clock_ports; iport++) { + for (ipin = 0; ipin < child_pb_graph_node->num_clock_pins[iport]; ipin++) { + /* Get the selected edge of current pin*/ + pb_rr_nodes = cur_pb->rr_graph; + node_index = child_pb_graph_node->clock_pins[iport][ipin].pin_count_in_cluster; + /* If we find an OPEN net, try to find the parasitic net_num*/ + if (OPEN == pb_rr_nodes[node_index].net_num) { + set_one_pb_rr_node_net_num(pb_rr_nodes, &(child_pb_graph_node->clock_pins[iport][ipin])); + } else { + assert(pb_rr_nodes[node_index].net_num == pb_rr_nodes[node_index].vpack_net_num); + } + } + } + } + } + + /* Go recursively, prior to update the output pins. + * Because output pins are depend on the deepest pbs + */ + for (ipb = 0; ipb < cur_pb->pb_graph_node->pb_type->modes[select_mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb->pb_graph_node->pb_type->modes[select_mode_index].pb_type_children[ipb].num_pb; jpb++) { + if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { + backannotate_one_pb_rr_nodes_net_info_rec(&(cur_pb->child_pbs[ipb][jpb])); + } + } + } + + /* We check output_pins of cur_pb_graph_node and its the input_edges + * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node + * child_pb_graph_node.output_pins -----------------> cur_pb_graph_node.outpins + * /|\ + * | + * input_pins, edges, output_pins + */ + for (iport = 0; iport < cur_pb->pb_graph_node->num_output_ports; iport++) { + for (ipin = 0; ipin < cur_pb->pb_graph_node->num_output_pins[iport]; ipin++) { + /* Get the selected edge of current pin*/ + pb_rr_nodes = cur_pb->rr_graph; + node_index = cur_pb->pb_graph_node->output_pins[iport][ipin].pin_count_in_cluster; + /* If we find an OPEN net, try to find the parasitic net_num*/ + if (OPEN == pb_rr_nodes[node_index].net_num) { + set_one_pb_rr_node_net_num(pb_rr_nodes, &(cur_pb->pb_graph_node->output_pins[iport][ipin])); + } else { + assert(pb_rr_nodes[node_index].net_num == pb_rr_nodes[node_index].vpack_net_num); + } + } + } + + return; +} + +static +void backannotate_pb_rr_nodes_net_info() { + int iblk; + + /* Foreach grid */ + for (iblk = 0; iblk < num_blocks; iblk++) { + /* By pass IO */ + if (IO_TYPE == block[iblk].type) { + continue; + } + backannotate_one_pb_rr_nodes_net_info_rec(block[iblk].pb); + } + + return; +} + +/* Mark the prev_edge and prev_node of all the rr_nodes in global routing */ +static +void back_annotate_rr_node_map_info() { + int inode, jnode, inet; + int next_node, iedge; + t_trace* tptr; + t_rr_type rr_type; + + /* 1st step: Set all the configurations to default. + * rr_nodes select edge[0] + */ + for (inode = 0; inode < num_rr_nodes; inode++) { + rr_node[inode].prev_node = OPEN; + /* set 0 if we want print all unused mux!!!*/ + rr_node[inode].prev_edge = OPEN; + /* Initial all the net_num*/ + rr_node[inode].net_num = OPEN; + rr_node[inode].vpack_net_num = OPEN; + } + for (inode = 0; inode < num_rr_nodes; inode++) { + if (0 == rr_node[inode].num_edges) { + continue; + } + assert(0 < rr_node[inode].num_edges); + for (iedge = 0; iedge < rr_node[inode].num_edges; iedge++) { + jnode = rr_node[inode].edges[iedge]; + if (&(rr_node[inode]) == rr_node[jnode].drive_rr_nodes[0]) { + rr_node[jnode].prev_node = inode; + rr_node[jnode].prev_edge = iedge; + } + } + } + + /* 2nd step: With the help of trace, we back-annotate */ + for (inet = 0; inet < num_nets; inet++) { + if (TRUE == clb_net[inet].is_global) { + continue; + } + tptr = trace_head[inet]; + while (tptr != NULL) { + inode = tptr->index; + rr_type = rr_node[inode].type; + /* Net num */ + rr_node[inode].net_num = inet; + rr_node[inode].vpack_net_num = clb_to_vpack_net_mapping[inet]; + //printf("Mark rr_node net_num for vpack_net(name=%s)..\n", + // vpack_net[rr_node[inode].vpack_net_num].name); + assert(OPEN != rr_node[inode].net_num); + assert(OPEN != rr_node[inode].vpack_net_num); + switch (rr_type) { + case SINK: + /* Nothing should be done. This supposed to the end of a trace*/ + break; + case IPIN: + case CHANX: + case CHANY: + case OPIN: + case SOURCE: + /* SINK(IO/Pad) is the end of a routing path. Should configure its prev_edge and prev_node*/ + /* We care the next rr_node, this one is driving, which we have to configure + */ + assert(NULL != tptr->next); + next_node = tptr->next->index; + assert((!(0 > next_node))&&(next_node < num_rr_nodes)); + /* Prev_node */ + rr_node[next_node].prev_node = inode; + /* Prev_edge */ + rr_node[next_node].prev_edge = OPEN; + for (iedge = 0; iedge < rr_node[inode].num_edges; iedge++) { + if (next_node == rr_node[inode].edges[iedge]) { + rr_node[next_node].prev_edge = iedge; + break; + } + } + assert(OPEN != rr_node[next_node].prev_edge); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid traceback element type.\n"); + exit(1); + } + tptr = tptr->next; + } + } + + return; +} + +void backup_one_pb_rr_node_pack_prev_node_edge(t_rr_node* pb_rr_node) { + + pb_rr_node->prev_node_in_pack = pb_rr_node->prev_node; + pb_rr_node->prev_edge_in_pack = pb_rr_node->prev_edge; + pb_rr_node->net_num_in_pack = pb_rr_node->net_num; + pb_rr_node->prev_node = OPEN; + pb_rr_node->prev_edge = OPEN; + + return; +} + +/* During routing stage, VPR swap logic equivalent pins + * which potentially changes the packing results (prev_node, prev_edge) in local routing + * The following functions are to update the local routing results to match them with routing results + */ +void update_one_grid_pack_prev_node_edge(int x, int y) { + int iblk, blk_id, ipin, iedge, jedge, inode; + int pin_global_rr_node_id, vpack_net_id, class_id; + t_type_ptr type = NULL; + t_pb* pb = NULL; + t_rr_node* local_rr_graph = NULL; + + /* Assert */ + assert((!(x < 0))&&(x < (nx + 2))); + assert((!(y < 0))&&(y < (ny + 2))); + + type = grid[x][y].type; + /* Bypass IO_TYPE*/ + if ((EMPTY_TYPE == type)||(IO_TYPE == type)) { + //if ((EMPTY_TYPE == type)) { + return; + } + for (iblk = 0; iblk < grid[x][y].usage; iblk++) { + blk_id = grid[x][y].blocks[iblk]; + if ((IO_TYPE != type)) { + assert(block[blk_id].x == x); + assert(block[blk_id].y == y); + } + pb = block[blk_id].pb; + assert(NULL != pb); + local_rr_graph = pb->rr_graph; + /* Foreach local rr_node*/ + for (ipin = 0; ipin < type->num_pins; ipin++) { + class_id = type->pin_class[ipin]; + if (DRIVER == type->class_inf[class_id].type) { + /* Find the pb net_num and update OPIN net_num */ + pin_global_rr_node_id = get_rr_node_index(x, y, OPIN, ipin, rr_node_indices); + if (OPEN == rr_node[pin_global_rr_node_id].net_num) { + local_rr_graph[ipin].net_num_in_pack = local_rr_graph[ipin].net_num; + local_rr_graph[ipin].net_num = OPEN; + local_rr_graph[ipin].vpack_net_num = OPEN; + //local_rr_graph[ipin].prev_node = 0; + //local_rr_graph[ipin].prev_edge = 0; + continue; /* bypass non-mapped OPIN */ + } + /* back annotate pb ! */ + rr_node[pin_global_rr_node_id].pb = pb; + vpack_net_id = clb_to_vpack_net_mapping[rr_node[pin_global_rr_node_id].net_num]; + //printf("Update post-route pb_rr_graph output: vpack_net_name = %s\n", + // vpack_net[vpack_net_id].name); + /* Special for IO_TYPE */ + if (IO_TYPE == type) { + assert(local_rr_graph[ipin].net_num == rr_node[pin_global_rr_node_id].vpack_net_num); + local_rr_graph[ipin].net_num_in_pack = local_rr_graph[ipin].net_num; + continue; + } + assert(ipin == local_rr_graph[ipin].pb_graph_pin->pin_count_in_cluster); + /* Update net_num */ + local_rr_graph[ipin].net_num_in_pack = local_rr_graph[ipin].net_num; + local_rr_graph[ipin].net_num = vpack_net_id; + local_rr_graph[ipin].vpack_net_num = vpack_net_id; + /* TODO: this is not so efficient... */ + for (iedge = 0; iedge < local_rr_graph[ipin].pb_graph_pin->num_input_edges; iedge++) { + check_pb_graph_edge(*(local_rr_graph[ipin].pb_graph_pin->input_edges[iedge])); + inode = local_rr_graph[ipin].pb_graph_pin->input_edges[iedge]->input_pins[0]->pin_count_in_cluster; + /* Update prev_node, prev_edge if needed*/ + if (vpack_net_id == local_rr_graph[inode].net_num) { + /* Backup prev_node, prev_edge */ + backup_one_pb_rr_node_pack_prev_node_edge(&(local_rr_graph[ipin])); + local_rr_graph[ipin].prev_node = inode; + for (jedge = 0; jedge < local_rr_graph[inode].pb_graph_pin->num_output_edges; jedge++) { + if (local_rr_graph[ipin].pb_graph_pin == local_rr_graph[inode].pb_graph_pin->output_edges[jedge]->output_pins[0]) { + local_rr_graph[ipin].prev_edge = jedge; + break; + } + } + break; + } + } + } else if (RECEIVER == type->class_inf[class_id].type) { + /* Find the global rr_node net_num and update pb net_num */ + pin_global_rr_node_id = get_rr_node_index(x, y, IPIN, ipin, rr_node_indices); + /* Get the index of Vpack net from global rr_node net_num (clb_net index)*/ + if (OPEN == rr_node[pin_global_rr_node_id].net_num) { + local_rr_graph[ipin].net_num_in_pack = local_rr_graph[ipin].net_num; + local_rr_graph[ipin].net_num = OPEN; + local_rr_graph[ipin].vpack_net_num = OPEN; + //local_rr_graph[ipin].prev_node = 0; + //local_rr_graph[ipin].prev_edge = 0; + continue; /* bypass non-mapped IPIN */ + } + /* back annotate pb ! */ + rr_node[pin_global_rr_node_id].pb = pb; + vpack_net_id = clb_to_vpack_net_mapping[rr_node[pin_global_rr_node_id].net_num]; + //printf("Update post-route pb_rr_graph input: vpack_net_name = %s\n", + // vpack_net[vpack_net_id].name); + /* Special for IO_TYPE */ + if (IO_TYPE == type) { + assert(local_rr_graph[ipin].net_num == rr_node[pin_global_rr_node_id].vpack_net_num); + local_rr_graph[ipin].net_num_in_pack = local_rr_graph[ipin].net_num; + continue; + } + assert(ipin == local_rr_graph[ipin].pb_graph_pin->pin_count_in_cluster); + /* Update net_num */ + local_rr_graph[ipin].net_num_in_pack = local_rr_graph[ipin].net_num; + local_rr_graph[ipin].net_num = vpack_net_id; + local_rr_graph[ipin].vpack_net_num = vpack_net_id; + /* TODO: this is not so efficient... */ + for (iedge = 0; iedge < local_rr_graph[ipin].pb_graph_pin->num_output_edges; iedge++) { + check_pb_graph_edge(*(local_rr_graph[ipin].pb_graph_pin->output_edges[iedge])); + inode = local_rr_graph[ipin].pb_graph_pin->output_edges[iedge]->output_pins[0]->pin_count_in_cluster; + /* Update prev_node, prev_edge if needed*/ + if (vpack_net_id == local_rr_graph[inode].net_num) { + /* Backup prev_node, prev_edge */ + backup_one_pb_rr_node_pack_prev_node_edge(&(local_rr_graph[inode])); + local_rr_graph[inode].prev_node = ipin; + local_rr_graph[inode].prev_edge = iedge; + } + } + } else { + continue; /* OPEN PIN */ + } + } + /* Second run to backannoate parasitic OPIN net_num*/ + //for (ipin = 0; ipin < type->num_pins; ipin++) { + // class_id = type->pin_class[ipin]; + // if (DRIVER == type->class_inf[class_id].type) { + // /* Find the pb net_num and update OPIN net_num */ + // pin_global_rr_node_id = get_rr_node_index(x, y, OPIN, ipin, rr_node_indices); + // if (OPEN == local_rr_graph[ipin].net_num) { + // continue; /* bypass non-mapped OPIN */ + // } + // rr_node[pin_global_rr_node_id].net_num = vpack_to_clb_net_mapping[local_rr_graph[ipin].net_num]; + // rr_node[pin_global_rr_node_id].vpack_net_num = vpack_to_clb_net_mapping[local_rr_graph[ipin].net_num]; + // } + //} + } + + return; +} + +void update_grid_pbs_post_route_rr_graph() { + int ix, iy; + t_type_ptr type = NULL; + + for (ix = 0; ix < (nx + 2); ix++) { + for (iy = 0; iy < (ny + 2); iy++) { + type = grid[ix][iy].type; + if (NULL != type) { + /* Backup the packing prev_node and prev_edge */ + update_one_grid_pack_prev_node_edge(ix, iy); + } + } + } + + return; +} + +/* In this function, we update the vpack_net_num in global rr_graph + * from the temp_net_num stored in the top_pb_graph_head + */ +void update_one_unused_grid_output_pins_parasitic_nets(int ix, int iy) { + int iport, ipin; + int pin_global_rr_node_id, class_id, type_pin_index; + t_type_ptr type = NULL; + t_pb_graph_node* top_pb_graph_node = NULL; + + /* Assert */ + assert((!(ix < 0))&&(ix < (nx + 2))); + assert((!(iy < 0))&&(iy < (ny + 2))); + + type = grid[ix][iy].type; + /* Bypass IO_TYPE*/ + if ((EMPTY_TYPE == type)||(IO_TYPE == type)) { + return; + } + + /* Use the temp_net_num of each pb_graph_pin at the top-level + * Update the global rr_graph + */ + top_pb_graph_node = type->pb_graph_head; + assert(NULL != top_pb_graph_node); + + /* We only care the outputs, since the inputs are updated in function + * mark_grid_type_pb_graph_node_pins_temp_net_num(ix, iy); + */ + for (iport = 0; iport < top_pb_graph_node->num_output_ports; iport++) { + for (ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport]; ipin++) { + top_pb_graph_node->output_pins[iport][ipin].temp_net_num = OPEN; + type_pin_index = top_pb_graph_node->output_pins[iport][ipin].pin_count_in_cluster; + class_id = type->pin_class[type_pin_index]; + assert(DRIVER == type->class_inf[class_id].type); + /* Find the pb net_num and update OPIN net_num */ + pin_global_rr_node_id = get_rr_node_index(ix, iy, OPIN, type_pin_index, rr_node_indices); + /* Avoid mistakenly overwrite */ + if (OPEN != rr_node[pin_global_rr_node_id].vpack_net_num) { + continue; + } + rr_node[pin_global_rr_node_id].vpack_net_num = top_pb_graph_node->output_pins[iport][ipin].temp_net_num; + } + } + + return; +} + + +/* SPEICAL: to assign parasitic nets, I modify the net_num in global + * global routing nets to be vpack_net_num. The reason is some vpack nets + * are absorbed into CLBs during packing, therefore they are invisible in + * clb_nets. But indeed, they exist in global routing as parasitic nets. + */ +void update_one_used_grid_pb_pins_parasitic_nets(t_pb* cur_pb, + int ix, int iy) { + int ipin; + int pin_global_rr_node_id,class_id; + t_type_ptr type = NULL; + t_rr_node* local_rr_graph = NULL; + + /* Assert */ + assert((!(ix < 0))&&(ix < (nx + 2))); + assert((!(iy < 0))&&(iy < (ny + 2))); + + type = grid[ix][iy].type; + /* Bypass IO_TYPE*/ + if ((EMPTY_TYPE == type)||(IO_TYPE == type)) { + return; + } + + assert(NULL != cur_pb); + local_rr_graph = cur_pb->rr_graph; + for (ipin = 0; ipin < type->num_pins; ipin++) { + class_id = type->pin_class[ipin]; + if (DRIVER == type->class_inf[class_id].type) { + /* Find the pb net_num and update OPIN net_num */ + pin_global_rr_node_id = get_rr_node_index(ix, iy, OPIN, ipin, rr_node_indices); + assert(local_rr_graph[ipin].vpack_net_num == local_rr_graph[ipin].net_num); + if (OPEN == local_rr_graph[ipin].net_num) { + assert(OPEN == local_rr_graph[ipin].vpack_net_num); + rr_node[pin_global_rr_node_id].net_num = OPEN; + rr_node[pin_global_rr_node_id].vpack_net_num = OPEN; + continue; /* bypass non-mapped OPIN */ + } + assert(ipin == local_rr_graph[ipin].pb_graph_pin->pin_count_in_cluster); + //rr_node[pin_global_rr_node_id].net_num = vpack_to_clb_net_mapping[local_rr_graph[ipin].net_num]; + rr_node[pin_global_rr_node_id].vpack_net_num = local_rr_graph[ipin].vpack_net_num; + } else if (RECEIVER == type->class_inf[class_id].type) { + /* Find the global rr_node net_num and update pb net_num */ + pin_global_rr_node_id = get_rr_node_index(ix, iy, IPIN, ipin, rr_node_indices); + /* Get the index of Vpack net from global rr_node net_num (clb_net index)*/ + if (OPEN == rr_node[pin_global_rr_node_id].vpack_net_num) { + local_rr_graph[ipin].net_num = OPEN; + local_rr_graph[ipin].vpack_net_num = OPEN; + continue; /* bypass non-mapped IPIN */ + } + assert(ipin == local_rr_graph[ipin].pb_graph_pin->pin_count_in_cluster); + local_rr_graph[ipin].net_num = rr_node[pin_global_rr_node_id].vpack_net_num; + local_rr_graph[ipin].vpack_net_num = rr_node[pin_global_rr_node_id].vpack_net_num; + } else { + continue; /* OPEN PIN */ + } + } + + return; +} + + +void update_one_grid_pb_pins_parasitic_nets(int ix, int iy) { + int iblk; + + /* Print all the grid */ + if ((NULL == grid[ix][iy].type)||(0 != grid[ix][iy].offset)) { + return; + } + /* Used blocks */ + for (iblk = 0; iblk < grid[ix][iy].usage; iblk++) { + /* Only for mapped block */ + assert(NULL != block[grid[ix][iy].blocks[iblk]].pb); + /* Mark the temporary net_num for the type pins*/ + mark_one_pb_parasitic_nets(block[grid[ix][iy].blocks[iblk]].pb); + /* Update parasitic nets */ + update_one_used_grid_pb_pins_parasitic_nets(block[grid[ix][iy].blocks[iblk]].pb, + ix, iy); + /* update parasitic nets in each pb */ + backannotate_one_pb_rr_nodes_net_info_rec(block[grid[ix][iy].blocks[iblk]].pb); + } + /* By pass Unused blocks */ + for (iblk = grid[ix][iy].usage; iblk < grid[ix][iy].type->capacity; iblk++) { + /* Mark the temporary net_num for the type pins*/ + mark_grid_type_pb_graph_node_pins_temp_net_num(ix, iy); + /* Update parasitic nets */ + update_one_unused_grid_output_pins_parasitic_nets(ix, iy); + } + + return; +} + + +void update_grid_pb_pins_parasitic_nets() { + int ix, iy; + t_type_ptr type = NULL; + + for (ix = 0; ix < (nx + 2); ix++) { + for (iy = 0; iy < (ny + 2); iy++) { + type = grid[ix][iy].type; + if ((EMPTY_TYPE == type)||(IO_TYPE == type)) { + continue; + } + /* Backup the packing prev_node and prev_edge */ + update_one_grid_pb_pins_parasitic_nets(ix, iy); + } + } + + return; +} + +/* Update the driver switch for each rr_node*/ +static +void identify_rr_node_driver_switch(t_det_routing_arch RoutingArch, + int LL_num_rr_nodes, + t_rr_node* LL_rr_node) { + int inode, iedge; + + /* Current Version: Support Uni-directional routing architecture only*/ + if (UNI_DIRECTIONAL != RoutingArch.directionality) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d])Assign rr_node driver switch only support uni-directional routing architecture.\n",__FILE__, __LINE__); + exit(1); + } + + /* I can do a simple job here: + * just assign driver_switch from drive_switches[0] + * which has been done in backannotation_vpr_post_route_info + */ + /* update_rr_nodes_driver_switch(routing_arch->directionality); */ + for (inode = 0; inode < LL_num_rr_nodes; inode++) { + if (0 == LL_rr_node[inode].fan_in) { + assert(0 == LL_rr_node[inode].num_drive_rr_nodes); + assert(NULL == LL_rr_node[inode].drive_switches); + continue; + } + LL_rr_node[inode].driver_switch = LL_rr_node[inode].drive_switches[0]; + for (iedge = 0; iedge < LL_rr_node[inode].num_drive_rr_nodes; iedge++) { + assert (LL_rr_node[inode].driver_switch == LL_rr_node[inode].drive_switches[iedge]); + } + } + + return; +} + +/* Find all the rr_nodes of a channel + * Return an array of rr_node pointers, and length of the array (num_pin_rr_nodes) + */ +t_rr_node** get_chan_rr_nodes(int* num_chan_rr_nodes, + t_rr_type chan_type, + int x, int y, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices) { + int itrack, inode; + t_rr_node** chan_rr_nodes = NULL; + + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + + switch (chan_type) { + case CHANX: + /* Get the channel width */ + (*num_chan_rr_nodes) = chan_width_x[y]; + /* Allocate */ + chan_rr_nodes = (t_rr_node**)my_malloc((*num_chan_rr_nodes)*sizeof(t_rr_node*)); + /* Fill the array */ + for (itrack = 0; itrack < (*num_chan_rr_nodes); itrack++) { + inode = get_rr_node_index(x, y, CHANX, itrack, LL_rr_node_indices); + chan_rr_nodes[itrack] = &(LL_rr_node[inode]); + } + break; + case CHANY: + /* Get the channel width */ + (*num_chan_rr_nodes) = chan_width_y[x]; + /* Allocate */ + chan_rr_nodes = (t_rr_node**)my_malloc((*num_chan_rr_nodes)*sizeof(t_rr_node*)); + /* Fill the array */ + for (itrack = 0; itrack < (*num_chan_rr_nodes); itrack++) { + inode = get_rr_node_index(x, y, CHANY, itrack, LL_rr_node_indices); + chan_rr_nodes[itrack] = &(LL_rr_node[inode]); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); + exit(1); + } + + return chan_rr_nodes; +} + + +/* Find all the rr_nodes at a certain side of a grid + * Return an array of rr_node pointers, and length of the array (num_pin_rr_nodes) + */ +t_rr_node** get_grid_side_pin_rr_nodes(int* num_pin_rr_nodes, + t_rr_type pin_type, + int x, int y, int side, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices) { + int height, ipin, class_id, inode; + t_type_ptr type = NULL; + t_rr_node** ret = NULL; + enum e_pin_type pin_class_type; + int cur; + + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + type = grid[x][y].type; + assert(NULL != type); + /* Assign the type of PIN*/ + switch (pin_type) { + case IPIN: + /* case SINK: */ + pin_class_type = RECEIVER; /* This is the end of a route path*/ + break; + /*case SOURCE:*/ + case OPIN: + pin_class_type = DRIVER; /* This is the start of a route path */ + break; + /* SINK and SOURCE are hypothesis nodes */ + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid pin_type!\n", __FILE__, __LINE__); + exit(1); + } + + /* Output the pins on the side*/ + (*num_pin_rr_nodes) = 0; + height = grid[x][y].offset; + for (ipin = 0; ipin < type->num_pins; ipin++) { + class_id = type->pin_class[ipin]; + if ((1 == type->pinloc[height][side][ipin])&&(pin_class_type == type->class_inf[class_id].type)) { + (*num_pin_rr_nodes)++; + } + } + /* Malloc */ + ret = (t_rr_node**)my_malloc(sizeof(t_rr_node*)*(*num_pin_rr_nodes)); + + /* Fill the return array*/ + cur = 0; + height = grid[x][y].offset; + for (ipin = 0; ipin < type->num_pins; ipin++) { + class_id = type->pin_class[ipin]; + if ((1 == type->pinloc[height][side][ipin])&&(pin_class_type == type->class_inf[class_id].type)) { + inode = get_rr_node_index(x, y, pin_type, ipin, LL_rr_node_indices); + ret[cur] = &(LL_rr_node[inode]); + cur++; + } + } + assert(cur == (*num_pin_rr_nodes)); + + return ret; +} + +/* Build arrays for rr_nodes of each Switch Blocks + * A Switch Box subckt consists of following ports: + * 1. Channel Y [x][y] inputs + * 2. Channel X [x+1][y] inputs + * 3. Channel Y [x][y-1] outputs + * 4. Channel X [x][y] outputs + * 5. Grid[x][y+1] Right side outputs pins + * 6. Grid[x+1][y+1] Left side output pins + * 7. Grid[x+1][y+1] Bottom side output pins + * 8. Grid[x+1][y] Top side output pins + * 9. Grid[x+1][y] Left side output pins + * 10. Grid[x][y] Right side output pins + * 11. Grid[x][y] Top side output pins + * 12. Grid[x][y+1] Bottom side output pins + * + * -------------- -------------- + * | | | | + * | Grid | ChanY | Grid | + * | [x][y+1] | [x][y+1] | [x+1][y+1] | + * | | | | + * -------------- -------------- + * ---------- + * ChanX | Switch | ChanX + * [x][y] | Box | [x+1][y] + * | [x][y] | + * ---------- + * -------------- -------------- + * | | | | + * | Grid | ChanY | Grid | + * | [x][y] | [x][y] | [x+1][y] | + * | | | | + * -------------- -------------- + * For channels chanY with INC_DIRECTION on the top side, they should be marked as outputs + * For channels chanY with DEC_DIRECTION on the top side, they should be marked as inputs + * For channels chanY with INC_DIRECTION on the bottom side, they should be marked as inputs + * For channels chanY with DEC_DIRECTION on the bottom side, they should be marked as outputs + * For channels chanX with INC_DIRECTION on the left side, they should be marked as inputs + * For channels chanX with DEC_DIRECTION on the left side, they should be marked as outputs + * For channels chanX with INC_DIRECTION on the right side, they should be marked as outputs + * For channels chanX with DEC_DIRECTION on the right side, they should be marked as inputs + */ +void build_one_switch_block_info(t_sb* cur_sb, int sb_x, int sb_y, + t_det_routing_arch RoutingArch, + int LL_num_rr_nodes, + t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices) { + int itrack, inode, side, ix, iy; + int temp_num_opin_rr_nodes[2] = {0,0}; + t_rr_node** temp_opin_rr_node[2] = {NULL, NULL}; + + /* Check */ + assert((!(0 > sb_x))&&(!(sb_x > (nx + 1)))); + assert((!(0 > sb_y))&&(!(sb_y > (ny + 1)))); + + /* Basic information*/ + cur_sb->x = sb_x; + cur_sb->y = sb_y; + cur_sb->directionality = RoutingArch.directionality; /* Could be more flexible, Currently we only support uni-directionalal routing architecture. */ + cur_sb->fs = RoutingArch.Fs; + cur_sb->num_sides = 4; /* Fixed */ + + /* Record the channel width of each side*/ + cur_sb->chan_width = (int*)my_calloc(cur_sb->num_sides, sizeof(int)); /* 4 sides */ + cur_sb->chan_rr_node_direction = (enum PORTS**)my_malloc(sizeof(enum PORTS*)*cur_sb->num_sides); /* 4 sides */ + cur_sb->chan_rr_node = (t_rr_node***)my_malloc(sizeof(t_rr_node**)*cur_sb->num_sides); /* 4 sides*/ + cur_sb->num_ipin_rr_nodes = (int*)my_calloc(cur_sb->num_sides, sizeof(int)); /* 4 sides */ + cur_sb->ipin_rr_node = (t_rr_node***)my_malloc(sizeof(t_rr_node**)*cur_sb->num_sides); /* 4 sides */ + cur_sb->ipin_rr_node_grid_side = (int**)my_malloc(sizeof(int*)*cur_sb->num_sides); /* 4 sides */ + cur_sb->num_opin_rr_nodes = (int*)my_calloc(cur_sb->num_sides, sizeof(int)); /* 4 sides */ + cur_sb->opin_rr_node = (t_rr_node***)my_malloc(sizeof(t_rr_node**)*cur_sb->num_sides); /* 4 sides */ + cur_sb->opin_rr_node_grid_side = (int**)my_malloc(sizeof(int*)*cur_sb->num_sides); /* 4 sides */ + + /* Find all rr_nodes of channels */ + for (side = 0; side < 4; side++) { + switch (side) { + case 0: + /* For the bording, we should take special care */ + if (sb_y == ny) { + cur_sb->chan_width[side] = 0; + cur_sb->chan_rr_node[side] = NULL; + cur_sb->chan_rr_node_direction[side] = NULL; + cur_sb->num_ipin_rr_nodes[side] = 0; + cur_sb->ipin_rr_node[side] = NULL; + cur_sb->ipin_rr_node_grid_side[side] = NULL; + cur_sb->num_opin_rr_nodes[side] = 0; + cur_sb->opin_rr_node[side] = NULL; + cur_sb->opin_rr_node_grid_side[side] = NULL; + break; + } + /* Routing channels*/ + ix = sb_x; + iy = sb_y + 1; + /* Channel width */ + cur_sb->chan_width[side] = chan_width_y[ix]; + /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ + cur_sb->chan_rr_node[side] = get_chan_rr_nodes(&(cur_sb->chan_width[side]), CHANY, ix, iy, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + /* Alloc */ + cur_sb->chan_rr_node_direction[side] = (enum PORTS*)my_malloc(sizeof(enum PORTS)*cur_sb->chan_width[side]); + /* Collect rr_nodes for Tracks for top: chany[x][y+1] */ + for (itrack = 0; itrack < cur_sb->chan_width[side]; itrack++) { + /* Identify the directionality, record it in rr_node_direction */ + if (INC_DIRECTION == cur_sb->chan_rr_node[side][itrack]->direction) { + cur_sb->chan_rr_node_direction[side][itrack] = OUT_PORT; + } else { + assert (DEC_DIRECTION == cur_sb->chan_rr_node[side][itrack]->direction); + cur_sb->chan_rr_node_direction[side][itrack] = IN_PORT; + } + } + /* TODO: Include Grid[x][y+1] RIGHT side outputs pins */ + temp_opin_rr_node[0] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[0], + OPIN, sb_x, sb_y + 1, 1, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + /* TODO: Include Grid[x+1][y+1] Left side output pins */ + temp_opin_rr_node[1] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[1], + OPIN, sb_x + 1, sb_y + 1, 3, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + /* Allocate opin_rr_node */ + cur_sb->num_opin_rr_nodes[side] = temp_num_opin_rr_nodes[0] + temp_num_opin_rr_nodes[1]; + cur_sb->opin_rr_node[side] = (t_rr_node**)my_calloc(cur_sb->num_opin_rr_nodes[side], sizeof(t_rr_node*)); + cur_sb->opin_rr_node_grid_side[side] = (int*)my_calloc(cur_sb->num_opin_rr_nodes[side], sizeof(int)); + /* Copy from temp_opin_rr_node to opin_rr_node */ + for (inode = 0; inode < temp_num_opin_rr_nodes[0]; inode++) { + cur_sb->opin_rr_node[side][inode] = temp_opin_rr_node[0][inode]; + cur_sb->opin_rr_node_grid_side[side][inode] = 1; /* Grid[x][y+1] RIGHT side outputs pins */ + } + for (inode = 0; inode < temp_num_opin_rr_nodes[1]; inode++) { + cur_sb->opin_rr_node[side][inode + temp_num_opin_rr_nodes[0]] = temp_opin_rr_node[1][inode]; + cur_sb->opin_rr_node_grid_side[side][inode + temp_num_opin_rr_nodes[0]] = 3; /* Grid[x+1][y+1] left side outputs pins */ + } + /* We do not have any IPIN for a Switch Block */ + cur_sb->num_ipin_rr_nodes[side] = 0; + cur_sb->ipin_rr_node[side] = NULL; + cur_sb->ipin_rr_node_grid_side[side] = NULL; + break; + case 1: + /* For the bording, we should take special care */ + if (sb_x == nx) { + cur_sb->chan_width[side] = 0; + cur_sb->chan_rr_node[side] = NULL; + cur_sb->chan_rr_node_direction[side] = NULL; + cur_sb->num_ipin_rr_nodes[side] = 0; + cur_sb->ipin_rr_node[side] = NULL; + cur_sb->ipin_rr_node_grid_side[side] = NULL; + cur_sb->num_opin_rr_nodes[side] = 0; + cur_sb->opin_rr_node[side] = NULL; + cur_sb->opin_rr_node_grid_side[side] = NULL; + break; + } + /* Routing channels*/ + ix = sb_x + 1; + iy = sb_y; + /* Channel width */ + cur_sb->chan_width[side] = chan_width_x[iy]; + /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ + /* Alloc */ + cur_sb->chan_rr_node[side] = get_chan_rr_nodes(&(cur_sb->chan_width[side]), CHANX, ix, iy, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + cur_sb->chan_rr_node_direction[side] = (enum PORTS*)my_malloc(sizeof(enum PORTS)*cur_sb->chan_width[side]); + /* Collect rr_nodes for Tracks for right: chanX[x+1][y] */ + for (itrack = 0; itrack < cur_sb->chan_width[side]; itrack++) { + /* Identify the directionality, record it in rr_node_direction */ + if (INC_DIRECTION == cur_sb->chan_rr_node[side][itrack]->direction) { + cur_sb->chan_rr_node_direction[side][itrack] = OUT_PORT; + } else { + assert (DEC_DIRECTION == cur_sb->chan_rr_node[side][itrack]->direction); + cur_sb->chan_rr_node_direction[side][itrack] = IN_PORT; + } + } + /* TODO: include Grid[x+1][y+1] Bottom side output pins */ + temp_opin_rr_node[0] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[0], + OPIN, sb_x + 1, sb_y + 1, 2, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + /* TODO: include Grid[x+1][y] Top side output pins */ + temp_opin_rr_node[1] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[1], + OPIN, sb_x + 1, sb_y, 0, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + /* Allocate opin_rr_node */ + cur_sb->num_opin_rr_nodes[side] = temp_num_opin_rr_nodes[0] + temp_num_opin_rr_nodes[1]; + cur_sb->opin_rr_node[side] = (t_rr_node**)my_calloc(cur_sb->num_opin_rr_nodes[side], sizeof(t_rr_node*)); + cur_sb->opin_rr_node_grid_side[side] = (int*)my_calloc(cur_sb->num_opin_rr_nodes[side], sizeof(int)); + /* Copy from temp_opin_rr_node to opin_rr_node */ + for (inode = 0; inode < temp_num_opin_rr_nodes[0]; inode++) { + cur_sb->opin_rr_node[side][inode] = temp_opin_rr_node[0][inode]; + cur_sb->opin_rr_node_grid_side[side][inode] = 2; /* Grid[x+1][y+1] Bottom side outputs pins */ + } + for (inode = 0; inode < temp_num_opin_rr_nodes[1]; inode++) { + cur_sb->opin_rr_node[side][inode + temp_num_opin_rr_nodes[0]] = temp_opin_rr_node[1][inode]; + cur_sb->opin_rr_node_grid_side[side][inode + temp_num_opin_rr_nodes[0]] = 0; /* Grid[x+1][y] TOP side outputs pins */ + } + /* We do not have any IPIN for a Switch Block */ + cur_sb->num_ipin_rr_nodes[side] = 0; + cur_sb->ipin_rr_node[side] = NULL; + cur_sb->ipin_rr_node_grid_side[side] = NULL; + break; + case 2: + /* For the bording, we should take special care */ + if (sb_y == 0) { + cur_sb->chan_width[side] = 0; + cur_sb->chan_rr_node[side] = NULL; + cur_sb->chan_rr_node_direction[side] = NULL; + cur_sb->num_ipin_rr_nodes[side] = 0; + cur_sb->ipin_rr_node[side] = NULL; + cur_sb->ipin_rr_node_grid_side[side] = NULL; + cur_sb->num_opin_rr_nodes[side] = 0; + cur_sb->opin_rr_node[side] = NULL; + cur_sb->opin_rr_node_grid_side[side] = NULL; + break; + } + /* Routing channels*/ + ix = sb_x; + iy = sb_y; + /* Channel width */ + cur_sb->chan_width[side] = chan_width_y[ix]; + /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ + /* Alloc */ + cur_sb->chan_rr_node[side] = get_chan_rr_nodes(&(cur_sb->chan_width[side]), CHANY, ix, iy, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + cur_sb->chan_rr_node_direction[side] = (enum PORTS*)my_malloc(sizeof(enum PORTS)*cur_sb->chan_width[side]); + /* Collect rr_nodes for Tracks for bottom: chany[x][y] */ + for (itrack = 0; itrack < cur_sb->chan_width[side]; itrack++) { + /* Identify the directionality, record it in rr_node_direction */ + if (DEC_DIRECTION == cur_sb->chan_rr_node[side][itrack]->direction) { + cur_sb->chan_rr_node_direction[side][itrack] = OUT_PORT; + } else { + assert (INC_DIRECTION == cur_sb->chan_rr_node[side][itrack]->direction); + cur_sb->chan_rr_node_direction[side][itrack] = IN_PORT; + } + } + /* TODO: include Grid[x+1][y] Left side output pins */ + temp_opin_rr_node[0] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[0], + OPIN, sb_x + 1, sb_y, 3, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + /* TODO: include Grid[x][y] Right side output pins */ + temp_opin_rr_node[1] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[1], + OPIN, sb_x, sb_y, 1, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + /* Allocate opin_rr_node */ + cur_sb->num_opin_rr_nodes[side] = temp_num_opin_rr_nodes[0] + temp_num_opin_rr_nodes[1]; + cur_sb->opin_rr_node[side] = (t_rr_node**)my_calloc(cur_sb->num_opin_rr_nodes[side], sizeof(t_rr_node*)); + cur_sb->opin_rr_node_grid_side[side] = (int*)my_calloc(cur_sb->num_opin_rr_nodes[side], sizeof(int)); + /* Copy from temp_opin_rr_node to opin_rr_node */ + for (inode = 0; inode < temp_num_opin_rr_nodes[0]; inode++) { + cur_sb->opin_rr_node[side][inode] = temp_opin_rr_node[0][inode]; + cur_sb->opin_rr_node_grid_side[side][inode] = 3; /* Grid[x+1][y] LEFT side outputs pins */ + } + for (inode = 0; inode < temp_num_opin_rr_nodes[1]; inode++) { + cur_sb->opin_rr_node[side][inode + temp_num_opin_rr_nodes[0]] = temp_opin_rr_node[1][inode]; + cur_sb->opin_rr_node_grid_side[side][inode + temp_num_opin_rr_nodes[0]] = 1; /* Grid[x][y] RIGHT side outputs pins */ + } + /* We do not have any IPIN for a Switch Block */ + cur_sb->num_ipin_rr_nodes[side] = 0; + cur_sb->ipin_rr_node[side] = NULL; + cur_sb->ipin_rr_node_grid_side[side] = NULL; + break; + case 3: + /* For the bording, we should take special care */ + if (sb_x == 0) { + cur_sb->chan_width[side] = 0; + cur_sb->chan_rr_node[side] = NULL; + cur_sb->chan_rr_node_direction[side] = NULL; + cur_sb->num_ipin_rr_nodes[side] = 0; + cur_sb->ipin_rr_node[side] = NULL; + cur_sb->ipin_rr_node_grid_side[side] = NULL; + cur_sb->num_opin_rr_nodes[side] = 0; + cur_sb->opin_rr_node[side] = NULL; + cur_sb->opin_rr_node_grid_side[side] = NULL; + break; + } + /* Routing channels*/ + ix = sb_x; + iy = sb_y; + /* Channel width */ + cur_sb->chan_width[side] = chan_width_x[iy]; + /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ + /* Alloc */ + cur_sb->chan_rr_node[side] = get_chan_rr_nodes(&(cur_sb->chan_width[side]), CHANX, ix, iy, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + cur_sb->chan_rr_node_direction[side] = (enum PORTS*)my_malloc(sizeof(enum PORTS)*cur_sb->chan_width[side]); + /* Collect rr_nodes for Tracks for left: chanx[x][y] */ + for (itrack = 0; itrack < cur_sb->chan_width[side]; itrack++) { + /* Identify the directionality, record it in rr_node_direction */ + if (DEC_DIRECTION == cur_sb->chan_rr_node[side][itrack]->direction) { + cur_sb->chan_rr_node_direction[side][itrack] = OUT_PORT; + } else { + assert (INC_DIRECTION == cur_sb->chan_rr_node[side][itrack]->direction); + cur_sb->chan_rr_node_direction[side][itrack] = IN_PORT; + } + } + /* TODO: include Grid[x][y+1] Bottom side outputs pins */ + temp_opin_rr_node[0] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[0], + OPIN, sb_x, sb_y + 1, 2, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + /* TODO: include Grid[x][y] Top side output pins */ + temp_opin_rr_node[1] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[1], + OPIN, sb_x, sb_y, 0, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + /* Allocate opin_rr_node */ + cur_sb->num_opin_rr_nodes[side] = temp_num_opin_rr_nodes[0] + temp_num_opin_rr_nodes[1]; + cur_sb->opin_rr_node[side] = (t_rr_node**)my_calloc(cur_sb->num_opin_rr_nodes[side], sizeof(t_rr_node*)); + cur_sb->opin_rr_node_grid_side[side] = (int*)my_calloc(cur_sb->num_opin_rr_nodes[side], sizeof(int)); + /* Copy from temp_opin_rr_node to opin_rr_node */ + for (inode = 0; inode < temp_num_opin_rr_nodes[0]; inode++) { + cur_sb->opin_rr_node[side][inode] = temp_opin_rr_node[0][inode]; + cur_sb->opin_rr_node_grid_side[side][inode] = 2; /* Grid[x][y+1] BOTTOM side outputs pins */ + } + for (inode = 0; inode < temp_num_opin_rr_nodes[1]; inode++) { + cur_sb->opin_rr_node[side][inode + temp_num_opin_rr_nodes[0]] = temp_opin_rr_node[1][inode]; + cur_sb->opin_rr_node_grid_side[side][inode + temp_num_opin_rr_nodes[0]] = 0; /* Grid[x][y] TOP side outputs pins */ + } + /* We do not have any IPIN for a Switch Block */ + cur_sb->num_ipin_rr_nodes[side] = 0; + cur_sb->ipin_rr_node[side] = NULL; + cur_sb->ipin_rr_node_grid_side[side] = NULL; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid side index!\n", __FILE__, __LINE__); + exit(1); + } + /* Free */ + temp_num_opin_rr_nodes[0] = 0; + my_free(temp_opin_rr_node[0]); + temp_num_opin_rr_nodes[1] = 0; + my_free(temp_opin_rr_node[1]); + /* Set them to NULL, avoid double free errors */ + temp_opin_rr_node[0] = NULL; + temp_opin_rr_node[1] = NULL; + } + + return; +} + +/* Build arrays for rr_nodes of each Switch Blocks + * Return a two-dimension array (t_rr_node**), + * each element of which is the entry of a two-dimension array of rr_node pointers (t_rr_node***) + * according to their location in a switch block + * Therefore, the return data type is (t_rr_node*****) + */ +static +void alloc_and_build_switch_blocks_info(t_det_routing_arch RoutingArch, + int LL_num_rr_nodes, + t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices) { + int ix, iy; + + sb_info = alloc_sb_info_array(nx, ny); + + /* For each switch block, determine the size of array */ + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 0; iy < (ny + 1); iy++) { + build_one_switch_block_info(&sb_info[ix][iy], ix, iy, RoutingArch, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + } + } + + return; +} + +/* Collect rr_nodes information for a connection box + * -------------- -------------- + * | | | | + * | Grid | ChanY | Grid | + * | [x][y+1] | [x][y] | [x+1][y+1] | + * | | Connection | | + * -------------- Box_Y[x][y] -------------- + * ---------- + * ChanX | Switch | ChanX + * [x][y] | Box | [x+1][y] + * Connection | [x][y] | Connection + * Box_X[x][y] ---------- Box_X[x+1][y] + * -------------- -------------- + * | | | | + * | Grid | ChanY | Grid | + * | [x][y] | [x][y-1] | [x+1][y] | + * | | Connection | | + * --------------Box_Y[x][y-1]-------------- + */ +void build_one_connection_block_info(t_cb* cur_cb, int cb_x, int cb_y, t_rr_type cb_type, + int LL_num_rr_nodes, + t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices) { + int itrack, inode, side; + + /* Check */ + assert((!(0 > cb_x))&&(!(cb_x > (nx + 1)))); + assert((!(0 > cb_y))&&(!(cb_y > (ny + 1)))); + + /* Fill basic information */ + cur_cb->x = cb_x; + cur_cb->y = cb_y; + cur_cb->type = cb_type; + + /* Record the channel width of each side*/ + cur_cb->chan_width = (int*)my_calloc(cur_cb->num_sides, sizeof(int)); /* 4 sides */ + cur_cb->chan_rr_node_direction = (enum PORTS**)my_malloc(sizeof(enum PORTS*)*cur_cb->num_sides); /* 4 sides */ + cur_cb->chan_rr_node = (t_rr_node***)my_malloc(sizeof(t_rr_node**)*cur_cb->num_sides); /* 4 sides*/ + cur_cb->num_ipin_rr_nodes = (int*)my_calloc(cur_cb->num_sides, sizeof(int)); /* 4 sides */ + cur_cb->ipin_rr_node = (t_rr_node***)my_malloc(sizeof(t_rr_node**)*cur_cb->num_sides); /* 4 sides*/ + cur_cb->ipin_rr_node_grid_side = (int**)my_calloc(cur_cb->num_sides, sizeof(int*)); /* 4 sides */ + cur_cb->num_opin_rr_nodes = (int*)my_calloc(cur_cb->num_sides, sizeof(int)); /* 4 sides */ + cur_cb->opin_rr_node = (t_rr_node***)my_malloc(sizeof(t_rr_node**)*cur_cb->num_sides); /* 4 sides*/ + cur_cb->opin_rr_node_grid_side = (int**)my_calloc(cur_cb->num_sides, sizeof(int*)); /* 4 sides */ + + /* Identify the type of connection box, the rr_nodes are different depending on the type */ + /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ + for (side = 0; side < 4; side++) { + switch (side) { + case 0: /* TOP */ + switch(cb_type) { + case CHANX: + /* BOTTOM INPUT Pins of Grid[x][y+1] */ + /* Collect IPIN rr_nodes*/ + cur_cb->ipin_rr_node[side] = get_grid_side_pin_rr_nodes(&(cur_cb->num_ipin_rr_nodes[side]), + IPIN, cb_x, cb_y + 1, 2, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + + cur_cb->ipin_rr_node_grid_side[side] = (int*)my_calloc(cur_cb->num_ipin_rr_nodes[side], sizeof(int)); + for (inode = 0; inode < cur_cb->num_ipin_rr_nodes[side]; inode++) { + cur_cb->ipin_rr_node_grid_side[side][inode] = 2; /* BOTTOM IPINs */ + } + /* Update channel width, num_opin_rr_nodes */ + cur_cb->chan_width[side] = 0; + /* Identify the directionality, record it in rr_node_direction */ + cur_cb->chan_rr_node[side] = NULL; + cur_cb->chan_rr_node_direction[side] = NULL; + /* There is no OPIN nodes at this side */ + cur_cb->num_opin_rr_nodes[side] = 0; + cur_cb->opin_rr_node[side] = NULL; + cur_cb->opin_rr_node_grid_side[side] = NULL; + break; + case CHANY: + /* Collect channel-Y [x][y] rr_nodes*/ + /* Update channel width */ + cur_cb->chan_rr_node[side] = get_chan_rr_nodes(&(cur_cb->chan_width[side]), CHANY, cb_x, cb_y, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + /* Alloc */ + cur_cb->chan_rr_node_direction[side] = (enum PORTS*)my_malloc(sizeof(enum PORTS)*cur_cb->chan_width[side]); + /* Collect rr_nodes for Tracks for left: chanx[x][y] */ + for (itrack = 0; itrack < cur_cb->chan_width[side]; itrack++) { + /* Identify the directionality, record it in rr_node_direction */ + cur_cb->chan_rr_node_direction[side][itrack] = IN_PORT; + } + /* There is no IPIN nodes at this side */ + cur_cb->num_ipin_rr_nodes[side] = 0; + cur_cb->ipin_rr_node[side] = NULL; + cur_cb->ipin_rr_node_grid_side[side] = NULL; + /* There is no OPIN nodes at this side */ + cur_cb->num_opin_rr_nodes[side] = 0; + cur_cb->opin_rr_node[side] = NULL; + cur_cb->opin_rr_node_grid_side[side] = NULL; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); + exit(1); + } + break; + case 1: /* RIGHT */ + switch(cb_type) { + case CHANX: + /* Collect channel-X [x][y] rr_nodes*/ + /* Update channel width */ + cur_cb->chan_rr_node[side] = get_chan_rr_nodes(&(cur_cb->chan_width[side]), CHANX, cb_x, cb_y, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + /* Alloc */ + cur_cb->chan_rr_node_direction[side] = (enum PORTS*)my_malloc(sizeof(enum PORTS)*cur_cb->chan_width[side]); + /* Collect rr_nodes for Tracks for left: chanx[x][y] */ + for (itrack = 0; itrack < cur_cb->chan_width[side]; itrack++) { + /* Identify the directionality, record it in rr_node_direction */ + cur_cb->chan_rr_node_direction[side][itrack] = IN_PORT; + } + /* There is no IPIN nodes at this side */ + cur_cb->num_ipin_rr_nodes[side] = 0; + cur_cb->ipin_rr_node[side] = NULL; + cur_cb->ipin_rr_node_grid_side[side] = NULL; + /* There is no OPIN nodes at this side */ + cur_cb->num_opin_rr_nodes[side] = 0; + cur_cb->opin_rr_node[side] = NULL; + cur_cb->opin_rr_node_grid_side[side] = NULL; + break; + case CHANY: + /* LEFT INPUT Pins of Grid[x+1][y] */ + /* Collect IPIN rr_nodes*/ + cur_cb->ipin_rr_node[side] = get_grid_side_pin_rr_nodes(&(cur_cb->num_ipin_rr_nodes[side]), + IPIN, cb_x + 1, cb_y, 3, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + cur_cb->ipin_rr_node_grid_side[side] = (int*)my_calloc(cur_cb->num_ipin_rr_nodes[side], sizeof(int)); + for (inode = 0; inode < cur_cb->num_ipin_rr_nodes[side]; inode++) { + cur_cb->ipin_rr_node_grid_side[side][inode] = 3; /* LEFT IPINs */ + } + /* Update channel width, num_opin_rr_nodes */ + cur_cb->chan_width[side] = 0; + /* Identify the directionality, record it in rr_node_direction */ + cur_cb->chan_rr_node[side] = NULL; + cur_cb->chan_rr_node_direction[side] = NULL; + /* There is no OPIN nodes at this side */ + cur_cb->num_opin_rr_nodes[side] = 0; + cur_cb->opin_rr_node[side] = NULL; + cur_cb->opin_rr_node_grid_side[side] = NULL; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); + exit(1); + } + break; + case 2: /* BOTTOM */ + switch(cb_type) { + case CHANX: + /* TOP INPUT Pins of Grid[x][y] */ + /* Collect IPIN rr_nodes*/ + cur_cb->ipin_rr_node[side] = get_grid_side_pin_rr_nodes(&(cur_cb->num_ipin_rr_nodes[side]), + IPIN, cb_x, cb_y, 0, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + cur_cb->ipin_rr_node_grid_side[side] = (int*)my_calloc(cur_cb->num_ipin_rr_nodes[side], sizeof(int)); + for (inode = 0; inode < cur_cb->num_ipin_rr_nodes[side]; inode++) { + cur_cb->ipin_rr_node_grid_side[side][inode] = 0; /* TOP IPINs */ + } + /* Update channel width, num_opin_rr_nodes */ + cur_cb->chan_width[side] = 0; + /* Identify the directionality, record it in rr_node_direction */ + cur_cb->chan_rr_node[side] = NULL; + cur_cb->chan_rr_node_direction[side] = NULL; + /* There is no OPIN nodes at this side */ + cur_cb->num_opin_rr_nodes[side] = 0; + cur_cb->opin_rr_node[side] = NULL; + cur_cb->opin_rr_node_grid_side[side] = NULL; + break; + case CHANY: + /* Nothing should be done other than setting NULL pointers and zero counter*/ + /* There is no input and output rr_nodes at this side */ + cur_cb->chan_width[side] = 0; + cur_cb->chan_rr_node[side] = NULL; + cur_cb->chan_rr_node_direction[side] = NULL; + cur_cb->num_ipin_rr_nodes[side] = 0; + cur_cb->ipin_rr_node[side] = NULL; + cur_cb->ipin_rr_node_grid_side[side] = NULL; + cur_cb->num_opin_rr_nodes[side] = 0; + cur_cb->opin_rr_node[side] = NULL; + cur_cb->opin_rr_node_grid_side[side] = NULL; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); + exit(1); + } + break; + case 3: /* LEFT */ + switch(cb_type) { + case CHANX: + /* Nothing should be done other than setting NULL pointers and zero counter*/ + /* There is no input and output rr_nodes at this side */ + cur_cb->chan_width[side] = 0; + cur_cb->chan_rr_node[side] = NULL; + cur_cb->chan_rr_node_direction[side] = NULL; + cur_cb->num_ipin_rr_nodes[side] = 0; + cur_cb->ipin_rr_node[side] = NULL; + cur_cb->ipin_rr_node_grid_side[side] = NULL; + cur_cb->num_opin_rr_nodes[side] = 0; + cur_cb->opin_rr_node[side] = NULL; + cur_cb->opin_rr_node_grid_side[side] = NULL; + break; + case CHANY: + /* RIGHT INPUT Pins of Grid[x][y] */ + /* Collect IPIN rr_nodes*/ + cur_cb->ipin_rr_node[side] = get_grid_side_pin_rr_nodes(&(cur_cb->num_ipin_rr_nodes[side]), + IPIN, cur_cb->x, cur_cb->y, 1, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + cur_cb->ipin_rr_node_grid_side[side] = (int*)my_calloc(cur_cb->num_ipin_rr_nodes[side], sizeof(int)); + for (inode = 0; inode < cur_cb->num_ipin_rr_nodes[side]; inode++) { + cur_cb->ipin_rr_node_grid_side[side][inode] = 1; /* RIGHT IPINs */ + } + /* Update channel width, num_opin_rr_nodes */ + cur_cb->chan_width[side] = 0; + /* Identify the directionality, record it in rr_node_direction */ + cur_cb->chan_rr_node[side] = NULL; + cur_cb->chan_rr_node_direction[side] = NULL; + /* There is no OPIN nodes at this side */ + cur_cb->num_opin_rr_nodes[side] = 0; + cur_cb->opin_rr_node[side] = NULL; + cur_cb->opin_rr_node_grid_side[side] = NULL; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); + exit(1); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid side index!\n", __FILE__, __LINE__); + exit(1); + } + } + + return; +} + + +/* Build arrays for rr_nodes of each Connection Blocks + * Different from Switch blocks, we have two types of Connection blocks: + * 1. Connecting X-channels to CLB inputs + * 2. Connection Y-channels to CLB inputs + */ +static +void alloc_and_build_connection_blocks_info(t_det_routing_arch RoutingArch, + int LL_num_rr_nodes, + t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices) { + int ix, iy; + + /* alloc CB for X-channels */ + cbx_info = alloc_cb_info_array(nx, ny); + /* Fill information for each CBX*/ + for (iy = 0; iy < (ny + 1); iy++) { + for (ix = 1; ix < (nx + 1); ix++) { + build_one_connection_block_info(&(cbx_info[ix][iy]), ix, iy, CHANX, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + } + } + + /* alloc CB for Y-channels */ + cby_info = alloc_cb_info_array(nx, ny); + /* Fill information for each CBX*/ + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + build_one_connection_block_info(&(cby_info[ix][iy]), ix, iy, CHANY, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + } + } + + return; +} + +/* Free all the allocated memories by function: + * either spice_backannotate_vpr_post_route_info or backannotate_vpr_post_route_info*/ +void free_backannotate_vpr_post_route_info() { + /* Free spice_net_info */ + free_clb_nets_spice_net_info(); + /* Free CB and SB info */ + free_sb_info_array(&sb_info, nx, ny); + free_cb_info_array(&cbx_info, nx, ny); + free_cb_info_array(&cby_info, nx, ny); +} + +static +boolean ipin_rr_nodes_vpack_net_num_changed(int LL_num_rr_nodes, + t_rr_node* LL_rr_node) { + int inode; + + for (inode = 0; inode < LL_num_rr_nodes; inode++) { + if (IPIN != LL_rr_node[inode].type) { + continue; + } + /* We only care IPINs */ + if (TRUE == LL_rr_node[inode].vpack_net_num_changed) { + return TRUE; + } + } + + return FALSE; +} + +static +void parasitic_net_estimation() { + int iter_cnt = 0; + boolean iter_continue = FALSE; + + + vpr_printf(TIO_MESSAGE_INFO, "Start backannotating global and local routing nets iteratively...\n"); + while(1) { + iter_cnt++; + + init_rr_nodes_vpack_net_num_changed(num_rr_nodes, + rr_node); + + /* + * vpr_printf(TIO_MESSAGE_INFO, "Backannotating local routing net...\n"); + backannotate_pb_rr_nodes_net_info(); + */ + + /* Update CLB pins parasitic nets: + * Traverse from inputs of CLBs to outputs. + * Mark parasitics nets propagated from input pins to output pins inside CLBs + */ + update_grid_pb_pins_parasitic_nets(); + + /* Backannoating global routing parasitic net... + * Traverse from OPINs in rr_graph to IPINs. + * Mark parasitic nets in the rr_graph + */ + backannotate_rr_nodes_parasitic_net_info(); + + /* Check vpack_net_num of all the OPINs are consistant */ + /* Consistency means iterations end here */ + iter_continue = ipin_rr_nodes_vpack_net_num_changed(num_rr_nodes, + rr_node); + + if (FALSE == iter_continue) { + break; + } + } + + vpr_printf(TIO_MESSAGE_INFO,"Parasitic net estimation ends in %d iterations.\n", iter_cnt); + + return; +} + +/* Back-Annotate post routing results to the VPR routing-resource graphs */ +void spice_backannotate_vpr_post_route_info(t_det_routing_arch RoutingArch, + boolean parasitic_net_estimation_off) { + + vpr_printf(TIO_MESSAGE_INFO, "Start backannotating post route information for SPICE modeling...\n"); + /* Give spice_name_tag for each pb*/ + vpr_printf(TIO_MESSAGE_INFO, "Generate SPICE name tags for pbs...\n"); + gen_spice_name_tags_all_pbs(); + /* Build previous node lists for each rr_node */ + vpr_printf(TIO_MESSAGE_INFO, "Building previous node list for all Routing Resource Nodes...\n"); + build_prev_node_list_rr_nodes(num_rr_nodes, rr_node); + /* Build driver switches for each rr_node*/ + vpr_printf(TIO_MESSAGE_INFO, "Identifying driver switches for all Routing Resource Nodes...\n"); + identify_rr_node_driver_switch(RoutingArch, num_rr_nodes, rr_node); + + /* Build Array for each Switch block and Connection block */ + vpr_printf(TIO_MESSAGE_INFO, "Collecting detailed information for each Switch block...\n"); + alloc_and_build_switch_blocks_info(RoutingArch, num_rr_nodes, rr_node, rr_node_indices); + vpr_printf(TIO_MESSAGE_INFO, "Collecting detailed information for each to Connection block...\n"); + alloc_and_build_connection_blocks_info(RoutingArch, num_rr_nodes, rr_node, rr_node_indices); + + /* This function should go very first because it gives all the net_num */ + vpr_printf(TIO_MESSAGE_INFO,"Back annotating mapping information to global routing resource nodes...\n"); + back_annotate_rr_node_map_info(); + /* Update local_rr_graphs to match post-route results*/ + vpr_printf(TIO_MESSAGE_INFO, "Update CLB local routing graph to match post-route results...\n"); + update_grid_pbs_post_route_rr_graph(); + vpr_printf(TIO_MESSAGE_INFO,"Back annotating mapping information to local routing resource nodes...\n"); + back_annotate_pb_rr_node_map_info(); + + /* Backannotate activity information, initialize the waveform information */ + /* Parasitic Net Activity Estimation */ + if (FALSE == parasitic_net_estimation_off) { + vpr_printf(TIO_MESSAGE_WARNING, "Parasitic Net Estimation starts...\n"); + parasitic_net_estimation(); + } else { + vpr_printf(TIO_MESSAGE_WARNING, "Parasitic Net Estimation is turned off...Accuracy loss may be expected!\n"); + } + + /* Net activities */ + vpr_printf(TIO_MESSAGE_INFO, "Backannoating Net activities...\n"); + backannotate_clb_nets_act_info(); + vpr_printf(TIO_MESSAGE_INFO, "Determine Net initial values...\n"); + backannotate_clb_nets_init_val(); + + vpr_printf(TIO_MESSAGE_INFO, "Finish backannotating post route information for SPICE modeling.\n"); + + return; +} + +void backannotate_vpr_post_route_info(t_det_routing_arch RoutingArch) { + + vpr_printf(TIO_MESSAGE_INFO, "Start backannotating post route information...\n"); + /* Build previous node lists for each rr_node */ + vpr_printf(TIO_MESSAGE_INFO, "Building previous node list for all Routing Resource Nodes...\n"); + build_prev_node_list_rr_nodes(num_rr_nodes, rr_node); + /* This function should go very first because it gives all the net_num */ + vpr_printf(TIO_MESSAGE_INFO,"Back annotating mapping information to global routing resource nodes...\n"); + back_annotate_rr_node_map_info(); + /* Update local_rr_graphs to match post-route results*/ + vpr_printf(TIO_MESSAGE_INFO, "Update logic block local routing graph to match post-route results...\n"); + update_grid_pbs_post_route_rr_graph(); + vpr_printf(TIO_MESSAGE_INFO,"Back annotating mapping information to local routing resource nodes...\n"); + back_annotate_pb_rr_node_map_info(); + + /* Build Array for each Switch block and Connection block */ + vpr_printf(TIO_MESSAGE_INFO, "Collecting detailed information for each Switch block...\n"); + alloc_and_build_switch_blocks_info(RoutingArch, num_rr_nodes, rr_node, rr_node_indices); + vpr_printf(TIO_MESSAGE_INFO, "Collecting detailed infromation for each to Connection block...\n"); + alloc_and_build_connection_blocks_info(RoutingArch, num_rr_nodes, rr_node, rr_node_indices); + + /* Backannotate activity information, initialize the waveform information */ + vpr_printf(TIO_MESSAGE_INFO, "Update logic block pins parasitic nets (1st time: for output pins)...\n"); + update_grid_pb_pins_parasitic_nets(); + vpr_printf(TIO_MESSAGE_WARNING, "Parasitic Net Estimation starts...\n"); + parasitic_net_estimation(); + + /* Net activities */ + vpr_printf(TIO_MESSAGE_INFO, "Backannoating Net activities...\n"); + backannotate_clb_nets_act_info(); + vpr_printf(TIO_MESSAGE_INFO, "Determine Net initial values...\n"); + backannotate_clb_nets_init_val(); + + vpr_printf(TIO_MESSAGE_INFO, "Finish backannotating post route information.\n"); + + return; +} diff --git a/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_backannotate_utils.h b/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_backannotate_utils.h new file mode 100644 index 000000000..bae6faa08 --- /dev/null +++ b/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_backannotate_utils.h @@ -0,0 +1,74 @@ + +void init_one_sb_info(t_sb* cur_sb); + +void free_one_sb_info(t_sb* cur_sb); + +t_sb** alloc_sb_info_array(int LL_nx, int LL_ny); + +void free_sb_info_array(t_sb*** LL_sb_info, int LL_nx, int LL_ny); + +void init_one_cb_info(t_cb* cur_cb); + +void free_one_cb_info(t_cb* cur_cb); + +t_cb** alloc_cb_info_array(int LL_nx, int LL_ny); + +void free_cb_info_array(t_cb*** LL_cb_info, int LL_nx, int LL_ny); + +void free_clb_nets_spice_net_info(); + +int get_rr_node_index_in_sb_info(t_rr_node* cur_rr_node, + t_sb cur_sb_info, + int chan_side, enum PORTS rr_node_direction); + +void get_rr_node_side_and_index_in_sb_info(t_rr_node* cur_rr_node, + t_sb cur_sb_info, + enum PORTS rr_node_direction, + OUTP int* cur_rr_node_side, + OUTP int* cur_rr_node_index); + +void get_chan_rr_node_coorindate_in_sb_info(t_sb cur_sb_info, + int chan_rr_node_side, + t_rr_type* chan_type, + int* chan_rr_node_x, int* chan_rr_node_y); + +int get_rr_node_index_in_cb_info(t_rr_node* cur_rr_node, + t_cb cur_cb_info, + int chan_side, enum PORTS rr_node_direction); + +void get_rr_node_side_and_index_in_cb_info(t_rr_node* cur_rr_node, + t_cb cur_cb_info, + enum PORTS rr_node_direction, + OUTP int* cur_rr_node_side, + OUTP int* cur_rr_node_index); + +t_rr_node** get_chan_rr_nodes(int* num_chan_rr_nodes, + t_rr_type chan_type, + int x, int y, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices); + +t_rr_node** get_grid_side_pin_rr_nodes(int* num_pin_rr_nodes, + t_rr_type pin_type, + int x, int y, int side, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices); + +void build_one_switch_block_info(t_sb* cur_sb, int sb_x, int sb_y, + t_det_routing_arch RoutingArch, + int LL_num_rr_nodes, + t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices); + +void build_one_connection_block_info(t_cb* cur_cb, int cb_x, int cb_y, t_rr_type cb_type, + int LL_num_rr_nodes, + t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices); + +void free_backannotate_vpr_post_route_info(); + +void spice_backannotate_vpr_post_route_info(t_det_routing_arch RoutingArch, + boolean parasitic_net_estimation_off); + +void backannotate_vpr_post_route_info(t_det_routing_arch RoutingArch); + diff --git a/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_bitstream.c b/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_bitstream.c new file mode 100644 index 000000000..cd9527249 --- /dev/null +++ b/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_bitstream.c @@ -0,0 +1,288 @@ +/***********************************/ +/* Synthesizable Verilog Dumping */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph.h" +#include "vpr_utils.h" +#include "path_delay.h" +#include "stats.h" + +/* Include FPGA-SPICE utils */ +#include "read_xml_spice_util.h" +#include "linkedlist.h" +#include "fpga_spice_utils.h" +#include "fpga_spice_backannotate_utils.h" +#include "spice_api.h" +#include "fpga_spice_globals.h" + +/* Include SynVerilog headers */ +#include "verilog_global.h" +#include "verilog_utils.h" + +/* Global variables only in file */ +static int dumped_num_conf_bits = 0; + +/* Local Subroutines */ +static +void rec_dump_conf_bits_to_bitstream_file(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info, + t_llist* cur_conf_bit); + +/* USE while LOOP !!! Recursive method causes memory corruptions!*/ +static +void dump_conf_bits_to_bitstream_file(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info, + t_llist* cur_conf_bit_head); + + +/* Generate a file contain all the configuration bits of the mapped FPGA. + * The configuration bits are loaded to FPGA in a stream, which is called bitstream + * In this file, the property of configuration bits will be shown as comments, + * which is easy for developers to debug + */ +void dump_fpga_spice_bitstream(char* bitstream_file_name, + char* circuit_name, + t_sram_orgz_info* cur_sram_orgz_info) { + FILE* fp; + + /* Check if the path exists*/ + fp = fopen(bitstream_file_name,"w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create bitstream %s!",__FILE__, __LINE__, bitstream_file_name); + exit(1); + } + + vpr_printf(TIO_MESSAGE_INFO, "Writing bitstream file (%s) for %s...\n", + bitstream_file_name, circuit_name); + + /* Reset counter */ + dumped_num_conf_bits = 0; + + /* Find the head of bitstream: which is the tail of linked list */ + /* rec_dump_conf_bits_to_bitstream_file(fp, cur_sram_orgz_info, cur_sram_orgz_info->conf_bit_head); */ + dump_conf_bits_to_bitstream_file(fp, cur_sram_orgz_info, cur_sram_orgz_info->conf_bit_head); + + /* close file */ + fclose(fp); + + vpr_printf(TIO_MESSAGE_INFO, "Dumped %d configuration bits into bitstream file...\n", + dumped_num_conf_bits); + + /* Free the linked-list contain configuration bits ? */ + + return; +} + +/* Encode the given input to the address for a decode*/ +void encode_decoder_addr(int input, + int decoder_size, char* addr) { + int temp = input; + int i; + + assert(NULL != addr); + /* Check the length of addr !*/ + // assert((decoder_size + 1) == len_addr); + /* Add the end of a string */ + addr[decoder_size] = '\0'; + + for (i = 0; i < decoder_size; i++) { + addr[i] = '0'; + } + + i = decoder_size - 1; + + /* Actually, we convert a decimal number to its binary format */ + while (0 != temp) { + addr[i] = (temp % 2) + '0'; + temp = temp/2; + i--; + /* Check i is still in the boundary */ + if (i < 0) { + break; /* Quit the loop */ + } + } + /* May be the decoder size is too small */ + if (0 != temp) { + vpr_printf(TIO_MESSAGE_WARNING, "(File:%s,[LINE%d])Decoder size(%d) is too small for input(%d)!\n", + __FILE__, __LINE__, decoder_size, input); + } + + return; +} + +/* Recursively dump configuration bits which are stored in the linked list + * We start dump configuration bit from the tail of the linked list + * until the head of the linked list + */ +static +void rec_dump_conf_bits_to_bitstream_file(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info, + t_llist* cur_conf_bit) { + t_conf_bit_info* cur_conf_bit_info = (t_conf_bit_info*)(cur_conf_bit->dptr); + int num_bl, num_wl, bl_decoder_size, wl_decoder_size; + char* bl_addr = NULL; + char* wl_addr = NULL; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!",__FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert(NULL != cur_conf_bit_info); + + if (NULL != cur_conf_bit->next) { + /* This is not the tail, keep going */ + rec_dump_conf_bits_to_bitstream_file(fp, cur_sram_orgz_info, cur_conf_bit->next); + } + + /* We alraedy touch the tail, start dump */ + switch (cur_sram_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + case SPICE_SRAM_SCAN_CHAIN: + /* Scan-chain only loads the SRAM values */ + fprintf(fp, "%d, ", cur_conf_bit_info->sram_bit->val), + fprintf(fp, "// Configuration bit No.: %d, ", cur_conf_bit_info->index); + fprintf(fp, " SRAM value: %d, ", cur_conf_bit_info->sram_bit->val); + fprintf(fp, " SPICE model name: %s, ", cur_conf_bit_info->parent_spice_model->name); + fprintf(fp, " SPICE model index: %d ", cur_conf_bit_info->parent_spice_model_index); + fprintf(fp, "\n"); + /* Update the counter */ + dumped_num_conf_bits++; + break; + case SPICE_SRAM_MEMORY_BANK: + get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &num_bl, &num_wl); + bl_decoder_size = determine_decoder_size(num_bl); + wl_decoder_size = determine_decoder_size(num_wl); + + /* Memory bank requires the address to be given to the decoder*/ + /* Word line address */ + bl_addr = (char*)my_calloc(bl_decoder_size + 1, sizeof(char)); + /* If this WL is selected , we decode its index to address */ + assert(NULL != cur_conf_bit_info->bl); + encode_decoder_addr(cur_conf_bit_info->bl->addr, bl_decoder_size, bl_addr); + fprintf(fp, "bl'%s = %d, ", bl_addr, cur_conf_bit_info->bl->val); + fprintf(fp, "// Configuration bit No.: %d, ", cur_conf_bit_info->index); + fprintf(fp, " Bit Line: %d, ", cur_conf_bit_info->bl->val); + fprintf(fp, " SPICE model name: %s, ", cur_conf_bit_info->parent_spice_model->name); + fprintf(fp, " SPICE model index: %d ", cur_conf_bit_info->parent_spice_model_index); + fprintf(fp, "\n"); + /* Bit line address */ + /* If this WL is selected , we decode its index to address */ + wl_addr = (char*)my_calloc(wl_decoder_size + 1, sizeof(char)); + assert(NULL != cur_conf_bit_info->wl); + encode_decoder_addr(cur_conf_bit_info->wl->addr, wl_decoder_size, wl_addr); + fprintf(fp, "wl'%s = %d, ", wl_addr, cur_conf_bit_info->wl->val); + fprintf(fp, "// Configuration bit No.: %d, ", cur_conf_bit_info->index); + fprintf(fp, " Word Line: %d, ", cur_conf_bit_info->wl->val); + fprintf(fp, " SPICE model name: %s, ", cur_conf_bit_info->parent_spice_model->name); + fprintf(fp, " SPICE model index: %d ", cur_conf_bit_info->parent_spice_model_index); + fprintf(fp, "\n"); + /* Update the counter */ + dumped_num_conf_bits++; + /* Free */ + my_free(wl_addr); + my_free(bl_addr); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization in Verilog Generator!\n", + __FILE__, __LINE__); + exit(1); + } + + + return; +} + +/* Dump a bitstream by using while loop */ +static +void dump_conf_bits_to_bitstream_file(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info, + t_llist* cur_conf_bit_head) { + t_llist* temp = cur_conf_bit_head; + t_conf_bit_info* cur_conf_bit_info = NULL; + int num_bl, num_wl, bl_decoder_size, wl_decoder_size; + char* bl_addr = NULL; + char* wl_addr = NULL; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!",__FILE__, __LINE__); + exit(1); + } + + get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &num_bl, &num_wl); + bl_decoder_size = determine_decoder_size(num_bl); + wl_decoder_size = determine_decoder_size(num_wl); + + + while (NULL != temp) { + cur_conf_bit_info = (t_conf_bit_info*)(temp->dptr); + /* We alraedy touch the tail, start dump */ + switch (cur_sram_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + case SPICE_SRAM_SCAN_CHAIN: + /* Scan-chain only loads the SRAM values */ + fprintf(fp, "%d, ", cur_conf_bit_info->sram_bit->val), + fprintf(fp, "// Configuration bit No.: %d, ", cur_conf_bit_info->index); + fprintf(fp, " SRAM value: %d, ", cur_conf_bit_info->sram_bit->val); + fprintf(fp, " SPICE model name: %s, ", cur_conf_bit_info->parent_spice_model->name); + fprintf(fp, " SPICE model index: %d ", cur_conf_bit_info->parent_spice_model_index); + fprintf(fp, "\n"); + /* Update the counter */ + dumped_num_conf_bits++; + break; + case SPICE_SRAM_MEMORY_BANK: + /* Memory bank requires the address to be given to the decoder*/ + /* Word line address */ + bl_addr = (char*)my_calloc(bl_decoder_size + 1, sizeof(char)); + /* If this WL is selected , we decode its index to address */ + assert(NULL != cur_conf_bit_info->bl); + encode_decoder_addr(cur_conf_bit_info->bl->addr, bl_decoder_size, bl_addr); + fprintf(fp, "bl'%s = %d, ", bl_addr, cur_conf_bit_info->bl->val); + fprintf(fp, "// Configuration bit No.: %d, ", cur_conf_bit_info->index); + fprintf(fp, " Bit Line: %d, ", cur_conf_bit_info->bl->val); + fprintf(fp, " SPICE model name: %s, ", cur_conf_bit_info->parent_spice_model->name); + fprintf(fp, " SPICE model index: %d ", cur_conf_bit_info->parent_spice_model_index); + fprintf(fp, "\n"); + /* Bit line address */ + /* If this WL is selected , we decode its index to address */ + wl_addr = (char*)my_calloc(wl_decoder_size + 1, sizeof(char)); + assert(NULL != cur_conf_bit_info->wl); + encode_decoder_addr(cur_conf_bit_info->wl->addr, wl_decoder_size, wl_addr); + fprintf(fp, "wl'%s = %d, ", wl_addr, cur_conf_bit_info->wl->val); + fprintf(fp, "// Configuration bit No.: %d, ", cur_conf_bit_info->index); + fprintf(fp, " Word Line: %d, ", cur_conf_bit_info->wl->val); + fprintf(fp, " SPICE model name: %s, ", cur_conf_bit_info->parent_spice_model->name); + fprintf(fp, " SPICE model index: %d ", cur_conf_bit_info->parent_spice_model_index); + fprintf(fp, "\n"); + /* Free */ + my_free(wl_addr); + my_free(bl_addr); + /* Update the counter */ + dumped_num_conf_bits++; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization in Verilog Generator!\n", + __FILE__, __LINE__); + exit(1); + } + /* Go to next */ + temp = temp->next; + } + + return; +} diff --git a/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_bitstream.h b/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_bitstream.h new file mode 100644 index 000000000..ac43b1881 --- /dev/null +++ b/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_bitstream.h @@ -0,0 +1,7 @@ + +void encode_decoder_addr(int input, + int decoder_size, char* addr); + +void dump_fpga_spice_bitstream(char* bitstream_file_name, + char* circuit_name, + t_sram_orgz_info* cur_sram_orgz_info); diff --git a/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_globals.c b/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_globals.c new file mode 100644 index 000000000..60e727c27 --- /dev/null +++ b/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_globals.c @@ -0,0 +1,42 @@ +/***********************************/ +/* FPGA-SPICE for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include "spice_types.h" +#include "linkedlist.h" +#include "fpga_spice_globals.h" + +/* Global variables to be shared by different tools of FPGA-SPICE */ +/* SRAM SPICE MODEL should be set as global*/ +t_spice_model* fpga_spice_sram_model = NULL; +enum e_sram_orgz fpga_spice_sram_orgz_type = SPICE_SRAM_STANDALONE; +/* Input and Output Pad spice model. should be set as global */ +t_spice_model* fpga_spice_inpad_model = NULL; +t_spice_model* fpga_spice_outpad_model = NULL; +t_spice_model* fpga_spice_iopad_model = NULL; + +/* Prefix of global input, output and inout of a I/O pad */ +char* gio_inout_prefix = "gfpga_pad_"; + +/* Number of configuration bits of each switch block */ +int** num_conf_bits_sb = NULL; +/* Number of configuration bits of each Connection Box CHANX */ +int** num_conf_bits_cbx = NULL; +/* Number of configuration bits of each Connection Box CHANY */ +int** num_conf_bits_cby = NULL; + +/* Linked list for global ports */ +t_llist* global_ports_head = NULL; + +/* Linked list for verilog and spice syntax char */ +t_llist* reserved_syntax_char_head = NULL; + +/* Default value of a signal */ +int default_signal_init_value = 0; + +/* Default do parasitic net estimation !!!*/ +boolean run_parasitic_net_estimation = TRUE; +boolean run_testbench_load_extraction = TRUE; + +char* renaming_report_postfix = "_io_renaming.rpt"; diff --git a/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_globals.h b/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_globals.h new file mode 100644 index 000000000..4b5c31b26 --- /dev/null +++ b/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_globals.h @@ -0,0 +1,39 @@ +/* global parameters for FPGA-SPICE tool suites */ + +extern t_spice_model* fpga_spice_sram_model; +extern enum e_sram_orgz fpga_spice_sram_orgz_type; + +/* Input and Output Pad spice model. should be set as global */ +extern t_spice_model* fpga_spice_inpad_model; +extern t_spice_model* fpga_spice_outpad_model; +extern t_spice_model* fpga_spice_iopad_model; + +/* Number of configuration bits of each switch block */ +extern int** num_conf_bits_sb; +/* Number of configuration bits of each Connection Box CHANX */ +extern int** num_conf_bits_cbx; +/* Number of configuration bits of each Connection Box CHANY */ +extern int** num_conf_bits_cby; + +/* Prefix of global input, output and inout of a I/O pad */ +extern char* gio_input_prefix; +extern char* gio_output_prefix; +extern char* gio_inout_prefix; + +extern int default_signal_init_value; +extern boolean run_parasitic_net_estimation; +extern boolean run_testbench_load_extraction; + +/* Linked list for global ports */ +extern t_llist* global_ports_head; + +/* Linked list for verilog and spice syntax char */ +extern t_llist* reserved_syntax_char_head; + +/* Enumeration */ +enum e_pin2pin_interc_type { + INPUT2INPUT_INTERC, OUTPUT2OUTPUT_INTERC +}; + + +extern char* renaming_report_postfix; diff --git a/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_setup.c b/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_setup.c new file mode 100644 index 000000000..0acaaab5d --- /dev/null +++ b/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_setup.c @@ -0,0 +1,1263 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph.h" +#include "vpr_utils.h" +#include "path_delay.h" +#include "stats.h" + +/* Include spice support headers*/ +#include "linkedlist.h" +#include "fpga_spice_globals.h" +#include "fpga_spice_utils.h" +#include "fpga_spice_backannotate_utils.h" +#include "syn_verilog_api.h" +#include "fpga_spice_setup.h" + +/***** Subroutines Declarations *****/ +static +int map_pb_type_port_to_spice_model_ports(t_pb_type* cur_pb_type, + t_spice_model* cur_spice_model); + +static +void match_pb_types_spice_model_rec(t_pb_type* cur_pb_type, + int num_spice_model, + t_spice_model* spice_models); + +static +void init_and_check_one_sram_inf_orgz(t_sram_inf_orgz* cur_sram_inf_orgz, + int num_spice_model, + t_spice_model* spice_models); + +static +void init_and_check_sram_inf(t_arch* arch, + t_det_routing_arch* routing_arch); + +static +t_llist* check_and_add_one_global_port_to_llist(t_llist* old_head, + t_spice_model_port* candidate_port); + +static +void rec_stat_pb_type_keywords(t_pb_type* cur_pb_type, + int* num_keyword); + +static +void rec_add_pb_type_keywords_to_list(t_pb_type* cur_pb_type, + int* cur, + char** keywords, + char* prefix); + +static +int check_conflict_syntax_char_in_string(t_llist* LL_reserved_syntax_char_head, + char* str_to_check); + +static +void check_spice_model_name_conflict_syntax_char(t_arch Arch, + t_llist* LL_reseved_syntax_char_head); + +static +t_llist* init_llist_verilog_and_spice_syntax_char(); + +static +boolean is_verilog_and_spice_syntax_conflict_char(t_llist* LL_reserved_syntax_char_head, + char ref_char); + +static +int check_and_rename_logical_block_and_net_names(t_llist* LL_reserved_syntax_char_head, + char* circuit_name, + boolean rename_illegal_port, + int LL_num_logical_blocks, t_logical_block* LL_logical_block, + int LL_num_clb_nets, t_net* LL_clb_net, + int LL_num_vpack_nets, t_net* LL_vpack_net); + +/***** Subroutines *****/ + +/* Map (synchronize) pb_type ports to SPICE model ports + */ +static +int map_pb_type_port_to_spice_model_ports(t_pb_type* cur_pb_type, + t_spice_model* cur_spice_model) { + int iport; + t_port* cur_pb_type_port = NULL; + + /* Check */ + assert(NULL != cur_pb_type); + + /* Initialize each port */ + for (iport = 0; iport < cur_pb_type->num_ports; iport++) { + cur_pb_type->ports[iport].spice_model_port = NULL; + } + + /* Return if SPICE_MODEL is NULL */ + if (NULL == cur_spice_model) { + return 0; + } + + /* For each port, find a SPICE model port, which has the same name and port size */ + for (iport = 0; iport < cur_spice_model->num_port; iport++) { + cur_pb_type_port = + find_pb_type_port_match_spice_model_port(cur_pb_type, + &(cur_spice_model->ports[iport])); + /* Not every spice_model_port can find a mapped pb_type_port. + * Since a pb_type only includes necessary ports in technology mapping. + * ports for physical designs may be ignored ! + */ + if (NULL != cur_pb_type_port) { + cur_pb_type_port->spice_model_port = &(cur_spice_model->ports[iport]); + } + } + /* Although some spice_model_port may not have a corresponding pb_type_port + * but each pb_type_port should be mapped to a spice_model_port + */ + for (iport = 0; iport < cur_pb_type->num_ports; iport++) { + if (NULL == cur_pb_type->ports[iport].spice_model_port) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Pb_type(%s) Port(%s) cannot find a corresponding port in SPICE model(%s)", + __FILE__, __LINE__, cur_pb_type->name, cur_pb_type->ports[iport].name, + cur_spice_model->name); + exit(1); + } + } + + return cur_pb_type->num_ports; +} + +/* Find spice_model_name definition in pb_types + * Try to match the name with defined spice_models + */ +static +void match_pb_types_spice_model_rec(t_pb_type* cur_pb_type, + int num_spice_model, + t_spice_model* spice_models) { + int imode, ipb, jinterc; + + if (NULL == cur_pb_type) { + vpr_printf(TIO_MESSAGE_WARNING,"(File:%s,LINE[%d])cur_pb_type is null pointor!\n",__FILE__,__LINE__); + return; + } + + /* If there is a spice_model_name, this is a leaf node!*/ + if (NULL != cur_pb_type->spice_model_name) { + /* What annoys me is VPR create a sub pb_type for each lut which suppose to be a leaf node + * This may bring software convience but ruins SPICE modeling + */ + /* Let's find a matched spice model!*/ + printf("INFO: matching cur_pb_type=%s with spice_model_name=%s...\n",cur_pb_type->name, cur_pb_type->spice_model_name); + assert(NULL == cur_pb_type->spice_model); + cur_pb_type->spice_model = find_name_matched_spice_model(cur_pb_type->spice_model_name, num_spice_model, spice_models); + if (NULL == cur_pb_type->spice_model) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d]) Fail to find a defined SPICE model called %s, in pb_type(%s)!\n",__FILE__, __LINE__, cur_pb_type->spice_model_name, cur_pb_type->name); + exit(1); + } + /* Map pb_type ports to SPICE model ports*/ + map_pb_type_port_to_spice_model_ports(cur_pb_type,cur_pb_type->spice_model); + return; + } + /* Traversal the hierarchy*/ + for (imode = 0; imode < cur_pb_type->num_modes; imode++) { + /* Task 1: Find the interconnections and match the spice_model */ + for (jinterc = 0; jinterc < cur_pb_type->modes[imode].num_interconnect; jinterc++) { + assert(NULL == cur_pb_type->modes[imode].interconnect[jinterc].spice_model); + /* If the spice_model_name is not defined, we use the default*/ + if (NULL == cur_pb_type->modes[imode].interconnect[jinterc].spice_model_name) { + switch (cur_pb_type->modes[imode].interconnect[jinterc].type) { + case DIRECT_INTERC: + cur_pb_type->modes[imode].interconnect[jinterc].spice_model = + get_default_spice_model(SPICE_MODEL_WIRE,num_spice_model,spice_models); + break; + case COMPLETE_INTERC: + /* Special for Completer Interconnection: + * 1. The input number is 1, this infers a direct interconnection. + * 2. The input number is larger than 1, this infers multplexers + * according to interconnect[j].num_mux identify the number of input at this level + */ + if (0 == cur_pb_type->modes[imode].interconnect[jinterc].num_mux) { + cur_pb_type->modes[imode].interconnect[jinterc].spice_model = + get_default_spice_model(SPICE_MODEL_WIRE,num_spice_model,spice_models); + } else { + cur_pb_type->modes[imode].interconnect[jinterc].spice_model = + get_default_spice_model(SPICE_MODEL_MUX,num_spice_model,spice_models); + } + break; + case MUX_INTERC: + cur_pb_type->modes[imode].interconnect[jinterc].spice_model = + get_default_spice_model(SPICE_MODEL_MUX,num_spice_model,spice_models); + break; + default: + break; + } + vpr_printf(TIO_MESSAGE_INFO,"INFO: Link a SPICE model (%s) for Interconnect (%s)!\n", + cur_pb_type->modes[imode].interconnect[jinterc].spice_model->name, cur_pb_type->modes[imode].interconnect[jinterc].name); + } else { + cur_pb_type->modes[imode].interconnect[jinterc].spice_model = + find_name_matched_spice_model(cur_pb_type->modes[imode].interconnect[jinterc].spice_model_name, num_spice_model, spice_models); + vpr_printf(TIO_MESSAGE_INFO,"INFO: Link a SPICE model (%s) for Interconnect (%s)!\n", + cur_pb_type->modes[imode].interconnect[jinterc].spice_model->name, cur_pb_type->modes[imode].interconnect[jinterc].name); + if (NULL == cur_pb_type->modes[imode].interconnect[jinterc].spice_model) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d]) Fail to find a defined SPICE model called %s, in pb_type(%s)!\n",__FILE__, __LINE__, cur_pb_type->modes[imode].interconnect[jinterc].spice_model_name, cur_pb_type->name); + exit(1); + } + switch (cur_pb_type->modes[imode].interconnect[jinterc].type) { + case DIRECT_INTERC: + if (SPICE_MODEL_WIRE != cur_pb_type->modes[imode].interconnect[jinterc].spice_model->type) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d]) Invalid type of matched SPICE model called %s, in pb_type(%s)! Sould be wire!\n",__FILE__, __LINE__, cur_pb_type->modes[imode].interconnect[jinterc].spice_model_name, cur_pb_type->name); + exit(1); + } + break; + case COMPLETE_INTERC: + if (0 == cur_pb_type->modes[imode].interconnect[jinterc].num_mux) { + if (SPICE_MODEL_WIRE != cur_pb_type->modes[imode].interconnect[jinterc].spice_model->type) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d]) Invalid type of matched SPICE model called %s, in pb_type(%s)! Sould be wire!\n",__FILE__, __LINE__, cur_pb_type->modes[imode].interconnect[jinterc].spice_model_name, cur_pb_type->name); + exit(1); + } + } else { + if (SPICE_MODEL_MUX != cur_pb_type->modes[imode].interconnect[jinterc].spice_model->type) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d]) Invalid type of matched SPICE model called %s, in pb_type(%s)! Sould be MUX!\n",__FILE__, __LINE__, cur_pb_type->modes[imode].interconnect[jinterc].spice_model_name, cur_pb_type->name); + exit(1); + } + } + break; + case MUX_INTERC: + if (SPICE_MODEL_MUX != cur_pb_type->modes[imode].interconnect[jinterc].spice_model->type) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d]) Invalid type of matched SPICE model called %s, in pb_type(%s)! Sould be MUX!\n",__FILE__, __LINE__, cur_pb_type->modes[imode].interconnect[jinterc].spice_model_name, cur_pb_type->name); + exit(1); + } + break; + default: + break; + } + } + } + /* Task 2: Find the child pb_type, do matching recursively */ + //if (1 == cur_pb_type->modes[imode].define_spice_model) { + for (ipb = 0; ipb < cur_pb_type->modes[imode].num_pb_type_children; ipb++) { + match_pb_types_spice_model_rec(&cur_pb_type->modes[imode].pb_type_children[ipb], + num_spice_model, + spice_models); + } + //} + } + return; +} + +static +void init_and_check_one_sram_inf_orgz(t_sram_inf_orgz* cur_sram_inf_orgz, + int num_spice_model, + t_spice_model* spice_models) { + /* If cur_sram_inf_orgz is not initialized, do nothing */ + if (NULL == cur_sram_inf_orgz) { + return; + } + + /* For SRAM */ + if (NULL == cur_sram_inf_orgz->spice_model_name) { + cur_sram_inf_orgz->spice_model = get_default_spice_model(SPICE_MODEL_SRAM, + num_spice_model, + spice_models); + } else { + cur_sram_inf_orgz->spice_model = + find_name_matched_spice_model(cur_sram_inf_orgz->spice_model_name, + num_spice_model, + spice_models); + } + + if (NULL == cur_sram_inf_orgz->spice_model) { + if (NULL == cur_sram_inf_orgz->spice_model_name) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d]) Cannot find any SRAM spice model!\n", + __FILE__ ,__LINE__); + exit(1); + } else { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d])Invalid SPICE model name(%s) of SRAM is undefined in SPICE models!\n", + __FILE__ ,__LINE__, cur_sram_inf_orgz->spice_model_name); + exit(1); + } + } + + /* Check the type of SRAM_SPICE_MODEL */ + switch (cur_sram_inf_orgz->type) { + case SPICE_SRAM_STANDALONE: + vpr_printf(TIO_MESSAGE_INFO, "INFO: Checking if SRAM spice model fit standalone organization...\n"); + if (SPICE_MODEL_SRAM != cur_sram_inf_orgz->spice_model->type) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d]) Standalone SRAM organization requires a SPICE model(type=sram)!\n", + __FILE__, __LINE__); + exit(1); + } + /* TODO: check SRAM ports */ + check_sram_spice_model_ports(cur_sram_inf_orgz->spice_model, FALSE); + break; + case SPICE_SRAM_SCAN_CHAIN: + vpr_printf(TIO_MESSAGE_INFO, "INFO: Checking if SRAM spice model fit scan-chain organization...\n"); + if (SPICE_MODEL_SCFF != cur_sram_inf_orgz->spice_model->type) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d]) Scan-chain SRAM organization requires a SPICE model(type=sff)!\n", + __FILE__, __LINE__); + exit(1); + } + /* TODO: check Scan-chain Flip-flop ports */ + check_ff_spice_model_ports(cur_sram_inf_orgz->spice_model, TRUE); + /* TODO: RRAM Scan-chain is not supported yet. Now just forbidden this option */ + if (SPICE_MODEL_DESIGN_RRAM == cur_sram_inf_orgz->spice_model->design_tech) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d]) RRAM-based Scan-chain Flip-flop has not been supported yet!\n", + __FILE__, __LINE__); + exit(1); + } + break; + case SPICE_SRAM_MEMORY_BANK: + vpr_printf(TIO_MESSAGE_INFO, "INFO: Checking if SRAM spice model fit memory-bank organization...\n"); + if (SPICE_MODEL_SRAM != cur_sram_inf_orgz->spice_model->type) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d]) Memory-bank SRAM organization requires a SPICE model(type=sram)!\n", + __FILE__, __LINE__); + exit(1); + } + /* TODO: check if this one has bit lines and word lines */ + check_sram_spice_model_ports(cur_sram_inf_orgz->spice_model, TRUE); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d]) Invalid SRAM organization type!\n", + __FILE__, __LINE__); + exit(1); + } + + return; +} + +static +void init_and_check_sram_inf(t_arch* arch, + t_det_routing_arch* routing_arch) { + /* We have two branches: + * 1. SPICE SRAM organization information + * 2. Verilog SRAM organization information + */ + init_and_check_one_sram_inf_orgz(arch->sram_inf.spice_sram_inf_orgz, + arch->spice->num_spice_model, + arch->spice->spice_models); + + init_and_check_one_sram_inf_orgz(arch->sram_inf.verilog_sram_inf_orgz, + arch->spice->num_spice_model, + arch->spice->spice_models); + + + return; +} + +/* Initialize and check spice models in architecture + * Tasks: + * 1. Link the spice model defined in pb_types and routing switches + * 2. Add default spice model (MUX) if needed + */ +void init_check_arch_spice_models(t_arch* arch, + t_det_routing_arch* routing_arch) { + int i, iport; + + vpr_printf(TIO_MESSAGE_INFO,"Initializing and checking SPICE models...\n"); + /* Check Spice models first*/ + assert(NULL != arch); + assert(NULL != arch->spice); + if ((0 == arch->spice->num_spice_model)||(0 > arch->spice->num_spice_model)) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d])SPICE models are not defined! Miss this part in architecture file.\n",__FILE__,__LINE__); + exit(1); + } + assert(NULL != arch->spice->spice_models); + + /* Find default spice model*/ + /* MUX */ + if (NULL == get_default_spice_model(SPICE_MODEL_MUX, + arch->spice->num_spice_model, + arch->spice->spice_models)) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d])Fail to find the default MUX SPICE Model! Should define it in architecture file\n",__FILE__,__LINE__); + exit(1); + } + + /* Channel Wire */ + if (NULL == get_default_spice_model(SPICE_MODEL_CHAN_WIRE, + arch->spice->num_spice_model, + arch->spice->spice_models)) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d])Fail to find the default Channel Wire SPICE Model! Should define it in architecture file\n",__FILE__,__LINE__); + exit(1); + } + + /* Wire */ + if (NULL == get_default_spice_model(SPICE_MODEL_WIRE, + arch->spice->num_spice_model, + arch->spice->spice_models)) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d])Fail to find the default Wire SPICE Model! Should define it in architecture file\n",__FILE__,__LINE__); + exit(1); + } + + /* Link the input/output buffer spice models to higher level spice models + * Configure (fill information) the input/output buffers of high level spice models */ + config_spice_model_input_output_buffers_pass_gate(arch->spice->num_spice_model, + arch->spice->spice_models); + + /* Find inversion spice_model for ports */ + config_spice_model_port_inv_spice_model(arch->spice->num_spice_model, + arch->spice->spice_models); + + /* 1. Link the spice model defined in pb_types and routing switches */ + /* Step A: Check routing switches, connection blocks*/ + if ((0 == arch->num_cb_switch)||(0 > arch->num_cb_switch)) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d]) Define Switches for Connection Blocks is mandatory in SPICE model support! Miss this part in architecture file.\n",__FILE__,__LINE__); + exit(1); + } + + for (i = 0; i < arch->num_cb_switch; i++) { + arch->cb_switches[i].spice_model = + find_name_matched_spice_model(arch->cb_switches[i].spice_model_name, + arch->spice->num_spice_model, + arch->spice->spice_models); + if (NULL == arch->cb_switches[i].spice_model) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d])Invalid SPICE model name(%s) of Switch(%s) is undefined in SPICE models!\n",__FILE__ ,__LINE__, arch->cb_switches[i].spice_model_name, arch->cb_switches[i].name); + exit(1); + } + /* Check the spice model structure is matched with the structure in switch_inf */ + if (FALSE == check_spice_model_structure_match_switch_inf(arch->cb_switches[i])) { + exit(1); + } + } + + /* Step B: Check switch list: Switch Box*/ + if ((0 == arch->num_switches)||(0 > arch->num_switches)) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d]) Define Switches for Switch Boxes is mandatory in SPICE model support! Miss this part in architecture file.\n",__FILE__,__LINE__); + exit(1); + } + + for (i = 0; i < arch->num_switches; i++) { + arch->Switches[i].spice_model = + find_name_matched_spice_model(arch->Switches[i].spice_model_name, + arch->spice->num_spice_model, + arch->spice->spice_models); + if (NULL == arch->Switches[i].spice_model) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d])Invalid SPICE model name(%s) of Switch(%s) is undefined in SPICE models!\n",__FILE__ ,__LINE__, arch->Switches[i].spice_model_name, arch->Switches[i].name); + exit(1); + } + /* Check the spice model structure is matched with the structure in switch_inf */ + if (FALSE == check_spice_model_structure_match_switch_inf(arch->Switches[i])) { + exit(1); + } + } + + /* Update the switches in detailed routing architecture settings*/ + for (i = 0; i < routing_arch->num_switch; i++) { + if (NULL == switch_inf[i].spice_model_name) { + switch_inf[i].spice_model = get_default_spice_model(SPICE_MODEL_MUX, + arch->spice->num_spice_model, + arch->spice->spice_models); + continue; + } + switch_inf[i].spice_model = + find_name_matched_spice_model(switch_inf[i].spice_model_name, + arch->spice->num_spice_model, + arch->spice->spice_models); + if (NULL == switch_inf[i].spice_model) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d])Invalid SPICE model name(%s) of Switch(%s) is undefined in SPICE models!\n",__FILE__ ,__LINE__, switch_inf[i].spice_model_name, switch_inf[i].name); + exit(1); + } + } + + /* Step C: Find SRAM Model*/ + init_and_check_sram_inf(arch, routing_arch); + + /* Step D: Find the segment spice_model*/ + for (i = 0; i < arch->num_segments; i++) { + if (NULL == arch->Segments[i].spice_model_name) { + arch->Segments[i].spice_model = + get_default_spice_model(SPICE_MODEL_CHAN_WIRE, + arch->spice->num_spice_model, + arch->spice->spice_models); + continue; + } else { + arch->Segments[i].spice_model = + find_name_matched_spice_model(arch->Segments[i].spice_model_name, + arch->spice->num_spice_model, + arch->spice->spice_models); + } + if (NULL == arch->Segments[i].spice_model) { + vpr_printf(TIO_MESSAGE_ERROR, "(FILE:%s, LINE[%d])Invalid SPICE model name(%s) of Segment(Length:%d) is undefined in SPICE models!\n", + __FILE__ ,__LINE__, + arch->Segments[i].spice_model_name, + arch->Segments[i].length); + exit(1); + } else if (SPICE_MODEL_CHAN_WIRE != arch->Segments[i].spice_model->type) { + vpr_printf(TIO_MESSAGE_ERROR, "(FILE:%s, LINE[%d])Invalid SPICE model(%s) type of Segment(Length:%d)! Should be chan_wire!\n", + __FILE__ , __LINE__, + arch->Segments[i].spice_model_name, + arch->Segments[i].length); + exit(1); + } + } + + /* 2. Search Complex Blocks (Pb_Types), Link spice_model according to the spice_model_name*/ + for (i = 0; i < num_types; i++) { + if (type_descriptors[i].pb_type) { + match_pb_types_spice_model_rec(type_descriptors[i].pb_type, + arch->spice->num_spice_model, + arch->spice->spice_models); + } + } + + /* 3. Initial grid_index_low/high for each spice_model */ + for (i = 0; i < arch->spice->num_spice_model; i++) { + alloc_spice_model_grid_index_low_high(&(arch->spice->spice_models[i])); + alloc_spice_model_routing_index_low_high(&(arch->spice->spice_models[i])); + } + /* 4. zero the counter of each spice_model */ + zero_spice_models_cnt(arch->spice->num_spice_model, arch->spice->spice_models); + /* 5. zero all index low high */ + /* + zero_spice_model_grid_index_low_high(arch->spice->num_spice_model, arch->spice->spice_models); + zero_spice_models_routing_index_low_high(arch->spice->num_spice_model, arch->spice->spice_models); + */ + + /* 6. Check each port of a spice model and create link to another spice model */ + for (i = 0; i < arch->spice->num_spice_model; i++) { + for (iport = 0; iport < arch->spice->spice_models[i].num_port; iport++) { + /* Set to NULL pointor first */ + arch->spice->spice_models[i].ports[iport].spice_model = NULL; + if (NULL != arch->spice->spice_models[i].ports[iport].spice_model_name) { + arch->spice->spice_models[i].ports[iport].spice_model = + find_name_matched_spice_model(arch->spice->spice_models[i].ports[iport].spice_model_name, + arch->spice->num_spice_model, + arch->spice->spice_models); + } + } + } + + return; +} + +/* Statistics reserved names in pb_types to the list*/ +static +void rec_stat_pb_type_keywords(t_pb_type* cur_pb_type, + int* num_keyword) { + int imode, ipb, jpb; + + assert((0 == (*num_keyword))||(0 < (*num_keyword))); + assert(NULL != num_keyword); + assert(NULL != cur_pb_type); + + for (ipb = 0; ipb < cur_pb_type->num_pb; ipb++) { + for (imode = 0; imode < cur_pb_type->num_modes; imode++) { + /* pb_type_name[num_pb]_mode[mode_name]*/ + (*num_keyword) += 1; + for (jpb = 0; jpb < cur_pb_type->modes[imode].num_pb_type_children; jpb++) { + if (NULL == cur_pb_type->modes[imode].pb_type_children[jpb].spice_model) { + rec_stat_pb_type_keywords(&(cur_pb_type->modes[imode].pb_type_children[jpb]), + num_keyword); + } + } + } + } + + return; +} + +/* Add reserved names in pb_types to the list*/ +static +void rec_add_pb_type_keywords_to_list(t_pb_type* cur_pb_type, + int* cur, + char** keywords, + char* prefix) { + int imode, ipb, jpb; + char* formatted_prefix = format_spice_node_prefix(prefix); + char* pass_on_prefix = NULL; + + assert(NULL != cur); + assert((0 == (*cur))||(0 < (*cur))); + assert(NULL != keywords); + assert(NULL != cur_pb_type); + + /* pb_type_name[num_pb]_mode[mode_name]*/ + // num_keyword += cur_pb_type->num_pb * cur_pb_type->num_modes; + for (ipb = 0; ipb < cur_pb_type->num_pb; ipb++) { + for (imode = 0; imode < cur_pb_type->num_modes; imode++) { + keywords[(*cur)] = (char*)my_malloc(sizeof(char)* + (strlen(formatted_prefix) + strlen(cur_pb_type->name) + 1 + strlen(my_itoa(ipb)) + 7 + + strlen(cur_pb_type->modes[imode].name) + 2)); + sprintf(keywords[(*cur)], "%s%s[%d]_mode[%s]", formatted_prefix, cur_pb_type->name, ipb, cur_pb_type->modes[imode].name); + pass_on_prefix = my_strdup(keywords[(*cur)]); + (*cur)++; + for (jpb = 0; jpb < cur_pb_type->modes[imode].num_pb_type_children; jpb++) { + if (NULL == cur_pb_type->modes[imode].pb_type_children[jpb].spice_model) { + rec_add_pb_type_keywords_to_list(&(cur_pb_type->modes[imode].pb_type_children[jpb]), + cur, keywords, pass_on_prefix); + my_free(pass_on_prefix); + } + } + } + } + + my_free(formatted_prefix); + + return; +} + +/* This function checks conflicts between + * 1. SPICE model names and reserved sub-circuit names + */ +void check_keywords_conflict(t_arch Arch) { + int num_keyword = 0; + char**keywords; + int conflict = 0; + + int num_keyword_per_grid = 0; + int cur, iseg, imodel, i, iport; + int ix, iy, iz; + t_pb_type* cur_pb_type = NULL; + char* prefix = NULL; + t_llist* temp = NULL; + t_spice_model_port* cur_global_port = NULL; + + /* Generate the list of reserved names */ + num_keyword = 0; + keywords = NULL; + + /* Reserved names: grid names */ + /* Reserved names: pb_type names */ + for (ix = 0; ix < (nx + 2); ix++) { + for (iy = 0; iy < (ny + 2); iy++) { + /* by_pass the empty */ + if (EMPTY_TYPE != grid[ix][iy].type) { + num_keyword += 1; /* plus grid[ix][iy]*/ + for (iz = 0; iz < grid[ix][iy].type->capacity; iz++) { + num_keyword_per_grid = 0; + /* Per grid, type_descriptor.name[i]*/ + /* Go recursive pb_graph_node, until the leaf which defines a spice_model */ + cur_pb_type = grid[ix][iy].type->pb_type; + rec_stat_pb_type_keywords(cur_pb_type, &num_keyword_per_grid); + num_keyword += num_keyword_per_grid; + } + } + } + } + + /* Reserved names: switch boxes, connection boxes, channels */ + /* Channels -X */ + num_keyword += (ny+1) * nx; + /* Channels -Y */ + num_keyword += (nx+1) * ny; + /* Switch Boxes */ + /* sb[ix][iy]*/ + num_keyword += (nx + 1)*(ny + 1); + /* Connection Boxes */ + /* cbx[ix][iy] */ + num_keyword += (ny+1) * nx; + /* cby[ix][iy] */ + num_keyword += (nx+1) * ny; + + /* internal names: inv, buf, cpt, vpr_nmos, vpr_pmos, wire_segments */ + num_keyword += 5 + Arch.num_segments; + + /* Include keywords of global ports */ + temp = global_ports_head; + while (NULL != temp) { + cur_global_port = (t_spice_model_port*)(temp->dptr); + num_keyword += cur_global_port->size; + temp = temp->next; + } + + /* Malloc */ + keywords = (char**)my_malloc(sizeof(char*)*num_keyword); + + /* Add reserved names to the list */ + cur = 0; + for (i = 0; i < num_keyword; i++) { + keywords[i] = NULL; + } + /* Include keywords of global ports */ + temp = global_ports_head; + while (NULL != temp) { + cur_global_port = (t_spice_model_port*)(temp->dptr); + for (iport = 0; iport < cur_global_port->size; iport++) { + keywords[cur] = (char*)my_malloc(sizeof(char)* + (strlen(cur_global_port->prefix) + 2 + strlen(my_itoa(iport)) + 1)); + sprintf(keywords[cur], "%s[%d]", cur_global_port->prefix, iport); + cur++; + } + temp = temp->next; + } + /* internal names: inv, buf, cpt, vpr_nmos, vpr_pmos, wire_segments */ + keywords[cur] = "inv"; cur++; + keywords[cur] = "buf"; cur++; + keywords[cur] = "cpt"; cur++; + keywords[cur] = "vpr_nmos"; cur++; + keywords[cur] = "vpr_pmos"; cur++; + for (iseg = 0; iseg < Arch.num_segments; iseg++) { + keywords[cur] = (char*)my_malloc(sizeof(char)* + (strlen(Arch.Segments[iseg].spice_model->name) + 4 + strlen(my_itoa(iseg)) + 1)); + sprintf(keywords[cur], "%s_seg%d", Arch.Segments[iseg].spice_model->name, iseg); + cur++; + } + /* Reserved names: switch boxes, connection boxes, channels */ + /* Channels -X */ + for (iy = 0; iy < (ny + 1); iy++) { + for (ix = 1; ix < (nx + 1); ix++) { + /* chanx[ix][iy]*/ + keywords[cur] = (char*)my_malloc(sizeof(char)* (6 + strlen(my_itoa(ix)) + 2 + strlen(my_itoa(iy)) + 2)); + sprintf(keywords[cur], "chanx[%d][%d]", ix, iy); + cur++; + } + } + /* Channels -Y */ + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + /* chany[ix][iy]*/ + keywords[cur] = (char*)my_malloc(sizeof(char)* (6 + strlen(my_itoa(ix)) + 2 + strlen(my_itoa(iy)) + 2)); + sprintf(keywords[cur], "chany[%d][%d]", ix, iy); + cur++; + } + } + /* Connection Box */ + /* cbx[ix][iy]*/ + for (iy = 0; iy < (ny + 1); iy++) { + for (ix = 1; ix < (nx + 1); ix++) { + /* cbx[ix][iy]*/ + keywords[cur] = (char*)my_malloc(sizeof(char)* (4 + strlen(my_itoa(ix)) + 2 + strlen(my_itoa(iy)) + 2)); + sprintf(keywords[cur], "cbx[%d][%d]", ix, iy); + cur++; + } + } + /* cby[ix][iy]*/ + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + /* cby[ix][iy]*/ + keywords[cur] = (char*)my_malloc(sizeof(char)* (4 + strlen(my_itoa(ix)) + 2 + strlen(my_itoa(iy)) + 2)); + sprintf(keywords[cur], "cby[%d][%d]", ix, iy); + cur++; + } + } + /* Switch Boxes */ + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 0; iy < (ny + 1); iy++) { + /* sb[ix][iy]*/ + keywords[cur] = (char*)my_malloc(sizeof(char)* (3 + strlen(my_itoa(ix)) + 2 + strlen(my_itoa(iy)) + 2)); + sprintf(keywords[cur], "sb[%d][%d]", ix, iy); + cur++; + } + } + /* Reserved names: grid names */ + /* Reserved names: pb_type names */ + for (ix = 0; ix < (nx + 2); ix++) { + for (iy = 0; iy < (ny + 2); iy++) { + /* by_pass the empty */ + if (EMPTY_TYPE != grid[ix][iy].type) { + prefix = (char*)my_malloc(sizeof(char)* (5 + strlen(my_itoa(ix)) + 2 + strlen(my_itoa(iy)) + 2)); + sprintf(prefix, "grid[%d][%d]", ix, iy); + /* plus grid[ix][iy]*/ + keywords[cur] = my_strdup(prefix); + cur++; + for (iz = 0; iz < grid[ix][iy].type->capacity; iz++) { + /* Per grid, type_descriptor.name[i]*/ + /* Go recursive pb_graph_node, until the leaf which defines a spice_model */ + cur_pb_type = grid[ix][iy].type->pb_type; + rec_add_pb_type_keywords_to_list(cur_pb_type, &cur, keywords, prefix); + } + my_free(prefix); + } + } + } + /* assert */ + assert(cur == num_keyword); + + /* Check the keywords conflicted with defined spice_model names */ + for (imodel = 0; imodel < Arch.spice->num_spice_model; imodel++) { + for (i = 0; i < num_keyword; i++) { + if (0 == strcmp(Arch.spice->spice_models[imodel].name, keywords[i])) { + vpr_printf(TIO_MESSAGE_ERROR, "Keyword Conflicted! Spice Model Name: %s\n", keywords[i]); + conflict++; + } + } + } + + assert((0 == conflict)||(0 < conflict)); + if (0 < conflict) { + vpr_printf(TIO_MESSAGE_ERROR, "Found %d conflicted keywords!\n", conflict); + exit(1); + } + + return; +} + +/* Need to check if we already a global port with the same name in the list! + * This could happen where two spice models share the same global port + * If this is a new name in the list, we add this global port. + * Otherwise, we do nothing + */ +static +t_llist* check_and_add_one_global_port_to_llist(t_llist* old_head, + t_spice_model_port* candidate_port) { + boolean is_new_global_port = TRUE; + t_llist* temp = old_head; + t_llist* new_head = NULL; + + while (NULL != temp) { + if (0 == strcmp(candidate_port->prefix, + ((t_spice_model_port*)(temp->dptr))->prefix) ) { + /* Find a same global port name, we do nothing, return directly */ + is_new_global_port = FALSE; + return old_head; + } + /* Go to the next */ + temp = temp->next; + } + + new_head = insert_llist_node_before_head(old_head); + new_head->dptr = (void*)(candidate_port); + + return new_head; +} + +/* Create and Initialize the global ports + * Search all the ports defined under spice_models + * if a port is defined to be global, we add its pointer to the linked list + */ +static +t_llist* init_llist_global_ports(t_spice* spice) { + int imodel, iport; + t_llist* head = NULL; + + /* Traverse all the spice models */ + for (imodel = 0; imodel < spice->num_spice_model; imodel++) { + for (iport = 0; iport < spice->spice_models[imodel].num_port; iport++) { + if (TRUE == spice->spice_models[imodel].ports[iport].is_global) { + /* Check each global signal has non conflicted flags : + * At most one of the properties: is_config_enable, is_set and is_reset, can be true */ + assert(2 > (spice->spice_models[imodel].ports[iport].is_set + + spice->spice_models[imodel].ports[iport].is_reset + + spice->spice_models[imodel].ports[iport].is_config_enable)); + /* Add to linked list, the organization will be first-in last-out + * First element would be the tail of linked list + */ + head = check_and_add_one_global_port_to_llist(head,&(spice->spice_models[imodel].ports[iport])); + } + } + } + + return head; +} + +/* Check how many conflicts of syntax char in a string */ +static +int check_conflict_syntax_char_in_string(t_llist* LL_reserved_syntax_char_head, + char* str_to_check) { + int num_conflicts = 0; + int len_str_to_check = strlen(str_to_check); + int ichar = 0; + + for (ichar = 0; ichar < len_str_to_check; ichar++) { + if (TRUE == is_verilog_and_spice_syntax_conflict_char(LL_reserved_syntax_char_head, + str_to_check[ichar])) { + /* Print warning */ + vpr_printf(TIO_MESSAGE_ERROR, "String (%s) contains conflicted chars[%c] which is not allowed by Verilog and SPICE!\n", + str_to_check, str_to_check[ichar]); + num_conflicts++; + } + } + + return num_conflicts; +} + +/* Check if each spice_model name contains any syntax char, which is reseved by SPICE or Verilog */ +static +void check_spice_model_name_conflict_syntax_char(t_arch Arch, + t_llist* LL_reserved_syntax_char_head) { + int imodel, iport; + int num_conflicts = 0; + + /* Check spice_model one by one */ + for (imodel = 0; imodel < Arch.spice->num_spice_model; imodel++) { + /* Check spice_model->name */ + num_conflicts += check_conflict_syntax_char_in_string(LL_reserved_syntax_char_head, + Arch.spice->spice_models[imodel].name); + /* Check spice_model->prefix */ + num_conflicts += check_conflict_syntax_char_in_string(LL_reserved_syntax_char_head, + Arch.spice->spice_models[imodel].prefix); + /* Check each port name */ + for (iport = 0; iport < Arch.spice->spice_models[imodel].num_port; iport++) { + num_conflicts += check_conflict_syntax_char_in_string(LL_reserved_syntax_char_head, + Arch.spice->spice_models[imodel].ports[iport].prefix); + } + } + + if (0 < num_conflicts) { + /* Print warning */ + vpr_printf(TIO_MESSAGE_ERROR, "Fail in syntax char checking, conflicts have been detected!\n"); + exit(1); + } + + return; +} + +/* Initialize a linked-list for syntax char of Verilog and SPICE */ +static +t_llist* init_llist_verilog_and_spice_syntax_char() { + t_llist* new_head = NULL; + int num_syntax_chars = 0; + char* syntax_chars = NULL; + t_reserved_syntax_char* new_syntax_char = NULL; + int ichar = 0; + + syntax_chars = my_strdup(".,:;\'\"+-<>()[]{}!@#$%^&*~`?/"); + num_syntax_chars = strlen(syntax_chars); + + /* Create a new element */ + for (ichar = 0; ichar < num_syntax_chars; ichar++) { + new_syntax_char = (t_reserved_syntax_char*)(my_malloc(sizeof(t_reserved_syntax_char))); + new_head = insert_llist_node_before_head(new_head); + new_head->dptr = (void*)new_syntax_char; + init_reserved_syntax_char(new_syntax_char, syntax_chars[ichar], TRUE, TRUE); + } + + return new_head; +} + +/* Check if a char violates the syntax of Verilog and SPICE */ +static +boolean is_verilog_and_spice_syntax_conflict_char(t_llist* LL_reserved_syntax_char_head, + char ref_char) { + boolean syntax_conflict = FALSE; + t_llist* temp = LL_reserved_syntax_char_head; + t_reserved_syntax_char* cur_syntax_char = NULL; + + /* Search the conflict linked list ? */ + while (NULL != temp) { + cur_syntax_char = (t_reserved_syntax_char*)(temp->dptr); + if (ref_char == cur_syntax_char->syntax_char) { + syntax_conflict = TRUE; + break; + } + /* go to the next */ + temp = temp->next; + } + + return syntax_conflict; +} + +/* Check and rename the name of each IO logical block + * if the current name violates syntax of SPICE or Verilog + */ +static +int check_and_rename_logical_block_and_net_names(t_llist* LL_reserved_syntax_char_head, + char* circuit_name, + boolean rename_illegal_port, + int LL_num_logical_blocks, t_logical_block* LL_logical_block, + int LL_num_clb_nets, t_net* LL_clb_net, + int LL_num_vpack_nets, t_net* LL_vpack_net) { + FILE* fp = NULL; + int iblock, inet, ichar, name_str_len, num_violations; + char renamed_char = '_'; + boolean io_renamed = FALSE; + boolean io_violate_syntax = FALSE; + char* temp_io_name = NULL; + char* renaming_report_file_path = NULL; + + vpr_printf(TIO_MESSAGE_INFO, "Check IO pad names, to avoid violate SPICE or Verilog Syntax...\n"); + + num_violations = 0; + + /* Check if the path exists*/ + renaming_report_file_path = my_strcat(circuit_name, renaming_report_postfix); + fp = fopen(renaming_report_file_path,"w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create renaming report %s!", + __FILE__, __LINE__, renaming_report_file_path); + exit(1); + } + + fprintf(fp, "------- Logical block renaming report BEGIN ----------\n"); + for (iblock = 0; iblock < LL_num_logical_blocks; iblock++) { + /* Bypass non-IO logical blocks */ + /* + if ((VPACK_INPAD != logical_block[iblock].type)&&(VPACK_OUTPAD != logical_block[iblock].type)) { + continue; + } + */ + /* initialize the flag */ + io_renamed = FALSE; + io_violate_syntax = FALSE; + /* Keep a copy of previous name */ + temp_io_name = my_strdup(LL_logical_block[iblock].name); + /* Check names character by charcter */ + name_str_len = strlen(LL_logical_block[iblock].name); /* exclude the last character: \0, which does require to be checked */ + for (ichar = 0; ichar < name_str_len; ichar++) { + /* Check syntax senstive list, if violates, rename it to be '_' */ + if (TRUE == is_verilog_and_spice_syntax_conflict_char(LL_reserved_syntax_char_head, LL_logical_block[iblock].name[ichar])) { + num_violations++; + io_violate_syntax = TRUE; + if ( TRUE == rename_illegal_port) { + LL_logical_block[iblock].name[ichar] = renamed_char; + io_renamed = TRUE; + } + } + } + /* Print a warning if */ + if (TRUE == io_renamed) { + fprintf(fp, "[RENAMING%d] Logical block (Name: %s) is renamed to %s\n", + num_violations, + temp_io_name, LL_logical_block[iblock].name); + } else if (TRUE == io_violate_syntax) { + fprintf(fp, "[RENAMING%d] Logical block name %s violates syntax rules \n", + num_violations, + temp_io_name); + } + /* Free */ + my_free(temp_io_name); + } + + fprintf(fp, "-------Logical block renaming report END ----------\n\n"); + + fprintf(fp, "-------CLB_NET renaming report BEGIN ----------\n"); + /* Change the net name in the clb_net and vpack_net info as well !!! */ + for (inet = 0; inet < LL_num_clb_nets; inet++) { + /* initialize the flag */ + io_renamed = FALSE; + io_violate_syntax = FALSE; + /* Keep a copy of previous name */ + temp_io_name = my_strdup(LL_clb_net[inet].name); + /* Check names character by charcter */ + name_str_len = strlen(LL_clb_net[inet].name); /* exclude the last character: \0, which does require to be checked */ + for (ichar = 0; ichar < name_str_len; ichar++) { + /* Check syntax senstive list, if violates, rename it to be '_' */ + if (TRUE == is_verilog_and_spice_syntax_conflict_char(LL_reserved_syntax_char_head, LL_clb_net[inet].name[ichar])) { + num_violations++; + io_violate_syntax = TRUE; + if ( TRUE == rename_illegal_port) { + LL_clb_net[inet].name[ichar] = renamed_char; + io_renamed = TRUE; + } + } + } + /* Print a warning if */ + if (TRUE == io_renamed) { + fprintf(fp, "[RENAMING%d] clb_net (Name: %s) is renamed to %s\n", + num_violations, + temp_io_name, LL_clb_net[inet].name); + } else if (TRUE == io_violate_syntax) { + fprintf(fp, "[RENAMING%d] clb_net name %s violates syntax rules \n", + num_violations, + temp_io_name); + } + /* Free */ + my_free(temp_io_name); + } + + fprintf(fp, "-------CLB_NET renaming report END ----------\n\n"); + + fprintf(fp, "-------VPACK_NET renaming report BEGIN ----------\n"); + + for (inet = 0; inet < LL_num_vpack_nets; inet++) { + /* initialize the flag */ + io_renamed = FALSE; + io_violate_syntax = FALSE; + /* Keep a copy of previous name */ + temp_io_name = my_strdup(LL_vpack_net[inet].name); + /* Check names character by charcter */ + name_str_len = strlen(LL_vpack_net[inet].name); /* exclude the last character: \0, which does require to be checked */ + for (ichar = 0; ichar < name_str_len; ichar++) { + /* Check syntax senstive list, if violates, rename it to be '_' */ + if (TRUE == is_verilog_and_spice_syntax_conflict_char(LL_reserved_syntax_char_head, LL_vpack_net[inet].name[ichar])) { + num_violations++; + io_violate_syntax = TRUE; + if ( TRUE == rename_illegal_port) { + LL_vpack_net[inet].name[ichar] = renamed_char; + io_renamed = TRUE; + } + } + } + /* Print a warning if */ + if (TRUE == io_renamed) { + fprintf(fp, "[RENAMING%d] vpack_net (Name: %s) is renamed to %s\n", + num_violations, + temp_io_name, LL_vpack_net[inet].name); + } else if (TRUE == io_violate_syntax) { + fprintf(fp, "[RENAMING%d] vpack_net name %s violates syntax rules \n", + num_violations, + temp_io_name); + } + /* Free */ + my_free(temp_io_name); + } + + fprintf(fp, "-------VPACK_NET renaming report END ----------\n"); + + if ((0 < num_violations) && ( FALSE == rename_illegal_port )) { + vpr_printf(TIO_MESSAGE_ERROR, "Detect %d port violate syntax rules while renaming port is disabled\n", num_violations); + exit(1); + } + + /* close fp */ + fclose(fp); + + vpr_printf(TIO_MESSAGE_INFO, "Renaming report is generated in %s\n", + renaming_report_file_path); + + return num_violations; +} + + +static +void spice_net_info_add_density_weight(float signal_density_weight) { + int inet; + + /* a weight of 1. means no change. directly return */ + if ( 1. == signal_density_weight ) { + return; + } + + for (inet = 0; inet < num_logical_nets; inet++) { + assert( NULL != vpack_net[inet].spice_net_info ); + /* By pass PIs since their signal density is usually high */ + if ( TRUE == is_net_pi(&(vpack_net[inet])) ) { + continue; + } + vpack_net[inet].spice_net_info->density *= signal_density_weight; + } + + for (inet = 0; inet < num_nets; inet++) { + assert( NULL != clb_net[inet].spice_net_info ); + /* By pass PIs since their signal density is usually high */ + if ( TRUE == is_net_pi(&(vpack_net[clb_to_vpack_net_mapping[inet]])) ) { + continue; + } + clb_net[inet].spice_net_info->density *= signal_density_weight; + } +} + +void fpga_spice_free(t_arch* Arch) { + /* Free index low and high */ + free_spice_model_grid_index_low_high(Arch->spice->num_spice_model, Arch->spice->spice_models); + free_spice_model_routing_index_low_high(Arch->spice->num_spice_model, Arch->spice->spice_models); +} + +/* Top-level function of FPGA-SPICE setup */ +void fpga_spice_setup(t_vpr_setup vpr_setup, + t_arch* Arch) { + + int num_clocks = 0; + float vpr_crit_path_delay = 0.; + float vpr_clock_freq = 0.; + float vpr_clock_period = 0.; + + + vpr_printf(TIO_MESSAGE_INFO, "\nFPGA-SPICE Tool suites Initilization begins...\n"); + + /* Initialize Arch SPICE MODELS*/ + init_check_arch_spice_models(Arch, &(vpr_setup.RoutingArch)); + + /* Create and initialize a linked list for global ports */ + global_ports_head = init_llist_global_ports(Arch->spice); + vpr_printf(TIO_MESSAGE_INFO, "Detect %d global ports...\n", + find_length_llist(global_ports_head) ); + + /* Build llist for verilog and spice syntax char */ + vpr_printf(TIO_MESSAGE_INFO, "Initialize reserved Verilog and SPICE syntax chars...\n"); + reserved_syntax_char_head = init_llist_verilog_and_spice_syntax_char(); + + /* Initialize verilog netlist to be included */ + /* Add keyword checking */ + check_keywords_conflict(*Arch); + /* TODO: check spice_model names conflict with SPICE or Verilog syntax */ + vpr_printf(TIO_MESSAGE_INFO, "Checking spice_model compatible with syntax chars...\n"); + check_spice_model_name_conflict_syntax_char(*Arch, + reserved_syntax_char_head); + + + /* Check and rename io names to avoid violating SPICE or Verilog syntax */ + check_and_rename_logical_block_and_net_names(reserved_syntax_char_head, + vpr_setup.FileNameOpts.CircuitName, + vpr_setup.FPGA_SPICE_Opts.rename_illegal_port, + num_logical_blocks, logical_block, + num_nets, clb_net, + num_logical_nets, vpack_net); + + /* Check Activity file is valid */ + if (TRUE == vpr_setup.FPGA_SPICE_Opts.read_act_file) { + if (1 == try_access_file(vpr_setup.FileNameOpts.ActFile)) { + vpr_printf(TIO_MESSAGE_ERROR,"Activity file (%s) does not exists! Please provide a valid file path!\n", + vpr_setup.FileNameOpts.ActFile); + exit(1); + } else { + vpr_printf(TIO_MESSAGE_INFO,"Check Activity file (%s) is a valid file path!\n", + vpr_setup.FileNameOpts.ActFile); + } + } + + /* Update global options: + * 1. run_parasitic_net_estimation + * 2. run_testbench_load_extraction + */ + if (TRUE == vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_parasitic_net_estimation_off) { + run_parasitic_net_estimation = FALSE; + } + if (TRUE == vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_testbench_load_extraction_off) { + run_testbench_load_extraction = FALSE; + vpr_printf(TIO_MESSAGE_WARNING, "SPICE testbench load extraction is turned off...Accuracy loss may be expected!\n"); + } + + /* Backannotation for post routing information */ + spice_backannotate_vpr_post_route_info(vpr_setup.RoutingArch, + vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_parasitic_net_estimation_off); + + /* Auto check the density and recommend sim_num_clock_cylce */ + vpr_crit_path_delay = get_critical_path_delay()/1e9; + assert(vpr_crit_path_delay > 0.); + /* if we don't have global clock, clock_freqency should be set to 0.*/ + num_clocks = count_netlist_clocks(); + if (0 == num_clocks) { + /* This could a combinational circuit */ + vpr_clock_freq = 1. / vpr_crit_path_delay; + } else { + assert(1 == num_clocks); + vpr_clock_freq = 1. / vpr_crit_path_delay; + } + Arch->spice->spice_params.stimulate_params.num_clocks = num_clocks; + Arch->spice->spice_params.stimulate_params.vpr_crit_path_delay = vpr_crit_path_delay; + vpr_clock_period = 1./vpr_clock_freq; + auto_select_num_sim_clock_cycle(Arch->spice, vpr_setup.FPGA_SPICE_Opts.sim_window_size); + + /* Determine the clock period */ + if (OPEN == Arch->spice->spice_params.stimulate_params.op_clock_freq) { + /* warning the negative slack ! TODO: move to the general check part??? */ + if (0. > Arch->spice->spice_params.stimulate_params.sim_clock_freq_slack) { + assert(0. < (1 + Arch->spice->spice_params.stimulate_params.sim_clock_freq_slack)); + vpr_printf(TIO_MESSAGE_WARNING, "Slack for clock frequency(=%g) is less than 0! The simulation may fail!\n", + Arch->spice->spice_params.stimulate_params.sim_clock_freq_slack); + } + Arch->spice->spice_params.stimulate_params.op_clock_freq = 1./(vpr_clock_period *(1. + Arch->spice->spice_params.stimulate_params.sim_clock_freq_slack)); + } else { + /* Simulate clock frequency should be larger than 0 !*/ + assert(0. < Arch->spice->spice_params.stimulate_params.op_clock_freq); + } + vpr_printf(TIO_MESSAGE_INFO, "Use Operation Clock freqency %.2f [MHz] in SPICE simulation.\n", + Arch->spice->spice_params.stimulate_params.op_clock_freq / 1e6); + vpr_printf(TIO_MESSAGE_INFO, "Use Programming Clock freqency %.2f [MHz] in SPICE simulation.\n", + Arch->spice->spice_params.stimulate_params.prog_clock_freq / 1e6); + + /* Add weights to spice_net density */ + if (!(0 < vpr_setup.FPGA_SPICE_Opts.signal_density_weight)) { + vpr_printf(TIO_MESSAGE_ERROR, "Signal_density_weight(currently is %.2f) should be a positive number!.\n", + vpr_setup.FPGA_SPICE_Opts.signal_density_weight); + exit(1); + } + if (1 != vpr_setup.FPGA_SPICE_Opts.signal_density_weight) { + vpr_printf(TIO_MESSAGE_INFO, "Add %.2f weight to signal density...\n", + vpr_setup.FPGA_SPICE_Opts.signal_density_weight); + spice_net_info_add_density_weight(vpr_setup.FPGA_SPICE_Opts.signal_density_weight); + } + + return; +} + diff --git a/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_setup.h b/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_setup.h new file mode 100644 index 000000000..2a375c0c5 --- /dev/null +++ b/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_setup.h @@ -0,0 +1,10 @@ + +void init_check_arch_spice_models(t_arch* arch, + t_det_routing_arch* routing_arch); + +void check_keywords_conflict(t_arch Arch); + +void fpga_spice_free(t_arch* Arch); + +void fpga_spice_setup(t_vpr_setup vpr_setup, + t_arch* Arch); diff --git a/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_utils.c b/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_utils.c new file mode 100644 index 000000000..a55c79f4d --- /dev/null +++ b/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_utils.c @@ -0,0 +1,7030 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph_util.h" +#include "rr_graph.h" +#include "rr_graph2.h" +#include "vpr_utils.h" + +/* Include SPICE support headers*/ +#include "quicksort.h" +#include "linkedlist.h" +#include "fpga_spice_globals.h" +#include "spice_globals.h" +#include "fpga_spice_utils.h" + +enum e_dir_err { + E_DIR_NOT_EXIST, + E_EXIST_BUT_NOT_DIR, + E_DIR_EXIST +}; + +/***** Subroutines *****/ +char* my_gettime() { + time_t current_time; + char* c_time_string; + + /* Obtain current time as seconds elapsed since the Epoch*/ + current_time = time(NULL); + + if (current_time == ((time_t)-1)) { + vpr_printf(TIO_MESSAGE_ERROR,"Failure to compute the current time.\n"); + exit(1); + } + + /* Convert to local time format*/ + c_time_string = ctime(¤t_time); + if (NULL == c_time_string) { + vpr_printf(TIO_MESSAGE_ERROR,"Failure to convert the current time.\n"); + exit(1); + } + /* Return it*/ + return c_time_string; +} + +char* format_dir_path(char* dir_path) { + int len = strlen(dir_path); /* String length without the last "\0"*/ + int i; + char* ret = (char*)my_malloc(sizeof(char)*(len+2)); + + strcpy(ret,dir_path); + /* Replace all the "\" to "/"*/ + for (i=0; i -1; i--) { + if (split_token == local_copy[i]) { + split_pos = i; + break; + } + } + + /* Get the path and prog_name*/ + if (-1 == split_pos) { + /* In this case, the prog_path actually contains only the program name*/ + path = NULL; + prog_name = local_copy; + } else if (len == split_pos) { + /* In this case the progrom name is NULL... actually the prog_path is a directory*/ + path = local_copy; + prog_name = NULL; + } else { + /* We have to split it!*/ + local_copy[split_pos] = '\0'; + path = my_strdup(local_copy); + prog_name = my_strdup(local_copy + split_pos + 1); + } + + /*Copy it to the return*/ + (*ret_path) = my_strdup(path); + (*ret_prog_name) = my_strdup(prog_name); + + /* Free useless resources */ + my_free(local_copy); + my_free(path); + my_free(prog_name); + + return 1; +} + +char* chomp_file_name_postfix(char* file_name) { + char* ret = NULL; + char* postfix = NULL; + + split_path_prog_name(file_name, '.', &ret, &postfix); + + my_free(postfix); + + return ret; +} + +/* Print SRAM bits, typically in a comment line */ +void fprint_commented_sram_bits(FILE* fp, + int num_sram_bits, int* sram_bits) { + int i; + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d]) FileHandle is NULL!\n",__FILE__,__LINE__); + exit(1); + } + + for (i = 0; i < num_sram_bits; i++) { + fprintf(fp, "%d", sram_bits[i]); + } + + return; +} + + +/* With a given spice_model_name, find the spice model and return its pointer + * If we find nothing, return NULL + */ +t_spice_model* find_name_matched_spice_model(char* spice_model_name, + int num_spice_model, + t_spice_model* spice_models) { + t_spice_model* ret = NULL; + int imodel; + int num_found = 0; + + for (imodel = 0; imodel < num_spice_model; imodel++) { + if (0 == strcmp(spice_model_name, spice_models[imodel].name)) { + ret = &(spice_models[imodel]); + num_found++; + } + } + + if (0 == num_found) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d])Fail to find a spice model match name: %s !\n", + __FILE__ ,__LINE__, spice_model_name); + exit(1); + } + + assert(1 == num_found); + + return ret; +} + +/* Get the default spice_model*/ +t_spice_model* get_default_spice_model(enum e_spice_model_type default_spice_model_type, + int num_spice_model, + t_spice_model* spice_models) { + t_spice_model* ret = NULL; + int i; + + for (i = 0; i < num_spice_model; i++) { + /* Find a MUX and it is set as default*/ + if ((default_spice_model_type == spice_models[i].type)&&(1 == spice_models[i].is_default)) { + /* Check if we have multiple default*/ + if (NULL != ret) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d])Both SPICE model(%s and %s) are set as default!\n", + __FILE__, __LINE__, ret->name, spice_models[i].name); + exit(1); + } else { + ret = &(spice_models[i]); + } + } + } + + return ret; +} + +/* Tasks: + * 1. Search the inv_spice_model_name of each ports of a spice_model + * 2. Copy the information from inverter spice model to higher level spice_models + */ +void config_spice_model_port_inv_spice_model(int num_spice_models, + t_spice_model* spice_model) { + int i, iport; + t_spice_model* inv_spice_model = NULL; + + for (i = 0; i < num_spice_models; i++) { + /* By pass inverters and buffers */ + if (SPICE_MODEL_INVBUF == spice_model[i].type) { + continue; + } + for (iport = 0; iport < spice_model[i].num_port; iport++) { + /* Now we bypass non BL/WL ports */ + if ((SPICE_MODEL_PORT_BL != spice_model[i].ports[iport].type) + && (SPICE_MODEL_PORT_BLB != spice_model[i].ports[iport].type) + && (SPICE_MODEL_PORT_WL != spice_model[i].ports[iport].type) + && (SPICE_MODEL_PORT_WLB != spice_model[i].ports[iport].type)) { + continue; + } + if (NULL == spice_model[i].ports[iport].inv_spice_model_name) { + inv_spice_model = get_default_spice_model(SPICE_MODEL_INVBUF, + num_spice_models, spice_model); + } else { + inv_spice_model = find_name_matched_spice_model(spice_model[i].ports[iport].inv_spice_model_name, + num_spice_models, spice_model); + /* We should find a buffer spice_model*/ + if (NULL == inv_spice_model) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Fail to find inv_spice_model to the port(name=%s) of spice_model(name=%s)!\n", + __FILE__, __LINE__, spice_model[i].ports[iport].prefix, spice_model[i].name); + exit(1); + } + } + /* Config */ + spice_model[i].ports[iport].inv_spice_model = inv_spice_model; + } + } + return; +} + + + +/* Tasks: + * 1. Search the spice_model_name of input and output buffer and link to the spice_model + * 2. Copy the information from input/output buffer spice model to higher level spice_models + */ +void config_spice_model_input_output_buffers_pass_gate(int num_spice_models, + t_spice_model* spice_model) { + int i; + t_spice_model* buf_spice_model = NULL; + t_spice_model* pgl_spice_model = NULL; + + for (i = 0; i < num_spice_models; i++) { + /* By pass inverters and buffers */ + if (SPICE_MODEL_INVBUF == spice_model[i].type) { + continue; + } + + /* Check if this spice model has input buffers */ + if (1 == spice_model[i].input_buffer->exist) { + buf_spice_model = find_name_matched_spice_model(spice_model[i].input_buffer->spice_model_name, + num_spice_models, spice_model); + /* We should find a buffer spice_model*/ + if (NULL == buf_spice_model) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Fail to find inv/buffer spice_model to the input buffer of spice_model(name=%s)!\n", + __FILE__, __LINE__, spice_model[i].name); + exit(1); + } + /* Copy the information from found spice model to current spice model*/ + memcpy(spice_model[i].input_buffer, buf_spice_model->design_tech_info.buffer_info, sizeof(t_spice_model_buffer)); + /* Recover the spice_model_name and exist */ + spice_model[i].input_buffer->exist = 1; + spice_model[i].input_buffer->spice_model_name = my_strdup(buf_spice_model->name); + spice_model[i].input_buffer->spice_model = buf_spice_model; + } + + /* Check if this spice model has output buffers */ + if (1 == spice_model[i].output_buffer->exist) { + buf_spice_model = find_name_matched_spice_model(spice_model[i].output_buffer->spice_model_name, + num_spice_models, spice_model); + /* We should find a buffer spice_model*/ + if (NULL == buf_spice_model) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Fail to find inv/buffer spice_model to the output buffer of spice_model(name=%s)!\n", + __FILE__, __LINE__, spice_model[i].name); + exit(1); + } + /* Copy the information from found spice model to current spice model*/ + memcpy(spice_model[i].output_buffer, buf_spice_model->design_tech_info.buffer_info, sizeof(t_spice_model_buffer)); + /* Recover the spice_model_name and exist */ + spice_model[i].output_buffer->exist = 1; + spice_model[i].output_buffer->spice_model_name = my_strdup(buf_spice_model->name); + spice_model[i].output_buffer->spice_model = buf_spice_model; + } + + /* If this spice_model is a LUT, check the lut_input_buffer */ + if (SPICE_MODEL_LUT == spice_model[i].type) { + assert(1 == spice_model[i].lut_input_buffer->exist); + + buf_spice_model = find_name_matched_spice_model(spice_model[i].lut_input_buffer->spice_model_name, + num_spice_models, spice_model); + + /* We should find a buffer spice_model*/ + if (NULL == buf_spice_model) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Fail to find inv/buffer spice_model to the lut_input buffer of spice_model(name=%s)!\n", + __FILE__, __LINE__, spice_model[i].name); + exit(1); + } + /* Copy the information from found spice model to current spice model*/ + memcpy(spice_model[i].lut_input_buffer, buf_spice_model->design_tech_info.buffer_info, sizeof(t_spice_model_buffer)); + /* Recover the spice_model_name and exist */ + spice_model[i].lut_input_buffer->exist = 1; + spice_model[i].lut_input_buffer->spice_model_name = my_strdup(buf_spice_model->name); + spice_model[i].lut_input_buffer->spice_model = buf_spice_model; + } + + /* Check pass_gate logic only for LUT and MUX */ + if ((SPICE_MODEL_LUT == spice_model[i].type) + ||(SPICE_MODEL_MUX == spice_model[i].type)) { + pgl_spice_model = find_name_matched_spice_model(spice_model[i].pass_gate_logic->spice_model_name, + num_spice_models, spice_model); + /* We should find a buffer spice_model*/ + if (NULL == pgl_spice_model) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Fail to find pass_gate spice_model to the pass_gate_logic of spice_model(name=%s)!\n", + __FILE__, __LINE__, spice_model[i].name); + exit(1); + } + /* Copy the information from found spice model to current spice model*/ + memcpy(spice_model[i].pass_gate_logic, pgl_spice_model->design_tech_info.pass_gate_info, sizeof(t_spice_model_pass_gate_logic)); + /* Recover the spice_model_name */ + spice_model[i].pass_gate_logic->spice_model_name = my_strdup(pgl_spice_model->name); + spice_model[i].pass_gate_logic->spice_model = pgl_spice_model; + } + } + + return; +} + +/* Return the SPICE model ports wanted + * ATTENTION: we use the pointer of spice model here although we don't modify anything of spice_model + * but we have return input ports, whose pointer will be lost if the input is not the pointor of spice_model + * BECAUSE spice_model will be a local copy if it is not a pointer. And it will be set free when this function + * finishes. So the return pointers become invalid ! + */ +t_spice_model_port** find_spice_model_ports(t_spice_model* spice_model, + enum e_spice_model_port_type port_type, + int* port_num, boolean ignore_global_port) { + int iport, cur; + t_spice_model_port** ret = NULL; + + /* Check codes*/ + assert(NULL != port_num); + assert(NULL != spice_model); + + /* Count the number of ports that match*/ + (*port_num) = 0; + for (iport = 0; iport < spice_model->num_port; iport++) { + /* ignore global port if user specified */ + if ((TRUE == ignore_global_port) + &&(TRUE == spice_model->ports[iport].is_global)) { + continue; + } + if (port_type == spice_model->ports[iport].type) { + (*port_num)++; + } + } + + /* Initial the return pointers*/ + ret = (t_spice_model_port**)my_malloc(sizeof(t_spice_model_port*)*(*port_num)); + memset(ret, 0 , sizeof(t_spice_model_port*)*(*port_num)); + + /* Fill the return pointers*/ + cur = 0; + for (iport = 0; iport < spice_model->num_port; iport++) { + /* ignore global port if user specified */ + if ((TRUE == ignore_global_port) + &&(TRUE == spice_model->ports[iport].is_global)) { + continue; + } + if (port_type == spice_model->ports[iport].type) { + ret[cur] = &(spice_model->ports[iport]); + cur++; + } + } + /* Check correctness*/ + assert(cur == (*port_num)); + + return ret; +} + +/* Find the configure done ports */ +t_spice_model_port** find_spice_model_config_done_ports(t_spice_model* spice_model, + enum e_spice_model_port_type port_type, + int* port_num, boolean ignore_global_port) { + int iport, cur; + t_spice_model_port** ret = NULL; + + /* Check codes*/ + assert(NULL != port_num); + assert(NULL != spice_model); + + /* Count the number of ports that match*/ + (*port_num) = 0; + for (iport = 0; iport < spice_model->num_port; iport++) { + /* ignore global port if user specified */ + if ((TRUE == ignore_global_port) + &&(TRUE == spice_model->ports[iport].is_global)) { + continue; + } + if ((port_type == spice_model->ports[iport].type) + &&(TRUE == spice_model->ports[iport].is_config_enable)) { + (*port_num)++; + } + } + + /* Initial the return pointers*/ + ret = (t_spice_model_port**)my_malloc(sizeof(t_spice_model_port*)*(*port_num)); + memset(ret, 0 , sizeof(t_spice_model_port*)*(*port_num)); + + /* Fill the return pointers*/ + cur = 0; + for (iport = 0; iport < spice_model->num_port; iport++) { + /* ignore global port if user specified */ + if ((TRUE == ignore_global_port) + &&(TRUE == spice_model->ports[iport].is_global)) { + continue; + } + if ((port_type == spice_model->ports[iport].type) + &&(TRUE == spice_model->ports[iport].is_config_enable)) { + ret[cur] = &(spice_model->ports[iport]); + cur++; + } + } + /* Check correctness*/ + assert(cur == (*port_num)); + + return ret; +} + +/* Find the transistor in the tech lib*/ +t_spice_transistor_type* find_mosfet_tech_lib(t_spice_tech_lib tech_lib, + e_spice_trans_type trans_type) { + /* If we did not find return NULL*/ + t_spice_transistor_type* ret = NULL; + int i; + + for (i = 0; i < tech_lib.num_transistor_type; i++) { + if (trans_type == tech_lib.transistor_types[i].type) { + ret = &(tech_lib.transistor_types[i]); + break; + } + } + + return ret; +} + +/* Convert a integer to a string*/ +char* my_itoa(int input) { + char* ret = NULL; + int sign = 0; + int len = 0; + int temp = input; + int cur; + char end_of_str; + + /* Identify input number is positive or negative*/ + if (input < 0) { + sign = 1; /* sign will be '-'*/ + len = 1; + temp = 0 - input; + } else if (0 == input) { + sign = 0; + len = 2; + /* Alloc*/ + ret = (char*)my_malloc(sizeof(char)*len); + /* Lets get the end_of_str, the char is dependent on OS*/ + sprintf(ret,"%s","0"); + return ret; + } + /* Identify the length of string*/ + while(temp > 0) { + len++; + temp = temp/10; + } + /* Total length of string should include '\0' at the end*/ + len = len + 1; + /* Alloc*/ + ret = (char*)my_malloc(sizeof(char)*len); + + /*Fill it*/ + temp = input; + /* Lets get the end_of_str, the char is dependent on OS*/ + sprintf(ret,"%s","-"); + end_of_str = ret[1]; + ret[len-1] = end_of_str; + cur = len - 2; + /* Print the number reversely*/ + while(temp > 0) { + ret[cur] = temp%10 + '0'; /* ASIC II base is '0'*/ + cur--; + temp = temp/10; + } + /* Print the sign*/ + if (1 == sign) { + assert(0 == cur); + ret[cur] = '-'; + temp = 0 - input; + } else { + assert(-1 == cur); + } + + return ret; +} + +/* With given spice_model_port, find the pb_type port with same name and type*/ +t_port* find_pb_type_port_match_spice_model_port(t_pb_type* pb_type, + t_spice_model_port* spice_model_port) { + int iport; + t_port* ret = NULL; + + /* Search ports */ + for (iport = 0; iport < pb_type->num_ports; iport++) { + /* Match the name and port size*/ + if ((0 == strcmp(pb_type->ports[iport].name, spice_model_port->prefix)) + &&(pb_type->ports[iport].num_pins == spice_model_port->size)) { + /* Match the type*/ + switch (spice_model_port->type) { + case SPICE_MODEL_PORT_INPUT: + if ((IN_PORT == pb_type->ports[iport].type) + &&(0 == pb_type->ports[iport].is_clock)) { + if (NULL != ret) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s, [LINE%d])More than 1 pb_type(%s) port match spice_model_port(%s)!\n", + __FILE__, __LINE__, pb_type->name, spice_model_port->prefix); + exit(1); + } + ret = &(pb_type->ports[iport]); + } + break; + case SPICE_MODEL_PORT_OUTPUT: + if (OUT_PORT == pb_type->ports[iport].type) { + if (NULL != ret) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s, [LINE%d])More than 1 pb_type(%s) port match spice_model_port(%s)!\n", + __FILE__, __LINE__, pb_type->name, spice_model_port->prefix); + exit(1); + } + ret = &(pb_type->ports[iport]); + } + break; + case SPICE_MODEL_PORT_CLOCK: + if ((IN_PORT == pb_type->ports[iport].type)&&(1 == pb_type->ports[iport].is_clock)) { + if (NULL != ret) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s, [LINE%d])More than 1 pb_type(%s) port match spice_model_port(%s)!\n", + __FILE__, __LINE__, pb_type->name, spice_model_port->prefix); + exit(1); + } + ret = &(pb_type->ports[iport]); + } + break; + case SPICE_MODEL_PORT_INOUT : + if ((INOUT_PORT == pb_type->ports[iport].type)&&(0 == pb_type->ports[iport].is_clock)) { + if (NULL != ret) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s, [LINE%d])More than 1 pb_type(%s) port match spice_model_port(%s)!\n", + __FILE__, __LINE__, pb_type->name, spice_model_port->prefix); + exit(1); + } + ret = &(pb_type->ports[iport]); + } + break; + case SPICE_MODEL_PORT_SRAM: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s, [LINE%d])Invalid type for spice_model_port(%s)!\n", + __FILE__, __LINE__, spice_model_port->prefix); + exit(1); + } + } + } + + return ret; +} + +char* chomp_spice_node_prefix(char* spice_node_prefix) { + int len = 0; + char* ret = NULL; + + if (NULL == spice_node_prefix) { + return NULL; + } + + len = strlen(spice_node_prefix); /* String length without the last "\0"*/ + ret = (char*)my_malloc(sizeof(char)*(len+2)); + + /* Don't do anything when input is NULL*/ + if (NULL == spice_node_prefix) { + my_free(ret); + return NULL; + } + + strcpy(ret,spice_node_prefix); + /* If the path end up with "_" we should remove it*/ + if ('_' == ret[len-1]) { + ret[len-1] = ret[len]; + } + + return ret; +} + +char* format_spice_node_prefix(char* spice_node_prefix) { + int len = strlen(spice_node_prefix); /* String length without the last "\0"*/ + char* ret = (char*)my_malloc(sizeof(char)*(len+2)); + + /* Don't do anything when input is NULL*/ + if (NULL == spice_node_prefix) { + my_free(ret); + return NULL; + } + + strcpy(ret,spice_node_prefix); + /* If the path does not end up with "_" we should complete it*/ + if (ret[len-1] != '_') { + strcat(ret, "_"); + } + return ret; +} + +t_port** find_pb_type_ports_match_spice_model_port_type(t_pb_type* pb_type, + enum e_spice_model_port_type port_type, + int* port_num) { + int iport, cur; + t_port** ret = NULL; + + /* Check codes*/ + assert(NULL != port_num); + assert(NULL != pb_type); + + /* Count the number of ports that match*/ + (*port_num) = 0; + for (iport = 0; iport < pb_type->num_ports; iport++) { + switch (port_type) { + case SPICE_MODEL_PORT_INPUT: /* TODO: support is_non_clock_global*/ + if ((IN_PORT == pb_type->ports[iport].type) + &&(0 == pb_type->ports[iport].is_clock)) { + (*port_num)++; + } + break; + case SPICE_MODEL_PORT_OUTPUT: + if ((OUT_PORT == pb_type->ports[iport].type) + &&(0 == pb_type->ports[iport].is_clock)) { + (*port_num)++; + } + break; + case SPICE_MODEL_PORT_INOUT: + if ((INOUT_PORT == pb_type->ports[iport].type) + &&(0 == pb_type->ports[iport].is_clock)) { + (*port_num)++; + } + break; + case SPICE_MODEL_PORT_CLOCK: + if ((IN_PORT == pb_type->ports[iport].type) + &&(1 == pb_type->ports[iport].is_clock)) { + (*port_num)++; + } + break; + case SPICE_MODEL_PORT_SRAM: + /* Original VPR don't support this*/ + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s, [LINE%d])Invalid type for port!\n", + __FILE__, __LINE__); + exit(1); + } + } + + /* Initial the return pointers*/ + ret = (t_port**)my_malloc(sizeof(t_port*)*(*port_num)); + memset(ret, 0 , sizeof(t_port*)*(*port_num)); + + /* Fill the return pointers*/ + cur = 0; + + for (iport = 0; iport < pb_type->num_ports; iport++) { + switch (port_type) { + case SPICE_MODEL_PORT_INPUT : /* TODO: support is_non_clock_global*/ + if ((IN_PORT == pb_type->ports[iport].type) + &&(0 == pb_type->ports[iport].is_clock)) { + ret[cur] = &(pb_type->ports[iport]); + cur++; + } + break; + case SPICE_MODEL_PORT_OUTPUT: + if ((OUT_PORT == pb_type->ports[iport].type) + &&(0 == pb_type->ports[iport].is_clock)) { + ret[cur] = &(pb_type->ports[iport]); + cur++; + } + break; + case SPICE_MODEL_PORT_INOUT: + if ((INOUT_PORT == pb_type->ports[iport].type) + &&(0 == pb_type->ports[iport].is_clock)) { + ret[cur] = &(pb_type->ports[iport]); + cur++; + } + break; + case SPICE_MODEL_PORT_CLOCK: + if ((IN_PORT == pb_type->ports[iport].type) + &&(1 == pb_type->ports[iport].is_clock)) { + ret[cur] = &(pb_type->ports[iport]); + cur++; + } + break; + case SPICE_MODEL_PORT_SRAM: + /* Original VPR don't support this*/ + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s, [LINE%d])Invalid type for port!\n", + __FILE__, __LINE__); + exit(1); + } + } + + /* Check correctness*/ + assert(cur == (*port_num)); + + return ret; +} + +/* Given the co-ordinators of grid, + * Find if there is a block mapped into this grid + */ +t_block* search_mapped_block(int x, int y, int z) { + t_block* ret = NULL; + int iblk = 0; + + /*Valid pointors*/ + assert(NULL != grid); + assert((0 < x)||(0 == x)); + assert((x < (nx + 1))||(x == (nx + 1))); + assert((0 < y)||(0 == y)); + assert((x < (ny + 1))||(x == (ny + 1))); + + /* Search all blocks*/ + for (iblk = 0; iblk < num_blocks; iblk++) { + if ((x == block[iblk].x)&&(y == block[iblk].y)&&(z == block[iblk].z)) { + /* Matched cordinators*/ + ret = &(block[iblk]); + /* Check */ + assert(block[iblk].type == grid[x][y].type); + assert(z < grid[x][y].type->capacity); + assert(0 < grid[x][y].usage); + } + } + + return ret; +} + + + + +/* Change the decimal number to binary + * and return a array of integer*/ +int* my_decimal2binary(int decimal, + int* binary_len) { + int* ret = NULL; + int i = 0; + int code = decimal; + + (*binary_len) = 0; + + while (0 < code) { + (*binary_len)++; + code = code/2; + } + + i = (*binary_len) - 1; + while (0 < code) { + ret[i] = code%2; + i--; + code = code/2; + } + + return ret; +} + +/* Determine the number of SRAM bit for a basis subckt of a multiplexer + * In general, the number of SRAM bits should be same as the number of inputs per level + * with one exception: + * When multiplexing structure is tree-like, there should be only 1 SRAM bit + */ +int determine_num_sram_bits_mux_basis_subckt(t_spice_model* mux_spice_model, + int mux_size, + int num_input_per_level, + boolean special_basis) { + int num_sram_bits; + + /* General cases */ + switch (mux_spice_model->design_tech_info.structure) { + case SPICE_MODEL_STRUCTURE_TREE: + num_sram_bits = 1; + break; + case SPICE_MODEL_STRUCTURE_ONELEVEL: + case SPICE_MODEL_STRUCTURE_MULTILEVEL: + num_sram_bits = num_input_per_level; + if ((2 == num_sram_bits)&&(2 == mux_size)) { + num_sram_bits = 1; + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n", + __FILE__, __LINE__, mux_spice_model->name); + exit(1); + } + + /* For special cases: overide the results */ + if (TRUE == special_basis) { + num_sram_bits = num_input_per_level; + } + + return num_sram_bits; +} + +/* Determine the level of multiplexer + */ +int determine_tree_mux_level(int mux_size) { + int level = 0; + + /* Do log2(mux_size), have a basic number*/ + level = (int)(log((double)mux_size)/log(2.)); + /* Fix the error, i.e. mux_size=5, level = 2, we have to complete */ + while (mux_size > pow(2.,(double)level)) { + level++; + } + + return level; +} + +int determine_num_input_basis_multilevel_mux(int mux_size, + int mux_level) { + int num_input_per_unit = 2; + + /* Special Case: mux_size = 2 */ + if (2 == mux_size) { + return mux_size; + } + + if (1 == mux_level) { + return mux_size; + } + + if (2 == mux_level) { + num_input_per_unit = (int)sqrt(mux_size); + while (num_input_per_unit*num_input_per_unit < mux_size) { + num_input_per_unit++; + } + return num_input_per_unit; + } + + assert(2 < mux_level); + + + while(pow((double)num_input_per_unit, (double)mux_level) < mux_size) { + num_input_per_unit++; + } + + if (num_input_per_unit < 2) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Number of inputs of each basis should be at least 2!\n", + __FILE__, __LINE__); + exit(1); + } + + return num_input_per_unit; +} + +/*Determine the number inputs required at the last level*/ +int tree_mux_last_level_input_num(int num_level, + int mux_size) { + int ret = 0; + + ret = (int)(pow(2., (double)num_level)) - mux_size; + + if (0 < ret) { + ret = (int)(2.*(mux_size - pow(2., (double)(num_level-1)))); + } else if (0 > ret) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])num_level(%d) is wrong with mux_size(%d)!\n", + __FILE__, __LINE__, num_level, mux_size); + exit(1); + } else { + ret = mux_size; + } + + return ret; +} + +int multilevel_mux_last_level_input_num(int num_level, int num_input_per_unit, + int mux_size) { + int ret = 0; + int num_basis_last_level = (int)(mux_size/num_input_per_unit); + int num_potential_special_inputs = 0; + int num_special_basis = 0; + int num_input_special_basis = 0; + + ret = mux_size - num_basis_last_level * num_input_per_unit; + assert((0 == ret)||(0 < ret)); + + /* Special Case: mux_size = 2 */ + if (2 == mux_size) { + return mux_size; + } + + if (0 < ret) { + /* Check if we need a special basis at last level, + * differ : the number of input of the last-2 level will be used + */ + num_potential_special_inputs = (num_basis_last_level + ret) - pow((double)(num_input_per_unit), (double)(num_level-1)); + /* should be smaller than the num_input_per_unit */ + assert((!(0 > num_potential_special_inputs))&&(num_potential_special_inputs < num_input_per_unit)); + /* We need a speical basis */ + num_special_basis = pow((double)(num_input_per_unit), (double)(num_level-1)) - num_basis_last_level; + if (ret == num_special_basis) { + num_input_special_basis = 0; + } else if (1 == num_special_basis) { + num_input_special_basis = ret; + } else { + assert ( 1 < num_special_basis ); + num_input_special_basis = ret - 1; + } + ret = num_input_special_basis + num_basis_last_level * num_input_per_unit; + } else { + ret = mux_size; + } + + return ret; +} + +int determine_lut_path_id(int lut_size, + int* lut_inputs) { + int path_id = 0; + int i; + + for (i = 0; i < lut_size; i++) { + switch (lut_inputs[i]) { + case 0: + path_id += (int)pow(2., (double)(i)); + break; + case 1: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid sram_bits[%d]!\n", + __FILE__, __LINE__, i); + exit(1); + } + } + + return path_id; +} + +/* Decoding a one-level MUX: + * SPICE/Verilog model declare the sram port sequence as follows: + * sel0, sel1, ... , selN, + * which control the pass-gate logic connected to + * in0, in1, ... , inN + * When decode the SRAM bits, we initialize every bits to zero + * And then set the sel signal corresponding to the input to be 1. + * TODO: previously the decoding is not correct, need to check any bug in SPICE part + */ +int* decode_onelevel_mux_sram_bits(int fan_in, + int mux_level, + int path_id) { + int* ret = (int*)my_malloc(sizeof(int)*fan_in); + int i; + + /* Check */ + assert( (!(0 > path_id)) && (path_id < fan_in) ); + + for (i = 0; i < fan_in; i++) { + ret[i] = 0; + } + ret[path_id] = 1; + /* ret[fan_in - 1 - path_id] = 1; */ + return ret; +} + +int* decode_multilevel_mux_sram_bits(int fan_in, + int mux_level, + int path_id) { + int* ret = NULL; + int i, j, path_differ, temp; + int num_last_level_input, active_mux_level, active_path_id, num_input_basis; + + /* Check */ + assert((0 == path_id)||(0 < path_id)); + assert(path_id < fan_in); + + /* TODO: determine the number of input of basis */ + switch (mux_level) { + case 1: + /* Special: 1-level should be have special care !!! */ + return decode_onelevel_mux_sram_bits(fan_in, mux_level, path_id); + default: + assert(1 < mux_level); + num_input_basis = determine_num_input_basis_multilevel_mux(fan_in, mux_level); + break; + } + + ret = (int*)my_malloc(sizeof(int)*(num_input_basis * mux_level)); + + /* Determine last level input */ + num_last_level_input = multilevel_mux_last_level_input_num(mux_level, num_input_basis, fan_in); + + /* Initialize */ + for (i = 0; i < (num_input_basis*mux_level); i++) { + ret[i] = 0; + } + + /* When last level input number is less than the 2**mux_level, + * There are some input at the level: (mux_level-1) + */ + active_mux_level = mux_level; + active_path_id = path_id; + if (num_last_level_input < fan_in) { + if (path_id > num_last_level_input) { + active_mux_level = mux_level - 1; + active_path_id = (int)pow((double)num_input_basis,(double)(active_mux_level)) - (fan_in - path_id); + } + } else { + assert(num_last_level_input == fan_in); + } + + temp = active_path_id; + for (i = mux_level - 1; i > (mux_level - active_mux_level - 1); i--) { + for (j = 0; j < num_input_basis; j++) { + path_differ = (j + 1) * (int)pow((double)num_input_basis,(double)(i+active_mux_level-mux_level)); + if (temp < path_differ) { + /* This is orignal one for SPICE, but not work for VerilogGen + * I comment it here + ret[i*num_input_basis + j] = 1; + */ + ret[(mux_level - 1 - i)*num_input_basis + j] = 1; + /* Reduce the min. start index of this basis */ + temp -= j * (int)pow((double)num_input_basis,(double)(i+active_mux_level-mux_level)); + break; /* Touch the boundry, stop and move onto the next level */ + } + } + } + + /* Check */ + assert(0 == temp); + + return ret; +} + +/* Decode the configuration to sram_bits + * A path_id is in the range of [0..fan_in-1] + * sram + * input0 -----| + * |----- output + * input1 -----| + * Here, we assume (fix) the mux2to1 pass input0 when sram = 1 (vdd), and pass input1 when sram = 0(gnd) + * To generate the sram bits, we can determine the in each level of MUX, + * the path id is on the upper path(sram = 1) or the lower path (sram = 0), by path_id > 2**mux_level + */ +int* decode_tree_mux_sram_bits(int fan_in, + int mux_level, + int path_id) { + int* ret = (int*)my_malloc(sizeof(int)*mux_level); + int i = 0; + int path_differ = 0; + int temp = 0; + int num_last_level_input = 0; + int active_mux_level = 0; + int active_path_id = 0; + + /* Check */ + assert((0 == path_id)||(0 < path_id)); + assert(path_id < fan_in); + + /* Determine last level input */ + num_last_level_input = tree_mux_last_level_input_num(mux_level, fan_in); + + /* Initialize */ + for (i = 0; i < mux_level; i++) { + ret[i] = 0; + } + + /* When last level input number is less than the 2**mux_level, + * There are some input at the level: (mux_level-1) + */ + active_mux_level = mux_level; + active_path_id = path_id; + if (num_last_level_input < fan_in) { + if (path_id > num_last_level_input) { + active_mux_level = mux_level - 1; + active_path_id = (int)pow(2.,(double)(active_mux_level)) - (fan_in - path_id); + } + } else { + assert(num_last_level_input == fan_in); + } + + temp = active_path_id; + for (i = mux_level - 1; i > (mux_level - active_mux_level - 1); i--) { + path_differ = (int)pow(2.,(double)(i+active_mux_level-mux_level)); + if (temp < path_differ) { + ret[i] = 1; + } else { + temp = temp - path_differ; + ret[i] = 0; + } + } + + /* Check */ + assert(0 == temp); + + return ret; +} + +void decode_cmos_mux_sram_bits(t_spice_model* mux_spice_model, + int mux_size, int path_id, + int* bit_len, int** conf_bits, int* mux_level) { + /* Check */ + assert(NULL != mux_level); + assert(NULL != bit_len); + assert(NULL != conf_bits); + assert((-1 < path_id)&&(path_id < mux_size)); + assert(SPICE_MODEL_MUX == mux_spice_model->type); + assert(SPICE_MODEL_DESIGN_CMOS == mux_spice_model->design_tech); + + /* Initialization */ + (*bit_len) = 0; + (*conf_bits) = NULL; + + /* Special for MUX-2: whatever structure it is, it has always one-level and one configuration bit */ + if (2 == mux_size) { + (*bit_len) = 1; + (*mux_level) = 1; + (*conf_bits) = decode_tree_mux_sram_bits(mux_size, (*mux_level), path_id); + return; + } + /* Other general cases */ + switch (mux_spice_model->design_tech_info.structure) { + case SPICE_MODEL_STRUCTURE_TREE: + (*mux_level) = determine_tree_mux_level(mux_size); + (*bit_len) = (*mux_level); + (*conf_bits) = decode_tree_mux_sram_bits(mux_size, (*mux_level), path_id); + break; + case SPICE_MODEL_STRUCTURE_ONELEVEL: + (*mux_level) = 1; + (*bit_len) = mux_size; + (*conf_bits) = decode_onelevel_mux_sram_bits(mux_size, (*mux_level), path_id); + break; + case SPICE_MODEL_STRUCTURE_MULTILEVEL: + (*mux_level) = mux_spice_model->design_tech_info.mux_num_level; + (*bit_len) = determine_num_input_basis_multilevel_mux(mux_size, (*mux_level)) * (*mux_level); + (*conf_bits) = decode_multilevel_mux_sram_bits(mux_size, (*mux_level), path_id); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for mux_spice_model (%s)!\n", + __FILE__, __LINE__, mux_spice_model->name); + exit(1); + } + return; +} + + +/** + * Split a string with strtok + * Store each token in a char array + * tokens (char**): + * tokens[i] (char*) : pointer to a string split by delims + */ + +char** my_strtok(char* str, + char* delims, + int* len) +{ + char** ret; + char* result; + int cnt=0; + int* lens; + char* tmp; + + if (NULL == str) + { + printf("Warning: NULL string found in my_strtok!\n"); + return NULL; + } + + tmp = my_strdup(str); + result = strtok(tmp,delims); + /*First scan to determine the size*/ + while(result != NULL) + { + cnt++; + /* strtok split until its buffer is NULL*/ + result = strtok(NULL,delims); + } + //printf("1st scan cnt=%d\n",cnt); + /* Allocate memory*/ + ret = (char**)my_malloc(cnt*sizeof(char*)); + lens = (int*)my_malloc(cnt*sizeof(int)); + /*Second to determine the size of each char*/ + cnt = 0; + memcpy(tmp,str,strlen(str)+1); + result = strtok(tmp,delims); + while(result != NULL) + { + lens[cnt] = strlen(result)+1; + //printf("lens[%d]=%d .",cnt,lens[cnt]); + cnt++; + /* strtok split until its buffer is NULL*/ + result = strtok(NULL,delims); + } + //printf("\n"); + /*Third to allocate and copy each char*/ + cnt = 0; + memcpy(tmp,str,strlen(str)+1); + result = strtok(tmp,delims); + while(result != NULL) + { + //printf("results[%d] = %s ",cnt,result); + ret[cnt] = my_strdup(result); + cnt++; + /* strtok split until its buffer is NULL*/ + result = strtok(NULL,delims); + } + //printf("\n"); + + (*len) = cnt; + + free(tmp); + + return ret; +} + +char* convert_side_index_to_string(int side) { + switch (side) { + case 0: + return "top"; + case 1: + return "right"; + case 2: + return "bottom"; + case 3: + return "left"; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid side index. Should be [0,3].\n", + __FILE__, __LINE__); + exit(1); + } +} + +char* convert_chan_type_to_string(t_rr_type chan_type) { + switch(chan_type) { + case CHANX: + return "chanx"; + break; + case CHANY: + return "chany"; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); + exit(1); + } +} + +char* convert_chan_rr_node_direction_to_string(enum PORTS chan_rr_node_direction) { + switch(chan_rr_node_direction) { + case IN_PORT: + return "in"; + break; + case OUT_PORT: + return "out"; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of port!\n", __FILE__, __LINE__); + exit(1); + } +} + +void init_spice_net_info(t_spice_net_info* spice_net_info) { + if (NULL == spice_net_info) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid spice_net_info!\n", __FILE__, __LINE__); + exit(1); + } + + spice_net_info->density = 0.; + spice_net_info->freq = 0.; + + assert((1 == default_signal_init_value)||(0 == default_signal_init_value)); + spice_net_info->init_val = default_signal_init_value; + spice_net_info->probability = (float)default_signal_init_value; + + spice_net_info->pwl = 0.; + spice_net_info->pwh = 0.; + spice_net_info->slew_rise = 0.; + + return; +} + +t_spice_model* find_iopad_spice_model(int num_spice_model, + t_spice_model* spice_models) { + t_spice_model* ret = NULL; + int imodel; + int num_found = 0; + + for (imodel = 0; imodel < num_spice_model; imodel++) { + if (SPICE_MODEL_IOPAD == spice_models[imodel].type) { + ret = &(spice_models[imodel]); + num_found++; + } + } + + assert(1 == num_found); + + return ret; +} + + +char* generate_string_spice_model_type(enum e_spice_model_type spice_model_type) { + char* ret = NULL; + + switch (spice_model_type) { + case SPICE_MODEL_WIRE: + ret = "wire"; + break; + case SPICE_MODEL_MUX: + ret = "Multiplexer"; + break; + case SPICE_MODEL_LUT: + ret = "Look-Up Table"; + break; + case SPICE_MODEL_FF: + ret = "Flip-flop"; + break; + case SPICE_MODEL_SRAM: + ret = "SRAM"; + break; + case SPICE_MODEL_HARDLOGIC: + ret = "hard_logic"; + break; + case SPICE_MODEL_IOPAD: + ret = "iopad"; + break; + case SPICE_MODEL_SCFF: + ret = "Scan-chain Flip-flop"; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid spice_model_type!\n", __FILE__, __LINE__); + exit(1); + } + + return ret; +} + +/* Deteremine the side of a io grid */ +int determine_io_grid_side(int x, + int y) { + /* TOP side IO of FPGA */ + if ((ny + 1) == y) { + /* Make sure a valid x, y */ + assert((!(0 > x))&&(x < (nx + 1))); + return BOTTOM; /* Such I/O has only Bottom side pins */ + } else if ((nx + 1) == x) { /* RIGHT side IO of FPGA */ + /* Make sure a valid x, y */ + assert((!(0 > y))&&(y < (ny + 1))); + return LEFT; /* Such I/O has only Left side pins */ + } else if (0 == y) { /* BOTTOM side IO of FPGA */ + /* Make sure a valid x, y */ + assert((!(0 > x))&&(x < (nx + 1))); + return TOP; /* Such I/O has only Top side pins */ + } else if (0 == x) { /* LEFT side IO of FPGA */ + /* Make sure a valid x, y */ + assert((!(0 > y))&&(y < (ny + 1))); + return RIGHT; /* Such I/O has only Right side pins */ + } else { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])I/O Grid is in the center part of FPGA! Currently unsupported!\n", + __FILE__, __LINE__); + exit(1); + } +} + +void find_prev_rr_nodes_with_src(t_rr_node* src_rr_node, + int* num_drive_rr_nodes, + t_rr_node*** drive_rr_nodes, + int** switch_indices) { + int inode, iedge, next_node; + int cur_index, switch_index; + + assert(NULL != src_rr_node); + assert(NULL != num_drive_rr_nodes); + assert(NULL != switch_indices); + + (*num_drive_rr_nodes) = 0; + (*drive_rr_nodes) = NULL; + (*switch_indices) = NULL; + + switch_index = -1; + /* Determine num_drive_rr_node */ + for (inode = 0; inode < num_rr_nodes; inode++) { + for (iedge = 0; iedge < rr_node[inode].num_edges; iedge++) { + next_node = rr_node[inode].edges[iedge]; + if (src_rr_node == &(rr_node[next_node])) { + /* Get the spice_model */ + if (-1 == switch_index) { + switch_index = rr_node[inode].switches[iedge]; + } else { /* Make sure the switches are the same*/ + assert(switch_index == rr_node[inode].switches[iedge]); + } + (*num_drive_rr_nodes)++; + } + } + } + /* Malloc */ + (*drive_rr_nodes) = (t_rr_node**)my_malloc(sizeof(t_rr_node*)*(*num_drive_rr_nodes)); + (*switch_indices) = (int*)my_malloc(sizeof(int)*(*num_drive_rr_nodes)); + + /* Find all the rr_nodes that drive current_rr_node*/ + cur_index = 0; + for (inode = 0; inode < num_rr_nodes; inode++) { + for (iedge = 0; iedge < rr_node[inode].num_edges; iedge++) { + next_node = rr_node[inode].edges[iedge]; + if (src_rr_node == &(rr_node[next_node])) { + /* Update drive_rr_nodes list */ + (*drive_rr_nodes)[cur_index] = &(rr_node[inode]); + (*switch_indices)[cur_index] = rr_node[inode].switches[iedge]; + cur_index++; + } + } + } + assert(cur_index == (*num_drive_rr_nodes)); + + return; +} + + +int find_path_id_prev_rr_node(int num_drive_rr_nodes, + t_rr_node** drive_rr_nodes, + t_rr_node* src_rr_node) { + int path_id, inode; + + /* Configuration bits for this MUX*/ + path_id = -1; + for (inode = 0; inode < num_drive_rr_nodes; inode++) { + if (drive_rr_nodes[inode] == &(rr_node[src_rr_node->prev_node])) { + path_id = inode; + break; + } + } + assert((-1 != path_id)&&(path_id < src_rr_node->fan_in)); + + return path_id; +} + +int pb_pin_net_num(t_rr_node* pb_rr_graph, + t_pb_graph_pin* pin) { + int net_num = OPEN; + + if (NULL == pb_rr_graph) { + /* Try the temp_net_num in pb_graph_pin */ + net_num = pin->temp_net_num; + } else { + net_num = pb_rr_graph[pin->pin_count_in_cluster].net_num; + } + + return net_num; +} + +float pb_pin_density(t_rr_node* pb_rr_graph, + t_pb_graph_pin* pin) { + float density = 0.; + int net_num; + + if (NULL == pb_rr_graph) { + /* Try the temp_net_num in pb_graph_pin */ + net_num = pin->temp_net_num; + if (OPEN != net_num) { + density = vpack_net[net_num].spice_net_info->density; + } + return density; + } + net_num = pb_rr_graph[pin->pin_count_in_cluster].net_num; + + if (OPEN != net_num) { + density = vpack_net[net_num].spice_net_info->density; + } + + return density; +} + +float pb_pin_probability(t_rr_node* pb_rr_graph, + t_pb_graph_pin* pin) { + float probability = (float)(default_signal_init_value); + int net_num; + + if (NULL == pb_rr_graph) { + /* Try the temp_net_num in pb_graph_pin */ + net_num = pin->temp_net_num; + if (OPEN != net_num) { + probability = vpack_net[net_num].spice_net_info->probability; + } + return probability; + } + net_num = pb_rr_graph[pin->pin_count_in_cluster].net_num; + + if (OPEN != net_num) { + probability = vpack_net[net_num].spice_net_info->probability; + } + + return probability; +} + +int pb_pin_init_value(t_rr_node* pb_rr_graph, + t_pb_graph_pin* pin) { + float init_val = (float)(default_signal_init_value); + int net_num; + + if (NULL == pb_rr_graph) { + /* TODO: we know initialize to vdd could reduce the leakage power od multiplexers! + * But I can this as an option ! + */ + /* Try the temp_net_num in pb_graph_pin */ + net_num = pin->temp_net_num; + if (OPEN != net_num) { + init_val = vpack_net[net_num].spice_net_info->init_val; + } + return init_val; + } + net_num = pb_rr_graph[pin->pin_count_in_cluster].net_num; + + if (OPEN != net_num) { + init_val = vpack_net[net_num].spice_net_info->init_val; + } + + return init_val; +} + +float get_rr_node_net_density(t_rr_node node) { + /* If we found this net is OPEN, we assume it zero-density */ + if (OPEN == node.vpack_net_num) { + return 0.; + } else { + return vpack_net[node.vpack_net_num].spice_net_info->density; + } +} + +float get_rr_node_net_probability(t_rr_node node) { + /* If we found this net is OPEN, we assume it zero-probability */ + if (OPEN == node.vpack_net_num) { + /* TODO: we know initialize to vdd could reduce the leakage power od multiplexers! + * But I can this as an option ! + */ + return (float)(default_signal_init_value); + } else { + return vpack_net[node.vpack_net_num].spice_net_info->probability; + } +} + +int get_rr_node_net_init_value(t_rr_node node) { + /* If we found this net is OPEN, we assume it zero-probability */ + if (OPEN == node.vpack_net_num) { + /* TODO: we know initialize to vdd could reduce the leakage power od multiplexers! + * But I can this as an option ! + */ + return (float)(default_signal_init_value); + } else { + return vpack_net[node.vpack_net_num].spice_net_info->init_val; + } +} + +int find_parent_pb_type_child_index(t_pb_type* parent_pb_type, + int mode_index, + t_pb_type* child_pb_type) { + int i; + + assert(NULL != parent_pb_type); + assert(NULL != child_pb_type); + assert((!(0 > mode_index))&&(mode_index < parent_pb_type->num_modes)); + + for (i = 0; i < parent_pb_type->modes[mode_index].num_pb_type_children; i++) { + if (child_pb_type == &(parent_pb_type->modes[mode_index].pb_type_children[i])) { + assert(0 == strcmp(child_pb_type->name, parent_pb_type->modes[mode_index].pb_type_children[i].name)); + return i; + } + } + + return -1; +} + +/* Rule in generating a unique name: + * name of current pb = _[index] + */ +void gen_spice_name_tag_pb_rec(t_pb* cur_pb, + char* prefix) { + char* prefix_rec = NULL; + int ipb, jpb, mode_index; + + mode_index = cur_pb->mode; + + /* Free previous name_tag if there is */ + /* my_free(cur_pb->spice_name_tag); */ + + /* Generate the name_tag */ + if ((0 < cur_pb->pb_graph_node->pb_type->num_modes) + &&(NULL == cur_pb->pb_graph_node->pb_type->spice_model_name)) { + prefix_rec = (char*)my_malloc(sizeof(char)*(strlen(prefix) + 1 + strlen(cur_pb->pb_graph_node->pb_type->name) + 1 + + strlen(my_itoa(cur_pb->pb_graph_node->placement_index)) + 7 + strlen(cur_pb->pb_graph_node->pb_type->modes[mode_index].name) + 2 )); + sprintf(prefix_rec, "%s_%s[%d]_mode[%s]", + prefix, cur_pb->pb_graph_node->pb_type->name, cur_pb->pb_graph_node->placement_index, cur_pb->pb_graph_node->pb_type->modes[mode_index].name); + cur_pb->spice_name_tag = my_strdup(prefix_rec); + } else { + assert((0 == cur_pb->pb_graph_node->pb_type->num_modes) + ||(NULL != cur_pb->pb_graph_node->pb_type->spice_model_name)); + prefix_rec = (char*)my_malloc(sizeof(char)*(strlen(prefix) + 1 + strlen(cur_pb->pb_graph_node->pb_type->name) + 1 + + strlen(my_itoa(cur_pb->pb_graph_node->placement_index)) + 2 )); + sprintf(prefix_rec, "%s_%s[%d]", + prefix, cur_pb->pb_graph_node->pb_type->name, cur_pb->pb_graph_node->placement_index); + cur_pb->spice_name_tag = my_strdup(prefix_rec); + } + + /* When reach the leaf, we directly return */ + /* Recursive until reach the leaf */ + if ((0 == cur_pb->pb_graph_node->pb_type->num_modes) + ||(NULL == cur_pb->child_pbs)) { + return; + } + for (ipb = 0; ipb < cur_pb->pb_graph_node->pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb->pb_graph_node->pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Refer to pack/output_clustering.c [LINE 392] */ + //if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { + /* Try to simplify the name tag... to avoid exceeding the length of SPICE name (up to 1024 chars) */ + /* gen_spice_name_tag_pb_rec(&(cur_pb->child_pbs[ipb][jpb]),prefix); */ + gen_spice_name_tag_pb_rec(&(cur_pb->child_pbs[ipb][jpb]),prefix_rec); + //} + } + } + + my_free(prefix_rec); + + return; +} + + +/* Generate a unique name tag for each pb, + * to identify it in both SPICE netlist and Power Modeling. + */ +void gen_spice_name_tags_all_pbs() { + int iblk; + char* prefix = NULL; + + for (iblk = 0; iblk < num_blocks; iblk++) { + prefix = (char*)my_malloc(sizeof(char)*(5 + strlen(my_itoa(block[iblk].x)) + 2 + strlen(my_itoa(block[iblk].y)) + 2)); + sprintf(prefix, "grid[%d][%d]", block[iblk].x, block[iblk].y); + gen_spice_name_tag_pb_rec(block[iblk].pb, prefix); + my_free(prefix); + } + + return; +} + +/* Make sure the edge has only one input pin and output pin*/ +void check_pb_graph_edge(t_pb_graph_edge pb_graph_edge) { + assert(1 == pb_graph_edge.num_input_pins); + assert(1 == pb_graph_edge.num_output_pins); + + return; +} + +/* Check all the edges for a given pb_graph_pin*/ +void check_pb_graph_pin_edges(t_pb_graph_pin pb_graph_pin) { + int iedge; + + for (iedge = 0; iedge < pb_graph_pin.num_input_edges; iedge++) { + check_pb_graph_edge(*(pb_graph_pin.input_edges[iedge])); + } + + for (iedge = 0; iedge < pb_graph_pin.num_output_edges; iedge++) { + check_pb_graph_edge(*(pb_graph_pin.output_edges[iedge])); + } + + return; +} + +int find_pb_mapped_logical_block_rec(t_pb* cur_pb, + t_spice_model* pb_spice_model, + char* pb_spice_name_tag) { + int logical_block_index = OPEN; + int mode_index, ipb, jpb; + + assert(NULL != cur_pb); + + if ((pb_spice_model == cur_pb->pb_graph_node->pb_type->spice_model) + &&(0 == strcmp(cur_pb->spice_name_tag, pb_spice_name_tag))) { + /* Special for LUT... They have sub modes!!!*/ + if (SPICE_MODEL_LUT == pb_spice_model->type) { + mode_index = cur_pb->mode; + assert(NULL != cur_pb->child_pbs); + return cur_pb->child_pbs[0][0].logical_block; + } + assert(pb_spice_model == logical_block[cur_pb->logical_block].mapped_spice_model); + return cur_pb->logical_block; + } + + /* Go recursively ... */ + mode_index = cur_pb->mode; + if (0 == cur_pb->pb_graph_node->pb_type->num_modes) { + return logical_block_index; + } + for (ipb = 0; ipb < cur_pb->pb_graph_node->pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb->pb_graph_node->pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Refer to pack/output_clustering.c [LINE 392] */ + if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { + logical_block_index = + find_pb_mapped_logical_block_rec(&(cur_pb->child_pbs[ipb][jpb]), pb_spice_model, pb_spice_name_tag); + if (OPEN != logical_block_index) { + return logical_block_index; + } + } + } + } + + return logical_block_index; +} + +int find_grid_mapped_logical_block(int x, int y, + t_spice_model* pb_spice_model, + char* pb_spice_name_tag) { + int logical_block_index = OPEN; + int iblk; + + /* Find the grid usage */ + if (0 == grid[x][y].usage) { + return logical_block_index; + } else { + assert(0 < grid[x][y].usage); + /* search each block */ + for (iblk = 0; iblk < grid[x][y].usage; iblk++) { + /* Get the pb */ + logical_block_index = find_pb_mapped_logical_block_rec(block[grid[x][y].blocks[iblk]].pb, + pb_spice_model, pb_spice_name_tag); + if (OPEN != logical_block_index) { + return logical_block_index; + } + } + } + + return logical_block_index; +} + +void stats_pb_graph_node_port_pin_numbers(t_pb_graph_node* cur_pb_graph_node, + int* num_inputs, + int* num_outputs, + int* num_clock_pins) { + int iport; + + assert(NULL != cur_pb_graph_node); + + (*num_inputs) = 0; + for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { + (*num_inputs) += cur_pb_graph_node->num_input_pins[iport]; + } + (*num_outputs) = 0; + for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) { + (*num_outputs) += cur_pb_graph_node->num_output_pins[iport]; + } + (*num_clock_pins) = 0; + for (iport = 0; iport < cur_pb_graph_node->num_clock_ports; iport++) { + (*num_clock_pins) += cur_pb_graph_node->num_clock_pins[iport]; + } + + return; +} + +int recommend_num_sim_clock_cycle(float sim_window_size) { + float avg_density = 0.; + float median_density = 0.; + int recmd_num_sim_clock_cycle = 0; + int inet, jnet; + int net_cnt = 0; + float* density_value = NULL; + int* sort_index = NULL; + int* net_to_sort_index_mapping = NULL; + + float weighted_avg_density = 0.; + float net_weight = 0.; + int weighted_net_cnt = 0; + + /* get the average density of all the nets */ + for (inet = 0; inet < num_logical_nets; inet++) { + assert(NULL != vpack_net[inet].spice_net_info); + if ((FALSE == vpack_net[inet].is_global) + &&(FALSE == vpack_net[inet].is_const_gen) + &&(0. != vpack_net[inet].spice_net_info->density)) { + avg_density += vpack_net[inet].spice_net_info->density; + net_cnt++; + /* Consider the weight of fan-out */ + if (0 == vpack_net[inet].num_sinks) { + net_weight = 1; + } else { + assert( 0 < vpack_net[inet].num_sinks ); + net_weight = vpack_net[inet].num_sinks; + } + weighted_avg_density += vpack_net[inet].spice_net_info->density * net_weight; + weighted_net_cnt += net_weight; + } + } + avg_density = avg_density/net_cnt; + weighted_avg_density = weighted_avg_density/weighted_net_cnt; + + /* Fill the array to be sorted */ + density_value = (float*)my_malloc(sizeof(float)*net_cnt); + sort_index = (int*)my_malloc(sizeof(int)*net_cnt); + net_to_sort_index_mapping = (int*)my_malloc(sizeof(int)*net_cnt); + jnet = 0; + for (inet = 0; inet < num_logical_nets; inet++) { + assert(NULL != vpack_net[inet].spice_net_info); + if ((FALSE == vpack_net[inet].is_global) + &&(FALSE == vpack_net[inet].is_const_gen) + &&(0. != vpack_net[inet].spice_net_info->density)) { + sort_index[jnet] = jnet; + net_to_sort_index_mapping[jnet] = inet; + density_value[jnet] = vpack_net[inet].spice_net_info->density; + jnet++; + } + } + assert(jnet == net_cnt); + /* Sort the density */ + quicksort_float_index(net_cnt, sort_index, density_value); + /* Get the median */ + median_density = vpack_net[sort_index[(int)(0.5*net_cnt)]].spice_net_info->density; + + /* It may be more reasonable to use median + * But, if median density is 0, we use average density + */ + if ((0 == median_density) && (0 == avg_density)) { + recmd_num_sim_clock_cycle = 1; + vpr_printf(TIO_MESSAGE_WARNING, + "All the signal density is zero! No. of clock cycles in simulations are set to be %d!", + recmd_num_sim_clock_cycle); + } else if (0 == avg_density) { + recmd_num_sim_clock_cycle = (int)(1/median_density); + } else if (0 == median_density) { + recmd_num_sim_clock_cycle = (int)(1/avg_density); + } else { + /* add a sim window size to balance the weight of average density and median density + * In practice, we find that there could be huge difference between avereage and median values + * For a reasonable number of simulation clock cycles, we do this window size. + */ + recmd_num_sim_clock_cycle = (int)round(1 / (sim_window_size * avg_density + (1 - sim_window_size) * median_density )); + } + + assert( 0 < recmd_num_sim_clock_cycle); + + vpr_printf(TIO_MESSAGE_INFO, "Average net density: %.2f\n", avg_density); + vpr_printf(TIO_MESSAGE_INFO, "Median net density: %.2f\n", median_density); + vpr_printf(TIO_MESSAGE_INFO, "Average net densityi after weighting: %.2f\n", weighted_avg_density); + vpr_printf(TIO_MESSAGE_INFO, "Window size set for Simulation: %.2f\n", sim_window_size); + vpr_printf(TIO_MESSAGE_INFO, "Net density after Window size : %.2f\n", + (sim_window_size * avg_density + (1 - sim_window_size) * median_density)); + vpr_printf(TIO_MESSAGE_INFO, "Recommend no. of clock cycles: %d\n", recmd_num_sim_clock_cycle); + + /* Free */ + my_free(sort_index); + my_free(density_value); + my_free(net_to_sort_index_mapping); + + return recmd_num_sim_clock_cycle; +} + +void auto_select_num_sim_clock_cycle(t_spice* spice, + float sim_window_size) { + int recmd_num_sim_clock_cycle = recommend_num_sim_clock_cycle(sim_window_size); + + /* Auto select number of simulation clock cycles*/ + if (-1 == spice->spice_params.meas_params.sim_num_clock_cycle) { + vpr_printf(TIO_MESSAGE_INFO, "Auto select the no. of clock cycles in simulation: %d\n", recmd_num_sim_clock_cycle); + spice->spice_params.meas_params.sim_num_clock_cycle = recmd_num_sim_clock_cycle; + } else { + vpr_printf(TIO_MESSAGE_INFO, "No. of clock cycles in simulation is forced to be: %d\n", + spice->spice_params.meas_params.sim_num_clock_cycle); + } + + return; +} + +/* Malloc grid_index_low and grid_index_high for a spice_model */ +void alloc_spice_model_grid_index_low_high(t_spice_model* cur_spice_model) { + int ix, iy; + + /* grid_index_low */ + /* x - direction*/ + cur_spice_model->grid_index_low = (int**)my_malloc(sizeof(int*)*(nx + 2)); + /* y - direction*/ + for (ix = 0; ix < (nx + 2); ix++) { + cur_spice_model->grid_index_low[ix] = (int*)my_malloc(sizeof(int)*(ny + 2)); + } + /* Initialize */ + for (ix = 0; ix < (nx + 2); ix++) { + for (iy = 0; iy < (ny + 2); iy++) { + cur_spice_model->grid_index_low[ix][iy] = 0; + } + } + /* grid_index_high */ + /* x - direction*/ + cur_spice_model->grid_index_high = (int**)my_malloc(sizeof(int*)*(nx + 2)); + /* y - direction*/ + for (ix = 0; ix < (nx + 2); ix++) { + cur_spice_model->grid_index_high[ix] = (int*)my_malloc(sizeof(int)*(ny + 2)); + } + /* Initialize */ + for (ix = 0; ix < (nx + 2); ix++) { + for (iy = 0; iy < (ny + 2); iy++) { + cur_spice_model->grid_index_high[ix][iy] = 0; + } + } + + return; +} + +void free_one_spice_model_grid_index_low_high(t_spice_model* cur_spice_model) { + int ix; + + for (ix = 0; ix < (nx + 2); ix++) { + my_free(cur_spice_model->grid_index_high[ix]); + my_free(cur_spice_model->grid_index_low[ix]); + } + + my_free(cur_spice_model->grid_index_high); + my_free(cur_spice_model->grid_index_low); + + return; +} + +void free_spice_model_grid_index_low_high(int num_spice_models, + t_spice_model* spice_model) { + int i; + + for (i = 0; i < num_spice_models; i++) { + free_one_spice_model_grid_index_low_high(&(spice_model[i])); + } + return; +} + + +void update_one_spice_model_grid_index_low(int x, int y, + t_spice_model* cur_spice_model) { + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + assert(NULL != cur_spice_model); + assert(NULL != cur_spice_model->grid_index_low); + assert(NULL != cur_spice_model->grid_index_low[x]); + + /* Assigne the low */ + cur_spice_model->grid_index_low[x][y] = cur_spice_model->cnt; + + return; +} + +void update_spice_models_grid_index_low(int x, int y, + int num_spice_models, + t_spice_model* spice_model) { + int i; + + for (i = 0; i < num_spice_models; i++) { + update_one_spice_model_grid_index_low(x, y, &(spice_model[i])); + } + + return; +} + +void update_one_spice_model_grid_index_high(int x, int y, + t_spice_model* cur_spice_model) { + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + assert(NULL != cur_spice_model); + assert(NULL != cur_spice_model->grid_index_high); + assert(NULL != cur_spice_model->grid_index_high[x]); + + /* Assigne the low */ + cur_spice_model->grid_index_high[x][y] = cur_spice_model->cnt; + + return; +} + +void update_spice_models_grid_index_high(int x, int y, + int num_spice_models, + t_spice_model* spice_model) { + int i; + + for (i = 0; i < num_spice_models; i++) { + update_one_spice_model_grid_index_high(x, y, &(spice_model[i])); + } + + return; +} + +void zero_one_spice_model_grid_index_low_high(t_spice_model* cur_spice_model) { + int ix, iy; + /* Initialize */ + for (ix = 0; ix < (nx + 2); ix++) { + for (iy = 0; iy < (ny + 2); iy++) { + cur_spice_model->grid_index_high[ix][iy] = 0; + cur_spice_model->grid_index_low[ix][iy] = 0; + } + } + return; +} + +void zero_spice_model_grid_index_low_high(int num_spice_models, + t_spice_model* spice_model) { + int i; + + for (i = 0; i < num_spice_models; i++) { + zero_one_spice_model_grid_index_low_high(&(spice_model[i])); + } + + return; +} + +char* gen_str_spice_model_structure(enum e_spice_model_structure spice_model_structure) { + switch (spice_model_structure) { + case SPICE_MODEL_STRUCTURE_TREE: + return "tree-like"; + case SPICE_MODEL_STRUCTURE_ONELEVEL: + return "one-level"; + case SPICE_MODEL_STRUCTURE_MULTILEVEL: + return "multi-level"; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid spice model structure!\n", + __FILE__, __LINE__); + exit(1); + } +} + +/* Check if the spice model structure is the same with the switch_inf structure */ +boolean check_spice_model_structure_match_switch_inf(t_switch_inf target_switch_inf) { + assert(NULL != target_switch_inf.spice_model); + if (target_switch_inf.structure != target_switch_inf.spice_model->design_tech_info.structure) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Structure in spice_model(%s) is different from switch_inf[%s]!\n", + __FILE__, __LINE__, target_switch_inf.spice_model->name, target_switch_inf.name); + return FALSE; + } + return TRUE; +} + +int find_pb_type_idle_mode_index(t_pb_type cur_pb_type) { + int idle_mode_index = 0; + int imode = 0; + int num_idle_mode = 0; + + /* if we touch the leaf node */ + if (NULL != cur_pb_type.blif_model) { + return 0; + } + + if (0 == cur_pb_type.num_modes) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Intend to find the idle mode while cur_pb_type has 0 modes!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Normal Condition: */ + for (imode = 0; imode < cur_pb_type.num_modes; imode++) { + if (1 == cur_pb_type.modes[imode].define_idle_mode) { + idle_mode_index = imode; + num_idle_mode++; + } + } + assert(1 == num_idle_mode); + + return idle_mode_index; +} + +/* Find the physical mode index */ +int find_pb_type_physical_mode_index(t_pb_type cur_pb_type) { + int phy_mode_index = 0; + int imode = 0; + int num_phy_mode = 0; + + /* if we touch the leaf node */ + if (NULL != cur_pb_type.blif_model) { + return 0; + } + + if (0 == cur_pb_type.num_modes) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Intend to find the idle mode while cur_pb_type has 0 modes!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Normal Condition: */ + for (imode = 0; imode < cur_pb_type.num_modes; imode++) { + if (1 == cur_pb_type.modes[imode].define_physical_mode) { + phy_mode_index = imode; + num_phy_mode++; + } + } + assert(1 == num_phy_mode); + + return phy_mode_index; +} + +void mark_grid_type_pb_graph_node_pins_temp_net_num(int x, int y) { + int iport, ipin, type_pin_index, class_id, pin_global_rr_node_id; + t_type_ptr type = NULL; + t_pb_graph_node* top_pb_graph_node = NULL; + int mode_index, ipb, jpb; + + /* Assert */ + assert((!(x < 0))&&(x < (nx + 2))); + assert((!(y < 0))&&(y < (ny + 2))); + + type = grid[x][y].type; + + if (EMPTY_TYPE == type) { + return; /* Bypass empty grid */ + } + + top_pb_graph_node = type->pb_graph_head; + /* Input ports */ + for (iport = 0; iport < top_pb_graph_node->num_input_ports; iport++) { + for (ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport]; ipin++) { + top_pb_graph_node->input_pins[iport][ipin].temp_net_num = OPEN; + type_pin_index = top_pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster; + class_id = type->pin_class[type_pin_index]; + assert(RECEIVER == type->class_inf[class_id].type); + /* Find the pb net_num and update OPIN net_num */ + pin_global_rr_node_id = get_rr_node_index(x, y, IPIN, type_pin_index, rr_node_indices); + if (OPEN == rr_node[pin_global_rr_node_id].net_num) { + top_pb_graph_node->input_pins[iport][ipin].temp_net_num = OPEN; + continue; + } + top_pb_graph_node->input_pins[iport][ipin].temp_net_num = clb_to_vpack_net_mapping[rr_node[pin_global_rr_node_id].net_num]; + } + } + /* clock ports */ + for (iport = 0; iport < top_pb_graph_node->num_clock_ports; iport++) { + for (ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport]; ipin++) { + top_pb_graph_node->clock_pins[iport][ipin].temp_net_num = OPEN; + type_pin_index = top_pb_graph_node->clock_pins[iport][ipin].pin_count_in_cluster; + class_id = type->pin_class[type_pin_index]; + assert(RECEIVER == type->class_inf[class_id].type); + /* Find the pb net_num and update OPIN net_num */ + pin_global_rr_node_id = get_rr_node_index(x, y, IPIN, type_pin_index, rr_node_indices); + if (OPEN == rr_node[pin_global_rr_node_id].net_num) { + top_pb_graph_node->clock_pins[iport][ipin].temp_net_num = OPEN; + continue; + } + top_pb_graph_node->clock_pins[iport][ipin].temp_net_num = clb_to_vpack_net_mapping[rr_node[pin_global_rr_node_id].net_num]; + } + } + + /* Go recursively ... */ + mode_index = find_pb_type_idle_mode_index(*(top_pb_graph_node->pb_type)); + for (ipb = 0; ipb < top_pb_graph_node->pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < top_pb_graph_node->pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Mark pb_graph_node temp_net_num */ + rec_mark_pb_graph_node_temp_net_num(&(top_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb])); + } + } + + /* Output ports */ + for (iport = 0; iport < top_pb_graph_node->num_output_ports; iport++) { + for (ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport]; ipin++) { + top_pb_graph_node->output_pins[iport][ipin].temp_net_num = OPEN; + type_pin_index = top_pb_graph_node->output_pins[iport][ipin].pin_count_in_cluster; + class_id = type->pin_class[type_pin_index]; + assert(DRIVER == type->class_inf[class_id].type); + /* Find the pb net_num and update OPIN net_num */ + pin_global_rr_node_id = get_rr_node_index(x, y, OPIN, type_pin_index, rr_node_indices); + if (OPEN == rr_node[pin_global_rr_node_id].net_num) { + top_pb_graph_node->output_pins[iport][ipin].temp_net_num = OPEN; + continue; + } + top_pb_graph_node->output_pins[iport][ipin].temp_net_num = clb_to_vpack_net_mapping[rr_node[pin_global_rr_node_id].net_num]; + } + } + + /* Run again to handle feedback loop */ + /* Input ports */ + for (iport = 0; iport < top_pb_graph_node->num_input_ports; iport++) { + for (ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport]; ipin++) { + top_pb_graph_node->input_pins[iport][ipin].temp_net_num = OPEN; + type_pin_index = top_pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster; + class_id = type->pin_class[type_pin_index]; + assert(RECEIVER == type->class_inf[class_id].type); + /* Find the pb net_num and update OPIN net_num */ + pin_global_rr_node_id = get_rr_node_index(x, y, IPIN, type_pin_index, rr_node_indices); + if (OPEN == rr_node[pin_global_rr_node_id].net_num) { + top_pb_graph_node->input_pins[iport][ipin].temp_net_num = OPEN; + continue; + } + top_pb_graph_node->input_pins[iport][ipin].temp_net_num = clb_to_vpack_net_mapping[rr_node[pin_global_rr_node_id].net_num]; + } + } + /* clock ports */ + for (iport = 0; iport < top_pb_graph_node->num_clock_ports; iport++) { + for (ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport]; ipin++) { + top_pb_graph_node->clock_pins[iport][ipin].temp_net_num = OPEN; + type_pin_index = top_pb_graph_node->clock_pins[iport][ipin].pin_count_in_cluster; + class_id = type->pin_class[type_pin_index]; + assert(RECEIVER == type->class_inf[class_id].type); + /* Find the pb net_num and update OPIN net_num */ + pin_global_rr_node_id = get_rr_node_index(x, y, IPIN, type_pin_index, rr_node_indices); + if (OPEN == rr_node[pin_global_rr_node_id].net_num) { + top_pb_graph_node->clock_pins[iport][ipin].temp_net_num = OPEN; + continue; + } + top_pb_graph_node->clock_pins[iport][ipin].temp_net_num = clb_to_vpack_net_mapping[rr_node[pin_global_rr_node_id].net_num]; + } + } + + + return; +} + +/* Assign the temp_net_num by considering the first incoming edge that belongs to the correct operating mode */ +void assign_pb_graph_node_pin_temp_net_num_by_mode_index(t_pb_graph_pin* cur_pb_graph_pin, + int mode_index) { + int iedge; + + /* IMPORTANT: I assume by default the index of selected edge is 0 + * Make sure this input edge comes from the default mode + */ + for (iedge = 0; iedge < cur_pb_graph_pin->num_input_edges; iedge++) { + if (mode_index != cur_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode_index) { + continue; + } + cur_pb_graph_pin->temp_net_num = cur_pb_graph_pin->input_edges[iedge]->input_pins[0]->temp_net_num; + break; + } + + return; +} + +void mark_pb_graph_node_input_pins_temp_net_num(t_pb_graph_node* cur_pb_graph_node, + int mode_index) { + int iport, ipin; + + assert(NULL != cur_pb_graph_node); + + /* Input ports */ + for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { + for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) { + cur_pb_graph_node->input_pins[iport][ipin].temp_net_num = OPEN; + /* IMPORTANT: I assume by default the index of selected edge is 0 + * Make sure this input edge comes from the default mode + */ + assign_pb_graph_node_pin_temp_net_num_by_mode_index(&(cur_pb_graph_node->input_pins[iport][ipin]), mode_index); + } + } + + return; +} + +void mark_pb_graph_node_clock_pins_temp_net_num(t_pb_graph_node* cur_pb_graph_node, + int mode_index) { + int iport, ipin; + + assert(NULL != cur_pb_graph_node); + + /* Clock ports */ + for (iport = 0; iport < cur_pb_graph_node->num_clock_ports; iport++) { + for (ipin = 0; ipin < cur_pb_graph_node->num_clock_pins[iport]; ipin++) { + cur_pb_graph_node->clock_pins[iport][ipin].temp_net_num = OPEN; + assign_pb_graph_node_pin_temp_net_num_by_mode_index(&(cur_pb_graph_node->clock_pins[iport][ipin]), mode_index); + } + } + + return; +} + +void mark_pb_graph_node_output_pins_temp_net_num(t_pb_graph_node* cur_pb_graph_node, + int mode_index) { + int iport, ipin; + + assert(NULL != cur_pb_graph_node); + + for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) { + for (ipin = 0; ipin < cur_pb_graph_node->num_output_pins[iport]; ipin++) { + cur_pb_graph_node->output_pins[iport][ipin].temp_net_num = OPEN; + /* IMPORTANT: I assume by default the index of selected edge is 0 + * Make sure this input edge comes from the default mode + */ + assign_pb_graph_node_pin_temp_net_num_by_mode_index(&(cur_pb_graph_node->output_pins[iport][ipin]), mode_index); + } + } + + return; +} + +/* Mark temp_net_num in current pb_graph_node from the parent pb_graph_node */ +void rec_mark_pb_graph_node_temp_net_num(t_pb_graph_node* cur_pb_graph_node) { + int mode_index, ipb, jpb; + + assert(NULL != cur_pb_graph_node); + + /* Find the default mode */ + mode_index = find_pb_type_idle_mode_index(*(cur_pb_graph_node->pb_type)); + + mark_pb_graph_node_input_pins_temp_net_num(cur_pb_graph_node, mode_index); + + mark_pb_graph_node_clock_pins_temp_net_num(cur_pb_graph_node, mode_index); + + if (NULL != cur_pb_graph_node->pb_type->spice_model) { + return; + } + + /* Go recursively ... */ + mode_index = find_pb_type_idle_mode_index(*(cur_pb_graph_node->pb_type)); + for (ipb = 0; ipb < cur_pb_graph_node->pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb_graph_node->pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Mark pb_graph_node temp_net_num */ + rec_mark_pb_graph_node_temp_net_num(&(cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb])); + } + } + + /* IMPORTANT: update the temp_net of Output ports after recursion is done! + * the outputs of sub pb_graph_node should be updated first + */ + mark_pb_graph_node_output_pins_temp_net_num(cur_pb_graph_node, mode_index); + + /* Do this again to handle feedback loops ! */ + mark_pb_graph_node_input_pins_temp_net_num(cur_pb_graph_node, mode_index); + + mark_pb_graph_node_clock_pins_temp_net_num(cur_pb_graph_node, mode_index); + + return; +} + +void load_one_pb_graph_pin_temp_net_num_from_pb(t_pb* cur_pb, + t_pb_graph_pin* cur_pb_graph_pin) { + int node_index; + t_rr_node* pb_rr_nodes = NULL; + + assert(NULL != cur_pb); + assert(NULL != cur_pb->pb_graph_node); + + /* Get the selected edge of current pin*/ + pb_rr_nodes = cur_pb->rr_graph; + node_index = cur_pb_graph_pin->pin_count_in_cluster; + cur_pb_graph_pin->temp_net_num = pb_rr_nodes[node_index].vpack_net_num; + + return; +} + +/* According to the vpack_net_num in cur_pb + * assign it to the corresponding pb_graph_pins + */ +void load_pb_graph_node_temp_net_num_from_pb(t_pb* cur_pb) { + int iport, ipin; + + assert(NULL != cur_pb); + assert(NULL != cur_pb->pb_graph_node); + + /* Input ports */ + for (iport = 0; iport < cur_pb->pb_graph_node->num_input_ports; iport++) { + for (ipin = 0; ipin < cur_pb->pb_graph_node->num_input_pins[iport]; ipin++) { + load_one_pb_graph_pin_temp_net_num_from_pb(cur_pb, + &(cur_pb->pb_graph_node->input_pins[iport][ipin])); + } + } + + /* Clock ports */ + for (iport = 0; iport < cur_pb->pb_graph_node->num_clock_ports; iport++) { + for (ipin = 0; ipin < cur_pb->pb_graph_node->num_clock_pins[iport]; ipin++) { + load_one_pb_graph_pin_temp_net_num_from_pb(cur_pb, + &(cur_pb->pb_graph_node->clock_pins[iport][ipin])); + } + } + + /* Output ports */ + for (iport = 0; iport < cur_pb->pb_graph_node->num_output_ports; iport++) { + for (ipin = 0; ipin < cur_pb->pb_graph_node->num_output_pins[iport]; ipin++) { + load_one_pb_graph_pin_temp_net_num_from_pb(cur_pb, + &(cur_pb->pb_graph_node->output_pins[iport][ipin])); + } + } + + return; +} + +/* Recursively traverse the hierachy of a pb, + * store parasitic nets in the temp_net_num of the assoicated pb_graph_node + */ +void rec_mark_one_pb_unused_pb_graph_node_temp_net_num(t_pb* cur_pb) { + int ipb, jpb; + int mode_index; + + /* Check */ + assert(NULL != cur_pb); + + if (NULL != cur_pb->pb_graph_node->pb_type->spice_model) { + return; + } + /* Go recursively ... */ + mode_index = cur_pb->mode; + if (!(0 < cur_pb->pb_graph_node->pb_type->num_modes)) { + return; + } + for (ipb = 0; ipb < cur_pb->pb_graph_node->pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb->pb_graph_node->pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Refer to pack/output_clustering.c [LINE 392] */ + if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { + rec_mark_one_pb_unused_pb_graph_node_temp_net_num(&(cur_pb->child_pbs[ipb][jpb])); + } else { + /* Print idle graph_node muxes */ + load_pb_graph_node_temp_net_num_from_pb(cur_pb); + /* We should update the net_num */ + rec_mark_pb_graph_node_temp_net_num(cur_pb->child_pbs[ipb][jpb].pb_graph_node); + } + } + } + + return; +} + +void update_pb_vpack_net_num_from_temp_net_num(t_pb* cur_pb, + t_pb_graph_pin* cur_pb_graph_pin) { + int node_index; + t_rr_node* pb_rr_nodes = NULL; + + assert(NULL != cur_pb); + assert(NULL != cur_pb->pb_graph_node); + + /* Get the selected edge of current pin*/ + pb_rr_nodes = cur_pb->rr_graph; + node_index = cur_pb_graph_pin->pin_count_in_cluster; + + /* Avoid mistakenly modification */ + if (OPEN != pb_rr_nodes[node_index].vpack_net_num) { + return; + } + /* Only modify when original vpack_net_num is open!!! */ + pb_rr_nodes[node_index].vpack_net_num = cur_pb_graph_pin->temp_net_num; + + return; +} + +void update_pb_graph_node_temp_net_num_to_pb(t_pb_graph_node* cur_pb_graph_node, + t_pb* cur_pb) { + int iport, ipin; + t_rr_node* pb_rr_nodes = NULL; + + assert(NULL != cur_pb->pb_graph_node); + assert(NULL != cur_pb); + + pb_rr_nodes = cur_pb->rr_graph; + + /* Input ports */ + for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { + for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) { + update_pb_vpack_net_num_from_temp_net_num(cur_pb, + &(cur_pb_graph_node->input_pins[iport][ipin])); + } + } + + /* Clock ports */ + for (iport = 0; iport < cur_pb_graph_node->num_clock_ports; iport++) { + for (ipin = 0; ipin < cur_pb_graph_node->num_clock_pins[iport]; ipin++) { + update_pb_vpack_net_num_from_temp_net_num(cur_pb, + &(cur_pb_graph_node->clock_pins[iport][ipin])); + } + } + + /* Output ports */ + for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) { + for (ipin = 0; ipin < cur_pb_graph_node->num_output_pins[iport]; ipin++) { + update_pb_vpack_net_num_from_temp_net_num(cur_pb, + &(cur_pb_graph_node->output_pins[iport][ipin])); + } + } + + return; +} + +void rec_load_unused_pb_graph_node_temp_net_num_to_pb(t_pb* cur_pb) { + int ipb, jpb; + int mode_index; + + /* Check */ + assert(NULL != cur_pb); + + if (NULL != cur_pb->pb_graph_node->pb_type->spice_model) { + return; + } + /* Go recursively ... */ + mode_index = cur_pb->mode; + if (!(0 < cur_pb->pb_graph_node->pb_type->num_modes)) { + return; + } + for (ipb = 0; ipb < cur_pb->pb_graph_node->pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb->pb_graph_node->pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Refer to pack/output_clustering.c [LINE 392] */ + if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { + rec_load_unused_pb_graph_node_temp_net_num_to_pb(&(cur_pb->child_pbs[ipb][jpb])); + } else { + update_pb_graph_node_temp_net_num_to_pb(cur_pb->child_pbs[ipb][jpb].pb_graph_node, + cur_pb); + } + } + } + + return; +} + +void mark_one_pb_parasitic_nets(t_pb* cur_pb) { + + /* By go recursively, parasitic net num are stored in the temp_net_num in pb_graph_node */ + rec_mark_one_pb_unused_pb_graph_node_temp_net_num(cur_pb); + + /* Load the temp_net_num to vpack_net_num in the current pb! */ + rec_load_unused_pb_graph_node_temp_net_num_to_pb(cur_pb); + + return; +} + +void init_rr_nodes_vpack_net_num_changed(int LL_num_rr_nodes, + t_rr_node* LL_rr_node) { + int inode; + + for (inode = 0; inode < LL_num_rr_nodes; inode++) { + LL_rr_node[inode].vpack_net_num_changed = FALSE; + } + + return; +} + +/* Check if this net is connected to a PI*/ +boolean is_net_pi(t_net* cur_net) { + int src_blk_idx; + + assert(NULL != cur_net); + + src_blk_idx = cur_net->node_block[0]; + if (VPACK_INPAD == logical_block[src_blk_idx].type) { + return TRUE; + } + return FALSE; +} + +int check_consistency_logical_block_net_num(t_logical_block* lgk_blk, + int num_inputs, int* input_net_num) { + int i, iport, ipin, net_eq; + int consistency = 1; + int* input_net_num_mapped = (int*)my_calloc(num_inputs, sizeof(int)); + + for (iport = 0; iport < lgk_blk->pb->pb_graph_node->num_input_ports; iport++) { + for (ipin = 0; ipin < lgk_blk->pb->pb_graph_node->num_input_pins[iport]; ipin++) { + if (OPEN == lgk_blk->input_nets[iport][ipin]) { + continue; /* bypass unused pins */ + } + /* Initial net_eq */ + net_eq = 0; + /* Check if this net can be found in the input net_num */ + for (i = 0; i < num_inputs; i++) { + if (1 == input_net_num_mapped[i]) { + continue; + } + if (input_net_num[i] == lgk_blk->input_nets[iport][ipin]) { + net_eq = 1; + input_net_num_mapped[i] = 1; + break; + } + } + if (0 == net_eq) { + consistency = 0; + break; + } + } + if (0 == consistency) { + break; + } + } + + /* Free */ + my_free(input_net_num_mapped); + + return consistency; +} + +/* Determine if this rr_node is driving this switch box (x,y) + * For more than length-1 wire, the fan-in of a des_rr_node in a switch box + * contain all the drivers in the switch boxes that it passes through. + * This function is to identify if the src_rr_node is the driver in this switch box + */ +int rr_node_drive_switch_box(t_rr_node* src_rr_node, + t_rr_node* des_rr_node, + int switch_box_x, + int switch_box_y, + int chan_side) { + + /* Make sure a valid src_rr_node and des_rr_node */ + if (NULL == src_rr_node) { + assert(NULL != src_rr_node); + } + assert(NULL != des_rr_node); + /* The src_rr_node should be either CHANX or CHANY */ + assert((CHANX == des_rr_node->type)||(CHANY == des_rr_node->type)); + /* Valid switch_box coordinator */ + assert((!(0 > switch_box_x))&&(!(switch_box_x > (nx + 1)))); + assert((!(0 > switch_box_y))&&(!(switch_box_y > (ny + 1)))); + /* Valid des_rr_node coordinator */ + assert((!(switch_box_x < (des_rr_node->xlow-1)))&&(!(switch_box_x > (des_rr_node->xhigh+1)))); + assert((!(switch_box_y < (des_rr_node->ylow-1)))&&(!(switch_box_y > (des_rr_node->yhigh+1)))); + + /* Check the src_rr_node coordinator */ + switch (chan_side) { + case TOP: + /* Following cases: + * | + * / | \ + */ + /* The destination rr_node only have one condition!!! */ + assert((INC_DIRECTION == des_rr_node->direction)&&(CHANY == des_rr_node->type)); + /* depend on the type of src_rr_node */ + switch (src_rr_node->type) { + case OPIN: + if (((switch_box_y + 1) == src_rr_node->ylow) + &&((switch_box_x == src_rr_node->xlow)||((switch_box_x + 1) == src_rr_node->xlow))) { + return 1; + } + break; + case CHANX: + assert(src_rr_node->ylow == src_rr_node->yhigh); + if ((switch_box_y == src_rr_node->ylow) + &&(!(switch_box_x < (src_rr_node->xlow-1)))&&(!(switch_box_x > (src_rr_node->xhigh+1)))) { + return 1; + } + break; + case CHANY: + assert(src_rr_node->xlow == src_rr_node->xhigh); + if ((switch_box_x == src_rr_node->xlow) + &&(!(switch_box_y < src_rr_node->ylow))&&(!(switch_box_y > src_rr_node->yhigh))) { + return 1; + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid src_rr_node type!\n", + __FILE__, __LINE__); + exit(1); + } + break; + case RIGHT: + /* Following cases: + * \ + * --- ---- + * / + */ + /* The destination rr_node only have one condition!!! */ + assert((INC_DIRECTION == des_rr_node->direction)&&(CHANX == des_rr_node->type)); + /* depend on the type of src_rr_node */ + switch (src_rr_node->type) { + case OPIN: + if (((switch_box_x + 1) == src_rr_node->xlow) + &&((switch_box_y == src_rr_node->ylow)||((switch_box_y + 1) == src_rr_node->ylow))) { + return 1; + } + break; + case CHANX: + assert(src_rr_node->ylow == src_rr_node->yhigh); + if ((switch_box_y == src_rr_node->ylow) + &&(!(switch_box_x < src_rr_node->xlow))&&(!(switch_box_x > src_rr_node->xhigh))) { + return 1; + } + break; + case CHANY: + assert(src_rr_node->xlow == src_rr_node->xhigh); + if ((switch_box_x == src_rr_node->xlow) + &&(!(switch_box_y < (src_rr_node->ylow-1)))&&(!(switch_box_y > (src_rr_node->yhigh+1)))) { + return 1; + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid src_rr_node type!\n", + __FILE__, __LINE__); + exit(1); + } + break; + case BOTTOM: + /* Following cases: + * | + * \ / + * | + */ + /* The destination rr_node only have one condition!!! */ + assert((DEC_DIRECTION == des_rr_node->direction)&&(CHANY == des_rr_node->type)); + /* depend on the type of src_rr_node */ + switch (src_rr_node->type) { + case OPIN: + if ((switch_box_y == src_rr_node->ylow) + &&((switch_box_x == src_rr_node->xlow)||((switch_box_x + 1) == src_rr_node->xlow))) { + return 1; + } + break; + case CHANX: + assert(src_rr_node->ylow == src_rr_node->yhigh); + if ((switch_box_y == src_rr_node->ylow) + &&(!(switch_box_x < (src_rr_node->xlow-1)))&&(!(switch_box_x > (src_rr_node->xhigh+1)))) { + return 1; + } + break; + case CHANY: + assert(src_rr_node->xlow == src_rr_node->xhigh); + if ((switch_box_x == src_rr_node->xlow) + &&(!((switch_box_y+1) < src_rr_node->ylow))&&(!((switch_box_y+1) > src_rr_node->yhigh))) { + return 1; + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid src_rr_node type!\n", + __FILE__, __LINE__); + exit(1); + } + break; + case LEFT: + /* Following cases: + * / + * --- ---- + * \ + */ + /* The destination rr_node only have one condition!!! */ + assert((DEC_DIRECTION == des_rr_node->direction)&&(CHANX == des_rr_node->type)); + /* depend on the type of src_rr_node */ + switch (src_rr_node->type) { + case OPIN: + if ((switch_box_x == src_rr_node->xlow) + &&((switch_box_y == src_rr_node->ylow)||((switch_box_y + 1) == src_rr_node->ylow))) { + return 1; + } + break; + case CHANX: + assert(src_rr_node->ylow == src_rr_node->yhigh); + if ((switch_box_y == src_rr_node->ylow) + &&(!((switch_box_x+1) < src_rr_node->xlow))&&(!((switch_box_x+1) > src_rr_node->xhigh))) { + return 1; + } + break; + case CHANY: + assert(src_rr_node->xlow == src_rr_node->xhigh); + if ((switch_box_x == src_rr_node->xlow) + &&(!(switch_box_y < (src_rr_node->ylow-1)))&&(!(switch_box_y > (src_rr_node->yhigh+1)))) { + return 1; + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid src_rr_node type!\n", + __FILE__, __LINE__); + exit(1); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s, [LINE%d])Invalid side!\n", __FILE__, __LINE__); + exit(1); + } + + return 0; +} + +void find_drive_rr_nodes_switch_box(int switch_box_x, + int switch_box_y, + t_rr_node* src_rr_node, + int chan_side, + int return_num_only, + int* num_drive_rr_nodes, + t_rr_node*** drive_rr_nodes, + int* switch_index) { + int cur_index = 0; + //int inode, iedge, next_node; + int inode; + + /* I decide to kill the codes that search all the edges, the running time is huge... */ + /* Determine the num_drive_rr_nodes */ + (*num_drive_rr_nodes) = 0; + (*switch_index) = -1; + + for (inode = 0; inode < src_rr_node->num_drive_rr_nodes; inode++) { + if (1 == rr_node_drive_switch_box(src_rr_node->drive_rr_nodes[inode], src_rr_node, + switch_box_x, switch_box_y, chan_side)) { + /* Get the spice_model */ + if (-1 == (*switch_index)) { + (*switch_index) = src_rr_node->drive_switches[inode]; + } else { /* Make sure the switches are the same*/ + assert((*switch_index) == src_rr_node->drive_switches[inode]); + } + (*num_drive_rr_nodes)++; + } + } + + //for (inode = 0; inode < num_rr_nodes; inode++) { + // for (iedge = 0; iedge < rr_node[inode].num_edges; iedge++) { + // next_node = rr_node[inode].edges[iedge]; + // /* Make sure the coordinator is matched to this switch box*/ + // if ((src_rr_node == &(rr_node[next_node])) + // &&(1 == rr_node_drive_switch_box(&(rr_node[inode]), src_rr_node, switch_box_x, switch_box_y, chan_side))) { + // /* Get the spice_model */ + // if (-1 == (*switch_index)) { + // (*switch_index) = rr_node[inode].switches[iedge]; + // } else { /* Make sure the switches are the same*/ + // assert((*switch_index) == rr_node[inode].switches[iedge]); + // } + // (*num_drive_rr_nodes)++; + // } + // } + //} + + /* Check and malloc*/ + assert((!(0 > (*num_drive_rr_nodes)))&&(!((*num_drive_rr_nodes) > src_rr_node->fan_in))); + if (1 == return_num_only) { + return; + } + (*drive_rr_nodes) = NULL; + if (0 == (*num_drive_rr_nodes)) { + return; + } + (*drive_rr_nodes) = (t_rr_node**)my_malloc(sizeof(t_rr_node*)*(*num_drive_rr_nodes)); + + /* Find all the rr_nodes that drive current_rr_node*/ + cur_index = 0; + (*switch_index) = -1; + + for (inode = 0; inode < src_rr_node->num_drive_rr_nodes; inode++) { + if (1 == rr_node_drive_switch_box(src_rr_node->drive_rr_nodes[inode], src_rr_node, + switch_box_x, switch_box_y, chan_side)) { + /* Update drive_rr_nodes list */ + (*drive_rr_nodes)[cur_index] = src_rr_node->drive_rr_nodes[inode]; + /* Get the spice_model */ + if (-1 == (*switch_index)) { + (*switch_index) = src_rr_node->drive_switches[inode]; + } else { /* Make sure the switches are the same*/ + assert((*switch_index) == src_rr_node->drive_switches[inode]); + } + cur_index++; + } + } + //for (inode = 0; inode < num_rr_nodes; inode++) { + // for (iedge = 0; iedge < rr_node[inode].num_edges; iedge++) { + // next_node = rr_node[inode].edges[iedge]; + // /* Make sure the coordinator is matched to this switch box*/ + // if ((src_rr_node == &(rr_node[next_node])) + // &&(1 == rr_node_drive_switch_box(&(rr_node[inode]), src_rr_node, switch_box_x, switch_box_y, chan_side))) { + // /* Update drive_rr_nodes list */ + // (*drive_rr_nodes)[cur_index] = &(rr_node[inode]); + // /* Get the spice_model */ + // if (-1 == (*switch_index)) { + // (*switch_index) = rr_node[inode].switches[iedge]; + // } else { /* Make sure the switches are the same*/ + // assert((*switch_index) == rr_node[inode].switches[iedge]); + // } + // cur_index++; + // } + // } + //} + /* Verification */ + assert(cur_index == (*num_drive_rr_nodes)); + + return; +} + +int is_sb_interc_between_segments(int switch_box_x, + int switch_box_y, + t_rr_node* src_rr_node, + int chan_side) { + int inode; + int cur_sb_num_drive_rr_nodes = 0; + + for (inode = 0; inode < src_rr_node->num_drive_rr_nodes; inode++) { + if (1 == rr_node_drive_switch_box(src_rr_node->drive_rr_nodes[inode], src_rr_node, + switch_box_x, switch_box_y, chan_side)) { + cur_sb_num_drive_rr_nodes++; + } + } + if (0 == cur_sb_num_drive_rr_nodes) { + return 1; + } else { + return 0; + } +} + +/* Count the number of configuration bits of a spice model */ +int count_num_sram_bits_one_spice_model(t_spice_model* cur_spice_model, + int mux_size) { + int num_sram_bits = 0; + int iport; + int lut_size; + int num_input_port = 0; + t_spice_model_port** input_ports = NULL; + int num_output_port = 0; + t_spice_model_port** output_ports = NULL; + int num_sram_port = 0; + t_spice_model_port** sram_ports = NULL; + + assert(NULL != cur_spice_model); + + /* Only LUT and MUX requires configuration bits*/ + switch (cur_spice_model->type) { + case SPICE_MODEL_LUT: + /* Determine size of LUT*/ + input_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + output_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + sram_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); + assert(1 == num_input_port); + assert(1 == num_output_port); + assert(1 == num_sram_port); + lut_size = input_ports[0]->size; + num_sram_bits = (int)pow(2.,(double)(lut_size)); + assert(num_sram_bits == sram_ports[0]->size); + assert(1 == output_ports[0]->size); + /* TODO: could be more smart! Use mapped spice_model of SRAM ports! + * Support Non-volatile RRAM-based SRAM */ + switch (cur_spice_model->design_tech) { + case SPICE_MODEL_DESIGN_RRAM: + /* Non-volatile SRAM requires 2 BLs and 2 WLs for each 1 memory bit, + * Number of memory bits is still same as CMOS SRAM + */ + break; + case SPICE_MODEL_DESIGN_CMOS: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of LUT(name: %s)\n", + __FILE__, __LINE__, cur_spice_model->name); + exit(1); + } + break; + case SPICE_MODEL_MUX: + assert((2 == mux_size)||(2 < mux_size)); + /* Number of configuration bits depends on the MUX structure */ + switch (cur_spice_model->design_tech_info.structure) { + case SPICE_MODEL_STRUCTURE_TREE: + num_sram_bits = determine_tree_mux_level(mux_size); + break; + case SPICE_MODEL_STRUCTURE_ONELEVEL: + num_sram_bits = mux_size; + break; + case SPICE_MODEL_STRUCTURE_MULTILEVEL: + num_sram_bits = cur_spice_model->design_tech_info.mux_num_level + * determine_num_input_basis_multilevel_mux(mux_size, + cur_spice_model->design_tech_info.mux_num_level); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n", + __FILE__, __LINE__, cur_spice_model->name); + exit(1); + } + /* For 2:1 MUX, whatever structure, there is only one level */ + if (2 == mux_size) { + num_sram_bits = 1; + } + /* Also the number of configuration bits depends on the technology*/ + switch (cur_spice_model->design_tech) { + case SPICE_MODEL_DESIGN_RRAM: + /* 4T1R MUX requires more configuration bits */ + if (SPICE_MODEL_STRUCTURE_TREE == cur_spice_model->design_tech_info.structure) { + /* For tree-structure: we need 3 times more config. bits */ + num_sram_bits = 3 * num_sram_bits; + } else if (SPICE_MODEL_STRUCTURE_MULTILEVEL == cur_spice_model->design_tech_info.structure) { + /* For multi-level structure: we need 1 more config. bits for each level */ + num_sram_bits += cur_spice_model->design_tech_info.mux_num_level; + } else { + num_sram_bits = (num_sram_bits + 1); + } + /* For 2:1 MUX, whatever structure, there is only one level */ + if (2 == mux_size) { + num_sram_bits = 3; + } + break; + case SPICE_MODEL_DESIGN_CMOS: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of MUX(name: %s)\n", + __FILE__, __LINE__, cur_spice_model->name); + exit(1); + } + break; + case SPICE_MODEL_WIRE: + case SPICE_MODEL_FF: + case SPICE_MODEL_SRAM: + case SPICE_MODEL_HARDLOGIC: + case SPICE_MODEL_SCFF: + case SPICE_MODEL_VDD: + case SPICE_MODEL_GND: + case SPICE_MODEL_IOPAD: + /* Other block, we just count the number SRAM ports defined by user */ + num_sram_bits = 0; + sram_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); + /* TODO: could be more smart! + * Support Non-volatile RRAM-based SRAM */ + if (0 < num_sram_port) { + assert(NULL != sram_ports); + for (iport = 0; iport < num_sram_port; iport++) { + assert(NULL != sram_ports[iport]->spice_model); + num_sram_bits += sram_ports[iport]->size; + /* TODO: could be more smart! + * Support Non-volatile RRAM-based SRAM */ + switch (cur_spice_model->design_tech) { + case SPICE_MODEL_DESIGN_RRAM: + /* Non-volatile SRAM requires 2 BLs and 2 WLs for each 1 memory bit, + * Number of memory bits is still same as CMOS SRAM + */ + case SPICE_MODEL_DESIGN_CMOS: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of LUT(name: %s)\n", + __FILE__, __LINE__, cur_spice_model->name); + exit(1); + } + } + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid spice_model_type!\n", __FILE__, __LINE__); + exit(1); + } + + return num_sram_bits; +} + +/* For a multiplexer, determine its reserved configuration bits */ +int count_num_reserved_conf_bits_one_lut_spice_model(t_spice_model* cur_spice_model, + enum e_sram_orgz cur_sram_orgz_type) { + int num_reserved_conf_bits = 0; + int num_sram_port = 0; + t_spice_model_port** sram_ports = NULL; + + /* Check */ + assert(SPICE_MODEL_LUT == cur_spice_model->type); + + /* Determine size of LUT*/ + sram_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); + assert(1 == num_sram_port); + /* TODO: could be more smart! Use mapped spice_model of SRAM ports! + * Support Non-volatile RRAM-based SRAM */ + switch (sram_ports[0]->spice_model->design_tech) { + case SPICE_MODEL_DESIGN_RRAM: + /* Non-volatile SRAM requires 2 BLs and 2 WLs for each 1 memory bit, + * In memory bank, by intensively share the Bit/Word Lines, + * we only need 1 additional BL and WL for each memory bit. + * Number of memory bits is still same as CMOS SRAM + */ + num_reserved_conf_bits = + count_num_reserved_conf_bits_one_rram_sram_spice_model(sram_ports[0]->spice_model, + cur_sram_orgz_type); + break; + case SPICE_MODEL_DESIGN_CMOS: + num_reserved_conf_bits = 0; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of LUT(name: %s)\n", + __FILE__, __LINE__, cur_spice_model->name); + exit(1); + } + + /* Free */ + my_free(sram_ports); + + return num_reserved_conf_bits; +} + +/* For a multiplexer, determine its reserved configuration bits */ +int count_num_reserved_conf_bits_one_mux_spice_model(t_spice_model* cur_spice_model, + enum e_sram_orgz cur_sram_orgz_type, + int mux_size) { + int num_reserved_conf_bits = 0; + + /* Check */ + assert(SPICE_MODEL_MUX == cur_spice_model->type); + assert((2 == mux_size)||(2 < mux_size)); + + /* Number of configuration bits depends on the MUX structure */ + switch (cur_spice_model->design_tech_info.structure) { + case SPICE_MODEL_STRUCTURE_TREE: + num_reserved_conf_bits = 2; + break; + case SPICE_MODEL_STRUCTURE_ONELEVEL: + num_reserved_conf_bits = mux_size; + break; + case SPICE_MODEL_STRUCTURE_MULTILEVEL: + num_reserved_conf_bits = cur_spice_model->design_tech_info.mux_num_level * + determine_num_input_basis_multilevel_mux(mux_size, + cur_spice_model->design_tech_info.mux_num_level); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n", + __FILE__, __LINE__, cur_spice_model->name); + exit(1); + } + /* For 2:1 MUX, whatever structure, there is only one level */ + if (2 == mux_size) { + num_reserved_conf_bits = 2; + } + /* Also the number of configuration bits depends on the technology*/ + switch (cur_spice_model->design_tech) { + case SPICE_MODEL_DESIGN_RRAM: + switch (cur_sram_orgz_type) { + case SPICE_SRAM_MEMORY_BANK: + /* In memory bank, by intensively share the Bit/Word Lines, + * we only need 1 additional BL and WL for each MUX level. + */ + /* For 2:1 MUX, whatever structure, there is only one level */ + if (2 == mux_size) { + num_reserved_conf_bits = 2; + } + break; + case SPICE_SRAM_SCAN_CHAIN: + case SPICE_SRAM_STANDALONE: + /* 4T1R MUX requires more configuration bits */ + if (SPICE_MODEL_STRUCTURE_TREE == cur_spice_model->design_tech_info.structure) { + /* For tree-structure: we need 3 times more config. bits */ + num_reserved_conf_bits = 0; + } else if (SPICE_MODEL_STRUCTURE_MULTILEVEL == cur_spice_model->design_tech_info.structure) { + /* For multi-level structure: we need 1 more config. bits for each level */ + num_reserved_conf_bits = 0; + } else { + num_reserved_conf_bits = 0; + } + /* For 2:1 MUX, whatever structure, there is only one level */ + if (2 == mux_size) { + num_reserved_conf_bits = 0; + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid type of SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } + break; + case SPICE_MODEL_DESIGN_CMOS: + num_reserved_conf_bits = 0; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of MUX(name: %s)\n", + __FILE__, __LINE__, cur_spice_model->name); + exit(1); + } + + return num_reserved_conf_bits; +} + +/* For a non-volatile SRAM, we determine its number of reserved conf. bits */ +int count_num_reserved_conf_bits_one_rram_sram_spice_model(t_spice_model* cur_spice_model, + enum e_sram_orgz cur_sram_orgz_type) { + int num_reserved_conf_bits = 0; + int num_bl_ports, num_wl_ports; + t_spice_model_port** bl_ports = NULL; + t_spice_model_port** wl_ports = NULL; + + /* Check */ + assert(SPICE_MODEL_SRAM == cur_spice_model->type); + + switch (cur_sram_orgz_type) { + case SPICE_SRAM_MEMORY_BANK: + find_bl_wl_ports_spice_model(cur_spice_model, + &num_bl_ports, &bl_ports, + &num_wl_ports, &wl_ports); + assert((1 == num_bl_ports)&&(1 == num_wl_ports)); + assert(bl_ports[0]->size == wl_ports[0]->size); + num_reserved_conf_bits = bl_ports[0]->size - 1; /*TODO: to be more smart: num_bl-1 of SRAM model ?*/ + break; + case SPICE_SRAM_SCAN_CHAIN: + case SPICE_SRAM_STANDALONE: + num_reserved_conf_bits = 0; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid type of SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Free */ + my_free(bl_ports); + my_free(wl_ports); + + return num_reserved_conf_bits; +} + +int count_num_reserved_conf_bits_one_spice_model(t_spice_model* cur_spice_model, + enum e_sram_orgz cur_sram_orgz_type, + int mux_size) { + int num_reserved_conf_bits = 0; + int temp_num_reserved_conf_bits = 0; + int iport; + int num_sram_port = 0; + t_spice_model_port** sram_ports = NULL; + + assert(NULL != cur_spice_model); + + /* Only LUT and MUX requires configuration bits*/ + switch (cur_spice_model->type) { + case SPICE_MODEL_LUT: + num_reserved_conf_bits = + count_num_reserved_conf_bits_one_lut_spice_model(cur_spice_model, + cur_sram_orgz_type); + break; + case SPICE_MODEL_MUX: + num_reserved_conf_bits = + count_num_reserved_conf_bits_one_mux_spice_model(cur_spice_model, + cur_sram_orgz_type, + mux_size); + break; + case SPICE_MODEL_WIRE: + case SPICE_MODEL_FF: + case SPICE_MODEL_SRAM: + case SPICE_MODEL_HARDLOGIC: + case SPICE_MODEL_SCFF: + case SPICE_MODEL_VDD: + case SPICE_MODEL_GND: + case SPICE_MODEL_IOPAD: + /* Other block, we just count the number SRAM ports defined by user */ + num_reserved_conf_bits = 0; + sram_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); + /* TODO: could be more smart! + * Support Non-volatile RRAM-based SRAM */ + if (0 < num_sram_port) { + assert(NULL != sram_ports); + for (iport = 0; iport < num_sram_port; iport++) { + assert(NULL != sram_ports[iport]->spice_model); + /* TODO: could be more smart! + * Support Non-volatile RRAM-based SRAM */ + switch (sram_ports[iport]->spice_model->design_tech) { + case SPICE_MODEL_DESIGN_RRAM: + /* Non-volatile SRAM requires 2 BLs and 2 WLs for each 1 memory bit, + * Number of memory bits is still same as CMOS SRAM + */ + temp_num_reserved_conf_bits = + count_num_reserved_conf_bits_one_rram_sram_spice_model(sram_ports[iport]->spice_model, + cur_sram_orgz_type); + if (temp_num_reserved_conf_bits > num_reserved_conf_bits) { + num_reserved_conf_bits = temp_num_reserved_conf_bits; + } + break; + case SPICE_MODEL_DESIGN_CMOS: + num_reserved_conf_bits = 0; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of LUT(name: %s)\n", + __FILE__, __LINE__, cur_spice_model->name); + exit(1); + } + } + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid spice_model_type!\n", __FILE__, __LINE__); + exit(1); + } + + /* Free */ + my_free(sram_ports); + + return num_reserved_conf_bits; +} + + + +/* Count the number of configuration bits of a spice model */ +int count_num_conf_bits_one_spice_model(t_spice_model* cur_spice_model, + enum e_sram_orgz cur_sram_orgz_type, + int mux_size) { + int num_conf_bits = 0; + int iport; + int lut_size; + int num_input_port = 0; + t_spice_model_port** input_ports = NULL; + int num_output_port = 0; + t_spice_model_port** output_ports = NULL; + int num_sram_port = 0; + t_spice_model_port** sram_ports = NULL; + + assert(NULL != cur_spice_model); + + /* Only LUT and MUX requires configuration bits*/ + switch (cur_spice_model->type) { + case SPICE_MODEL_LUT: + /* Determine size of LUT*/ + input_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + output_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + sram_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); + assert(1 == num_input_port); + assert(1 == num_output_port); + assert(1 == num_sram_port); + lut_size = input_ports[0]->size; + num_conf_bits = (int)pow(2.,(double)(lut_size)); + assert(num_conf_bits == sram_ports[0]->size); + assert(1 == output_ports[0]->size); + /* TODO: could be more smart! Use mapped spice_model of SRAM ports! + * Support Non-volatile RRAM-based SRAM */ + switch (sram_ports[0]->spice_model->design_tech) { + case SPICE_MODEL_DESIGN_RRAM: + /* Non-volatile SRAM requires 2 BLs and 2 WLs for each 1 memory bit, + * In memory bank, by intensively share the Bit/Word Lines, + * we only need 1 additional BL and WL for each memory bit. + * Number of memory bits is still same as CMOS SRAM + */ + switch (cur_sram_orgz_type) { + case SPICE_SRAM_MEMORY_BANK: + break; + case SPICE_SRAM_SCAN_CHAIN: + case SPICE_SRAM_STANDALONE: + num_conf_bits = 2 * num_conf_bits; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid type of SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } + break; + case SPICE_MODEL_DESIGN_CMOS: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of LUT(name: %s)\n", + __FILE__, __LINE__, cur_spice_model->name); + exit(1); + } + break; + case SPICE_MODEL_MUX: + assert((2 == mux_size)||(2 < mux_size)); + /* Number of configuration bits depends on the MUX structure */ + switch (cur_spice_model->design_tech_info.structure) { + case SPICE_MODEL_STRUCTURE_TREE: + num_conf_bits = determine_tree_mux_level(mux_size); + break; + case SPICE_MODEL_STRUCTURE_ONELEVEL: + num_conf_bits = mux_size; + break; + case SPICE_MODEL_STRUCTURE_MULTILEVEL: + num_conf_bits = cur_spice_model->design_tech_info.mux_num_level + * determine_num_input_basis_multilevel_mux(mux_size, + cur_spice_model->design_tech_info.mux_num_level); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n", + __FILE__, __LINE__, cur_spice_model->name); + exit(1); + } + /* For 2:1 MUX, whatever structure, there is only one level */ + if (2 == mux_size) { + num_conf_bits = 1; + } + /* Also the number of configuration bits depends on the technology*/ + switch (cur_spice_model->design_tech) { + case SPICE_MODEL_DESIGN_RRAM: + switch (cur_sram_orgz_type) { + case SPICE_SRAM_MEMORY_BANK: + /* In memory bank, by intensively share the Bit/Word Lines, + * we only need 1 additional BL and WL for each MUX level. + */ + num_conf_bits = cur_spice_model->design_tech_info.mux_num_level; + /* For 2:1 MUX, whatever structure, there is only one level */ + if (2 == mux_size) { + num_conf_bits = 1; + } + break; + case SPICE_SRAM_SCAN_CHAIN: + case SPICE_SRAM_STANDALONE: + /* Currently we keep the same as CMOS MUX */ + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid type of SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } + break; + case SPICE_MODEL_DESIGN_CMOS: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of MUX(name: %s)\n", + __FILE__, __LINE__, cur_spice_model->name); + exit(1); + } + break; + case SPICE_MODEL_WIRE: + case SPICE_MODEL_FF: + case SPICE_MODEL_SRAM: + case SPICE_MODEL_HARDLOGIC: + case SPICE_MODEL_SCFF: + case SPICE_MODEL_VDD: + case SPICE_MODEL_GND: + case SPICE_MODEL_IOPAD: + /* Other block, we just count the number SRAM ports defined by user */ + num_conf_bits = 0; + sram_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); + /* TODO: could be more smart! + * Support Non-volatile RRAM-based SRAM */ + if (0 < num_sram_port) { + assert(NULL != sram_ports); + for (iport = 0; iport < num_sram_port; iport++) { + assert(NULL != sram_ports[iport]->spice_model); + /* TODO: could be more smart! + * Support Non-volatile RRAM-based SRAM */ + switch (sram_ports[iport]->spice_model->design_tech) { + case SPICE_MODEL_DESIGN_RRAM: + /* Non-volatile SRAM requires 2 BLs and 2 WLs for each 1 memory bit, + * Number of memory bits is still same as CMOS SRAM + */ + switch (cur_sram_orgz_type) { + case SPICE_SRAM_MEMORY_BANK: + num_conf_bits += sram_ports[iport]->size; + break; + case SPICE_SRAM_SCAN_CHAIN: + case SPICE_SRAM_STANDALONE: + num_conf_bits += sram_ports[iport]->size; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid type of SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } + break; + case SPICE_MODEL_DESIGN_CMOS: + /* Non-volatile SRAM requires 2 BLs and 2 WLs for each 1 memory bit, + * Number of memory bits is still same as CMOS SRAM + */ + switch (cur_sram_orgz_type) { + case SPICE_SRAM_MEMORY_BANK: + num_conf_bits += sram_ports[iport]->size; + break; + case SPICE_SRAM_SCAN_CHAIN: + case SPICE_SRAM_STANDALONE: + num_conf_bits += sram_ports[iport]->size; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid type of SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } + + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of LUT(name: %s)\n", + __FILE__, __LINE__, cur_spice_model->name); + exit(1); + } + } + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid spice_model_type!\n", __FILE__, __LINE__); + exit(1); + } + + /* Free */ + my_free(input_ports); + my_free(output_ports); + my_free(sram_ports); + + return num_conf_bits; +} + +int count_num_reserved_conf_bit_one_interc(t_interconnect* cur_interc, + enum e_sram_orgz cur_sram_orgz_type) { + int fan_in = 0; + enum e_interconnect spice_interc_type = DIRECT_INTERC; + + int num_reserved_conf_bits = 0; + int temp_num_reserved_conf_bits = 0; + + /* 1. identify pin interconnection type, + * 2. Identify the number of fan-in (Consider interconnection edges of only selected mode) + * 3. Select and print the SPICE netlist + */ + if (NULL == cur_interc) { + return num_reserved_conf_bits; + } else { + fan_in = cur_interc->fan_in; + if (0 == fan_in) { + return num_reserved_conf_bits; + } + } + /* Initialize the interconnection type that will be implemented in SPICE netlist*/ + switch (cur_interc->type) { + case DIRECT_INTERC: + assert(cur_interc->fan_out == fan_in); + spice_interc_type = DIRECT_INTERC; + break; + case COMPLETE_INTERC: + if (1 == fan_in) { + spice_interc_type = DIRECT_INTERC; + } else { + assert((2 == fan_in)||(2 < fan_in)); + spice_interc_type = MUX_INTERC; + } + break; + case MUX_INTERC: + assert((2 == fan_in)||(2 < fan_in)); + spice_interc_type = MUX_INTERC; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid interconnection type for %s (Arch[LINE%d])!\n", + __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); + exit(1); + } + /* This time, (2nd round), count the number of configuration bits, according to interc type*/ + switch (spice_interc_type) { + case DIRECT_INTERC: + /* Check : + * 1. Direct interc has only one fan-in! + */ + assert((cur_interc->fan_out == fan_in) + ||((COMPLETE_INTERC == cur_interc->type)&&(1 == fan_in))); + break; + case COMPLETE_INTERC: + case MUX_INTERC: + /* Check : + * MUX should have at least 2 fan_in + */ + assert((2 == fan_in)||(2 < fan_in)); + assert((1 == cur_interc->fan_out)||(1 < cur_interc->fan_out)); + /* 2. spice_model is a wire */ + assert(NULL != cur_interc->spice_model); + assert(SPICE_MODEL_MUX == cur_interc->spice_model->type); + temp_num_reserved_conf_bits = count_num_reserved_conf_bits_one_spice_model(cur_interc->spice_model, + cur_sram_orgz_type, fan_in); + /* FOR COMPLETE_INTERC: we should consider fan_out number ! */ + if (temp_num_reserved_conf_bits > num_reserved_conf_bits) { + num_reserved_conf_bits = temp_num_reserved_conf_bits; + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid interconnection type for %s (Arch[LINE%d])!\n", + __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); + exit(1); + } + return num_reserved_conf_bits; +} + + +int count_num_conf_bit_one_interc(t_interconnect* cur_interc, + enum e_sram_orgz cur_sram_orgz_type) { + int fan_in = 0; + enum e_interconnect spice_interc_type = DIRECT_INTERC; + + int num_conf_bits = 0; + + /* 1. identify pin interconnection type, + * 2. Identify the number of fan-in (Consider interconnection edges of only selected mode) + * 3. Select and print the SPICE netlist + */ + if (NULL == cur_interc) { + return num_conf_bits; + } else { + fan_in = cur_interc->fan_in; + if (0 == fan_in) { + return num_conf_bits; + } + } + /* Initialize the interconnection type that will be implemented in SPICE netlist*/ + switch (cur_interc->type) { + case DIRECT_INTERC: + assert(cur_interc->fan_out == fan_in); + spice_interc_type = DIRECT_INTERC; + break; + case COMPLETE_INTERC: + if (1 == fan_in) { + spice_interc_type = DIRECT_INTERC; + } else { + assert((2 == fan_in)||(2 < fan_in)); + spice_interc_type = MUX_INTERC; + } + break; + case MUX_INTERC: + assert((2 == fan_in)||(2 < fan_in)); + spice_interc_type = MUX_INTERC; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid interconnection type for %s (Arch[LINE%d])!\n", + __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); + exit(1); + } + /* This time, (2nd round), count the number of configuration bits, according to interc type*/ + switch (spice_interc_type) { + case DIRECT_INTERC: + /* Check : + * 1. Direct interc has only one fan-in! + */ + assert((cur_interc->fan_out == fan_in) + ||((COMPLETE_INTERC == cur_interc->type)&&(1 == fan_in))); + break; + case COMPLETE_INTERC: + case MUX_INTERC: + /* Check : + * MUX should have at least 2 fan_in + */ + assert((2 == fan_in)||(2 < fan_in)); + assert((1 == cur_interc->fan_out)||(1 < cur_interc->fan_out)); + /* 2. spice_model is a wire */ + assert(NULL != cur_interc->spice_model); + assert(SPICE_MODEL_MUX == cur_interc->spice_model->type); + num_conf_bits = count_num_conf_bits_one_spice_model(cur_interc->spice_model, + cur_sram_orgz_type, fan_in); + /* FOR COMPLETE_INTERC: we should consider fan_out number ! */ + num_conf_bits = num_conf_bits * cur_interc->fan_out; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid interconnection type for %s (Arch[LINE%d])!\n", + __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); + exit(1); + } + return num_conf_bits; +} + +/* Count the number of configuration bits of interconnection inside a pb_type in its default mode */ +int count_num_conf_bits_pb_type_mode_interc(t_mode* cur_pb_type_mode, + enum e_sram_orgz cur_sram_orgz_type) { + int num_conf_bits = 0; + int jinterc = 0; + + for (jinterc = 0; jinterc < cur_pb_type_mode->num_interconnect; jinterc++) { + num_conf_bits += count_num_conf_bit_one_interc(&(cur_pb_type_mode->interconnect[jinterc]), + cur_sram_orgz_type); + } + + return num_conf_bits; +} + +/* Count the number of configuration bits of interconnection inside a pb_type in its default mode */ +int count_num_reserved_conf_bits_pb_type_mode_interc(t_mode* cur_pb_type_mode, + enum e_sram_orgz cur_sram_orgz_type) { + int num_reserved_conf_bits = 0; + int temp_num_reserved_conf_bits = 0; + int jinterc = 0; + + for (jinterc = 0; jinterc < cur_pb_type_mode->num_interconnect; jinterc++) { + /* num of reserved configuration bits is determined by the largest one */ + temp_num_reserved_conf_bits = + count_num_reserved_conf_bit_one_interc(&(cur_pb_type_mode->interconnect[jinterc]), + cur_sram_orgz_type); + if (temp_num_reserved_conf_bits > num_reserved_conf_bits) { + num_reserved_conf_bits = temp_num_reserved_conf_bits; + } + } + + return num_reserved_conf_bits; +} + +/* Count the number of configuration bits of a grid (type_descriptor) in default mode */ +int rec_count_num_conf_bits_pb_type_default_mode(t_pb_type* cur_pb_type, + t_sram_orgz_info* cur_sram_orgz_info) { + int mode_index, ipb, jpb; + int sum_num_conf_bits = 0; + int num_reserved_conf_bits = 0; + int temp_num_reserved_conf_bits = 0; + + cur_pb_type->default_mode_num_conf_bits = 0; + + /* Recursively finish all the child pb_types*/ + if (NULL == cur_pb_type->spice_model) { + /* Find the mode that define_idle_mode*/ + mode_index = find_pb_type_idle_mode_index((*cur_pb_type)); + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + rec_count_num_conf_bits_pb_type_default_mode(&(cur_pb_type->modes[mode_index].pb_type_children[ipb]), cur_sram_orgz_info); + } + } + } + + /* Check if this has defined a spice_model*/ + if (NULL != cur_pb_type->spice_model) { + sum_num_conf_bits = count_num_conf_bits_one_spice_model(cur_pb_type->spice_model, cur_sram_orgz_info->type, 0); + cur_pb_type->default_mode_num_conf_bits = sum_num_conf_bits; + /* calculate the number of reserved configuration bits */ + cur_pb_type->default_mode_num_reserved_conf_bits = + count_num_reserved_conf_bits_one_spice_model(cur_pb_type->spice_model, + cur_sram_orgz_info->type, 0); + } else { /* Count the sum of configuration bits of all the children pb_types */ + /* Find the mode that define_idle_mode*/ + mode_index = find_pb_type_idle_mode_index((*cur_pb_type)); + /* Quote all child pb_types */ + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + /* Each child may exist multiple times in the hierarchy*/ + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Count in the number of configuration bits of on child pb_type */ + sum_num_conf_bits += cur_pb_type->modes[mode_index].pb_type_children[ipb].default_mode_num_conf_bits; + temp_num_reserved_conf_bits = + cur_pb_type->modes[mode_index].pb_type_children[ipb].default_mode_num_reserved_conf_bits; + /* number of reserved conf. bits is deteremined by the largest number of reserved conf. bits !*/ + if (temp_num_reserved_conf_bits > num_reserved_conf_bits) { + num_reserved_conf_bits = temp_num_reserved_conf_bits; + } + } + } + /* Count the number of configuration bits of interconnection */ + sum_num_conf_bits += count_num_conf_bits_pb_type_mode_interc(&(cur_pb_type->modes[mode_index]), cur_sram_orgz_info->type); + /* Count the number of reserved_configuration bits of interconnection */ + temp_num_reserved_conf_bits = + count_num_reserved_conf_bits_pb_type_mode_interc(&(cur_pb_type->modes[mode_index]), + cur_sram_orgz_info->type); + /* number of reserved conf. bits is deteremined by the largest number of reserved conf. bits !*/ + if (temp_num_reserved_conf_bits > num_reserved_conf_bits) { + num_reserved_conf_bits = temp_num_reserved_conf_bits; + } + /* Update the info in pb_type */ + cur_pb_type->default_mode_num_reserved_conf_bits = num_reserved_conf_bits; + cur_pb_type->default_mode_num_conf_bits = sum_num_conf_bits; + } + + return sum_num_conf_bits; +} + +/* Count the number of configuration bits of a grid (type_descriptor) in default mode */ +int rec_count_num_conf_bits_pb_type_physical_mode(t_pb_type* cur_pb_type, + t_sram_orgz_info* cur_sram_orgz_info) { + int mode_index, ipb, jpb; + int sum_num_conf_bits = 0; + int num_reserved_conf_bits = 0; + int temp_num_reserved_conf_bits = 0; + + cur_pb_type->physical_mode_num_conf_bits = 0; + + /* Recursively finish all the child pb_types*/ + if (NULL == cur_pb_type->spice_model) { + /* Find the mode that define_idle_mode*/ + mode_index = find_pb_type_physical_mode_index((*cur_pb_type)); + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + rec_count_num_conf_bits_pb_type_physical_mode(&(cur_pb_type->modes[mode_index].pb_type_children[ipb]), cur_sram_orgz_info); + } + } + } + + /* Check if this has defined a spice_model*/ + if (NULL != cur_pb_type->spice_model) { + sum_num_conf_bits = count_num_conf_bits_one_spice_model(cur_pb_type->spice_model, cur_sram_orgz_info->type, 0); + cur_pb_type->physical_mode_num_conf_bits = sum_num_conf_bits; + /* calculate the number of reserved configuration bits */ + cur_pb_type->physical_mode_num_reserved_conf_bits = + count_num_reserved_conf_bits_one_spice_model(cur_pb_type->spice_model, + cur_sram_orgz_info->type, 0); + } else { /* Count the sum of configuration bits of all the children pb_types */ + /* Find the mode that define_idle_mode*/ + mode_index = find_pb_type_physical_mode_index((*cur_pb_type)); + /* Quote all child pb_types */ + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + /* Each child may exist multiple times in the hierarchy*/ + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Count in the number of configuration bits of on child pb_type */ + sum_num_conf_bits += cur_pb_type->modes[mode_index].pb_type_children[ipb].physical_mode_num_conf_bits; + temp_num_reserved_conf_bits = cur_pb_type->modes[mode_index].pb_type_children[ipb].physical_mode_num_reserved_conf_bits; + + /* number of reserved conf. bits is deteremined by the largest number of reserved conf. bits !*/ + if (temp_num_reserved_conf_bits > num_reserved_conf_bits) { + num_reserved_conf_bits = temp_num_reserved_conf_bits; + } + } + } + /* Count the number of configuration bits of interconnection */ + sum_num_conf_bits += count_num_conf_bits_pb_type_mode_interc(&(cur_pb_type->modes[mode_index]), + cur_sram_orgz_info->type); + /* Count the number of reserved_configuration bits of interconnection */ + temp_num_reserved_conf_bits = + count_num_reserved_conf_bits_pb_type_mode_interc(&(cur_pb_type->modes[mode_index]), + cur_sram_orgz_info->type); + /* number of reserved conf. bits is deteremined by the largest number of reserved conf. bits !*/ + if (temp_num_reserved_conf_bits > num_reserved_conf_bits) { + num_reserved_conf_bits = temp_num_reserved_conf_bits; + } + /* Update the info in pb_type */ + cur_pb_type->physical_mode_num_reserved_conf_bits = num_reserved_conf_bits; + cur_pb_type->physical_mode_num_conf_bits = sum_num_conf_bits; + } + + return sum_num_conf_bits; +} + + +/* Count the number of configuration bits of a pb_graph_node */ +int rec_count_num_conf_bits_pb(t_pb* cur_pb, + t_sram_orgz_info* cur_sram_orgz_info) { + int mode_index, ipb, jpb; + t_pb_type* cur_pb_type = NULL; + t_pb_graph_node* cur_pb_graph_node = NULL; + int sum_num_conf_bits = 0; + int num_reserved_conf_bits = 0; + int temp_num_reserved_conf_bits = 0; + + /* Check cur_pb_graph_node*/ + if (NULL == cur_pb) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb.\n", + __FILE__, __LINE__); + exit(1); + } + cur_pb_graph_node = cur_pb->pb_graph_node; + cur_pb_type = cur_pb_graph_node->pb_type; + mode_index = cur_pb->mode; + + cur_pb->num_conf_bits = 0; + + /* Recursively finish all the child pb_types*/ + if (NULL == cur_pb_type->spice_model) { + /* recursive for the child_pbs*/ + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Recursive*/ + /* Refer to pack/output_clustering.c [LINE 392] */ + if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { + rec_count_num_conf_bits_pb(&(cur_pb->child_pbs[ipb][jpb]), cur_sram_orgz_info); + } else { + /* Check if this pb has no children, no children mean idle*/ + rec_count_num_conf_bits_pb_type_default_mode(cur_pb->child_pbs[ipb][jpb].pb_graph_node->pb_type, + cur_sram_orgz_info); + } + } + } + } + + /* Check if this has defined a spice_model*/ + if (NULL != cur_pb_type->spice_model) { + sum_num_conf_bits += count_num_conf_bits_one_spice_model(cur_pb_type->spice_model, + cur_sram_orgz_info->type, 0); + cur_pb->num_conf_bits = sum_num_conf_bits; + /* calculate the number of reserved configuration bits */ + cur_pb->num_reserved_conf_bits = + count_num_reserved_conf_bits_one_spice_model(cur_pb_type->spice_model, + cur_sram_orgz_info->type, 0); + + } else { + /* Definition ends*/ + /* Quote all child pb_types */ + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + /* Each child may exist multiple times in the hierarchy*/ + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* we should make sure this placement index == child_pb_type[jpb]*/ + assert(jpb == cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb].placement_index); + if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { + /* Count in the number of configuration bits of on child pb */ + sum_num_conf_bits += cur_pb->child_pbs[ipb][jpb].num_conf_bits; + temp_num_reserved_conf_bits = cur_pb->child_pbs[ipb][jpb].num_reserved_conf_bits; + } else { + /* Count in the number of configuration bits of on child pb_type */ + sum_num_conf_bits += cur_pb_type->modes[mode_index].pb_type_children[ipb].default_mode_num_conf_bits; + temp_num_reserved_conf_bits = + cur_pb_type->modes[mode_index].pb_type_children[ipb].default_mode_num_reserved_conf_bits; + } + /* number of reserved conf. bits is deteremined by the largest number of reserved conf. bits !*/ + if (temp_num_reserved_conf_bits > num_reserved_conf_bits) { + num_reserved_conf_bits = temp_num_reserved_conf_bits; + } + } + } + /* Count the number of configuration bits of interconnection */ + sum_num_conf_bits += count_num_conf_bits_pb_type_mode_interc(&(cur_pb_type->modes[mode_index]), + cur_sram_orgz_info->type); + /* Count the number of reserved_configuration bits of interconnection */ + temp_num_reserved_conf_bits = + count_num_reserved_conf_bits_pb_type_mode_interc(&(cur_pb_type->modes[mode_index]), + cur_sram_orgz_info->type); + /* number of reserved conf. bits is deteremined by the largest number of reserved conf. bits !*/ + if (temp_num_reserved_conf_bits > num_reserved_conf_bits) { + num_reserved_conf_bits = temp_num_reserved_conf_bits; + } + /* Update the info in pb_type */ + cur_pb->num_reserved_conf_bits = num_reserved_conf_bits; + cur_pb->num_conf_bits = sum_num_conf_bits; + } + + return sum_num_conf_bits; +} + +/* Initialize the number of configuraion bits for one grid */ +void init_one_grid_num_conf_bits(int ix, int iy, + t_sram_orgz_info* cur_sram_orgz_info) { + t_block* mapped_block = NULL; + int iz; + int cur_block_index = 0; + int capacity; + + /* Check */ + assert((!(0 > ix))&&(!(ix > (nx + 1)))); + assert((!(0 > iy))&&(!(iy > (ny + 1)))); + + if ((NULL == grid[ix][iy].type)||(0 != grid[ix][iy].offset)) { + /* Empty grid, directly return */ + return; + } + capacity= grid[ix][iy].type->capacity; + assert(0 < capacity); + + /* check capacity and if this has been mapped */ + for (iz = 0; iz < capacity; iz++) { + /* Check in all the blocks(clustered logic block), there is a match x,y,z*/ + mapped_block = search_mapped_block(ix, iy, iz); + rec_count_num_conf_bits_pb_type_physical_mode(grid[ix][iy].type->pb_type, cur_sram_orgz_info); + /* Comments: Grid [x][y]*/ + if (NULL == mapped_block) { + /* Print a consider a idle pb_type ...*/ + rec_count_num_conf_bits_pb_type_default_mode(grid[ix][iy].type->pb_type, cur_sram_orgz_info); + } else { + if (iz == mapped_block->z) { + // assert(mapped_block == &(block[grid[ix][iy].blocks[cur_block_index]])); + cur_block_index++; + } + rec_count_num_conf_bits_pb(mapped_block->pb, cur_sram_orgz_info); + } + } + + assert(cur_block_index == grid[ix][iy].usage); + + return; +} + +/* Initialize the number of configuraion bits for all grids */ +void init_grids_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info) { + int ix, iy; + + /* Core grid */ + vpr_printf(TIO_MESSAGE_INFO, "INFO: Initializing number of configuration bits of Core grids...\n"); + for (ix = 1; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + init_one_grid_num_conf_bits(ix, iy, cur_sram_orgz_info); + } + } + + /* Consider the IO pads */ + vpr_printf(TIO_MESSAGE_INFO, "INFO: Initializing number of configuration bits of I/O grids...\n"); + /* Left side: x = 0, y = 1 .. ny*/ + ix = 0; + for (iy = 1; iy < (ny + 1); iy++) { + /* Ensure this is a io */ + assert(IO_TYPE == grid[ix][iy].type); + init_one_grid_num_conf_bits(ix, iy, cur_sram_orgz_info); + } + /* Right side : x = nx + 1, y = 1 .. ny*/ + ix = nx + 1; + for (iy = 1; iy < (ny + 1); iy++) { + /* Ensure this is a io */ + assert(IO_TYPE == grid[ix][iy].type); + init_one_grid_num_conf_bits(ix, iy, cur_sram_orgz_info); + } + /* Bottom side : x = 1 .. nx + 1, y = 0 */ + iy = 0; + for (ix = 1; ix < (nx + 1); ix++) { + /* Ensure this is a io */ + assert(IO_TYPE == grid[ix][iy].type); + init_one_grid_num_conf_bits(ix, iy, cur_sram_orgz_info); + } + /* Top side : x = 1 .. nx + 1, y = nx + 1 */ + iy = ny + 1; + for (ix = 1; ix < (nx + 1); ix++) { + /* Ensure this is a io */ + assert(IO_TYPE == grid[ix][iy].type); + init_one_grid_num_conf_bits(ix, iy, cur_sram_orgz_info); + } + + return; +} + +/* Reset the counter of each spice_model to be zero */ +void zero_spice_models_cnt(int num_spice_models, t_spice_model* spice_model) { + int imodel = 0; + + for (imodel = 0; imodel < num_spice_models; imodel++) { + spice_model[imodel].cnt = 0; + } + + return; +} + +void zero_one_spice_model_routing_index_low_high(t_spice_model* cur_spice_model) { + int ix, iy; + /* Initialize */ + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 0; iy < (ny + 1); iy++) { + cur_spice_model->sb_index_low[ix][iy] = 0; + cur_spice_model->cbx_index_low[ix][iy] = 0; + cur_spice_model->cby_index_low[ix][iy] = 0; + cur_spice_model->sb_index_high[ix][iy] = 0; + cur_spice_model->cbx_index_high[ix][iy] = 0; + cur_spice_model->cby_index_high[ix][iy] = 0; + } + } + return; +} + +void zero_spice_models_routing_index_low_high(int num_spice_models, + t_spice_model* spice_model) { + int i; + + for (i = 0; i < num_spice_models; i++) { + zero_one_spice_model_routing_index_low_high(&(spice_model[i])); + } + + return; +} + +/* Malloc routing_index_low and routing_index_high for a spice_model */ +void alloc_spice_model_routing_index_low_high(t_spice_model* cur_spice_model) { + int ix; + + /* [cbx|cby|sb]_index_low */ + /* x - direction*/ + cur_spice_model->sb_index_low = (int**)my_malloc(sizeof(int*)*(nx + 1)); + cur_spice_model->cbx_index_low = (int**)my_malloc(sizeof(int*)*(nx + 1)); + cur_spice_model->cby_index_low = (int**)my_malloc(sizeof(int*)*(nx + 1)); + /* y - direction*/ + for (ix = 0; ix < (nx + 1); ix++) { + cur_spice_model->sb_index_low[ix] = (int*)my_malloc(sizeof(int)*(ny + 1)); + cur_spice_model->cbx_index_low[ix] = (int*)my_malloc(sizeof(int)*(ny + 1)); + cur_spice_model->cby_index_low[ix] = (int*)my_malloc(sizeof(int)*(ny + 1)); + } + + /* grid_index_high */ + /* x - direction*/ + cur_spice_model->sb_index_high = (int**)my_malloc(sizeof(int*)*(nx + 1)); + cur_spice_model->cbx_index_high = (int**)my_malloc(sizeof(int*)*(nx + 1)); + cur_spice_model->cby_index_high = (int**)my_malloc(sizeof(int*)*(nx + 1)); + /* y - direction*/ + for (ix = 0; ix < (nx + 1); ix++) { + cur_spice_model->sb_index_high[ix] = (int*)my_malloc(sizeof(int)*(ny + 1)); + cur_spice_model->cbx_index_high[ix] = (int*)my_malloc(sizeof(int)*(ny + 1)); + cur_spice_model->cby_index_high[ix] = (int*)my_malloc(sizeof(int)*(ny + 1)); + } + + zero_one_spice_model_routing_index_low_high(cur_spice_model); + + return; +} + +void free_one_spice_model_routing_index_low_high(t_spice_model* cur_spice_model) { + int ix; + + /* index_high */ + for (ix = 0; ix < (nx + 1); ix++) { + my_free(cur_spice_model->sb_index_low[ix]); + my_free(cur_spice_model->cbx_index_low[ix]); + my_free(cur_spice_model->cby_index_low[ix]); + + my_free(cur_spice_model->sb_index_high[ix]); + my_free(cur_spice_model->cbx_index_high[ix]); + my_free(cur_spice_model->cby_index_high[ix]); + } + my_free(cur_spice_model->sb_index_low); + my_free(cur_spice_model->cbx_index_low); + my_free(cur_spice_model->cby_index_low); + + my_free(cur_spice_model->sb_index_high); + my_free(cur_spice_model->cbx_index_high); + my_free(cur_spice_model->cby_index_high); + + return; +} + +void free_spice_model_routing_index_low_high(int num_spice_models, + t_spice_model* spice_model) { + int i; + + for (i = 0; i < num_spice_models; i++) { + free_one_spice_model_routing_index_low_high(&(spice_model[i])); + } + + return; +} + +void update_one_spice_model_routing_index_high(int x, int y, t_rr_type chan_type, + t_spice_model* cur_spice_model) { + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + assert(NULL != cur_spice_model); + assert(NULL != cur_spice_model->sb_index_high); + assert(NULL != cur_spice_model->sb_index_high[x]); + assert(NULL != cur_spice_model->cbx_index_high); + assert(NULL != cur_spice_model->cbx_index_high[x]); + assert(NULL != cur_spice_model->cby_index_high); + assert(NULL != cur_spice_model->cby_index_high[x]); + + /* Assigne the low */ + if (CHANX == chan_type) { + cur_spice_model->cbx_index_high[x][y] = cur_spice_model->cnt; + } else if (CHANY == chan_type) { + cur_spice_model->cby_index_high[x][y] = cur_spice_model->cnt; + } else if (SOURCE == chan_type) { + cur_spice_model->sb_index_high[x][y] = cur_spice_model->cnt; + } + + return; +} + +void update_spice_models_routing_index_high(int x, int y, t_rr_type chan_type, + int num_spice_models, + t_spice_model* spice_model) { + int i; + + for (i = 0; i < num_spice_models; i++) { + update_one_spice_model_routing_index_high(x, y, chan_type, &(spice_model[i])); + } + + return; +} + +void update_one_spice_model_routing_index_low(int x, int y, t_rr_type chan_type, + t_spice_model* cur_spice_model) { + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + assert(NULL != cur_spice_model); + assert(NULL != cur_spice_model->sb_index_low); + assert(NULL != cur_spice_model->sb_index_low[x]); + assert(NULL != cur_spice_model->cbx_index_low); + assert(NULL != cur_spice_model->cbx_index_low[x]); + assert(NULL != cur_spice_model->cby_index_low); + assert(NULL != cur_spice_model->cby_index_low[x]); + + /* Assigne the low */ + if (CHANX == chan_type) { + cur_spice_model->cbx_index_low[x][y] = cur_spice_model->cnt; + } else if (CHANY == chan_type) { + cur_spice_model->cby_index_low[x][y] = cur_spice_model->cnt; + } else if (SOURCE == chan_type) { + cur_spice_model->sb_index_low[x][y] = cur_spice_model->cnt; + } + + return; +} + +void update_spice_models_routing_index_low(int x, int y, t_rr_type chan_type, + int num_spice_models, + t_spice_model* spice_model) { + int i; + + for (i = 0; i < num_spice_models; i++) { + update_one_spice_model_routing_index_low(x, y, chan_type, &(spice_model[i])); + } + + return; +} + +/* Count the number of inpad and outpad of a grid (type_descriptor) in default mode */ +void rec_count_num_iopads_pb_type_physical_mode(t_pb_type* cur_pb_type) { + int mode_index, ipb, jpb; + int sum_num_iopads = 0; + + cur_pb_type->physical_mode_num_iopads = 0; + + /* Recursively finish all the child pb_types*/ + if (NULL == cur_pb_type->spice_model) { + /* Find the mode that define_idle_mode*/ + mode_index = find_pb_type_physical_mode_index((*cur_pb_type)); + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + rec_count_num_iopads_pb_type_physical_mode(&(cur_pb_type->modes[mode_index].pb_type_children[ipb])); + } + } + } + + /* Check if this has defined a spice_model*/ + if (NULL != cur_pb_type->spice_model) { + if (SPICE_MODEL_IOPAD == cur_pb_type->spice_model->type) { + sum_num_iopads = 1; + cur_pb_type->physical_mode_num_iopads = sum_num_iopads; + } + } else { /* Count the sum of configuration bits of all the children pb_types */ + /* Find the mode that define_idle_mode*/ + mode_index = find_pb_type_physical_mode_index((*cur_pb_type)); + /* Quote all child pb_types */ + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + /* Each child may exist multiple times in the hierarchy*/ + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Count in the number of configuration bits of on child pb_type */ + sum_num_iopads += cur_pb_type->modes[mode_index].pb_type_children[ipb].physical_mode_num_iopads; + } + } + /* Count the number of configuration bits of interconnection */ + /* Update the info in pb_type */ + cur_pb_type->physical_mode_num_iopads = sum_num_iopads; + } + + return; +} + +/* Count the number of inpad and outpad of a grid (type_descriptor) in default mode */ +void rec_count_num_iopads_pb_type_default_mode(t_pb_type* cur_pb_type) { + int mode_index, ipb, jpb; + int sum_num_iopads = 0; + + cur_pb_type->default_mode_num_iopads = 0; + + /* Recursively finish all the child pb_types*/ + if (NULL == cur_pb_type->spice_model) { + /* Find the mode that define_idle_mode*/ + mode_index = find_pb_type_idle_mode_index((*cur_pb_type)); + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + rec_count_num_iopads_pb_type_default_mode(&(cur_pb_type->modes[mode_index].pb_type_children[ipb])); + } + } + } + + /* Check if this has defined a spice_model*/ + if (NULL != cur_pb_type->spice_model) { + if (SPICE_MODEL_IOPAD == cur_pb_type->spice_model->type) { + sum_num_iopads = 1; + cur_pb_type->default_mode_num_iopads = sum_num_iopads; + } + } else { /* Count the sum of configuration bits of all the children pb_types */ + /* Find the mode that define_idle_mode*/ + mode_index = find_pb_type_idle_mode_index((*cur_pb_type)); + /* Quote all child pb_types */ + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + /* Each child may exist multiple times in the hierarchy*/ + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Count in the number of configuration bits of on child pb_type */ + sum_num_iopads += cur_pb_type->modes[mode_index].pb_type_children[ipb].default_mode_num_iopads; + } + } + /* Count the number of configuration bits of interconnection */ + /* Update the info in pb_type */ + cur_pb_type->default_mode_num_iopads = sum_num_iopads; + } + + return; +} + +/* Count the number of configuration bits of a pb_graph_node */ +void rec_count_num_iopads_pb(t_pb* cur_pb) { + int mode_index, ipb, jpb; + t_pb_type* cur_pb_type = NULL; + t_pb_graph_node* cur_pb_graph_node = NULL; + + int sum_num_iopads = 0; + + /* Check cur_pb_graph_node*/ + if (NULL == cur_pb) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb.\n", + __FILE__, __LINE__); + exit(1); + } + cur_pb_graph_node = cur_pb->pb_graph_node; + cur_pb_type = cur_pb_graph_node->pb_type; + mode_index = cur_pb->mode; + + cur_pb->num_iopads = 0; + + /* Recursively finish all the child pb_types*/ + if (NULL == cur_pb_type->spice_model) { + /* recursive for the child_pbs*/ + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Recursive*/ + /* Refer to pack/output_clustering.c [LINE 392] */ + if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { + rec_count_num_iopads_pb(&(cur_pb->child_pbs[ipb][jpb])); + } else { + /* Check if this pb has no children, no children mean idle*/ + rec_count_num_iopads_pb_type_default_mode(cur_pb->child_pbs[ipb][jpb].pb_graph_node->pb_type); + } + } + } + } + + /* Check if this has defined a spice_model*/ + if (NULL != cur_pb_type->spice_model) { + if (SPICE_MODEL_IOPAD == cur_pb_type->spice_model->type) { + sum_num_iopads = 1; + cur_pb->num_iopads = sum_num_iopads; + } + } else { + /* Definition ends*/ + /* Quote all child pb_types */ + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + /* Each child may exist multiple times in the hierarchy*/ + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* we should make sure this placement index == child_pb_type[jpb]*/ + assert(jpb == cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb].placement_index); + if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { + /* Count in the number of configuration bits of on child pb */ + sum_num_iopads += cur_pb->child_pbs[ipb][jpb].num_iopads; + } else { + /* Count in the number of configuration bits of on child pb_type */ + sum_num_iopads += cur_pb_type->modes[mode_index].pb_type_children[ipb].default_mode_num_iopads; + } + } + } + /* Count the number of configuration bits of interconnection */ + /* Update the info in pb_type */ + cur_pb->num_iopads = sum_num_iopads; + } + + return; +} + +/* Initialize the number of configuraion bits for one grid */ +void init_one_grid_num_iopads(int ix, int iy) { + t_block* mapped_block = NULL; + int iz; + int cur_block_index = 0; + int capacity; + + /* Check */ + assert((!(0 > ix))&&(!(ix > (nx + 1)))); + assert((!(0 > iy))&&(!(iy > (ny + 1)))); + + if ((NULL == grid[ix][iy].type)||(0 != grid[ix][iy].offset)) { + /* Empty grid, directly return */ + return; + } + capacity= grid[ix][iy].type->capacity; + assert(0 < capacity); + + /* check capacity and if this has been mapped */ + for (iz = 0; iz < capacity; iz++) { + /* Check in all the blocks(clustered logic block), there is a match x,y,z*/ + mapped_block = search_mapped_block(ix, iy, iz); + rec_count_num_iopads_pb_type_physical_mode(grid[ix][iy].type->pb_type); + /* Comments: Grid [x][y]*/ + if (NULL == mapped_block) { + /* Print a consider a idle pb_type ...*/ + rec_count_num_iopads_pb_type_default_mode(grid[ix][iy].type->pb_type); + } else { + if (iz == mapped_block->z) { + // assert(mapped_block == &(block[grid[ix][iy].blocks[cur_block_index]])); + cur_block_index++; + } + rec_count_num_iopads_pb(mapped_block->pb); + } + } + + assert(cur_block_index == grid[ix][iy].usage); + + return; +} + +/* Initialize the number of configuraion bits for all grids */ +void init_grids_num_iopads() { + int ix, iy; + + /* Core grid */ + vpr_printf(TIO_MESSAGE_INFO, "INFO: Initializing number of I/O pads of Core grids...\n"); + for (ix = 1; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + init_one_grid_num_iopads(ix, iy); + } + } + + /* Consider the IO pads */ + vpr_printf(TIO_MESSAGE_INFO, "INFO: Initializing number of I/O pads of I/O grids...\n"); + /* Left side: x = 0, y = 1 .. ny*/ + ix = 0; + for (iy = 1; iy < (ny + 1); iy++) { + /* Ensure this is a io */ + assert(IO_TYPE == grid[ix][iy].type); + init_one_grid_num_iopads(ix, iy); + } + /* Right side : x = nx + 1, y = 1 .. ny*/ + ix = nx + 1; + for (iy = 1; iy < (ny + 1); iy++) { + /* Ensure this is a io */ + assert(IO_TYPE == grid[ix][iy].type); + init_one_grid_num_iopads(ix, iy); + } + /* Bottom side : x = 1 .. nx + 1, y = 0 */ + iy = 0; + for (ix = 1; ix < (nx + 1); ix++) { + /* Ensure this is a io */ + assert(IO_TYPE == grid[ix][iy].type); + init_one_grid_num_iopads(ix, iy); + } + /* Top side : x = 1 .. nx + 1, y = nx + 1 */ + iy = ny + 1; + for (ix = 1; ix < (nx + 1); ix++) { + /* Ensure this is a io */ + assert(IO_TYPE == grid[ix][iy].type); + init_one_grid_num_iopads(ix, iy); + } + + return; +} + +/* Count the number of mode configuration bits of a grid (type_descriptor) in default mode */ +void rec_count_num_mode_bits_pb_type_default_mode(t_pb_type* cur_pb_type) { + int mode_index, ipb, jpb; + int sum_num_mode_bits = 0; + + cur_pb_type->default_mode_num_mode_bits = 0; + + /* Recursively finish all the child pb_types*/ + if (NULL == cur_pb_type->spice_model) { + /* Find the mode that define_idle_mode*/ + mode_index = find_pb_type_idle_mode_index((*cur_pb_type)); + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + rec_count_num_mode_bits_pb_type_default_mode(&(cur_pb_type->modes[mode_index].pb_type_children[ipb])); + } + } + } + + /* Check if this has defined a spice_model*/ + if (NULL != cur_pb_type->spice_model) { + if (SPICE_MODEL_IOPAD == cur_pb_type->spice_model->type) { + sum_num_mode_bits = 1; + cur_pb_type->default_mode_num_mode_bits = sum_num_mode_bits; + } + } else { /* Count the sum of configuration bits of all the children pb_types */ + /* Find the mode that define_idle_mode*/ + mode_index = find_pb_type_idle_mode_index((*cur_pb_type)); + /* Quote all child pb_types */ + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + /* Each child may exist multiple times in the hierarchy*/ + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Count in the number of configuration bits of on child pb_type */ + sum_num_mode_bits += cur_pb_type->modes[mode_index].pb_type_children[ipb].default_mode_num_mode_bits; + } + } + /* Count the number of configuration bits of interconnection */ + /* Update the info in pb_type */ + cur_pb_type->default_mode_num_mode_bits = sum_num_mode_bits; + } + + return; +} + +/* Count the number of configuration bits of a pb_graph_node */ +void rec_count_num_mode_bits_pb(t_pb* cur_pb) { + int mode_index, ipb, jpb; + t_pb_type* cur_pb_type = NULL; + t_pb_graph_node* cur_pb_graph_node = NULL; + + int sum_num_mode_bits = 0; + + /* Check cur_pb_graph_node*/ + if (NULL == cur_pb) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb.\n", + __FILE__, __LINE__); + exit(1); + } + cur_pb_graph_node = cur_pb->pb_graph_node; + cur_pb_type = cur_pb_graph_node->pb_type; + mode_index = cur_pb->mode; + + cur_pb->num_mode_bits = 0; + + /* Recursively finish all the child pb_types*/ + if (NULL == cur_pb_type->spice_model) { + /* recursive for the child_pbs*/ + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Recursive*/ + /* Refer to pack/output_clustering.c [LINE 392] */ + if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { + rec_count_num_mode_bits_pb(&(cur_pb->child_pbs[ipb][jpb])); + } else { + /* Check if this pb has no children, no children mean idle*/ + rec_count_num_mode_bits_pb_type_default_mode(cur_pb->child_pbs[ipb][jpb].pb_graph_node->pb_type); + } + } + } + } + + /* Check if this has defined a spice_model*/ + if (NULL != cur_pb_type->spice_model) { + if (SPICE_MODEL_IOPAD == cur_pb_type->spice_model->type) { + sum_num_mode_bits = 1; + cur_pb->num_mode_bits = sum_num_mode_bits; + } + } else { + /* Definition ends*/ + /* Quote all child pb_types */ + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + /* Each child may exist multiple times in the hierarchy*/ + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* we should make sure this placement index == child_pb_type[jpb]*/ + assert(jpb == cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb].placement_index); + if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { + /* Count in the number of configuration bits of on child pb */ + sum_num_mode_bits += cur_pb->child_pbs[ipb][jpb].num_mode_bits; + } else { + /* Count in the number of configuration bits of on child pb_type */ + sum_num_mode_bits += cur_pb_type->modes[mode_index].pb_type_children[ipb].default_mode_num_mode_bits; + } + } + } + /* Count the number of configuration bits of interconnection */ + /* Update the info in pb_type */ + cur_pb->num_mode_bits = sum_num_mode_bits; + } + + return; +} + +/* Initialize the number of configuraion bits for one grid */ +void init_one_grid_num_mode_bits(int ix, int iy) { + t_block* mapped_block = NULL; + int iz; + int cur_block_index = 0; + int capacity; + + /* Check */ + assert((!(0 > ix))&&(!(ix > (nx + 1)))); + assert((!(0 > iy))&&(!(iy > (ny + 1)))); + + if ((NULL == grid[ix][iy].type)||(0 != grid[ix][iy].offset)) { + /* Empty grid, directly return */ + return; + } + capacity= grid[ix][iy].type->capacity; + assert(0 < capacity); + + /* check capacity and if this has been mapped */ + for (iz = 0; iz < capacity; iz++) { + /* Check in all the blocks(clustered logic block), there is a match x,y,z*/ + mapped_block = search_mapped_block(ix, iy, iz); + /* Comments: Grid [x][y]*/ + if (NULL == mapped_block) { + /* Print a consider a idle pb_type ...*/ + rec_count_num_mode_bits_pb_type_default_mode(grid[ix][iy].type->pb_type); + } else { + if (iz == mapped_block->z) { + // assert(mapped_block == &(block[grid[ix][iy].blocks[cur_block_index]])); + cur_block_index++; + } + rec_count_num_mode_bits_pb(mapped_block->pb); + } + } + + assert(cur_block_index == grid[ix][iy].usage); + + return; +} + +/* Initialize the number of configuraion bits for all grids */ +void init_grids_num_mode_bits() { + int ix, iy; + + /* Core grid */ + vpr_printf(TIO_MESSAGE_INFO, "INFO: Initializing number of mode configuraiton bits of Core grids...\n"); + for (ix = 1; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + init_one_grid_num_mode_bits(ix, iy); + } + } + + /* Consider the IO pads */ + vpr_printf(TIO_MESSAGE_INFO, "INFO: Initializing number of mode configuration bits of I/O grids...\n"); + /* Left side: x = 0, y = 1 .. ny*/ + ix = 0; + for (iy = 1; iy < (ny + 1); iy++) { + /* Ensure this is a io */ + assert(IO_TYPE == grid[ix][iy].type); + init_one_grid_num_mode_bits(ix, iy); + } + /* Right side : x = nx + 1, y = 1 .. ny*/ + ix = nx + 1; + for (iy = 1; iy < (ny + 1); iy++) { + /* Ensure this is a io */ + assert(IO_TYPE == grid[ix][iy].type); + init_one_grid_num_mode_bits(ix, iy); + } + /* Bottom side : x = 1 .. nx + 1, y = 0 */ + iy = 0; + for (ix = 1; ix < (nx + 1); ix++) { + /* Ensure this is a io */ + assert(IO_TYPE == grid[ix][iy].type); + init_one_grid_num_mode_bits(ix, iy); + } + /* Top side : x = 1 .. nx + 1, y = nx + 1 */ + iy = ny + 1; + for (ix = 1; ix < (nx + 1); ix++) { + /* Ensure this is a io */ + assert(IO_TYPE == grid[ix][iy].type); + init_one_grid_num_mode_bits(ix, iy); + } + + return; +} + + +/* Check if this SPICE model defined as SRAM + * contain necessary ports for its functionality + */ +void check_sram_spice_model_ports(t_spice_model* cur_spice_model, + boolean include_bl_wl) { + int num_input_ports; + t_spice_model_port** input_ports = NULL; + int num_output_ports; + t_spice_model_port** output_ports = NULL; + int num_bl_ports; + t_spice_model_port** bl_ports = NULL; + int num_wl_ports; + t_spice_model_port** wl_ports = NULL; + + int iport; + int num_global_ports = 0; + int num_err = 0; + + /* Check the type of SPICE model */ + assert(SPICE_MODEL_SRAM == cur_spice_model->type); + + /* Check if we has 1 input other than global ports */ + input_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_ports, TRUE); + num_global_ports = 0; + for (iport = 0; iport < num_input_ports; iport++) { + if (TRUE == input_ports[iport]->is_global) { + num_global_ports++; + } + } + if (1 != (num_input_ports - num_global_ports)) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SRAM SPICE MODEL should have only 1 non-global input port!\n", + __FILE__, __LINE__); + num_err++; + if (1 != input_ports[0]->size) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SRAM SPICE MODEL should have an input port with size 1!\n", + __FILE__, __LINE__); + num_err++; + } + } + /* Check if we has 1 output with size 2 */ + output_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_ports, TRUE); + num_global_ports = 0; + for (iport = 0; iport < num_output_ports; iport++) { + if (TRUE == output_ports[iport]->is_global) { + num_global_ports++; + } + } + if (1 != (num_output_ports - num_global_ports)) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SRAM SPICE MODEL should have only 1 non-global output port!\n", + __FILE__, __LINE__); + num_err++; + if (2 != output_ports[0]->size) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SRAM SPICE MODEL should have a output port with size 2!\n", + __FILE__, __LINE__); + num_err++; + } + } + if (FALSE == include_bl_wl) { + if (0 == num_err) { + return; + } else { + exit(1); + } + } + /* If bl and wl are required, check their existence */ + bl_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_BL, &num_bl_ports, TRUE); + if (1 != num_bl_ports) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SRAM SPICE MODEL with BL and WL should have only 1 BL port!\n", + __FILE__, __LINE__); + num_err++; + exit(1); + if (1 != bl_ports[0]->size) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SRAM SPICE MODEL should have a BL port with size 1!\n", + __FILE__, __LINE__); + num_err++; + } + } + + wl_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_WL, &num_wl_ports, TRUE); + if (1 != num_wl_ports) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SRAM SPICE MODEL with WL and WL should have only 1 WL port!\n", + __FILE__, __LINE__); + num_err++; + exit(1); + if (1 != wl_ports[0]->size) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SRAM SPICE MODEL should have a WL port with size 1!\n", + __FILE__, __LINE__); + num_err++; + } + } + + if (0 < num_err) { + exit(1); + } + + /* Free */ + my_free(input_ports); + my_free(output_ports); + my_free(bl_ports); + my_free(wl_ports); + + return; +} + +void check_ff_spice_model_ports(t_spice_model* cur_spice_model, + boolean is_scff) { + int iport; + int num_input_ports; + t_spice_model_port** input_ports = NULL; + int num_output_ports; + t_spice_model_port** output_ports = NULL; + int num_clock_ports; + t_spice_model_port** clock_ports = NULL; + + int num_err = 0; + + /* Check the type of SPICE model */ + if (FALSE == is_scff) { + assert(SPICE_MODEL_FF == cur_spice_model->type); + } else { + assert(SPICE_MODEL_SCFF == cur_spice_model->type); + } + /* Check if we have D, Set and Reset */ + input_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_ports, FALSE); + if (TRUE == is_scff) { + if (1 > num_input_ports) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SCFF SPICE MODEL should at least have an input port!\n", + __FILE__, __LINE__); + num_err++; + } + for (iport = 0; iport < num_input_ports; iport++) { + if (1 != input_ports[iport]->size) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SCFF SPICE MODEL: each input port with size 1!\n", + __FILE__, __LINE__); + num_err++; + } + } + } else { + if (3 != num_input_ports) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) FF SPICE MODEL should have only 3 input port!\n", + __FILE__, __LINE__); + num_err++; + } + for (iport = 0; iport < num_input_ports; iport++) { + if (1 != input_ports[iport]->size) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) FF SPICE MODEL: each input port with size 1!\n", + __FILE__, __LINE__); + num_err++; + } + } + } + /* Check if we have clock */ + clock_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_CLOCK, &num_clock_ports, FALSE); + if (1 > num_clock_ports) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) [FF|SCFF] SPICE MODEL should have at least 1 clock port!\n", + __FILE__, __LINE__); + num_err++; + } + for (iport = 0; iport < num_clock_ports; iport++) { + if (1 != clock_ports[iport]->size) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) [FF|SCFF] SPICE MODEL: 1 clock port with size 1!\n", + __FILE__, __LINE__); + num_err++; + } + } + /* Check if we have output */ + output_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_ports, TRUE); + if (FALSE == is_scff) { + if (1 != output_ports[0]->size) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) FF SPICE MODEL: each output port with size 1!\n", + __FILE__, __LINE__); + num_err++; + } + } else { + if (1 != num_output_ports) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SCFF SPICE MODEL should have only 1 output port!\n", + __FILE__, __LINE__); + num_err++; + if (2 != output_ports[0]->size) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SCFF SPICE MODEL: the output port with size 2!\n", + __FILE__, __LINE__); + num_err++; + } + } + } + /* Error out if required */ + if (0 < num_err) { + exit(1); + } + + /* Free */ + my_free(input_ports); + my_free(output_ports); + my_free(clock_ports); + + return; +} + +/* Free a conf_bit_info */ +void free_conf_bit(t_conf_bit* conf_bit) { + return; +} + +void free_conf_bit_info(t_conf_bit_info* conf_bit_info) { + free_conf_bit(conf_bit_info->sram_bit); + my_free(conf_bit_info->sram_bit); + + free_conf_bit(conf_bit_info->bl); + my_free(conf_bit_info->bl); + + free_conf_bit(conf_bit_info->wl); + my_free(conf_bit_info->wl); + + return; +} + +/* Fill the information into a confbit_info */ +t_conf_bit_info* +alloc_one_conf_bit_info(int index, + t_conf_bit* sram_val, + t_conf_bit* bl_val, t_conf_bit* wl_val, + t_spice_model* parent_spice_model) { + t_conf_bit_info* new_conf_bit_info = (t_conf_bit_info*)my_malloc(sizeof(t_conf_bit_info)); + + /* Check if we have a valid conf_bit_info */ + if (NULL == new_conf_bit_info) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Fail to malloc a new conf_bit_info!\n", + __FILE__, __LINE__); + exit(1); + } + /* Fill the information */ + new_conf_bit_info->index = index; + new_conf_bit_info->sram_bit = sram_val; + new_conf_bit_info->bl = bl_val; + new_conf_bit_info->wl = wl_val; + new_conf_bit_info->parent_spice_model = parent_spice_model; + new_conf_bit_info->parent_spice_model_index = parent_spice_model->cnt; + + return new_conf_bit_info; +} + +/* Add an element to linked-list */ +t_llist* +add_conf_bit_info_to_llist(t_llist* head, int index, + t_conf_bit* sram_val, t_conf_bit* bl_val, t_conf_bit* wl_val, + t_spice_model* parent_spice_model) { + t_llist* temp = NULL; + t_conf_bit_info* new_conf_bit_info = NULL; + + /* if head is NULL, we create a head */ + if (NULL == head) { + temp = create_llist(1); + new_conf_bit_info = alloc_one_conf_bit_info(index, sram_val, bl_val, wl_val, parent_spice_model); + assert(NULL != new_conf_bit_info); + temp->dptr = (void*)new_conf_bit_info; + assert(NULL == temp->next); + return temp; + } else { + /* If head is a valid pointer, we add a new element to the tail of this linked-list */ + temp = insert_llist_node_before_head(head); + new_conf_bit_info = alloc_one_conf_bit_info(index, sram_val, bl_val, wl_val, parent_spice_model); + assert(NULL != new_conf_bit_info); + temp->dptr = (void*)new_conf_bit_info; + return temp; + } +} + +/* add configuration bits of a MUX to linked-list + * when SRAM organization type is scan-chain */ +void +add_mux_scff_conf_bits_to_llist(int mux_size, + t_sram_orgz_info* cur_sram_orgz_info, + int num_mux_sram_bits, int* mux_sram_bits, + t_spice_model* mux_spice_model) { + int ibit, cur_mem_bit; + t_conf_bit** sram_bit = NULL; + + /* Assert*/ + assert(NULL != cur_sram_orgz_info); + assert(NULL != mux_spice_model); + + cur_mem_bit = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); + + /* Depend on the design technology of mux_spice_model + * Fill the conf_bits information */ + switch (mux_spice_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + case SPICE_MODEL_DESIGN_RRAM: + /* Count how many configuration bits need to program + * Scan-chain needs to know each memory bit whatever it is 0 or 1 + */ + /* Allocate the array */ + sram_bit = (t_conf_bit**)my_malloc(num_mux_sram_bits * sizeof(t_conf_bit*)); + for (ibit = 0; ibit < num_mux_sram_bits; ibit++) { + sram_bit[ibit] = (t_conf_bit*)my_malloc(sizeof(t_conf_bit)); + } + /* Fill the array: sram_bit */ + for (ibit = 0; ibit < num_mux_sram_bits; ibit++) { + sram_bit[ibit]->addr = cur_mem_bit + ibit; + sram_bit[ibit]->val = mux_sram_bits[ibit]; + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid design technology!", + __FILE__, __LINE__ ); + exit(1); + } + + /*ย Fill the linked list */ + for (ibit = 0; ibit < num_mux_sram_bits; ibit++) { + cur_sram_orgz_info->conf_bit_head = + add_conf_bit_info_to_llist(cur_sram_orgz_info->conf_bit_head, cur_mem_bit + ibit, + sram_bit[ibit], NULL, NULL, + mux_spice_model); + } + + /* Free */ + my_free(sram_bit); + + return; +} + +/* add configuration bits of a MUX to linked-list + * when SRAM organization type is scan-chain */ +void +add_mux_membank_conf_bits_to_llist(int mux_size, + t_sram_orgz_info* cur_sram_orgz_info, + int num_mux_sram_bits, int* mux_sram_bits, + t_spice_model* mux_spice_model) { + int ibit, cur_mem_bit, num_conf_bits, cur_bit, cur_bl, cur_wl; + int ilevel; + int num_bl_enabled, num_wl_enabled; + t_conf_bit** sram_bit = NULL; + t_conf_bit** wl_bit = NULL; + t_conf_bit** bl_bit = NULL; + + /* Assert*/ + assert(NULL != cur_sram_orgz_info); + assert(NULL != mux_spice_model); + + cur_mem_bit = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); + get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_bl, &cur_wl); + + /* Depend on the design technology of mux_spice_model + * Fill the conf_bits information */ + switch (mux_spice_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + /* Count how many configuration bits need to program + * Assume all the SRAMs are zero initially. + * only Configuration to bit 1 requires a programming operation + */ + num_conf_bits = num_mux_sram_bits; + /* Allocate the array */ + bl_bit = (t_conf_bit**)my_malloc(num_mux_sram_bits * sizeof(t_conf_bit*)); + wl_bit = (t_conf_bit**)my_malloc(num_mux_sram_bits * sizeof(t_conf_bit*)); + for (ibit = 0; ibit < num_mux_sram_bits; ibit++) { + bl_bit[ibit] = (t_conf_bit*)my_malloc(sizeof(t_conf_bit)); + wl_bit[ibit] = (t_conf_bit*)my_malloc(sizeof(t_conf_bit)); + } + /* SRAMs are typically organized in an array where BLs and WLs are efficiently shared + * Actual BL/WL address in the array is hard to predict here, + * they will be handled in the top_netlist and top_testbench generation + */ + for (ibit = 0; ibit < num_mux_sram_bits; ibit++) { + bl_bit[ibit]->addr = cur_mem_bit + ibit; + bl_bit[ibit]->val = mux_sram_bits[ibit]; + wl_bit[ibit]->addr = cur_mem_bit + ibit; + wl_bit[ibit]->val = 1; /* We always assume WL is the write enable signal of a SRAM */ + } + break; + case SPICE_MODEL_DESIGN_RRAM: + /* Count how many configuration bits need to program + * only BL and WL are both 1 requires a programming operation + * Each level of a MUX requires 1 RRAM to be configured. + * Therefore, the number of configuration bits should be num_mux_levels + */ + num_bl_enabled = 0; + /* Check how many Bit lines are 1 */ + for (ibit = 0; ibit < num_mux_sram_bits/2; ibit++) { + if (1 == mux_sram_bits[ibit]) { + num_bl_enabled++; + } + } + num_wl_enabled = 0; + /* Check how many Word lines are 1 */ + for (ibit = 0; ibit < num_mux_sram_bits/2; ibit++) { + if (1 == mux_sram_bits[ibit + num_mux_sram_bits/2]) { + num_wl_enabled++; + } + } + /* The number of enabled Bit and Word lines should be the same */ + assert(num_bl_enabled == num_wl_enabled); + /* Assign num_conf_bits */ + num_conf_bits = num_bl_enabled; + /* Allocate the array */ + bl_bit = (t_conf_bit**)my_malloc(num_conf_bits * sizeof(t_conf_bit*)); + wl_bit = (t_conf_bit**)my_malloc(num_conf_bits * sizeof(t_conf_bit*)); + for (ibit = 0; ibit < num_conf_bits; ibit++) { + bl_bit[ibit] = (t_conf_bit*)my_malloc(sizeof(t_conf_bit)); + wl_bit[ibit] = (t_conf_bit*)my_malloc(sizeof(t_conf_bit)); + } + /* For one-level RRAM MUX: + * There should be only 1 BL and 1 WL whose value is 1 + * First half of mux_sram_bits are BL, the rest are WL + * For multi-level RRAM MUX: + * There could be more than 1 BL and 1 WL whose value is 1 + * We need to divde the mux_sram_bits into small part, + * each part has only 1 BL and 1 WL whose value is 1 + */ + /* Assign bit lines address and values */ + cur_bit = 0; + /* We slice the BL part of array mux_sram_bits to N=num_conf_bits parts */ + for (ilevel = 0; ilevel < num_conf_bits; ilevel++) { + for (ibit = ilevel * num_mux_sram_bits/(2*num_conf_bits); /* Start address of each slice*/ + ibit < (ilevel + 1) * num_mux_sram_bits/(2*num_conf_bits); /* End address of each slice*/ + ibit++) { + if (0 == mux_sram_bits[ibit]) { + continue; /* Skip non-zero bits */ + } + assert(1 == mux_sram_bits[ibit]); + if (ibit == (ilevel + 1) * num_mux_sram_bits/(2*num_conf_bits) - 1) { + bl_bit[cur_bit]->addr = cur_bl + ilevel; + /* Last conf_bit should use a new BL/WL */ + } else { + /* First part of conf_bit should use reserved BL/WL */ + bl_bit[cur_bit]->addr = ibit; + } + bl_bit[cur_bit]->val = mux_sram_bits[ibit]; + cur_bit++; + } + } + assert(num_conf_bits == cur_bit); + /* Assign Word lines address and values */ + cur_bit = 0; + for (ilevel = 0; ilevel < num_conf_bits; ilevel++) { + for (ibit = num_mux_sram_bits/2 + ilevel * num_mux_sram_bits/(2*num_conf_bits); /* Start address of each slice*/ + ibit < num_mux_sram_bits/2 + (ilevel + 1) * num_mux_sram_bits/(2*num_conf_bits); /* End address of each slice*/ + ibit++) { + if (0 == mux_sram_bits[ibit]) { + continue; /* Skip non-zero bits */ + } + assert(1 == mux_sram_bits[ibit]); + if (ibit == num_mux_sram_bits/2 + (ilevel + 1) * num_mux_sram_bits/(2*num_conf_bits) - 1) { + wl_bit[cur_bit]->addr = cur_wl + ilevel; + /* Last conf_bit should use a new BL/WL */ + } else { + /* First part of conf_bit should use reserved BL/WL */ + wl_bit[cur_bit]->addr = ibit; + } + wl_bit[cur_bit]->val = mux_sram_bits[ibit]; + cur_bit++; + } + } + assert(num_conf_bits == cur_bit); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid design technology!", + __FILE__, __LINE__ ); + exit(1); + } + + /*ย Fill the linked list */ + for (ibit = 0; ibit < num_conf_bits; ibit++) { + cur_sram_orgz_info->conf_bit_head = + add_conf_bit_info_to_llist(cur_sram_orgz_info->conf_bit_head, cur_mem_bit + ibit, + NULL, bl_bit[ibit], wl_bit[ibit], + mux_spice_model); + } + + /* Free */ + my_free(sram_bit); + my_free(bl_bit); + my_free(wl_bit); + + return; +} + +/* Should we return a value ? */ +void +add_mux_conf_bits_to_llist(int mux_size, + t_sram_orgz_info* cur_sram_orgz_info, + int num_mux_sram_bits, int* mux_sram_bits, + t_spice_model* mux_spice_model) { + /* According to the type, we allocate structs */ + switch (cur_sram_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + case SPICE_SRAM_SCAN_CHAIN: + add_mux_scff_conf_bits_to_llist(mux_size, cur_sram_orgz_info, + num_mux_sram_bits, mux_sram_bits, + mux_spice_model); + break; + case SPICE_SRAM_MEMORY_BANK: + add_mux_membank_conf_bits_to_llist(mux_size, cur_sram_orgz_info, + num_mux_sram_bits, mux_sram_bits, + mux_spice_model); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", + __FILE__, __LINE__); + exit(1); + } + + return; +} + +/* Add SCFF configutration bits to a linked list*/ +void +add_sram_scff_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, + int num_sram_bits, int* sram_bits) { + int ibit, cur_mem_bit; + t_conf_bit** sram_bit = NULL; + t_spice_model* cur_sram_spice_model = NULL; + + /* Assert*/ + assert(NULL != cur_sram_orgz_info); + + cur_mem_bit = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); + + /* Get memory model */ + get_sram_orgz_info_mem_model(cur_sram_orgz_info, &cur_sram_spice_model); + assert(NULL != cur_sram_spice_model); + + /* Count how many configuration bits need to program + * Scan-chain needs to know each memory bit whatever it is 0 or 1 + */ + /* Allocate the array */ + sram_bit = (t_conf_bit**)my_malloc(num_sram_bits * sizeof(t_conf_bit*)); + for (ibit = 0; ibit < num_sram_bits; ibit++) { + sram_bit[ibit] = (t_conf_bit*)my_malloc(sizeof(t_conf_bit)); + } + /* Fill the array: sram_bit */ + for (ibit = 0; ibit < num_sram_bits; ibit++) { + sram_bit[ibit]->addr = cur_mem_bit + ibit; + sram_bit[ibit]->val = sram_bits[ibit]; + } + + /*ย Fill the linked list */ + for (ibit = 0; ibit < num_sram_bits; ibit++) { + cur_sram_orgz_info->conf_bit_head = + add_conf_bit_info_to_llist(cur_sram_orgz_info->conf_bit_head, cur_mem_bit + ibit, + sram_bit[ibit], NULL, NULL, + cur_sram_spice_model); + } + + /* Free */ + my_free(sram_bit); + + return; +} + + +/* Add SRAM configuration bits in memory bank organization to a linked list */ +void add_sram_membank_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, int mem_index, + int num_bls, int num_wls, + int* bl_conf_bits, int* wl_conf_bits) { + int ibit, cur_bl, cur_wl, cur_mem_bit; + t_spice_model* cur_sram_spice_model = NULL; + t_conf_bit* bl_bit = NULL; + t_conf_bit* wl_bit = NULL; + int bit_cnt = 0; + + /* Assert*/ + assert(NULL != cur_sram_orgz_info); + + /* Get current counter of sram_spice_model */ + cur_mem_bit = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); + get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_bl, &cur_wl); + + /* Get memory model */ + get_sram_orgz_info_mem_model(cur_sram_orgz_info, &cur_sram_spice_model); + assert(NULL != cur_sram_spice_model); + + /* Malloc */ + bl_bit = (t_conf_bit*)my_malloc(sizeof(t_conf_bit)); + wl_bit = (t_conf_bit*)my_malloc(sizeof(t_conf_bit)); + + /* Depend on the memory technology, we have different configuration bits */ + switch (cur_sram_spice_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + assert((1 == num_bls)&&(1 == num_wls)); + bl_bit->addr = mem_index; + wl_bit->addr = mem_index; + bl_bit->val = bl_conf_bits[0]; + wl_bit->val = wl_conf_bits[0]; + break; + case SPICE_MODEL_DESIGN_RRAM: + /* Fill information */ + bit_cnt = 0; /* Check counter */ + for (ibit = 0; ibit < num_bls; ibit++) { + /* Bypass zero bit */ + if (0 == bl_conf_bits[ibit]) { + continue; + } + /* Check if this bit is in reserved bls */ + if (ibit == num_bls - 1) { + /* Last bit is always independent */ + bl_bit->addr = mem_index; + bl_bit->val = 1; + } else { + /* Other bits are shared */ + bl_bit->addr = ibit; + bl_bit->val = 1; + } + /* Update check counter */ + bit_cnt++; + } + /* Check */ + assert(1 == bit_cnt); + + bit_cnt = 0; /* Check counter */ + for (ibit = 0; ibit < num_wls; ibit++) { + /* Bypass zero bit */ + if (0 == wl_conf_bits[ibit]) { + continue; + } + /* Check if this bit is in reserved bls */ + if (ibit == num_wls - 1) { + /* Last bit is always independent */ + wl_bit->addr = mem_index; + wl_bit->val = 1; + } else { + /* Other bits are shared */ + wl_bit->addr = ibit; + wl_bit->val = 1; + } + /* Update check counter */ + bit_cnt++; + } + /* Check */ + assert(1 == bit_cnt); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid design technology!", + __FILE__, __LINE__); + exit(1); + } + + /*ย Fill the linked list */ + cur_sram_orgz_info->conf_bit_head = + add_conf_bit_info_to_llist(cur_sram_orgz_info->conf_bit_head, mem_index, + NULL, bl_bit, wl_bit, + cur_sram_spice_model); + + return; +} + +/* Add SRAM configuration bits to a linked list */ +void +add_sram_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, int mem_index, + int num_sram_bits, int* sram_bits) { + int num_bls, num_wls; + int* bl_conf_bits = NULL; + int* wl_conf_bits = NULL; + + /* According to the type, we allocate structs */ + switch (cur_sram_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + case SPICE_SRAM_SCAN_CHAIN: + add_sram_scff_conf_bits_to_llist(cur_sram_orgz_info, + num_sram_bits, sram_bits); + break; + case SPICE_SRAM_MEMORY_BANK: + /* Initialize parameters */ + /* Number of BLs should be same as WLs */ + num_bls = num_sram_bits/2; + num_wls = num_sram_bits/2; + /* Convention: first part of Array (sram_bits) is BL configuration bits, + * second part is WL configuration bits. + */ + bl_conf_bits = sram_bits; + wl_conf_bits = sram_bits + num_bls; + add_sram_membank_conf_bits_to_llist(cur_sram_orgz_info, mem_index, + num_bls, num_wls, + bl_conf_bits, wl_conf_bits); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", + __FILE__, __LINE__); + exit(1); + } + + return; +} + +/* Find BL and WL ports for a SRAM model. + * And check if the number of BL/WL satisfy the technology needs + */ +void find_bl_wl_ports_spice_model(t_spice_model* cur_spice_model, + int* num_bl_ports, t_spice_model_port*** bl_ports, + int* num_wl_ports, t_spice_model_port*** wl_ports) { + int i; + + /* Check */ + assert(NULL != cur_spice_model); + + /* Find BL ports */ + (*bl_ports) = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_BL, num_bl_ports, TRUE); + /* Find WL ports */ + (*wl_ports) = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_WL, num_wl_ports, TRUE); + + /* port size of BL/WL should be at least 1 !*/ + assert((*num_bl_ports) == (*num_wl_ports)); + + /* Check the size of BL/WL ports */ + switch (cur_spice_model->design_tech) { + case SPICE_MODEL_DESIGN_RRAM: + /* This check may be too tight */ + for (i = 0; i < (*num_bl_ports); i++) { + assert(0 < (*bl_ports)[i]->size); + } + for (i = 0; i < (*num_wl_ports); i++) { + assert(0 < (*wl_ports)[i]->size); + } + break; + case SPICE_MODEL_DESIGN_CMOS: + for (i = 0; i < (*num_bl_ports); i++) { + assert(0 < (*bl_ports)[i]->size); + } + for (i = 0; i < (*num_wl_ports); i++) { + assert(0 < (*wl_ports)[i]->size); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of MUX(name: %s)\n", + __FILE__, __LINE__, cur_spice_model->name); + exit(1); + } + + return; +} + +/* Find BL and WL ports for a SRAM model. + * And check if the number of BL/WL satisfy the technology needs + */ +void find_blb_wlb_ports_spice_model(t_spice_model* cur_spice_model, + int* num_blb_ports, t_spice_model_port*** blb_ports, + int* num_wlb_ports, t_spice_model_port*** wlb_ports) { + int i; + + /* Check */ + assert(NULL != cur_spice_model); + + /* Find BL ports */ + (*blb_ports) = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_BLB, num_blb_ports, TRUE); + /* Find WL ports */ + (*wlb_ports) = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_WLB, num_wlb_ports, TRUE); + + return; +} + +/* Decode mode bits "01..." to a SRAM bits array */ +int* decode_mode_bits(char* mode_bits, int* num_sram_bits) { + int* sram_bits = NULL; + int i; + + assert(NULL != mode_bits); + (*num_sram_bits) = strlen(mode_bits); + + sram_bits = (int*)my_calloc((*num_sram_bits), sizeof(int)); + + for (i = 0; i < (*num_sram_bits); i++) { + switch(mode_bits[i]) { + case '1': + sram_bits[i] = 1; + break; + case '0': + sram_bits[i] = 0; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid mode_bits(%s)!\n", + __FILE__, __LINE__, mode_bits); + exit(1); + } + } + + return sram_bits; +} + +/* For LUTs without SPICE netlist defined, we can create a SPICE netlist + * In this case, we need a MUX + */ +void stats_lut_spice_mux(t_llist** muxes_head, + t_spice_model* spice_model) { + int lut_mux_size = 0; + int num_input_port = 0; + t_spice_model_port** input_ports = NULL; + + if (NULL == spice_model) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid Spice_model pointer!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert(SPICE_MODEL_LUT == spice_model->type); + + /* Get input ports */ + input_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + assert(1 == num_input_port); + lut_mux_size = (int)pow(2.,(double)(input_ports[0]->size)); + + /* MUX size = 2^lut_size */ + check_and_add_mux_to_linked_list(muxes_head, lut_mux_size, spice_model); + + return; +} + +char* complete_truth_table_line(int lut_size, + char* input_truth_table_line) { + char* ret = NULL; + int num_token = 0; + char** tokens = NULL; + int cover_len = 0; + int j; + + /* Due to the size of truth table may be less than the lut size. + * i.e. in LUT-6 architecture, there exists LUT1-6 in technology-mapped netlists + * So, in truth table line, there may be 10- 1 + * In this case, we should complete it by --10- 1 + */ + /*Malloc the completed truth table, lut_size + space + truth_val + '\0'*/ + ret = (char*)my_malloc(sizeof(char)*lut_size + 3); + /* Split one line of truth table line*/ + tokens = my_strtok(input_truth_table_line, " ", &num_token); + /* Check, only 2 tokens*/ + /* Sometimes, the truth table is ' 0' or ' 1', which corresponds to a constant */ + if (1 == num_token) { + /* restore the token[0]*/ + tokens = (char**)realloc(tokens, 2*sizeof(char*)); + tokens[1] = tokens[0]; + tokens[0] = my_strdup("-"); + num_token = 2; + } + + /* In Most cases, there should be 2 tokens. */ + assert(2 == num_token); + if ((0 != strcmp(tokens[1], "1"))&&(0 != strcmp(tokens[1], "0"))) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Last token of truth table line should be [0|1]!\n", + __FILE__, __LINE__); + exit(1); + } + /* Complete the truth table line*/ + cover_len = strlen(tokens[0]); + assert((cover_len < lut_size)||(cover_len == lut_size)); + + /* Copy the original truth table line */ + for (j = 0; j < cover_len; j++) { + ret[j] = tokens[0][j]; + } + /* Add the number of '-' we should add in the back !!! */ + for (j = cover_len; j < lut_size; j++) { + ret[j] = '-'; + } + + /* Copy the original truth table line */ + sprintf(ret + lut_size, " %s", tokens[1]); + + /* Free */ + for (j = 0; j < num_token; j++) { + my_free(tokens[j]); + } + + return ret; +} + +/* For each lut_bit_lines, we should recover the truth table, + * and then set the sram bits to "1" if the truth table defines so. + * Start_point: the position we start decode recursively + */ +void configure_lut_sram_bits_per_line_rec(int** sram_bits, + int lut_size, + char* truth_table_line, + int start_point) { + int i; + int num_sram_bit = (int)pow(2., (double)(lut_size)); + char* temp_line = my_strdup(truth_table_line); + int do_config = 1; + int sram_id = 0; + + /* Check the length of sram bits and truth table line */ + //assert((sizeof(int)*num_sram_bit) == sizeof(*sram_bits)); /*TODO: fix this assert*/ + assert((unsigned)(lut_size + 1 + 1)== strlen(truth_table_line)); /* lut_size + space + '1' */ + /* End of truth_table_line should be "space" and "1" */ + assert((0 == strcmp(" 1", truth_table_line + lut_size))||(0 == strcmp(" 0", truth_table_line + lut_size))); + /* Make sure before start point there is no '-' */ + for (i = 0; i < start_point; i++) { + assert('-' != truth_table_line[i]); + } + + /* Configure sram bits recursively */ + for (i = start_point; i < lut_size; i++) { + if ('-' == truth_table_line[i]) { + do_config = 0; + /* if we find a dont_care, we don't do configure now but recursively*/ + /* '0' branch */ + temp_line[i] = '0'; + configure_lut_sram_bits_per_line_rec(sram_bits, lut_size, temp_line, start_point + 1); + /* '1' branch */ + temp_line[i] = '1'; + configure_lut_sram_bits_per_line_rec(sram_bits, lut_size, temp_line, start_point + 1); + break; + } + } + + /* do_config*/ + if (do_config) { + for (i = 0; i < lut_size; i++) { + /* Should be either '0' or '1' */ + switch (truth_table_line[i]) { + case '0': + /* We assume the 1-lut pass sram1 when input = 0 */ + sram_id += (int)pow(2., (double)(i)); + break; + case '1': + /* We assume the 1-lut pass sram0 when input = 1 */ + break; + case '-': + assert('-' != truth_table_line[i]); /* Make sure there is no dont_care */ + default : + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid truth_table bit(%c), should be [0|1|'-]!\n", + __FILE__, __LINE__, truth_table_line[i]); + exit(1); + } + } + /* Set the sram bit to '1'*/ + assert((-1 < sram_id) && (sram_id < num_sram_bit)); + if (0 == strcmp(" 1", truth_table_line + lut_size)) { + (*sram_bits)[sram_id] = 1; /* on set*/ + } else if (0 == strcmp(" 0", truth_table_line + lut_size)) { + (*sram_bits)[sram_id] = 0; /* off set */ + } else { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid truth_table_line ending(=%s)!\n", + __FILE__, __LINE__, truth_table_line + lut_size); + exit(1); + } + } + + /* Free */ + my_free(temp_line); + + return; +} + +int* generate_lut_sram_bits(int truth_table_len, + char** truth_table, + int lut_size, + int default_sram_bit_value) { + int num_sram = (int)pow(2.,(double)(lut_size)); + int* ret = (int*)my_malloc(sizeof(int)*num_sram); + char** completed_truth_table = (char**)my_malloc(sizeof(char*)*truth_table_len); + int on_set = 0; + int off_set = 0; + int i; + + /* if No truth_table, do default*/ + if (0 == truth_table_len) { + switch (default_sram_bit_value) { + case 0: + off_set = 0; + on_set = 1; + break; + case 1: + off_set = 1; + on_set = 0; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid default_signal_init_value(=%d)!\n", + __FILE__, __LINE__, default_sram_bit_value); + exit(1); + } + } + + /* Read in truth table lines, decode one by one */ + for (i = 0; i < truth_table_len; i++) { + /* Complete the truth table line by line*/ + //printf("truth_table[%d] = %s\n", i, truth_table[i]); + completed_truth_table[i] = complete_truth_table_line(lut_size, truth_table[i]); + //printf("Completed_truth_table[%d] = %s\n", i, completed_truth_table[i]); + if (0 == strcmp(" 1", completed_truth_table[i] + lut_size)) { + on_set = 1; + } else if (0 == strcmp(" 0", completed_truth_table[i] + lut_size)) { + off_set = 1; + } + } + //printf("on_set=%d off_set=%d", on_set, off_set); + assert(1 == (on_set + off_set)); + + if (1 == on_set) { + /* Initial all sram bits to 0*/ + for (i = 0 ; i < num_sram; i++) { + ret[i] = 0; + } + } else if (1 == off_set) { + /* Initial all sram bits to 1*/ + for (i = 0 ; i < num_sram; i++) { + ret[i] = 1; + } + } + + for (i = 0; i < truth_table_len; i++) { + /* Update the truth table, sram_bits */ + configure_lut_sram_bits_per_line_rec(&ret, lut_size, completed_truth_table[i], 0); + } + + /* Free */ + for (i = 0; i < truth_table_len; i++) { + my_free(completed_truth_table[i]); + } + + return ret; +} + +char** assign_lut_truth_table(t_logical_block* mapped_logical_block, + int* truth_table_length) { + char** truth_table = NULL; + t_linked_vptr* head = NULL; + int cur = 0; + + if (NULL == mapped_logical_block) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid mapped_logical_block!\n", + __FILE__, __LINE__); + exit(1); + } + /* Count the lines of truth table*/ + head = mapped_logical_block->truth_table; + while(head) { + (*truth_table_length)++; + head = head->next; + } + /* Allocate truth_tables */ + truth_table = (char**)my_malloc(sizeof(char*)*(*truth_table_length)); + /* Fill truth_tables*/ + cur = 0; + head = mapped_logical_block->truth_table; + while(head) { + truth_table[cur] = my_strdup((char*)head->data_vptr); + head = head->next; + cur++; + } + assert(cur == (*truth_table_length)); + + return truth_table; +} + +int get_lut_output_init_val(t_logical_block* lut_logical_block) { + int i; + int* sram_bits = NULL; /* decoded SRAM bits */ + int truth_table_length = 0; + char** truth_table = NULL; + int lut_size = 0; + int input_net_index = OPEN; + int* input_init_val = NULL; + int init_path_id = 0; + int output_init_val = 0; + + t_spice_model* lut_spice_model = NULL; + int num_sram_port = 0; + t_spice_model_port** sram_ports = NULL; + + /* Ensure a valid file handler*/ + if (NULL == lut_logical_block) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid LUT logical block!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Get SPICE model */ + assert((NULL != lut_logical_block->pb) + && ( NULL != lut_logical_block->pb->pb_graph_node) + && ( NULL != lut_logical_block->pb->pb_graph_node->pb_type)); + lut_spice_model = lut_logical_block->pb->pb_graph_node->pb_type->parent_mode->parent_pb_type->spice_model; + assert(SPICE_MODEL_LUT == lut_spice_model->type); + sram_ports = find_spice_model_ports(lut_spice_model, SPICE_MODEL_PORT_SRAM, + &num_sram_port, TRUE); + assert(1 == num_sram_port); + + /* Get the truth table */ + truth_table = assign_lut_truth_table(lut_logical_block, &truth_table_length); + lut_size = lut_logical_block->used_input_pins; + assert(!(0 > lut_size)); + /* Special for LUT_size = 0 */ + if (0 == lut_size) { + /* Generate sram bits*/ + sram_bits = generate_lut_sram_bits(truth_table_length, truth_table, + 1, sram_ports[0]->default_val); + /* This is constant generator, SRAM bits should be the same */ + output_init_val = sram_bits[0]; + for (i = 0; i < (int)pow(2.,(double)lut_size); i++) { + assert(sram_bits[i] == output_init_val); + } + } else { + /* Generate sram bits*/ + sram_bits = generate_lut_sram_bits(truth_table_length, truth_table, + lut_size, sram_ports[0]->default_val); + + assert(1 == lut_logical_block->pb->pb_graph_node->num_input_ports); + assert(1 == lut_logical_block->pb->pb_graph_node->num_output_ports); + /* Get the initial path id */ + input_init_val = (int*)my_malloc(sizeof(int)*lut_size); + for (i = 0; i < lut_size; i++) { + input_net_index = lut_logical_block->input_nets[0][i]; + input_init_val[i] = vpack_net[input_net_index].spice_net_info->init_val; + } + + init_path_id = determine_lut_path_id(lut_size, input_init_val); + /* Check */ + assert((!(0 > init_path_id))&&(init_path_id < (int)pow(2.,(double)lut_size))); + output_init_val = sram_bits[init_path_id]; + } + + /*Free*/ + for (i = 0; i < truth_table_length; i++) { + free(truth_table[i]); + } + free(truth_table); + my_free(sram_bits); + + return output_init_val; +} + + +/* Functions to manipulate struct sram_orgz_info */ +t_sram_orgz_info* alloc_one_sram_orgz_info() { + return (t_sram_orgz_info*)my_malloc(sizeof(t_sram_orgz_info)); +} + +t_mem_bank_info* alloc_one_mem_bank_info() { + return (t_mem_bank_info*)my_malloc(sizeof(t_mem_bank_info)); +} + +void free_one_mem_bank_info(t_mem_bank_info* mem_bank_info) { + return; +} + +t_scff_info* alloc_one_scff_info() { + return (t_scff_info*)my_malloc(sizeof(t_scff_info)); +} + +void free_one_scff_info(t_scff_info* scff_info) { + return; +} + +t_standalone_sram_info* alloc_one_standalone_sram_info() { + return (t_standalone_sram_info*)my_malloc(sizeof(t_standalone_sram_info)); +} + +void free_one_standalone_sram_info(t_standalone_sram_info* standalone_sram_info) { + return; +} + +void init_mem_bank_info(t_mem_bank_info* cur_mem_bank_info, + t_spice_model* cur_mem_model) { + assert(NULL != cur_mem_bank_info); + assert(NULL != cur_mem_model); + cur_mem_bank_info->mem_model = cur_mem_model; + cur_mem_bank_info->num_mem_bit = 0; + cur_mem_bank_info->num_bl = 0; + cur_mem_bank_info->num_wl = 0; + cur_mem_bank_info->reserved_bl = 0; + cur_mem_bank_info->reserved_wl = 0; + + return; +} + +void update_mem_bank_info_num_mem_bit(t_mem_bank_info* cur_mem_bank_info, + int num_mem_bit) { + assert(NULL != cur_mem_bank_info); + + cur_mem_bank_info->num_mem_bit = num_mem_bit; + + return; +} + +void init_scff_info(t_scff_info* cur_scff_info, + t_spice_model* cur_mem_model) { + assert(NULL != cur_scff_info); + assert(NULL != cur_mem_model); + + cur_scff_info->mem_model = cur_mem_model; + cur_scff_info->num_mem_bit = 0; + cur_scff_info->num_scff = 0; + + return; +} + +void update_scff_info_num_mem_bit(t_scff_info* cur_scff_info, + int num_mem_bit) { + assert(NULL != cur_scff_info); + + cur_scff_info->num_mem_bit = num_mem_bit; + + return; +} + +void init_standalone_sram_info(t_standalone_sram_info* cur_standalone_sram_info, + t_spice_model* cur_mem_model) { + assert(NULL != cur_standalone_sram_info); + assert(NULL != cur_mem_model); + + cur_standalone_sram_info->mem_model = cur_mem_model; + cur_standalone_sram_info->num_mem_bit = 0; + cur_standalone_sram_info->num_sram = 0; + + return; +} + +void update_standalone_sram_info_num_mem_bit(t_standalone_sram_info* cur_standalone_sram_info, + int num_mem_bit) { + assert(NULL != cur_standalone_sram_info); + + cur_standalone_sram_info->num_mem_bit = num_mem_bit; + + return; +} + +void init_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info, + enum e_sram_orgz cur_sram_orgz_type, + t_spice_model* cur_mem_model, + int grid_nx, int grid_ny) { + int i, num_bl_per_sram, num_wl_per_sram; + int num_bl_ports; + t_spice_model_port** bl_port = NULL; + int num_wl_ports; + t_spice_model_port** wl_port = NULL; + + assert(NULL != cur_sram_orgz_info); + + cur_sram_orgz_info->type = cur_sram_orgz_type; + cur_sram_orgz_info->conf_bit_head = NULL; /* Configuration bits will be allocated later */ + + /* According to the type, we allocate structs */ + switch (cur_sram_orgz_info->type) { + case SPICE_SRAM_MEMORY_BANK: + cur_sram_orgz_info->mem_bank_info = alloc_one_mem_bank_info(); + init_mem_bank_info(cur_sram_orgz_info->mem_bank_info, cur_mem_model); + find_bl_wl_ports_spice_model(cur_mem_model, + &num_bl_ports, &bl_port, &num_wl_ports, &wl_port); + assert(1 == num_bl_ports); + assert(1 == num_wl_ports); + num_bl_per_sram = bl_port[0]->size; + num_wl_per_sram = wl_port[0]->size; + try_update_sram_orgz_info_reserved_blwl(cur_sram_orgz_info, + num_bl_per_sram, num_wl_per_sram); + break; + case SPICE_SRAM_SCAN_CHAIN: + cur_sram_orgz_info->scff_info = alloc_one_scff_info(); + init_scff_info(cur_sram_orgz_info->scff_info, cur_mem_model); + break; + case SPICE_SRAM_STANDALONE: + cur_sram_orgz_info->standalone_sram_info = alloc_one_standalone_sram_info(); + init_standalone_sram_info(cur_sram_orgz_info->standalone_sram_info, cur_mem_model); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", + __FILE__, __LINE__ ); + exit(1); + } + + /* Alloc the configuration bit information per grid */ + cur_sram_orgz_info->grid_reserved_conf_bits = (int**)my_malloc(grid_nx*sizeof(int*)); + for (i = 0; i < grid_nx; i++) { + cur_sram_orgz_info->grid_reserved_conf_bits[i] = (int*)my_calloc(grid_ny, sizeof(int)); + } + + cur_sram_orgz_info->grid_conf_bits_lsb = (int**)my_malloc(grid_nx*sizeof(int*)); + for (i = 0; i < grid_nx; i++) { + cur_sram_orgz_info->grid_conf_bits_lsb[i] = (int*)my_calloc(grid_ny, sizeof(int)); + } + + cur_sram_orgz_info->grid_conf_bits_msb = (int**)my_malloc(grid_nx*sizeof(int*)); + for (i = 0; i < grid_nx; i++) { + cur_sram_orgz_info->grid_conf_bits_msb[i] = (int*)my_calloc(grid_ny, sizeof(int)); + } + + return; +} + +void free_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info, + enum e_sram_orgz cur_sram_orgz_type, + int grid_nx, int grid_ny) { + int i; + t_llist* temp = NULL; + + assert(NULL != cur_sram_orgz_info); + + /* According to the type, we allocate structs */ + switch (cur_sram_orgz_info->type) { + case SPICE_SRAM_MEMORY_BANK: + free_one_mem_bank_info(cur_sram_orgz_info->mem_bank_info); + break; + case SPICE_SRAM_SCAN_CHAIN: + free_one_scff_info(cur_sram_orgz_info->scff_info); + break; + case SPICE_SRAM_STANDALONE: + free_one_standalone_sram_info(cur_sram_orgz_info->standalone_sram_info); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", + __FILE__, __LINE__ ); + exit(1); + } + + /* Free configuration bits linked-list */ + temp = cur_sram_orgz_info->conf_bit_head; + while(NULL != temp) { + free_conf_bit_info((t_conf_bit_info*)(temp->dptr)); + /* Set the data pointor to NULL, then we can call linked list free function */ + temp->dptr = NULL; + /* Go the next */ + temp = temp->next; + } + free_llist(cur_sram_orgz_info->conf_bit_head); + + /* Free the configuration bit information per grid */ + for (i = 0; i < grid_nx; i++) { + my_free(cur_sram_orgz_info->grid_reserved_conf_bits[i]); + } + my_free(cur_sram_orgz_info->grid_reserved_conf_bits); + + for (i = 0; i < grid_nx; i++) { + my_free(cur_sram_orgz_info->grid_conf_bits_lsb[i]); + } + my_free(cur_sram_orgz_info->grid_conf_bits_lsb); + + for (i = 0; i < grid_nx; i++) { + my_free(cur_sram_orgz_info->grid_conf_bits_msb[i]); + } + my_free(cur_sram_orgz_info->grid_conf_bits_msb); + + return; +} + +void update_mem_bank_info_reserved_blwl(t_mem_bank_info* cur_mem_bank_info, + int updated_reserved_bl, int updated_reserved_wl) { + assert(NULL != cur_mem_bank_info); + + cur_mem_bank_info->reserved_bl = updated_reserved_bl; + cur_mem_bank_info->reserved_wl = updated_reserved_wl; + + return; +} + +void get_mem_bank_info_reserved_blwl(t_mem_bank_info* cur_mem_bank_info, + int* num_reserved_bl, int* num_reserved_wl) { + assert(NULL != cur_mem_bank_info); + + (*num_reserved_bl) = cur_mem_bank_info->reserved_bl; + (*num_reserved_wl) = cur_mem_bank_info->reserved_wl; + + return; +} + +void update_mem_bank_info_num_blwl(t_mem_bank_info* cur_mem_bank_info, + int updated_bl, int updated_wl) { + assert(NULL != cur_mem_bank_info); + + cur_mem_bank_info->num_bl = updated_bl; + cur_mem_bank_info->num_wl = updated_wl; + + return; +} + +/* Initialize the number of normal/reserved BLs and WLs, mem_bits in sram_orgz_info + * If the updated_reserved_bl|wl is larger than the existed value, + * we update the reserved_bl|wl + */ +void try_update_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info, + int updated_reserved_bl, int updated_reserved_wl) { + t_spice_model* mem_model = NULL; + int cur_bl, cur_wl; + + /* Check */ + assert(updated_reserved_bl == updated_reserved_wl); + + /* get memory model */ + get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); + + /* According to the type, we allocate structs */ + switch (cur_sram_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + break; + case SPICE_SRAM_SCAN_CHAIN: + break; + case SPICE_SRAM_MEMORY_BANK: + /* CMOS technology does not need to update */ + switch (mem_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + break; + case SPICE_MODEL_DESIGN_RRAM: + /* get the current number of reserved bls and wls */ + get_sram_orgz_info_reserved_blwl(cur_sram_orgz_info, &cur_bl, &cur_wl); + if ((updated_reserved_bl > cur_bl) || (updated_reserved_wl > cur_wl)) { + update_sram_orgz_info_reserved_blwl(cur_sram_orgz_info, + updated_reserved_bl, updated_reserved_wl); + update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, + updated_reserved_bl); + update_sram_orgz_info_num_blwl(cur_sram_orgz_info, + updated_reserved_bl, updated_reserved_wl); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of design technology!", + __FILE__, __LINE__ ); + exit(1); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", + __FILE__, __LINE__ ); + exit(1); + } + +} + +/* Force to update the number of reserved BLs and WLs in sram_orgz_info + * we always update the reserved_bl|wl + */ +void update_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info, + int updated_reserved_bl, int updated_reserved_wl) { + assert(NULL != cur_sram_orgz_info); + + /* According to the type, we allocate structs */ + switch (cur_sram_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + break; + case SPICE_SRAM_SCAN_CHAIN: + break; + case SPICE_SRAM_MEMORY_BANK: + update_mem_bank_info_reserved_blwl(cur_sram_orgz_info->mem_bank_info, + updated_reserved_bl, updated_reserved_wl); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", + __FILE__, __LINE__ ); + exit(1); + } + + return; +} + +void get_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info, + int* num_reserved_bl, int* num_reserved_wl) { + assert(NULL != cur_sram_orgz_info); + + /* According to the type, we allocate structs */ + switch (cur_sram_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + break; + case SPICE_SRAM_SCAN_CHAIN: + break; + case SPICE_SRAM_MEMORY_BANK: + get_mem_bank_info_reserved_blwl(cur_sram_orgz_info->mem_bank_info, + num_reserved_bl, num_reserved_wl); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", + __FILE__, __LINE__ ); + exit(1); + } + + return; +} + +void get_sram_orgz_info_num_blwl(t_sram_orgz_info* cur_sram_orgz_info, + int* cur_bl, int* cur_wl) { + assert(NULL != cur_bl); + assert(NULL != cur_wl); + assert(NULL != cur_sram_orgz_info); + + /* According to the type, we allocate structs */ + switch (cur_sram_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + case SPICE_SRAM_SCAN_CHAIN: + (*cur_bl) = 0; + (*cur_wl) = 0; + break; + case SPICE_SRAM_MEMORY_BANK: + (*cur_bl) = cur_sram_orgz_info->mem_bank_info->num_bl; + (*cur_wl) = cur_sram_orgz_info->mem_bank_info->num_wl; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", + __FILE__, __LINE__ ); + exit(1); + } + + return; +} + +int get_sram_orgz_info_num_mem_bit(t_sram_orgz_info* cur_sram_orgz_info) { + + assert(NULL != cur_sram_orgz_info); + + /* According to the type, we allocate structs */ + switch (cur_sram_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + return cur_sram_orgz_info->standalone_sram_info->num_mem_bit; + case SPICE_SRAM_SCAN_CHAIN: + return cur_sram_orgz_info->scff_info->num_mem_bit; + case SPICE_SRAM_MEMORY_BANK: + return cur_sram_orgz_info->mem_bank_info->num_mem_bit; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", + __FILE__, __LINE__ ); + exit(1); + } + + return 0; +} + +void update_sram_orgz_info_num_mem_bit(t_sram_orgz_info* cur_sram_orgz_info, + int new_num_mem_bit) { + + assert(NULL != cur_sram_orgz_info); + + /* According to the type, we allocate structs */ + switch (cur_sram_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + update_standalone_sram_info_num_mem_bit(cur_sram_orgz_info->standalone_sram_info, new_num_mem_bit); + break; + case SPICE_SRAM_SCAN_CHAIN: + update_scff_info_num_mem_bit(cur_sram_orgz_info->scff_info, new_num_mem_bit); + break; + case SPICE_SRAM_MEMORY_BANK: + update_mem_bank_info_num_mem_bit(cur_sram_orgz_info->mem_bank_info, new_num_mem_bit); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", + __FILE__, __LINE__ ); + exit(1); + } + + return; +} + +void update_sram_orgz_info_num_blwl(t_sram_orgz_info* cur_sram_orgz_info, + int new_bl, int new_wl) { + + assert(NULL != cur_sram_orgz_info); + + /* According to the type, we allocate structs */ + switch (cur_sram_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + break; + case SPICE_SRAM_SCAN_CHAIN: + break; + case SPICE_SRAM_MEMORY_BANK: + update_mem_bank_info_num_blwl(cur_sram_orgz_info->mem_bank_info, new_bl, new_wl); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", + __FILE__, __LINE__ ); + exit(1); + } + + return; +} + +void get_sram_orgz_info_mem_model(t_sram_orgz_info* cur_sram_orgz_info, + t_spice_model** mem_model_ptr) { + + assert(NULL != cur_sram_orgz_info); + assert(NULL != mem_model_ptr); + + /* According to the type, we allocate structs */ + switch (cur_sram_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + (*mem_model_ptr) = cur_sram_orgz_info->standalone_sram_info->mem_model; + break; + case SPICE_SRAM_SCAN_CHAIN: + (*mem_model_ptr) = cur_sram_orgz_info->scff_info->mem_model; + break; + case SPICE_SRAM_MEMORY_BANK: + (*mem_model_ptr) = cur_sram_orgz_info->mem_bank_info->mem_model; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", + __FILE__, __LINE__ ); + exit(1); + } + + assert(NULL != (*mem_model_ptr)); + + return; +} + +/* Manipulating functions for struct t_reserved_syntax_char */ +void init_reserved_syntax_char(t_reserved_syntax_char* cur_reserved_syntax_char, + char cur_syntax_char, boolean cur_verilog_reserved, boolean cur_spice_reserved) { + assert(NULL != cur_reserved_syntax_char); + + cur_reserved_syntax_char->syntax_char = cur_syntax_char; + cur_reserved_syntax_char->verilog_reserved = cur_verilog_reserved; + cur_reserved_syntax_char->spice_reserved = cur_spice_reserved; + + return; +} + +void check_mem_model_blwl_inverted(t_spice_model* cur_mem_model, + enum e_spice_model_port_type blwl_port_type, + boolean* blwl_inverted) { + int num_blwl_ports = 0; + t_spice_model_port** blwl_port = NULL; + + /* Check */ + assert((SPICE_MODEL_PORT_BL == blwl_port_type)||(SPICE_MODEL_PORT_WL == blwl_port_type)); + + /* Find BL and WL ports */ + blwl_port = find_spice_model_ports(cur_mem_model, blwl_port_type, &num_blwl_ports, TRUE); + + /* If we cannot find any return with warnings */ + if (0 == num_blwl_ports) { + (*blwl_inverted) = FALSE; + vpr_printf(TIO_MESSAGE_WARNING, "(FILE:%s,[LINE%d])Unable to find any BL/WL port for memory model(%s)!\n", + __FILE__, __LINE__, cur_mem_model->name); + return; + } + + /* Only 1 port should be found */ + assert(1 == num_blwl_ports); + /* And port size should be at least 1 */ + assert(0 < blwl_port[0]->size); + + /* if default value of a BL/WL port is 0, we do not need an inversion. */ + if (0 == blwl_port[0]->default_val) { + (*blwl_inverted) = FALSE; + } else { + /* if default value of a BL/WL port is 1, we need an inversion! */ + assert(1 == blwl_port[0]->default_val); + (*blwl_inverted) = TRUE; + } + + return; +} + +/* Useful functions for MUX architecture */ +void init_spice_mux_arch(t_spice_model* spice_model, + t_spice_mux_arch* spice_mux_arch, + int mux_size) { + int cur; + int i; + /* Make sure we have a valid pointer*/ + if (NULL == spice_mux_arch) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d])Invalid spice_mux_arch!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Basic info*/ + spice_mux_arch->structure = spice_model->design_tech_info.structure; + spice_mux_arch->num_input = mux_size; + /* For different structure */ + switch (spice_model->design_tech_info.structure) { + case SPICE_MODEL_STRUCTURE_TREE: + spice_mux_arch->num_level = determine_tree_mux_level(spice_mux_arch->num_input); + spice_mux_arch->num_input_basis = 2; + /* Determine the level and index of per MUX inputs*/ + spice_mux_arch->num_input_last_level = tree_mux_last_level_input_num(spice_mux_arch->num_level, mux_size); + break; + case SPICE_MODEL_STRUCTURE_ONELEVEL: + spice_mux_arch->num_level = 1; + spice_mux_arch->num_input_basis = mux_size; + /* Determine the level and index of per MUX inputs*/ + spice_mux_arch->num_input_last_level = mux_size; + break; + case SPICE_MODEL_STRUCTURE_MULTILEVEL: + /* Handle speical case: input size is 2 */ + if (2 == mux_size) { + spice_mux_arch->num_level = 1; + } else { + spice_mux_arch->num_level = spice_model->design_tech_info.mux_num_level; + } + spice_mux_arch->num_input_basis = determine_num_input_basis_multilevel_mux(mux_size, spice_mux_arch->num_level); + /* Determine the level and index of per MUX inputs*/ + spice_mux_arch->num_input_last_level = multilevel_mux_last_level_input_num(spice_mux_arch->num_level, spice_mux_arch->num_input_basis, mux_size); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n", + __FILE__, __LINE__, spice_model->name); + exit(1); + } + + /* Alloc*/ + spice_mux_arch->num_input_per_level = (int*) my_malloc(sizeof(int)*spice_mux_arch->num_level); + spice_mux_arch->input_level = (int*)my_malloc(sizeof(int)*spice_mux_arch->num_input); + spice_mux_arch->input_offset = (int*)my_malloc(sizeof(int)*spice_mux_arch->num_input); + + /* Assign inputs info for the last level first */ + for (i = 0; i < spice_mux_arch->num_input_last_level; i++) { + spice_mux_arch->input_level[i] = spice_mux_arch->num_level; + spice_mux_arch->input_offset[i] = i; + } + /* For the last second level*/ + if (spice_mux_arch->num_input > spice_mux_arch->num_input_last_level) { + cur = spice_mux_arch->num_input_last_level/spice_mux_arch->num_input_basis; + /* Start from the input ports that are not occupied by the last level + * last level has (cur) outputs + */ + for (i = spice_mux_arch->num_input_last_level; i < spice_mux_arch->num_input; i++) { + spice_mux_arch->input_level[i] = spice_mux_arch->num_level - 1; + spice_mux_arch->input_offset[i] = cur; + cur++; + } + assert((cur < (int)pow((double)spice_mux_arch->num_input_basis, (double)(spice_mux_arch->num_level-1))) + ||(cur == (int)pow((double)spice_mux_arch->num_input_basis, (double)(spice_mux_arch->num_level-1)))); + } + /* Fill the num_input_per_level*/ + for (i = 0; i < spice_mux_arch->num_level; i++) { + cur = i+1; + spice_mux_arch->num_input_per_level[i] = (int)pow((double)spice_mux_arch->num_input_basis, (double)cur); + if ((cur == spice_mux_arch->num_level) + &&(spice_mux_arch->num_input_last_level < spice_mux_arch->num_input_per_level[i])) { + spice_mux_arch->num_input_per_level[i] = spice_mux_arch->num_input_last_level; + } + } + + return; +} + +/* Determine if we need a speical basis. + * If we need one, we give the MUX size of this special basis + */ +int find_spice_mux_arch_special_basis_size(t_spice_mux_arch spice_mux_arch) { + int im; + int mux_size = spice_mux_arch.num_input; + int num_input_basis = spice_mux_arch.num_input_basis; + int num_input_special_basis = 0; + int special_basis_start = 0; + + /* For different structure */ + switch (spice_mux_arch.structure) { + case SPICE_MODEL_STRUCTURE_TREE: + break; + case SPICE_MODEL_STRUCTURE_ONELEVEL: + break; + case SPICE_MODEL_STRUCTURE_MULTILEVEL: + special_basis_start = mux_size - mux_size % num_input_basis; + for (im = special_basis_start; im < mux_size; im++) { + if (spice_mux_arch.num_level == spice_mux_arch.input_level[im]) { + num_input_special_basis++; + } + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice_mux_arch!\n", + __FILE__, __LINE__); + exit(1); + } + + return num_input_special_basis; +} + +/* Search the linked list, if we have the same mux size and spice_model + * return 1, if not we return 0 + */ +t_llist* search_mux_linked_list(t_llist* mux_head, + int mux_size, + t_spice_model* spice_model) { + t_llist* temp = mux_head; + t_spice_mux_model* cur_mux = NULL; + /* traversal the linked list*/ + while(temp) { + cur_mux = (t_spice_mux_model*)(temp->dptr); + if ((cur_mux->size == mux_size) + &&(spice_model == cur_mux->spice_model)) { + return temp; + } + /* next */ + temp = temp->next; + } + + return NULL; +} + +/* Check the linked list if we have a mux stored with same spice model + * if not, we create a new one. + */ +void check_and_add_mux_to_linked_list(t_llist** muxes_head, + int mux_size, + t_spice_model* spice_model) { + t_spice_mux_model* cur_mux = NULL; + t_llist* temp = NULL; + + /* Check code: to avoid mistake, we should check the mux size + * the mux_size should be at least 2 so that we need a mux + */ + if (mux_size < 2) { + printf("Warning:(File:%s,LINE[%d]) ilegal mux size (%d), expect to be at least 2!\n", + __FILE__, __LINE__, mux_size); + return; + } + + /* Search the linked list */ + if (NULL != search_mux_linked_list((*muxes_head),mux_size,spice_model)) { + /* We find one, there is no need to create a new one*/ + return; + } + /*Create a linked list, if head is NULL*/ + if (NULL == (*muxes_head)) { + (*muxes_head) = create_llist(1); + (*muxes_head)->dptr = my_malloc(sizeof(t_spice_mux_model)); + cur_mux = (t_spice_mux_model*)((*muxes_head)->dptr); + } else { + /* We have to create a new elment in linked list*/ + temp = insert_llist_node((*muxes_head)); + temp->dptr = my_malloc(sizeof(t_spice_mux_model)); + cur_mux = (t_spice_mux_model*)(temp->dptr); + } + /* Fill the new SPICE MUX Model*/ + cur_mux->size = mux_size; + cur_mux->spice_model = spice_model; + cur_mux->cnt = 1; /* Initialize the counter*/ + + return; +} + +/* Free muxes linked list + */ +void free_muxes_llist(t_llist* muxes_head) { + t_llist* temp = muxes_head; + while(temp) { + /* Free the mux_spice_model, remember to set the pointer to NULL */ + free(temp->dptr); + temp->dptr = NULL; + /* Move on to the next pointer*/ + temp = temp->next; + } + free_llist(muxes_head); + return; +} + + + + +/* Stats the multiplexer sizes and structure in the global routing architecture*/ +void stats_spice_muxes_routing_arch(t_llist** muxes_head, + int num_switch, + t_switch_inf* switches, + t_spice* spice, + t_det_routing_arch* routing_arch) { + int inode; + t_rr_node* node; + t_spice_model* sb_switch_spice_model = NULL; + t_spice_model* cb_switch_spice_model = NULL; + + /* Current Version: Support Uni-directional routing architecture only*/ + if (UNI_DIRECTIONAL != routing_arch->directionality) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d])Spice Modeling Only support uni-directional routing architecture.\n",__FILE__, __LINE__); + exit(1); + } + + /* The routing path is. + * OPIN ----> CHAN ----> ... ----> CHAN ----> IPIN + * Each edge is a switch, for IPIN, the switch is a connection block, + * for the rest is a switch box + */ + /* Count the sizes of muliplexers in routing architecture */ + /* Visit the global variable : num_rr_nodes, rr_node */ + for (inode = 0; inode < num_rr_nodes; inode++) { + node = &rr_node[inode]; + switch (node->type) { + case IPIN: + /* Have to consider the fan_in only, it is a connection box(multiplexer)*/ + assert((node->fan_in > 0)||(0 == node->fan_in)); + if (0 == node->fan_in) { + break; + } + /* Find the spice_model for multiplexers in connection blocks */ + cb_switch_spice_model = switches[node->driver_switch].spice_model; + /* we should select a spice model for the connection box*/ + assert(NULL != cb_switch_spice_model); + check_and_add_mux_to_linked_list(muxes_head, node->fan_in,cb_switch_spice_model); + break; + case CHANX: + case CHANY: + /* Channels are the same, have to consider the fan_in as well, + * it could be a switch box if previous rr_node is a channel + * or it could be a connection box if previous rr_node is a IPIN or OPIN + */ + assert((node->fan_in > 0)||(0 == node->fan_in)); + if (0 == node->fan_in) { + break; + } + /* Find the spice_model for multiplexers in switch blocks*/ + sb_switch_spice_model = switches[node->driver_switch].spice_model; + /* we should select a spice model for the Switch box*/ + assert(NULL != sb_switch_spice_model); + check_and_add_mux_to_linked_list(muxes_head, node->fan_in,sb_switch_spice_model); + break; + case OPIN: + /* Actually, in single driver routing architecture, the OPIN, source of a routing path, + * is directly connected to Switch Box multiplexers + */ + break; + default: + break; + } + } + + return; +} + +/* Recursively do statistics for the + * multiplexer spice models inside pb_types + */ +void stats_mux_spice_model_pb_type_rec(t_llist** muxes_head, + t_pb_type* cur_pb_type) { + + int imode, ichild, jinterc; + t_spice_model* interc_spice_model = NULL; + + if (NULL == cur_pb_type) { + vpr_printf(TIO_MESSAGE_WARNING,"(File:%s,LINE[%d])cur_pb_type is null pointor!\n",__FILE__,__LINE__); + return; + } + + /* If there is spice_model_name, this is a leaf node!*/ + if (NULL != cur_pb_type->spice_model_name) { + /* What annoys me is VPR create a sub pb_type for each lut which suppose to be a leaf node + * This may bring software convience but ruins SPICE modeling + */ + assert(NULL != cur_pb_type->spice_model); + return; + } + /* Traversal the hierarchy*/ + for (imode = 0; imode < cur_pb_type->num_modes; imode++) { + /* Then we have to statisitic the interconnections*/ + for (jinterc = 0; jinterc < cur_pb_type->modes[imode].num_interconnect; jinterc++) { + /* Check the num_mux and fan_in*/ + assert((0 == cur_pb_type->modes[imode].interconnect[jinterc].num_mux) + ||(0 < cur_pb_type->modes[imode].interconnect[jinterc].num_mux)); + if (0 == cur_pb_type->modes[imode].interconnect[jinterc].num_mux) { + continue; + } + interc_spice_model = cur_pb_type->modes[imode].interconnect[jinterc].spice_model; + assert(NULL != interc_spice_model); + check_and_add_mux_to_linked_list(muxes_head, + cur_pb_type->modes[imode].interconnect[jinterc].fan_in, + interc_spice_model); + } + for (ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ichild++) { + stats_mux_spice_model_pb_type_rec(muxes_head, + &cur_pb_type->modes[imode].pb_type_children[ichild]); + } + } + return; +} + +/* Statistics the MUX SPICE MODEL with the help of pb_graph + * Not the most efficient function to finish the job + * Abandon it. But remains a good framework that could be re-used in connecting + * spice components together + */ +void stats_mux_spice_model_pb_node_rec(t_llist** muxes_head, + t_pb_graph_node* cur_pb_node) { + int imode, ipb, ichild, iport, ipin; + t_pb_type* cur_pb_type = cur_pb_node->pb_type; + t_spice_model* interc_spice_model = NULL; + enum e_interconnect pin_interc_type; + + if (NULL == cur_pb_node) { + vpr_printf(TIO_MESSAGE_WARNING,"(File:%s,LINE[%d])cur_pb_node is null pointor!\n",__FILE__,__LINE__); + return; + } + + if (NULL == cur_pb_type) { + vpr_printf(TIO_MESSAGE_WARNING,"(File:%s,LINE[%d])cur_pb_type is null pointor!\n",__FILE__,__LINE__); + return; + } + + /* If there is 0 mode, this is a leaf node!*/ + if (NULL != cur_pb_type->blif_model) { + assert(0 == cur_pb_type->num_modes); + assert(NULL == cur_pb_type->modes); + /* Ensure there is blif_model, and spice_model*/ + assert(NULL != cur_pb_type->model); + assert(NULL != cur_pb_type->spice_model_name); + assert(NULL != cur_pb_type->spice_model); + return; + } + /* Traversal the hierarchy*/ + for (imode = 0; imode < cur_pb_type->num_modes; imode++) { + /* Then we have to statisitic the interconnections*/ + /* See the input ports*/ + for (iport = 0; iport < cur_pb_node->num_input_ports; iport++) { + for (ipin = 0; ipin < cur_pb_node->num_input_pins[iport]; ipin++) { + /* Ensure this is an input port */ + assert(IN_PORT == cur_pb_node->input_pins[iport][ipin].port->type); + /* See the edges, if the interconnetion type infer a MUX, we go next step*/ + pin_interc_type = find_pb_graph_pin_in_edges_interc_type(cur_pb_node->input_pins[iport][ipin]); + if ((COMPLETE_INTERC != pin_interc_type)&&(MUX_INTERC != pin_interc_type)) { + continue; + } + /* We shoule check the size of inputs, in some case of complete, the input_edge is one...*/ + if ((COMPLETE_INTERC == pin_interc_type)&&(1 == cur_pb_node->input_pins[iport][ipin].num_input_edges)) { + continue; + } + /* Note: i do care the input_edges only! They may infer multiplexers*/ + interc_spice_model = find_pb_graph_pin_in_edges_interc_spice_model(cur_pb_node->input_pins[iport][ipin]); + check_and_add_mux_to_linked_list(muxes_head, + cur_pb_node->input_pins[iport][ipin].num_input_edges, + interc_spice_model); + } + } + /* See the output ports*/ + for (iport = 0; iport < cur_pb_node->num_output_ports; iport++) { + for (ipin = 0; ipin < cur_pb_node->num_output_pins[iport]; ipin++) { + /* Ensure this is an input port */ + assert(OUT_PORT == cur_pb_node->output_pins[iport][ipin].port->type); + /* See the edges, if the interconnetion type infer a MUX, we go next step*/ + pin_interc_type = find_pb_graph_pin_in_edges_interc_type(cur_pb_node->output_pins[iport][ipin]); + if ((COMPLETE_INTERC != pin_interc_type)&&(MUX_INTERC != pin_interc_type)) { + continue; + } + /* We shoule check the size of inputs, in some case of complete, the input_edge is one...*/ + if ((COMPLETE_INTERC == pin_interc_type)&&(1 == cur_pb_node->output_pins[iport][ipin].num_input_edges)) { + continue; + } + /* Note: i do care the input_edges only! They may infer multiplexers*/ + interc_spice_model = find_pb_graph_pin_in_edges_interc_spice_model(cur_pb_node->output_pins[iport][ipin]); + check_and_add_mux_to_linked_list(muxes_head, + cur_pb_node->output_pins[iport][ipin].num_input_edges, + interc_spice_model); + } + } + /* See the clock ports*/ + for (iport = 0; iport < cur_pb_node->num_clock_ports; iport++) { + for (ipin = 0; ipin < cur_pb_node->num_clock_pins[iport]; ipin++) { + /* Ensure this is an input port */ + assert(IN_PORT == cur_pb_node->clock_pins[iport][ipin].port->type); + /* See the edges, if the interconnetion type infer a MUX, we go next step*/ + pin_interc_type = find_pb_graph_pin_in_edges_interc_type(cur_pb_node->clock_pins[iport][ipin]); + if ((COMPLETE_INTERC != pin_interc_type)&&(MUX_INTERC != pin_interc_type)) { + continue; + } + /* We shoule check the size of inputs, in some case of complete, the input_edge is one...*/ + if ((COMPLETE_INTERC == pin_interc_type)&&(1 == cur_pb_node->clock_pins[iport][ipin].num_input_edges)) { + continue; + } + /* Note: i do care the input_edges only! They may infer multiplexers*/ + interc_spice_model = find_pb_graph_pin_in_edges_interc_spice_model(cur_pb_node->clock_pins[iport][ipin]); + check_and_add_mux_to_linked_list(muxes_head, + cur_pb_node->clock_pins[iport][ipin].num_input_edges, + interc_spice_model); + } + } + for (ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ichild++) { + /* num_pb is the number of such pb_type in a mode*/ + for (ipb = 0; ipb < cur_pb_type->modes[imode].pb_type_children[ichild].num_pb; ipb++) { + /* child_pb_grpah_nodes: [0..num_modes-1][0..num_pb_type_in_mode-1][0..num_pb_type-1]*/ + stats_mux_spice_model_pb_node_rec(muxes_head, + &cur_pb_node->child_pb_graph_nodes[imode][ichild][ipb]); + } + } + } + return; +} + + +/* Statistic for all the multiplexers in FPGA + * We determine the sizes and its structure (according to spice_model) for each type of multiplexers + * We search multiplexers in Switch Blocks, Connection blocks and Configurable Logic Blocks + * In additional to multiplexers, this function also consider crossbars. + * All the statistics are stored in a linked list, as a return value + */ +t_llist* stats_spice_muxes(int num_switches, + t_switch_inf* switches, + t_spice* spice, + t_det_routing_arch* routing_arch) { + int iedge; + int itype; + int imodel; + /* Linked-list to store the information of Multiplexers*/ + t_llist* muxes_head = NULL; + + /* Step 1: We should check the multiplexer spice models defined in routing architecture.*/ + stats_spice_muxes_routing_arch(&muxes_head, num_switches, switches, spice, routing_arch); + + /* Statistics after search routing resources */ + /* + temp = muxes_head; + while(temp) { + t_spice_mux_model* spice_mux_model = (t_spice_mux_model*)temp->dptr; + vpr_printf(TIO_MESSAGE_INFO,"Routing multiplexers: size=%d\n",spice_mux_model->size); + temp = temp->next; + } + */ + + /* Step 2: Count the sizes of multiplexers in complex logic blocks */ + for (itype = 0; itype < num_types; itype++) { + if (NULL != type_descriptors[itype].pb_type) { + stats_mux_spice_model_pb_type_rec(&muxes_head,type_descriptors[itype].pb_type); + } + } + + /* Step 3: count the size of multiplexer that will be used in LUTs*/ + for (imodel = 0; imodel < spice->num_spice_model; imodel++) { + /* For those LUTs that netlists are not provided. We create a netlist and thus need a MUX*/ + if ((SPICE_MODEL_LUT == spice->spice_models[imodel].type) + &&(NULL == spice->spice_models[imodel].model_netlist)) { + stats_lut_spice_mux(&muxes_head, &(spice->spice_models[imodel])); + } + } + + /* Statistics after search routing resources */ + /* + temp = muxes_head; + while(temp) { + t_spice_mux_model* spice_mux_model = (t_spice_mux_model*)temp->dptr; + vpr_printf(TIO_MESSAGE_INFO,"Pb_types multiplexers: size=%d\n",spice_mux_model->size); + temp = temp->next; + } + */ + + return muxes_head; +} + +/* Find the interconnection type of pb_graph_pin edges*/ +enum e_interconnect find_pb_graph_pin_in_edges_interc_type(t_pb_graph_pin pb_graph_pin) { + enum e_interconnect interc_type; + int def_interc_type = 0; + int iedge; + + for (iedge = 0; iedge < pb_graph_pin.num_input_edges; iedge++) { + /* Make sure all edges are legal: 1 input_pin, 1 output_pin*/ + check_pb_graph_edge(*(pb_graph_pin.input_edges[iedge])); + /* Make sure all the edges interconnect type is the same*/ + if (0 == def_interc_type) { + interc_type = pb_graph_pin.input_edges[iedge]->interconnect->type; + } else if (interc_type != pb_graph_pin.input_edges[iedge]->interconnect->type) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d])Interconnection type are not same for port(%s),pin(%d).\n", + __FILE__, __LINE__, pb_graph_pin.port->name,pb_graph_pin.pin_number); + exit(1); + } + } + + return interc_type; +} + +/* Find the interconnection type of pb_graph_pin edges*/ +t_spice_model* find_pb_graph_pin_in_edges_interc_spice_model(t_pb_graph_pin pb_graph_pin) { + t_spice_model* interc_spice_model; + int def_interc_model = 0; + int iedge; + + for (iedge = 0; iedge < pb_graph_pin.num_input_edges; iedge++) { + /* Make sure all edges are legal: 1 input_pin, 1 output_pin*/ + check_pb_graph_edge(*(pb_graph_pin.input_edges[iedge])); + /* Make sure all the edges interconnect type is the same*/ + if (0 == def_interc_model) { + interc_spice_model= pb_graph_pin.input_edges[iedge]->interconnect->spice_model; + } else if (interc_spice_model != pb_graph_pin.input_edges[iedge]->interconnect->spice_model) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d])Interconnection spice_model are not same for port(%s),pin(%d).\n", + __FILE__, __LINE__, pb_graph_pin.port->name,pb_graph_pin.pin_number); + exit(1); + } + } + + return interc_spice_model; +} + +int find_path_id_between_pb_rr_nodes(t_rr_node* local_rr_graph, + int src_node, + int des_node) { + int path_id = -1; + int prev_edge = -1; + int path_count = 0; + int iedge; + t_interconnect* cur_interc = NULL; + + /* Check */ + assert(NULL != local_rr_graph); + assert((0 == src_node)||(0 < src_node)); + assert((0 == des_node)||(0 < des_node)); + + prev_edge = local_rr_graph[des_node].prev_edge; + check_pb_graph_edge(*(local_rr_graph[src_node].pb_graph_pin->output_edges[prev_edge])); + assert(local_rr_graph[src_node].pb_graph_pin->output_edges[prev_edge]->output_pins[0] == local_rr_graph[des_node].pb_graph_pin); + + cur_interc = local_rr_graph[src_node].pb_graph_pin->output_edges[prev_edge]->interconnect; + /* Search des_node input edges */ + for (iedge = 0; iedge < local_rr_graph[des_node].pb_graph_pin->num_input_edges; iedge++) { + if (local_rr_graph[des_node].pb_graph_pin->input_edges[iedge]->input_pins[0] + == local_rr_graph[src_node].pb_graph_pin) { + /* Strict check */ + assert(local_rr_graph[src_node].pb_graph_pin->output_edges[prev_edge] + == local_rr_graph[des_node].pb_graph_pin->input_edges[iedge]); + path_id = path_count; + break; + } + if (cur_interc == local_rr_graph[des_node].pb_graph_pin->input_edges[iedge]->interconnect) { + path_count++; + } + } + + return path_id; +} + +/* Return a child_pb if it is mapped.*/ +t_pb* get_child_pb_for_phy_pb_graph_node(t_pb* cur_pb, int ipb, int jpb) { + t_pb* child_pb = NULL; + + /* TODO: more check ? */ + + if (NULL == cur_pb) { + return NULL; + } + + if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { + child_pb = &(cur_pb->child_pbs[ipb][jpb]); + } + + return child_pb; +} + +/* Check if all the SRAM ports have the correct SPICE MODEL */ +void config_spice_models_sram_port_spice_model(int num_spice_model, + t_spice_model* spice_models, + t_spice_model* default_sram_spice_model) { + int i, iport; + + for (i = 0; i < num_spice_model; i++) { + for (iport = 0; iport < spice_models[i].num_port; iport++) { + /* Bypass non SRAM ports */ + if (SPICE_MODEL_PORT_SRAM != spice_models[i].ports[iport].type) { + continue; + } + /* Write for the default SRAM SPICE model! */ + spice_models[i].ports[iport].spice_model = default_sram_spice_model; + /* Only show warning when we try to override the given spice_model_name ! */ + if (NULL == spice_models[i].ports[iport].spice_model_name) { + continue; + } + /* Give a warning !!! */ + if (0 != strcmp(default_sram_spice_model->name, spice_models[i].ports[iport].spice_model_name)) { + vpr_printf(TIO_MESSAGE_WARNING, + "(FILE:%s, LINE[%d]) Overwrite SRAM SPICE MODEL of SPICE model port (name:%s, port:%s) to be the correct one (name:%s)!\n", + __FILE__ ,__LINE__, + spice_models[i].name, + spice_models[i].ports[iport].prefix, + default_sram_spice_model->name); + } + } + } + + return; +} + +t_pb* get_lut_child_pb(t_pb* cur_lut_pb, + int mode_index) { + + assert(SPICE_MODEL_LUT == cur_lut_pb->pb_graph_node->pb_type->spice_model->type); + + assert(1 == cur_lut_pb->pb_graph_node->pb_type->modes[mode_index].num_pb_type_children); + assert(1 == cur_lut_pb->pb_graph_node->pb_type->num_pb); + + return (&(cur_lut_pb->child_pbs[0][0])); +} + +int get_grid_pin_height(int grid_x, int grid_y, int pin_index) { + int pin_height; + t_type_ptr grid_type = NULL; + + /* Get type */ + grid_type = grid[grid_x][grid_y].type; + + /* Return if this is an empty type */ + if ((NULL == grid_type) + ||(EMPTY_TYPE == grid_type)) { + pin_height = 0; + return pin_height; + } + + /* Check if the pin index is in the range */ + assert ( ((0 == pin_index) || (0 < pin_index)) + &&(pin_index < grid_type->num_pins) ); + + /* Find the pin_height */ + pin_height = grid_type->pin_height[pin_index]; + + return pin_height; +} + +void determine_sb_port_coordinator(t_sb cur_sb_info, int side, + int* port_x, int* port_y) { + /* Check */ + assert ((-1 < side) && (side < 4)); + /* Initialize */ + (*port_x) = -1; + (*port_y) = -1; + + switch (side) { + case TOP: + /* (0 == side) */ + /* 1. Channel Y [x][y+1] inputs */ + (*port_x) = cur_sb_info.x; + (*port_y) = cur_sb_info.y + 1; + break; + case RIGHT: + /* 1 == side */ + /* 2. Channel X [x+1][y] inputs */ + (*port_x) = cur_sb_info.x + 1; + (*port_y) = cur_sb_info.y; + break; + case BOTTOM: + /* 2 == side */ + /* 3. Channel Y [x][y] inputs */ + (*port_x) = cur_sb_info.x; + (*port_y) = cur_sb_info.y; + break; + case LEFT: + /* 3 == side */ + /* 4. Channel X [x][y] inputs */ + (*port_x) = cur_sb_info.x; + (*port_y) = cur_sb_info.y; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid side of sb[%d][%d]!\n", + __FILE__, __LINE__, cur_sb_info.x, cur_sb_info.y, side); + exit(1); + } + + return; +} + +void init_spice_models_tb_cnt(int num_spice_models, + t_spice_model* spice_model) { + int imodel; + + for (imodel = 0; imodel < num_spice_models; imodel++) { + spice_model[imodel].tb_cnt = 0; + } + + return; +} + +void init_spice_models_grid_tb_cnt(int num_spice_models, + t_spice_model* spice_model, + int grid_x, int grid_y) { + int imodel; + + for (imodel = 0; imodel < num_spice_models; imodel++) { + spice_model[imodel].tb_cnt = spice_model[imodel].grid_index_low[grid_x][grid_y]; + } + + return; +} + +void check_spice_models_grid_tb_cnt(int num_spice_models, + t_spice_model* spice_model, + int grid_x, int grid_y, + enum e_spice_model_type spice_model_type_to_check) { + int imodel; + + for (imodel = 0; imodel < num_spice_models; imodel++) { + if (spice_model_type_to_check != spice_model[imodel].type) { + continue; + } + assert(spice_model[imodel].tb_cnt = spice_model[imodel].grid_index_high[grid_x][grid_y]); + } + + return; +} + +boolean check_negative_variation(float avg_val, + t_spice_mc_variation_params variation_params) { + boolean exist_neg_val = FALSE; + + /* Assume only support gaussian variation now */ + if (avg_val < 0.) { + exist_neg_val = TRUE; + } + + return exist_neg_val; +} + diff --git a/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_utils.h b/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_utils.h new file mode 100644 index 000000000..9996ebfc2 --- /dev/null +++ b/vpr7_rram/vpr/SRC/fpga_spice/fpga_spice_utils.h @@ -0,0 +1,605 @@ +void my_free(void* ptr); + +char* my_gettime(); + +char* format_dir_path(char* dir_path); + +int try_access_file(char* file_path); + +void my_remove_file(char* file_path); + +int create_dir_path(char* dir_path); + +char* my_strcat(char* str1, + char* str2); + +int split_path_prog_name(char* prog_path, + char split_token, + char** ret_path, + char** ret_prog_name); + +char* chomp_file_name_postfix(char* file_name); + +void fprint_commented_sram_bits(FILE* fp, + int num_sram_bits, int* sram_bits); + +t_spice_model* find_name_matched_spice_model(char* spice_model_name, + int num_spice_model, + t_spice_model* spice_models); + +t_spice_model* get_default_spice_model(enum e_spice_model_type default_spice_model_type, + int num_spice_model, + t_spice_model* spice_models); + +void config_spice_model_input_output_buffers_pass_gate(int num_spice_models, + t_spice_model* spice_model); + +t_spice_model_port** find_spice_model_ports(t_spice_model* spice_model, + enum e_spice_model_port_type port_type, + int* port_num, boolean ignore_global_port); + +t_spice_model_port** find_spice_model_config_done_ports(t_spice_model* spice_model, + enum e_spice_model_port_type port_type, + int* port_num, boolean ignore_global_port); + + +t_spice_transistor_type* find_mosfet_tech_lib(t_spice_tech_lib tech_lib, + e_spice_trans_type trans_type); + +char* my_itoa(int input); + +char* chomp_spice_node_prefix(char* spice_node_prefix); + +char* format_spice_node_prefix(char* spice_node_prefix); + +t_port* find_pb_type_port_match_spice_model_port(t_pb_type* pb_type, + t_spice_model_port* spice_model_port); + +char* format_spice_node_prefix(char* spice_node_prefix); + +t_port** find_pb_type_ports_match_spice_model_port_type(t_pb_type* pb_type, + enum e_spice_model_port_type port_type, + int* port_num); + + +t_block* search_mapped_block(int x, int y, int z); + + +int determine_num_sram_bits_mux_basis_subckt(t_spice_model* mux_spice_model, + int mux_size, + int num_input_per_level, + boolean special_basis); + +int determine_tree_mux_level(int mux_size); + +int determine_num_input_basis_multilevel_mux(int mux_size, + int mux_level); + +int tree_mux_last_level_input_num(int num_level, + int mux_size); + +int multilevel_mux_last_level_input_num(int num_level, int num_input_per_unit, + int mux_size); + +int determine_lut_path_id(int lut_size, + int* lut_inputs); + +int* decode_onelevel_mux_sram_bits(int fan_in, + int mux_level, + int path_id); + +int* decode_multilevel_mux_sram_bits(int fan_in, + int mux_level, + int path_id); + +int* decode_tree_mux_sram_bits(int fan_in, + int mux_level, + int path_id); + +void decode_cmos_mux_sram_bits(t_spice_model* mux_spice_model, + int mux_size, int path_id, + int* bit_len, int** conf_bits, int* mux_level); + +char** my_strtok(char* str, + char* delims, + int* len); + +char* convert_side_index_to_string(int side); + +char* convert_chan_type_to_string(t_rr_type chan_type); + +char* convert_chan_rr_node_direction_to_string(enum PORTS chan_rr_node_direction); + +void init_spice_net_info(t_spice_net_info* spice_net_info); + +t_spice_model* find_iopad_spice_model(int num_spice_model, + t_spice_model* spice_models); + +char* generate_string_spice_model_type(enum e_spice_model_type spice_model_type); + +int determine_io_grid_side(int x, + int y); + +void find_prev_rr_nodes_with_src(t_rr_node* src_rr_node, + int* num_drive_rr_nodes, + t_rr_node*** drive_rr_nodes, + int** switch_indices); + +int find_path_id_prev_rr_node(int num_drive_rr_nodes, + t_rr_node** drive_rr_nodes, + t_rr_node* src_rr_node); + +int pb_pin_net_num(t_rr_node* pb_rr_graph, + t_pb_graph_pin* pin); + +float pb_pin_density(t_rr_node* pb_rr_graph, + t_pb_graph_pin* pin); + +float pb_pin_probability(t_rr_node* pb_rr_graph, + t_pb_graph_pin* pin); + +int pb_pin_init_value(t_rr_node* pb_rr_graph, + t_pb_graph_pin* pin); + +float get_rr_node_net_density(t_rr_node node); + +float get_rr_node_net_probability(t_rr_node node); + +int get_rr_node_net_init_value(t_rr_node node); + + +int find_parent_pb_type_child_index(t_pb_type* parent_pb_type, + int mode_index, + t_pb_type* child_pb_type); + +void gen_spice_name_tag_pb_rec(t_pb* cur_pb, + char* prefix); + +void gen_spice_name_tags_all_pbs(); + +void check_pb_graph_edge(t_pb_graph_edge pb_graph_edge); + +void check_pb_graph_pin_edges(t_pb_graph_pin pb_graph_pin); + +void backup_one_pb_rr_node_pack_prev_node_edge(t_rr_node* pb_rr_node); + +void update_one_grid_pack_prev_node_edge(int x, int y); + +void update_grid_pbs_post_route_rr_graph(); + +int find_pb_mapped_logical_block_rec(t_pb* cur_pb, + t_spice_model* pb_spice_model, + char* pb_spice_name_tag); + +int find_grid_mapped_logical_block(int x, int y, + t_spice_model* pb_spice_model, + char* pb_spice_name_tag); + +void stats_pb_graph_node_port_pin_numbers(t_pb_graph_node* cur_pb_graph_node, + int* num_inputs, + int* num_outputs, + int* num_clock_pins); + +void map_clb_pins_to_pb_graph_pins(); + +int recommend_num_sim_clock_cycle(); + +void auto_select_num_sim_clock_cycle(t_spice* spice, + float signal_density_weight); + +void alloc_spice_model_grid_index_low_high(t_spice_model* cur_spice_model); + +void free_one_spice_model_grid_index_low_high(t_spice_model* cur_spice_model); + +void free_spice_model_grid_index_low_high(int num_spice_models, + t_spice_model* spice_model); + +void update_one_spice_model_grid_index_low(int x, int y, + t_spice_model* cur_spice_model); + +void update_spice_models_grid_index_low(int x, int y, + int num_spice_models, + t_spice_model* spice_model); + +void update_one_spice_model_grid_index_high(int x, int y, + t_spice_model* cur_spice_model); + +void update_spice_models_grid_index_high(int x, int y, + int num_spice_models, + t_spice_model* spice_model); + +void zero_one_spice_model_grid_index_low_high(t_spice_model* cur_spice_model); + +void zero_spice_model_grid_index_low_high(int num_spice_models, + t_spice_model* spice_model); + +char* gen_str_spice_model_structure(enum e_spice_model_structure spice_model_structure); + +boolean check_spice_model_structure_match_switch_inf(t_switch_inf target_switch_inf); + +int find_pb_type_idle_mode_index(t_pb_type cur_pb_type); + +int find_pb_type_physical_mode_index(t_pb_type cur_pb_type); + +void mark_grid_type_pb_graph_node_pins_temp_net_num(int x, int y); + +void assign_pb_graph_node_pin_temp_net_num_by_mode_index(t_pb_graph_pin* cur_pb_graph_pin, + int mode_index); + +void mark_pb_graph_node_input_pins_temp_net_num(t_pb_graph_node* cur_pb_graph_node, + int mode_index); + +void mark_pb_graph_node_clock_pins_temp_net_num(t_pb_graph_node* cur_pb_graph_node, + int mode_index); + +void mark_pb_graph_node_output_pins_temp_net_num(t_pb_graph_node* cur_pb_graph_node, + int mode_index); + +void rec_mark_pb_graph_node_temp_net_num(t_pb_graph_node* cur_pb_graph_node); + +void load_one_pb_graph_pin_temp_net_num_from_pb(t_pb* cur_pb, + t_pb_graph_pin* cur_pb_graph_pin); + +void load_pb_graph_node_temp_net_num_from_pb(t_pb* cur_pb); + +void rec_mark_one_pb_unused_pb_graph_node_temp_net_num(t_pb* cur_pb); + +void update_pb_vpack_net_num_from_temp_net_num(t_pb* cur_pb, + t_pb_graph_pin* cur_pb_graph_pin); + +void update_pb_graph_node_temp_net_num_to_pb(t_pb_graph_node* cur_pb_graph_node, + t_pb* cur_pb); + +void rec_load_unused_pb_graph_node_temp_net_num_to_pb(t_pb* cur_pb); + +void mark_one_pb_parasitic_nets(t_pb* cur_pb); + +void init_rr_nodes_vpack_net_num_changed(int LL_num_rr_nodes, + t_rr_node* LL_rr_node); + +boolean is_net_pi(t_net* cur_net); + +int check_consistency_logical_block_net_num(t_logical_block* lgk_blk, + int num_inputs, int* input_net_num); + +int rr_node_drive_switch_box(t_rr_node* src_rr_node, + t_rr_node* des_rr_node, + int switch_box_x, + int switch_box_y, + int chan_side); + +void find_drive_rr_nodes_switch_box(int switch_box_x, + int switch_box_y, + t_rr_node* src_rr_node, + int chan_side, + int return_num_only, + int* num_drive_rr_nodes, + t_rr_node*** drive_rr_nodes, + int* switch_index); + +int is_sb_interc_between_segments(int switch_box_x, + int switch_box_y, + t_rr_node* src_rr_node, + int chan_side); + +int count_num_sram_bits_one_spice_model(t_spice_model* cur_spice_model, + int mux_size); + +int count_num_conf_bits_one_spice_model(t_spice_model* cur_spice_model, + enum e_sram_orgz cur_sram_orgz_type, + int mux_size); + +int count_num_reserved_conf_bits_one_lut_spice_model(t_spice_model* cur_spice_model, + enum e_sram_orgz cur_sram_orgz_type); + +int count_num_reserved_conf_bits_one_mux_spice_model(t_spice_model* cur_spice_model, + enum e_sram_orgz cur_sram_orgz_type, + int mux_size); + +int count_num_reserved_conf_bits_one_rram_sram_spice_model(t_spice_model* cur_spice_model, + enum e_sram_orgz cur_sram_orgz_type); + +int count_num_reserved_conf_bits_one_spice_model(t_spice_model* cur_spice_model, + enum e_sram_orgz cur_sram_orgz_type, + int mux_size); + +int count_num_conf_bit_one_interc(t_interconnect* cur_interc, + enum e_sram_orgz cur_sram_orgz_type); + +int count_num_reserved_conf_bit_one_interc(t_interconnect* cur_interc, + enum e_sram_orgz cur_sram_orgz_type); + +int count_num_conf_bits_pb_type_mode_interc(t_mode* cur_pb_type_mode, + enum e_sram_orgz cur_sram_orgz_type); + +int rec_count_num_conf_bits_pb_type_default_mode(t_pb_type* cur_pb_type, + t_sram_orgz_info* cur_sram_orgz_info); + +int rec_count_num_conf_bits_pb_type_physical_mode(t_pb_type* cur_pb_type, + t_sram_orgz_info* cur_sram_orgz_info); + +int rec_count_num_conf_bits_pb(t_pb* cur_pb, + t_sram_orgz_info* cur_sram_orgz_info); + +void init_one_grid_num_conf_bits(int ix, int iy, + t_sram_orgz_info* cur_sram_orgz_info); + +void init_grids_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info); + +void zero_spice_models_cnt(int num_spice_models, t_spice_model* spice_model); + +void zero_one_spice_model_routing_index_low_high(t_spice_model* cur_spice_model); + +void zero_spice_models_routing_index_low_high(int num_spice_models, + t_spice_model* spice_model); + +void alloc_spice_model_routing_index_low_high(t_spice_model* cur_spice_model); + +void free_one_spice_model_routing_index_low_high(t_spice_model* cur_spice_model); + +void free_spice_model_routing_index_low_high(int num_spice_models, + t_spice_model* spice_model); + +void update_one_spice_model_routing_index_high(int x, int y, t_rr_type chan_type, + t_spice_model* cur_spice_model); + +void update_spice_models_routing_index_high(int x, int y, t_rr_type chan_type, + int num_spice_models, + t_spice_model* spice_model); + +void update_one_spice_model_routing_index_low(int x, int y, t_rr_type chan_type, + t_spice_model* cur_spice_model); + +void update_spice_models_routing_index_low(int x, int y, t_rr_type chan_type, + int num_spice_models, + t_spice_model* spice_model); + +void rec_count_num_iopads_pb_type_physical_mode(t_pb_type* cur_pb_type); + +void rec_count_num_iopads_pb_type_default_mode(t_pb_type* cur_pb_type); + +void rec_count_num_iopads_pb(t_pb* cur_pb); + +void init_one_grid_num_iopads(int ix, int iy); + +void init_grids_num_iopads(); + +void rec_count_num_mode_bits_pb_type_default_mode(t_pb_type* cur_pb_type); + +void rec_count_num_mode_bits_pb(t_pb* cur_pb); + +void init_one_grid_num_mode_bits(int ix, int iy); + +void init_grids_num_mode_bits(); + +void check_sram_spice_model_ports(t_spice_model* cur_spice_model, + boolean include_bl_wl); + +void check_ff_spice_model_ports(t_spice_model* cur_spice_model, + boolean is_scff); + +/* Functions to manipulate t_conf_bit and t_conf_bit_info */ +void free_conf_bit(t_conf_bit* conf_bit); +void free_conf_bit_info(t_conf_bit_info* conf_bit_info); + +t_conf_bit_info* +alloc_one_conf_bit_info(int index, + t_conf_bit* sram_val, + t_conf_bit* bl_val, t_conf_bit* wl_val, + t_spice_model* parent_spice_model); + +t_llist* +add_conf_bit_info_to_llist(t_llist* head, int index, + t_conf_bit* sram_val, t_conf_bit* bl_val, t_conf_bit* wl_val, + t_spice_model* parent_spice_model); + +void +add_mux_scff_conf_bits_to_llist(int mux_size, + t_sram_orgz_info* cur_sram_orgz_info, + int num_mux_sram_bits, int* mux_sram_bits, + t_spice_model* mux_spice_model); + +void +add_mux_membank_conf_bits_to_llist(int mux_size, + t_sram_orgz_info* cur_sram_orgz_info, + int num_mux_sram_bits, int* mux_sram_bits, + t_spice_model* mux_spice_model); + +void +add_mux_conf_bits_to_llist(int mux_size, + t_sram_orgz_info* cur_sram_orgz_info, + int num_mux_sram_bits, int* mux_sram_bits, + t_spice_model* mux_spice_model); + +void add_sram_membank_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, int mem_index, + int num_bls, int num_wls, + int* bl_conf_bits, int* wl_conf_bits); + +void +add_sram_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, int mem_index, + int num_sram_bits, int* sram_bits); + +void find_bl_wl_ports_spice_model(t_spice_model* cur_spice_model, + int* num_bl_ports, t_spice_model_port*** bl_ports, + int* num_wl_ports, t_spice_model_port*** wl_ports); + +void find_blb_wlb_ports_spice_model(t_spice_model* cur_spice_model, + int* num_blb_ports, t_spice_model_port*** blb_ports, + int* num_wlb_ports, t_spice_model_port*** wlb_ports); + +int* decode_mode_bits(char* mode_bits, int* num_sram_bits); + +/* Useful functions for LUT decoding */ +void stats_lut_spice_mux(t_llist** muxes_head, + t_spice_model* spice_model); + +char* complete_truth_table_line(int lut_size, + char* input_truth_table_line); + +void configure_lut_sram_bits_per_line_rec(int** sram_bits, + int lut_size, + char* truth_table_line, + int start_point); + +int* generate_lut_sram_bits(int truth_table_len, + char** truth_table, + int lut_size, + int default_sram_bit_value); + +char** assign_lut_truth_table(t_logical_block* mapped_logical_block, + int* truth_table_length); + +int get_lut_output_init_val(t_logical_block* lut_logical_block); + +/* Functions to manipulate structs of SRAM orgz */ +t_sram_orgz_info* alloc_one_sram_orgz_info(); + +t_mem_bank_info* alloc_one_mem_bank_info(); + +void free_one_mem_bank_info(t_mem_bank_info* mem_bank_info); + +t_scff_info* alloc_one_scff_info(); + +void free_one_scff_info(t_scff_info* scff_info); + +t_standalone_sram_info* alloc_one_standalone_sram_info(); + +void free_one_standalone_sram_info(t_standalone_sram_info* standalone_sram_info); + +void init_mem_bank_info(t_mem_bank_info* cur_mem_bank_info, + t_spice_model* cur_mem_model); + +void try_update_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info, + int updated_reserved_bl, int updated_reserved_wl); + +void update_mem_bank_info_reserved_blwl(t_mem_bank_info* cur_mem_bank_info, + int updated_reserved_bl, int updated_reserved_wl); + +void get_mem_bank_info_reserved_blwl(t_mem_bank_info* cur_mem_bank_info, + int* num_reserved_bl, int* num_reserved_wl); + +void update_mem_bank_info_num_blwl(t_mem_bank_info* cur_mem_bank_info, + int updated_bl, int updated_wl); + +void get_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info, + int* num_reserved_bl, int* num_reserved_wl); + +void update_mem_bank_info_num_mem_bit(t_mem_bank_info* cur_mem_bank_info, + int num_mem_bit); + +void init_scff_info(t_scff_info* cur_scff_info, + t_spice_model* cur_mem_model); + +void update_scff_info_num_mem_bit(t_scff_info* cur_scff_info, + int num_mem_bit); + +void init_standalone_sram_info(t_standalone_sram_info* cur_standalone_sram_info, + t_spice_model* cur_mem_model); + +void update_standalone_sram_info_num_mem_bit(t_standalone_sram_info* cur_standalone_sram_info, + int num_mem_bit); + +void init_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info, + enum e_sram_orgz cur_sram_orgz_type, + t_spice_model* cur_mem_model, + int grid_nx, int grid_ny); + +void free_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info, + enum e_sram_orgz cur_sram_orgz_type, + int grid_nx, int grid_ny); + +void update_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info, + int updated_reserved_bl, int updated_reserved_wl); + +int get_sram_orgz_info_num_mem_bit(t_sram_orgz_info* cur_sram_orgz_info); + +void get_sram_orgz_info_num_blwl(t_sram_orgz_info* cur_sram_orgz_info, + int* cur_bl, int* cur_wl); + +void update_sram_orgz_info_num_mem_bit(t_sram_orgz_info* cur_sram_orgz_info, + int new_num_mem_bit); + +void update_sram_orgz_info_num_blwl(t_sram_orgz_info* cur_sram_orgz_info, + int new_bl, int new_wl); + +void get_sram_orgz_info_mem_model(t_sram_orgz_info* cur_sram_orgz_info, + t_spice_model** mem_model_ptr); + +void init_reserved_syntax_char(t_reserved_syntax_char* cur_reserved_syntax_char, + char cur_syntax_char, boolean cur_verilog_reserved, boolean cur_spice_reserved); + +void check_mem_model_blwl_inverted(t_spice_model* cur_mem_model, + enum e_spice_model_port_type blwl_port_type, + boolean* blwl_inverted); + +void init_spice_mux_arch(t_spice_model* spice_model, + t_spice_mux_arch* spice_mux_arch, + int mux_size); + +int find_spice_mux_arch_special_basis_size(t_spice_mux_arch spice_mux_arch); + +t_llist* search_mux_linked_list(t_llist* mux_head, + int mux_size, + t_spice_model* spice_model); + +void check_and_add_mux_to_linked_list(t_llist** muxes_head, + int mux_size, + t_spice_model* spice_model); + +void free_muxes_llist(t_llist* muxes_head); + +void stats_spice_muxes_routing_arch(t_llist** muxes_head, + int num_switch, + t_switch_inf* switches, + t_spice* spice, + t_det_routing_arch* routing_arch); + +void stats_mux_spice_model_pb_type_rec(t_llist** muxes_head, + t_pb_type* cur_pb_type); + +void stats_mux_spice_model_pb_node_rec(t_llist** muxes_head, + t_pb_graph_node* cur_pb_node); + +t_llist* stats_spice_muxes(int num_switch, + t_switch_inf* switches, + t_spice* spice, + t_det_routing_arch* routing_arch); + +enum e_interconnect find_pb_graph_pin_in_edges_interc_type(t_pb_graph_pin pb_graph_pin); + +t_spice_model* find_pb_graph_pin_in_edges_interc_spice_model(t_pb_graph_pin pb_graph_pin); + +int find_path_id_between_pb_rr_nodes(t_rr_node* local_rr_graph, + int src_node, + int des_node); + +t_pb* get_child_pb_for_phy_pb_graph_node(t_pb* cur_pb, int ipb, int jpb); + +void config_spice_model_port_inv_spice_model(int num_spice_models, + t_spice_model* spice_model); + +void config_spice_models_sram_port_spice_model(int num_spice_model, + t_spice_model* spice_models, + t_spice_model* default_sram_spice_model); +t_pb* get_lut_child_pb(t_pb* cur_lut_pb, + int mode_index); + +int get_grid_pin_height(int grid_x, int grid_y, int pin_index); + +void determine_sb_port_coordinator(t_sb cur_sb_info, int side, + int* port_x, int* port_y); + +void init_spice_models_tb_cnt(int num_spice_models, + t_spice_model* spice_model); + +void init_spice_models_grid_tb_cnt(int num_spice_models, + t_spice_model* spice_model, + int grid_x, int grid_y); + +void check_spice_models_grid_tb_cnt(int num_spice_models, + t_spice_model* spice_model, + int grid_x, int grid_y, + enum e_spice_model_type spice_model_type_to_check); + +boolean check_negative_variation(float avg_val, + t_spice_mc_variation_params variation_params); diff --git a/vpr7_rram/vpr/SRC/fpga_spice/quicksort.c b/vpr7_rram/vpr/SRC/fpga_spice/quicksort.c new file mode 100644 index 000000000..7949aeb8c --- /dev/null +++ b/vpr7_rram/vpr/SRC/fpga_spice/quicksort.c @@ -0,0 +1,163 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +void my_free(void* ptr); + +/* Subroutines */ +/* Swap two elements of sort_index */ +static +void swap_int(int* int_a, int* int_b) { + int temp = (*int_a); + + (*int_a) = (*int_b); + (*int_b) = temp; + + return; +} + +static +void swap_float(float* int_a, float* int_b) { + float temp = (*int_a); + + (*int_a) = (*int_b); + (*int_b) = temp; + + return; +} + +/* Partition for quicksort + * Given a array(sort_value) , and the index (sort_index) + * Create two arrays, A and B, whose length is start_index and len-start_index, + * Move all the elements that are less than sort_value[start_index] to arrayA [0:start_index] + * Move all the elements that are larger than sort_value[start_index] to arrayB [0:len-start_index] + */ +static +int partition(int len, float* sort_value, int pivot_index) { + int i; + int small_len = 0; + float pivot_val = sort_value[pivot_index]; + + /* Move the pivot to the last position */ + swap_float(&sort_value[pivot_index], &sort_value[len - 1]); + + /* Move all the elements smaller than sort_value[start_index] to the first partition */ + for (i = 0; i < len-1; i++) { + if ((sort_value[i] < pivot_val) + ||(sort_value[i] == pivot_val)) { + swap_float(&sort_value[i], &sort_value[small_len]); + small_len++; + } + } + /* Move the pivot to the critical position */ + swap_float(&sort_value[small_len], &sort_value[len - 1]); + + return small_len; +} + +/* Partition according to the sort_index, + * In this funciton sort_value is not touched. + */ +static +int partition_index(int len, int* sort_index, + float* sort_value, int pivot_index) { + int i; + int small_len = 0; + float pivot_val = sort_value[sort_index[pivot_index]]; + + /* Move the pivot to the last position */ + swap_int(&sort_index[pivot_index], &sort_index[len - 1]); + + /* Move all the elements smaller than sort_value[start_index] to the first partition */ + for (i = 0; i < len-1; i++) { + if ((sort_value[sort_index[i]] < pivot_val) + ||(sort_value[sort_index[i]] == pivot_val)) { + swap_int(&sort_index[i], &sort_index[small_len]); + small_len++; + } + } + /* Move the pivot to the critical position */ + swap_int(&sort_index[small_len], &sort_index[len - 1]); + + return small_len; +} + +/* Top functions for quicksort */ +/* Sort float numbers by index, sort_value is not changed. + */ +void quicksort_float(int len, + float* sort_value) { + int small_len = 0; + //int pivot_val = 0; + //int pivot_index = 0; + + if ((0 == len)||(1 == len)) { + return; + } + + /* get partition */ + small_len = partition(len, sort_value, 0); + /* Check */ + //assert(pivot_val == sort_value[small_len]); + //assert(pivot_index == sort_index[small_len]); + /* Recursive */ + quicksort_float(small_len, sort_value); + quicksort_float(len - small_len - 1, sort_value+small_len + 1); + + return; +} + +/* Sort float numbers by index, sort_value is not changed. + */ +void do_quicksort_float_index(int len, + int* sort_index, + float* sort_value) { + int small_len = 0; + //int pivot_val = 0; + //int pivot_index = 0; + + if ((0 == len)||(1 == len)) { + return; + } + + /* get partition */ + small_len = partition_index(len, sort_index, sort_value, 0); + /* Check */ + //assert(pivot_val == sort_value[small_len]); + //assert(pivot_index == sort_index[small_len]); + /* Recursive */ + do_quicksort_float_index(small_len, sort_index, sort_value); + do_quicksort_float_index(len - small_len - 1, sort_index + small_len + 1, sort_value); + + return; +} + +/* One of the top functions: sort_index should be meet the specfication */ +void quicksort_float_index(int len, + int* sort_index, + float* sort_value) { + int i; + + /* Check the sort index */ + for (i = 0; i < len; i++) { + assert(i == sort_index[i]); + } + + do_quicksort_float_index(len, sort_index, sort_value); + + return; +} + + + diff --git a/vpr7_rram/vpr/SRC/fpga_spice/quicksort.h b/vpr7_rram/vpr/SRC/fpga_spice/quicksort.h new file mode 100644 index 000000000..df600eb19 --- /dev/null +++ b/vpr7_rram/vpr/SRC/fpga_spice/quicksort.h @@ -0,0 +1,4 @@ + +/* QuickSort functions */ +void quicksort_float_index(int len, int* sort_index, + float* sort_value); diff --git a/vpr7_rram/vpr/SRC/main.c b/vpr7_rram/vpr/SRC/main.c new file mode 100644 index 000000000..637f30ade --- /dev/null +++ b/vpr7_rram/vpr/SRC/main.c @@ -0,0 +1,86 @@ +/** + VPR is a CAD tool used to conduct FPGA architecture exploration. It takes, as input, a technology-mapped netlist and a description of the FPGA architecture being investigated. + VPR then generates a packed, placed, and routed FPGA (in .net, .place, and .route files respectively) that implements the input netlist. + + This file is where VPR starts execution. + + Key files in VPR: + 1. libarchfpga/physical_types.h - Data structures that define the properties of the FPGA architecture + 2. vpr_types.h - Very major file that defines the core data structures used in VPR. This includes detailed architecture information, user netlist data structures, and data structures that describe the mapping between those two. + 3. globals.h - Defines the global variables used by VPR. + */ + + +#include +#include +#include +#include + +#include "vpr_api.h" +/* mrFPGA : Xifan TANG */ +#include "mrfpga_api.h" +/* END */ + +/** + * VPR program + * Generate FPGA architecture given architecture description + * Pack, place, and route circuit into FPGA architecture + * Electrical timing analysis on results + * + * Overall steps + * 1. Initialization + * 2. Pack + * 3. Place-and-route and timing analysis + * 4. Clean up + */ +int main(int argc, char **argv) { + t_options Options; + t_arch Arch; + t_vpr_setup vpr_setup; + clock_t entire_flow_begin,entire_flow_end; + + entire_flow_begin = clock(); + + /* Read options, architecture, and circuit netlist */ + vpr_init(argc, argv, &Options, &vpr_setup, &Arch); + + /* If the user requests packing, do packing */ + if (vpr_setup.PackerOpts.doPacking) { + vpr_pack(vpr_setup, Arch); + } + + if (vpr_setup.PlacerOpts.doPlacement || vpr_setup.RouterOpts.doRouting) { + vpr_init_pre_place_and_route(vpr_setup, Arch); + vpr_place_and_route(vpr_setup, Arch); +#if 0 + if(vpr_setup.RouterOpts.doRouting) { + vpr_resync_post_route_netlist_to_TI_CLAY_v1_architecture(&Arch); + } +#endif + } + + if (vpr_setup.PowerOpts.do_power) { + vpr_power_estimation(vpr_setup, Arch); + } + + /* Run FPGA-SPICE tool suites*/ + vpr_fpga_spice_tool_suites(vpr_setup, Arch); + + entire_flow_end = clock(); + + #ifdef CLOCKS_PER_SEC + vpr_printf(TIO_MESSAGE_INFO, "The entire flow of VPR took %g seconds.\n", (float)(entire_flow_end - entire_flow_begin) / CLOCKS_PER_SEC); + #else + vpr_printf(TIO_MESSAGE_INFO, "The entire flow of VPR took %g seconds.\n", (float)(entire_flow_end - entire_flow_begin) / CLK_PER_SEC); + #endif + + /* free data structures */ + vpr_free_all(Arch, Options, vpr_setup); + + /* Return 0 to single success to scripts */ + return 0; +} + + + + diff --git a/vpr7_rram/vpr/SRC/mrfpga/buffer_insertion.c b/vpr7_rram/vpr/SRC/mrfpga/buffer_insertion.c new file mode 100644 index 000000000..f0b74dc5f --- /dev/null +++ b/vpr7_rram/vpr/SRC/mrfpga/buffer_insertion.c @@ -0,0 +1,593 @@ +#include +#include "util.h" +/* Xifan TANG */ +#include "physical_types.h" +/* END */ +#include "vpr_types.h" +#include "globals.h" +#include "buffer_insertion.h" +/* Xifan TANG */ +#include "mrfpga_util.h" +#include "mrfpga_globals.h" +#include "net_delay_types.h" +#include "net_delay_local_void.h" +/* END */ + +/* memristor */ +typedef struct s_buffer_plan {t_linked_int* inode_head; t_linked_int* sink_head; float* sink_delay; float C_downstream; float Tdel;} t_buffer_plan; +typedef struct s_buffer_plan_node { t_buffer_plan value; struct s_buffer_plan_node* next;} t_buffer_plan_node; +typedef struct s_buffer_plan_list { t_buffer_plan_node* front; } t_buffer_plan_list; + +/* memristor */ +static t_buffer_plan_list get_empty_buffer_plan_list( ); +static t_buffer_plan_list join_left_plan_list_into_whole( t_buffer_plan_list left, t_buffer_plan_list* whole, int num_whole, t_buffer_plan_list current, int num_pins ); +static void free_buffer_list( t_buffer_plan_list list ); +static t_buffer_plan_list insert_buffer( t_buffer_plan_list list, int inode, float C, float R, float Tdel, int num_pins ); +static t_buffer_plan insert_wire_to_buffer_plan( t_buffer_plan plan, float C, float R); +static void insert_wire_to_buffer_list( t_buffer_plan_list list, float C,float R); +static void insert_switch_to_buffer_list( t_buffer_plan_list list, struct s_switch_inf switch_inf_local); +static t_buffer_plan insert_switch_to_buffer_plan( t_buffer_plan plan, struct s_switch_inf switch_inf_local); +static t_buffer_plan_list insert_buffer_plan_to_list( t_buffer_plan plan, t_buffer_plan_list list ); +static void save_best_buffer_list( t_linked_int* best_list ); +static void free_best_buffer_list( ); +static int get_int_list_length( t_linked_int* list ); +static void save_best_timing( float* sink_delay, t_linked_int* index, float* net_delay ); +static int alloc_isink_to_inode( int inet, int** isink_to_inode_ptr ); +static t_buffer_plan_list try_buffer_rc_tree (t_rc_node* rc_node, int num_pins, int* isink_to_inode); +static t_buffer_plan get_init_buffer_plan( int inode, int num_pins, int* isink_to_inode ); +static t_buffer_plan_list get_init_buffer_plan_list( int inode, int num_pins, int* isink_to_inode ); +static t_buffer_plan combine_buffer_plan( t_buffer_plan slow_branch, t_buffer_plan* plan_whole, int num_whole, int num_pins ); +static void copy_delay( float* base, float* source, t_linked_int* index ); +static void add_delay_to_array( float* sink_delay, t_linked_int* index, float delay_addition ); +static float* copy_from_float_array( float* source, int num ); +static t_buffer_plan add_delay_to_buffer_plan( t_buffer_plan plan, float Tdel ); + + +void try_buffer_for_net( int inet, t_rc_node** rc_node_free_list, t_linked_rc_edge** rc_edge_free_list, t_linked_rc_ptr* rr_node_to_rc_node, float* net_delay ); +/* memristor */ + +void try_buffer_for_routing ( float** net_delay ) { + + t_rc_node *rc_node_free_list; + t_linked_rc_edge *rc_edge_free_list; + int inet; + t_linked_rc_ptr *rr_node_to_rc_node; /* [0..num_rr_nodes-1] */ + + rr_node_to_rc_node = (t_linked_rc_ptr *) my_calloc (num_rr_nodes, + sizeof (t_linked_rc_ptr)); + + rc_node_free_list = NULL; + rc_edge_free_list = NULL; + + free_best_buffer_list( ); + for (inet=0;inetvalue.Tdel < best.Tdel || ( traverse->value.Tdel == best.Tdel && get_int_list_length( traverse->value.inode_head ) < get_int_list_length( best.inode_head ) ) ) + { + best = traverse->value;; + } + traverse = traverse->next; + } + crit_delay = max( crit_delay, best.Tdel ); + save_best_buffer_list( best.inode_head ); + save_best_timing( best.sink_delay, best.sink_head, net_delay ); + free_buffer_list( plan_list ); + free_rc_tree (rc_root, rc_node_free_list, rc_edge_free_list); + reset_rr_node_to_rc_node (rr_node_to_rc_node, inet ); + free( isink_to_inode ); + } +} + +static void save_best_timing( float* sink_delay, t_linked_int* index, float* net_delay ) +{ + t_linked_int* traverse; + traverse = index; + while( traverse != NULL ) + { + net_delay[traverse->data] = sink_delay[traverse->data]; + traverse = traverse->next; + } +} + +static int alloc_isink_to_inode( int inet, int** isink_to_inode_ptr ) +{ + int i; + int num_pins = clb_net[inet].num_sinks + 1; + *isink_to_inode_ptr = (int*)my_malloc( sizeof(int) * num_pins ); + for( i = 1; i < num_pins; i++ ) + { + (*isink_to_inode_ptr)[i] = net_rr_terminals[inet][i]; + } + return num_pins; +} + +static int get_int_list_length( t_linked_int* list ) +{ + t_linked_int* traverse = list; + int counter = 0; + while ( traverse != NULL ) + { + counter++; + traverse = traverse->next; + } + return counter; +} + +static void free_best_buffer_list( ) +{ + t_linked_int* traverse = main_best_buffer_list; + t_linked_int* current; + while ( traverse != NULL ) + { + current = traverse; + traverse = current->next; + free( current ); + } + main_best_buffer_list = NULL; +} + +static void save_best_buffer_list( t_linked_int* best_list ) +{ + t_linked_int* current; + t_linked_int* traverse = best_list; + while ( traverse != NULL ) + { + current = ( t_linked_int* ) my_malloc( sizeof( t_linked_int ) ); + current->data = traverse->data; + current->next = main_best_buffer_list; + main_best_buffer_list = current; + traverse = traverse->next; + } +} + +void load_best_buffer_list( ) +{ + t_linked_int* traverse = main_best_buffer_list; + clear_buffer( ); + while ( traverse != NULL ) + { + rr_node[ traverse->data ].buffered = 1; + traverse = traverse->next; + } +} + +int print_stat_memristor_buffer( char* fname, float buffer_size ) +{ + char fnamex[100]; + char fnamey[100]; + FILE* fpx; + FILE* fpy; + int** freqx; + int** freqy; + int counter; + int i, j; + t_linked_int* traverse; + int max_number; + sprintf( fnamex, "x_%s", fname ); + sprintf( fnamey, "y_%s", fname ); + fpx = my_fopen( fnamex, "w" ,0); + fpy = my_fopen( fnamey, "w" ,0); + freqx = (int**) alloc_matrix( 1, nx, 0, ny, sizeof(int) ); + freqy = (int**) alloc_matrix( 0, nx, 1, ny, sizeof(int) ); + counter = 0; + for( i = 1; i <= nx; i++ ) + { + for( j = 0; j <= ny; j++ ) + { + freqx[i][j]=0; + } + } + for( i = 0; i <= nx; i++ ) + { + for( j = 1; j <= ny; j++ ) + { + freqy[i][j]=0; + } + } + traverse = main_best_buffer_list; + while ( traverse != NULL ) + { + counter++; + if ( rr_node[traverse->data].type == CHANX ) + { + freqx[rr_node[traverse->data].xlow][( rr_node[traverse->data].ylow + rr_node[traverse->data].yhigh ) / 2]++; + } + else if ( rr_node[traverse->data].type == CHANY ) + { + freqy[(rr_node[traverse->data].xlow+rr_node[traverse->data].xhigh)/2][rr_node[traverse->data].ylow]++; + } + traverse = traverse->next; + } + max_number = 0; + for( i = 1; i <= nx; i++ ) + { + for( j = 0; j <= ny; j++ ) + { + max_number = max( max_number, freqx[i][j] ); + fprintf( fpx, "%d ", freqx[i][j] ); + } + fprintf( fpx, "\n" ); + } + for( i = 0; i <= nx; i++ ) + { + for( j = 1; j <= ny; j++ ) + { + max_number = max( max_number, freqy[i][j] ); + fprintf( fpy, "%d ", freqy[i][j] ); + } + fprintf( fpy, "\n" ); + } + free_matrix( freqx, 1, nx, 0, sizeof(int) ); + free_matrix( freqy, 0, nx, 1, sizeof(int) ); + fclose( fpx ); + fclose( fpy ); + printf( "%d buffers ( size: %g ) inserted, total active trans: %g\n", counter, buffer_size, counter*buffer_size ); + printf( "maximum # of buffers in one channel: %d\n", max_number ); + return max_number; +} + +void clear_buffer( ) +{ + int i; + for( i = 0; i < num_rr_nodes; i++ ) + { + rr_node[ i ].buffered = 0; + } +} + +static t_buffer_plan_list try_buffer_rc_tree (t_rc_node *rc_node, int num_pins, int* isink_to_inode) { + t_linked_rc_edge *linked_rc_edge; + t_rc_node *child_node; + short iswitch; + int inode; + int num_whole; + int i; + t_rr_node rrnode; + t_buffer_plan_list result; + t_buffer_plan_list* plan_list_from_branch; + + inode = rc_node->inode; + rrnode = rr_node[ inode ]; + + if ( rrnode.type == SINK ) + { + result = get_init_buffer_plan_list( inode, num_pins, isink_to_inode ); + } + else + { + result = get_empty_buffer_plan_list( ); + num_whole = 0; + linked_rc_edge = rc_node->u.child_list; + while (linked_rc_edge != NULL) { /* For all children */ + num_whole++; + linked_rc_edge = linked_rc_edge->next; + } + plan_list_from_branch = ( t_buffer_plan_list* )my_malloc( num_whole*sizeof(t_buffer_plan_list) ); + + i = 0; + linked_rc_edge = rc_node->u.child_list; + while (linked_rc_edge != NULL) { /* For all children */ + iswitch = linked_rc_edge->iswitch; + child_node = linked_rc_edge->child; + plan_list_from_branch[i] = try_buffer_rc_tree( child_node, num_pins, isink_to_inode ); + insert_switch_to_buffer_list( plan_list_from_branch[i], switch_inf[ iswitch ] ); + linked_rc_edge = linked_rc_edge->next; + i++; + } + if ( num_whole > 1 ) + { + for( i = 0; i < num_whole; i++ ) + { + result = join_left_plan_list_into_whole( plan_list_from_branch[ i ], plan_list_from_branch, num_whole, result, num_pins ); + } + for( i = 0; i < num_whole; i++ ) + { + free_buffer_list( plan_list_from_branch[ i ] ); + } + } + else + { + result = plan_list_from_branch[ 0 ]; + } + free( plan_list_from_branch ); + insert_wire_to_buffer_list( result, rrnode.C, 0.5 * rrnode.R ); + if (rr_node[ inode ].type == CHANX || rr_node[ inode ].type == CHANY) + { + result = insert_buffer( result, inode, wire_buffer_inf.C, wire_buffer_inf.R, wire_buffer_inf.Tdel, num_pins ); + } + } + return result; +} + +static void add_delay_to_buffer_list( t_buffer_plan_list list, float Tdel , boolean skip_first ) +{ + t_buffer_plan_node* traverse = list.front; + if ( skip_first && traverse != NULL ) + { + traverse = traverse->next; + } + while ( traverse != NULL ) + { + traverse->value = add_delay_to_buffer_plan( traverse->value, Tdel ); + traverse = traverse->next; + } +} + +static t_buffer_plan add_delay_to_buffer_plan( t_buffer_plan plan, float Tdel ) +{ + add_delay_to_array( plan.sink_delay, plan.sink_head, Tdel ); + plan.Tdel += Tdel; + return plan; +} + +static t_buffer_plan_list get_empty_buffer_plan_list( ) +{ + t_buffer_plan_list list; + list.front = NULL; + return list; +} + +static t_buffer_plan get_init_buffer_plan( int inode, int num_pins, int* isink_to_inode ) +{ + t_buffer_plan plan; + int i; + plan.inode_head = NULL; + plan.sink_head = (t_linked_int*) my_malloc( sizeof( t_linked_int ) ); + plan.sink_head->next = 0; + plan.sink_delay = (float*) my_malloc( sizeof(float) * num_pins ); + for( i = 1; i < num_pins; i++ ) + { + if( isink_to_inode[ i ] == inode ) + { + plan.sink_head->data = i; + } + plan.sink_delay[i] = 0; + } + plan.C_downstream = 0.; + plan.Tdel = 0.; + return plan; +} + +static t_buffer_plan_list get_init_buffer_plan_list( int inode, int num_pins, int* isink_to_inode ) +{ + t_buffer_plan_list list; + list.front = ( t_buffer_plan_node* ) my_malloc( sizeof( t_buffer_plan_node ) ); + list.front->value = get_init_buffer_plan( inode, num_pins, isink_to_inode ); + list.front->next = NULL; + return list; +} + +static t_buffer_plan_list join_left_plan_list_into_whole( t_buffer_plan_list left, t_buffer_plan_list* whole, int num_whole, t_buffer_plan_list current, int num_pins ) +{ + int i; + t_buffer_plan_node* left_traverse; + t_buffer_plan_node* whole_traverse; + t_buffer_plan* best_plans = (t_buffer_plan*) my_malloc(num_whole*sizeof(t_buffer_plan)); + left_traverse = left.front; + while( left_traverse != NULL ) + { + for( i=0; i< num_whole; i++ ) + { + best_plans[i].C_downstream = HUGE_VAL; + if ( left.front == whole[ i ].front ) + { + continue; + } + whole_traverse = whole[i].front; + while ( whole_traverse != NULL ) + { + if ( whole_traverse->value.Tdel <= left_traverse->value.Tdel + && whole_traverse->value.C_downstream < best_plans[i].C_downstream ) + { + best_plans[i] = whole_traverse->value; + } + whole_traverse = whole_traverse->next; + } + if ( best_plans[i].C_downstream == HUGE_VAL ) + { + break; + } + } + if ( i == num_whole ) + { + current = insert_buffer_plan_to_list( combine_buffer_plan( left_traverse->value, best_plans, num_whole, num_pins ), current ); + } + left_traverse = left_traverse->next; + } + free( best_plans ); + return current; +} + +static t_buffer_plan combine_buffer_plan( t_buffer_plan slow_branch, t_buffer_plan* plan_whole, int num_whole, int num_pins ) +{ + int i; + t_buffer_plan new_plan = slow_branch; + new_plan.inode_head = NULL; + new_plan.sink_head = NULL; + new_plan.sink_delay = (float*) my_malloc( sizeof(float) * num_pins ); + new_plan.inode_head = copy_from_list( new_plan.inode_head, slow_branch.inode_head ); + new_plan.sink_head = copy_from_list( new_plan.sink_head, slow_branch.sink_head ); + copy_delay( new_plan.sink_delay, slow_branch.sink_delay, slow_branch.sink_head ); + for( i = 0; i < num_whole; i++ ) + { + if ( plan_whole[ i ].C_downstream == HUGE_VAL ) + { + continue; + } + new_plan.C_downstream += plan_whole[i].C_downstream; + new_plan.inode_head = copy_from_list( new_plan.inode_head, plan_whole[i].inode_head ); + new_plan.sink_head = copy_from_list( new_plan.sink_head, plan_whole[i].sink_head ); + copy_delay( new_plan.sink_delay, plan_whole[i].sink_delay, plan_whole[i].sink_head ); + } + return new_plan; +} + +static void copy_delay( float* base, float* source, t_linked_int* index ) +{ + t_linked_int* traverse = index; + while( traverse != NULL ) + { + base[traverse->data] = source[traverse->data]; + traverse = traverse->next; + } +} + +static void free_buffer_list( t_buffer_plan_list list ) +{ + t_buffer_plan_node* traverse = list.front; + t_buffer_plan_node* temp; + while( traverse != NULL ) + { + free_int_list( &( traverse->value.inode_head ) ); + free_int_list( &( traverse->value.sink_head ) ); + free( traverse->value.sink_delay ); + temp = traverse->next; + free( traverse ); + traverse = temp; + } +} + +static t_buffer_plan_list insert_buffer( t_buffer_plan_list list, int inode, float C, float R, float Tdel, int num_pins ) +{ + t_buffer_plan best; + //int i; + float Tdel_temp; + float delay_addition; + float Tdel_best = HUGE_VAL; + t_buffer_plan_node* traverse = list.front; + while ( traverse != NULL ) + { + Tdel_temp = traverse->value.Tdel + traverse->value.C_downstream * R; + if ( Tdel_temp < Tdel_best ) + { + Tdel_best = Tdel_temp; + best = traverse->value; + } + traverse = traverse->next; + } + best.inode_head = copy_from_list( NULL, best.inode_head ); + best.inode_head = insert_in_int_list2( best.inode_head, inode ); + best.sink_head = copy_from_list( NULL, best.sink_head ); + best.sink_delay = copy_from_float_array( best.sink_delay, num_pins ); + best.C_downstream = C; + delay_addition = Tdel_best + Tdel - best.Tdel; + add_delay_to_array( best.sink_delay, best.sink_head, delay_addition ); + best.Tdel += delay_addition; + return insert_buffer_plan_to_list( best, list ); +} + +static float* copy_from_float_array( float* source, int num ) +{ + int i; + float* result = (float*)my_malloc( sizeof(float) * num ); + for( i = 0; i < num; i++ ) + { + result[i] = source[i]; + } + return result; +} + +static t_buffer_plan insert_wire_to_buffer_plan( t_buffer_plan plan, float C, float R ) +{ + float delay_addition; + plan.C_downstream += C; + delay_addition = R * plan.C_downstream; + add_delay_to_array( plan.sink_delay, plan.sink_head, delay_addition ); + plan.Tdel += delay_addition; + return plan; +} + +static void add_delay_to_array( float* sink_delay, t_linked_int* index, float delay_addition ) +{ + t_linked_int* traverse = index; + while( traverse != NULL ) + { + sink_delay[traverse->data] += delay_addition; + traverse = traverse->next; + } +} + +static t_buffer_plan insert_switch_to_buffer_plan( t_buffer_plan plan, struct s_switch_inf switch_inf_local) +{ + float delay_addition; + delay_addition = switch_inf_local.R * plan.C_downstream + switch_inf_local.Tdel; + add_delay_to_array( plan.sink_delay, plan.sink_head, delay_addition ); + plan.Tdel += delay_addition; + if ( switch_inf_local.buffered ) + { + plan.C_downstream = switch_inf_local.Cin; + } + else + { + plan.C_downstream += switch_inf_local.Cout + switch_inf_local.Cin; + } + return plan; +} + +static void insert_switch_to_buffer_list( t_buffer_plan_list list, struct s_switch_inf switch_inf_local) +{ + t_buffer_plan_node* traverse = list.front; + while ( traverse != NULL ) + { + traverse->value = insert_switch_to_buffer_plan( traverse->value, switch_inf_local); + traverse = traverse->next; + } +} + +static void insert_wire_to_buffer_list( t_buffer_plan_list list, float C,float R ) +{ + t_buffer_plan_node* traverse = list.front; + while ( traverse != NULL ) + { + traverse->value = insert_wire_to_buffer_plan( traverse->value, C, R ); + traverse = traverse->next; + } +} + +static t_buffer_plan_list insert_buffer_plan_to_list( t_buffer_plan plan, t_buffer_plan_list list ) { + /* original name : new is a resevered word in C++!!! */ + t_buffer_plan_node* new_buffer_plan_node = ( t_buffer_plan_node* )my_malloc( sizeof( t_buffer_plan_node ) ); + new_buffer_plan_node->value = plan; + new_buffer_plan_node->next = list.front; + list.front = new_buffer_plan_node; + return list; +} + +void count_routing_memristor_buffer( int num_per_channel, float buffer_size ) +{ + float total_area = num_per_channel*((1+nx)*ny+(1+ny)*nx)*buffer_size; + printf("\nRouting area due to inserted buffers: Total: %g Per clb: %g\n", total_area, total_area / nx / ny ); + printf("tile area: %#g\n", total_area / nx / ny + grid_logic_tile_area ); +} + +/* memristor end */ + diff --git a/vpr7_rram/vpr/SRC/mrfpga/buffer_insertion.h b/vpr7_rram/vpr/SRC/mrfpga/buffer_insertion.h new file mode 100644 index 000000000..887cabc96 --- /dev/null +++ b/vpr7_rram/vpr/SRC/mrfpga/buffer_insertion.h @@ -0,0 +1,10 @@ +#ifndef BUFFER_INSERTION_H +#define BUFFER_INSERTION_H + +void try_buffer_for_routing ( float** net_delay ); +void load_best_buffer_list( ); +int print_stat_memristor_buffer( char* fname, float buffer_size ); +void clear_buffer( ); +void count_routing_memristor_buffer( int num_per_channel, float buffer_size ); + +#endif diff --git a/vpr7_rram/vpr/SRC/mrfpga/cal_capacitance.c b/vpr7_rram/vpr/SRC/mrfpga/cal_capacitance.c new file mode 100644 index 000000000..1842383e2 --- /dev/null +++ b/vpr7_rram/vpr/SRC/mrfpga/cal_capacitance.c @@ -0,0 +1,83 @@ +#include +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "cal_capacitance.h" +/* Xifan TANG */ +#include "mrfpga_globals.h" +#include "net_delay_types.h" +#include "net_delay_local_void.h" +/* end */ + +static float load_rc_tree_Ctotal (t_rc_node *rc_node); + +void cal_capacitance_from_routing ( ) { + + t_rc_node *rc_node_free_list, *rc_root; + t_linked_rc_edge *rc_edge_free_list; + int inet; + t_linked_rc_ptr *rr_node_to_rc_node; /* [0..num_rr_nodes-1] */ + + float total_capacitance = 0; + + rc_node_free_list = NULL; + rc_edge_free_list = NULL; + + rr_node_to_rc_node = (t_linked_rc_ptr *) my_calloc (num_rr_nodes, + sizeof (t_linked_rc_ptr)); + + for (inet=0;inetu.child_list; + inode = rc_node->inode; + C = rr_node[inode].C; + + if( rr_node[inode].buffered ) + { + C += wire_buffer_inf.C * 3.0; + } + + while (linked_rc_edge != NULL) { /* For all children */ + iswitch = linked_rc_edge->iswitch; + child_node = linked_rc_edge->child; + C += load_rc_tree_Ctotal (child_node); + + if ( is_mrFPGA ) + { + C += switch_inf[iswitch].Cin; + C += switch_inf[iswitch].Cout; + } + else if ( switch_inf[iswitch].buffered ) + { + C += switch_inf[iswitch].Cin * 2.0; + C += switch_inf[iswitch].Cout * 2.0; + } + linked_rc_edge = linked_rc_edge->next; + } + return (C); +} + diff --git a/vpr7_rram/vpr/SRC/mrfpga/cal_capacitance.h b/vpr7_rram/vpr/SRC/mrfpga/cal_capacitance.h new file mode 100644 index 000000000..d79864a38 --- /dev/null +++ b/vpr7_rram/vpr/SRC/mrfpga/cal_capacitance.h @@ -0,0 +1,6 @@ +#ifndef CAL_CAPACITANCE_H +#define CAL_CAPACITANCE_H + +void cal_capacitance_from_routing ( ); + +#endif diff --git a/vpr7_rram/vpr/SRC/mrfpga/mrfpga_api.c b/vpr7_rram/vpr/SRC/mrfpga/mrfpga_api.c new file mode 100644 index 000000000..9d46026fb --- /dev/null +++ b/vpr7_rram/vpr/SRC/mrfpga/mrfpga_api.c @@ -0,0 +1,142 @@ +#include +#include +#include +#include + +/* libarchfpga data structures*/ +#include "util.h" +#include "physical_types.h" +/* END */ + +/* VPR data structures*/ +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph.h" +#include "vpr_utils.h" +/* END */ + +/* mrFPGA: Xifan TANG*/ +#include "mrfpga_globals.h" +#include "mrfpga_util.h" +#include "buffer_insertion.h" +#include "cal_capacitance.h" +#include "mrfpga_api.h" + +/***** Subroutines *****/ +/* Copy the contents in arch_mrfpga to globals*/ +void sync_arch_mrfpga_globals(t_arch_mrfpga arch_mrfpga) { + /* Booleans */ + is_isolation = arch_mrfpga.is_isolation; + is_stack = arch_mrfpga.is_stack; + is_junction = arch_mrfpga.is_junction; + is_wire_buffer = arch_mrfpga.is_wire_buffer; + is_mrFPGA = arch_mrfpga.is_mrFPGA; + + /* Copy some struct*/ + wire_buffer_inf = arch_mrfpga.wire_buffer_inf; + memristor_inf = arch_mrfpga.memristor_inf; + max_pins_per_side = arch_mrfpga.max_pins_per_side; + main_best_buffer_list = arch_mrfpga.main_best_buffer_list; + num_normal_switch = arch_mrfpga.num_normal_switch; + start_seg_switch = arch_mrfpga.start_seg_switch; + + /* SRAM and Pass Transistor Usage*/ + is_show_sram = arch_mrfpga.is_show_sram; + is_show_pass_trans = arch_mrfpga.is_show_pass_trans; + Rseg_global = arch_mrfpga.Rseg_global; + Cseg_global = arch_mrfpga.Cseg_global; + + return; +} + +/* Get the switch type for mrFPGA: Xifan TANG + * This function is called rr_graph2.c but I move it here + * so that it is easy to see mrFPGA modifications + */ +void get_mrfpga_switch_type(boolean is_from_sbox, + boolean is_to_sbox, + short from_node_switch, + short to_node_switch, + short switch_types[2]) { + /* This routine looks at whether the from_node and to_node want a switch, * + * and what type of switch is used to connect *to* each type of node * + * (from_node_switch and to_node_switch). It decides what type of switch, * + * if any, should be used to go from from_node to to_node. If no switch * + * should be inserted (i.e. no connection), it returns OPEN. Its returned * + * values are in the switch_types array. It needs to return an array * + * because one topology (a buffer in the forward direction and a pass * + * transistor in the backward direction) results in *two* switches. */ + + /* modified by bjxiao to make the pass transistors accepted */ + /* the original version has bugs */ + /* this version is copied from VPR4.3 */ + switch_types[0] = OPEN; /* No switch */ + switch_types[1] = OPEN; + + if (!is_from_sbox && !is_to_sbox) { /* No connection wanted in either dir */ + switch_types[0] = OPEN; + } + + else if (is_from_sbox && !is_to_sbox) { /* Only forward connection wanted */ + switch_types[0] = to_node_switch; /* Type of switch to go *to* to_node */ + } + + else if (!is_from_sbox && is_to_sbox) { + + /* Only backward connection desired. We're deciding whether or not to put * + * in the forward connection. Put it in if the backward connection uses * + * a bidirectional (pass transistor) switch. Remember that the backward * + * connection uses a from_node_switch type of switch. */ + + if ( switch_inf[from_node_switch].buffered == FALSE) { + switch_types[0] = from_node_switch; + } + } else { + /* Both a forward and a backward connection desired. If the switch types * + * desired for the two connection are different, we have to reconcile them. */ + + if (from_node_switch == to_node_switch) { + switch_types[0] = to_node_switch; + } else { /* Different switch types. Reconcile. */ + if (switch_inf[to_node_switch].buffered) { + switch_types[0] = to_node_switch; + if ( switch_inf[from_node_switch].buffered == FALSE) { + /* Buffer in forward direction, pass transistor in backward. Put * + * in *two* edges. */ + switch_types[1] = from_node_switch; + } + } else { /* Forward connection is a pass transistor. */ + if (switch_inf[from_node_switch].buffered) { + switch_types[0] = to_node_switch; + } else { + + /* Both forward and backward connections use pass transistors. * + * use whichever one is larger, since you'll only physically * + * build one switch. */ + + if (switch_inf[to_node_switch].R < + switch_inf[from_node_switch].R) { + switch_types[0] = to_node_switch; + } else if (switch_inf[from_node_switch].R < + switch_inf[to_node_switch].R) { + switch_types[0] = from_node_switch; + } else { + + /* Two pass transistors have the same R, but are have different * + * switch indices. Use the one with lower index (arbitrarily), * + * to ensure both switches are of the same type (since you can * + * only physically build one). I'm being pretty dogmatic here. */ + + if (to_node_switch < from_node_switch) { + switch_types[0] = to_node_switch; + } else { + switch_types[0] = from_node_switch; + } + } + } + } + } /* End switch types are different */ + } /* End both forward and backward connection desired. */ + /* end */ +} + diff --git a/vpr7_rram/vpr/SRC/mrfpga/mrfpga_api.h b/vpr7_rram/vpr/SRC/mrfpga/mrfpga_api.h new file mode 100644 index 000000000..0cf0139f8 --- /dev/null +++ b/vpr7_rram/vpr/SRC/mrfpga/mrfpga_api.h @@ -0,0 +1,8 @@ + +void sync_arch_mrfpga_globals(t_arch_mrfpga arch_mrfpga); + +void get_mrfpga_switch_type(boolean is_from_sbox, + boolean is_to_sbox, + short from_node_switch, + short to_node_switch, + short switch_types[2]); diff --git a/vpr7_rram/vpr/SRC/mrfpga/mrfpga_globals.c b/vpr7_rram/vpr/SRC/mrfpga/mrfpga_globals.c new file mode 100644 index 000000000..be0a87b03 --- /dev/null +++ b/vpr7_rram/vpr/SRC/mrfpga/mrfpga_globals.c @@ -0,0 +1,27 @@ +#include +#include +#include +#include "util.h" +#include "vpr_types.h" +#include "globals.h" + +/* mrFPGA specfications */ +boolean is_isolation = FALSE; +boolean is_stack = FALSE; +boolean is_junction = FALSE; +boolean is_wire_buffer = FALSE; +boolean is_mrFPGA = FALSE; +t_buffer_inf wire_buffer_inf; +t_memristor_inf memristor_inf; +int max_pins_per_side; +t_linked_int* main_best_buffer_list; +short num_normal_switch; +short start_seg_switch; +/* end */ + +/* bjxiao: show sram and pass transistor usage */ +boolean is_show_sram = FALSE, is_show_pass_trans = FALSE; +float Rseg_global, Cseg_global; +float rram_pass_tran_value = 0; +/* end */ + diff --git a/vpr7_rram/vpr/SRC/mrfpga/mrfpga_globals.h b/vpr7_rram/vpr/SRC/mrfpga/mrfpga_globals.h new file mode 100644 index 000000000..df217944d --- /dev/null +++ b/vpr7_rram/vpr/SRC/mrfpga/mrfpga_globals.h @@ -0,0 +1,26 @@ +#ifndef MRFPGA_H +#define MRFPGA_H + +/* mrFPGA specfications */ +extern boolean is_isolation; +extern boolean is_stack; +extern boolean is_junction; +extern boolean is_wire_buffer; +extern boolean is_mrFPGA; +//extern boolean is_accurate; /* Xifan TANG: Abolish */ +extern t_buffer_inf wire_buffer_inf; +extern t_memristor_inf memristor_inf; +extern int max_pins_per_side; +extern t_linked_int* main_best_buffer_list; +extern short num_normal_switch; +extern short start_seg_switch; +/* end */ + +/* bjxiao: show sram and pass transistor usage */ +extern boolean is_show_sram, is_show_pass_trans; +//extern enum e_tech_comp tech_comp; /* Xifan TANG : abolish */ +extern float Rseg_global, Cseg_global; +extern float rram_pass_tran_value; +/* end */ + +#endif diff --git a/vpr7_rram/vpr/SRC/mrfpga/mrfpga_util.c b/vpr7_rram/vpr/SRC/mrfpga/mrfpga_util.c new file mode 100644 index 000000000..470a46d5f --- /dev/null +++ b/vpr7_rram/vpr/SRC/mrfpga/mrfpga_util.c @@ -0,0 +1,28 @@ +#include +#include +#include "util.h" +#include "vpr_types.h" +#include "mrfpga_util.h" + +/* mrFPGA */ +t_linked_int* insert_in_int_list2 (t_linked_int *head, int data ) +{ + t_linked_int *linked_int; + linked_int = (t_linked_int *) my_malloc (sizeof (t_linked_int)); + linked_int->data = data; + linked_int->next = head; + return (linked_int); +} + +t_linked_int* copy_from_list( t_linked_int* base, t_linked_int* target ) +{ + t_linked_int* traverse = target; + while ( target != NULL ) + { + base = insert_in_int_list2( base, target->data ); + target = target->next; + } + return base; +} + +/* end */ diff --git a/vpr7_rram/vpr/SRC/mrfpga/mrfpga_util.h b/vpr7_rram/vpr/SRC/mrfpga/mrfpga_util.h new file mode 100644 index 000000000..d0970629b --- /dev/null +++ b/vpr7_rram/vpr/SRC/mrfpga/mrfpga_util.h @@ -0,0 +1,15 @@ +/* Xifan TANG : + * Create a local copy of max and min exclusively for mrFPGA + */ + +#ifndef max +#define max(a,b) (((a) > (b))? (a) : (b)) +#endif + +#ifndef min +#define min(a,b) (((a) > (b))? (b) : (a)) +#endif + +t_linked_int* copy_from_list(t_linked_int* base, t_linked_int* target); + +t_linked_int* insert_in_int_list2(t_linked_int *head, int data); diff --git a/vpr7_rram/vpr/SRC/pack/cluster.c b/vpr7_rram/vpr/SRC/pack/cluster.c new file mode 100755 index 000000000..8ebd01b67 --- /dev/null +++ b/vpr7_rram/vpr/SRC/pack/cluster.c @@ -0,0 +1,2876 @@ +/* + * Main clustering algorithm + * Author(s): Vaughn Betz (first revision - VPack), Alexander Marquardt (second revision - T-VPack), Jason Luu (third revision - AAPack) + * June 8, 2011 + */ + +#include +#include +#include +#include +#include +#include + +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "cluster.h" +#include "heapsort.h" +#include "output_clustering.h" +#include "output_blif.h" +#include "SetupGrid.h" +#include "read_xml_arch_file.h" +#include "cluster_legality.h" +#include "path_delay2.h" +#include "path_delay.h" +#include "vpr_utils.h" +#include "cluster_placement.h" +#include "ReadOptions.h" + +/*#define DEBUG_FAILED_PACKING_CANDIDATES*/ + +#define AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC 2 /* Maximum relative number of pins that can exceed input pins before giving up */ +#define AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST 5 /* Maximum constant number of pins that can exceed input pins before giving up */ + +#define AAPACK_MAX_FEASIBLE_BLOCK_ARRAY_SIZE 30 /* This value is used to determine the max size of the priority queue for candidates that pass the early filter legality test but not the more detailed routing test */ +#define AAPACK_MAX_NET_SINKS_IGNORE 256 /* The packer looks at all sinks of a net when deciding what next candidate block to pack, for high-fanout nets, this is too runtime costly for marginal benefit, thus ignore those high fanout nets */ +#define AAPACK_MAX_HIGH_FANOUT_EXPLORE 10 /* For high-fanout nets that are ignored, consider a maximum of this many nets */ + +#define SCALE_NUM_PATHS 1e-2 /*this value is used as a multiplier to assign a * + *slightly higher criticality value to nets that * + *affect a large number of critical paths versus * + *nets that do not have such a broad effect. * + *Note that this multiplier is intentionally very * + *small compared to the total criticality because * + *we want to make sure that vpack_net criticality is * + *primarily determined by slacks, with this acting * + *only as a tie-breaker between otherwise equal nets*/ +#define SCALE_DISTANCE_VAL 1e-4 /*this value is used as a multiplier to assign a * + *slightly higher criticality value to nets that * + *are otherwise equal but one is farther * + *from sources (the farther one being made slightly * + *more critical) */ + +enum e_gain_update { + GAIN, NO_GAIN +}; +enum e_feasibility { + FEASIBLE, INFEASIBLE +}; +enum e_gain_type { + HILL_CLIMBING, NOT_HILL_CLIMBING +}; +enum e_removal_policy { + REMOVE_CLUSTERED, LEAVE_CLUSTERED +}; +/* TODO: REMOVE_CLUSTERED no longer used, remove */ +enum e_net_relation_to_clustered_block { + INPUT, OUTPUT +}; + +enum e_detailed_routing_stages { + E_DETAILED_ROUTE_AT_END_ONLY = 0, E_DETAILED_ROUTE_FOR_EACH_ATOM, E_DETAILED_ROUTE_END +}; + + +/* Linked list structure. Stores one integer (iblk). */ +struct s_molecule_link { + t_pack_molecule *moleculeptr; + struct s_molecule_link *next; +}; + +/* 1/MARKED_FRAC is the fraction of nets or blocks that must be * + * marked in order for the brute force (go through the whole * + * data structure linearly) gain update etc. code to be used. * + * This is done for speed only; make MARKED_FRAC whatever * + * number speeds the code up most. */ +#define MARKED_FRAC 2 + +/* Keeps a linked list of the unclustered blocks to speed up looking for * + * unclustered blocks with a certain number of *external* inputs. * + * [0..lut_size]. Unclustered_list_head[i] points to the head of the * + * list of blocks with i inputs to be hooked up via external interconnect. */ +static struct s_molecule_link *unclustered_list_head; +int unclustered_list_head_size; +static struct s_molecule_link *memory_pool; /*Declared here so I can free easily.*/ + +/* Does the logical_block that drives the output of this vpack_net also appear as a * + * receiver (input) pin of the vpack_net? [0..num_logical_nets-1]. If so, then by how much? This is used * + * in the gain routines to avoid double counting the connections from * + * the current cluster to other blocks (hence yielding better * + * clusterings). The only time a logical_block should connect to the same vpack_net * + * twice is when one connection is an output and the other is an input, * + * so this should take care of all multiple connections. */ +static int *net_output_feeds_driving_block_input; + +/* Timing information for blocks */ + +static float *block_criticality = NULL; +static int *critindexarray = NULL; + +/*****************************************/ +/*local functions*/ +/*****************************************/ + +static void check_clocks(boolean *is_clock); + +#if 0 +static void check_for_duplicate_inputs (); +#endif + +static boolean is_logical_blk_in_pb(int iblk, t_pb *pb); + +static void add_molecule_to_pb_stats_candidates(t_pack_molecule *molecule, + std::map &gain, t_pb *pb); + +static void alloc_and_init_clustering(boolean global_clocks, float alpha, + float beta, int max_cluster_size, int max_molecule_inputs, + int max_pb_depth, int max_models, + t_cluster_placement_stats **cluster_placement_stats, + t_pb_graph_node ***primitives_list, t_pack_molecule *molecules_head, + int num_molecules); +static void free_pb_stats_recursive(t_pb *pb); +static void try_update_lookahead_pins_used(t_pb *cur_pb); +static void reset_lookahead_pins_used(t_pb *cur_pb); +static void compute_and_mark_lookahead_pins_used(int ilogical_block); +static void compute_and_mark_lookahead_pins_used_for_pin( + t_pb_graph_pin *pb_graph_pin, t_pb *primitive_pb, int inet); +static void commit_lookahead_pins_used(t_pb *cur_pb); +static boolean check_lookahead_pins_used(t_pb *cur_pb); +static boolean primitive_feasible(int iblk, t_pb *cur_pb); +static boolean primitive_type_and_memory_feasible(int iblk, + const t_pb_type *cur_pb_type, t_pb *memory_class_pb, + int sibling_memory_blk); + +static t_pack_molecule *get_molecule_by_num_ext_inputs( + INP enum e_packer_algorithm packer_algorithm, INOUTP t_pb *cur_pb, + INP int ext_inps, INP enum e_removal_policy remove_flag, + INP t_cluster_placement_stats *cluster_placement_stats_ptr); + +static t_pack_molecule* get_free_molecule_with_most_ext_inputs_for_cluster( + INP enum e_packer_algorithm packer_algorithm, INOUTP t_pb *cur_pb, + INP t_cluster_placement_stats *cluster_placement_stats_ptr); + +static t_pack_molecule* get_seed_logical_molecule_with_most_ext_inputs( + int max_molecule_inputs); + +static enum e_block_pack_status try_pack_molecule( + INOUTP t_cluster_placement_stats *cluster_placement_stats_ptr, + INP t_pack_molecule *molecule, INOUTP t_pb_graph_node **primitives_list, + INOUTP t_pb * pb, INP int max_models, INP int max_cluster_size, + INP int clb_index, INP int max_nets_in_pb_type, INP int detailed_routing_stage); +static enum e_block_pack_status try_place_logical_block_rec( + INP t_pb_graph_node *pb_graph_node, INP int ilogical_block, + INP t_pb *cb, OUTP t_pb **parent, INP int max_models, + INP int max_cluster_size, INP int clb_index, + INP int max_nets_in_pb_type, + INP t_cluster_placement_stats *cluster_placement_stats_ptr, + INP boolean is_root_of_chain, INP t_pb_graph_pin *chain_root_pin); +static void revert_place_logical_block(INP int ilogical_block, + INP int max_models); + +static void update_connection_gain_values(int inet, int clustered_block, + t_pb * cur_pb, + enum e_net_relation_to_clustered_block net_relation_to_clustered_block); + +static void update_timing_gain_values(int inet, int clustered_block, + t_pb* cur_pb, + enum e_net_relation_to_clustered_block net_relation_to_clustered_block, + t_slack * slacks); + +static void mark_and_update_partial_gain(int inet, enum e_gain_update gain_flag, + int clustered_block, int port_on_clustered_block, + int pin_on_clustered_block, boolean timing_driven, + boolean connection_driven, + enum e_net_relation_to_clustered_block net_relation_to_clustered_block, + t_slack * slacks); + +static void update_total_gain(float alpha, float beta, boolean timing_driven, + boolean connection_driven, boolean global_clocks, t_pb *pb); + +static void update_cluster_stats( INP t_pack_molecule *molecule, + INP int clb_index, INP boolean *is_clock, INP boolean global_clocks, + INP float alpha, INP float beta, INP boolean timing_driven, + INP boolean connection_driven, INP t_slack * slacks); + +static void start_new_cluster( + INP t_cluster_placement_stats *cluster_placement_stats, + INP t_pb_graph_node **primitives_list, INP const t_arch * arch, + INOUTP t_block *new_cluster, INP int clb_index, + INP t_pack_molecule *molecule, INP float aspect, + INOUTP int *num_used_instances_type, INOUTP int *num_instances_type, + INP int num_models, INP int max_cluster_size, + INP int max_nets_in_pb_type, INP int detailed_routing_stage); + +static t_pack_molecule* get_highest_gain_molecule( + INP enum e_packer_algorithm packer_algorithm, INOUTP t_pb *cur_pb, + INP enum e_gain_type gain_mode, + INP t_cluster_placement_stats *cluster_placement_stats_ptr); + +static t_pack_molecule* get_molecule_for_cluster( + INP enum e_packer_algorithm packer_algorithm, INP t_pb *cur_pb, + INP boolean allow_unrelated_clustering, + INOUTP int *num_unrelated_clustering_attempts, + INP t_cluster_placement_stats *cluster_placement_stats_ptr); + +static void alloc_and_load_cluster_info(INP int num_clb, INOUTP t_block *clb); + +static void check_clustering(int num_clb, t_block *clb, boolean *is_clock); + +static void check_cluster_logical_blocks(t_pb *pb, boolean *blocks_checked); + +static t_pack_molecule* get_most_critical_seed_molecule(int * indexofcrit); + +static float get_molecule_gain(t_pack_molecule *molecule, std::map &blk_gain); +static int compare_molecule_gain(const void *a, const void *b); +static int get_net_corresponding_to_pb_graph_pin(t_pb *cur_pb, + t_pb_graph_pin *pb_graph_pin); + +static void print_block_criticalities(const char * fname); + +/*****************************************/ +/*globally accessable function*/ +void do_clustering(const t_arch *arch, t_pack_molecule *molecule_head, + int num_models, boolean global_clocks, boolean *is_clock, + boolean hill_climbing_flag, char *out_fname, boolean timing_driven, + enum e_cluster_seed cluster_seed_type, float alpha, float beta, + int recompute_timing_after, float block_delay, + float intra_cluster_net_delay, float inter_cluster_net_delay, + float aspect, boolean allow_unrelated_clustering, + boolean allow_early_exit, boolean connection_driven, + enum e_packer_algorithm packer_algorithm, t_timing_inf timing_inf) { + + /* Does the actual work of clustering multiple netlist blocks * + * into clusters. */ + + /* Algorithm employed + 1. Find type that can legally hold block and create cluster with pb info + 2. Populate started cluster + 3. Repeat 1 until no more blocks need to be clustered + + */ + + int i, iblk, num_molecules, blocks_since_last_analysis, num_clb, max_nets_in_pb_type, + cur_nets_in_pb_type, num_blocks_hill_added, max_cluster_size, cur_cluster_size, + max_molecule_inputs, max_pb_depth, cur_pb_depth, num_unrelated_clustering_attempts, + indexofcrit, savedindexofcrit /* index of next most timing critical block */, + detailed_routing_stage, *hill_climbing_inputs_avail; + + int *num_used_instances_type, *num_instances_type; + /* [0..num_types] Holds array for total number of each cluster_type available */ + + boolean early_exit, is_cluster_legal; + enum e_block_pack_status block_pack_status; + float crit; + + t_cluster_placement_stats *cluster_placement_stats, *cur_cluster_placement_stats_ptr; + t_pb_graph_node **primitives_list; + t_block *clb; + t_slack * slacks = NULL; + t_pack_molecule *istart, *next_molecule, *prev_molecule, *cur_molecule; + +#ifdef PATH_COUNTING + int inet, ipin; +#else + int inode; + float num_paths_scaling, distance_scaling; +#endif + + /* TODO: This is memory inefficient, fix if causes problems */ + clb = (t_block*)my_calloc(num_logical_blocks, sizeof(t_block)); + num_clb = 0; + istart = NULL; + + /* determine bound on cluster size and primitive input size */ + max_cluster_size = 0; + max_molecule_inputs = 0; + max_pb_depth = 0; + max_nets_in_pb_type = 0; + + indexofcrit = 0; + + cur_molecule = molecule_head; + num_molecules = 0; + while (cur_molecule != NULL) { + cur_molecule->valid = TRUE; + if (cur_molecule->num_ext_inputs > max_molecule_inputs) { + max_molecule_inputs = cur_molecule->num_ext_inputs; + } + num_molecules++; + cur_molecule = cur_molecule->next; + } + + for (i = 0; i < num_types; i++) { + if (EMPTY_TYPE == &type_descriptors[i]) + continue; + cur_cluster_size = get_max_primitives_in_pb_type( + type_descriptors[i].pb_type); + cur_pb_depth = get_max_depth_of_pb_type(type_descriptors[i].pb_type); + cur_nets_in_pb_type = get_max_nets_in_pb_type( + type_descriptors[i].pb_type); + if (cur_cluster_size > max_cluster_size) { + max_cluster_size = cur_cluster_size; + } + if (cur_pb_depth > max_pb_depth) { + max_pb_depth = cur_pb_depth; + } + if (cur_nets_in_pb_type > max_nets_in_pb_type) { + max_nets_in_pb_type = cur_nets_in_pb_type; + } + } + + if (hill_climbing_flag) { + hill_climbing_inputs_avail = (int *) my_calloc(max_cluster_size + 1, + sizeof(int)); + } else { + hill_climbing_inputs_avail = NULL; /* if used, die hard */ + } + + /* TODO: make better estimate for nx and ny */ + nx = ny = 1; + + check_clocks(is_clock); +#if 0 + check_for_duplicate_inputs (); +#endif + alloc_and_init_clustering(global_clocks, alpha, beta, max_cluster_size, + max_molecule_inputs, max_pb_depth, num_models, + &cluster_placement_stats, &primitives_list, molecule_head, + num_molecules); + + blocks_since_last_analysis = 0; + early_exit = FALSE; + num_blocks_hill_added = 0; + num_used_instances_type = (int*) my_calloc(num_types, sizeof(int)); + num_instances_type = (int*) my_calloc(num_types, sizeof(int)); + + assert(max_cluster_size < MAX_SHORT); + /* Limit maximum number of elements for each cluster */ + + if (timing_driven) { + slacks = alloc_and_load_pre_packing_timing_graph(block_delay, + inter_cluster_net_delay, arch->models, timing_inf); + do_timing_analysis(slacks, TRUE, FALSE, FALSE); + + if (getEchoEnabled()) { + if(isEchoFileEnabled(E_ECHO_PRE_PACKING_TIMING_GRAPH)) + print_timing_graph(getEchoFileName(E_ECHO_PRE_PACKING_TIMING_GRAPH)); +#ifndef PATH_COUNTING + if(isEchoFileEnabled(E_ECHO_CLUSTERING_TIMING_INFO)) + print_clustering_timing_info(getEchoFileName(E_ECHO_CLUSTERING_TIMING_INFO)); +#endif + if(isEchoFileEnabled(E_ECHO_PRE_PACKING_SLACK)) + print_slack(slacks->slack, FALSE, getEchoFileName(E_ECHO_PRE_PACKING_SLACK)); + if(isEchoFileEnabled(E_ECHO_PRE_PACKING_CRITICALITY)) + print_criticality(slacks, FALSE, getEchoFileName(E_ECHO_PRE_PACKING_CRITICALITY)); + } + + block_criticality = (float*) my_calloc(num_logical_blocks, sizeof(float)); + + critindexarray = (int*) my_malloc(num_logical_blocks * sizeof(int)); + + for (i = 0; i < num_logical_blocks; i++) { + assert(logical_block[i].index == i); + critindexarray[i] = i; + } + +#ifdef PATH_COUNTING + /* Calculate block criticality from a weighted sum of timing and path criticalities. */ + for (inet = 0; inet < num_logical_nets; inet++) { + for (ipin = 1; ipin <= vpack_net[inet].num_sinks; ipin++) { + + /* Find the logical block iblk which this pin is a sink on. */ + iblk = vpack_net[inet].node_block[ipin]; + + /* The criticality of this pin is a sum of its timing and path criticalities. */ + crit = PACK_PATH_WEIGHT * slacks->path_criticality[inet][ipin] + + (1 - PACK_PATH_WEIGHT) * slacks->timing_criticality[inet][ipin]; + + /* The criticality of each block is the maximum of the criticalities of all its pins. */ + if (block_criticality[iblk] < crit) { + block_criticality[iblk] = crit; + } + } + } + +#else + /* Calculate criticality based on slacks and tie breakers (# paths, distance from source) */ + for (inode = 0; inode < num_tnodes; inode++) { + /* Only calculate for tnodes which have valid normalized values. + Either all values will be accurate or none will, so we only have + to check whether one particular value (normalized_T_arr) is valid + Tnodes that do not have both times valid were not part of the analysis. + Because we calloc-ed the array criticality, such nodes will have criticality 0, the lowest possible value. */ + if (has_valid_normalized_T_arr(inode)) { + iblk = tnode[inode].block; + num_paths_scaling = SCALE_NUM_PATHS + * (float) tnode[inode].prepacked_data->normalized_total_critical_paths; + distance_scaling = SCALE_DISTANCE_VAL + * (float) tnode[inode].prepacked_data->normalized_T_arr; + crit = (1 - tnode[inode].prepacked_data->normalized_slack) + num_paths_scaling + + distance_scaling; + if (block_criticality[iblk] < crit) { + block_criticality[iblk] = crit; + } + } + } +#endif + heapsort(critindexarray, block_criticality, num_logical_blocks, 1); + + if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_CLUSTERING_BLOCK_CRITICALITIES)) { + print_block_criticalities(getEchoFileName(E_ECHO_CLUSTERING_BLOCK_CRITICALITIES)); + } + + + if (cluster_seed_type == VPACK_TIMING) { + istart = get_most_critical_seed_molecule(&indexofcrit); + } else {/*max input seed*/ + istart = get_seed_logical_molecule_with_most_ext_inputs( + max_molecule_inputs); + } + + } else /*cluster seed is max input (since there is no timing information)*/ { + istart = get_seed_logical_molecule_with_most_ext_inputs( + max_molecule_inputs); + } + + + while (istart != NULL) { + is_cluster_legal = FALSE; + savedindexofcrit = indexofcrit; + for (detailed_routing_stage = (int)E_DETAILED_ROUTE_AT_END_ONLY; !is_cluster_legal && detailed_routing_stage != (int)E_DETAILED_ROUTE_END; detailed_routing_stage++) { + reset_legalizer_for_cluster(&clb[num_clb]); + + /* start a new cluster and reset all stats */ + start_new_cluster(cluster_placement_stats, primitives_list, arch, + &clb[num_clb], num_clb, istart, aspect, num_used_instances_type, + num_instances_type, num_models, max_cluster_size, + max_nets_in_pb_type, detailed_routing_stage); + vpr_printf(TIO_MESSAGE_INFO, "Complex block %d: %s, type: %s\n", + num_clb, clb[num_clb].name, clb[num_clb].type->name); + vpr_printf(TIO_MESSAGE_INFO, "\t"); + fflush(stdout); + update_cluster_stats(istart, num_clb, is_clock, global_clocks, alpha, + beta, timing_driven, connection_driven, slacks); + num_clb++; + + if (timing_driven && !early_exit) { + blocks_since_last_analysis++; + /*it doesn't make sense to do a timing analysis here since there* + *is only one logical_block clustered it would not change anything */ + } + cur_cluster_placement_stats_ptr = &cluster_placement_stats[clb[num_clb - 1].type->index]; + num_unrelated_clustering_attempts = 0; + next_molecule = get_molecule_for_cluster(PACK_BRUTE_FORCE, + clb[num_clb - 1].pb, allow_unrelated_clustering, + &num_unrelated_clustering_attempts, + cur_cluster_placement_stats_ptr); + prev_molecule = istart; + while (next_molecule != NULL && prev_molecule != next_molecule) { + block_pack_status = try_pack_molecule(cur_cluster_placement_stats_ptr, next_molecule, + primitives_list, clb[num_clb - 1].pb, num_models, + max_cluster_size, num_clb - 1, max_nets_in_pb_type, + detailed_routing_stage); + prev_molecule = next_molecule; + if (block_pack_status != BLK_PASSED) { + if (next_molecule != NULL) { + if (block_pack_status == BLK_FAILED_ROUTE) { +#ifdef DEBUG_FAILED_PACKING_CANDIDATES + vpr_printf(TIO_MESSAGE_DIRECT, "\tNO_ROUTE:%s type %s/n", + next_molecule->logical_block_ptrs[next_molecule->root]->name, + next_molecule->logical_block_ptrs[next_molecule->root]->model->name); + fflush(stdout); + #else + vpr_printf(TIO_MESSAGE_DIRECT, "."); + #endif + } else { + #ifdef DEBUG_FAILED_PACKING_CANDIDATES + vpr_printf(TIO_MESSAGE_DIRECT, "\tFAILED_CHECK:%s type %s check %d\n", + next_molecule->logical_block_ptrs[next_molecule->root]->name, + next_molecule->logical_block_ptrs[next_molecule->root]->model->name, + block_pack_status); + fflush(stdout); + #else + vpr_printf(TIO_MESSAGE_DIRECT, "."); + #endif + } + } + + next_molecule = get_molecule_for_cluster(PACK_BRUTE_FORCE, + clb[num_clb - 1].pb, allow_unrelated_clustering, + &num_unrelated_clustering_attempts, + cur_cluster_placement_stats_ptr); + continue; + } else { + /* Continue packing by filling smallest cluster */ + #ifdef DEBUG_FAILED_PACKING_CANDIDATES + vpr_printf(TIO_MESSAGE_DIRECT, "\tPASSED:%s type %s\n", + next_molecule->logical_block_ptrs[next_molecule->root]->name, + next_molecule->logical_block_ptrs[next_molecule->root]->model->name); + fflush(stdout); + #else + vpr_printf(TIO_MESSAGE_DIRECT, "."); + #endif + } + update_cluster_stats(next_molecule, num_clb - 1, is_clock, + global_clocks, alpha, beta, timing_driven, + connection_driven, slacks); + num_unrelated_clustering_attempts = 0; + + if (timing_driven && !early_exit) { + blocks_since_last_analysis++; /* historically, timing slacks were recomputed after X number of blocks were packed, but this doesn't significantly alter results so I (jluu) did not port the code */ + } + next_molecule = get_molecule_for_cluster(PACK_BRUTE_FORCE, + clb[num_clb - 1].pb, allow_unrelated_clustering, + &num_unrelated_clustering_attempts, + cur_cluster_placement_stats_ptr); + } + vpr_printf(TIO_MESSAGE_DIRECT, "\n"); + if (detailed_routing_stage == (int)E_DETAILED_ROUTE_AT_END_ONLY) { + is_cluster_legal = try_breadth_first_route_cluster(); + if (is_cluster_legal == TRUE) { + vpr_printf(TIO_MESSAGE_INFO, "Passed route at end.\n"); + } else { + vpr_printf(TIO_MESSAGE_INFO, "Failed route at end, repack cluster trying detailed routing at each stage.\n"); + } + } else { + is_cluster_legal = TRUE; + } + if (is_cluster_legal == TRUE) { + save_cluster_solution(); + if (timing_driven) { + if (num_blocks_hill_added > 0 && !early_exit) { + blocks_since_last_analysis += num_blocks_hill_added; + } + if (cluster_seed_type == VPACK_TIMING) { + istart = get_most_critical_seed_molecule(&indexofcrit); + } else { /*max input seed*/ + istart = get_seed_logical_molecule_with_most_ext_inputs( + max_molecule_inputs); + } + } else + /*cluster seed is max input (since there is no timing information)*/ + istart = get_seed_logical_molecule_with_most_ext_inputs( + max_molecule_inputs); + + free_pb_stats_recursive(clb[num_clb - 1].pb); + } else { + /* Free up data structures and requeue used molecules */ + num_used_instances_type[clb[num_clb - 1].type->index]--; + free_cb(clb[num_clb - 1].pb); + free(clb[num_clb - 1].pb); + free(clb[num_clb - 1].name); + clb[num_clb - 1].name = NULL; + clb[num_clb - 1].pb = NULL; + num_clb--; + indexofcrit = savedindexofcrit; + } + } + } + + free_cluster_legality_checker(); + + alloc_and_load_cluster_info(num_clb, clb); + + check_clustering(num_clb, clb, is_clock); + + output_clustering(clb, num_clb, global_clocks, is_clock, out_fname, FALSE); + if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_POST_PACK_NETLIST)) { + output_blif (clb, num_clb, global_clocks, is_clock, + getEchoFileName(E_ECHO_POST_PACK_NETLIST), FALSE); + } + + if (hill_climbing_flag) { + free(hill_climbing_inputs_avail); + } + free_cluster_placement_stats(cluster_placement_stats); + + for (i = 0; i < num_clb; i++) { + free_cb(clb[i].pb); + free(clb[i].name); + free(clb[i].nets); + free(clb[i].pb); + } + free(clb); + + free(num_used_instances_type); + free(num_instances_type); + free(unclustered_list_head); + free(memory_pool); + free(net_output_feeds_driving_block_input); + + if (timing_driven) { + free(block_criticality); + free(critindexarray); + + block_criticality = NULL; + critindexarray = NULL; + } + + if (timing_driven) { + free_timing_graph(slacks); + } + + free (primitives_list); + +} + +/*****************************************/ +static void check_clocks(boolean *is_clock) { + + /* Checks that nets used as clock inputs to latches are never also used * + * as VPACK_LUT inputs. It's electrically questionable, and more importantly * + * would break the clustering code. */ + + int inet, iblk, ipin; + t_model_ports *port; + + for (iblk = 0; iblk < num_logical_blocks; iblk++) { + if (logical_block[iblk].type != VPACK_OUTPAD) { + port = logical_block[iblk].model->inputs; + while (port) { + for (ipin = 0; ipin < port->size; ipin++) { + inet = logical_block[iblk].input_nets[port->index][ipin]; + if (inet != OPEN) { + if (is_clock[inet]) { + vpr_printf(TIO_MESSAGE_ERROR, "Error in check_clocks.\n"); + vpr_printf(TIO_MESSAGE_ERROR, "Net %d (%s) is a clock, but also connects to a logic block input on logical_block %d (%s).\n", + inet, vpack_net[inet].name, iblk, logical_block[iblk].name); + vpr_printf(TIO_MESSAGE_ERROR, "This would break the current clustering implementation and is electrically questionable, so clustering has been aborted.\n"); + exit(1); + } + } + } + port = port->next; + } + } + } +} + +/* Determine if logical block is in pb */ +static boolean is_logical_blk_in_pb(int iblk, t_pb *pb) { + t_pb * cur_pb; + cur_pb = logical_block[iblk].pb; + while (cur_pb) { + if (cur_pb == pb) { + return TRUE; + } + cur_pb = cur_pb->parent_pb; + } + return FALSE; +} + +/* Add blk to list of feasible blocks sorted according to gain */ +static void add_molecule_to_pb_stats_candidates(t_pack_molecule *molecule, + std::map &gain, t_pb *pb) { + int i, j; + + for (i = 0; i < pb->pb_stats->num_feasible_blocks; i++) { + if (pb->pb_stats->feasible_blocks[i] == molecule) { + return; /* already in queue, do nothing */ + } + } + + if (pb->pb_stats->num_feasible_blocks >= AAPACK_MAX_FEASIBLE_BLOCK_ARRAY_SIZE - 1) { + /* maximum size for array, remove smallest gain element and sort */ + if (get_molecule_gain(molecule, gain) > get_molecule_gain(pb->pb_stats->feasible_blocks[0], gain)) { + /* single loop insertion sort */ + for (j = 0; j < pb->pb_stats->num_feasible_blocks - 1; j++) { + if (get_molecule_gain(molecule, gain) <= get_molecule_gain(pb->pb_stats->feasible_blocks[j + 1], gain)) { + pb->pb_stats->feasible_blocks[j] = molecule; + break; + } else { + pb->pb_stats->feasible_blocks[j] = pb->pb_stats->feasible_blocks[j + 1]; + } + } + if (j == pb->pb_stats->num_feasible_blocks - 1) { + pb->pb_stats->feasible_blocks[j] = molecule; + } + } + } else { + /* Expand array and single loop insertion sort */ + for (j = pb->pb_stats->num_feasible_blocks - 1; j >= 0; j--) { + if (get_molecule_gain(pb->pb_stats->feasible_blocks[j], gain) > get_molecule_gain(molecule, gain)) { + pb->pb_stats->feasible_blocks[j + 1] = pb->pb_stats->feasible_blocks[j]; + } else { + pb->pb_stats->feasible_blocks[j + 1] = molecule; + break; + } + } + if (j < 0) { + pb->pb_stats->feasible_blocks[0] = molecule; + } + pb->pb_stats->num_feasible_blocks++; + } +} + +/*****************************************/ +static void alloc_and_init_clustering(boolean global_clocks, float alpha, + float beta, int max_cluster_size, int max_molecule_inputs, + int max_pb_depth, int max_models, + t_cluster_placement_stats **cluster_placement_stats, + t_pb_graph_node ***primitives_list, t_pack_molecule *molecules_head, + int num_molecules) { + + /* Allocates the main data structures used for clustering and properly * + * initializes them. */ + + int i, ext_inps, ipin, driving_blk, inet; + struct s_molecule_link *next_ptr; + t_pack_molecule *cur_molecule; + t_pack_molecule **molecule_array; + int max_molecule_size; + + alloc_and_load_cluster_legality_checker(); + /**cluster_placement_stats = alloc_and_load_cluster_placement_stats();*/ + + for (i = 0; i < num_logical_blocks; i++) { + logical_block[i].clb_index = NO_CLUSTER; + } + + /* alloc and load list of molecules to pack */ + unclustered_list_head = (struct s_molecule_link *) my_calloc( + max_molecule_inputs + 1, sizeof(struct s_molecule_link)); + unclustered_list_head_size = max_molecule_inputs + 1; + + for (i = 0; i <= max_molecule_inputs; i++) { + unclustered_list_head[i].next = NULL; + } + + molecule_array = (t_pack_molecule **) my_malloc( + num_molecules * sizeof(t_pack_molecule*)); + cur_molecule = molecules_head; + for (i = 0; i < num_molecules; i++) { + assert(cur_molecule != NULL); + molecule_array[i] = cur_molecule; + cur_molecule = cur_molecule->next; + } + assert(cur_molecule == NULL); + qsort((void*) molecule_array, num_molecules, sizeof(t_pack_molecule*), + compare_molecule_gain); + + memory_pool = (struct s_molecule_link *) my_malloc( + num_molecules * sizeof(struct s_molecule_link)); + next_ptr = memory_pool; + + for (i = 0; i < num_molecules; i++) { + ext_inps = molecule_array[i]->num_ext_inputs; + next_ptr->moleculeptr = molecule_array[i]; + next_ptr->next = unclustered_list_head[ext_inps].next; + unclustered_list_head[ext_inps].next = next_ptr; + next_ptr++; + } + free(molecule_array); + + /* alloc and load net info */ + net_output_feeds_driving_block_input = (int *) my_malloc( + num_logical_nets * sizeof(int)); + + for (inet = 0; inet < num_logical_nets; inet++) { + net_output_feeds_driving_block_input[inet] = 0; + driving_blk = vpack_net[inet].node_block[0]; + for (ipin = 1; ipin <= vpack_net[inet].num_sinks; ipin++) { + if (vpack_net[inet].node_block[ipin] == driving_blk) { + net_output_feeds_driving_block_input[inet]++; + } + } + } + + /* alloc and load cluster placement info */ + *cluster_placement_stats = alloc_and_load_cluster_placement_stats(); + + /* alloc array that will store primitives that a molecule gets placed to, + primitive_list is referenced by index, for example a logical block in index 2 of a molecule matches to a primitive in index 2 in primitive_list + this array must be the size of the biggest molecule + */ + max_molecule_size = 1; + cur_molecule = molecules_head; + while (cur_molecule != NULL) { + if (cur_molecule->num_blocks > max_molecule_size) { + max_molecule_size = cur_molecule->num_blocks; + } + cur_molecule = cur_molecule->next; + } + *primitives_list = (t_pb_graph_node **)my_calloc(max_molecule_size, sizeof(t_pb_graph_node *)); +} + +/*****************************************/ +static void free_pb_stats_recursive(t_pb *pb) { + + int i, j; + /* Releases all the memory used by clustering data structures. */ + if (pb) { + if (pb->pb_graph_node != NULL) { + if (pb->pb_graph_node->pb_type->num_modes != 0) { + for (i = 0; + i + < pb->pb_graph_node->pb_type->modes[pb->mode].num_pb_type_children; + i++) { + for (j = 0; + j + < pb->pb_graph_node->pb_type->modes[pb->mode].pb_type_children[i].num_pb; + j++) { + if (pb->child_pbs && pb->child_pbs[i]) { + free_pb_stats_recursive(&pb->child_pbs[i][j]); + } + } + } + } + } + free_pb_stats(pb); + } +} + +static boolean primitive_feasible(int iblk, t_pb *cur_pb) { + const t_pb_type *cur_pb_type; + int i; + t_pb *memory_class_pb; /* Used for memory class only, for memories, open pins must be the same among siblings */ + int sibling_memory_blk; + + cur_pb_type = cur_pb->pb_graph_node->pb_type; + memory_class_pb = NULL; + sibling_memory_blk = OPEN; + + assert(cur_pb_type->num_modes == 0); + /* primitive */ + if (cur_pb->logical_block != OPEN && cur_pb->logical_block != iblk) { + /* This pb already has a different logical block */ + return FALSE; + } + + if (cur_pb_type->class_type == MEMORY_CLASS) { + /* memory class is special, all siblings must share all nets, including open nets, with the exception of data nets */ + /* find sibling if one exists */ + memory_class_pb = cur_pb->parent_pb; + for (i = 0; i < cur_pb_type->parent_mode->num_pb_type_children; i++) { + if (memory_class_pb->child_pbs[cur_pb->mode][i].name != NULL + && memory_class_pb->child_pbs[cur_pb->mode][i].logical_block != OPEN) { + sibling_memory_blk = memory_class_pb->child_pbs[cur_pb->mode][i].logical_block; + } + } + if (sibling_memory_blk == OPEN) { + memory_class_pb = NULL; + } + } + + return primitive_type_and_memory_feasible(iblk, cur_pb_type, + memory_class_pb, sibling_memory_blk); +} + +static boolean primitive_type_and_memory_feasible(int iblk, + const t_pb_type *cur_pb_type, t_pb *memory_class_pb, + int sibling_memory_blk) { + t_model_ports *port; + int i, j; + boolean second_pass; + + /* check if ports are big enough */ + /* for memories, also check that pins are the same with existing siblings */ + port = logical_block[iblk].model->inputs; + second_pass = FALSE; + while (port || !second_pass) { + /* TODO: This is slow if the number of ports are large, fix if becomes a problem */ + if (!port) { + second_pass = TRUE; + port = logical_block[iblk].model->outputs; + } + for (i = 0; i < cur_pb_type->num_ports; i++) { + if (cur_pb_type->ports[i].model_port == port) { + /* TODO: This is slow, I only need to check from 0 if it is a memory block, other blocks I can check from port->size onwards */ + for (j = 0; j < port->size; j++) { + if (port->dir == IN_PORT && !port->is_clock) { + if (memory_class_pb) { + if (cur_pb_type->ports[i].port_class == NULL + || strstr(cur_pb_type->ports[i].port_class,"data") != cur_pb_type->ports[i].port_class) { + if (logical_block[iblk].input_nets[port->index][j] != logical_block[sibling_memory_blk].input_nets[port->index][j]) { + return FALSE; + } + } + } + if (logical_block[iblk].input_nets[port->index][j] != OPEN + && j >= cur_pb_type->ports[i].num_pins) { + return FALSE; + } + } else if (port->dir == OUT_PORT) { + if (memory_class_pb) { + if (cur_pb_type->ports[i].port_class == NULL + || strstr(cur_pb_type->ports[i].port_class, "data") != cur_pb_type->ports[i].port_class) { + if (logical_block[iblk].output_nets[port->index][j] != logical_block[sibling_memory_blk].output_nets[port->index][j]) { + return FALSE; + } + } + } + if (logical_block[iblk].output_nets[port->index][j] != OPEN + && j >= cur_pb_type->ports[i].num_pins) { + return FALSE; + } + } else { + assert(port->dir == IN_PORT && port->is_clock); + assert(j == 0); + if (memory_class_pb) { + if (logical_block[iblk].clock_net != logical_block[sibling_memory_blk].clock_net) { + return FALSE; + } + } + if (logical_block[iblk].clock_net != OPEN && j >= cur_pb_type->ports[i].num_pins) { + return FALSE; + } + } + } + break; + } + } + if (i == cur_pb_type->num_ports) { + if (((logical_block[iblk].model->inputs != NULL) && !second_pass) + || (logical_block[iblk].model->outputs != NULL + && second_pass)) { + /* physical port not found */ + return FALSE; + } + } + if (port) { + port = port->next; + } + } + return TRUE; +} + +/*****************************************/ +static t_pack_molecule *get_molecule_by_num_ext_inputs( + INP enum e_packer_algorithm packer_algorithm, INOUTP t_pb *cur_pb, + INP int ext_inps, INP enum e_removal_policy remove_flag, + INP t_cluster_placement_stats *cluster_placement_stats_ptr) { + + /* This routine returns a logical_block which has not been clustered, has * + * no connection to the current cluster, satisfies the cluster * + * clock constraints, is a valid subblock inside the cluster, does not exceed the cluster subblock units available, + and has ext_inps external inputs. If * + * there is no such logical_block it returns NO_CLUSTER. Remove_flag * + * controls whether or not blocks that have already been clustered * + * are removed from the unclustered_list data structures. NB: * + * to get a logical_block regardless of clock constraints just set clocks_ * + * avail > 0. */ + + struct s_molecule_link *ptr, *prev_ptr; + int ilogical_blk, i; + boolean success; + + prev_ptr = &unclustered_list_head[ext_inps]; + ptr = unclustered_list_head[ext_inps].next; + while (ptr != NULL) { + /* TODO: Get better candidate logical block in future, eg. return most timing critical or some other smarter metric */ + /* TODO: (Xifan Tang) An alternation is to select the candidate that share the max. number of input/output nets to the other logic block with other primitives in the logic block */ + if (ptr->moleculeptr->valid) { + success = TRUE; + for (i = 0; i < get_array_size_of_molecule(ptr->moleculeptr); i++) { + if (ptr->moleculeptr->logical_block_ptrs[i] != NULL) { + ilogical_blk = ptr->moleculeptr->logical_block_ptrs[i]->index; + if (!exists_free_primitive_for_logical_block(cluster_placement_stats_ptr, ilogical_blk)) { /* TODO: I should be using a better filtering check especially when I'm dealing with multiple clock/multiple global reset signals where the clock/reset packed in matters, need to do later when I have the circuits to check my work */ + success = FALSE; + break; + } + } + } + if (success == TRUE) { + return ptr->moleculeptr; + } + prev_ptr = ptr; + } + + else if (remove_flag == REMOVE_CLUSTERED) { + assert(0); /* this doesn't work right now with 2 the pass packing for each complex block */ + prev_ptr->next = ptr->next; + } + + ptr = ptr->next; + } + + return NULL; +} + +/*****************************************/ +static t_pack_molecule *get_free_molecule_with_most_ext_inputs_for_cluster( + INP enum e_packer_algorithm packer_algorithm, INOUTP t_pb *cur_pb, + INP t_cluster_placement_stats *cluster_placement_stats_ptr) { + + /* This routine is used to find new blocks for clustering when there are no feasible * + * blocks with any attraction to the current cluster (i.e. it finds * + * blocks which are unconnected from the current cluster). It returns * + * the logical_block with the largest number of used inputs that satisfies the * + * clocking and number of inputs constraints. If no suitable logical_block is * + * found, the routine returns NO_CLUSTER. + * TODO: Analyze if this function is useful in more detail, also, should probably not include clock in input count + */ + + int ext_inps; + int i, j; + t_pack_molecule *molecule; + + int inputs_avail = 0; + + for (i = 0; i < cur_pb->pb_graph_node->num_input_pin_class; i++) { + for (j = 0; j < cur_pb->pb_graph_node->input_pin_class_size[i]; j++) { + if (cur_pb->pb_stats->input_pins_used[i][j] != OPEN) + inputs_avail++; + } + } + + molecule = NULL; + + if (inputs_avail >= unclustered_list_head_size) { + inputs_avail = unclustered_list_head_size - 1; + } + + for (ext_inps = inputs_avail; ext_inps >= 0; ext_inps--) { + molecule = get_molecule_by_num_ext_inputs(packer_algorithm, cur_pb, + ext_inps, LEAVE_CLUSTERED, cluster_placement_stats_ptr); + if (molecule != NULL) { + break; + } + } + return molecule; +} + +/*****************************************/ +static t_pack_molecule* get_seed_logical_molecule_with_most_ext_inputs( + int max_molecule_inputs) { + + /* This routine is used to find the first seed logical_block for the clustering. It returns * + * the logical_block with the largest number of used inputs that satisfies the * + * clocking and number of inputs constraints. If no suitable logical_block is * + * found, the routine returns NO_CLUSTER. */ + + int ext_inps; + struct s_molecule_link *ptr; + + for (ext_inps = max_molecule_inputs; ext_inps >= 0; ext_inps--) { + ptr = unclustered_list_head[ext_inps].next; + + while (ptr != NULL) { + if (ptr->moleculeptr->valid) { + return ptr->moleculeptr; + } + ptr = ptr->next; + } + } + return NULL; +} + +/*****************************************/ + +/*****************************************/ +static void alloc_and_load_pb_stats(t_pb *pb, int max_models, + int max_nets_in_pb_type) { + + /* Call this routine when starting to fill up a new cluster. It resets * + * the gain vector, etc. */ + + int i, j; + + pb->pb_stats = new t_pb_stats; + + /* If statement below is for speed. If nets are reasonably low-fanout, * + * only a relatively small number of blocks will be marked, and updating * + * only those logical_block structures will be fastest. If almost all blocks * + * have been touched it should be faster to just run through them all * + * in order (less addressing and better cache locality). */ + pb->pb_stats->input_pins_used = (int **) my_malloc( + pb->pb_graph_node->num_input_pin_class * sizeof(int*)); + pb->pb_stats->output_pins_used = (int **) my_malloc( + pb->pb_graph_node->num_output_pin_class * sizeof(int*)); + pb->pb_stats->lookahead_input_pins_used = (int **) my_malloc( + pb->pb_graph_node->num_input_pin_class * sizeof(int*)); + pb->pb_stats->lookahead_output_pins_used = (int **) my_malloc( + pb->pb_graph_node->num_output_pin_class * sizeof(int*)); + pb->pb_stats->num_feasible_blocks = NOT_VALID; + pb->pb_stats->feasible_blocks = (t_pack_molecule**) my_calloc( + AAPACK_MAX_FEASIBLE_BLOCK_ARRAY_SIZE, sizeof(t_pack_molecule *)); + + pb->pb_stats->tie_break_high_fanout_net = OPEN; + for (i = 0; i < pb->pb_graph_node->num_input_pin_class; i++) { + pb->pb_stats->input_pins_used[i] = (int*) my_malloc( + pb->pb_graph_node->input_pin_class_size[i] * sizeof(int)); + for (j = 0; j < pb->pb_graph_node->input_pin_class_size[i]; j++) { + pb->pb_stats->input_pins_used[i][j] = OPEN; + } + } + + for (i = 0; i < pb->pb_graph_node->num_output_pin_class; i++) { + pb->pb_stats->output_pins_used[i] = (int*) my_malloc( + pb->pb_graph_node->output_pin_class_size[i] * sizeof(int)); + for (j = 0; j < pb->pb_graph_node->output_pin_class_size[i]; j++) { + pb->pb_stats->output_pins_used[i][j] = OPEN; + } + } + + for (i = 0; i < pb->pb_graph_node->num_input_pin_class; i++) { + pb->pb_stats->lookahead_input_pins_used[i] = (int*) my_malloc( + (AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST + pb->pb_graph_node->input_pin_class_size[i] + * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC) * sizeof(int)); + for (j = 0; + j + < pb->pb_graph_node->input_pin_class_size[i] + * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC + AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST; j++) { + pb->pb_stats->lookahead_input_pins_used[i][j] = OPEN; + } + } + + for (i = 0; i < pb->pb_graph_node->num_output_pin_class; i++) { + pb->pb_stats->lookahead_output_pins_used[i] = (int*) my_malloc( + (AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST + + pb->pb_graph_node->output_pin_class_size[i] + * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC) * sizeof(int)); + for (j = 0; + j + < pb->pb_graph_node->output_pin_class_size[i] + * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC + AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST; j++) { + pb->pb_stats->lookahead_output_pins_used[i][j] = OPEN; + } + } + + pb->pb_stats->gain.clear(); + pb->pb_stats->timinggain.clear(); + pb->pb_stats->connectiongain.clear(); + pb->pb_stats->sharinggain.clear(); + pb->pb_stats->hillgain.clear(); + + pb->pb_stats->num_pins_of_net_in_pb.clear(); + + pb->pb_stats->marked_nets = (int *) my_malloc( + max_nets_in_pb_type * sizeof(int)); + pb->pb_stats->marked_blocks = (int *) my_malloc( + num_logical_blocks * sizeof(int)); + + pb->pb_stats->num_marked_nets = 0; + pb->pb_stats->num_marked_blocks = 0; + + pb->pb_stats->num_child_blocks_in_pb = 0; +} +/*****************************************/ + +/** + * Try pack molecule into current cluster + */ +static enum e_block_pack_status try_pack_molecule( + INOUTP t_cluster_placement_stats *cluster_placement_stats_ptr, + INP t_pack_molecule *molecule, INOUTP t_pb_graph_node **primitives_list, + INOUTP t_pb * pb, INP int max_models, INP int max_cluster_size, + INP int clb_index, INP int max_nets_in_pb_type, INP int detailed_routing_stage) { + int molecule_size, failed_location; + int i; + enum e_block_pack_status block_pack_status; + struct s_linked_vptr *cur_molecule; + t_pb *parent; + t_pb *cur_pb; + t_logical_block *chain_root_block; + boolean is_root_of_chain; + t_pb_graph_pin *chain_root_pin; + /* Xifan TANG: count the runtime for packing placement*/ + clock_t begin, end; + + parent = NULL; + + block_pack_status = BLK_STATUS_UNDEFINED; + + molecule_size = get_array_size_of_molecule(molecule); + failed_location = 0; + + while (block_pack_status != BLK_PASSED) { + save_and_reset_routing_cluster(); /* save current routing information because speculative packing will change routing*/ + if (get_next_primitive_list(cluster_placement_stats_ptr, molecule, + primitives_list, clb_index)) { + block_pack_status = BLK_PASSED; + + for (i = 0; i < molecule_size && block_pack_status == BLK_PASSED; + i++) { + assert( + (primitives_list[i] == NULL) == (molecule->logical_block_ptrs[i] == NULL)); + failed_location = i + 1; + if (molecule->logical_block_ptrs[i] != NULL) { + if(molecule->type == MOLECULE_FORCED_PACK && molecule->pack_pattern->is_chain && i == molecule->pack_pattern->root_block->block_id) { + chain_root_pin = molecule->pack_pattern->chain_root_pin; + is_root_of_chain = TRUE; + } else { + chain_root_pin = NULL; + is_root_of_chain = FALSE; + } + block_pack_status = try_place_logical_block_rec( + primitives_list[i], + molecule->logical_block_ptrs[i]->index, pb, &parent, + max_models, max_cluster_size, clb_index, + max_nets_in_pb_type, cluster_placement_stats_ptr, is_root_of_chain, chain_root_pin); + } + } + if (block_pack_status == BLK_PASSED) { + /* Check if pin usage is feasible for the current packing assigment */ + reset_lookahead_pins_used(pb); + try_update_lookahead_pins_used(pb); + if (!check_lookahead_pins_used(pb)) { + block_pack_status = BLK_FAILED_FEASIBLE; + } + } + if (block_pack_status == BLK_PASSED) { + /* start of pack placement */ + begin = clock(); + /* Try to route if heuristic is to route for every atom + Skip routing if heuristic is to route at the end of packing complex block + */ + setup_intracluster_routing_for_molecule(molecule, primitives_list); + if (detailed_routing_stage == (int)E_DETAILED_ROUTE_FOR_EACH_ATOM && try_breadth_first_route_cluster() == FALSE) { + /* Cannot pack */ + block_pack_status = BLK_FAILED_ROUTE; + } else { + /* Pack successful, commit + TODO: SW Engineering note - may want to update cluster stats here too instead of doing it outside + */ + assert(block_pack_status == BLK_PASSED); + if(molecule->type == MOLECULE_FORCED_PACK && molecule->pack_pattern->is_chain) { + /* Chained molecules often take up lots of area and are important, if a chain is packed in, want to rename logic block to match chain name */ + chain_root_block = molecule->logical_block_ptrs[molecule->pack_pattern->root_block->block_id]; + cur_pb = chain_root_block->pb->parent_pb; + while(cur_pb != NULL) { + free(cur_pb->name); + cur_pb->name = my_strdup(chain_root_block->name); + cur_pb = cur_pb->parent_pb; + } + } + for (i = 0; i < molecule_size; i++) { + if (molecule->logical_block_ptrs[i] != NULL) { + /* invalidate all molecules that share logical block with current molecule */ + cur_molecule = molecule->logical_block_ptrs[i]->packed_molecules; + while (cur_molecule != NULL) { + ((t_pack_molecule*) cur_molecule->data_vptr)->valid = FALSE; + cur_molecule = cur_molecule->next; + } + commit_primitive(cluster_placement_stats_ptr, primitives_list[i]); + } + } + } + /* end of pack route */ + end = clock(); + /* accumulate the runtime for pack route */ +#ifdef CLOCKS_PER_SEC + pack_route_time += (float)(end - begin)/ CLOCKS_PER_SEC; +#else + pack_route_time += (float)(end - begin)/ CLK_PER_SEC; +#endif + } + if (block_pack_status != BLK_PASSED) { + for (i = 0; i < failed_location; i++) { + if (molecule->logical_block_ptrs[i] != NULL) { + revert_place_logical_block(molecule->logical_block_ptrs[i]->index, max_models); + } + } + restore_routing_cluster(); + } + } else { + block_pack_status = BLK_FAILED_FEASIBLE; + restore_routing_cluster(); + break; /* no more candidate primitives available, this molecule will not pack, return fail */ + } + } + return block_pack_status; +} + +/** + * Try place logical block into current primitive location + */ + +static enum e_block_pack_status try_place_logical_block_rec( + INP t_pb_graph_node *pb_graph_node, INP int ilogical_block, + INP t_pb *cb, OUTP t_pb **parent, INP int max_models, + INP int max_cluster_size, INP int clb_index, + INP int max_nets_in_pb_type, + INP t_cluster_placement_stats *cluster_placement_stats_ptr, + INP boolean is_root_of_chain, INP t_pb_graph_pin *chain_root_pin) { + int i, j; + boolean is_primitive; + enum e_block_pack_status block_pack_status; + + t_pb *my_parent; + t_pb *pb, *parent_pb; + const t_pb_type *pb_type; + + t_model_ports *root_port; + + my_parent = NULL; + + block_pack_status = BLK_PASSED; + + /* Discover parent */ + if (pb_graph_node->parent_pb_graph_node != cb->pb_graph_node) { + block_pack_status = try_place_logical_block_rec( + pb_graph_node->parent_pb_graph_node, ilogical_block, cb, + &my_parent, max_models, max_cluster_size, clb_index, + max_nets_in_pb_type, cluster_placement_stats_ptr, is_root_of_chain, chain_root_pin); + parent_pb = my_parent; + } else { + parent_pb = cb; + } + + /* Create siblings if siblings are not allocated */ + if (parent_pb->child_pbs == NULL) { + assert(parent_pb->name == NULL); + parent_pb->logical_block = OPEN; + parent_pb->name = my_strdup(logical_block[ilogical_block].name); + parent_pb->mode = pb_graph_node->pb_type->parent_mode->index; + set_pb_graph_mode(parent_pb->pb_graph_node, 0, 0); /* TODO: default mode is to use mode 0, document this! */ + set_pb_graph_mode(parent_pb->pb_graph_node, parent_pb->mode, 1); + parent_pb->child_pbs = (t_pb **) my_calloc(parent_pb->pb_graph_node->pb_type->modes[parent_pb->mode].num_pb_type_children, sizeof(t_pb *)); + for (i = 0; i < parent_pb->pb_graph_node->pb_type->modes[parent_pb->mode].num_pb_type_children; i++) { + parent_pb->child_pbs[i] = (t_pb *) my_calloc(parent_pb->pb_graph_node->pb_type->modes[parent_pb->mode].pb_type_children[i].num_pb, sizeof(t_pb)); + for (j = 0; j < parent_pb->pb_graph_node->pb_type->modes[parent_pb->mode].pb_type_children[i].num_pb; j++) { + parent_pb->child_pbs[i][j].parent_pb = parent_pb; + parent_pb->child_pbs[i][j].logical_block = OPEN; + parent_pb->child_pbs[i][j].pb_graph_node = &(parent_pb->pb_graph_node->child_pb_graph_nodes[parent_pb->mode][i][j]); + } + } + } else { + assert(parent_pb->mode == pb_graph_node->pb_type->parent_mode->index); + } + + for (i = 0; i < parent_pb->pb_graph_node->pb_type->modes[parent_pb->mode].num_pb_type_children; i++) { + if (pb_graph_node->pb_type == &parent_pb->pb_graph_node->pb_type->modes[parent_pb->mode].pb_type_children[i]) { + break; + } + } + assert(i < parent_pb->pb_graph_node->pb_type->modes[parent_pb->mode].num_pb_type_children); + pb = &parent_pb->child_pbs[i][pb_graph_node->placement_index]; + *parent = pb; /* this pb is parent of it's child that called this function */ + assert(pb->pb_graph_node == pb_graph_node); + if (pb->pb_stats == NULL) { + alloc_and_load_pb_stats(pb, max_models, max_nets_in_pb_type); + } + pb_type = pb_graph_node->pb_type; + + is_primitive = (boolean) (pb_type->num_modes == 0); + + if (is_primitive) { + assert(pb->logical_block == OPEN && logical_block[ilogical_block].pb == NULL && logical_block[ilogical_block].clb_index == NO_CLUSTER); + /* try pack to location */ + pb->name = my_strdup(logical_block[ilogical_block].name); + pb->logical_block = ilogical_block; + logical_block[ilogical_block].clb_index = clb_index; + logical_block[ilogical_block].pb = pb; + + if (!primitive_feasible(ilogical_block, pb)) { + /* failed location feasibility check, revert pack */ + block_pack_status = BLK_FAILED_FEASIBLE; + } + + if (block_pack_status == BLK_PASSED && is_root_of_chain == TRUE) { + /* is carry chain, must check if this carry chain spans multiple logic blocks or not */ + root_port = chain_root_pin->port->model_port; + if(logical_block[ilogical_block].input_nets[root_port->index][chain_root_pin->pin_number] != OPEN) { + /* this carry chain spans multiple logic blocks, must match up correctly with previous chain for this to route */ + if(pb_graph_node != chain_root_pin->parent_node) { + /* this location does not match with the dedicated chain input from outside logic block, therefore not feasible */ + block_pack_status = BLK_FAILED_FEASIBLE; + } + } + } + } + + return block_pack_status; +} + +/* Revert trial logical block iblock and free up memory space accordingly + */ +static void revert_place_logical_block(INP int iblock, INP int max_models) { + t_pb *pb, *next; + + pb = logical_block[iblock].pb; + logical_block[iblock].clb_index = NO_CLUSTER; + logical_block[iblock].pb = NULL; + + if (pb != NULL) { + /* When freeing molecules, the current block might already have been freed by a prior revert + When this happens, no need to do anything beyond basic book keeping at the logical block + */ + + next = pb->parent_pb; + free_pb(pb); + pb = next; + + while (pb != NULL) { + /* If this is pb is created only for the purposes of holding new molecule, remove it + Must check if cluster is already freed (which can be the case) + */ + next = pb->parent_pb; + + if (pb->child_pbs != NULL && pb->pb_stats != NULL + && pb->pb_stats->num_child_blocks_in_pb == 0) { + set_pb_graph_mode(pb->pb_graph_node, pb->mode, 0); /* default mode is to use mode 1 */ + set_pb_graph_mode(pb->pb_graph_node, 0, 1); + if (next != NULL) { + /* If the code gets here, then that means that placing the initial seed molecule failed, don't free the actual complex block itself as the seed needs to find another placement */ + free_pb(pb); + } + } + pb = next; + } + } +} + +static void update_connection_gain_values(int inet, int clustered_block, + t_pb *cur_pb, + enum e_net_relation_to_clustered_block net_relation_to_clustered_block) { + /*This function is called when the connectiongain values on the vpack_net* + *inet require updating. */ + + int iblk, ipin; + int clb_index; + int num_internal_connections, num_open_connections, num_stuck_connections; + + num_internal_connections = num_open_connections = num_stuck_connections = 0; + + clb_index = logical_block[clustered_block].clb_index; + + /* may wish to speed things up by ignoring clock nets since they are high fanout */ + + for (ipin = 0; ipin <= vpack_net[inet].num_sinks; ipin++) { + iblk = vpack_net[inet].node_block[ipin]; + if (logical_block[iblk].clb_index == clb_index + && is_logical_blk_in_pb(iblk, + logical_block[clustered_block].pb)) { + num_internal_connections++; + } else if (logical_block[iblk].clb_index == OPEN) { + num_open_connections++; + } else { + num_stuck_connections++; + } + } + + if (net_relation_to_clustered_block == OUTPUT) { + for (ipin = 1; ipin <= vpack_net[inet].num_sinks; ipin++) { + iblk = vpack_net[inet].node_block[ipin]; + if (logical_block[iblk].clb_index == NO_CLUSTER) { + /* TODO: Gain function accurate only if net has one connection to block, TODO: Should we handle case where net has multi-connection to block? Gain computation is only off by a bit in this case */ + if(cur_pb->pb_stats->connectiongain.count(iblk) == 0) { + cur_pb->pb_stats->connectiongain[iblk] = 0; + } + + if (num_internal_connections > 1) { + cur_pb->pb_stats->connectiongain[iblk] -= 1 + / (float) (vpack_net[inet].num_sinks + - (num_internal_connections - 1) + + 1 * num_stuck_connections); + } + cur_pb->pb_stats->connectiongain[iblk] += 1 + / (float) (vpack_net[inet].num_sinks + - num_internal_connections + + 1 * num_stuck_connections); + } + } + } + + if (net_relation_to_clustered_block == INPUT) { + /*Calculate the connectiongain for the logical_block which is driving * + *the vpack_net that is an input to a logical_block in the cluster */ + + iblk = vpack_net[inet].node_block[0]; + if (logical_block[iblk].clb_index == NO_CLUSTER) { + if(cur_pb->pb_stats->connectiongain.count(iblk) == 0) { + cur_pb->pb_stats->connectiongain[iblk] = 0; + } + if (num_internal_connections > 1) { + cur_pb->pb_stats->connectiongain[iblk] -= 1 + / (float) (vpack_net[inet].num_sinks + - (num_internal_connections - 1) + 1 + + 1 * num_stuck_connections); + } + cur_pb->pb_stats->connectiongain[iblk] += 1 + / (float) (vpack_net[inet].num_sinks + - num_internal_connections + 1 + + 1 * num_stuck_connections); + } + } +} +/*****************************************/ +static void update_timing_gain_values(int inet, int clustered_block, + t_pb *cur_pb, + enum e_net_relation_to_clustered_block net_relation_to_clustered_block, t_slack * slacks) { + + /*This function is called when the timing_gain values on the vpack_net* + *inet requires updating. */ + float timinggain; + int newblk, ifirst; + int iblk, ipin; + + /* Check if this vpack_net lists its driving logical_block twice. If so, avoid * + * double counting this logical_block by skipping the first (driving) pin. */ + if (net_output_feeds_driving_block_input[inet] == FALSE) + ifirst = 0; + else + ifirst = 1; + + if (net_relation_to_clustered_block == OUTPUT + && !vpack_net[inet].is_global) { + for (ipin = ifirst; ipin <= vpack_net[inet].num_sinks; ipin++) { + iblk = vpack_net[inet].node_block[ipin]; + if (logical_block[iblk].clb_index == NO_CLUSTER) { +#ifdef PATH_COUNTING + /* Timing gain is a weighted sum of timing and path criticalities. */ + timinggain = TIMING_GAIN_PATH_WEIGHT * slacks->path_criticality[inet][ipin] + + (1 - TIMING_GAIN_PATH_WEIGHT) * slacks->timing_criticality[inet][ipin]; +#else + /* Timing gain is the timing criticality. */ + timinggain = slacks->timing_criticality[inet][ipin]; +#endif + if(cur_pb->pb_stats->timinggain.count(iblk) == 0) { + cur_pb->pb_stats->timinggain[iblk] = 0; + } + if (timinggain > cur_pb->pb_stats->timinggain[iblk]) + cur_pb->pb_stats->timinggain[iblk] = timinggain; + } + } + } + + if (net_relation_to_clustered_block == INPUT + && !vpack_net[inet].is_global) { + /*Calculate the timing gain for the logical_block which is driving * + *the vpack_net that is an input to a logical_block in the cluster */ + newblk = vpack_net[inet].node_block[0]; + if (logical_block[newblk].clb_index == NO_CLUSTER) { + for (ipin = 1; ipin <= vpack_net[inet].num_sinks; ipin++) { +#ifdef PATH_COUNTING + /* Timing gain is a weighted sum of timing and path criticalities. */ + timinggain = TIMING_GAIN_PATH_WEIGHT * slacks->path_criticality[inet][ipin] + + (1 - TIMING_GAIN_PATH_WEIGHT) * slacks->timing_criticality[inet][ipin]; +#else + /* Timing gain is the timing criticality. */ + timinggain = slacks->timing_criticality[inet][ipin]; +#endif + if(cur_pb->pb_stats->timinggain.count(newblk) == 0) { + cur_pb->pb_stats->timinggain[newblk] = 0; + } + if (timinggain > cur_pb->pb_stats->timinggain[newblk]) + cur_pb->pb_stats->timinggain[newblk] = timinggain; + + } + } + } +} +/*****************************************/ +static void mark_and_update_partial_gain(int inet, enum e_gain_update gain_flag, + int clustered_block, int port_on_clustered_block, + int pin_on_clustered_block, boolean timing_driven, + boolean connection_driven, + enum e_net_relation_to_clustered_block net_relation_to_clustered_block, + t_slack * slacks) { + + /* Updates the marked data structures, and if gain_flag is GAIN, * + * the gain when a logic logical_block is added to a cluster. The * + * sharinggain is the number of inputs that a logical_block shares with * + * blocks that are already in the cluster. Hillgain is the * + * reduction in number of pins-required by adding a logical_block to the * + * cluster. The timinggain is the criticality of the most critical* + * vpack_net between this logical_block and a logical_block in the cluster. */ + + int iblk, ipin, ifirst, stored_net; + t_pb *cur_pb; + + cur_pb = logical_block[clustered_block].pb->parent_pb; + + + if (vpack_net[inet].num_sinks > AAPACK_MAX_NET_SINKS_IGNORE) { + /* Optimization: It can be too runtime costly for marking all sinks for a high fanout-net that probably has no hope of ever getting packed, thus ignore those high fanout nets */ + if(vpack_net[inet].is_global != TRUE) { + /* If no low/medium fanout nets, we may need to consider high fan-out nets for packing, so select one and store it */ + while(cur_pb->parent_pb != NULL) { + cur_pb = cur_pb->parent_pb; + } + stored_net = cur_pb->pb_stats->tie_break_high_fanout_net; + if(stored_net == OPEN || vpack_net[inet].num_sinks < vpack_net[stored_net].num_sinks) { + cur_pb->pb_stats->tie_break_high_fanout_net = inet; + } + } + return; + } + + while (cur_pb) { + /* Mark vpack_net as being visited, if necessary. */ + + if (cur_pb->pb_stats->num_pins_of_net_in_pb.count(inet) == 0) { + cur_pb->pb_stats->marked_nets[cur_pb->pb_stats->num_marked_nets] = + inet; + cur_pb->pb_stats->num_marked_nets++; + } + + /* Update gains of affected blocks. */ + + if (gain_flag == GAIN) { + + /* Check if this vpack_net lists its driving logical_block twice. If so, avoid * + * double counting this logical_block by skipping the first (driving) pin. */ + + if (net_output_feeds_driving_block_input[inet] == 0) + ifirst = 0; + else + ifirst = 1; + + if (cur_pb->pb_stats->num_pins_of_net_in_pb.count(inet) == 0) { + for (ipin = ifirst; ipin <= vpack_net[inet].num_sinks; ipin++) { + iblk = vpack_net[inet].node_block[ipin]; + if (logical_block[iblk].clb_index == NO_CLUSTER) { + + if (cur_pb->pb_stats->sharinggain.count(iblk) == 0) { + cur_pb->pb_stats->marked_blocks[cur_pb->pb_stats->num_marked_blocks] = + iblk; + cur_pb->pb_stats->num_marked_blocks++; + cur_pb->pb_stats->sharinggain[iblk] = 1; + cur_pb->pb_stats->hillgain[iblk] = 1 + - num_ext_inputs_logical_block(iblk); + } else { + cur_pb->pb_stats->sharinggain[iblk]++; + cur_pb->pb_stats->hillgain[iblk]++; + } + } + } + } + + if (connection_driven) { + update_connection_gain_values(inet, clustered_block, cur_pb, + net_relation_to_clustered_block); + } + + if (timing_driven) { + update_timing_gain_values(inet, clustered_block, cur_pb, + net_relation_to_clustered_block, slacks); + } + } + if(cur_pb->pb_stats->num_pins_of_net_in_pb.count(inet) == 0) { + cur_pb->pb_stats->num_pins_of_net_in_pb[inet] = 0; + } + cur_pb->pb_stats->num_pins_of_net_in_pb[inet]++; + cur_pb = cur_pb->parent_pb; + } +} + +/*****************************************/ +static void update_total_gain(float alpha, float beta, boolean timing_driven, + boolean connection_driven, boolean global_clocks, t_pb *pb) { + + /*Updates the total gain array to reflect the desired tradeoff between* + *input sharing (sharinggain) and path_length minimization (timinggain)*/ + + int i, iblk, j, k; + t_pb * cur_pb; + int num_input_pins, num_output_pins; + int num_used_input_pins, num_used_output_pins; + t_model_ports *port; + + cur_pb = pb; + while (cur_pb) { + + for (i = 0; i < cur_pb->pb_stats->num_marked_blocks; i++) { + iblk = cur_pb->pb_stats->marked_blocks[i]; + + if(cur_pb->pb_stats->connectiongain.count(iblk) == 0) { + cur_pb->pb_stats->connectiongain[iblk] = 0; + } + if(cur_pb->pb_stats->sharinggain.count(iblk) == 0) { + cur_pb->pb_stats->connectiongain[iblk] = 0; + } + + /* Todo: This was used to explore different normalization options, can be made more efficient once we decide on which one to use*/ + num_input_pins = 0; + port = logical_block[iblk].model->inputs; + j = 0; + num_used_input_pins = 0; + while (port) { + num_input_pins += port->size; + if (!port->is_clock) { + for (k = 0; k < port->size; k++) { + if (logical_block[iblk].input_nets[j][k] != OPEN) { + num_used_input_pins++; + } + } + j++; + } + port = port->next; + } + if (num_input_pins == 0) { + num_input_pins = 1; + } + + num_used_output_pins = 0; + j = 0; + num_output_pins = 0; + port = logical_block[iblk].model->outputs; + while (port) { + num_output_pins += port->size; + for (k = 0; k < port->size; k++) { + if (logical_block[iblk].output_nets[j][k] != OPEN) { + num_used_output_pins++; + } + } + port = port->next; + j++; + } + /* end todo */ + + /* Calculate area-only cost function */ + if (connection_driven) { + /*try to absorb as many connections as possible*/ + /*cur_pb->pb_stats->gain[iblk] = ((1-beta)*(float)cur_pb->pb_stats->sharinggain[iblk] + beta*(float)cur_pb->pb_stats->connectiongain[iblk])/(num_input_pins + num_output_pins);*/ + cur_pb->pb_stats->gain[iblk] = ((1 - beta) + * (float) cur_pb->pb_stats->sharinggain[iblk] + + beta * (float) cur_pb->pb_stats->connectiongain[iblk]) + / (num_used_input_pins + num_used_output_pins); + } else { + /*cur_pb->pb_stats->gain[iblk] = ((float)cur_pb->pb_stats->sharinggain[iblk])/(num_input_pins + num_output_pins); */ + cur_pb->pb_stats->gain[iblk] = + ((float) cur_pb->pb_stats->sharinggain[iblk]) + / (num_used_input_pins + num_used_output_pins); + + } + + /* Add in timing driven cost into cost function */ + if (timing_driven) { + cur_pb->pb_stats->gain[iblk] = alpha + * cur_pb->pb_stats->timinggain[iblk] + + (1.0 - alpha) * (float) cur_pb->pb_stats->gain[iblk]; + } + } + cur_pb = cur_pb->parent_pb; + } +} + +/*****************************************/ +static void update_cluster_stats( INP t_pack_molecule *molecule, + INP int clb_index, INP boolean *is_clock, INP boolean global_clocks, + INP float alpha, INP float beta, INP boolean timing_driven, + INP boolean connection_driven, INP t_slack * slacks) { + + /* Updates cluster stats such as gain, used pins, and clock structures. */ + + int ipin, inet; + int new_blk, molecule_size; + int iblock; + t_model_ports *port; + t_pb *cur_pb, *cb; + + /* TODO: what a scary comment from Vaughn, we'll have to watch out for this causing problems */ + /* Output can be open so the check is necessary. I don't change * + * the gain for clock outputs when clocks are globally distributed * + * because I assume there is no real need to pack similarly clocked * + * FFs together then. Note that by updating the gain when the * + * clock driver is placed in a cluster implies that the output of * + * LUTs can be connected to clock inputs internally. Probably not * + * true, but it doesn't make much difference, since it will still * + * make local routing of this clock very short, and none of my * + * benchmarks actually generate local clocks (all come from pads). */ + + molecule_size = get_array_size_of_molecule(molecule); + cb = NULL; + + for (iblock = 0; iblock < molecule_size; iblock++) { + if (molecule->logical_block_ptrs[iblock] == NULL) { + continue; + } + new_blk = molecule->logical_block_ptrs[iblock]->index; + + logical_block[new_blk].clb_index = clb_index; + + cur_pb = logical_block[new_blk].pb->parent_pb; + while (cur_pb) { + /* reset list of feasible blocks */ + cur_pb->pb_stats->num_feasible_blocks = NOT_VALID; + cur_pb->pb_stats->num_child_blocks_in_pb++; + if (cur_pb->parent_pb == NULL) { + cb = cur_pb; + } + cur_pb = cur_pb->parent_pb; + } + + port = logical_block[new_blk].model->outputs; + while (port) { + for (ipin = 0; ipin < port->size; ipin++) { + inet = logical_block[new_blk].output_nets[port->index][ipin]; /* Output pin first. */ + if (inet != OPEN) { + if (!is_clock[inet] || !global_clocks) + mark_and_update_partial_gain(inet, GAIN, new_blk, + port->index, ipin, timing_driven, + connection_driven, OUTPUT, slacks); + else + mark_and_update_partial_gain(inet, NO_GAIN, new_blk, + port->index, ipin, timing_driven, + connection_driven, OUTPUT, slacks); + } + } + port = port->next; + } + port = logical_block[new_blk].model->inputs; + while (port) { + if (port->is_clock) { + port = port->next; + continue; + } + for (ipin = 0; ipin < port->size; ipin++) { /* VPACK_BLOCK input pins. */ + + inet = logical_block[new_blk].input_nets[port->index][ipin]; + if (inet != OPEN) { + mark_and_update_partial_gain(inet, GAIN, new_blk, + port->index, ipin, timing_driven, connection_driven, + INPUT, slacks); + } + } + port = port->next; + } + + /* Note: The code below ONLY WORKS when nets that go to clock inputs * + * NEVER go to the input of a VPACK_COMB. It doesn't really make electrical * + * sense for that to happen, and I check this in the check_clocks * + * function. Don't disable that sanity check. */ + inet = logical_block[new_blk].clock_net; /* Clock input pin. */ + if (inet != OPEN) { + if (global_clocks) + mark_and_update_partial_gain(inet, NO_GAIN, new_blk, 0, 0, + timing_driven, connection_driven, INPUT, slacks); + else + mark_and_update_partial_gain(inet, GAIN, new_blk, 0, 0, + timing_driven, connection_driven, INPUT, slacks); + + } + + update_total_gain(alpha, beta, timing_driven, connection_driven, + global_clocks, logical_block[new_blk].pb->parent_pb); + + commit_lookahead_pins_used(cb); + } + +} + +static void start_new_cluster( + INP t_cluster_placement_stats *cluster_placement_stats, + INOUTP t_pb_graph_node **primitives_list, INP const t_arch * arch, + INOUTP t_block *new_cluster, INP int clb_index, + INP t_pack_molecule *molecule, INP float aspect, + INOUTP int *num_used_instances_type, INOUTP int *num_instances_type, + INP int num_models, INP int max_cluster_size, + INP int max_nets_in_pb_type, INP int detailed_routing_stage) { + /* Given a starting seed block, start_new_cluster determines the next cluster type to use + It expands the FPGA if it cannot find a legal cluster for the logical block + */ + int i, j; + boolean success; + int count; + + assert(new_cluster->name == NULL); + /* Check if this cluster is really empty */ + + /* Allocate a dummy initial cluster and load a logical block as a seed and check if it is legal */ + new_cluster->name = (char*) my_malloc( + (strlen(molecule->logical_block_ptrs[molecule->root]->name) + 4) * sizeof(char)); + sprintf(new_cluster->name, "cb.%s", + molecule->logical_block_ptrs[molecule->root]->name); + new_cluster->nets = NULL; + new_cluster->type = NULL; + new_cluster->pb = NULL; + new_cluster->x = UNDEFINED; + new_cluster->y = UNDEFINED; + new_cluster->z = UNDEFINED; + + success = FALSE; + + while (!success) { + count = 0; + for (i = 0; i < num_types; i++) { + if (num_used_instances_type[i] < num_instances_type[i]) { + new_cluster->type = &type_descriptors[i]; + if (new_cluster->type == EMPTY_TYPE) { + continue; + } + new_cluster->pb = (t_pb*)my_calloc(1, sizeof(t_pb)); + new_cluster->pb->pb_graph_node = + new_cluster->type->pb_graph_head; + alloc_and_load_pb_stats(new_cluster->pb, num_models, + max_nets_in_pb_type); + new_cluster->pb->parent_pb = NULL; + + alloc_and_load_legalizer_for_cluster(new_cluster, clb_index, + arch); + for (j = 0; + j < new_cluster->type->pb_graph_head->pb_type->num_modes + && !success; j++) { + new_cluster->pb->mode = j; + reset_cluster_placement_stats(&cluster_placement_stats[i]); + set_mode_cluster_placement_stats( + new_cluster->pb->pb_graph_node, j); + success = (boolean) (BLK_PASSED + == try_pack_molecule(&cluster_placement_stats[i], + molecule, primitives_list, new_cluster->pb, + num_models, max_cluster_size, clb_index, + max_nets_in_pb_type, detailed_routing_stage)); + } + if (success) { + /* TODO: For now, just grab any working cluster, in the future, heuristic needed to grab best complex block based on supply and demand */ + break; + } else { + free_legalizer_for_cluster(new_cluster, TRUE); + free_pb_stats(new_cluster->pb); + free(new_cluster->pb); + } + count++; + } + } + if (count == num_types - 1) { + vpr_printf(TIO_MESSAGE_ERROR, "Can not find any logic block that can implement molecule.\n"); + if (molecule->type == MOLECULE_FORCED_PACK) { + vpr_printf(TIO_MESSAGE_ERROR, "\tPattern %s %s\n", + molecule->pack_pattern->name, + molecule->logical_block_ptrs[molecule->root]->name); + } else { + vpr_printf(TIO_MESSAGE_ERROR, "\tAtom %s\n", + molecule->logical_block_ptrs[molecule->root]->name); + } + exit(1); + } + + /* Expand FPGA size and recalculate number of available cluster types*/ + if (!success) { + if (aspect >= 1.0) { + ny++; + nx = nint(ny * aspect); + } else { + nx++; + ny = nint(nx / aspect); + } + vpr_printf(TIO_MESSAGE_INFO, "Not enough resources expand FPGA size to x = %d y = %d.\n", + nx, ny); + if ((nx > MAX_SHORT) || (ny > MAX_SHORT)) { + vpr_printf(TIO_MESSAGE_ERROR, "Circuit cannot pack into architecture, architecture size (nx = %d, ny = %d) exceeds packer range.\n", + nx, ny); + exit(1); + } + alloc_and_load_grid(num_instances_type); + freeGrid(); + } + } + num_used_instances_type[new_cluster->type->index]++; +} + +/*****************************************/ +static t_pack_molecule *get_highest_gain_molecule( + INP enum e_packer_algorithm packer_algorithm, INOUTP t_pb *cur_pb, + INP enum e_gain_type gain_mode, + INP t_cluster_placement_stats *cluster_placement_stats_ptr) { + + /* This routine populates a list of feasible blocks outside the cluster then returns the best one for the list * + * not currently in a cluster and satisfies the feasibility * + * function passed in as is_feasible. If there are no feasible * + * blocks it returns NO_CLUSTER. */ + + int i, j, iblk, index, inet, count; + boolean success; + struct s_linked_vptr *cur; + + t_pack_molecule *molecule; + molecule = NULL; + + if (gain_mode == HILL_CLIMBING) { + vpr_printf(TIO_MESSAGE_ERROR, "Hill climbing not supported yet, error out.\n"); + exit(1); + } + + if (cur_pb->pb_stats->num_feasible_blocks == NOT_VALID) { + /* Divide into two cases for speed only. */ + /* Typical case: not too many blocks have been marked. */ + + cur_pb->pb_stats->num_feasible_blocks = 0; + + if (cur_pb->pb_stats->num_marked_blocks < num_logical_blocks / MARKED_FRAC) { + for (i = 0; i < cur_pb->pb_stats->num_marked_blocks; i++) { + iblk = cur_pb->pb_stats->marked_blocks[i]; + if (logical_block[iblk].clb_index == NO_CLUSTER) { + cur = logical_block[iblk].packed_molecules; + while (cur != NULL) { + molecule = (t_pack_molecule *) cur->data_vptr; + if (molecule->valid) { + success = TRUE; + for (j = 0; j < get_array_size_of_molecule(molecule); j++) { + if (molecule->logical_block_ptrs[j] != NULL) { + assert(molecule->logical_block_ptrs[j]->clb_index == NO_CLUSTER); + if (!exists_free_primitive_for_logical_block(cluster_placement_stats_ptr,iblk)) { /* TODO: debating whether to check if placement exists for molecule (more robust) or individual logical blocks (faster) */ + success = FALSE; + break; + } + } + } + if (success) { + add_molecule_to_pb_stats_candidates(molecule, + cur_pb->pb_stats->gain, cur_pb); + } + } + cur = cur->next; + } + } + } + } else { /* Some high fanout nets marked lots of blocks. */ + for (iblk = 0; iblk < num_logical_blocks; iblk++) { + if (logical_block[iblk].clb_index == NO_CLUSTER) { + cur = logical_block[iblk].packed_molecules; + while (cur != NULL) { + molecule = (t_pack_molecule *) cur->data_vptr; + if (molecule->valid) { + success = TRUE; + for (j = 0; j < get_array_size_of_molecule(molecule);j++) { + if (molecule->logical_block_ptrs[j] != NULL) { + assert(molecule->logical_block_ptrs[j]->clb_index == NO_CLUSTER); + if (!exists_free_primitive_for_logical_block( + cluster_placement_stats_ptr, + iblk)) { + success = FALSE; + break; + } + } + } + if (success) { + add_molecule_to_pb_stats_candidates(molecule, cur_pb->pb_stats->gain, cur_pb); + } + } + cur = cur->next; + } + } + } + } + } + if(cur_pb->pb_stats->num_feasible_blocks == 0 && cur_pb->pb_stats->tie_break_high_fanout_net != OPEN) { + /* Because the packer ignores high fanout nets when marking what blocks to consider, use one of the ignored high fanout net to fill up lightly related blocks */ + reset_tried_but_unused_cluster_placements(cluster_placement_stats_ptr); + inet = cur_pb->pb_stats->tie_break_high_fanout_net; + count = 0; + for (i = 0; i <= vpack_net[inet].num_sinks && count < AAPACK_MAX_HIGH_FANOUT_EXPLORE; i++) { + iblk = vpack_net[inet].node_block[i]; + if (logical_block[iblk].clb_index == NO_CLUSTER) { + cur = logical_block[iblk].packed_molecules; + while (cur != NULL) { + molecule = (t_pack_molecule *) cur->data_vptr; + if (molecule->valid) { + success = TRUE; + for (j = 0; + j < get_array_size_of_molecule(molecule); + j++) { + if (molecule->logical_block_ptrs[j] != NULL) { + assert(molecule->logical_block_ptrs[j]->clb_index == NO_CLUSTER); + if (!exists_free_primitive_for_logical_block(cluster_placement_stats_ptr,iblk)) { /* TODO: debating whether to check if placement exists for molecule (more robust) or individual logical blocks (faster) */ + success = FALSE; + break; + } + } + } + if (success) { + add_molecule_to_pb_stats_candidates(molecule, + cur_pb->pb_stats->gain, cur_pb); + count++; + } + } + cur = cur->next; + } + } + } + cur_pb->pb_stats->tie_break_high_fanout_net = OPEN; /* Mark off that this high fanout net has been considered */ + } + molecule = NULL; + for (j = 0; j < cur_pb->pb_stats->num_feasible_blocks; j++) { + if (cur_pb->pb_stats->num_feasible_blocks != 0) { + cur_pb->pb_stats->num_feasible_blocks--; + index = cur_pb->pb_stats->num_feasible_blocks; + molecule = cur_pb->pb_stats->feasible_blocks[index]; + assert(molecule->valid == TRUE); + return molecule; + } + } + + return molecule; +} + +/*****************************************/ +static t_pack_molecule *get_molecule_for_cluster( + INP enum e_packer_algorithm packer_algorithm, INOUTP t_pb *cur_pb, + INP boolean allow_unrelated_clustering, + INOUTP int *num_unrelated_clustering_attempts, + INP t_cluster_placement_stats *cluster_placement_stats_ptr) { + + /* Finds the vpack block with the the greatest gain that satisifies the * + * input, clock and capacity constraints of a cluster that are * + * passed in. If no suitable vpack block is found it returns NO_CLUSTER. + */ + + t_pack_molecule *best_molecule; + + /* If cannot pack into primitive, try packing into cluster */ + + best_molecule = get_highest_gain_molecule(packer_algorithm, cur_pb, + NOT_HILL_CLIMBING, cluster_placement_stats_ptr); + + /* If no blocks have any gain to the current cluster, the code above * + * will not find anything. However, another logical_block with no inputs in * + * common with the cluster may still be inserted into the cluster. */ + + if (allow_unrelated_clustering) { + if (best_molecule == NULL) { + if (*num_unrelated_clustering_attempts == 0) { + best_molecule = get_free_molecule_with_most_ext_inputs_for_cluster( + packer_algorithm, cur_pb, + cluster_placement_stats_ptr); + (*num_unrelated_clustering_attempts)++; + } + } else { + *num_unrelated_clustering_attempts = 0; + } + } + + return best_molecule; +} + +/*****************************************/ +static void alloc_and_load_cluster_info(INP int num_clb, INOUTP t_block *clb) { + + /* Loads all missing clustering info necessary to complete clustering. */ + int i, j, i_clb, node_index, ipin, iclass; + int inport, outport, clockport; + + const t_pb_type * pb_type; + t_pb *pb; + + for (i_clb = 0; i_clb < num_clb; i_clb++) { + rr_node = clb[i_clb].pb->rr_graph; + pb_type = clb[i_clb].pb->pb_graph_node->pb_type; + pb = clb[i_clb].pb; + + clb[i_clb].nets = (int*)my_malloc(clb[i_clb].type->num_pins * sizeof(int)); + for (i = 0; i < clb[i_clb].type->num_pins; i++) { + clb[i_clb].nets[i] = OPEN; + } + + inport = outport = clockport = 0; + ipin = 0; + /* Assume top-level pb and clb share a one-to-one connection */ + for (i = 0; i < pb_type->num_ports; i++) { + if (!pb_type->ports[i].is_clock + && pb_type->ports[i].type == IN_PORT) { + for (j = 0; j < pb_type->ports[i].num_pins; j++) { + iclass = clb[i_clb].type->pin_class[ipin]; + assert(clb[i_clb].type->class_inf[iclass].type == RECEIVER); + assert(clb[i_clb].type->is_global_pin[ipin] == pb->pb_graph_node->input_pins[inport][j].port->is_non_clock_global); + node_index = + pb->pb_graph_node->input_pins[inport][j].pin_count_in_cluster; + clb[i_clb].nets[ipin] = rr_node[node_index].net_num; + ipin++; + } + inport++; + } else if (pb_type->ports[i].type == OUT_PORT) { + for (j = 0; j < pb_type->ports[i].num_pins; j++) { + iclass = clb[i_clb].type->pin_class[ipin]; + assert(clb[i_clb].type->class_inf[iclass].type == DRIVER); + node_index = + pb->pb_graph_node->output_pins[outport][j].pin_count_in_cluster; + clb[i_clb].nets[ipin] = rr_node[node_index].net_num; + ipin++; + } + outport++; + } else { + assert( + pb_type->ports[i].is_clock && pb_type->ports[i].type == IN_PORT); + for (j = 0; j < pb_type->ports[i].num_pins; j++) { + iclass = clb[i_clb].type->pin_class[ipin]; + assert(clb[i_clb].type->class_inf[iclass].type == RECEIVER); + assert(clb[i_clb].type->is_global_pin[ipin]); + node_index = + pb->pb_graph_node->clock_pins[clockport][j].pin_count_in_cluster; + clb[i_clb].nets[ipin] = rr_node[node_index].net_num; + ipin++; + } + clockport++; + } + } + } +} + +/* TODO: Add more error checking, too light */ +/*****************************************/ +static void check_clustering(int num_clb, t_block *clb, boolean *is_clock) { + int i; + t_pb * cur_pb; + boolean * blocks_checked; + + blocks_checked = (boolean*)my_calloc(num_logical_blocks, sizeof(boolean)); + + /* + * Check that each logical block connects to one primitive and that the primitive links up to the parent clb + */ + for (i = 0; i < num_blocks; i++) { + if (logical_block[i].pb->logical_block != i) { + vpr_printf(TIO_MESSAGE_ERROR, "pb %s does not contain logical block %s but logical block %s #%d links to pb.\n", + logical_block[i].pb->name, logical_block[i].name, logical_block[i].name, i); + exit(1); + } + cur_pb = logical_block[i].pb; + assert(strcmp(cur_pb->name, logical_block[i].name) == 0); + while (cur_pb->parent_pb) { + cur_pb = cur_pb->parent_pb; + assert(cur_pb->name); + } + if (cur_pb != clb[num_clb].pb) { + vpr_printf(TIO_MESSAGE_ERROR, "CLB %s does not match CLB contained by pb %s.\n", + cur_pb->name, logical_block[i].pb->name); + exit(1); + } + } + + /* Check that I do not have spurious links in children pbs */ + for (i = 0; i < num_clb; i++) { + check_cluster_logical_blocks(clb[i].pb, blocks_checked); + } + + for (i = 0; i < num_logical_blocks; i++) { + if (blocks_checked[i] == FALSE) { + vpr_printf(TIO_MESSAGE_ERROR, "Logical block %s #%d not found in any cluster.\n", + logical_block[i].name, i); + exit(1); + } + } + + free(blocks_checked); +} + +/* TODO: May want to check that all logical blocks are actually reached (low priority, nice to have) */ +static void check_cluster_logical_blocks(t_pb *pb, boolean *blocks_checked) { + int i, j; + const t_pb_type *pb_type; + boolean has_child; + + has_child = FALSE; + pb_type = pb->pb_graph_node->pb_type; + if (pb_type->num_modes == 0) { + /* primitive */ + if (pb->logical_block != OPEN) { + if (blocks_checked[pb->logical_block] != FALSE) { + vpr_printf(TIO_MESSAGE_ERROR, "pb %s contains logical block %s #%d but logical block is already contained in another pb.\n", + pb->name, logical_block[pb->logical_block].name, pb->logical_block); + exit(1); + } + blocks_checked[pb->logical_block] = TRUE; + if (pb != logical_block[pb->logical_block].pb) { + vpr_printf(TIO_MESSAGE_ERROR, "pb %s contains logical block %s #%d but logical block does not link to pb.\n", + pb->name, logical_block[pb->logical_block].name, pb->logical_block); + exit(1); + } + } + } else { + /* this is a container pb, all container pbs must contain children */ + for (i = 0; i < pb_type->modes[pb->mode].num_pb_type_children; i++) { + for (j = 0; j < pb_type->modes[pb->mode].pb_type_children[i].num_pb; + j++) { + if (pb->child_pbs[i] != NULL) { + if (pb->child_pbs[i][j].name != NULL) { + has_child = TRUE; + check_cluster_logical_blocks(&pb->child_pbs[i][j], + blocks_checked); + } + } + } + } + assert(has_child); + } +} + +static t_pack_molecule* get_most_critical_seed_molecule(int * indexofcrit) { + /* Do_timing_analysis must be called before this, or this function + * will return garbage. Returns molecule with most critical block; + * if block belongs to multiple molecules, return the biggest molecule. */ + + int blkidx; + t_pack_molecule *molecule, *best; + struct s_linked_vptr *cur; + + while (*indexofcrit < num_logical_blocks) { + + blkidx = critindexarray[(*indexofcrit)++]; + + if (logical_block[blkidx].clb_index == NO_CLUSTER) { + cur = logical_block[blkidx].packed_molecules; + best = NULL; + while (cur != NULL) { + molecule = (t_pack_molecule *) cur->data_vptr; + if (molecule->valid) { + if (best == NULL + || (best->base_gain) < (molecule->base_gain)) { + best = molecule; + } + } + cur = cur->next; + } + assert(best != NULL); + return best; + } + } + + /*if it makes it to here , there are no more blocks available*/ + return NULL; +} + +/* get gain of packing molecule into current cluster + gain is equal to total_block_gain + molecule_base_gain*some_factor - introduced_input_nets_of_unrelated_blocks_pulled_in_by_molecule*some_other_factor + + */ +static float get_molecule_gain(t_pack_molecule *molecule, std::map &blk_gain) { + float gain; + int i, ipin, iport, inet, iblk; + int num_introduced_inputs_of_indirectly_related_block; + t_model_ports *cur; + + gain = 0; + num_introduced_inputs_of_indirectly_related_block = 0; + for (i = 0; i < get_array_size_of_molecule(molecule); i++) { + if (molecule->logical_block_ptrs[i] != NULL) { + if(blk_gain.count(molecule->logical_block_ptrs[i]->index) > 0) { + gain += blk_gain[molecule->logical_block_ptrs[i]->index]; + } else { + /* This block has no connection with current cluster, penalize molecule for having this block + */ + cur = molecule->logical_block_ptrs[i]->model->inputs; + iport = 0; + while (cur != NULL) { + if (cur->is_clock != TRUE) { + for (ipin = 0; ipin < cur->size; ipin++) { + inet = molecule->logical_block_ptrs[i]->input_nets[iport][ipin]; + if (inet != OPEN) { + num_introduced_inputs_of_indirectly_related_block++; + for (iblk = 0; iblk < get_array_size_of_molecule(molecule); iblk++) { + if (molecule->logical_block_ptrs[iblk] != NULL + && vpack_net[inet].node_block[0] == molecule->logical_block_ptrs[iblk]->index) { + num_introduced_inputs_of_indirectly_related_block--; + break; + } + } + } + } + iport++; + } + cur = cur->next; + } + } + } + } + + gain += molecule->base_gain * 0.0001; /* Use base gain as tie breaker TODO: need to sweep this value and perhaps normalize */ + gain -= num_introduced_inputs_of_indirectly_related_block * (0.001); + + return gain; +} + +static int compare_molecule_gain(const void *a, const void *b) { + float base_gain_a, base_gain_b, diff; + const t_pack_molecule *molecule_a, *molecule_b; + molecule_a = (*(const t_pack_molecule * const *) a); + molecule_b = (*(const t_pack_molecule * const *) b); + + base_gain_a = molecule_a->base_gain; + base_gain_b = molecule_b->base_gain; + diff = base_gain_a - base_gain_b; + if (diff > 0) { + return 1; + } + if (diff < 0) { + return -1; + } + return 0; +} + +/* Determine if speculatively packed cur_pb is pin feasible + * Runtime is actually not that bad for this. It's worst case O(k^2) where k is the number of pb_graph pins. Can use hash tables or make incremental if becomes an issue. + */ +static void try_update_lookahead_pins_used(t_pb *cur_pb) { + int i, j; + const t_pb_type *pb_type = cur_pb->pb_graph_node->pb_type; + + if (pb_type->num_modes > 0 && cur_pb->name != NULL) { + if (cur_pb->child_pbs != NULL) { + for (i = 0; i < pb_type->modes[cur_pb->mode].num_pb_type_children; + i++) { + if (cur_pb->child_pbs[i] != NULL) { + for (j = 0; + j + < pb_type->modes[cur_pb->mode].pb_type_children[i].num_pb; + j++) { + try_update_lookahead_pins_used( + &cur_pb->child_pbs[i][j]); + } + } + } + } + } else { + if (pb_type->blif_model != NULL && cur_pb->logical_block != OPEN) { + compute_and_mark_lookahead_pins_used(cur_pb->logical_block); + } + } +} + +/* Resets nets used at different pin classes for determining pin feasibility */ +static void reset_lookahead_pins_used(t_pb *cur_pb) { + int i, j; + const t_pb_type *pb_type = cur_pb->pb_graph_node->pb_type; + if (cur_pb->pb_stats == NULL) { + return; /* No pins used, no need to continue */ + } + + if (pb_type->num_modes > 0 && cur_pb->name != NULL) { + for (i = 0; i < cur_pb->pb_graph_node->num_input_pin_class; i++) { + for (j = 0; + j + < cur_pb->pb_graph_node->input_pin_class_size[i] + * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC + AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST; + j++) { + cur_pb->pb_stats->lookahead_input_pins_used[i][j] = OPEN; + } + } + + for (i = 0; i < cur_pb->pb_graph_node->num_output_pin_class; i++) { + for (j = 0; + j + < cur_pb->pb_graph_node->output_pin_class_size[i] + * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC + AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST; + j++) { + cur_pb->pb_stats->lookahead_output_pins_used[i][j] = OPEN; + } + } + + if (cur_pb->child_pbs != NULL) { + for (i = 0; i < pb_type->modes[cur_pb->mode].num_pb_type_children; + i++) { + if (cur_pb->child_pbs[i] != NULL) { + for (j = 0; + j + < pb_type->modes[cur_pb->mode].pb_type_children[i].num_pb; + j++) { + reset_lookahead_pins_used(&cur_pb->child_pbs[i][j]); + } + } + } + } + } +} + +/* Determine if pins of speculatively packed pb are legal */ +static void compute_and_mark_lookahead_pins_used(int ilogical_block) { + int i, j; + t_pb *cur_pb; + t_pb_graph_node *pb_graph_node; + const t_pb_type *pb_type; + t_port *prim_port; + + int input_port; + int output_port; + int clock_port; + + assert(logical_block[ilogical_block].pb != NULL); + + cur_pb = logical_block[ilogical_block].pb; + pb_graph_node = cur_pb->pb_graph_node; + pb_type = pb_graph_node->pb_type; + + /* Walk through inputs, outputs, and clocks marking pins off of the same class */ + /* TODO: This is inelegant design, I should change the primitive ports in pb_type to be input, output, or clock instead of this lookup */ + input_port = output_port = clock_port = 0; + for (i = 0; i < pb_type->num_ports; i++) { + prim_port = &pb_type->ports[i]; + if (prim_port->is_clock) { + assert(prim_port->type == IN_PORT); + assert(prim_port->num_pins == 1 && clock_port == 0); + /* currently support only one clock for primitives */ + if (logical_block[ilogical_block].clock_net != OPEN) { + compute_and_mark_lookahead_pins_used_for_pin( + &pb_graph_node->clock_pins[0][0], cur_pb, + logical_block[ilogical_block].clock_net); + } + clock_port++; + } else if (prim_port->type == IN_PORT) { + for (j = 0; j < prim_port->num_pins; j++) { + if (logical_block[ilogical_block].input_nets[prim_port->model_port->index][j] + != OPEN) { + compute_and_mark_lookahead_pins_used_for_pin( + &pb_graph_node->input_pins[input_port][j], cur_pb, + logical_block[ilogical_block].input_nets[prim_port->model_port->index][j]); + } + } + input_port++; + } else if (prim_port->type == OUT_PORT) { + for (j = 0; j < prim_port->num_pins; j++) { + if (logical_block[ilogical_block].output_nets[prim_port->model_port->index][j] + != OPEN) { + compute_and_mark_lookahead_pins_used_for_pin( + &pb_graph_node->output_pins[output_port][j], cur_pb, + logical_block[ilogical_block].output_nets[prim_port->model_port->index][j]); + } + } + output_port++; + } else { + assert(0); + } + } +} + +/* Given a pin and its assigned net, mark all pin classes that are affected */ +static void compute_and_mark_lookahead_pins_used_for_pin( + t_pb_graph_pin *pb_graph_pin, t_pb *primitive_pb, int inet) { + int depth, i; + int pin_class, output_port; + t_pb * cur_pb; + t_pb * check_pb; + const t_pb_type *pb_type; + t_port *prim_port; + t_pb_graph_pin *output_pb_graph_pin; + int count; + + boolean skip, found; + + cur_pb = primitive_pb->parent_pb; + + while (cur_pb) { + depth = cur_pb->pb_graph_node->pb_type->depth; + pin_class = pb_graph_pin->parent_pin_class[depth]; + assert(pin_class != OPEN); + + if (pb_graph_pin->port->type == IN_PORT) { + /* find location of net driver if exist in clb, NULL otherwise */ + output_pb_graph_pin = NULL; + if (logical_block[vpack_net[inet].node_block[0]].clb_index + == logical_block[primitive_pb->logical_block].clb_index) { + pb_type = + logical_block[vpack_net[inet].node_block[0]].pb->pb_graph_node->pb_type; + output_port = 0; + found = FALSE; + for (i = 0; i < pb_type->num_ports && !found; i++) { + prim_port = &pb_type->ports[i]; + if (prim_port->type == OUT_PORT) { + if (pb_type->ports[i].model_port->index + == vpack_net[inet].node_block_port[0]) { + found = TRUE; + break; + } + output_port++; + } + } + assert(found); + output_pb_graph_pin = + &(logical_block[vpack_net[inet].node_block[0]].pb->pb_graph_node->output_pins[output_port][vpack_net[inet].node_block_pin[0]]); + } + + skip = FALSE; + + /* check if driving pin for input is contained within the currently investigated cluster, if yes, do nothing since no input needs to be used */ + if (output_pb_graph_pin != NULL) { + check_pb = logical_block[vpack_net[inet].node_block[0]].pb; + while (check_pb != NULL && check_pb != cur_pb) { + check_pb = check_pb->parent_pb; + } + if (check_pb != NULL) { + for (i = 0; + skip == FALSE + && i + < output_pb_graph_pin->num_connectable_primtive_input_pins[depth]; + i++) { + if (pb_graph_pin + == output_pb_graph_pin->list_of_connectable_input_pin_ptrs[depth][i]) { + skip = TRUE; + } + } + } + } + + /* Must use input pin */ + if (!skip) { + /* Check if already in pin class, if yes, skip */ + skip = FALSE; + for (i = 0; + i + < cur_pb->pb_graph_node->input_pin_class_size[pin_class] + * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC + AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST; + i++) { + if (cur_pb->pb_stats->lookahead_input_pins_used[pin_class][i] + == inet) { + skip = TRUE; + } + } + if (!skip) { + /* Net must take up a slot */ + for (i = 0; + i + < cur_pb->pb_graph_node->input_pin_class_size[pin_class] + * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC + AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST; + i++) { + if (cur_pb->pb_stats->lookahead_input_pins_used[pin_class][i] + == OPEN) { + cur_pb->pb_stats->lookahead_input_pins_used[pin_class][i] = + inet; + break; + } + } + } + } + } else { + assert(pb_graph_pin->port->type == OUT_PORT); + + skip = FALSE; + if (pb_graph_pin->num_connectable_primtive_input_pins[depth] + >= vpack_net[inet].num_sinks) { + /* Important: This runtime penalty looks a lot scarier than it really is. For high fan-out nets, I at most look at the number of pins within the cluster which limits runtime. + DO NOT REMOVE THIS INITIAL FILTER WITHOUT CAREFUL ANALYSIS ON RUNTIME!!! + + Key Observation: + For LUT-based designs it is impossible for the average fanout to exceed the number of LUT inputs so it's usually around 4-5 (pigeon-hole argument, if the average fanout is greater than the + number of LUT inputs, where do the extra connections go? Therefore, average fanout must be capped to a small constant where the constant is equal to the number of LUT inputs). The real danger to runtime + is when the number of sinks of a net gets doubled + + */ + for (i = 1; i <= vpack_net[inet].num_sinks; i++) { + if (logical_block[vpack_net[inet].node_block[i]].clb_index + != logical_block[vpack_net[inet].node_block[0]].clb_index) { + break; + } + } + if (i == vpack_net[inet].num_sinks + 1) { + count = 0; + /* TODO: I should cache the absorbed outputs, once net is absorbed, net is forever absorbed, no point in rechecking every time */ + for (i = 0; + i + < pb_graph_pin->num_connectable_primtive_input_pins[depth]; + i++) { + if (get_net_corresponding_to_pb_graph_pin(cur_pb, + pb_graph_pin->list_of_connectable_input_pin_ptrs[depth][i]) + == inet) { + count++; + } + } + if (count == vpack_net[inet].num_sinks) { + skip = TRUE; + } + } + } + + if (!skip) { + /* This output must exit this cluster */ + for (i = 0; + i + < cur_pb->pb_graph_node->output_pin_class_size[pin_class] + * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC + AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST; + i++) { + assert( + cur_pb->pb_stats->lookahead_output_pins_used[pin_class][i] != inet); + if (cur_pb->pb_stats->lookahead_output_pins_used[pin_class][i] + == OPEN) { + cur_pb->pb_stats->lookahead_output_pins_used[pin_class][i] = + inet; + break; + } + } + } + } + + cur_pb = cur_pb->parent_pb; + } +} + +/* Check if the number of available inputs/outputs for a pin class is sufficient for speculatively packed blocks */ +static boolean check_lookahead_pins_used(t_pb *cur_pb) { + int i, j; + int ipin; + const t_pb_type *pb_type = cur_pb->pb_graph_node->pb_type; + boolean success; + + success = TRUE; + + if (pb_type->num_modes > 0 && cur_pb->name != NULL) { + for (i = 0; i < cur_pb->pb_graph_node->num_input_pin_class && success; + i++) { + ipin = 0; + for (j = 0; + j + < cur_pb->pb_graph_node->input_pin_class_size[i] + * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC + AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST; + j++) { + if (cur_pb->pb_stats->lookahead_input_pins_used[i][j] != OPEN) { + ipin++; + } + } + if (ipin > cur_pb->pb_graph_node->input_pin_class_size[i]) { + success = FALSE; + } + } + + for (i = 0; i < cur_pb->pb_graph_node->num_output_pin_class && success; + i++) { + ipin = 0; + for (j = 0; + j + < cur_pb->pb_graph_node->output_pin_class_size[i] + * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC + AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST; + j++) { + if (cur_pb->pb_stats->lookahead_output_pins_used[i][j] != OPEN) { + ipin++; + } + } + if (ipin > cur_pb->pb_graph_node->output_pin_class_size[i]) { + success = FALSE; + } + } + + if (success && cur_pb->child_pbs != NULL) { + for (i = 0; + success + && i + < pb_type->modes[cur_pb->mode].num_pb_type_children; + i++) { + if (cur_pb->child_pbs[i] != NULL) { + for (j = 0; + success + && j + < pb_type->modes[cur_pb->mode].pb_type_children[i].num_pb; + j++) { + success = check_lookahead_pins_used( + &cur_pb->child_pbs[i][j]); + } + } + } + } + } + return success; +} + +/* Speculation successful, commit input/output pins used */ +static void commit_lookahead_pins_used(t_pb *cur_pb) { + int i, j; + int ipin; + const t_pb_type *pb_type = cur_pb->pb_graph_node->pb_type; + + if (pb_type->num_modes > 0 && cur_pb->name != NULL) { + for (i = 0; i < cur_pb->pb_graph_node->num_input_pin_class; i++) { + ipin = 0; + for (j = 0; + j + < cur_pb->pb_graph_node->input_pin_class_size[i] + * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC + AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST; + j++) { + if (cur_pb->pb_stats->lookahead_input_pins_used[i][j] != OPEN) { + cur_pb->pb_stats->input_pins_used[i][ipin] = + cur_pb->pb_stats->lookahead_input_pins_used[i][j]; + ipin++; + } + assert(ipin <= cur_pb->pb_graph_node->input_pin_class_size[i]); + } + } + + for (i = 0; i < cur_pb->pb_graph_node->num_output_pin_class; i++) { + ipin = 0; + for (j = 0; + j + < cur_pb->pb_graph_node->output_pin_class_size[i] + * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC + AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST; + j++) { + if (cur_pb->pb_stats->lookahead_output_pins_used[i][j] != OPEN) { + cur_pb->pb_stats->output_pins_used[i][ipin] = + cur_pb->pb_stats->lookahead_output_pins_used[i][j]; + ipin++; + } + assert(ipin <= cur_pb->pb_graph_node->output_pin_class_size[i]); + } + } + + if (cur_pb->child_pbs != NULL) { + for (i = 0; i < pb_type->modes[cur_pb->mode].num_pb_type_children; + i++) { + if (cur_pb->child_pbs[i] != NULL) { + for (j = 0; + j + < pb_type->modes[cur_pb->mode].pb_type_children[i].num_pb; + j++) { + commit_lookahead_pins_used(&cur_pb->child_pbs[i][j]); + } + } + } + } + } +} + +/* determine net at given pin location for cluster, return OPEN if none exists */ +static int get_net_corresponding_to_pb_graph_pin(t_pb *cur_pb, + t_pb_graph_pin *pb_graph_pin) { + t_pb_graph_node *pb_graph_node; + int i; + t_model_ports *model_port; + int ilogical_block; + + if (cur_pb->name == NULL) { + return OPEN; + } + if (cur_pb->pb_graph_node->pb_type->num_modes != 0) { + pb_graph_node = pb_graph_pin->parent_node; + while (pb_graph_node->parent_pb_graph_node->pb_type->depth + > cur_pb->pb_graph_node->pb_type->depth) { + pb_graph_node = pb_graph_node->parent_pb_graph_node; + } + if (pb_graph_node->parent_pb_graph_node == cur_pb->pb_graph_node) { + if (cur_pb->mode != pb_graph_node->pb_type->parent_mode->index) { + return OPEN; + } + for (i = 0; + i + < cur_pb->pb_graph_node->pb_type->modes[cur_pb->mode].num_pb_type_children; + i++) { + if (pb_graph_node + == &cur_pb->pb_graph_node->child_pb_graph_nodes[cur_pb->mode][i][pb_graph_node->placement_index]) { + break; + } + } + assert( + i < cur_pb->pb_graph_node->pb_type->modes[cur_pb->mode].num_pb_type_children); + return get_net_corresponding_to_pb_graph_pin( + &cur_pb->child_pbs[i][pb_graph_node->placement_index], + pb_graph_pin); + } else { + return OPEN; + } + } else { + ilogical_block = cur_pb->logical_block; + if (ilogical_block == OPEN) { + return OPEN; + } else { + model_port = pb_graph_pin->port->model_port; + if (model_port->is_clock) { + assert(model_port->dir == IN_PORT); + return logical_block[ilogical_block].clock_net; + } else if (model_port->dir == IN_PORT) { + return logical_block[ilogical_block].input_nets[model_port->index][pb_graph_pin->pin_number]; + } else { + assert(model_port->dir == OUT_PORT); + return logical_block[ilogical_block].output_nets[model_port->index][pb_graph_pin->pin_number]; + } + } + } +} + +static void print_block_criticalities(const char * fname) { + /* Prints criticality and critindexarray for each logical block to a file. */ + + int iblock, len; + FILE * fp; + char * name; + + fp = my_fopen(fname, "w", 0); + fprintf(fp, "Index \tLogical block name \tCriticality \tCritindexarray\n\n"); + for (iblock = 0; iblock < num_logical_blocks; iblock++) { + name = logical_block[iblock].name; + len = strlen(name); + fprintf(fp, "%d\t%s\t", logical_block[iblock].index, name); + if (len < 8) { + fprintf(fp, "\t\t"); + } else if (len < 16) { + fprintf(fp, "\t"); + } + fprintf(fp, "%f\t%d\n", block_criticality[iblock], critindexarray[iblock]); + } + fclose(fp); +} diff --git a/vpr7_rram/vpr/SRC/pack/cluster.h b/vpr7_rram/vpr/SRC/pack/cluster.h new file mode 100644 index 000000000..c717040f6 --- /dev/null +++ b/vpr7_rram/vpr/SRC/pack/cluster.h @@ -0,0 +1,10 @@ +void do_clustering(const t_arch *arch, t_pack_molecule *molecule_head, + int num_models, boolean global_clocks, boolean *is_clock, + boolean hill_climbing_flag, char *out_fname, boolean timing_driven, + enum e_cluster_seed cluster_seed_type, float alpha, float beta, + int recompute_timing_after, float block_delay, + float intra_cluster_net_delay, float inter_cluster_net_delay, + float aspect, boolean allow_unrelated_clustering, + boolean allow_early_exit, boolean connection_driven, + enum e_packer_algorithm packer_algorithm, t_timing_inf timing_inf); +int get_cluster_of_block(int blkidx); diff --git a/vpr7_rram/vpr/SRC/pack/cluster_feasibility_filter.c b/vpr7_rram/vpr/SRC/pack/cluster_feasibility_filter.c new file mode 100644 index 000000000..3510df5ca --- /dev/null +++ b/vpr7_rram/vpr/SRC/pack/cluster_feasibility_filter.c @@ -0,0 +1,590 @@ +/* + Feasibility filter used during packing that determines if various necessary conditions for legality are met + + Important for 2 reasons: + 1) Quickly reject cases that are bad so that we don't waste time exploring useless cases in packing + 2) Robustness issue. During packing, we have a limited size queue to store candidates to try to pack. A good filter helps keep that queue filled with candidates likely to pass. + + 1st major filter: Pin counting based on pin classes + Rationale: If the number of a particular gruop of pins supplied by the pb_graph_node in the architecture is insufficient to meet a candidate packing solution's demand for that group of pins, then that + candidate solution is for sure invalid without any further legalization checks. For example, if a candidate solution requires 2 clock pins but the architecture only has one clock, then that solution + can't be legal. + + Implementation details: + a) Definition of a pin class - If there exists a path (ignoring directionality of connections) from pin A to pin B and pin A and pin B are of the same type (input, output, or clock), then pin A and pin B are in the same pin class. Otherwise, pin A and pin B are in different pin classes. + b) Code Identifies pin classes. Given a candidate solution + + TODO: May 30, 2012 Jason Luu - Must take into consideration modes when doing pin counting. For fracturable LUTs FI = 5, the soft logic block sees 6 pins instead of 5 pins for the dual LUT mode messing up the pin counter. The packer still produces correct results but runs slower than its best (experiment on a modified architecture file that forces correct pin counting shows 40x speedup vs VPR 6.0 as opposed to 3x speedup at the time) + + Author: Jason Luu + Date: May 16, 2012 + + + */ +#include + +#include "read_xml_arch_file.h" +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "hash.h" +#include "cluster_feasibility_filter.h" +#include "vpr_utils.h" +#include "ReadOptions.h" + +/* header functions that identify pin classes */ +static void alloc_pin_classes_in_pb_graph_node( + INOUTP t_pb_graph_node *pb_graph_node); +static int get_max_depth_of_pb_graph_node(INP t_pb_graph_node *pb_graph_node); +static void load_pin_class_by_depth(INOUTP t_pb_graph_node *pb_graph_node, + INP int depth, OUTP int *input_count, OUTP int *output_count); +static void load_list_of_connectable_input_pin_ptrs( + INOUTP t_pb_graph_node *pb_graph_node); +static void expand_pb_graph_node_and_load_output_to_input_connections( + INOUTP t_pb_graph_pin *current_pb_graph_pin, + INOUTP t_pb_graph_pin *reference_pin, INP int depth); +static void unmark_fanout_intermediate_nodes( + INOUTP t_pb_graph_pin *current_pb_graph_pin); +static void reset_pin_class_scratch_pad_rec( + INOUTP t_pb_graph_node *pb_graph_node); +static void expand_pb_graph_node_and_load_pin_class_by_depth( + INOUTP t_pb_graph_pin *current_pb_graph_pin, + INP t_pb_graph_pin *reference_pb_graph_pin, INP int depth, + OUTP int *input_count, OUTP int *output_count); +static void sum_pin_class(INOUTP t_pb_graph_node *pb_graph_node); + +static void discover_all_forced_connections(INOUTP t_pb_graph_node *pb_graph_node); +static boolean is_forced_connection(INP t_pb_graph_pin *pb_graph_pin); + + +/* Identify all pin class information for complex block + */ +void load_pin_classes_in_pb_graph_head(INOUTP t_pb_graph_node *pb_graph_node) { + int i, depth, input_count, output_count; + + /* Allocate memory for primitives */ + alloc_pin_classes_in_pb_graph_node(pb_graph_node); + + /* Load pin classes */ + depth = get_max_depth_of_pb_graph_node(pb_graph_node); + for (i = 0; i < depth; i++) { + input_count = output_count = 0; + reset_pin_class_scratch_pad_rec(pb_graph_node); + load_pin_class_by_depth(pb_graph_node, i, &input_count, &output_count); + } + + /* Load internal output-to-input connections within each cluster */ + reset_pin_class_scratch_pad_rec(pb_graph_node); + load_list_of_connectable_input_pin_ptrs(pb_graph_node); + discover_all_forced_connections(pb_graph_node); +} + +/** + * Recursive function to allocate memory space for pin classes in primitives + */ +static void alloc_pin_classes_in_pb_graph_node( + INOUTP t_pb_graph_node *pb_graph_node) { + int i, j, k; + + /* If primitive, allocate space, else go to primitive */ + if (pb_graph_node->pb_type->num_modes == 0) { + /* allocate space */ + for (i = 0; i < pb_graph_node->num_input_ports; i++) { + for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { + pb_graph_node->input_pins[i][j].parent_pin_class = + (int *) my_calloc(pb_graph_node->pb_type->depth, + sizeof(int*)); + for (k = 0; k < pb_graph_node->pb_type->depth; k++) { + pb_graph_node->input_pins[i][j].parent_pin_class[k] = OPEN; + } + } + } + for (i = 0; i < pb_graph_node->num_output_ports; i++) { + for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { + pb_graph_node->output_pins[i][j].parent_pin_class = + (int *) my_calloc(pb_graph_node->pb_type->depth, + sizeof(int*)); + pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs = + (t_pb_graph_pin ***) my_calloc( + pb_graph_node->pb_type->depth, + sizeof(t_pb_graph_pin**)); + pb_graph_node->output_pins[i][j].num_connectable_primtive_input_pins = + (int*) my_calloc(pb_graph_node->pb_type->depth, + sizeof(int)); + for (k = 0; k < pb_graph_node->pb_type->depth; k++) { + pb_graph_node->output_pins[i][j].parent_pin_class[k] = OPEN; + } + } + } + for (i = 0; i < pb_graph_node->num_clock_ports; i++) { + for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { + pb_graph_node->clock_pins[i][j].parent_pin_class = + (int *) my_calloc(pb_graph_node->pb_type->depth, + sizeof(int*)); + for (k = 0; k < pb_graph_node->pb_type->depth; k++) { + pb_graph_node->clock_pins[i][j].parent_pin_class[k] = OPEN; + } + } + } + } else { + for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { + for (j = 0; + j < pb_graph_node->pb_type->modes[i].num_pb_type_children; + j++) { + for (k = 0; + k + < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; + k++) { + alloc_pin_classes_in_pb_graph_node( + &pb_graph_node->child_pb_graph_nodes[i][j][k]); + } + } + } + } +} + +/* determine maximum depth of pb_graph_node */ +static int get_max_depth_of_pb_graph_node(INP t_pb_graph_node *pb_graph_node) { + int i, j, k; + int max_depth, depth; + + max_depth = 0; + + /* If primitive, allocate space, else go to primitive */ + if (pb_graph_node->pb_type->num_modes == 0) { + return pb_graph_node->pb_type->depth; + } else { + for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { + for (j = 0; + j < pb_graph_node->pb_type->modes[i].num_pb_type_children; + j++) { + for (k = 0; + k + < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; + k++) { + depth = get_max_depth_of_pb_graph_node( + &pb_graph_node->child_pb_graph_nodes[i][j][k]); + if (depth > max_depth) { + max_depth = depth; + } + } + } + } + } + + return max_depth; +} + +static void reset_pin_class_scratch_pad_rec( + INOUTP t_pb_graph_node *pb_graph_node) { + int i, j, k; + + for (i = 0; i < pb_graph_node->num_input_ports; i++) { + for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { + pb_graph_node->input_pins[i][j].scratch_pad = OPEN; + } + } + for (i = 0; i < pb_graph_node->num_output_ports; i++) { + for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { + pb_graph_node->output_pins[i][j].scratch_pad = OPEN; + } + } + for (i = 0; i < pb_graph_node->num_clock_ports; i++) { + for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { + pb_graph_node->clock_pins[i][j].scratch_pad = OPEN; + } + } + + for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { + for (j = 0; j < pb_graph_node->pb_type->modes[i].num_pb_type_children; + j++) { + for (k = 0; + k + < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; + k++) { + reset_pin_class_scratch_pad_rec( + &pb_graph_node->child_pb_graph_nodes[i][j][k]); + } + } + } +} + +/* load pin class based on limited depth */ +static void load_pin_class_by_depth(INOUTP t_pb_graph_node *pb_graph_node, + INP int depth, OUTP int *input_count, OUTP int *output_count) { + int i, j, k; + + if (pb_graph_node->pb_type->num_modes == 0) { + if (pb_graph_node->pb_type->depth > depth) { + /* At primitive, determine which pin class each of its pins belong to */ + for (i = 0; i < pb_graph_node->num_input_ports; i++) { + for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { + if (pb_graph_node->input_pins[i][j].parent_pin_class[depth] + == OPEN) { + expand_pb_graph_node_and_load_pin_class_by_depth( + &pb_graph_node->input_pins[i][j], + &pb_graph_node->input_pins[i][j], depth, + input_count, output_count); + (*input_count)++; + } + } + } + for (i = 0; i < pb_graph_node->num_output_ports; i++) { + for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { + if (pb_graph_node->output_pins[i][j].parent_pin_class[depth] + == OPEN) { + expand_pb_graph_node_and_load_pin_class_by_depth( + &pb_graph_node->output_pins[i][j], + &pb_graph_node->output_pins[i][j], depth, + input_count, output_count); + (*output_count)++; + } + } + } + for (i = 0; i < pb_graph_node->num_clock_ports; i++) { + for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { + if (pb_graph_node->clock_pins[i][j].parent_pin_class[depth] + == OPEN) { + expand_pb_graph_node_and_load_pin_class_by_depth( + &pb_graph_node->clock_pins[i][j], + &pb_graph_node->clock_pins[i][j], depth, + input_count, output_count); + (*input_count)++; + } + } + } + } + } + + if (pb_graph_node->pb_type->depth == depth) { + /* Load pin classes for all pb_graph_nodes of this depth, therefore, at a particular pb_graph_node of this depth, set # of pin classes to be 0 */ + *input_count = 0; + *output_count = 0; + for (i = 0; i < pb_graph_node->num_input_ports; i++) { + for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { + pb_graph_node->input_pins[i][j].pin_class = OPEN; + } + } + for (i = 0; i < pb_graph_node->num_output_ports; i++) { + for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { + pb_graph_node->output_pins[i][j].pin_class = OPEN; + } + } + for (i = 0; i < pb_graph_node->num_clock_ports; i++) { + for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { + pb_graph_node->clock_pins[i][j].pin_class = OPEN; + } + } + } + + /* Expand down to primitives */ + for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { + for (j = 0; j < pb_graph_node->pb_type->modes[i].num_pb_type_children; + j++) { + for (k = 0; + k + < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; + k++) { + load_pin_class_by_depth( + &pb_graph_node->child_pb_graph_nodes[i][j][k], depth, + input_count, output_count); + } + } + } + + if (pb_graph_node->pb_type->depth == depth + && pb_graph_node->pb_type->num_modes != 0) { + /* Record pin class information for cluster */ + pb_graph_node->num_input_pin_class = *input_count + 1; /* number of input pin classes discovered + 1 for primitive inputs not reachable from cluster input pins */ + pb_graph_node->input_pin_class_size = (int*) my_calloc(*input_count + 1, + sizeof(int)); + pb_graph_node->num_output_pin_class = *output_count + 1; /* number of output pin classes discovered + 1 for primitive inputs not reachable from cluster input pins */ + pb_graph_node->output_pin_class_size = (int*) my_calloc(*output_count + 1, + sizeof(int)); + sum_pin_class(pb_graph_node); + } + +} + +/** + * Load internal output-to-input connections within each cluster + */ +static void load_list_of_connectable_input_pin_ptrs( + INOUTP t_pb_graph_node *pb_graph_node) { + int i, j, k; + + if (pb_graph_node->pb_type->num_modes == 0) { + /* If this is a primitive, discover what input pins the output pins can connect to */ + for (i = 0; i < pb_graph_node->num_output_ports; i++) { + for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { + for (k = 0; k < pb_graph_node->pb_type->depth; k++) { + expand_pb_graph_node_and_load_output_to_input_connections( + &pb_graph_node->output_pins[i][j], + &pb_graph_node->output_pins[i][j], k); + unmark_fanout_intermediate_nodes( + &pb_graph_node->output_pins[i][j]); + } + } + } + } + /* Expand down to primitives */ + for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { + for (j = 0; j < pb_graph_node->pb_type->modes[i].num_pb_type_children; + j++) { + for (k = 0;k < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; + k++) { + load_list_of_connectable_input_pin_ptrs( + &pb_graph_node->child_pb_graph_nodes[i][j][k]); + } + } + } +} + +/* Traverse outputs of output pin or primitive to see what input pins it reaches + Record list of input pins based on depth + */ +static void expand_pb_graph_node_and_load_output_to_input_connections( + INOUTP t_pb_graph_pin *current_pb_graph_pin, + INOUTP t_pb_graph_pin *reference_pin, INP int depth) { + int i; + + if (current_pb_graph_pin->scratch_pad == OPEN + && current_pb_graph_pin->parent_node->pb_type->depth > depth) { + current_pb_graph_pin->scratch_pad = 1; + for (i = 0; i < current_pb_graph_pin->num_output_edges; i++) { + assert(current_pb_graph_pin->output_edges[i]->num_output_pins == 1); + expand_pb_graph_node_and_load_output_to_input_connections( + current_pb_graph_pin->output_edges[i]->output_pins[0], + reference_pin, depth); + } + if (current_pb_graph_pin->parent_node->pb_type->num_modes == 0 + && current_pb_graph_pin->port->type == IN_PORT) { + reference_pin->num_connectable_primtive_input_pins[depth]++; + reference_pin->list_of_connectable_input_pin_ptrs[depth] = + (t_pb_graph_pin**) my_realloc( + reference_pin->list_of_connectable_input_pin_ptrs[depth], + reference_pin->num_connectable_primtive_input_pins[depth] + * sizeof(t_pb_graph_pin*)); + reference_pin->list_of_connectable_input_pin_ptrs[depth][reference_pin->num_connectable_primtive_input_pins[depth] + - 1] = current_pb_graph_pin; + } + } +} + +/** + * Clear scratch_pad for all fanout of pin + */ +static void unmark_fanout_intermediate_nodes( + INOUTP t_pb_graph_pin *current_pb_graph_pin) { + int i; + if (current_pb_graph_pin->scratch_pad != OPEN) { + current_pb_graph_pin->scratch_pad = OPEN; + for (i = 0; i < current_pb_graph_pin->num_output_edges; i++) { + assert(current_pb_graph_pin->output_edges[i]->num_output_pins == 1); + unmark_fanout_intermediate_nodes( + current_pb_graph_pin->output_edges[i]->output_pins[0]); + } + } +} + +/** + * Determine other primitive pins that belong to the same pin class as reference pin + */ +static void expand_pb_graph_node_and_load_pin_class_by_depth( + INOUTP t_pb_graph_pin *current_pb_graph_pin, + INP t_pb_graph_pin *reference_pb_graph_pin, INP int depth, + OUTP int *input_count, OUTP int *output_count) { + int i; + int marker; + int active_pin_class; + + if (reference_pb_graph_pin->port->type == IN_PORT) { + marker = *input_count + 10; + active_pin_class = *input_count; + } else { + marker = -10 - *output_count; + active_pin_class = *output_count; + } + assert(reference_pb_graph_pin->parent_node->pb_type->num_modes == 0); + assert(current_pb_graph_pin->parent_node->pb_type->depth >= depth); + assert(current_pb_graph_pin->port->type != INOUT_PORT); + if (current_pb_graph_pin->scratch_pad != marker) { + if (current_pb_graph_pin->parent_node->pb_type->num_modes == 0) { + current_pb_graph_pin->scratch_pad = marker; + /* This is a primitive, determine what pins cans share the same pin class as the reference pin */ + if (current_pb_graph_pin->parent_pin_class[depth] == OPEN + && reference_pb_graph_pin->port->is_clock + == current_pb_graph_pin->port->is_clock + && reference_pb_graph_pin->port->type + == current_pb_graph_pin->port->type) { + current_pb_graph_pin->parent_pin_class[depth] = + active_pin_class; + } + for (i = 0; i < current_pb_graph_pin->num_input_edges; i++) { + assert( + current_pb_graph_pin->input_edges[i]->num_input_pins == 1); + expand_pb_graph_node_and_load_pin_class_by_depth( + current_pb_graph_pin->input_edges[i]->input_pins[0], + reference_pb_graph_pin, depth, input_count, + output_count); + } + for (i = 0; i < current_pb_graph_pin->num_output_edges; i++) { + assert( + current_pb_graph_pin->output_edges[i]->num_output_pins == 1); + expand_pb_graph_node_and_load_pin_class_by_depth( + current_pb_graph_pin->output_edges[i]->output_pins[0], + reference_pb_graph_pin, depth, input_count, + output_count); + } + } else if (current_pb_graph_pin->parent_node->pb_type->depth == depth) { + current_pb_graph_pin->scratch_pad = marker; + if (current_pb_graph_pin->port->type == OUT_PORT) { + if (reference_pb_graph_pin->port->type == OUT_PORT) { + /* This cluster's output pin can be driven by primitive outputs belonging to this pin class */ + current_pb_graph_pin->pin_class = active_pin_class; + } + for (i = 0; i < current_pb_graph_pin->num_input_edges; i++) { + assert( + current_pb_graph_pin->input_edges[i]->num_input_pins == 1); + expand_pb_graph_node_and_load_pin_class_by_depth( + current_pb_graph_pin->input_edges[i]->input_pins[0], + reference_pb_graph_pin, depth, input_count, + output_count); + } + } + if (current_pb_graph_pin->port->type == IN_PORT) { + if (reference_pb_graph_pin->port->type == IN_PORT) { + /* This cluster's input pin can drive the primitive input pins belonging to this pin class */ + current_pb_graph_pin->pin_class = active_pin_class; + } + for (i = 0; i < current_pb_graph_pin->num_output_edges; i++) { + assert( + current_pb_graph_pin->output_edges[i]->num_output_pins == 1); + expand_pb_graph_node_and_load_pin_class_by_depth( + current_pb_graph_pin->output_edges[i]->output_pins[0], + reference_pb_graph_pin, depth, input_count, + output_count); + } + } + } else if (current_pb_graph_pin->parent_node->pb_type->depth > depth) { + /* Inside an intermediate cluster, traverse to either a primitive or to the cluster we're interested in populating */ + current_pb_graph_pin->scratch_pad = marker; + for (i = 0; i < current_pb_graph_pin->num_input_edges; i++) { + assert( + current_pb_graph_pin->input_edges[i]->num_input_pins == 1); + expand_pb_graph_node_and_load_pin_class_by_depth( + current_pb_graph_pin->input_edges[i]->input_pins[0], + reference_pb_graph_pin, depth, input_count, + output_count); + } + for (i = 0; i < current_pb_graph_pin->num_output_edges; i++) { + assert( + current_pb_graph_pin->output_edges[i]->num_output_pins == 1); + expand_pb_graph_node_and_load_pin_class_by_depth( + current_pb_graph_pin->output_edges[i]->output_pins[0], + reference_pb_graph_pin, depth, input_count, + output_count); + } + } + } +} + +/* count up pin classes of the same number for the given cluster */ +static void sum_pin_class(INOUTP t_pb_graph_node *pb_graph_node) { + int i, j; + + /* This is a primitive, for each pin in primitive, sum appropriate pin class */ + for (i = 0; i < pb_graph_node->num_input_ports; i++) { + for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { + assert( + pb_graph_node->input_pins[i][j].pin_class < pb_graph_node->num_input_pin_class); + if (pb_graph_node->input_pins[i][j].pin_class == OPEN) { + vpr_printf(TIO_MESSAGE_WARNING, "%s[%d].%s[%d] unconnected pin in architecture.\n", + pb_graph_node->pb_type->name, + pb_graph_node->placement_index, + pb_graph_node->input_pins[i][j].port->name, + pb_graph_node->input_pins[i][j].pin_number); + continue; + } + pb_graph_node->input_pin_class_size[pb_graph_node->input_pins[i][j].pin_class]++; + } + } + for (i = 0; i < pb_graph_node->num_output_ports; i++) { + for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { + assert( + pb_graph_node->output_pins[i][j].pin_class < pb_graph_node->num_output_pin_class); + if (pb_graph_node->output_pins[i][j].pin_class == OPEN) { + vpr_printf(TIO_MESSAGE_WARNING, "%s[%d].%s[%d] unconnected pin in architecture.\n", + pb_graph_node->pb_type->name, + pb_graph_node->placement_index, + pb_graph_node->output_pins[i][j].port->name, + pb_graph_node->output_pins[i][j].pin_number); + continue; + } + pb_graph_node->output_pin_class_size[pb_graph_node->output_pins[i][j].pin_class]++; + } + } + for (i = 0; i < pb_graph_node->num_clock_ports; i++) { + for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { + assert( + pb_graph_node->clock_pins[i][j].pin_class < pb_graph_node->num_input_pin_class); + if (pb_graph_node->clock_pins[i][j].pin_class == OPEN) { + vpr_printf(TIO_MESSAGE_WARNING, "%s[%d].%s[%d] unconnected pin in architecture.\n", + pb_graph_node->pb_type->name, + pb_graph_node->placement_index, + pb_graph_node->clock_pins[i][j].port->name, + pb_graph_node->clock_pins[i][j].pin_number); + continue; + } + pb_graph_node->input_pin_class_size[pb_graph_node->clock_pins[i][j].pin_class]++; + } + } +} + +/* Recursively visit all pb_graph_pins and determine primitive output pins that connect to nothing else than one primitive input pin. If a net maps to this output pin, then the primitive corresponding to that input must be used */ +static void discover_all_forced_connections(INOUTP t_pb_graph_node *pb_graph_node) { + int i, j, k; + + /* If primitive, allocate space, else go to primitive */ + if (pb_graph_node->pb_type->num_modes == 0) { + for(i = 0; i < pb_graph_node->num_output_ports; i++) { + for(j = 0; j < pb_graph_node->num_output_pins[i]; j++) { + pb_graph_node->output_pins[i][j].is_forced_connection = is_forced_connection(&pb_graph_node->output_pins[i][j]); + } + } + } else { + for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { + for (j = 0; + j < pb_graph_node->pb_type->modes[i].num_pb_type_children; + j++) { + for (k = 0; + k < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; + k++) { + discover_all_forced_connections(&pb_graph_node->child_pb_graph_nodes[i][j][k]); + } + } + } + } +} + +/** + * Given an output pin, determine if it connects to only one input pin and nothing else. + */ +static boolean is_forced_connection(INP t_pb_graph_pin *pb_graph_pin) { + if(pb_graph_pin->num_output_edges > 1) { + return FALSE; + } + if(pb_graph_pin->num_output_edges == 0) { + if(pb_graph_pin->parent_node->pb_type->num_modes == 0) { + /* Check that this pin belongs to a primitive */ + return TRUE; + } else { + return FALSE; + } + } + return is_forced_connection(pb_graph_pin->output_edges[0]->output_pins[0]); +} + + + + diff --git a/vpr7_rram/vpr/SRC/pack/cluster_feasibility_filter.h b/vpr7_rram/vpr/SRC/pack/cluster_feasibility_filter.h new file mode 100644 index 000000000..095df09e0 --- /dev/null +++ b/vpr7_rram/vpr/SRC/pack/cluster_feasibility_filter.h @@ -0,0 +1,29 @@ +/* + Feasibility filter used during packing that determines if various necessary conditions for legality are met + + Important for 2 reasons: + 1) Quickly reject cases that are bad so that we don't waste time exploring useless cases in packing + 2) Robustness issue. During packing, we have a limited size queue to store candidates to try to pack. A good filter helps keep that queue filled with candidates likely to pass. + + 1st major filter: Pin counting based on pin classes + Rationale: If the number of a particular gruop of pins supplied by the pb_graph_node in the architecture is insufficient to meet a candidate packing solution's demand for that group of pins, then that + candidate solution is for sure invalid without any further legalization checks. For example, if a candidate solution requires 2 clock pins but the architecture only has one clock, then that solution + can't be legal. + + Implementation details: + a) Definition of a pin class - If there exists a path (ignoring directionality of connections) from pin A to pin B and pin A and pin B are of the same type (input, output, or clock), then pin A and pin B are in the same pin class. Otherwise, pin A and pin B are in different pin classes. + b) Code Identifies pin classes. Given a candidate solution + + Author: Jason Luu + Date: May 16, 2012 + + */ + +#ifndef CLUSTER_FEASIBILITY_CHECK_H +#define CLUSTER_FEASIBILITY_CHECK_H +#include "arch_types.h" +#include "util.h" + +void load_pin_classes_in_pb_graph_head(INOUTP t_pb_graph_node *pb_graph_node); + +#endif diff --git a/vpr7_rram/vpr/SRC/pack/cluster_legality.c b/vpr7_rram/vpr/SRC/pack/cluster_legality.c new file mode 100755 index 000000000..b68822a82 --- /dev/null +++ b/vpr7_rram/vpr/SRC/pack/cluster_legality.c @@ -0,0 +1,1299 @@ +#include +#include +#include +#include + +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "route_export.h" +#include "route_common.h" +#include "cluster_legality.h" +#include "cluster_placement.h" +#include "rr_graph.h" + +static t_chunk rr_mem_ch = {NULL, 0, NULL}; + +/*static struct s_linked_vptr *rr_mem_chunk_list_head = NULL; +static int chunk_bytes_avail = 0; +static char *chunk_next_avail_mem = NULL;*/ +static struct s_trace **best_routing; + +/* nets_in_cluster: array of all nets contained in the cluster */ +static int *nets_in_cluster; /* [0..num_nets_in_cluster-1] */ +static int num_nets_in_cluster; +static int saved_num_nets_in_cluster; +static int curr_cluster_index; + +static int ext_input_rr_node_index, ext_output_rr_node_index, + ext_clock_rr_node_index, max_ext_index; +static int **saved_net_rr_terminals; +static float pres_fac; + +/********************* Subroutines local to this module *********************/ +static boolean is_net_in_cluster(INP int inet); + +static void add_net_rr_terminal_cluster(int iblk_net, + t_pb_graph_node * primitive, int ilogical_block, + t_model_ports * model_port, int ipin); + +static boolean breadth_first_route_net_cluster(int inet); + +static void breadth_first_expand_trace_segment_cluster( + struct s_trace *start_ptr, int remaining_connections_to_sink); + +static void breadth_first_expand_neighbours_cluster(int inode, float pcost, + int inet, boolean first_time); + +static void breadth_first_add_source_to_heap_cluster(int inet); + +static void alloc_net_rr_terminals_cluster(void); + +static void mark_ends_cluster(int inet); + +static float rr_node_intrinsic_cost(int inode); + +/************************ Subroutine definitions ****************************/ + +static boolean is_net_in_cluster(INP int inet) { + int i; + for (i = 0; i < num_nets_in_cluster; i++) { + if (nets_in_cluster[i] == inet) { + return TRUE; + } + } + return FALSE; +} + +/* load rr_node for source and sinks of net if exists, return FALSE otherwise */ +/* Todo: Note this is an inefficient way to determine port, better to use a lookup, worry about this if runtime becomes an issue */ +static void add_net_rr_terminal_cluster(int iblk_net, + t_pb_graph_node * primitive, int ilogical_block, + t_model_ports * model_port, int ipin) { + /* Ensure at most one external input/clock source and one external output sink for net */ + int i, net_pin; + t_port *prim_port; + const t_pb_type *pb_type; + boolean found; + + int input_port; + int output_port; + int clock_port; + + input_port = output_port = clock_port = 0; + + pb_type = primitive->pb_type; + prim_port = NULL; + + assert(pb_type->num_modes == 0); + + found = FALSE; + /* TODO: This is inelegant design, I should change the primitive ports in pb_type to be input, output, or clock instead of this lookup */ + for (i = 0; i < pb_type->num_ports && !found; i++) { + prim_port = &pb_type->ports[i]; + if (pb_type->ports[i].model_port == model_port) { + found = TRUE; + } else { + if (prim_port->is_clock) { + clock_port++; + assert(prim_port->type == IN_PORT); + } else if (prim_port->type == IN_PORT) { + input_port++; + } else if (prim_port->type == OUT_PORT) { + output_port++; + } else { + assert(0); + } + } + } + assert(found); + assert(ipin < prim_port->num_pins); + net_pin = OPEN; + if (prim_port->is_clock) { + for (i = 1; i <= vpack_net[iblk_net].num_sinks; i++) { + if (vpack_net[iblk_net].node_block[i] == ilogical_block + && vpack_net[iblk_net].node_block_port[i] + == model_port->index + && vpack_net[iblk_net].node_block_pin[i] == ipin) { + net_pin = i; + break; + } + } + assert(net_pin != OPEN); + assert(rr_node[primitive->clock_pins[clock_port][ipin].pin_count_in_cluster].num_edges == 1); + net_rr_terminals[iblk_net][net_pin] = rr_node[primitive->clock_pins[clock_port][ipin].pin_count_in_cluster].edges[0]; + } else if (prim_port->type == IN_PORT) { + for (i = 1; i <= vpack_net[iblk_net].num_sinks; i++) { + if (vpack_net[iblk_net].node_block[i] == ilogical_block + && vpack_net[iblk_net].node_block_port[i] + == model_port->index + && vpack_net[iblk_net].node_block_pin[i] == ipin) { + net_pin = i; + break; + } + } + assert(net_pin != OPEN); + assert(rr_node[primitive->input_pins[input_port][ipin].pin_count_in_cluster].num_edges == 1); + net_rr_terminals[iblk_net][net_pin] = rr_node[primitive->input_pins[input_port][ipin].pin_count_in_cluster].edges[0]; + } else if (prim_port->type == OUT_PORT) { + i = 0; + if (vpack_net[iblk_net].node_block[i] == ilogical_block + && vpack_net[iblk_net].node_block_port[i] == model_port->index + && vpack_net[iblk_net].node_block_pin[i] == ipin) { + net_pin = i; + } + assert(net_pin != OPEN); + net_rr_terminals[iblk_net][net_pin] = + primitive->output_pins[output_port][ipin].pin_count_in_cluster; + } else { + assert(0); + } +} + +void reload_ext_net_rr_terminal_cluster(void) { + int i, j, net_index; + boolean has_ext_sink, has_ext_source; + int curr_ext_output, curr_ext_input, curr_ext_clock; + + curr_ext_input = ext_input_rr_node_index; + curr_ext_output = ext_output_rr_node_index; + curr_ext_clock = ext_clock_rr_node_index; + + for (i = 0; i < num_nets_in_cluster; i++) { + net_index = nets_in_cluster[i]; + has_ext_sink = FALSE; + has_ext_source = (boolean) + (logical_block[vpack_net[net_index].node_block[0]].clb_index + != curr_cluster_index); + if (has_ext_source) { + /* Instantiate a source of this net */ + if (vpack_net[net_index].is_global) { + net_rr_terminals[net_index][0] = curr_ext_clock; + curr_ext_clock++; + } else { + net_rr_terminals[net_index][0] = curr_ext_input; + curr_ext_input++; + } + } + for (j = 1; j <= vpack_net[net_index].num_sinks; j++) { + if (logical_block[vpack_net[net_index].node_block[j]].clb_index + != curr_cluster_index) { + if (has_ext_sink || has_ext_source) { + /* Only need one node driving external routing, either this cluster drives external routing or another cluster does it */ + net_rr_terminals[net_index][j] = OPEN; + } else { + /* External sink, only need to route once, externally routing will take care of the rest */ + net_rr_terminals[net_index][j] = curr_ext_output; + curr_ext_output++; + has_ext_sink = TRUE; + } + } + } + + if (curr_ext_input > ext_output_rr_node_index + || curr_ext_output > ext_clock_rr_node_index + || curr_ext_clock > max_ext_index) { + /* failed, not enough pins of proper type, overran index */ + assert(0); + } + } +} + +void alloc_and_load_cluster_legality_checker(void) { + best_routing = (struct s_trace **) my_calloc(num_logical_nets, + sizeof(struct s_trace *)); + nets_in_cluster = (int *) my_malloc(num_logical_nets * sizeof(int)); + num_nets_in_cluster = 0; + num_nets = num_logical_nets; + + /* inside a cluster, I do not consider rr_indexed_data cost, set to 1 since other costs are multiplied by it */ + num_rr_indexed_data = 1; + rr_indexed_data = (t_rr_indexed_data *) my_calloc(1, sizeof(t_rr_indexed_data)); + rr_indexed_data[0].base_cost = 1; + + /* alloc routing structures */ + alloc_route_static_structs(); + alloc_net_rr_terminals_cluster(); +} + +void free_cluster_legality_checker(void) { + int inet; + free(best_routing); + free(rr_indexed_data); + free_rr_node_route_structs(); + free_route_structs(); + free_trace_structs(); + + free_chunk_memory(&rr_mem_ch); + + for (inet = 0; inet < num_logical_nets; inet++) { + free(saved_net_rr_terminals[inet]); + } + free(net_rr_terminals); + free(nets_in_cluster); + free(saved_net_rr_terminals); +} + +void alloc_and_load_rr_graph_for_pb_graph_node( + INP t_pb_graph_node *pb_graph_node, INP const t_arch* arch, int mode) { + + int i, j, k, index; + boolean is_primitive; + + is_primitive = (boolean) (pb_graph_node->pb_type->num_modes == 0); + + for (i = 0; i < pb_graph_node->num_input_ports; i++) { + for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { + index = pb_graph_node->input_pins[i][j].pin_count_in_cluster; + rr_node[index].pb_graph_pin = &pb_graph_node->input_pins[i][j]; + rr_node[index].fan_in = + pb_graph_node->input_pins[i][j].num_input_edges; + rr_node[index].num_edges = + pb_graph_node->input_pins[i][j].num_output_edges; + rr_node[index].pack_intrinsic_cost = 1 + + (float) rr_node[index].num_edges / 5 + ((float)j/(float)pb_graph_node->num_input_pins[i])/(float)10; /* need to normalize better than 5 and 10, bias router to use earlier inputs pins */ + rr_node[index].edges = (int *) my_malloc( + rr_node[index].num_edges * sizeof(int)); + rr_node[index].switches = (short *) my_calloc(rr_node[index].num_edges, + sizeof(short)); + rr_node[index].net_num = OPEN; + rr_node[index].prev_node = OPEN; + rr_node[index].prev_edge = OPEN; + if (mode == 0) { /* default mode is the first mode */ + rr_node[index].capacity = 1; + } else { + rr_node[index].capacity = 0; + } + for (k = 0; k < pb_graph_node->input_pins[i][j].num_output_edges; + k++) { + /* TODO: Intention was to do bus-based implementation here */ + rr_node[index].edges[k] = + pb_graph_node->input_pins[i][j].output_edges[k]->output_pins[0]->pin_count_in_cluster; + rr_node[index].switches[k] = arch->num_switches - 1; /* last switch in arch switch properties is a delayless switch */ + assert( + pb_graph_node->input_pins[i][j].output_edges[k]->num_output_pins == 1); + } + rr_node[index].type = INTRA_CLUSTER_EDGE; + if (is_primitive) { + /* This is a terminating pin, add SINK node */ + assert(rr_node[index].num_edges == 0); + rr_node[index].num_edges = 1; + rr_node[index].edges = (int *) my_calloc(rr_node[index].num_edges, sizeof(int)); + rr_node[index].switches = (short *) my_calloc(rr_node[index].num_edges, sizeof(short)); + rr_node[index].edges[0] = num_rr_nodes; + + /* Create SINK node */ + rr_node[num_rr_nodes].pb_graph_pin = NULL; + rr_node[num_rr_nodes].fan_in = 1; + rr_node[num_rr_nodes].num_edges = 0; + rr_node[num_rr_nodes].pack_intrinsic_cost = 1; + rr_node[num_rr_nodes].edges = NULL; + rr_node[num_rr_nodes].switches = NULL; + rr_node[num_rr_nodes].net_num = OPEN; + rr_node[num_rr_nodes].prev_node = OPEN; + rr_node[num_rr_nodes].prev_edge = OPEN; + rr_node[num_rr_nodes].capacity = 1; + rr_node[num_rr_nodes].type = SINK; + num_rr_nodes++; + + if(pb_graph_node->pb_type->class_type == LUT_CLASS) { + /* LUTs are special, they have logical equivalence at inputs, logical equivalence is represented by a single high capacity sink instead of multiple single capacity sinks */ + rr_node[num_rr_nodes - 1].capacity = pb_graph_node->num_input_pins[i]; + if(j != 0) { + num_rr_nodes--; + rr_node[index].edges[0] = num_rr_nodes - 1; + } + } + } + } + } + + for (i = 0; i < pb_graph_node->num_output_ports; i++) { + for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { + index = pb_graph_node->output_pins[i][j].pin_count_in_cluster; + rr_node[index].pb_graph_pin = &pb_graph_node->output_pins[i][j]; + rr_node[index].fan_in = + pb_graph_node->output_pins[i][j].num_input_edges; + rr_node[index].num_edges = + pb_graph_node->output_pins[i][j].num_output_edges; + rr_node[index].pack_intrinsic_cost = 1 + + (float) rr_node[index].num_edges / 5; /* need to normalize better than 5 */ + rr_node[index].edges = (int *) my_malloc( + rr_node[index].num_edges * sizeof(int)); + rr_node[index].switches = (short *) my_calloc(rr_node[index].num_edges, + sizeof(short)); + rr_node[index].net_num = OPEN; + rr_node[index].prev_node = OPEN; + rr_node[index].prev_edge = OPEN; + if (mode == 0) { /* Default mode is the first mode */ + rr_node[index].capacity = 1; + } else { + rr_node[index].capacity = 0; + } + for (k = 0; k < pb_graph_node->output_pins[i][j].num_output_edges; + k++) { + /* TODO: Intention was to do bus-based implementation here */ + rr_node[index].edges[k] = + pb_graph_node->output_pins[i][j].output_edges[k]->output_pins[0]->pin_count_in_cluster; + rr_node[index].switches[k] = arch->num_switches - 1; + assert( + pb_graph_node->output_pins[i][j].output_edges[k]->num_output_pins == 1); + } + rr_node[index].type = INTRA_CLUSTER_EDGE; + if (is_primitive) { + rr_node[index].type = SOURCE; + } + } + } + + for (i = 0; i < pb_graph_node->num_clock_ports; i++) { + for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { + index = pb_graph_node->clock_pins[i][j].pin_count_in_cluster; + rr_node[index].pb_graph_pin = &pb_graph_node->clock_pins[i][j]; + rr_node[index].fan_in = + pb_graph_node->clock_pins[i][j].num_input_edges; + rr_node[index].num_edges = + pb_graph_node->clock_pins[i][j].num_output_edges; + rr_node[index].pack_intrinsic_cost = 1 + + (float) rr_node[index].num_edges / 5; /* need to normalize better than 5 */ + rr_node[index].edges = (int *) my_malloc( + rr_node[index].num_edges * sizeof(int)); + rr_node[index].switches = (short *) my_calloc(rr_node[index].num_edges, + sizeof(short)); + rr_node[index].net_num = OPEN; + rr_node[index].prev_node = OPEN; + rr_node[index].prev_edge = OPEN; + if (mode == 0) { /* default mode is the first mode (useful for routing */ + rr_node[index].capacity = 1; + } else { + rr_node[index].capacity = 0; + } + for (k = 0; k < pb_graph_node->clock_pins[i][j].num_output_edges; + k++) { + /* TODO: Intention was to do bus-based implementation here */ + rr_node[index].edges[k] = + pb_graph_node->clock_pins[i][j].output_edges[k]->output_pins[0]->pin_count_in_cluster; + rr_node[index].switches[k] = arch->num_switches - 1; + assert( + pb_graph_node->clock_pins[i][j].output_edges[k]->num_output_pins == 1); + } + rr_node[index].type = INTRA_CLUSTER_EDGE; + if (is_primitive) { + /* This is a terminating pin, add SINK node */ + assert(rr_node[index].num_edges == 0); + rr_node[index].num_edges = 1; + rr_node[index].edges = (int *) my_calloc(rr_node[index].num_edges, sizeof(int)); + rr_node[index].switches = (short *) my_calloc(rr_node[index].num_edges, sizeof(short)); + rr_node[index].edges[0] = num_rr_nodes; + + /* Create SINK node */ + rr_node[num_rr_nodes].pb_graph_pin = NULL; + rr_node[num_rr_nodes].fan_in = 1; + rr_node[num_rr_nodes].num_edges = 0; + rr_node[num_rr_nodes].pack_intrinsic_cost = 1; + rr_node[num_rr_nodes].edges = NULL; + rr_node[num_rr_nodes].switches = NULL; + rr_node[num_rr_nodes].net_num = OPEN; + rr_node[num_rr_nodes].prev_node = OPEN; + rr_node[num_rr_nodes].prev_edge = OPEN; + rr_node[num_rr_nodes].capacity = 1; + rr_node[num_rr_nodes].type = SINK; + num_rr_nodes++; + } + } + } + + for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { + for (j = 0; j < pb_graph_node->pb_type->modes[i].num_pb_type_children; + j++) { + for (k = 0; + k + < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; + k++) { + alloc_and_load_rr_graph_for_pb_graph_node( + &pb_graph_node->child_pb_graph_nodes[i][j][k], arch, i); + } + } + } + +} + +void alloc_and_load_legalizer_for_cluster(INP t_block* clb, INP int clb_index, + INP const t_arch *arch) { + + /** + * Structure: Model external routing and internal routing + * + * 1. Model external routing + * num input pins == num external sources for input pins, fully connect them to input pins (simulates external routing) + * num output pins == num external sinks for output pins, fully connect them to output pins (simulates external routing) + * num clock pins == num external sources for clock pins, fully connect them to clock pins (simulates external routing) + * 2. Model internal routing + * + */ + /* make each rr_node one correspond with pin and correspond with pin's index pin_count_in_cluster */ + int i, j, k, m, index, pb_graph_rr_index; + int count_pins; + t_pb_type * pb_type; + t_pb_graph_node *pb_graph_node; + int ipin; + + /* Create rr_graph */ + pb_type = clb->type->pb_type; + pb_graph_node = clb->type->pb_graph_head; + num_rr_nodes = pb_graph_node->total_pb_pins + pb_type->num_input_pins + + pb_type->num_output_pins + pb_type->num_clock_pins; + + /* allocate memory for rr_node resources + additional memory for any additional sources/sinks, 2x is an overallocation but guarantees that there will be enough sources/sinks available */ + rr_node = (t_rr_node *) my_calloc(num_rr_nodes * 2, sizeof(t_rr_node)); + clb->pb->rr_graph = rr_node; + + alloc_and_load_rr_graph_for_pb_graph_node(pb_graph_node, arch, 0); + + curr_cluster_index = clb_index; + + /* Alloc and load rr_graph external sources and sinks */ + ext_input_rr_node_index = pb_graph_node->total_pb_pins; + ext_output_rr_node_index = pb_type->num_input_pins + + pb_graph_node->total_pb_pins; + ext_clock_rr_node_index = pb_type->num_input_pins + pb_type->num_output_pins + + pb_graph_node->total_pb_pins; + max_ext_index = pb_type->num_input_pins + pb_type->num_output_pins + + pb_type->num_clock_pins + pb_graph_node->total_pb_pins; + + for (i = 0; i < pb_type->num_input_pins; i++) { + index = i + pb_graph_node->total_pb_pins; + rr_node[index].type = SOURCE; + rr_node[index].fan_in = 0; + rr_node[index].num_edges = pb_type->num_input_pins; + rr_node[index].pack_intrinsic_cost = 1 + + (float) rr_node[index].num_edges / 5; /* need to normalize better than 5 */ + rr_node[index].edges = (int *) my_malloc( + rr_node[index].num_edges * sizeof(int)); + rr_node[index].switches = (short *) my_calloc(rr_node[index].num_edges, + sizeof(int)); + rr_node[index].capacity = 1; + } + + for (i = 0; i < pb_type->num_output_pins; i++) { + index = i + pb_type->num_input_pins + pb_graph_node->total_pb_pins; + rr_node[index].type = SINK; + rr_node[index].fan_in = pb_type->num_output_pins; + rr_node[index].num_edges = 0; + rr_node[index].pack_intrinsic_cost = 1 + + (float) rr_node[index].num_edges / 5; /* need to normalize better than 5 */ + rr_node[index].capacity = 1; + } + + for (i = 0; i < pb_type->num_clock_pins; i++) { + index = i + pb_type->num_input_pins + pb_type->num_output_pins + + pb_graph_node->total_pb_pins; + rr_node[index].type = SOURCE; + rr_node[index].fan_in = 0; + rr_node[index].num_edges = pb_type->num_clock_pins; + rr_node[index].pack_intrinsic_cost = 1 + + (float) rr_node[index].num_edges / 5; /* need to normalize better than 5 */ + rr_node[index].edges = (int *) my_malloc( + rr_node[index].num_edges * sizeof(int)); + rr_node[index].switches = (short *) my_calloc(rr_node[index].num_edges, + sizeof(int)); + rr_node[index].capacity = 1; + } + + ipin = 0; + for (i = 0; i < pb_graph_node->num_input_ports; i++) { + for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { + pb_graph_rr_index = + pb_graph_node->input_pins[i][j].pin_count_in_cluster; + for (k = 0; k < pb_type->num_input_pins; k++) { + index = k + pb_graph_node->total_pb_pins; + rr_node[index].edges[ipin] = pb_graph_rr_index; + rr_node[index].switches[ipin] = arch->num_switches - 1; + } + rr_node[pb_graph_rr_index].pack_intrinsic_cost = MAX_SHORT; /* using an input pin should be made costly */ + ipin++; + } + } + + /* Must attach output pins to input pins because if a connection cannot fit using intra-cluster routing, it can also use external routing */ + for (i = 0; i < pb_graph_node->num_output_ports; i++) { + for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { + count_pins = pb_graph_node->output_pins[i][j].num_output_edges + + pb_type->num_output_pins + pb_type->num_input_pins; + pb_graph_rr_index = + pb_graph_node->output_pins[i][j].pin_count_in_cluster; + rr_node[pb_graph_rr_index].edges = (int *) my_realloc( + rr_node[pb_graph_rr_index].edges, + (count_pins) * sizeof(int)); + rr_node[pb_graph_rr_index].switches = (short *) my_realloc( + rr_node[pb_graph_rr_index].switches, + (count_pins) * sizeof(int)); + + ipin = 0; + for (k = 0; k < pb_graph_node->num_input_ports; k++) { + for (m = 0; m < pb_graph_node->num_input_pins[k]; m++) { + index = + pb_graph_node->input_pins[k][m].pin_count_in_cluster; + rr_node[pb_graph_rr_index].edges[ipin + + pb_graph_node->output_pins[i][j].num_output_edges] = + index; + rr_node[pb_graph_rr_index].switches[ipin + + pb_graph_node->output_pins[i][j].num_output_edges] = + arch->num_switches - 1; + ipin++; + } + } + for (k = 0; k < pb_type->num_output_pins; k++) { + index = k + pb_type->num_input_pins + + pb_graph_node->total_pb_pins; + rr_node[pb_graph_rr_index].edges[k + pb_type->num_input_pins + + pb_graph_node->output_pins[i][j].num_output_edges] = + index; + rr_node[pb_graph_rr_index].switches[k + pb_type->num_input_pins + + pb_graph_node->output_pins[i][j].num_output_edges] = + arch->num_switches - 1; + } + rr_node[pb_graph_rr_index].num_edges += pb_type->num_output_pins + + pb_type->num_input_pins; + rr_node[pb_graph_rr_index].pack_intrinsic_cost = 1 + + (float) rr_node[pb_graph_rr_index].num_edges / 5; /* need to normalize better than 5 */ + } + } + + ipin = 0; + for (i = 0; i < pb_graph_node->num_clock_ports; i++) { + for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { + for (k = 0; k < pb_type->num_clock_pins; k++) { + index = k + pb_type->num_input_pins + pb_type->num_output_pins + + pb_graph_node->total_pb_pins; + pb_graph_rr_index = + pb_graph_node->clock_pins[i][j].pin_count_in_cluster; + rr_node[index].edges[ipin] = pb_graph_rr_index; + rr_node[index].switches[ipin] = arch->num_switches - 1; + } + ipin++; + } + } + + alloc_and_load_rr_node_route_structs(); + num_nets_in_cluster = 0; + +} + +void free_legalizer_for_cluster(INP t_block* clb, boolean free_local_rr_graph) { + int i; + + free_rr_node_route_structs(); + if(free_local_rr_graph == TRUE) { + for (i = 0; i < num_rr_nodes; i++) { + if (clb->pb->rr_graph[i].edges != NULL) { + free(clb->pb->rr_graph[i].edges); + } + if (clb->pb->rr_graph[i].switches != NULL) { + free(clb->pb->rr_graph[i].switches); + } + } + free(clb->pb->rr_graph); + } +} + +void reset_legalizer_for_cluster(t_block *clb) { + int i; + for (i = 0; i < num_nets_in_cluster; i++) { + free_traceback(nets_in_cluster[i]); + trace_head[nets_in_cluster[i]] = best_routing[nets_in_cluster[i]]; + free_traceback(nets_in_cluster[i]); + best_routing[nets_in_cluster[i]] = NULL; + } + + free_rr_node_route_structs(); + num_nets_in_cluster = 0; + saved_num_nets_in_cluster = 0; +} + +/** + * + * internal_nets: index of nets to route [0..num_internal_nets - 1] + */ +boolean try_breadth_first_route_cluster(void) { + + /* Iterated maze router ala Pathfinder Negotiated Congestion algorithm, * + * (FPGA 95 p. 111). Returns TRUE if it can route this FPGA, FALSE if * + * it can't. */ + + /* For different modes, when a mode is turned on, I set the max occupancy of all rr_nodes in the mode to 1 and all others to 0 */ + /* TODO: There is a bug for route-throughs where edges in route-throughs do not get turned off because the rr_edge is in a particular mode but the two rr_nodes are outside */ + + boolean success, is_routable; + int itry, inet, net_index; + struct s_router_opts router_opts; + + /* Xifan TANG: Count runtime for routing in packing stage */ + clock_t begin, end; + + begin = clock(); + + /* Usually the first iteration uses a very small (or 0) pres_fac to find * + * the shortest path and get a congestion map. For fast compiles, I set * + * pres_fac high even for the first iteration. */ + + /* sets up a fast breadth-first router */ + router_opts.first_iter_pres_fac = 10; + router_opts.max_router_iterations = 20; + router_opts.initial_pres_fac = 10; + router_opts.pres_fac_mult = 2; + router_opts.acc_fac = 1; + + reset_rr_node_route_structs(); /* Clear all prior rr_graph history */ + + pres_fac = router_opts.first_iter_pres_fac; + + for (itry = 1; itry <= router_opts.max_router_iterations; itry++) { + for (inet = 0; inet < num_nets_in_cluster; inet++) { + net_index = nets_in_cluster[inet]; + + pathfinder_update_one_cost(trace_head[net_index], -1, pres_fac); + + is_routable = breadth_first_route_net_cluster(net_index); + + /* Impossible to route? (disconnected rr_graph) */ + + if (!is_routable) { + /* TODO: Inelegant, can be more intelligent */ + vpr_printf(TIO_MESSAGE_INFO, "Failed routing net %s\n", vpack_net[net_index].name); + vpr_printf(TIO_MESSAGE_INFO, "Routing failed. Disconnected rr_graph.\n"); + return FALSE; + } + + pathfinder_update_one_cost(trace_head[net_index], 1, pres_fac); + + } + + success = feasible_routing(); + if (success) { + /* End of packing routing */ + end = clock(); + /* accumulate the runtime for pack routing */ +#ifdef CLOCKS_PER_SEC + pack_route_time += (float)(end - begin)/ CLOCKS_PER_SEC; +#else + pack_route_time += (float)(end - begin)/ CLK_PER_SEC; +#endif + /* vpr_printf(TIO_MESSAGE_INFO, "Updated: Packing routing took %g seconds\n", pack_route_time); */ + return (TRUE); + } + + if (itry == 1) + pres_fac = router_opts.initial_pres_fac; + else + pres_fac *= router_opts.pres_fac_mult; + + pres_fac = std::min(pres_fac, static_cast(HUGE_POSITIVE_FLOAT / 1e5)); + + pathfinder_update_cost(pres_fac, router_opts.acc_fac); + } + /* End of packing routing */ + end = clock(); + /* accumulate the runtime for pack routing */ +#ifdef CLOCKS_PER_SEC + pack_route_time += (float)(end - begin)/ CLOCKS_PER_SEC; +#else + pack_route_time += (float)(end - begin)/ CLK_PER_SEC; +#endif + /* vpr_printf(TIO_MESSAGE_INFO, "Updated: Packing routing took %g seconds\n", pack_route_time); */ + + return (FALSE); +} + +static boolean breadth_first_route_net_cluster(int inet) { + + /* Uses a maze routing (Dijkstra's) algorithm to route a net. The net * + * begins at the net output, and expands outward until it hits a target * + * pin. The algorithm is then restarted with the entire first wire segment * + * included as part of the source this time. For an n-pin net, the maze * + * router is invoked n-1 times to complete all the connections. Inet is * + * the index of the net to be routed. * + * If this routine finds that a net *cannot* be connected (due to a complete * + * lack of potential paths, rather than congestion), it returns FALSE, as * + * routing is impossible on this architecture. Otherwise it returns TRUE. */ + + int i, inode, prev_node, remaining_connections_to_sink; + float pcost, new_pcost; + struct s_heap *current; + struct s_trace *tptr; + boolean first_time; + + free_traceback(inet); + breadth_first_add_source_to_heap_cluster(inet); + mark_ends_cluster(inet); + + tptr = NULL; + remaining_connections_to_sink = 0; + + for (i = 1; i <= vpack_net[inet].num_sinks; i++) { /* Need n-1 wires to connect n pins */ + + /* Do not connect open terminals */ + if (net_rr_terminals[inet][i] == OPEN) + continue; + /* Expand and begin routing */ + breadth_first_expand_trace_segment_cluster(tptr, + remaining_connections_to_sink); + current = get_heap_head(); + + if (current == NULL) { /* Infeasible routing. No possible path for net. */ + reset_path_costs(); /* Clean up before leaving. */ + return (FALSE); + } + + inode = current->index; + + while (rr_node_route_inf[inode].target_flag == 0) { + pcost = rr_node_route_inf[inode].path_cost; + new_pcost = current->cost; + if (pcost > new_pcost) { /* New path is lowest cost. */ + rr_node_route_inf[inode].path_cost = new_pcost; + prev_node = current->u.prev_node; + rr_node_route_inf[inode].prev_node = prev_node; + rr_node_route_inf[inode].prev_edge = current->prev_edge; + first_time = FALSE; + + if (pcost > 0.99 * HUGE_POSITIVE_FLOAT) /* First time touched. */{ + add_to_mod_list(&rr_node_route_inf[inode].path_cost); + first_time = TRUE; + } + + breadth_first_expand_neighbours_cluster(inode, new_pcost, inet, + first_time); + } + + free_heap_data(current); + current = get_heap_head(); + + if (current == NULL) { /* Impossible routing. No path for net. */ + reset_path_costs(); + return (FALSE); + } + + inode = current->index; + } + + rr_node_route_inf[inode].target_flag--; /* Connected to this SINK. */ + remaining_connections_to_sink = rr_node_route_inf[inode].target_flag; + tptr = update_traceback(current, inet); + free_heap_data(current); + } + + empty_heap(); + reset_path_costs(); + return (TRUE); +} + +static void breadth_first_expand_trace_segment_cluster( + struct s_trace *start_ptr, int remaining_connections_to_sink) { + + /* Adds all the rr_nodes in the traceback segment starting at tptr (and * + * continuing to the end of the traceback) to the heap with a cost of zero. * + * This allows expansion to begin from the existing wiring. The * + * remaining_connections_to_sink value is 0 if the route segment ending * + * at this location is the last one to connect to the SINK ending the route * + * segment. This is the usual case. If it is not the last connection this * + * net must make to this SINK, I have a hack to ensure the next connection * + * to this SINK goes through a different IPIN. Without this hack, the * + * router would always put all the connections from this net to this SINK * + * through the same IPIN. With LUTs or cluster-based logic blocks, you * + * should never have a net connecting to two logically-equivalent pins on * + * the same logic block, so the hack will never execute. If your logic * + * block is an and-gate, however, nets might connect to two and-inputs on * + * the same logic block, and since the and-inputs are logically-equivalent, * + * this means two connections to the same SINK. */ + + struct s_trace *tptr, *next_ptr; + int inode, sink_node, last_ipin_node; + + tptr = start_ptr; + + if (remaining_connections_to_sink == 0) { /* Usual case. */ + while (tptr != NULL) { + node_to_heap(tptr->index, 0., NO_PREVIOUS, NO_PREVIOUS, OPEN, OPEN); + tptr = tptr->next; + } + } + + else { /* This case never executes for most logic blocks. */ + + /* Weird case. Lots of hacks. The cleanest way to do this would be to empty * + * the heap, update the congestion due to the partially-completed route, put * + * the whole route so far (excluding IPINs and SINKs) on the heap with cost * + * 0., and expand till you hit the next SINK. That would be slow, so I * + * do some hacks to enable incremental wavefront expansion instead. */ + + if (tptr == NULL) + return; /* No route yet */ + + next_ptr = tptr->next; + last_ipin_node = OPEN; /* Stops compiler from complaining. */ + + /* Can't put last SINK on heap with NO_PREVIOUS, etc, since that won't let * + * us reach it again. Instead, leave the last traceback element (SINK) off * + * the heap. */ + + while (next_ptr != NULL) { + inode = tptr->index; + node_to_heap(inode, 0., NO_PREVIOUS, NO_PREVIOUS, OPEN, OPEN); + + if (rr_node[inode].type == INTRA_CLUSTER_EDGE) + { + if(rr_node[inode].pb_graph_pin != NULL && rr_node[inode].pb_graph_pin->num_output_edges == 0) + { + last_ipin_node = inode; + } + } + + tptr = next_ptr; + next_ptr = tptr->next; + } + + /* This will stop the IPIN node used to get to this SINK from being * + * reexpanded for the remainder of this net's routing. This will make us * + * hook up more IPINs to this SINK (which is what we want). If IPIN * + * doglegs are allowed in the graph, we won't be able to use this IPIN to * + * do a dogleg, since it won't be re-expanded. Shouldn't be a big problem. */ + assert(last_ipin_node != OPEN); + rr_node_route_inf[last_ipin_node].path_cost = -HUGE_POSITIVE_FLOAT; + + /* Also need to mark the SINK as having high cost, so another connection can * + * be made to it. */ + + sink_node = tptr->index; + rr_node_route_inf[sink_node].path_cost = HUGE_POSITIVE_FLOAT; + + /* Finally, I need to remove any pending connections to this SINK via the * + * IPIN I just used (since they would result in congestion). Scan through * + * the heap to do this. */ + + invalidate_heap_entries(sink_node, last_ipin_node); + } +} + +static void breadth_first_expand_neighbours_cluster(int inode, float pcost, + int inet, boolean first_time) { + + /* Puts all the rr_nodes adjacent to inode on the heap. rr_nodes outside * + * the expanded bounding box specified in route_bb are not added to the * + * heap. pcost is the path_cost to get to inode. */ + + int iconn, to_node, num_edges; + float tot_cost; + + num_edges = rr_node[inode].num_edges; + for (iconn = 0; iconn < num_edges; iconn++) { + to_node = rr_node[inode].edges[iconn]; + /*if (first_time) { */ + tot_cost = pcost + + get_rr_cong_cost(to_node) * rr_node_intrinsic_cost(to_node); + /* + } else { + tot_cost = pcost + get_rr_cong_cost(to_node); + }*/ + node_to_heap(to_node, tot_cost, inode, iconn, OPEN, OPEN); + } +} + +static void breadth_first_add_source_to_heap_cluster(int inet) { + + /* Adds the SOURCE of this net to the heap. Used to start a net's routing. */ + + int inode; + float cost; + + inode = net_rr_terminals[inet][0]; /* SOURCE */ + cost = get_rr_cong_cost(inode); + + node_to_heap(inode, cost, NO_PREVIOUS, NO_PREVIOUS, OPEN, OPEN); +} + +static void mark_ends_cluster(int inet) { + + /* Mark all the SINKs of this net as targets by setting their target flags * + * to the number of times the net must connect to each SINK. Note that * + * this number can occassionally be greater than 1 -- think of connecting * + * the same net to two inputs of an and-gate (and-gate inputs are logically * + * equivalent, so both will connect to the same SINK). */ + + int ipin, inode; + + for (ipin = 1; ipin <= vpack_net[inet].num_sinks; ipin++) { + inode = net_rr_terminals[inet][ipin]; + if (inode == OPEN) + continue; + rr_node_route_inf[inode].target_flag++; + assert(rr_node_route_inf[inode].target_flag > 0 && rr_node_route_inf[inode].target_flag <= rr_node[inode].capacity); + } +} + +static void alloc_net_rr_terminals_cluster(void) { + int inet; + + net_rr_terminals = (int **) my_malloc(num_logical_nets * sizeof(int *)); + saved_net_rr_terminals = (int **) my_malloc( + num_logical_nets * sizeof(int *)); + saved_num_nets_in_cluster = 0; + + for (inet = 0; inet < num_logical_nets; inet++) { + net_rr_terminals[inet] = (int *) my_chunk_malloc( + (vpack_net[inet].num_sinks + 1) * sizeof(int), + &rr_mem_ch); + + saved_net_rr_terminals[inet] = (int *) my_malloc( + (vpack_net[inet].num_sinks + 1) * sizeof(int)); + } +} + +void setup_intracluster_routing_for_molecule(INP t_pack_molecule *molecule, + INP t_pb_graph_node **primitive_list) { + + /* Allocates and loads the net_rr_terminals data structure. For each net * + * it stores the rr_node index of the SOURCE of the net and all the SINKs * + * of the net. [0..num_logical_nets-1][0..num_pins-1]. */ + int i; + + for (i = 0; i < get_array_size_of_molecule(molecule); i++) { + if (molecule->logical_block_ptrs[i] != NULL) { + setup_intracluster_routing_for_logical_block( + molecule->logical_block_ptrs[i]->index, primitive_list[i]); + } + } + + reload_ext_net_rr_terminal_cluster(); +} + +void setup_intracluster_routing_for_logical_block(INP int iblock, + INP t_pb_graph_node *primitive) { + + /* Allocates and loads the net_rr_terminals data structure. For each net * + * it stores the rr_node index of the SOURCE of the net and all the SINKs * + * of the net. [0..num_logical_nets-1][0..num_pins-1]. */ + int ipin, iblk_net; + t_model_ports *port; + + assert(primitive->pb_type->num_modes == 0); + /* check if primitive */ + assert(logical_block[iblock].clb_index != NO_CLUSTER); + /* check if primitive and block is open */ + + /* check if block type matches primitive type */ + if (logical_block[iblock].model != primitive->pb_type->model) { + /* End early, model is incompatible */ + assert(0); + } + + /* for each net of logical block, check if it is in cluster, if not add it */ + /* also check if pins on primitive can fit logical block */ + + port = logical_block[iblock].model->inputs; + + while (port) { + for (ipin = 0; ipin < port->size; ipin++) { + if (port->is_clock) { + assert(port->size == 1); + iblk_net = logical_block[iblock].clock_net; + } else { + iblk_net = logical_block[iblock].input_nets[port->index][ipin]; + } + if (iblk_net == OPEN) { + continue; + } + if (!is_net_in_cluster(iblk_net)) { + nets_in_cluster[num_nets_in_cluster] = iblk_net; + num_nets_in_cluster++; + } + add_net_rr_terminal_cluster(iblk_net, primitive, iblock, port, + ipin); + } + port = port->next; + } + + port = logical_block[iblock].model->outputs; + while (port) { + for (ipin = 0; ipin < port->size; ipin++) { + iblk_net = logical_block[iblock].output_nets[port->index][ipin]; + if (iblk_net == OPEN) { + continue; + } + if (!is_net_in_cluster(iblk_net)) { + nets_in_cluster[num_nets_in_cluster] = iblk_net; + num_nets_in_cluster++; + } + add_net_rr_terminal_cluster(iblk_net, primitive, iblock, port, + ipin); + } + port = port->next; + } +} + +void save_and_reset_routing_cluster(void) { + + /* This routing frees any routing currently held in best routing, * + * then copies over the current routing (held in trace_head), and * + * finally sets trace_head and trace_tail to all NULLs so that the * + * connection to the saved routing is broken. This is necessary so * + * that the next iteration of the router does not free the saved * + * routing elements. Also, the routing path costs and net_rr_terminals is stripped from the + * existing rr_graph so that the saved routing does not affect the graph */ + + int inet, i, j; + struct s_trace *tempptr; + saved_num_nets_in_cluster = num_nets_in_cluster; + + for (i = 0; i < num_nets_in_cluster; i++) { + inet = nets_in_cluster[i]; + for (j = 0; j <= vpack_net[inet].num_sinks; j++) { + saved_net_rr_terminals[inet][j] = net_rr_terminals[inet][j]; + } + + /* Free any previously saved routing. It is no longer best. */ + /* Also Save a pointer to the current routing in best_routing. */ + + pathfinder_update_one_cost(trace_head[inet], -1, pres_fac); + tempptr = trace_head[inet]; + trace_head[inet] = best_routing[inet]; + free_traceback(inet); + best_routing[inet] = tempptr; + + /* Set the current (working) routing to NULL so the current trace * + * elements won't be reused by the memory allocator. */ + + trace_head[inet] = NULL; + trace_tail[inet] = NULL; + } +} + +void restore_routing_cluster(void) { + + /* Deallocates any current routing in trace_head, and replaces it with * + * the routing in best_routing. Best_routing is set to NULL to show that * + * it no longer points to a valid routing. NOTE: trace_tail is not * + * restored -- it is set to all NULLs since it is only used in * + * update_traceback. If you need trace_tail restored, modify this * + * routine. Also restores the locally used opin data. */ + + int inet, i, j; + + for (i = 0; i < num_nets_in_cluster; i++) { + inet = nets_in_cluster[i]; + + pathfinder_update_one_cost(trace_head[inet], -1, pres_fac); + + /* Free any current routing. */ + free_traceback(inet); + + /* Set the current routing to the saved one. */ + trace_head[inet] = best_routing[inet]; + best_routing[inet] = NULL; /* No stored routing. */ + + /* restore net terminals */ + for (j = 0; j <= vpack_net[inet].num_sinks; j++) { + net_rr_terminals[inet][j] = saved_net_rr_terminals[inet][j]; + } + + /* restore old routing */ + pathfinder_update_one_cost(trace_head[inet], 1, pres_fac); + } + num_nets_in_cluster = saved_num_nets_in_cluster; +} + +void save_cluster_solution(void) { + + /* This routine updates the occupancy and pres_cost of the rr_nodes that are * + * affected by the portion of the routing of one net that starts at * + * route_segment_start. If route_segment_start is trace_head[inet], the * + * cost of all the nodes in the routing of net inet are updated. If * + * add_or_sub is -1 the net (or net portion) is ripped up, if it is 1 the * + * net is added to the routing. The size of pres_fac determines how severly * + * oversubscribed rr_nodes are penalized. */ + + int i, j, net_index; + struct s_trace *tptr, *prev; + int inode; + for (i = 0; i < max_ext_index; i++) { + rr_node[i].net_num = OPEN; + rr_node[i].prev_edge = OPEN; + rr_node[i].prev_node = OPEN; + } + for (i = 0; i < num_nets_in_cluster; i++) { + prev = NULL; + net_index = nets_in_cluster[i]; + tptr = trace_head[net_index]; + if (tptr == NULL) /* No routing yet. */ + return; + + for (;;) { + inode = tptr->index; + rr_node[inode].net_num = net_index; + if (prev != NULL) { + rr_node[inode].prev_node = prev->index; + for (j = 0; j < rr_node[prev->index].num_edges; j++) { + if (rr_node[prev->index].edges[j] == inode) { + rr_node[inode].prev_edge = j; + break; + } + } + assert(j != rr_node[prev->index].num_edges); + } else { + rr_node[inode].prev_node = OPEN; + rr_node[inode].prev_edge = OPEN; + } + + if (rr_node[inode].type == SINK) { + tptr = tptr->next; /* Skip next segment. */ + if (tptr == NULL) + break; + } + + prev = tptr; + tptr = tptr->next; + + } /* End while loop -- did an entire traceback. */ + } +} + +boolean is_pin_open(int i) { + return (boolean) (rr_node[i].occ == 0); +} + +static float rr_node_intrinsic_cost(int inode) { + /* This is a tie breaker to avoid using nodes with more edges whenever possible */ + float value; + value = rr_node[inode].pack_intrinsic_cost; + return value; +} + +/* turns on mode for a pb by setting capacity of its rr_nodes to 1 */ +void set_pb_graph_mode(t_pb_graph_node *pb_graph_node, int mode, int isOn) { + int i, j, index; + int i_pb_type, i_pb_inst; + const t_pb_type *pb_type; + + pb_type = pb_graph_node->pb_type; + for (i_pb_type = 0; i_pb_type < pb_type->modes[mode].num_pb_type_children; + i_pb_type++) { + for (i_pb_inst = 0; + i_pb_inst + < pb_type->modes[mode].pb_type_children[i_pb_type].num_pb; + i_pb_inst++) { + for (i = 0; + i + < pb_graph_node->child_pb_graph_nodes[mode][i_pb_type][i_pb_inst].num_input_ports; + i++) { + for (j = 0; + j + < pb_graph_node->child_pb_graph_nodes[mode][i_pb_type][i_pb_inst].num_input_pins[i]; + j++) { + index = + pb_graph_node->child_pb_graph_nodes[mode][i_pb_type][i_pb_inst].input_pins[i][j].pin_count_in_cluster; + rr_node[index].capacity = isOn; + } + } + + for (i = 0; + i + < pb_graph_node->child_pb_graph_nodes[mode][i_pb_type][i_pb_inst].num_output_ports; + i++) { + for (j = 0; + j + < pb_graph_node->child_pb_graph_nodes[mode][i_pb_type][i_pb_inst].num_output_pins[i]; + j++) { + index = + pb_graph_node->child_pb_graph_nodes[mode][i_pb_type][i_pb_inst].output_pins[i][j].pin_count_in_cluster; + rr_node[index].capacity = isOn; + } + } + + for (i = 0; + i + < pb_graph_node->child_pb_graph_nodes[mode][i_pb_type][i_pb_inst].num_clock_ports; + i++) { + for (j = 0; + j + < pb_graph_node->child_pb_graph_nodes[mode][i_pb_type][i_pb_inst].num_clock_pins[i]; + j++) { + index = + pb_graph_node->child_pb_graph_nodes[mode][i_pb_type][i_pb_inst].clock_pins[i][j].pin_count_in_cluster; + rr_node[index].capacity = isOn; + } + } + } + } +} + +/* If this is done post place and route, use the cb pins determined by place-and-route rather than letting the legalizer freely determine */ +void force_post_place_route_cb_input_pins(int iblock) { + int i, j, k, ipin, net_index, ext_net; + int pin_offset; + boolean has_ext_source, success; + int curr_ext_output, curr_ext_input, curr_ext_clock; + t_pb_graph_node *pb_graph_node; + + pb_graph_node = block[iblock].pb->pb_graph_node; + pin_offset = block[iblock].z * (pb_graph_node->pb_type->num_input_pins + pb_graph_node->pb_type->num_output_pins + pb_graph_node->pb_type->num_clock_pins); + + curr_ext_input = ext_input_rr_node_index; + curr_ext_output = ext_output_rr_node_index; + curr_ext_clock = ext_clock_rr_node_index; + + for (i = 0; i < num_nets_in_cluster; i++) { + net_index = nets_in_cluster[i]; + has_ext_source = (boolean) + (logical_block[vpack_net[net_index].node_block[0]].clb_index + != curr_cluster_index); + if(has_ext_source) { + ext_net = vpack_to_clb_net_mapping[net_index]; + assert(ext_net != OPEN); + if (vpack_net[net_index].is_global) { + free(rr_node[curr_ext_clock].edges); + rr_node[curr_ext_clock].edges = NULL; + rr_node[curr_ext_clock].num_edges = 0; + + success = FALSE; + ipin = 0; + /* force intra-cluster net to use pins from ext route */ + for(j = 0; j < pb_graph_node->num_clock_ports; j++) { + for(k = 0; k < pb_graph_node->num_clock_pins[j]; k++) { + if(ext_net == block[iblock].nets[ipin + pb_graph_node->pb_type->num_input_pins + pb_graph_node->pb_type->num_output_pins + pin_offset]) { + success = TRUE; + rr_node[curr_ext_clock].num_edges++; + rr_node[curr_ext_clock].edges = (int*)my_realloc(rr_node[curr_ext_clock].edges, rr_node[curr_ext_clock].num_edges * sizeof(int)); + rr_node[curr_ext_clock].edges[rr_node[curr_ext_clock].num_edges - 1] = pb_graph_node->clock_pins[j][k].pin_count_in_cluster; + } + ipin++; + } + } + assert(success); + curr_ext_clock++; + } else { + free(rr_node[curr_ext_input].edges); + rr_node[curr_ext_input].edges = NULL; + rr_node[curr_ext_input].num_edges = 0; + + success = FALSE; + ipin = 0; + /* force intra-cluster net to use pins from ext route */ + for(j = 0; j < pb_graph_node->num_input_ports; j++) { + for(k = 0; k < pb_graph_node->num_input_pins[j]; k++) { + if(ext_net == block[iblock].nets[ipin + pin_offset]) { + success = TRUE; + rr_node[curr_ext_input].num_edges++; + rr_node[curr_ext_input].edges = (int*)my_realloc(rr_node[curr_ext_input].edges, rr_node[curr_ext_input].num_edges * sizeof(int)); + rr_node[curr_ext_input].edges[rr_node[curr_ext_input].num_edges - 1] = pb_graph_node->input_pins[j][k].pin_count_in_cluster; + } + ipin++; + } + } + curr_ext_input++; + assert(success); + } + } + } +} + diff --git a/vpr7_rram/vpr/SRC/pack/cluster_legality.h b/vpr7_rram/vpr/SRC/pack/cluster_legality.h new file mode 100644 index 000000000..4e6e8f4fa --- /dev/null +++ b/vpr7_rram/vpr/SRC/pack/cluster_legality.h @@ -0,0 +1,36 @@ +#ifndef CLUSTER_LEGALITY_H +#define CLUSTER_LEGALITY_H + +/* Legalizes routing for a cluster + */ +void alloc_and_load_cluster_legality_checker(void); + +void alloc_and_load_legalizer_for_cluster(INP t_block* clb, INP int clb_index, INP const t_arch *arch); + +void free_legalizer_for_cluster(INP t_block* clb, boolean free_local_rr_graph); + +void free_cluster_legality_checker(void); + +void reset_legalizer_for_cluster(t_block *clb); + +/* order of use: 1. save cluster 2. Add blocks. 3. route 4. save if successful, undo if not successful */ +void save_and_reset_routing_cluster(void); +void setup_intracluster_routing_for_molecule(INP t_pack_molecule *molecule, INOUTP t_pb_graph_node **primitives_list); +boolean try_breadth_first_route_cluster(void); +void restore_routing_cluster(void); +void save_cluster_solution(void); + +boolean is_pin_open(int i); + +void set_pb_graph_mode(t_pb_graph_node *pb_graph_node, int mode, int isOn); + +void alloc_and_load_rr_graph_for_pb_graph_node(INP t_pb_graph_node *pb_graph_node, INP const t_arch* arch, int mode); + + +/* Power user options */ +void reload_ext_net_rr_terminal_cluster(void); +void force_post_place_route_cb_input_pins(int iblock); +void setup_intracluster_routing_for_logical_block(INP int iblock, + INP t_pb_graph_node *primitive); + +#endif diff --git a/vpr7_rram/vpr/SRC/pack/cluster_placement.c b/vpr7_rram/vpr/SRC/pack/cluster_placement.c new file mode 100644 index 000000000..f85a955d0 --- /dev/null +++ b/vpr7_rram/vpr/SRC/pack/cluster_placement.c @@ -0,0 +1,802 @@ +/* + Given a group of logical blocks and a partially-packed complex block, find placement for group of logical blocks in complex block + To use, keep "cluster_placement_stats" data structure throughout packing + cluster_placement_stats undergoes these major states: + Initialization - performed once at beginning of packing + Reset - reset state in between packing of clusters + In flight - Speculatively place + Finalized - Commit or revert placements + Freed - performed once at end of packing + + Author: Jason Luu + March 12, 2012 + */ +#include +#include +#include + +#include "read_xml_arch_file.h" +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "vpr_utils.h" +#include "hash.h" +#include "cluster_placement.h" + +/****************************************/ +/*Local Function Declaration */ +/****************************************/ +static void load_cluster_placement_stats_for_pb_graph_node( + INOUTP t_cluster_placement_stats *cluster_placement_stats, + INOUTP t_pb_graph_node *pb_graph_node); +static void requeue_primitive( + INOUTP t_cluster_placement_stats *cluster_placement_stats, + t_cluster_placement_primitive *cluster_placement_primitive); +static void update_primitive_cost_or_status(INP t_pb_graph_node *pb_graph_node, + INP float incremental_cost, INP boolean valid); +static float try_place_molecule(INP t_pack_molecule *molecule, + INP t_pb_graph_node *root, INOUTP t_pb_graph_node **primitives_list, INP int clb_index); +static boolean expand_forced_pack_molecule_placement( + INP t_pack_molecule *molecule, + INP t_pack_pattern_block *pack_pattern_block, + INOUTP t_pb_graph_node **primitives_list, INOUTP float *cost); +static t_pb_graph_pin *expand_pack_molecule_pin_edge(INP int pattern_id, + INP t_pb_graph_pin *cur_pin, INP boolean forward); +static void flush_intermediate_queues( + INOUTP t_cluster_placement_stats *cluster_placement_stats); +static boolean root_passes_early_filter(INP t_pb_graph_node *root, INP t_pack_molecule *molecule, INP int clb_index); + +/****************************************/ +/*Function Definitions */ +/****************************************/ + +/** + * [0..num_pb_types-1] array of cluster placement stats, one for each type_descriptors + */ +t_cluster_placement_stats *alloc_and_load_cluster_placement_stats(void) { + t_cluster_placement_stats *cluster_placement_stats_list; + int i; + + cluster_placement_stats_list = (t_cluster_placement_stats *) my_calloc(num_types, + sizeof(t_cluster_placement_stats)); + for (i = 0; i < num_types; i++) { + if (EMPTY_TYPE != &type_descriptors[i]) { + cluster_placement_stats_list[i].valid_primitives = (t_cluster_placement_primitive **) my_calloc( + get_max_primitives_in_pb_type(type_descriptors[i].pb_type) + + 1, sizeof(t_cluster_placement_primitive*)); /* too much memory allocated but shouldn't be a problem */ + cluster_placement_stats_list[i].curr_molecule = NULL; + load_cluster_placement_stats_for_pb_graph_node( + &cluster_placement_stats_list[i], + type_descriptors[i].pb_graph_head); + } + } + return cluster_placement_stats_list; +} + +/** + * get next list of primitives for list of logical blocks + * primitives is the list of ptrs to primitives that matches with the list of logical_blocks (by index), assumes memory is preallocated + * - if this is a new block, requeue tried primitives and return a in-flight primitive list to try + * - if this is an old block, put root primitive to tried queue, requeue rest of primitives. try another set of primitives + * + * return TRUE if can find next primitive, FALSE otherwise + * + * cluster_placement_stats - ptr to the current cluster_placement_stats of open complex block + * molecule - molecule to pack into open complex block + * primitives_list - a list of primitives indexed to match logical_block_ptrs of molecule. Expects an allocated array of primitives ptrs as inputs. This function loads the array with the lowest cost primitives that implement molecule + */ +boolean get_next_primitive_list( + INOUTP t_cluster_placement_stats *cluster_placement_stats, + INP t_pack_molecule *molecule, INOUTP t_pb_graph_node **primitives_list, INP int clb_index) { + t_cluster_placement_primitive *cur, *next, *best, *before_best, *prev; + int i; + float cost, lowest_cost; + best = NULL; + before_best = NULL; + + if (cluster_placement_stats->curr_molecule != molecule) { + /* New block, requeue tried primitives and in-flight primitives */ + flush_intermediate_queues(cluster_placement_stats); + + cluster_placement_stats->curr_molecule = molecule; + } else { + /* Hack! Same failed molecule may re-enter if upper stream functions suck, I'm going to make the molecule selector more intelligent, TODO: Remove later */ + if (cluster_placement_stats->in_flight != NULL) { + /* Hack end */ + + /* old block, put root primitive currently inflight to tried queue */ + cur = cluster_placement_stats->in_flight; + next = cur->next_primitive; + cur->next_primitive = cluster_placement_stats->tried; + cluster_placement_stats->tried = cur; + /* should have only one block in flight at any point in time */ + assert(next == NULL); + cluster_placement_stats->in_flight = NULL; + } + } + + /* find next set of blocks + 1. Remove invalid blocks to invalid queue + 2. Find lowest cost array of primitives that implements blocks + 3. When found, move current blocks to in-flight, return lowest cost array of primitives + 4. Return NULL if not found + */ + lowest_cost = HUGE_POSITIVE_FLOAT; + for (i = 0; i < cluster_placement_stats->num_pb_types; i++) { + if (cluster_placement_stats->valid_primitives[i]->next_primitive == NULL) { + continue; /* no more primitives of this type available */ + } + if (primitive_type_feasible( + molecule->logical_block_ptrs[molecule->root]->index, + cluster_placement_stats->valid_primitives[i]->next_primitive->pb_graph_node->pb_type)) { + prev = cluster_placement_stats->valid_primitives[i]; + cur = cluster_placement_stats->valid_primitives[i]->next_primitive; + while (cur) { + /* remove invalid nodes lazily when encountered */ + while (cur && cur->valid == FALSE) { + prev->next_primitive = cur->next_primitive; + cur->next_primitive = cluster_placement_stats->invalid; + cluster_placement_stats->invalid = cur; + cur = prev->next_primitive; + } + if (cur == NULL) { + break; + } + /* try place molecule at root location cur */ + cost = try_place_molecule(molecule, cur->pb_graph_node, + primitives_list, clb_index); + if (cost < lowest_cost) { + lowest_cost = cost; + best = cur; + before_best = prev; + } + prev = cur; + cur = cur->next_primitive; + } + } + } + if (best == NULL) { + /* failed to find a placement */ + for (i = 0; i < molecule->num_blocks; i++) { + primitives_list[i] = NULL; + } + } else { + /* populate primitive list with best */ + cost = try_place_molecule(molecule, best->pb_graph_node, primitives_list, clb_index); + assert(cost == lowest_cost); + + /* take out best node and put it in flight */ + cluster_placement_stats->in_flight = best; + before_best->next_primitive = best->next_primitive; + best->next_primitive = NULL; + } + + if (best == NULL) { + return FALSE; + } + return TRUE; +} + +/** + * Resets one cluster placement stats by clearing incremental costs and returning all primitives to valid queue + */ +void reset_cluster_placement_stats( + INOUTP t_cluster_placement_stats *cluster_placement_stats) { + t_cluster_placement_primitive *cur, *next; + int i; + + /* Requeue primitives */ + flush_intermediate_queues(cluster_placement_stats); + cur = cluster_placement_stats->invalid; + while (cur != NULL) { + next = cur->next_primitive; + requeue_primitive(cluster_placement_stats, cur); + cur = next; + } + cur = cluster_placement_stats->invalid = NULL; + /* reset flags and cost */ + for (i = 0; i < cluster_placement_stats->num_pb_types; i++) { + assert( + cluster_placement_stats->valid_primitives[i] != NULL && cluster_placement_stats->valid_primitives[i]->next_primitive != NULL); + cur = cluster_placement_stats->valid_primitives[i]->next_primitive; + while (cur != NULL) { + cur->incremental_cost = 0; + cur->valid = TRUE; + cur = cur->next_primitive; + } + } + cluster_placement_stats->curr_molecule = NULL; +} + +/** + * Free linked lists found in cluster_placement_stats_list + */ +void free_cluster_placement_stats( + INOUTP t_cluster_placement_stats *cluster_placement_stats_list) { + t_cluster_placement_primitive *cur, *next; + int i, j; + for (i = 0; i < num_types; i++) { + cur = cluster_placement_stats_list[i].tried; + while (cur != NULL) { + next = cur->next_primitive; + free(cur); + cur = next; + } + cur = cluster_placement_stats_list[i].in_flight; + while (cur != NULL) { + next = cur->next_primitive; + free(cur); + cur = next; + } + cur = cluster_placement_stats_list[i].invalid; + while (cur != NULL) { + next = cur->next_primitive; + free(cur); + cur = next; + } + for (j = 0; j < cluster_placement_stats_list[i].num_pb_types; j++) { + cur = + cluster_placement_stats_list[i].valid_primitives[j]->next_primitive; + while (cur != NULL) { + next = cur->next_primitive; + free(cur); + cur = next; + } + free(cluster_placement_stats_list[i].valid_primitives[j]); + } + free(cluster_placement_stats_list[i].valid_primitives); + } + free(cluster_placement_stats_list); +} + +/** + * Put primitive back on queue of valid primitives + * Note that valid status is not changed because if the primitive is not valid, it will get properly collected later + */ +static void requeue_primitive( + INOUTP t_cluster_placement_stats *cluster_placement_stats, + t_cluster_placement_primitive *cluster_placement_primitive) { + int i; + int null_index; + boolean success; + null_index = OPEN; + + success = FALSE; + for (i = 0; i < cluster_placement_stats->num_pb_types; i++) { + if (cluster_placement_stats->valid_primitives[i]->next_primitive == NULL) { + null_index = i; + continue; + } + if (cluster_placement_primitive->pb_graph_node->pb_type + == cluster_placement_stats->valid_primitives[i]->next_primitive->pb_graph_node->pb_type) { + success = TRUE; + cluster_placement_primitive->next_primitive = + cluster_placement_stats->valid_primitives[i]->next_primitive; + cluster_placement_stats->valid_primitives[i]->next_primitive = + cluster_placement_primitive; + } + } + if (success == FALSE) { + assert(null_index != OPEN); + cluster_placement_primitive->next_primitive = + cluster_placement_stats->valid_primitives[null_index]->next_primitive; + cluster_placement_stats->valid_primitives[null_index]->next_primitive = + cluster_placement_primitive; + } +} + +/** + * Add any primitives found in pb_graph_nodes to cluster_placement_stats + * Adds backward link from pb_graph_node to cluster_placement_primitive + */ +static void load_cluster_placement_stats_for_pb_graph_node( + INOUTP t_cluster_placement_stats *cluster_placement_stats, + INOUTP t_pb_graph_node *pb_graph_node) { + int i, j, k; + t_cluster_placement_primitive *placement_primitive; + const t_pb_type *pb_type = pb_graph_node->pb_type; + boolean success; + if (pb_type->modes == 0) { + placement_primitive = (t_cluster_placement_primitive *) my_calloc(1, + sizeof(t_cluster_placement_primitive)); + placement_primitive->pb_graph_node = pb_graph_node; + placement_primitive->valid = TRUE; + pb_graph_node->cluster_placement_primitive = placement_primitive; + placement_primitive->base_cost = compute_primitive_base_cost( + pb_graph_node); + success = FALSE; + i = 0; + while (success == FALSE) { + if (cluster_placement_stats->valid_primitives[i] == NULL + || cluster_placement_stats->valid_primitives[i]->next_primitive->pb_graph_node->pb_type + == pb_graph_node->pb_type) { + if (cluster_placement_stats->valid_primitives[i] == NULL) { + cluster_placement_stats->valid_primitives[i] = (t_cluster_placement_primitive *) my_calloc(1, + sizeof(t_cluster_placement_primitive)); /* head of linked list is empty, makes it easier to remove nodes later */ + cluster_placement_stats->num_pb_types++; + } + success = TRUE; + placement_primitive->next_primitive = + cluster_placement_stats->valid_primitives[i]->next_primitive; + cluster_placement_stats->valid_primitives[i]->next_primitive = + placement_primitive; + } + i++; + } + } else { + for (i = 0; i < pb_type->num_modes; i++) { + for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { + for (k = 0; k < pb_type->modes[i].pb_type_children[j].num_pb; + k++) { + load_cluster_placement_stats_for_pb_graph_node( + cluster_placement_stats, + &pb_graph_node->child_pb_graph_nodes[i][j][k]); + } + } + } + } +} + +/** + * Commit primitive, invalidate primitives blocked by mode assignment and update costs for primitives in same cluster as current + * Costing is done to try to pack blocks closer to existing primitives + * actual value based on closest common ancestor to committed placement, the farther the ancestor, the less reduction in cost there is + * Side effects: All cluster_placement_primitives may be invalidated/costed in this algorithm + * Al intermediate queues are requeued + */ +void commit_primitive(INOUTP t_cluster_placement_stats *cluster_placement_stats, + INP t_pb_graph_node *primitive) { + t_pb_graph_node *pb_graph_node, *skip; + float incr_cost; + int i, j, k; + int valid_mode; + t_cluster_placement_primitive *cur; + + /* Clear out intermediate queues */ + flush_intermediate_queues(cluster_placement_stats); + + /* commit primitive as used, invalidate it */ + cur = primitive->cluster_placement_primitive; + assert(cur->valid == TRUE); + + cur->valid = FALSE; + incr_cost = -0.01; /* cost of using a node drops as its neighbours are used, this drop should be small compared to scarcity values */ + + pb_graph_node = cur->pb_graph_node; + /* walk up pb_graph_node and update primitives of children */ + while (pb_graph_node->parent_pb_graph_node != NULL) { + skip = pb_graph_node; /* do not traverse stuff that's already traversed */ + valid_mode = pb_graph_node->pb_type->parent_mode->index; + pb_graph_node = pb_graph_node->parent_pb_graph_node; + for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { + for (j = 0; + j < pb_graph_node->pb_type->modes[i].num_pb_type_children; + j++) { + for (k = 0; + k + < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; + k++) { + if (&pb_graph_node->child_pb_graph_nodes[i][j][k] != skip) { + update_primitive_cost_or_status( + &pb_graph_node->child_pb_graph_nodes[i][j][k], + incr_cost, (boolean)(i == valid_mode)); + } + } + } + } + incr_cost /= 10; /* blocks whose ancestor is further away in tree should be affected less than blocks closer in tree */ + } +} + +/** + * Set mode of cluster + */ +void set_mode_cluster_placement_stats(INP t_pb_graph_node *pb_graph_node, + int mode) { + int i, j, k; + for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { + if (i != mode) { + for (j = 0; + j < pb_graph_node->pb_type->modes[i].num_pb_type_children; + j++) { + for (k = 0; + k + < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; + k++) { + update_primitive_cost_or_status( + &pb_graph_node->child_pb_graph_nodes[i][j][k], 0, + FALSE); + } + } + } + } +} + +/** + * For sibling primitives of pb_graph node, decrease cost + * For modes invalidated by pb_graph_node, invalidate primitive + * int distance is the distance of current pb_graph_node from original + */ +static void update_primitive_cost_or_status(INP t_pb_graph_node *pb_graph_node, + INP float incremental_cost, INP boolean valid) { + int i, j, k; + t_cluster_placement_primitive *placement_primitive; + if (pb_graph_node->pb_type->num_modes == 0) { + /* is primitive */ + placement_primitive = + (t_cluster_placement_primitive*) pb_graph_node->cluster_placement_primitive; + if (valid) { + placement_primitive->incremental_cost += incremental_cost; + } else { + placement_primitive->valid = FALSE; + } + } else { + for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { + for (j = 0; + j < pb_graph_node->pb_type->modes[i].num_pb_type_children; + j++) { + for (k = 0; + k + < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; + k++) { + update_primitive_cost_or_status( + &pb_graph_node->child_pb_graph_nodes[i][j][k], + incremental_cost, valid); + } + } + } + } +} + +/** + * Try place molecule at root location, populate primitives list with locations of placement if successful + */ +static float try_place_molecule(INP t_pack_molecule *molecule, + INP t_pb_graph_node *root, INOUTP t_pb_graph_node **primitives_list, INP int clb_index) { + int list_size, i; + float cost = HUGE_POSITIVE_FLOAT; + list_size = get_array_size_of_molecule(molecule); + + if (primitive_type_feasible( + molecule->logical_block_ptrs[molecule->root]->index, + root->pb_type)) { + if (root->cluster_placement_primitive->valid == TRUE) { + if(root_passes_early_filter(root, molecule, clb_index)) { + for (i = 0; i < list_size; i++) { + primitives_list[i] = NULL; + } + cost = root->cluster_placement_primitive->base_cost + + root->cluster_placement_primitive->incremental_cost; + primitives_list[molecule->root] = root; + if (molecule->type == MOLECULE_FORCED_PACK) { + if (!expand_forced_pack_molecule_placement(molecule, + molecule->pack_pattern->root_block, primitives_list, + &cost)) { + return HUGE_POSITIVE_FLOAT; + } + } + for (i = 0; i < list_size; i++) { + assert( + (primitives_list[i] == NULL) == (molecule->logical_block_ptrs[i] == NULL)); + } + } + } + } + return cost; +} + +/** + * Expand molecule at pb_graph_node + * Assumes molecule and pack pattern connections have fan-out 1 + */ +static boolean expand_forced_pack_molecule_placement( + INP t_pack_molecule *molecule, + INP t_pack_pattern_block *pack_pattern_block, + INOUTP t_pb_graph_node **primitives_list, INOUTP float *cost) { + t_pb_graph_node *pb_graph_node = + primitives_list[pack_pattern_block->block_id]; + t_pb_graph_node *next_primitive; + t_pack_pattern_connections *cur; + int from_pin, from_port; + t_pb_graph_pin *cur_pin, *next_pin; + t_pack_pattern_block *next_block; + + cur = pack_pattern_block->connections; + while (cur) { + if (cur->from_block == pack_pattern_block) { + next_block = cur->to_block; + } else { + next_block = cur->from_block; + } + if (primitives_list[next_block->block_id] == NULL && molecule->logical_block_ptrs[next_block->block_id] != NULL) { + /* first time visiting location */ + + /* find next primitive based on pattern connections, expand next primitive if not visited */ + from_pin = cur->from_pin->pin_number; + from_port = cur->from_pin->port->port_index_by_type; + if (cur->from_block == pack_pattern_block) { + /* forward expand to find next block */ + cur_pin = &pb_graph_node->output_pins[from_port][from_pin]; + next_pin = expand_pack_molecule_pin_edge( + pack_pattern_block->pattern_index, cur_pin, TRUE); + } else { + /* backward expand to find next block */ + assert(cur->to_block == pack_pattern_block); + if (cur->from_pin->port->is_clock) { + cur_pin = &pb_graph_node->clock_pins[from_port][from_pin]; + } else { + cur_pin = &pb_graph_node->input_pins[from_port][from_pin]; + } + next_pin = expand_pack_molecule_pin_edge( + pack_pattern_block->pattern_index, cur_pin, FALSE); + } + /* found next primitive */ + if (next_pin != NULL) { + next_primitive = next_pin->parent_node; + /* Check for legality of placement, if legal, expand from legal placement, if not, return FALSE */ + if (molecule->logical_block_ptrs[next_block->block_id] != NULL + && primitives_list[next_block->block_id] == NULL) { + if (next_primitive->cluster_placement_primitive->valid + == TRUE + && primitive_type_feasible( + molecule->logical_block_ptrs[next_block->block_id]->index, + next_primitive->pb_type)) { + primitives_list[next_block->block_id] = next_primitive; + *cost += + next_primitive->cluster_placement_primitive->base_cost + + next_primitive->cluster_placement_primitive->incremental_cost; + if (!expand_forced_pack_molecule_placement(molecule, + next_block, primitives_list, cost)) { + return FALSE; + } + } else { + return FALSE; + } + } + } else { + return FALSE; + } + } + cur = cur->next; + } + + return TRUE; +} + +/** + * Find next primitive pb_graph_pin + */ +static t_pb_graph_pin *expand_pack_molecule_pin_edge(INP int pattern_id, + INP t_pb_graph_pin *cur_pin, INP boolean forward) { + int i, j, k; + t_pb_graph_pin *temp_pin, *dest_pin; + temp_pin = NULL; + dest_pin = NULL; + if (forward) { + for (i = 0; i < cur_pin->num_output_edges; i++) { + /* one fanout assumption */ + if (cur_pin->output_edges[i]->infer_pattern) { + for (k = 0; k < cur_pin->output_edges[i]->num_output_pins; + k++) { + if (cur_pin->output_edges[i]->output_pins[k]->parent_node->pb_type->num_modes + == 0) { + temp_pin = cur_pin->output_edges[i]->output_pins[k]; + } else { + temp_pin = expand_pack_molecule_pin_edge(pattern_id, + cur_pin->output_edges[i]->output_pins[k], + forward); + } + } + if (temp_pin != NULL) { + assert(dest_pin == NULL || dest_pin == temp_pin); + dest_pin = temp_pin; + } + } else { + for (j = 0; j < cur_pin->output_edges[i]->num_pack_patterns; + j++) { + if (cur_pin->output_edges[i]->pack_pattern_indices[j] + == pattern_id) { + for (k = 0; + k < cur_pin->output_edges[i]->num_output_pins; + k++) { + if (cur_pin->output_edges[i]->output_pins[k]->parent_node->pb_type->num_modes + == 0) { + temp_pin = + cur_pin->output_edges[i]->output_pins[k]; + } else { + temp_pin = + expand_pack_molecule_pin_edge( + pattern_id, + cur_pin->output_edges[i]->output_pins[k], + forward); + } + } + if (temp_pin != NULL) { + assert(dest_pin == NULL || dest_pin == temp_pin); + dest_pin = temp_pin; + } + } + } + } + } + } else { + for (i = 0; i < cur_pin->num_input_edges; i++) { + /* one fanout assumption */ + if (cur_pin->input_edges[i]->infer_pattern) { + for (k = 0; k < cur_pin->input_edges[i]->num_input_pins; k++) { + if (cur_pin->input_edges[i]->input_pins[k]->parent_node->pb_type->num_modes + == 0) { + temp_pin = cur_pin->input_edges[i]->input_pins[k]; + } else { + temp_pin = expand_pack_molecule_pin_edge(pattern_id, + cur_pin->input_edges[i]->input_pins[k], + forward); + } + } + if (temp_pin != NULL) { + assert(dest_pin == NULL || dest_pin == temp_pin); + dest_pin = temp_pin; + } + } else { + for (j = 0; j < cur_pin->input_edges[i]->num_pack_patterns; + j++) { + if (cur_pin->input_edges[i]->pack_pattern_indices[j] + == pattern_id) { + for (k = 0; k < cur_pin->input_edges[i]->num_input_pins; + k++) { + if (cur_pin->input_edges[i]->input_pins[k]->parent_node->pb_type->num_modes + == 0) { + temp_pin = + cur_pin->input_edges[i]->input_pins[k]; + } else { + temp_pin = expand_pack_molecule_pin_edge( + pattern_id, + cur_pin->input_edges[i]->input_pins[k], + forward); + } + } + if (temp_pin != NULL) { + assert(dest_pin == NULL || dest_pin == temp_pin); + dest_pin = temp_pin; + } + } + } + } + } + } + return dest_pin; +} + +static void flush_intermediate_queues( + INOUTP t_cluster_placement_stats *cluster_placement_stats) { + t_cluster_placement_primitive *cur, *next; + cur = cluster_placement_stats->tried; + while (cur != NULL) { + next = cur->next_primitive; + requeue_primitive(cluster_placement_stats, cur); + cur = next; + } + cluster_placement_stats->tried = NULL; + + cur = cluster_placement_stats->in_flight; + if (cur != NULL) { + next = cur->next_primitive; + requeue_primitive(cluster_placement_stats, cur); + /* should have at most one block in flight at any point in time */ + assert(next == NULL); + } + cluster_placement_stats->in_flight = NULL; +} + +/* Determine max index + 1 of molecule */ +int get_array_size_of_molecule(t_pack_molecule *molecule) { + if (molecule->type == MOLECULE_FORCED_PACK) { + return molecule->pack_pattern->num_blocks; + } else { + return molecule->num_blocks; + } +} + +/* Given logical block, determines if a free primitive exists for it */ +boolean exists_free_primitive_for_logical_block( + INOUTP t_cluster_placement_stats *cluster_placement_stats, + INP int ilogical_block) { + int i; + t_cluster_placement_primitive *cur, *prev; + + /* might have a primitive in flight that's still valid */ + if (cluster_placement_stats->in_flight) { + if (primitive_type_feasible(ilogical_block, + cluster_placement_stats->in_flight->pb_graph_node->pb_type)) { + return TRUE; + } + } + + /* Look through list of available primitives to see if any valid */ + for (i = 0; i < cluster_placement_stats->num_pb_types; i++) { + if (cluster_placement_stats->valid_primitives[i]->next_primitive == NULL) { + continue; /* no more primitives of this type available */ + } + if (primitive_type_feasible(ilogical_block, + cluster_placement_stats->valid_primitives[i]->next_primitive->pb_graph_node->pb_type)) { + prev = cluster_placement_stats->valid_primitives[i]; + cur = cluster_placement_stats->valid_primitives[i]->next_primitive; + while (cur) { + /* remove invalid nodes lazily when encountered */ + while (cur && cur->valid == FALSE) { + prev->next_primitive = cur->next_primitive; + cur->next_primitive = cluster_placement_stats->invalid; + cluster_placement_stats->invalid = cur; + cur = prev->next_primitive; + } + if (cur == NULL) { + break; + } + return TRUE; + } + } + } + + return FALSE; +} + + +void reset_tried_but_unused_cluster_placements( + INOUTP t_cluster_placement_stats *cluster_placement_stats) { + flush_intermediate_queues(cluster_placement_stats); +} + + +/* Quick, additional filter to see if root is feasible for molecule + + Limitation: This code can absorb a single atom by a "forced connection". A forced connection is one where there is no interconnect flexibility connecting + two primitives so if one primitive is used, then the other must also be used. + + TODO: jluu - Many ways to make this either more efficient or more robust. + 1. For forced connections, I can get the packer to try forced connections first thus avoid trying out other locations that + I know are bad thus saving runtime and potentially improving robustness because the placement cost function is not always 100%. + 2. I need to extend this so that molecules can be pulled in instead of just atoms. +*/ +static boolean root_passes_early_filter(INP t_pb_graph_node *root, INP t_pack_molecule *molecule, INP int clb_index) { + int i, j; + boolean feasible; + t_logical_block *root_block; + t_model_ports *model_port; + int inet; + int isink; + t_pb_graph_pin *sink_pb_graph_pin; + + feasible = TRUE; + root_block = molecule->logical_block_ptrs[molecule->root]; + for(i = 0; feasible && i < root->num_output_ports; i++) { + for(j = 0; feasible && j < root->num_output_pins[i]; j++) { + if(root->output_pins[i][j].is_forced_connection) { + model_port = root->output_pins[i][j].port->model_port; + inet = root_block->output_nets[model_port->index][j]; + if(inet != OPEN) { + /* This output pin has a dedicated connection to one output, make sure that molecule works */ + if(molecule->type == MOLECULE_SINGLE_ATOM) { + feasible = FALSE; /* There is only one case where an atom can fit in here, so by default, feasibility is false unless proven otherwise */ + if(vpack_net[inet].num_sinks == 1) { + isink = vpack_net[inet].node_block[1]; + if(logical_block[isink].clb_index == clb_index) { + sink_pb_graph_pin = &root->output_pins[i][j]; + while(sink_pb_graph_pin->num_output_edges != 0) { + assert(sink_pb_graph_pin->num_output_edges == 1); + assert(sink_pb_graph_pin->output_edges[0]->num_output_pins == 1); + sink_pb_graph_pin = sink_pb_graph_pin->output_edges[0]->output_pins[0]; + } + if(sink_pb_graph_pin->parent_node == logical_block[isink].pb->pb_graph_node) { + /* There is a logical block mapped to the physical position that pulls in the atom in question */ + feasible = TRUE; + } + } + } + } + } + } + } + } + return feasible; +} + diff --git a/vpr7_rram/vpr/SRC/pack/cluster_placement.h b/vpr7_rram/vpr/SRC/pack/cluster_placement.h new file mode 100644 index 000000000..92265d3e3 --- /dev/null +++ b/vpr7_rram/vpr/SRC/pack/cluster_placement.h @@ -0,0 +1,35 @@ +/* + Find placement for group of logical blocks in complex block + Author: Jason Luu + */ + +#ifndef CLUSTER_PLACEMENT_H +#define CLUSTER_PLACEMENT_H +#include "arch_types.h" +#include "util.h" + +t_cluster_placement_stats *alloc_and_load_cluster_placement_stats(void); +boolean get_next_primitive_list( + INOUTP t_cluster_placement_stats *cluster_placement_stats, + INP t_pack_molecule *molecule, + INOUTP t_pb_graph_node **primitives_list, + INP int clb_index); +void commit_primitive(INOUTP t_cluster_placement_stats *cluster_placement_stats, + INP t_pb_graph_node *primitive); +void set_mode_cluster_placement_stats(INP t_pb_graph_node *complex_block, + int mode); +void reset_cluster_placement_stats( + INOUTP t_cluster_placement_stats *cluster_placement_stats); +void free_cluster_placement_stats( + INOUTP t_cluster_placement_stats *cluster_placement_stats); + +int get_array_size_of_molecule(t_pack_molecule *molecule); +boolean exists_free_primitive_for_logical_block( + INOUTP t_cluster_placement_stats *cluster_placement_stats, + INP int ilogical_block); + +void reset_tried_but_unused_cluster_placements( + INOUTP t_cluster_placement_stats *cluster_placement_stats); + + +#endif diff --git a/vpr7_rram/vpr/SRC/pack/output_blif.c b/vpr7_rram/vpr/SRC/pack/output_blif.c new file mode 100644 index 000000000..a11affe38 --- /dev/null +++ b/vpr7_rram/vpr/SRC/pack/output_blif.c @@ -0,0 +1,559 @@ +/* + Jason Luu 2008 + Print blif representation of circuit + Assumptions: Assumes first valid rr input to node is the correct rr input + Assumes clocks are routed globally + */ + +#include +#include +#include +#include +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "output_blif.h" +#include "ReadOptions.h" + +#define LINELENGTH 1024 +#define TABLENGTH 1 + +/****************** Subroutines local to this module ************************/ + +/**************** Subroutine definitions ************************************/ + +static void print_string(const char *str_ptr, int *column, FILE * fpout) { + + /* Prints string without making any lines longer than LINELENGTH. Column * + * points to the column in which the next character will go (both used and * + * updated), and fpout points to the output file. */ + + int len; + + len = strlen(str_ptr); + if (len + 3 > LINELENGTH) { + vpr_printf(TIO_MESSAGE_ERROR, "in print_string: String %s is too long for desired maximum line length.\n", str_ptr); + exit(1); + } + + if (*column + len + 2 > LINELENGTH) { + fprintf(fpout, "\\ \n"); + *column = TABLENGTH; + } + + fprintf(fpout, "%s ", str_ptr); + *column += len + 1; +} + +static void print_net_name(int inet, int *column, FILE * fpout) { + + /* This routine prints out the vpack_net name (or open) and limits the * + * length of a line to LINELENGTH characters by using \ to continue * + * lines. net_num is the index of the vpack_net to be printed, while * + * column points to the current printing column (column is both * + * used and updated by this routine). fpout is the output file * + * pointer. */ + + const char *str_ptr; + + if (inet == OPEN) + str_ptr = "open"; + else + str_ptr = vpack_net[inet].name; + + print_string(str_ptr, column, fpout); +} + +static int find_fanin_rr_node(t_pb *cur_pb, enum PORTS type, int rr_node_index) { + /* finds first fanin rr_node */ + t_pb *parent, *sibling, *child; + int net_num, irr_node; + int i, j, k, ichild_type, ichild_inst; + int hack_empty_route_through; + t_pb_graph_node *hack_empty_pb_graph_node; + + hack_empty_route_through = OPEN; + + net_num = rr_node[rr_node_index].net_num; + + parent = cur_pb->parent_pb; + + if (net_num == OPEN) { + return OPEN; + } + + if (type == IN_PORT) { + /* check parent inputs for valid connection */ + for (i = 0; i < parent->pb_graph_node->num_input_ports; i++) { + for (j = 0; j < parent->pb_graph_node->num_input_pins[i]; j++) { + irr_node = + parent->pb_graph_node->input_pins[i][j].pin_count_in_cluster; + if (rr_node[irr_node].net_num == net_num) { + if (cur_pb->pb_graph_node->pb_type->model + && strcmp( + cur_pb->pb_graph_node->pb_type->model->name, + MODEL_LATCH) == 0) { + /* HACK: latches are special becuase LUTs can be set to route-through mode for them + I will assume that the input to a LATCH can always come from a parent input pin + this only works for hierarchical soft logic structures that follow LUT -> LATCH design + must do it better later + */ + return irr_node; + } + hack_empty_route_through = irr_node; + for (k = 0; k < rr_node[irr_node].num_edges; k++) { + if (rr_node[irr_node].edges[k] == rr_node_index) { + return irr_node; + } + } + } + } + } + /* check parent clocks for valid connection */ + for (i = 0; i < parent->pb_graph_node->num_clock_ports; i++) { + for (j = 0; j < parent->pb_graph_node->num_clock_pins[i]; j++) { + irr_node = + parent->pb_graph_node->clock_pins[i][j].pin_count_in_cluster; + if (rr_node[irr_node].net_num == net_num) { + for (k = 0; k < rr_node[irr_node].num_edges; k++) { + if (rr_node[irr_node].edges[k] == rr_node_index) { + return irr_node; + } + } + } + } + } + /* check siblings for connection */ + if (parent) { + for (ichild_type = 0; + ichild_type + < parent->pb_graph_node->pb_type->modes[parent->mode].num_pb_type_children; + ichild_type++) { + for (ichild_inst = 0; + ichild_inst + < parent->pb_graph_node->pb_type->modes[parent->mode].pb_type_children[ichild_type].num_pb; + ichild_inst++) { + if (parent->child_pbs[ichild_type] + && parent->child_pbs[ichild_type][ichild_inst].name + != NULL) { + sibling = &parent->child_pbs[ichild_type][ichild_inst]; + for (i = 0; + i < sibling->pb_graph_node->num_output_ports; + i++) { + for (j = 0; + j + < sibling->pb_graph_node->num_output_pins[i]; + j++) { + irr_node = + sibling->pb_graph_node->output_pins[i][j].pin_count_in_cluster; + if (rr_node[irr_node].net_num == net_num) { + for (k = 0; k < rr_node[irr_node].num_edges; + k++) { + if (rr_node[irr_node].edges[k] + == rr_node_index) { + return irr_node; + } + } + } + } + } + } else { + /* hack just in case routing is down through an empty cluster */ + hack_empty_pb_graph_node = + &parent->pb_graph_node->child_pb_graph_nodes[ichild_type][0][ichild_inst]; + for (i = 0; + i < hack_empty_pb_graph_node->num_output_ports; + i++) { + for (j = 0; + j + < hack_empty_pb_graph_node->num_output_pins[i]; + j++) { + irr_node = + hack_empty_pb_graph_node->output_pins[i][j].pin_count_in_cluster; + if (rr_node[irr_node].net_num == net_num) { + for (k = 0; k < rr_node[irr_node].num_edges; + k++) { + if (rr_node[irr_node].edges[k] + == rr_node_index) { + return irr_node; + } + } + } + } + } + } + } + } + } + } else { + assert(type == OUT_PORT); + + /* check children for connection */ + for (ichild_type = 0; + ichild_type + < cur_pb->pb_graph_node->pb_type->modes[cur_pb->mode].num_pb_type_children; + ichild_type++) { + for (ichild_inst = 0; + ichild_inst + < cur_pb->pb_graph_node->pb_type->modes[cur_pb->mode].pb_type_children[ichild_type].num_pb; + ichild_inst++) { + if (cur_pb->child_pbs[ichild_type] + && cur_pb->child_pbs[ichild_type][ichild_inst].name + != NULL) { + child = &cur_pb->child_pbs[ichild_type][ichild_inst]; + for (i = 0; i < child->pb_graph_node->num_output_ports; + i++) { + for (j = 0; + j < child->pb_graph_node->num_output_pins[i]; + j++) { + irr_node = + child->pb_graph_node->output_pins[i][j].pin_count_in_cluster; + if (rr_node[irr_node].net_num == net_num) { + for (k = 0; k < rr_node[irr_node].num_edges; + k++) { + if (rr_node[irr_node].edges[k] + == rr_node_index) { + return irr_node; + } + } + hack_empty_route_through = irr_node; + } + } + } + } + } + } + + /* If not in children, check current pb inputs for valid connection */ + for (i = 0; i < cur_pb->pb_graph_node->num_input_ports; i++) { + for (j = 0; j < cur_pb->pb_graph_node->num_input_pins[i]; j++) { + irr_node = + cur_pb->pb_graph_node->input_pins[i][j].pin_count_in_cluster; + if (rr_node[irr_node].net_num == net_num) { + hack_empty_route_through = irr_node; + for (k = 0; k < rr_node[irr_node].num_edges; k++) { + if (rr_node[irr_node].edges[k] == rr_node_index) { + return irr_node; + } + } + } + } + } + } + + /* TODO: Once I find a way to output routing in empty blocks then code should never reach here, for now, return OPEN */ + vpr_printf(TIO_MESSAGE_INFO, "Use hack in blif dumper (do properly later): connecting net %s #%d for pb %s type %s\n", + vpack_net[net_num].name, net_num, cur_pb->name, + cur_pb->pb_graph_node->pb_type->name); + + assert(hack_empty_route_through != OPEN); + return hack_empty_route_through; +} + +static void print_primitive(FILE *fpout, int iblk) { + t_pb *pb; + int clb_index; + int i, j, k, node_index; + int in_port_index, out_port_index, clock_port_index; + struct s_linked_vptr *truth_table; + const t_pb_type *pb_type; + + pb = logical_block[iblk].pb; + pb_type = pb->pb_graph_node->pb_type; + clb_index = logical_block[iblk].clb_index; + + if (logical_block[iblk].type == VPACK_INPAD + || logical_block[iblk].type == VPACK_OUTPAD) { + /* do nothing */ + } else if (logical_block[iblk].type == VPACK_LATCH) { + fprintf(fpout, ".latch "); + + in_port_index = 0; + out_port_index = 0; + clock_port_index = 0; + for (i = 0; i < pb_type->num_ports; i++) { + if (pb_type->ports[i].type == IN_PORT + && pb_type->ports[i].is_clock == FALSE) { + assert(pb_type->ports[i].num_pins == 1); + assert(logical_block[iblk].input_nets[i][0] != OPEN); + node_index = + pb->pb_graph_node->input_pins[in_port_index][0].pin_count_in_cluster; + fprintf(fpout, "clb_%d_rr_node_%d ", clb_index, + find_fanin_rr_node(pb, pb_type->ports[i].type, + node_index)); + in_port_index++; + } + } + for (i = 0; i < pb_type->num_ports; i++) { + if (pb_type->ports[i].type == OUT_PORT) { + assert(pb_type->ports[i].num_pins == 1 && out_port_index == 0); + node_index = + pb->pb_graph_node->output_pins[out_port_index][0].pin_count_in_cluster; + fprintf(fpout, "clb_%d_rr_node_%d re ", clb_index, node_index); + out_port_index++; + } + } + for (i = 0; i < pb_type->num_ports; i++) { + if (pb_type->ports[i].type == IN_PORT + && pb_type->ports[i].is_clock == TRUE) { + assert(logical_block[iblk].clock_net != OPEN); + node_index = + pb->pb_graph_node->clock_pins[clock_port_index][0].pin_count_in_cluster; + fprintf(fpout, "clb_%d_rr_node_%d 2", clb_index, + find_fanin_rr_node(pb, pb_type->ports[i].type, + node_index)); + clock_port_index++; + } + } + fprintf(fpout, "\n"); + } else if (logical_block[iblk].type == VPACK_COMB) { + if (strcmp(logical_block[iblk].model->name, "names") == 0) { + fprintf(fpout, ".names "); + in_port_index = 0; + out_port_index = 0; + for (i = 0; i < pb_type->num_ports; i++) { + if (pb_type->ports[i].type == IN_PORT + && pb_type->ports[i].is_clock == FALSE) { + /* This is a LUT + LUTs receive special handling because a LUT has logically equivalent inputs. + The intra-logic block router may have taken advantage of logical equivalence so we need to unscramble the inputs when we output the LUT logic. + */ + for (j = 0; j < pb_type->ports[i].num_pins; j++) { + if (logical_block[iblk].input_nets[in_port_index][j] != OPEN) { + for (k = 0; k < pb_type->ports[i].num_pins; k++) { + node_index = pb->pb_graph_node->input_pins[in_port_index][k].pin_count_in_cluster; + if(rr_node[node_index].net_num != OPEN) { + if(rr_node[node_index].net_num == logical_block[iblk].input_nets[in_port_index][j]) { + fprintf(fpout, "clb_%d_rr_node_%d ", clb_index, + find_fanin_rr_node(pb, + pb_type->ports[i].type, + node_index)); + break; + } + } + } + if(k == pb_type->ports[i].num_pins) { + /* Failed to find LUT input, a netlist error has occurred */ + vpr_printf(TIO_MESSAGE_ERROR, "LUT %s missing input %s post packing. This is a VPR internal error, report to vpr@eecg.utoronto.ca\n", + logical_block[iblk].name, vpack_net[logical_block[iblk].input_nets[in_port_index][j]].name); + exit(1); + } + } + } + in_port_index++; + } + } + for (i = 0; i < pb_type->num_ports; i++) { + if (pb_type->ports[i].type == OUT_PORT) { + for (j = 0; j < pb_type->ports[i].num_pins; j++) { + node_index = + pb->pb_graph_node->output_pins[out_port_index][j].pin_count_in_cluster; + fprintf(fpout, "clb_%d_rr_node_%d\n", clb_index, + node_index); + } + out_port_index++; + } + } + truth_table = logical_block[iblk].truth_table; + while (truth_table) { + fprintf(fpout, "%s\n", (char *) truth_table->data_vptr); + truth_table = truth_table->next; + } + } else { + vpr_printf(TIO_MESSAGE_WARNING, "TODO: Implement blif dumper for subckt %s model %s", logical_block[iblk].name, logical_block[iblk].model->name); + } + } +} + +static void print_pb(FILE *fpout, t_pb * pb, int clb_index) { + + int column; + int i, j, k; + const t_pb_type *pb_type; + t_mode *mode; + int in_port_index, out_port_index, node_index; + + pb_type = pb->pb_graph_node->pb_type; + mode = &pb_type->modes[pb->mode]; + column = 0; + if (pb_type->num_modes == 0) { + print_primitive(fpout, pb->logical_block); + } else { + in_port_index = 0; + out_port_index = 0; + for (i = 0; i < pb_type->num_ports; i++) { + if (!pb_type->ports[i].is_clock) { + for (j = 0; j < pb_type->ports[i].num_pins; j++) { + /* print .blif buffer to represent routing */ + column = 0; + if (pb_type->ports[i].type == OUT_PORT) { + node_index = + pb->pb_graph_node->output_pins[out_port_index][j].pin_count_in_cluster; + if (rr_node[node_index].net_num != OPEN) { + fprintf(fpout, ".names clb_%d_rr_node_%d ", + clb_index, + find_fanin_rr_node(pb, + pb_type->ports[i].type, + node_index)); + if (pb->parent_pb) { + fprintf(fpout, "clb_%d_rr_node_%d ", clb_index, + node_index); + } else { + print_net_name(rr_node[node_index].net_num, + &column, fpout); + } + fprintf(fpout, "\n1 1\n"); + if (pb->parent_pb == NULL) { + for (k = 1; + k + <= vpack_net[rr_node[node_index].net_num].num_sinks; + k++) { + /* output pads pre-pended with "out:", must remove */ + if (logical_block[vpack_net[rr_node[node_index].net_num].node_block[k]].type + == VPACK_OUTPAD + && strcmp( + logical_block[vpack_net[rr_node[node_index].net_num].node_block[k]].name + + 4, + vpack_net[rr_node[node_index].net_num].name) + != 0) { + fprintf(fpout, + ".names clb_%d_rr_node_%d %s", + clb_index, + find_fanin_rr_node(pb, + pb_type->ports[i].type, + node_index), + logical_block[vpack_net[rr_node[node_index].net_num].node_block[k]].name + + 4); + fprintf(fpout, "\n1 1\n"); + } + } + } + } + + } else { + node_index = + pb->pb_graph_node->input_pins[in_port_index][j].pin_count_in_cluster; + if (rr_node[node_index].net_num != OPEN) { + + fprintf(fpout, ".names "); + if (pb->parent_pb) { + fprintf(fpout, "clb_%d_rr_node_%d ", clb_index, + find_fanin_rr_node(pb, + pb_type->ports[i].type, + node_index)); + } else { + print_net_name(rr_node[node_index].net_num, + &column, fpout); + } + fprintf(fpout, "clb_%d_rr_node_%d", clb_index, + node_index); + fprintf(fpout, "\n1 1\n"); + } + } + } + } + if (pb_type->ports[i].type == OUT_PORT) { + out_port_index++; + } else { + in_port_index++; + } + } + for (i = 0; i < mode->num_pb_type_children; i++) { + for (j = 0; j < mode->pb_type_children[i].num_pb; j++) { + /* If child pb is not used but routing is used, I must print things differently */ + if ((pb->child_pbs[i] != NULL) + && (pb->child_pbs[i][j].name != NULL)) { + print_pb(fpout, &pb->child_pbs[i][j], clb_index); + } else { + /* do nothing for now, we'll print something later if needed */ + } + } + } + } +} + +static void print_clusters(t_block *clb, int num_clusters, FILE * fpout) { + + /* Prints out one cluster (clb). Both the external pins and the * + * internal connections are printed out. */ + + int icluster; + + for (icluster = 0; icluster < num_clusters; icluster++) { + rr_node = clb[icluster].pb->rr_graph; + if (clb[icluster].type != IO_TYPE) + print_pb(fpout, clb[icluster].pb, icluster); + } +} + +void output_blif (t_block *clb, int num_clusters, boolean global_clocks, + boolean * is_clock, const char *out_fname, boolean skip_clustering) { + + /* + * This routine dumps out the output netlist in a format suitable for * + * input to vpr. This routine also dumps out the internal structure of * + * the cluster, in essentially a graph based format. */ + + FILE *fpout; + int bnum, column; + struct s_linked_vptr *p_io_removed; + int i; + + fpout = my_fopen(out_fname, "w", 0); + + column = 0; + fprintf(fpout, ".model %s\n", blif_circuit_name); + + /* Print out all input and output pads. */ + fprintf(fpout, "\n.inputs "); + for (bnum = 0; bnum < num_logical_blocks; bnum++) { + if (logical_block[bnum].type == VPACK_INPAD) { + print_string(logical_block[bnum].name, &column, fpout); + } + } + p_io_removed = circuit_p_io_removed; + while (p_io_removed) { + print_string((char*) p_io_removed->data_vptr, &column, fpout); + p_io_removed = p_io_removed->next; + } + + column = 0; + fprintf(fpout, "\n.outputs "); + for (bnum = 0; bnum < num_logical_blocks; bnum++) { + if (logical_block[bnum].type == VPACK_OUTPAD) { + /* remove output prefix "out:" */ + print_string(logical_block[bnum].name + 4, &column, fpout); + } + } + + column = 0; + + fprintf(fpout, "\n\n"); + + /* print logic of clusters */ + print_clusters(clb, num_clusters, fpout); + + /* handle special case: input goes straight to output without going through any logic */ + for (bnum = 0; bnum < num_logical_blocks; bnum++) { + if (logical_block[bnum].type == VPACK_INPAD) { + for (i = 1; + i + <= vpack_net[logical_block[bnum].output_nets[0][0]].num_sinks; + i++) { + if (logical_block[vpack_net[logical_block[bnum].output_nets[0][0]].node_block[i]].type + == VPACK_OUTPAD) { + fprintf(fpout, ".names "); + print_string(logical_block[bnum].name, &column, fpout); + print_string( + logical_block[vpack_net[logical_block[bnum].output_nets[0][0]].node_block[i]].name + + 4, &column, fpout); + fprintf(fpout, "\n1 1\n"); + } + } + } + } + + fprintf(fpout, "\n.end\n"); + + fclose(fpout); +} diff --git a/vpr7_rram/vpr/SRC/pack/output_blif.h b/vpr7_rram/vpr/SRC/pack/output_blif.h new file mode 100644 index 000000000..38463de61 --- /dev/null +++ b/vpr7_rram/vpr/SRC/pack/output_blif.h @@ -0,0 +1,3 @@ +void output_blif (t_block *clb, int num_clusters, boolean global_clocks, + boolean * is_clock, const char *out_fname, boolean skip_clustering); + diff --git a/vpr7_rram/vpr/SRC/pack/output_clustering.c b/vpr7_rram/vpr/SRC/pack/output_clustering.c new file mode 100755 index 000000000..db3a5fed9 --- /dev/null +++ b/vpr7_rram/vpr/SRC/pack/output_clustering.c @@ -0,0 +1,609 @@ +/* + Jason Luu 2008 + Print complex block information to a file + */ + +#include +#include +#include +#include +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "output_clustering.h" +#include "read_xml_arch_file.h" + +#define LINELENGTH 1024 +#define TAB_LENGTH 4 + +/****************** Subroutines local to this module ************************/ + +/**************** Subroutine definitions ************************************/ + +static void print_tabs(FILE *fpout, int num_tabs) { + int i; + for (i = 0; i < num_tabs; i++) { + fprintf(fpout, "\t"); + } +} + +static void print_string(const char *str_ptr, int *column, int num_tabs, FILE * fpout) { + + /* Prints string without making any lines longer than LINELENGTH. Column * + * points to the column in which the next character will go (both used and * + * updated), and fpout points to the output file. */ + + int len; + + len = strlen(str_ptr); + if (len + 3 > LINELENGTH) { + vpr_printf(TIO_MESSAGE_ERROR, "in print_string: String %s is too long for desired maximum line length.\n", str_ptr); + exit(1); + } + + if (*column + len + 2 > LINELENGTH) { + fprintf(fpout, "\n"); + print_tabs(fpout, num_tabs); + *column = num_tabs * TAB_LENGTH; + } + + fprintf(fpout, "%s ", str_ptr); + *column += len + 1; +} + +static void print_net_name(int inet, int *column, int num_tabs, FILE * fpout) { + + /* This routine prints out the vpack_net name (or open) and limits the * + * length of a line to LINELENGTH characters by using \ to continue * + * lines. net_num is the index of the vpack_net to be printed, while * + * column points to the current printing column (column is both * + * used and updated by this routine). fpout is the output file * + * pointer. */ + + const char *str_ptr; + + if (inet == OPEN) + str_ptr = "open"; + else + str_ptr = vpack_net[inet].name; + + print_string(str_ptr, column, num_tabs, fpout); +} + +static void print_interconnect(int inode, int *column, int num_tabs, + FILE * fpout) { + + /* This routine prints out the vpack_net name (or open) and limits the * + * length of a line to LINELENGTH characters by using \ to continue * + * lines. net_num is the index of the vpack_net to be printed, while * + * column points to the current printing column (column is both * + * used and updated by this routine). fpout is the output file * + * pointer. */ + + char *str_ptr, *name; + int prev_node, prev_edge; + int len; + + if (rr_node[inode].net_num == OPEN) { + print_string("open", column, num_tabs, fpout); + } else { + str_ptr = NULL; + prev_node = rr_node[inode].prev_node; + prev_edge = rr_node[inode].prev_edge; + + if (prev_node == OPEN + && rr_node[inode].pb_graph_pin->port->parent_pb_type->num_modes + == 0 + && rr_node[inode].pb_graph_pin->port->type == OUT_PORT) { /* This is a primitive output */ + print_net_name(rr_node[inode].net_num, column, num_tabs, fpout); + } else { + name = + rr_node[prev_node].pb_graph_pin->output_edges[prev_edge]->interconnect->name; + if (rr_node[prev_node].pb_graph_pin->port->parent_pb_type->depth + >= rr_node[inode].pb_graph_pin->port->parent_pb_type->depth) { + /* Connections from siblings or children should have an explicit index, connections from parent does not need an explicit index */ + len = + strlen( + rr_node[prev_node].pb_graph_pin->parent_node->pb_type->name) + + rr_node[prev_node].pb_graph_pin->parent_node->placement_index + / 10 + + strlen( + rr_node[prev_node].pb_graph_pin->port->name) + + rr_node[prev_node].pb_graph_pin->pin_number + / 10 + strlen(name) + 11; + str_ptr = (char*)my_malloc(len * sizeof(char)); + sprintf(str_ptr, "%s[%d].%s[%d]->%s ", + rr_node[prev_node].pb_graph_pin->parent_node->pb_type->name, + rr_node[prev_node].pb_graph_pin->parent_node->placement_index, + rr_node[prev_node].pb_graph_pin->port->name, + rr_node[prev_node].pb_graph_pin->pin_number, name); + } else { + len = + strlen( + rr_node[prev_node].pb_graph_pin->parent_node->pb_type->name) + + strlen( + rr_node[prev_node].pb_graph_pin->port->name) + + rr_node[prev_node].pb_graph_pin->pin_number + / 10 + strlen(name) + 8; + str_ptr = (char*)my_malloc(len * sizeof(char)); + sprintf(str_ptr, "%s.%s[%d]->%s ", + rr_node[prev_node].pb_graph_pin->parent_node->pb_type->name, + rr_node[prev_node].pb_graph_pin->port->name, + rr_node[prev_node].pb_graph_pin->pin_number, name); + } + print_string(str_ptr, column, num_tabs, fpout); + } + if (str_ptr) + free(str_ptr); + } +} + +static void print_open_pb_graph_node(t_pb_graph_node * pb_graph_node, + int pb_index, boolean is_used, int tab_depth, FILE * fpout) { + int column = 0; + int i, j, k, m; + const t_pb_type * pb_type, *child_pb_type; + t_mode * mode = NULL; + int prev_edge, prev_node; + t_pb_graph_pin *pb_graph_pin; + int mode_of_edge, port_index, node_index; + + mode_of_edge = UNDEFINED; + + pb_type = pb_graph_node->pb_type; + + print_tabs(fpout, tab_depth); + + if (is_used) { + /* Determine mode if applicable */ + port_index = 0; + for (i = 0; i < pb_type->num_ports; i++) { + if (pb_type->ports[i].type == OUT_PORT) { + assert(!pb_type->ports[i].is_clock); + for (j = 0; j < pb_type->ports[i].num_pins; j++) { + node_index = + pb_graph_node->output_pins[port_index][j].pin_count_in_cluster; + if (pb_type->num_modes > 0 + && rr_node[node_index].net_num != OPEN) { + prev_edge = rr_node[node_index].prev_edge; + prev_node = rr_node[node_index].prev_node; + pb_graph_pin = rr_node[prev_node].pb_graph_pin; + mode_of_edge = + pb_graph_pin->output_edges[prev_edge]->interconnect->parent_mode_index; + assert( + mode == NULL || &pb_type->modes[mode_of_edge] == mode); + mode = &pb_type->modes[mode_of_edge]; + } + } + port_index++; + } + } + + assert(mode != NULL && mode_of_edge != UNDEFINED); + fprintf(fpout, + "\n", + pb_graph_node->pb_type->name, pb_index, mode->name); + + print_tabs(fpout, tab_depth); + fprintf(fpout, "\t\n"); + port_index = 0; + for (i = 0; i < pb_type->num_ports; i++) { + if (!pb_type->ports[i].is_clock + && pb_type->ports[i].type == IN_PORT) { + print_tabs(fpout, tab_depth); + fprintf(fpout, "\t\t", + pb_graph_node->pb_type->ports[i].name); + for (j = 0; j < pb_type->ports[i].num_pins; j++) { + node_index = + pb_graph_node->input_pins[port_index][j].pin_count_in_cluster; + print_interconnect(node_index, &column, tab_depth + 2, + fpout); + } + fprintf(fpout, "\n"); + port_index++; + } + } + print_tabs(fpout, tab_depth); + fprintf(fpout, "\t\n"); + + column = tab_depth * TAB_LENGTH + 8; /* Next column I will write to. */ + print_tabs(fpout, tab_depth); + fprintf(fpout, "\t\n"); + port_index = 0; + for (i = 0; i < pb_type->num_ports; i++) { + if (pb_type->ports[i].type == OUT_PORT) { + print_tabs(fpout, tab_depth); + fprintf(fpout, "\t\t", + pb_graph_node->pb_type->ports[i].name); + assert(!pb_type->ports[i].is_clock); + for (j = 0; j < pb_type->ports[i].num_pins; j++) { + node_index = + pb_graph_node->output_pins[port_index][j].pin_count_in_cluster; + print_interconnect(node_index, &column, tab_depth + 2, + fpout); + } + fprintf(fpout, "\n"); + port_index++; + } + } + print_tabs(fpout, tab_depth); + fprintf(fpout, "\t\n"); + + column = tab_depth * TAB_LENGTH + 8; /* Next column I will write to. */ + print_tabs(fpout, tab_depth); + fprintf(fpout, "\t\n"); + port_index = 0; + for (i = 0; i < pb_type->num_ports; i++) { + if (pb_type->ports[i].is_clock + && pb_type->ports[i].type == IN_PORT) { + print_tabs(fpout, tab_depth); + fprintf(fpout, "\t\t", + pb_graph_node->pb_type->ports[i].name); + for (j = 0; j < pb_type->ports[i].num_pins; j++) { + node_index = + pb_graph_node->clock_pins[port_index][j].pin_count_in_cluster; + print_interconnect(node_index, &column, tab_depth + 2, + fpout); + } + fprintf(fpout, "\n"); + port_index++; + } + } + print_tabs(fpout, tab_depth); + fprintf(fpout, "\t\n"); + + if (pb_type->num_modes > 0) { + for (i = 0; i < mode->num_pb_type_children; i++) { + child_pb_type = &mode->pb_type_children[i]; + for (j = 0; j < mode->pb_type_children[i].num_pb; j++) { + port_index = 0; + is_used = FALSE; + for (k = 0; k < child_pb_type->num_ports && !is_used; k++) { + if (child_pb_type->ports[k].type == OUT_PORT) { + for (m = 0; m < child_pb_type->ports[k].num_pins; + m++) { + node_index = + pb_graph_node->child_pb_graph_nodes[mode_of_edge][i][j].output_pins[port_index][m].pin_count_in_cluster; + if (rr_node[node_index].net_num != OPEN) { + is_used = TRUE; + break; + } + } + port_index++; + } + } + print_open_pb_graph_node( + &pb_graph_node->child_pb_graph_nodes[mode_of_edge][i][j], + j, is_used, tab_depth + 1, fpout); + } + } + } + + print_tabs(fpout, tab_depth); + fprintf(fpout, "\n"); + } else { + fprintf(fpout, "\n", + pb_graph_node->pb_type->name, pb_index); + } +} + +static void print_pb(FILE *fpout, t_pb * pb, int pb_index, int tab_depth) { + + int column; + int i, j, k, m; + const t_pb_type *pb_type, *child_pb_type; + t_pb_graph_node *pb_graph_node; + t_mode *mode; + int port_index, node_index; + boolean is_used; + + pb_type = pb->pb_graph_node->pb_type; + pb_graph_node = pb->pb_graph_node; + mode = &pb_type->modes[pb->mode]; + column = tab_depth * TAB_LENGTH + 8; /* Next column I will write to. */ + print_tabs(fpout, tab_depth); + if (pb_type->num_modes == 0) { + fprintf(fpout, "\n", pb->name, + pb_type->name, pb_index); + } else { + fprintf(fpout, "\n", + pb->name, pb_type->name, pb_index, mode->name); + } + + print_tabs(fpout, tab_depth); + fprintf(fpout, "\t\n"); + port_index = 0; + for (i = 0; i < pb_type->num_ports; i++) { + if (!pb_type->ports[i].is_clock && pb_type->ports[i].type == IN_PORT) { + print_tabs(fpout, tab_depth); + fprintf(fpout, "\t\t", + pb_graph_node->pb_type->ports[i].name); + for (j = 0; j < pb_type->ports[i].num_pins; j++) { + node_index = + pb->pb_graph_node->input_pins[port_index][j].pin_count_in_cluster; + if (pb_type->parent_mode == NULL) { + print_net_name(rr_node[node_index].net_num, &column, + tab_depth, fpout); + } else { + print_interconnect(node_index, &column, tab_depth + 2, + fpout); + } + } + fprintf(fpout, "\n"); + port_index++; + } + } + print_tabs(fpout, tab_depth); + fprintf(fpout, "\t\n"); + + column = tab_depth * TAB_LENGTH + 8; /* Next column I will write to. */ + print_tabs(fpout, tab_depth); + fprintf(fpout, "\t\n"); + port_index = 0; + for (i = 0; i < pb_type->num_ports; i++) { + if (pb_type->ports[i].type == OUT_PORT) { + assert(!pb_type->ports[i].is_clock); + print_tabs(fpout, tab_depth); + fprintf(fpout, "\t\t", + pb_graph_node->pb_type->ports[i].name); + for (j = 0; j < pb_type->ports[i].num_pins; j++) { + node_index = + pb->pb_graph_node->output_pins[port_index][j].pin_count_in_cluster; + print_interconnect(node_index, &column, tab_depth + 2, fpout); + } + fprintf(fpout, "\n"); + port_index++; + } + } + print_tabs(fpout, tab_depth); + fprintf(fpout, "\t\n"); + + column = tab_depth * TAB_LENGTH + 8; /* Next column I will write to. */ + print_tabs(fpout, tab_depth); + fprintf(fpout, "\t\n"); + port_index = 0; + for (i = 0; i < pb_type->num_ports; i++) { + if (pb_type->ports[i].is_clock && pb_type->ports[i].type == IN_PORT) { + print_tabs(fpout, tab_depth); + fprintf(fpout, "\t\t", + pb_graph_node->pb_type->ports[i].name); + for (j = 0; j < pb_type->ports[i].num_pins; j++) { + node_index = + pb->pb_graph_node->clock_pins[port_index][j].pin_count_in_cluster; + if (pb_type->parent_mode == NULL) { + print_net_name(rr_node[node_index].net_num, &column, + tab_depth, fpout); + } else { + print_interconnect(node_index, &column, tab_depth + 2, + fpout); + } + } + fprintf(fpout, "\n"); + port_index++; + } + } + print_tabs(fpout, tab_depth); + fprintf(fpout, "\t\n"); + + if (pb_type->num_modes > 0) { + for (i = 0; i < mode->num_pb_type_children; i++) { + for (j = 0; j < mode->pb_type_children[i].num_pb; j++) { + /* If child pb is not used but routing is used, I must print things differently */ + if ((pb->child_pbs[i] != NULL) + && (pb->child_pbs[i][j].name != NULL)) { + print_pb(fpout, &pb->child_pbs[i][j], j, tab_depth + 1); + } else { + is_used = FALSE; + child_pb_type = &mode->pb_type_children[i]; + port_index = 0; + + for (k = 0; k < child_pb_type->num_ports && !is_used; k++) { + if (child_pb_type->ports[k].type == OUT_PORT) { + for (m = 0; m < child_pb_type->ports[k].num_pins; + m++) { + node_index = + pb_graph_node->child_pb_graph_nodes[pb->mode][i][j].output_pins[port_index][m].pin_count_in_cluster; + if (rr_node[node_index].net_num != OPEN) { + is_used = TRUE; + break; + } + } + port_index++; + } + } + print_open_pb_graph_node( + &pb_graph_node->child_pb_graph_nodes[pb->mode][i][j], + j, is_used, tab_depth + 1, fpout); + } + } + } + } + print_tabs(fpout, tab_depth); + fprintf(fpout, "\n"); +} + +static void print_clusters(t_block *clb, int num_clusters, FILE * fpout) { + + /* Prints out one cluster (clb). Both the external pins and the * + * internal connections are printed out. */ + + int icluster; + + for (icluster = 0; icluster < num_clusters; icluster++) { + rr_node = clb[icluster].pb->rr_graph; + + /* TODO: Must do check that total CLB pins match top-level pb pins, perhaps check this earlier? */ + + print_pb(fpout, clb[icluster].pb, icluster, 1); + } +} + +static void print_stats(t_block *clb, int num_clusters) { + + /* Prints out one cluster (clb). Both the external pins and the * + * internal connections are printed out. */ + + int ipin, icluster, itype, inet;/*, iblk;*/ + /*int unabsorbable_ffs;*/ + int total_nets_absorbed; + boolean * nets_absorbed; + + int *num_clb_types, *num_clb_inputs_used, *num_clb_outputs_used; + + nets_absorbed = NULL; + num_clb_types = num_clb_inputs_used = num_clb_outputs_used = NULL; + + num_clb_types = (int*) my_calloc(num_types, sizeof(int)); + num_clb_inputs_used = (int*) my_calloc(num_types, sizeof(int)); + num_clb_outputs_used = (int*) my_calloc(num_types, sizeof(int)); + + + nets_absorbed = (boolean *) my_calloc(num_logical_nets, sizeof(boolean)); + for (inet = 0; inet < num_logical_nets; inet++) { + nets_absorbed[inet] = TRUE; + } + +#if 0 + +/*counting number of flipflops which cannot be absorbed to check the optimality of the packer wrt CLB density*/ + + unabsorbable_ffs = 0; + for (iblk = 0; iblk < num_logical_blocks; iblk++) { + if (strcmp(logical_block[iblk].model->name, "latch") == 0) { + if (vpack_net[logical_block[iblk].input_nets[0][0]].num_sinks > 1 + || strcmp( + logical_block[vpack_net[logical_block[iblk].input_nets[0][0]].node_block[0]].model->name, + "names") != 0) { + unabsorbable_ffs++; + } + } + } + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "%d FFs in input netlist not absorbable (ie. impossible to form BLE).\n", unabsorbable_ffs); +#endif + + /* Counters used only for statistics purposes. */ + + for (icluster = 0; icluster < num_clusters; icluster++) { + for (ipin = 0; ipin < clb[icluster].type->num_pins; ipin++) { + if (clb[icluster].nets[ipin] != OPEN) { + nets_absorbed[clb[icluster].nets[ipin]] = FALSE; + if (clb[icluster].type->class_inf[clb[icluster].type->pin_class[ipin]].type + == RECEIVER) { + num_clb_inputs_used[clb[icluster].type->index]++; + } else if (clb[icluster].type->class_inf[clb[icluster].type->pin_class[ipin]].type + == DRIVER) { + num_clb_outputs_used[clb[icluster].type->index]++; + } + } + } + num_clb_types[clb[icluster].type->index]++; + } + + for (itype = 0; itype < num_types; itype++) { + if (num_clb_types[itype] == 0) { + vpr_printf(TIO_MESSAGE_INFO, "\t%s: # blocks: %d, average # input + clock pins used: %g, average # output pins used: %g\n", + type_descriptors[itype].name, num_clb_types[itype], 0.0, 0.0); + } else { + vpr_printf(TIO_MESSAGE_INFO, "\t%s: # blocks: %d, average # input + clock pins used: %g, average # output pins used: %g\n", + type_descriptors[itype].name, num_clb_types[itype], + (float) num_clb_inputs_used[itype] / (float) num_clb_types[itype], + (float) num_clb_outputs_used[itype] / (float) num_clb_types[itype]); + } + } + + total_nets_absorbed = 0; + for (inet = 0; inet < num_logical_nets; inet++) { + if (nets_absorbed[inet] == TRUE) { + total_nets_absorbed++; + } + } + vpr_printf(TIO_MESSAGE_INFO, "Absorbed logical nets %d out of %d nets, %d nets not absorbed.\n", + total_nets_absorbed, num_logical_nets, num_logical_nets - total_nets_absorbed); + free(nets_absorbed); + free(num_clb_types); + free(num_clb_inputs_used); + free(num_clb_outputs_used); + /* TODO: print more stats */ +} + +void output_clustering(t_block *clb, int num_clusters, boolean global_clocks, + boolean * is_clock, char *out_fname, boolean skip_clustering) { + + /* + * This routine dumps out the output netlist in a format suitable for * + * input to vpr. This routine also dumps out the internal structure of * + * the cluster, in essentially a graph based format. */ + + FILE *fpout; + int bnum, netnum, column; + + fpout = fopen(out_fname, "w"); + + fprintf(fpout, "\n", + out_fname); + fprintf(fpout, "\t\n\t\t"); + + column = 2 * TAB_LENGTH; /* Organize whitespace to ident data inside block */ + for (bnum = 0; bnum < num_logical_blocks; bnum++) { + if (logical_block[bnum].type == VPACK_INPAD) { + print_string(logical_block[bnum].name, &column, 2, fpout); + } + } + fprintf(fpout, "\n\t\n"); + fprintf(fpout, "\n\t\n\t\t"); + + column = 2 * TAB_LENGTH; + for (bnum = 0; bnum < num_logical_blocks; bnum++) { + if (logical_block[bnum].type == VPACK_OUTPAD) { + print_string(logical_block[bnum].name, &column, 2, fpout); + } + } + fprintf(fpout, "\n\t\n"); + + column = 2 * TAB_LENGTH; + if (global_clocks) { + fprintf(fpout, "\n\t\n\t\t"); + + for (netnum = 0; netnum < num_logical_nets; netnum++) { + if (is_clock[netnum]) { + print_string(vpack_net[netnum].name, &column, 2, fpout); + } + } + fprintf(fpout, "\n\t\n\n"); + } + + /* Print out all input and output pads. */ + + for (bnum = 0; bnum < num_logical_blocks; bnum++) { + switch (logical_block[bnum].type) { + case VPACK_INPAD: + case VPACK_OUTPAD: + case VPACK_COMB: + case VPACK_LATCH: + if (skip_clustering) { + assert(0); + } + break; + + case VPACK_EMPTY: + vpr_printf(TIO_MESSAGE_ERROR, "in output_netlist: logical_block %d is VPACK_EMPTY.\n", + bnum); + exit(1); + break; + + default: + vpr_printf(TIO_MESSAGE_ERROR, "in output_netlist: Unexpected type %d for logical_block %d.\n", + logical_block[bnum].type, bnum); + } + } + + if (skip_clustering == FALSE) + print_clusters(clb, num_clusters, fpout); + + fprintf(fpout, "\n\n"); + + fclose(fpout); + + print_stats(clb, num_clusters); +} diff --git a/vpr7_rram/vpr/SRC/pack/output_clustering.h b/vpr7_rram/vpr/SRC/pack/output_clustering.h new file mode 100644 index 000000000..935c5b06a --- /dev/null +++ b/vpr7_rram/vpr/SRC/pack/output_clustering.h @@ -0,0 +1,3 @@ +void output_clustering(t_block *clb, int num_clusters, boolean global_clocks, + boolean * is_clock, char *out_fname, boolean skip_clustering); + diff --git a/vpr7_rram/vpr/SRC/pack/pack.c b/vpr7_rram/vpr/SRC/pack/pack.c new file mode 100644 index 000000000..3d73aec90 --- /dev/null +++ b/vpr7_rram/vpr/SRC/pack/pack.c @@ -0,0 +1,165 @@ +#include +#include +#include +#include "read_xml_arch_file.h" +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "prepack.h" +#include "pack.h" +#include "read_blif.h" +#include "cluster.h" +#include "output_clustering.h" +#include "ReadOptions.h" + +/* #define DUMP_PB_GRAPH 1 */ +/* #define DUMP_BLIF_INPUT 1 */ + +static boolean *alloc_and_load_is_clock(boolean global_clocks); + +void try_pack(INP struct s_packer_opts *packer_opts, INP const t_arch * arch, + INP t_model *user_models, INP t_model *library_models, t_timing_inf timing_inf, float interc_delay) { + boolean *is_clock; + int num_models; + t_model *cur_model; + t_pack_patterns *list_of_packing_patterns; + int num_packing_patterns; + t_pack_molecule *list_of_pack_molecules, * cur_pack_molecule; + int num_pack_molecules; + + vpr_printf(TIO_MESSAGE_INFO, "Begin packing '%s'.\n", packer_opts->blif_file_name); + + /* determine number of models in the architecture */ + num_models = 0; + cur_model = user_models; + while (cur_model) { + num_models++; + cur_model = cur_model->next; + } + cur_model = library_models; + while (cur_model) { + num_models++; + cur_model = cur_model->next; + } + + + is_clock = alloc_and_load_is_clock(packer_opts->global_clocks); + + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "After removing unused inputs...\n"); + vpr_printf(TIO_MESSAGE_INFO, "\ttotal blocks: %d, total nets: %d, total inputs: %d, total outputs: %d\n", + num_logical_blocks, num_logical_nets, num_p_inputs, num_p_outputs); + + vpr_printf(TIO_MESSAGE_INFO, "Begin prepacking.\n"); + list_of_packing_patterns = alloc_and_load_pack_patterns( + &num_packing_patterns); + list_of_pack_molecules = alloc_and_load_pack_molecules( + list_of_packing_patterns, num_packing_patterns, + &num_pack_molecules); + vpr_printf(TIO_MESSAGE_INFO, "Finish prepacking.\n"); + + if(packer_opts->auto_compute_inter_cluster_net_delay) { + packer_opts->inter_cluster_net_delay = interc_delay; + vpr_printf(TIO_MESSAGE_INFO, "Using inter-cluster delay: %g\n", packer_opts->inter_cluster_net_delay); + } + + /* Uncomment line below if you want a dump of compressed netlist. */ + /* if (getEchoEnabled()){ + echo_input (packer_opts->blif_file_name, packer_opts->lut_size, "packed.echo"); + }else; */ + + if (packer_opts->skip_clustering == FALSE) { + do_clustering(arch, list_of_pack_molecules, num_models, + packer_opts->global_clocks, is_clock, + packer_opts->hill_climbing_flag, packer_opts->output_file, + packer_opts->timing_driven, packer_opts->cluster_seed_type, + packer_opts->alpha, packer_opts->beta, + packer_opts->recompute_timing_after, packer_opts->block_delay, + packer_opts->intra_cluster_net_delay, + packer_opts->inter_cluster_net_delay, packer_opts->aspect, + packer_opts->allow_unrelated_clustering, + packer_opts->allow_early_exit, packer_opts->connection_driven, + packer_opts->packer_algorithm, timing_inf); + } else { + vpr_printf(TIO_MESSAGE_ERROR, "Skip clustering no longer supported.\n"); + exit(1); + } + + free(is_clock); + + /*free list_of_pack_molecules*/ + free_list_of_pack_patterns(list_of_packing_patterns, num_packing_patterns); + + cur_pack_molecule = list_of_pack_molecules; + while (cur_pack_molecule != NULL){ + if (cur_pack_molecule->logical_block_ptrs != NULL) + free(cur_pack_molecule->logical_block_ptrs); + cur_pack_molecule = list_of_pack_molecules->next; + free(list_of_pack_molecules); + list_of_pack_molecules = cur_pack_molecule; + } + + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "Netlist conversion complete.\n"); + vpr_printf(TIO_MESSAGE_INFO, "\n"); +} + +float get_switch_info(short switch_index, float &Tdel_switch, float &R_switch, float &Cout_switch) { + /* Fetches delay, resistance and output capacitance of the switch at switch_index. + Returns the total delay through the switch. Used to calculate inter-cluster net delay. */ + + Tdel_switch = switch_inf[switch_index].Tdel; /* Delay when unloaded */ + R_switch = switch_inf[switch_index].R; + Cout_switch = switch_inf[switch_index].Cout; + + /* The delay through a loaded switch is its intrinsic (unloaded) + delay plus the product of its resistance and output capacitance. */ + return Tdel_switch + R_switch * Cout_switch; +} + +boolean *alloc_and_load_is_clock(boolean global_clocks) { + + /* Looks through all the logical_block to find and mark all the clocks, by setting * + * the corresponding entry in is_clock to true. global_clocks is used * + * only for an error check. */ + + int num_clocks, bnum, clock_net; + boolean * is_clock; + + num_clocks = 0; + + is_clock = (boolean *) my_calloc(num_logical_nets, sizeof(boolean)); + + /* Want to identify all the clock nets. */ + + for (bnum = 0; bnum < num_logical_blocks; bnum++) { + if (logical_block[bnum].type == VPACK_LATCH) { + clock_net = logical_block[bnum].clock_net; + assert(clock_net != OPEN); + if (is_clock[clock_net] == FALSE) { + is_clock[clock_net] = TRUE; + num_clocks++; + } + } else { + if (logical_block[bnum].clock_net != OPEN) { + clock_net = logical_block[bnum].clock_net; + if (is_clock[clock_net] == FALSE) { + is_clock[clock_net] = TRUE; + num_clocks++; + } + } + } + } + + /* If we have multiple clocks and we're supposed to declare them global, * + * print a warning message, since it looks like this circuit may have * + * locally generated clocks. */ + + if (num_clocks > 1 && global_clocks) { + vpr_printf(TIO_MESSAGE_WARNING, "Circuit contains %d clocks. All clocks will be marked global.\n", num_clocks); + } + + return (is_clock); +} + + diff --git a/vpr7_rram/vpr/SRC/pack/pack.h b/vpr7_rram/vpr/SRC/pack/pack.h new file mode 100644 index 000000000..31f0b8364 --- /dev/null +++ b/vpr7_rram/vpr/SRC/pack/pack.h @@ -0,0 +1,2 @@ +void try_pack(INP struct s_packer_opts *packer_opts, INP const t_arch * arch, INP t_model *user_models, INP t_model *library_models, t_timing_inf timing_inf, float interc_delay); +float get_switch_info(short switch_index, float &Tdel_switch, float &R_switch, float &Cout_switch); diff --git a/vpr7_rram/vpr/SRC/pack/pb_type_graph.c b/vpr7_rram/vpr/SRC/pack/pb_type_graph.c new file mode 100755 index 000000000..20be15117 --- /dev/null +++ b/vpr7_rram/vpr/SRC/pack/pb_type_graph.c @@ -0,0 +1,1751 @@ +/** + * Jason Luu + * July 17, 2009 + * pb_graph creates the internal routing edges that join together the different + * pb_types modes within a pb_type + */ + +#include +#include +#include + +#include "util.h" +#include "token.h" +#include "arch_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "vpr_utils.h" +#include "pb_type_graph.h" +#include "pb_type_graph_annotations.h" +#include "cluster_feasibility_filter.h" +#include "power.h" + +/* variable global to this section that indexes each pb graph pin within a cluster */ +static int pin_count_in_cluster; +static struct s_linked_vptr *edges_head; +static struct s_linked_vptr *num_edges_head; + +/* TODO: Software engineering decision needed: Move this file to libarch? + + */ + +static int check_pb_graph(void); +static void alloc_and_load_pb_graph(INOUTP t_pb_graph_node *pb_graph_node, + INP t_pb_graph_node *parent_pb_graph_node, INP t_pb_type *pb_type, + INP int index, boolean load_power_structures); + +static void alloc_and_load_mode_interconnect( + INOUTP t_pb_graph_node *pb_graph_parent_node, + INOUTP t_pb_graph_node **pb_graph_children_nodes, + INP const t_mode * mode, boolean load_power_structures); + +static boolean realloc_and_load_pb_graph_pin_ptrs_at_var(INP int line_num, + INP const t_pb_graph_node *pb_graph_parent_node, + INP t_pb_graph_node **pb_graph_children_nodes, + INP boolean interconnect_error_check, INP boolean is_input_to_interc, + INP const t_token *tokens, INOUTP int *token_index, + INOUTP int *num_pins, OUTP t_pb_graph_pin ***pb_graph_pins); + +static t_pb_graph_pin * get_pb_graph_pin_from_name(INP const char * port_name, + INP const t_pb_graph_node * pb, INP int pin); + +static void alloc_and_load_complete_interc_edges( + INP t_interconnect * interconnect, + INOUTP t_pb_graph_pin *** input_pb_graph_node_pin_ptrs, + INP int num_input_sets, INP int *num_input_ptrs, + INOUTP t_pb_graph_pin *** output_pb_graph_node_pin_ptrs, + INP int num_output_sets, INP int *num_output_ptrs); + +static void alloc_and_load_direct_interc_edges( + INP t_interconnect * interconnect, + INOUTP t_pb_graph_pin *** input_pb_graph_node_pin_ptrs, + INP int num_input_sets, INP int *num_input_ptrs, + INOUTP t_pb_graph_pin *** output_pb_graph_node_pin_ptrs, + INP int num_output_sets, INP int *num_output_ptrs); + +static void alloc_and_load_mux_interc_edges(INP t_interconnect * interconnect, + INOUTP t_pb_graph_pin *** input_pb_graph_node_pin_ptrs, + INP int num_input_sets, INP int *num_input_ptrs, + INOUTP t_pb_graph_pin *** output_pb_graph_node_pin_ptrs, + INP int num_output_sets, INP int *num_output_ptrs); + +static void alloc_and_load_pin_locations_from_pb_graph(t_type_descriptor *type); + +static void echo_pb_rec(INP const t_pb_graph_node *pb, INP int level, + INP FILE * fp); +static void echo_pb_pins(INP t_pb_graph_pin **pb_graph_pins, INP int num_ports, + INP int level, INP FILE * fp); +static void free_pb_graph(INOUTP t_pb_graph_node *pb_graph_node); + +static void alloc_and_load_interconnect_pins(t_interconnect_pins * interc_pins, + t_interconnect * interconnect, t_pb_graph_pin *** input_pins, + int num_input_sets, int * num_input_pins, + t_pb_graph_pin *** output_pins, int num_output_sets, + int * num_output_pins); + +/** + * Allocate memory into types and load the pb graph with interconnect edges + */ +void alloc_and_load_all_pb_graphs(boolean load_power_structures) { + int i, errors; + edges_head = NULL; + num_edges_head = NULL; + for (i = 0; i < num_types; i++) { + if (type_descriptors[i].pb_type) { + pin_count_in_cluster = 0; + type_descriptors[i].pb_graph_head = (t_pb_graph_node*) my_calloc(1, + sizeof(t_pb_graph_node)); + alloc_and_load_pb_graph(type_descriptors[i].pb_graph_head, NULL, + type_descriptors[i].pb_type, 0, load_power_structures); + type_descriptors[i].pb_graph_head->total_pb_pins = + pin_count_in_cluster; + alloc_and_load_pin_locations_from_pb_graph(&type_descriptors[i]); + load_pin_classes_in_pb_graph_head( + type_descriptors[i].pb_graph_head); + } else { + type_descriptors[i].pb_graph_head = NULL; + assert(&type_descriptors[i] == EMPTY_TYPE); + } + } + + errors = check_pb_graph(); + if (errors > 0) { + vpr_printf(TIO_MESSAGE_ERROR, "in pb graph"); + exit(1); + } + for (i = 0; i < num_types; i++) { + if (type_descriptors[i].pb_type) { + load_pb_graph_pin_to_pin_annotations( + type_descriptors[i].pb_graph_head); + } + } +} + +/** + * Free pb graph + */ +void free_all_pb_graph_nodes(void) { + int i; + for (i = 0; i < num_types; i++) { + if (type_descriptors[i].pb_type) { + pin_count_in_cluster = 0; + if (type_descriptors[i].pb_graph_head) { + free_pb_graph(type_descriptors[i].pb_graph_head); + free(type_descriptors[i].pb_graph_head); + } + } + } +} + +/** + * Print out the pb_type graph + */ +void echo_pb_graph(char * filename) { + FILE *fp; + int i; + + fp = my_fopen(filename, "w", 0); + + fprintf(fp, "Physical Blocks Graph\n"); + fprintf(fp, "--------------------------------------------\n\n"); + + for (i = 0; i < num_types; i++) { + fprintf(fp, "type %s\n", type_descriptors[i].name); + if (type_descriptors[i].pb_graph_head) + echo_pb_rec(type_descriptors[i].pb_graph_head, 1, fp); + } + + fclose(fp); +} + +/** + * check pb_type graph and return the number of errors + */ +static int check_pb_graph(void) { + int num_errors; + /* TODO: Error checks to do + 1. All pin and edge connections are bidirectional and match each other + 2. All pb_type names are unique in a namespace + 3. All ports are unique in a pb_type + 4. Number of pb of a pb_type in graph is the same as requested number + 5. All pins are connected to edges + */ + num_errors = 0; + + return num_errors; +} + +static void alloc_and_load_pb_graph(INOUTP t_pb_graph_node *pb_graph_node, + INP t_pb_graph_node *parent_pb_graph_node, INP t_pb_type *pb_type, + INP int index, boolean load_power_structures) { + int i, j, k, i_input, i_output, i_clockport; + + pb_graph_node->placement_index = index; + pb_graph_node->pb_type = pb_type; + pb_graph_node->parent_pb_graph_node = parent_pb_graph_node; + + pb_graph_node->num_input_ports = 0; + pb_graph_node->num_output_ports = 0; + pb_graph_node->num_clock_ports = 0; + + /* Generate ports for pb graph node */ + for (i = 0; i < pb_type->num_ports; i++) { + if (pb_type->ports[i].type == IN_PORT && !pb_type->ports[i].is_clock) { + pb_graph_node->num_input_ports++; + } else if (pb_type->ports[i].type == OUT_PORT) { + assert(!pb_type->ports[i].is_clock); + pb_graph_node->num_output_ports++; + } else { + assert( + pb_type->ports[i].is_clock && pb_type->ports[i].type == IN_PORT); + pb_graph_node->num_clock_ports++; + } + } + + pb_graph_node->num_input_pins = (int*) my_calloc( + pb_graph_node->num_input_ports, sizeof(int)); + pb_graph_node->num_output_pins = (int*) my_calloc( + pb_graph_node->num_output_ports, sizeof(int)); + pb_graph_node->num_clock_pins = (int*) my_calloc( + pb_graph_node->num_clock_ports, sizeof(int)); + + pb_graph_node->input_pins = (t_pb_graph_pin**) my_calloc( + pb_graph_node->num_input_ports, sizeof(t_pb_graph_pin*)); + pb_graph_node->output_pins = (t_pb_graph_pin**) my_calloc( + pb_graph_node->num_output_ports, sizeof(t_pb_graph_pin*)); + pb_graph_node->clock_pins = (t_pb_graph_pin**) my_calloc( + pb_graph_node->num_clock_ports, sizeof(t_pb_graph_pin*)); + + i_input = i_output = i_clockport = 0; + for (i = 0; i < pb_type->num_ports; i++) { + if (pb_type->ports[i].model_port) { + assert(pb_type->num_modes == 0); + } else { + assert(pb_type->num_modes != 0 || pb_type->ports[i].is_clock); + } + if (pb_type->ports[i].type == IN_PORT && !pb_type->ports[i].is_clock) { + pb_graph_node->input_pins[i_input] = (t_pb_graph_pin*) my_calloc( + pb_type->ports[i].num_pins, sizeof(t_pb_graph_pin)); + pb_graph_node->num_input_pins[i_input] = pb_type->ports[i].num_pins; + for (j = 0; j < pb_type->ports[i].num_pins; j++) { + pb_graph_node->input_pins[i_input][j].input_edges = NULL; + pb_graph_node->input_pins[i_input][j].num_input_edges = 0; + pb_graph_node->input_pins[i_input][j].output_edges = NULL; + pb_graph_node->input_pins[i_input][j].num_output_edges = 0; + pb_graph_node->input_pins[i_input][j].pin_number = j; + pb_graph_node->input_pins[i_input][j].port = &pb_type->ports[i]; + pb_graph_node->input_pins[i_input][j].parent_node = + pb_graph_node; + pb_graph_node->input_pins[i_input][j].pin_count_in_cluster = + pin_count_in_cluster; + pb_graph_node->input_pins[i_input][j].type = PB_PIN_NORMAL; + if (pb_graph_node->pb_type->blif_model != NULL ) { + if (strcmp(pb_graph_node->pb_type->blif_model, ".output") + == 0) { + pb_graph_node->input_pins[i_input][j].type = + PB_PIN_OUTPAD; + } else if (pb_graph_node->num_clock_ports != 0) { + pb_graph_node->input_pins[i_input][j].type = + PB_PIN_SEQUENTIAL; + } else { + pb_graph_node->input_pins[i_input][j].type = + PB_PIN_TERMINAL; + } + } + pin_count_in_cluster++; + } + i_input++; + } else if (pb_type->ports[i].type == OUT_PORT) { + pb_graph_node->output_pins[i_output] = (t_pb_graph_pin*) my_calloc( + pb_type->ports[i].num_pins, sizeof(t_pb_graph_pin)); + pb_graph_node->num_output_pins[i_output] = + pb_type->ports[i].num_pins; + for (j = 0; j < pb_type->ports[i].num_pins; j++) { + pb_graph_node->output_pins[i_output][j].input_edges = NULL; + pb_graph_node->output_pins[i_output][j].num_input_edges = 0; + pb_graph_node->output_pins[i_output][j].output_edges = NULL; + pb_graph_node->output_pins[i_output][j].num_output_edges = 0; + pb_graph_node->output_pins[i_output][j].pin_number = j; + pb_graph_node->output_pins[i_output][j].port = + &pb_type->ports[i]; + pb_graph_node->output_pins[i_output][j].parent_node = + pb_graph_node; + pb_graph_node->output_pins[i_output][j].pin_count_in_cluster = + pin_count_in_cluster; + pb_graph_node->output_pins[i_output][j].type = PB_PIN_NORMAL; + if (pb_graph_node->pb_type->blif_model != NULL ) { + if (strcmp(pb_graph_node->pb_type->blif_model, ".input") + == 0) { + pb_graph_node->output_pins[i_output][j].type = + PB_PIN_INPAD; + } else if (pb_graph_node->num_clock_ports != 0) { + pb_graph_node->output_pins[i_output][j].type = + PB_PIN_SEQUENTIAL; + } else { + pb_graph_node->output_pins[i_output][j].type = + PB_PIN_TERMINAL; + } + } + pin_count_in_cluster++; + } + i_output++; + } else { + assert( + pb_type->ports[i].is_clock && pb_type->ports[i].type == IN_PORT); + pb_graph_node->clock_pins[i_clockport] = + (t_pb_graph_pin*) my_calloc(pb_type->ports[i].num_pins, + sizeof(t_pb_graph_pin)); + pb_graph_node->num_clock_pins[i_clockport] = + pb_type->ports[i].num_pins; + for (j = 0; j < pb_type->ports[i].num_pins; j++) { + pb_graph_node->clock_pins[i_clockport][j].input_edges = NULL; + pb_graph_node->clock_pins[i_clockport][j].num_input_edges = 0; + pb_graph_node->clock_pins[i_clockport][j].output_edges = NULL; + pb_graph_node->clock_pins[i_clockport][j].num_output_edges = 0; + pb_graph_node->clock_pins[i_clockport][j].pin_number = j; + pb_graph_node->clock_pins[i_clockport][j].port = + &pb_type->ports[i]; + pb_graph_node->clock_pins[i_clockport][j].parent_node = + pb_graph_node; + pb_graph_node->clock_pins[i_clockport][j].pin_count_in_cluster = + pin_count_in_cluster; + pb_graph_node->clock_pins[i_clockport][j].type = PB_PIN_NORMAL; + if (pb_graph_node->pb_type->blif_model != NULL ) { + pb_graph_node->clock_pins[i_clockport][j].type = + PB_PIN_CLOCK; + } + pin_count_in_cluster++; + } + i_clockport++; + } + } + + /* Power */ + if (load_power_structures) { + pb_graph_node->pb_node_power = (t_pb_graph_node_power*) my_calloc(1, + sizeof(t_pb_graph_node_power)); + pb_graph_node->pb_node_power->transistor_cnt_buffers = 0.; + pb_graph_node->pb_node_power->transistor_cnt_interc = 0.; + pb_graph_node->pb_node_power->transistor_cnt_pb_children = 0.; + } + + /* Allocate and load child nodes for each mode and create interconnect in each mode */ + pb_graph_node->child_pb_graph_nodes = (t_pb_graph_node***) my_calloc( + pb_type->num_modes, sizeof(t_pb_graph_node **)); + for (i = 0; i < pb_type->num_modes; i++) { + pb_graph_node->child_pb_graph_nodes[i] = (t_pb_graph_node**) my_calloc( + pb_type->modes[i].num_pb_type_children, + sizeof(t_pb_graph_node *)); + for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { + pb_graph_node->child_pb_graph_nodes[i][j] = + (t_pb_graph_node*) my_calloc( + pb_type->modes[i].pb_type_children[j].num_pb, + sizeof(t_pb_graph_node)); + for (k = 0; k < pb_type->modes[i].pb_type_children[j].num_pb; k++) { + alloc_and_load_pb_graph( + &pb_graph_node->child_pb_graph_nodes[i][j][k], + pb_graph_node, &pb_type->modes[i].pb_type_children[j], + k, load_power_structures); + } + } + } + + pb_graph_node->interconnect_pins = (t_interconnect_pins**) my_calloc( + pb_type->num_modes, sizeof(t_interconnect_pins *)); + for (i = 0; i < pb_type->num_modes; i++) { + /* Create interconnect for mode */ + alloc_and_load_mode_interconnect(pb_graph_node, + pb_graph_node->child_pb_graph_nodes[i], &pb_type->modes[i], + load_power_structures); + } +} + +static void free_pb_graph(INOUTP t_pb_graph_node *pb_graph_node) { + int i, j, k; + const t_pb_type *pb_type; + struct s_linked_vptr *cur, *cur_num; + t_pb_graph_edge *edges; + + pb_type = pb_graph_node->pb_type; + + /*free all lists of connectable input pin pointer of pb_graph_node and it's children*/ + /*free_list_of_connectable_input_pin_ptrs (pb_graph_node);*/ + + /* Free ports for pb graph node */ + for (i = 0; i < pb_graph_node->num_input_ports; i++) { + for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { + if (pb_graph_node->input_pins[i][j].pin_timing) + free(pb_graph_node->input_pins[i][j].pin_timing); + if (pb_graph_node->input_pins[i][j].pin_timing_del_max) + free(pb_graph_node->input_pins[i][j].pin_timing_del_max); + if (pb_graph_node->input_pins[i][j].input_edges) + free(pb_graph_node->input_pins[i][j].input_edges); + if (pb_graph_node->input_pins[i][j].output_edges) + free(pb_graph_node->input_pins[i][j].output_edges); + if (pb_graph_node->input_pins[i][j].parent_pin_class) + free(pb_graph_node->input_pins[i][j].parent_pin_class); + } + free(pb_graph_node->input_pins[i]); + } + for (i = 0; i < pb_graph_node->num_output_ports; i++) { + for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { + if (pb_graph_node->output_pins[i][j].pin_timing) + free(pb_graph_node->output_pins[i][j].pin_timing); + if (pb_graph_node->output_pins[i][j].pin_timing_del_max) + free(pb_graph_node->output_pins[i][j].pin_timing_del_max); + if (pb_graph_node->output_pins[i][j].input_edges) + free(pb_graph_node->output_pins[i][j].input_edges); + if (pb_graph_node->output_pins[i][j].output_edges) + free(pb_graph_node->output_pins[i][j].output_edges); + if (pb_graph_node->output_pins[i][j].parent_pin_class) + free(pb_graph_node->output_pins[i][j].parent_pin_class); + + if (pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs) { + for (k = 0; k < pb_graph_node->pb_type->depth; k++) { + if (pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs[k]) { + free( + pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs[k]); + } + } + free( + pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs); + } + + if (pb_graph_node->output_pins[i][j].num_connectable_primtive_input_pins) + free( + pb_graph_node->output_pins[i][j].num_connectable_primtive_input_pins); + } + free(pb_graph_node->output_pins[i]); + } + for (i = 0; i < pb_graph_node->num_clock_ports; i++) { + for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { + if (pb_graph_node->clock_pins[i][j].pin_timing) + free(pb_graph_node->clock_pins[i][j].pin_timing); + if (pb_graph_node->clock_pins[i][j].pin_timing_del_max) + free(pb_graph_node->clock_pins[i][j].pin_timing_del_max); + if (pb_graph_node->clock_pins[i][j].input_edges) + free(pb_graph_node->clock_pins[i][j].input_edges); + if (pb_graph_node->clock_pins[i][j].output_edges) + free(pb_graph_node->clock_pins[i][j].output_edges); + if (pb_graph_node->clock_pins[i][j].parent_pin_class) + free(pb_graph_node->clock_pins[i][j].parent_pin_class); + } + free(pb_graph_node->clock_pins[i]); + } + + + for(i = 0; i < pb_graph_node->pb_type->num_modes; i++) { + free(pb_graph_node->interconnect_pins[i]); + } + free(pb_graph_node->interconnect_pins); + + free(pb_graph_node->input_pins); + free(pb_graph_node->output_pins); + free(pb_graph_node->clock_pins); + + free(pb_graph_node->num_input_pins); + free(pb_graph_node->num_output_pins); + free(pb_graph_node->num_clock_pins); + + free(pb_graph_node->input_pin_class_size); + free(pb_graph_node->output_pin_class_size); + + for (i = 0; i < pb_type->num_modes; i++) { + for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { + for (k = 0; k < pb_type->modes[i].pb_type_children[j].num_pb; k++) { + free_pb_graph(&pb_graph_node->child_pb_graph_nodes[i][j][k]); + } + free(pb_graph_node->child_pb_graph_nodes[i][j]); + } + free(pb_graph_node->child_pb_graph_nodes[i]); + } + free(pb_graph_node->child_pb_graph_nodes); + + while (edges_head != NULL ) { + cur = edges_head; + cur_num = num_edges_head; + edges = (t_pb_graph_edge*) cur->data_vptr; + for (i = 0; i < (long) cur_num->data_vptr; i++) { + free(edges[i].input_pins); + free(edges[i].output_pins); + if (edges[i].pack_pattern_indices) { + free(edges[i].pack_pattern_indices); + } + if (edges[i].pack_pattern_names) { + free(edges[i].pack_pattern_names); + } + } + edges_head = edges_head->next; + num_edges_head = num_edges_head->next; + free(edges); + free(cur_num); + free(cur); + } +} + +static void alloc_and_load_interconnect_pins(t_interconnect_pins * interc_pins, + t_interconnect * interconnect, t_pb_graph_pin *** input_pins, + int num_input_sets, int * num_input_pins, + t_pb_graph_pin *** output_pins, int num_output_sets, + int * num_output_pins) { + int set_idx; + int pin_idx; + int port_idx; + int num_ports; + + interc_pins->interconnect = interconnect; + + switch (interconnect->type) { + case DIRECT_INTERC: + assert(num_output_sets == 1); + /* Fall through here */ + + case MUX_INTERC: + if (!interconnect->interconnect_power->port_info_initialized) { + for (set_idx = 0; set_idx < num_input_sets; set_idx++) { + if (num_input_pins[set_idx] != num_output_pins[0]) { + assert(num_input_pins[set_idx] == num_output_pins[0]); + } + } + interconnect->interconnect_power->num_pins_per_port = + num_input_pins[0]; + interconnect->interconnect_power->num_input_ports = num_input_sets; + interconnect->interconnect_power->num_output_ports = 1; + + /* No longer used - mux architectures are not configurable, the + * default is always assumed + if (interconnect->mux_arch) { + interconnect->mux_arch->num_inputs = + interconnect->num_input_ports; + + mux_arch_fix_levels(interconnect->mux_arch); + + interconnect->mux_arch->mux_graph_head = + alloc_and_load_mux_graph(interconnect->num_input_ports, + interconnect->mux_arch->levels); + } + */ + + interconnect->interconnect_power->port_info_initialized = TRUE; + } + + interc_pins->input_pins = (t_pb_graph_pin***) my_calloc(num_input_sets, + sizeof(t_pb_graph_pin**)); + for (set_idx = 0; set_idx < num_input_sets; set_idx++) { + interc_pins->input_pins[set_idx] = (t_pb_graph_pin**) my_calloc( + interconnect->interconnect_power->num_pins_per_port, + sizeof(t_pb_graph_pin*)); + } + + interc_pins->output_pins = (t_pb_graph_pin***) my_calloc(1, + sizeof(t_pb_graph_pin**)); + interc_pins->output_pins[0] = (t_pb_graph_pin**) my_calloc( + interconnect->interconnect_power->num_pins_per_port, + sizeof(t_pb_graph_pin*)); + + for (pin_idx = 0; + pin_idx < interconnect->interconnect_power->num_pins_per_port; + pin_idx++) { + for (set_idx = 0; set_idx < num_input_sets; set_idx++) { + interc_pins->input_pins[set_idx][pin_idx] = + input_pins[set_idx][pin_idx]; + } + interc_pins->output_pins[0][pin_idx] = output_pins[0][pin_idx]; + } + + break; + case COMPLETE_INTERC: + + if (!interconnect->interconnect_power->port_info_initialized) { + /* The code does not support bus-based crossbars, so all pins from all input sets + * connect to all pins from all output sets */ + interconnect->interconnect_power->num_pins_per_port = 1; + + num_ports = 0; + for (set_idx = 0; set_idx < num_input_sets; set_idx++) { + num_ports += num_input_pins[set_idx]; + } + interconnect->interconnect_power->num_input_ports = num_ports; + + num_ports = 0; + for (set_idx = 0; set_idx < num_output_sets; set_idx++) { + num_ports += num_output_pins[set_idx]; + } + interconnect->interconnect_power->num_output_ports = num_ports; + + /* + if (interconnect->mux_arch) { + interconnect->mux_arch->num_inputs = + interconnect->num_input_ports; + + mux_arch_fix_levels(interconnect->mux_arch); + + interconnect->mux_arch->mux_graph_head = + alloc_and_load_mux_graph(interconnect->num_input_ports, + interconnect->mux_arch->levels); + }*/ + + interconnect->interconnect_power->port_info_initialized = TRUE; + } + + /* Input Pins */ + interc_pins->input_pins = (t_pb_graph_pin ***) my_calloc( + interconnect->interconnect_power->num_input_ports, + sizeof(t_pb_graph_pin**)); + for (port_idx = 0; + port_idx < interconnect->interconnect_power->num_input_ports; + port_idx++) { + interc_pins->input_pins[port_idx] = (t_pb_graph_pin**) my_calloc( + interconnect->interconnect_power->num_pins_per_port, + sizeof(t_pb_graph_pin*)); + } + num_ports = 0; + for (set_idx = 0; set_idx < num_input_sets; set_idx++) { + for (pin_idx = 0; pin_idx < num_input_pins[set_idx]; pin_idx++) { + interc_pins->input_pins[num_ports++][0] = + input_pins[set_idx][pin_idx]; + } + } + + /* Output Pins */ + interc_pins->output_pins = (t_pb_graph_pin ***) my_calloc( + interconnect->interconnect_power->num_output_ports, + sizeof(t_pb_graph_pin**)); + for (port_idx = 0; + port_idx < interconnect->interconnect_power->num_output_ports; + port_idx++) { + interc_pins->output_pins[port_idx] = (t_pb_graph_pin **) my_calloc( + interconnect->interconnect_power->num_pins_per_port, + sizeof(t_pb_graph_pin*)); + } + num_ports = 0; + for (set_idx = 0; set_idx < num_output_sets; set_idx++) { + for (pin_idx = 0; pin_idx < num_output_pins[set_idx]; pin_idx++) { + interc_pins->output_pins[num_ports++][0] = + output_pins[set_idx][pin_idx]; + } + } + + break; + } + +} + +/** + * Generate interconnect associated with a mode of operation + * pb_graph_parent_node: parent node of pb in mode + * pb_graph_children_nodes: [0..num_pb_type_in_mode-1][0..num_pb] + * mode: mode of operation + */ +static void alloc_and_load_mode_interconnect( + INOUTP t_pb_graph_node *pb_graph_parent_node, + INOUTP t_pb_graph_node **pb_graph_children_nodes, + INP const t_mode * mode, boolean load_power_structures) { + int i, j; + int *num_input_pb_graph_node_pins, *num_output_pb_graph_node_pins; /* number of pins in a set [0..num_sets-1] */ + int num_input_pb_graph_node_sets, num_output_pb_graph_node_sets; + t_pb_graph_pin *** input_pb_graph_node_pins, ***output_pb_graph_node_pins; + + /* Xifan TANG: Spice Model Support, count the fan-in and fan-out, num_mux in the interconnection*/ + int fan_in, fan_out, num_mux; + /* END */ + + if (load_power_structures) { + assert(pb_graph_parent_node->interconnect_pins[mode->index] == NULL); + pb_graph_parent_node->interconnect_pins[mode->index] = + (t_interconnect_pins*) my_calloc(mode->num_interconnect, + sizeof(t_interconnect_pins)); + } + + for (i = 0; i < mode->num_interconnect; i++) { + /* determine the interconnect input and output pins */ + input_pb_graph_node_pins = alloc_and_load_port_pin_ptrs_from_string( + mode->interconnect[i].line_num, pb_graph_parent_node, + pb_graph_children_nodes, mode->interconnect[i].input_string, + &num_input_pb_graph_node_pins, &num_input_pb_graph_node_sets, + TRUE, TRUE); + + output_pb_graph_node_pins = alloc_and_load_port_pin_ptrs_from_string( + mode->interconnect[i].line_num, pb_graph_parent_node, + pb_graph_children_nodes, mode->interconnect[i].output_string, + &num_output_pb_graph_node_pins, &num_output_pb_graph_node_sets, + FALSE, TRUE); + + if (load_power_structures) { + alloc_and_load_interconnect_pins( + &pb_graph_parent_node->interconnect_pins[mode->index][i], + &mode->interconnect[i], input_pb_graph_node_pins, + num_input_pb_graph_node_sets, num_input_pb_graph_node_pins, + output_pb_graph_node_pins, num_output_pb_graph_node_sets, + num_output_pb_graph_node_pins); + } + + /* process the interconnect based on its type */ + switch (mode->interconnect[i].type) { + + case COMPLETE_INTERC: + alloc_and_load_complete_interc_edges(&mode->interconnect[i], + input_pb_graph_node_pins, num_input_pb_graph_node_sets, + num_input_pb_graph_node_pins, output_pb_graph_node_pins, + num_output_pb_graph_node_sets, + num_output_pb_graph_node_pins); + + break; + + case DIRECT_INTERC: + alloc_and_load_direct_interc_edges(&mode->interconnect[i], + input_pb_graph_node_pins, num_input_pb_graph_node_sets, + num_input_pb_graph_node_pins, output_pb_graph_node_pins, + num_output_pb_graph_node_sets, + num_output_pb_graph_node_pins); + break; + + case MUX_INTERC: + alloc_and_load_mux_interc_edges(&mode->interconnect[i], + input_pb_graph_node_pins, num_input_pb_graph_node_sets, + num_input_pb_graph_node_pins, output_pb_graph_node_pins, + num_output_pb_graph_node_sets, + num_output_pb_graph_node_pins); + + break; + + default: + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] Unknown interconnect %d for mode %s in pb_type %s, input %s, output %s\n", + mode->interconnect[i].line_num, mode->interconnect[i].type, + mode->name, pb_graph_parent_node->pb_type->name, + mode->interconnect[i].input_string, + mode->interconnect[i].output_string); + exit(1); + } + /* Xifan TANG: count the fan-in and fan-out of this interconnect, + * And infer the number of multiplexer + */ + fan_in = 0; + /* Count fan-in */ + for (j = 0; j < num_input_pb_graph_node_sets; j++) { + fan_in += num_input_pb_graph_node_pins[j]; + } + mode->interconnect[i].fan_in = fan_in; + /* Count fan-out */ + fan_out = 0; + for (j = 0; j < num_output_pb_graph_node_sets; j++) { + fan_out += num_output_pb_graph_node_pins[j]; + } + mode->interconnect[i].fan_out = fan_out; + /* Check if this is a legal interconnect*/ + if (1 > mode->interconnect[i].fan_in) { + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] fan_in is 0!(Interconnect %d for mode %s in pb_type %s, input %s, output %s)\n", + mode->interconnect[i].line_num, mode->interconnect[i].type, + mode->name, pb_graph_parent_node->pb_type->name, + mode->interconnect[i].input_string, + mode->interconnect[i].output_string); + exit(1); + } + /* infer the number of mux*/ + num_mux = 0; + switch (mode->interconnect[i].type) { + case COMPLETE_INTERC: + if (1 == mode->interconnect[i].fan_in) { + num_mux = 0; + } else { + num_mux = mode->interconnect[i].fan_out; + } + break; + case MUX_INTERC: + num_mux = mode->interconnect[i].fan_out; + break; + case DIRECT_INTERC: + num_mux = 0; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] Unknown interconnect %d for mode %s in pb_type %s, input %s, output %s\n", + mode->interconnect[i].line_num, mode->interconnect[i].type, + mode->name, pb_graph_parent_node->pb_type->name, + mode->interconnect[i].input_string, + mode->interconnect[i].output_string); + exit(1); + } + mode->interconnect[i].num_mux = num_mux; + /* END */ + + for (j = 0; j < num_input_pb_graph_node_sets; j++) { + free(input_pb_graph_node_pins[j]); + } + free(input_pb_graph_node_pins); + for (j = 0; j < num_output_pb_graph_node_sets; j++) { + free(output_pb_graph_node_pins[j]); + } + free(output_pb_graph_node_pins); + free(num_input_pb_graph_node_pins); + free(num_output_pb_graph_node_pins); + } +} + +/** + * creates an array of pointers to the pb graph node pins in order from the port string + * returns t_pb_graph_pin ptr indexed by [0..num_sets_in_port - 1][0..num_ptrs - 1] + */ +t_pb_graph_pin *** alloc_and_load_port_pin_ptrs_from_string(INP int line_num, + INP const t_pb_graph_node *pb_graph_parent_node, + INP t_pb_graph_node **pb_graph_children_nodes, + INP const char * port_string, OUTP int ** num_ptrs, OUTP int * num_sets, + INP boolean is_input_to_interc, INP boolean interconnect_error_check) { + t_token * tokens; + int num_tokens, curr_set; + int i; + boolean in_squig_bracket, success; + + t_pb_graph_pin ***pb_graph_pins; + + num_tokens = 0; + tokens = GetTokensFromString(port_string, &num_tokens); + *num_sets = 0; + in_squig_bracket = FALSE; + + /* count the number of sets available */ + for (i = 0; i < num_tokens; i++) { + assert(tokens[i].type != TOKEN_NULL); + if (tokens[i].type == TOKEN_OPEN_SQUIG_BRACKET) { + if (in_squig_bracket) { + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] { inside { in port %s\n", line_num, + port_string); + exit(1); + } + in_squig_bracket = TRUE; + } else if (tokens[i].type == TOKEN_CLOSE_SQUIG_BRACKET) { + if (!in_squig_bracket) { + (*num_sets)++; + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] No matching '{' for '}' in port %s\n", + line_num, port_string); + exit(1); + } + in_squig_bracket = FALSE; + } else if (tokens[i].type == TOKEN_DOT) { + if (!in_squig_bracket) { + (*num_sets)++; + } + } + } + + if (in_squig_bracket) { + (*num_sets)++; + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] No matching '{' for '}' in port %s\n", line_num, + port_string); + exit(1); + } + + pb_graph_pins = (t_pb_graph_pin***) my_calloc(*num_sets, + sizeof(t_pb_graph_pin**)); + *num_ptrs = (int*) my_calloc(*num_sets, sizeof(int)); + + curr_set = 0; + for (i = 0; i < num_tokens; i++) { + assert(tokens[i].type != TOKEN_NULL); + if (tokens[i].type == TOKEN_OPEN_SQUIG_BRACKET) { + if (in_squig_bracket) { + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] { inside { in port %s\n", line_num, + port_string); + exit(1); + } + in_squig_bracket = TRUE; + } else if (tokens[i].type == TOKEN_CLOSE_SQUIG_BRACKET) { + if ((*num_ptrs)[curr_set] == 0) { + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] No data contained in {} in port %s\n", + line_num, port_string); + exit(1); + } + if (!in_squig_bracket) { + curr_set++; + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] No matching '{' for '}' in port %s\n", + line_num, port_string); + exit(1); + } + in_squig_bracket = FALSE; + } else if (tokens[i].type == TOKEN_STRING) { + + success = realloc_and_load_pb_graph_pin_ptrs_at_var(line_num, + pb_graph_parent_node, pb_graph_children_nodes, + interconnect_error_check, is_input_to_interc, tokens, &i, + &((*num_ptrs)[curr_set]), &pb_graph_pins[curr_set]); + + if (!success) { + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] syntax error processing port string %s\n", + line_num, port_string); + exit(1); + } + + if (!in_squig_bracket) { + curr_set++; + } + } + } + assert(curr_set == *num_sets); + freeTokens(tokens, num_tokens); + return pb_graph_pins; +} + +/** + * Creates edges to connect all input pins to output pins + */ +static void alloc_and_load_complete_interc_edges( + INP t_interconnect *interconnect, + INOUTP t_pb_graph_pin *** input_pb_graph_node_pin_ptrs, + INP int num_input_sets, INP int *num_input_ptrs, + INOUTP t_pb_graph_pin *** output_pb_graph_node_pin_ptrs, + INP int num_output_sets, INP int *num_output_ptrs) { + int i_inset, i_outset, i_inpin, i_outpin; + int in_count, out_count; + t_pb_graph_edge *edges; + int i_edge; + struct s_linked_vptr *cur; + + assert(interconnect->infer_annotations == FALSE); + + /* Allocate memory for edges, and reallocate more memory for pins connecting to those edges */ + in_count = out_count = 0; + + for (i_inset = 0; i_inset < num_input_sets; i_inset++) { + in_count += num_input_ptrs[i_inset]; + } + for (i_outset = 0; i_outset < num_output_sets; i_outset++) { + out_count += num_output_ptrs[i_outset]; + } + + edges = (t_pb_graph_edge*) my_calloc(in_count * out_count, + sizeof(t_pb_graph_edge)); + cur = (struct s_linked_vptr*) my_malloc(sizeof(struct s_linked_vptr)); + cur->next = edges_head; + edges_head = cur; + cur->data_vptr = (void *) edges; + cur = (struct s_linked_vptr*) my_malloc(sizeof(struct s_linked_vptr)); + cur->next = num_edges_head; + num_edges_head = cur; + cur->data_vptr = (void *) ((long) in_count * out_count); + + for (i_inset = 0; i_inset < num_input_sets; i_inset++) { + for (i_inpin = 0; i_inpin < num_input_ptrs[i_inset]; i_inpin++) { + input_pb_graph_node_pin_ptrs[i_inset][i_inpin]->output_edges = + (t_pb_graph_edge **) my_realloc( + input_pb_graph_node_pin_ptrs[i_inset][i_inpin]->output_edges, + (input_pb_graph_node_pin_ptrs[i_inset][i_inpin]->num_output_edges + + out_count) * sizeof(t_pb_graph_edge *)); + } + } + + for (i_outset = 0; i_outset < num_output_sets; i_outset++) { + for (i_outpin = 0; i_outpin < num_output_ptrs[i_outset]; i_outpin++) { + output_pb_graph_node_pin_ptrs[i_outset][i_outpin]->input_edges = + (t_pb_graph_edge **) my_realloc( + output_pb_graph_node_pin_ptrs[i_outset][i_outpin]->input_edges, + (output_pb_graph_node_pin_ptrs[i_outset][i_outpin]->num_input_edges + + in_count) * sizeof(t_pb_graph_edge *)); + } + } + + i_edge = 0; + + /* Load connections between pins and record these updates in the edges */ + for (i_inset = 0; i_inset < num_input_sets; i_inset++) { + for (i_inpin = 0; i_inpin < num_input_ptrs[i_inset]; i_inpin++) { + for (i_outset = 0; i_outset < num_output_sets; i_outset++) { + for (i_outpin = 0; i_outpin < num_output_ptrs[i_outset]; + i_outpin++) { + + input_pb_graph_node_pin_ptrs[i_inset][i_inpin]->output_edges[input_pb_graph_node_pin_ptrs[i_inset][i_inpin]->num_output_edges] = + &edges[i_edge]; + input_pb_graph_node_pin_ptrs[i_inset][i_inpin]->num_output_edges++; + output_pb_graph_node_pin_ptrs[i_outset][i_outpin]->input_edges[output_pb_graph_node_pin_ptrs[i_outset][i_outpin]->num_input_edges] = + &edges[i_edge]; + output_pb_graph_node_pin_ptrs[i_outset][i_outpin]->num_input_edges++; + + edges[i_edge].num_input_pins = 1; + edges[i_edge].input_pins = (t_pb_graph_pin **) my_malloc( + sizeof(t_pb_graph_pin *)); + edges[i_edge].input_pins[0] = + input_pb_graph_node_pin_ptrs[i_inset][i_inpin]; + edges[i_edge].num_output_pins = 1; + edges[i_edge].output_pins = (t_pb_graph_pin **) my_malloc( + sizeof(t_pb_graph_pin *)); + edges[i_edge].output_pins[0] = + output_pb_graph_node_pin_ptrs[i_outset][i_outpin]; + + edges[i_edge].interconnect = interconnect; + edges[i_edge].driver_set = i_inset; + edges[i_edge].driver_pin = i_inpin; + + i_edge++; + } + } + } + } + assert(i_edge == in_count * out_count); +} + +static void alloc_and_load_direct_interc_edges( + INP t_interconnect *interconnect, + INOUTP t_pb_graph_pin *** input_pb_graph_node_pin_ptrs, + INP int num_input_sets, INP int *num_input_ptrs, + INOUTP t_pb_graph_pin *** output_pb_graph_node_pin_ptrs, + INP int num_output_sets, INP int *num_output_ptrs) { + + int i; + t_pb_graph_edge *edges; + struct s_linked_vptr *cur; + + /* Allocate memory for edges */ + if (!(num_input_sets == 1 && num_output_sets == 1)) { + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] Direct interconnect allows connections from one set of pins to one other set\n", + interconnect->line_num); + exit(1); + } + if (!(num_input_ptrs[0] == num_output_ptrs[0])) { + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] Direct interconnect must use an equal number of pins\n", + interconnect->line_num); + exit(1); + } + + edges = (t_pb_graph_edge*) my_calloc(num_input_ptrs[0], + sizeof(t_pb_graph_edge)); + cur = (struct s_linked_vptr*) my_malloc(sizeof(struct s_linked_vptr)); + cur->next = edges_head; + edges_head = cur; + cur->data_vptr = (void *) edges; + cur = (struct s_linked_vptr*) my_malloc(sizeof(struct s_linked_vptr)); + cur->next = num_edges_head; + num_edges_head = cur; + cur->data_vptr = (void *) ((long) num_input_ptrs[0]); + + /* Reallocate memory for pins and load connections between pins and record these updates in the edges */ + for (i = 0; i < num_input_ptrs[0]; i++) { + input_pb_graph_node_pin_ptrs[0][i]->output_edges = + (t_pb_graph_edge **) my_realloc( + input_pb_graph_node_pin_ptrs[0][i]->output_edges, + (input_pb_graph_node_pin_ptrs[0][i]->num_output_edges + + 1) * sizeof(t_pb_graph_edge *)); + input_pb_graph_node_pin_ptrs[0][i]->output_edges[input_pb_graph_node_pin_ptrs[0][i]->num_output_edges] = + &edges[i]; + input_pb_graph_node_pin_ptrs[0][i]->num_output_edges++; + + output_pb_graph_node_pin_ptrs[0][i]->input_edges = + (t_pb_graph_edge **) my_realloc( + output_pb_graph_node_pin_ptrs[0][i]->input_edges, + (output_pb_graph_node_pin_ptrs[0][i]->num_input_edges + + 1) * sizeof(t_pb_graph_edge *)); + output_pb_graph_node_pin_ptrs[0][i]->input_edges[output_pb_graph_node_pin_ptrs[0][i]->num_input_edges] = + &edges[i]; + output_pb_graph_node_pin_ptrs[0][i]->num_input_edges++; + + edges[i].num_input_pins = 1; + edges[i].input_pins = (t_pb_graph_pin **) my_malloc( + sizeof(t_pb_graph_pin *)); + edges[i].input_pins[0] = input_pb_graph_node_pin_ptrs[0][i]; + edges[i].num_output_pins = 1; + edges[i].output_pins = (t_pb_graph_pin **) my_malloc( + sizeof(t_pb_graph_pin *)); + edges[i].output_pins[0] = output_pb_graph_node_pin_ptrs[0][i]; + + edges[i].interconnect = interconnect; + edges[i].driver_set = 0; + edges[i].driver_pin = i; + edges[i].infer_pattern = interconnect->infer_annotations; + } +} + +static void alloc_and_load_mux_interc_edges( INP t_interconnect * interconnect, + INOUTP t_pb_graph_pin *** input_pb_graph_node_pin_ptrs, + INP int num_input_sets, INP int *num_input_ptrs, + INOUTP t_pb_graph_pin *** output_pb_graph_node_pin_ptrs, + INP int num_output_sets, INP int *num_output_ptrs) { + int i_inset, i_inpin, i_outpin; + t_pb_graph_edge *edges; + struct s_linked_vptr *cur; + + assert(interconnect->infer_annotations == FALSE); + + /* Allocate memory for edges, and reallocate more memory for pins connecting to those edges */ + if (num_output_sets != 1) { + vpr_printf(TIO_MESSAGE_ERROR, "[LINE %d] Mux must have one output\n", + interconnect->line_num); + exit(1); + } + + edges = (t_pb_graph_edge*) my_calloc(num_input_sets, + sizeof(t_pb_graph_edge)); + cur = (struct s_linked_vptr*) my_malloc(sizeof(struct s_linked_vptr)); + cur->next = edges_head; + edges_head = cur; + cur->data_vptr = (void *) edges; + cur = (struct s_linked_vptr*) my_malloc(sizeof(struct s_linked_vptr)); + cur->next = num_edges_head; + num_edges_head = cur; + cur->data_vptr = (void *) ((long) num_input_sets); + + for (i_inset = 0; i_inset < num_input_sets; i_inset++) { + for (i_inpin = 0; i_inpin < num_input_ptrs[i_inset]; i_inpin++) { + input_pb_graph_node_pin_ptrs[i_inset][i_inpin]->output_edges = + (t_pb_graph_edge**) my_realloc( + input_pb_graph_node_pin_ptrs[i_inset][i_inpin]->output_edges, + (input_pb_graph_node_pin_ptrs[i_inset][i_inpin]->num_output_edges + + 1) * sizeof(t_pb_graph_edge *)); + } + } + + for (i_outpin = 0; i_outpin < num_output_ptrs[0]; i_outpin++) { + output_pb_graph_node_pin_ptrs[0][i_outpin]->input_edges = + (t_pb_graph_edge**) my_realloc( + output_pb_graph_node_pin_ptrs[0][i_outpin]->input_edges, + (output_pb_graph_node_pin_ptrs[0][i_outpin]->num_input_edges + + num_input_sets) * sizeof(t_pb_graph_edge *)); + } + + /* Load connections between pins and record these updates in the edges */ + for (i_inset = 0; i_inset < num_input_sets; i_inset++) { + if (num_output_ptrs[0] != num_input_ptrs[i_inset]) { + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] # of pins for a particular data line of a mux must equal number of pins at output of mux\n", + interconnect->line_num); + exit(1); + } + edges[i_inset].input_pins = (t_pb_graph_pin**) my_calloc( + num_output_ptrs[0], sizeof(t_pb_graph_pin *)); + edges[i_inset].output_pins = (t_pb_graph_pin**) my_calloc( + num_output_ptrs[0], sizeof(t_pb_graph_pin *)); + edges[i_inset].num_input_pins = num_output_ptrs[0]; + edges[i_inset].num_output_pins = num_output_ptrs[0]; + for (i_inpin = 0; i_inpin < num_input_ptrs[i_inset]; i_inpin++) { + input_pb_graph_node_pin_ptrs[i_inset][i_inpin]->output_edges[input_pb_graph_node_pin_ptrs[i_inset][i_inpin]->num_output_edges] = + &edges[i_inset]; + input_pb_graph_node_pin_ptrs[i_inset][i_inpin]->num_output_edges++; + output_pb_graph_node_pin_ptrs[0][i_inpin]->input_edges[output_pb_graph_node_pin_ptrs[0][i_inpin]->num_input_edges] = + &edges[i_inset]; + output_pb_graph_node_pin_ptrs[0][i_inpin]->num_input_edges++; + + edges[i_inset].input_pins[i_inpin] = + input_pb_graph_node_pin_ptrs[i_inset][i_inpin]; + edges[i_inset].output_pins[i_inpin] = + output_pb_graph_node_pin_ptrs[0][i_inpin]; + + if (i_inpin != 0) { + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] Bus-based mux not yet supported, will consider for future work\n", + interconnect->line_num); + exit(1); + } + edges[i_inset].interconnect = interconnect; + edges[i_inset].driver_set = i_inset; + edges[i_inset].driver_pin = i_inpin; + } + } +} + +/** + * populate array of pb graph pins for a single variable of type pb_type[int:int].port[int:int] + * pb_graph_pins: pointer to array from [0..num_port_pins] of pb_graph_pin pointers + * tokens: array of tokens to scan + * num_pins: current number of pins in pb_graph_pin array + */ +static boolean realloc_and_load_pb_graph_pin_ptrs_at_var(INP int line_num, + INP const t_pb_graph_node *pb_graph_parent_node, + INP t_pb_graph_node **pb_graph_children_nodes, + INP boolean interconnect_error_check, INP boolean is_input_to_interc, + INP const t_token *tokens, INOUTP int *token_index, + INOUTP int *num_pins, OUTP t_pb_graph_pin ***pb_graph_pins) { + + int i, j, ipin, ipb; + int pb_msb, pb_lsb; + int pin_msb, pin_lsb; + int max_pb_node_array; + const t_pb_graph_node *pb_node_array; + char *port_name; + t_port *iport; + int add_or_subtract_pb, add_or_subtract_pin; + boolean found; + t_mode *mode = NULL; + + assert(tokens[*token_index].type == TOKEN_STRING); + pb_node_array = NULL; + max_pb_node_array = 0; + + if (pb_graph_children_nodes) + mode = pb_graph_children_nodes[0][0].pb_type->parent_mode; + + pb_msb = pb_lsb = OPEN; + pin_msb = pin_lsb = OPEN; + + /* parse pb */ + found = FALSE; + if (0 + == strcmp(pb_graph_parent_node->pb_type->name, + tokens[*token_index].data)) { + pb_node_array = pb_graph_parent_node; + max_pb_node_array = 1; + pb_msb = pb_lsb = 0; + found = TRUE; + (*token_index)++; + if (tokens[*token_index].type == TOKEN_OPEN_SQUARE_BRACKET) { + (*token_index)++; + if (!checkTokenType(tokens[*token_index], TOKEN_INT)) { + return FALSE; + } + pb_msb = my_atoi(tokens[*token_index].data); + (*token_index)++; + if (!checkTokenType(tokens[*token_index], TOKEN_COLON)) { + if (!checkTokenType(tokens[*token_index], + TOKEN_CLOSE_SQUARE_BRACKET)) { + return FALSE; + } + pb_lsb = pb_msb; + (*token_index)++; + } else { + (*token_index)++; + if (!checkTokenType(tokens[*token_index], TOKEN_INT)) { + return FALSE; + } + pb_lsb = my_atoi(tokens[*token_index].data); + (*token_index)++; + if (!checkTokenType(tokens[*token_index], + TOKEN_CLOSE_SQUARE_BRACKET)) { + return FALSE; + } + (*token_index)++; + } + /* Check to make sure indices from user match internal data structures for the indices of the parent */ + if ((pb_lsb != pb_msb) + && (pb_lsb != pb_graph_parent_node->placement_index)) { + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] Incorrect placement index for %s, expected index %d\n", + line_num, tokens[0].data, + pb_graph_parent_node->placement_index); + return FALSE; + } + pb_lsb = pb_msb = 0; /* Internal representation of parent is always 0 */ + } + } else { + if (mode == NULL ) { + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] pb_graph_parent_node %s failed\n", line_num, + pb_graph_parent_node->pb_type->name); + exit(1); + } + for (i = 0; i < mode->num_pb_type_children; i++) { + assert( + &mode->pb_type_children[i] == pb_graph_children_nodes[i][0].pb_type); + if (0 + == strcmp(mode->pb_type_children[i].name, + tokens[*token_index].data)) { + pb_node_array = pb_graph_children_nodes[i]; + max_pb_node_array = mode->pb_type_children[i].num_pb; + found = TRUE; + (*token_index)++; + + if (tokens[*token_index].type == TOKEN_OPEN_SQUARE_BRACKET) { + (*token_index)++; + if (!checkTokenType(tokens[*token_index], TOKEN_INT)) { + return FALSE; + } + pb_msb = my_atoi(tokens[*token_index].data); + (*token_index)++; + if (!checkTokenType(tokens[*token_index], TOKEN_COLON)) { + if (!checkTokenType(tokens[*token_index], + TOKEN_CLOSE_SQUARE_BRACKET)) { + return FALSE; + } + pb_lsb = pb_msb; + (*token_index)++; + } else { + (*token_index)++; + if (!checkTokenType(tokens[*token_index], TOKEN_INT)) { + return FALSE; + } + pb_lsb = my_atoi(tokens[*token_index].data); + (*token_index)++; + if (!checkTokenType(tokens[*token_index], + TOKEN_CLOSE_SQUARE_BRACKET)) { + return FALSE; + } + (*token_index)++; + } + } else { + pb_msb = pb_node_array[0].pb_type->num_pb - 1; + pb_lsb = 0; + } + break; + } + } + } + + if (!found) { + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] Unknown pb_type name %s, not defined in namespace of mode %s\n", + line_num, tokens[*token_index].data, mode->name); + return FALSE; + } + + found = FALSE; + + if (!checkTokenType(tokens[*token_index], TOKEN_DOT)) { + return FALSE; + } + (*token_index)++; + if (!checkTokenType(tokens[*token_index], TOKEN_STRING)) { + return FALSE; + } + + /* parse ports and port pins of pb */ + port_name = tokens[*token_index].data; + + (*token_index)++; + if (tokens[*token_index].type == TOKEN_OPEN_SQUARE_BRACKET) { + (*token_index)++; + if (!checkTokenType(tokens[*token_index], TOKEN_INT)) { + return FALSE; + } + pin_msb = my_atoi(tokens[*token_index].data); + (*token_index)++; + if (!checkTokenType(tokens[*token_index], TOKEN_COLON)) { + if (!checkTokenType(tokens[*token_index], + TOKEN_CLOSE_SQUARE_BRACKET)) { + return FALSE; + } + pin_lsb = pin_msb; + (*token_index)++; + } else { + (*token_index)++; + if (!checkTokenType(tokens[*token_index], TOKEN_INT)) { + return FALSE; + } + pin_lsb = my_atoi(tokens[*token_index].data); + (*token_index)++; + if (!checkTokenType(tokens[*token_index], + TOKEN_CLOSE_SQUARE_BRACKET)) { + return FALSE; + } + (*token_index)++; + } + } else { + if (pb_lsb < 0 || pb_lsb >= max_pb_node_array) { + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] pb %d out of range [%d,%d]\n", line_num, pb_lsb, + max_pb_node_array - 1, 0); + exit(1); + } + if (get_pb_graph_pin_from_name(port_name, &pb_node_array[pb_lsb], + 0) == NULL) { + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] failed to find port name %s\n", line_num, + port_name); + exit(1); + } + iport = + get_pb_graph_pin_from_name(port_name, &pb_node_array[pb_lsb], 0)->port; + pin_msb = iport->num_pins - 1; + pin_lsb = 0; + } + (*token_index)--; + + if (pb_msb < pb_lsb) { + add_or_subtract_pb = -1; + } else { + add_or_subtract_pb = 1; + } + + if (pin_msb < pin_lsb) { + add_or_subtract_pin = -1; + } else { + add_or_subtract_pin = 1; + } + *num_pins += (abs(pb_msb - pb_lsb) + 1) * (abs(pin_msb - pin_lsb) + 1); + *pb_graph_pins = (t_pb_graph_pin**) my_calloc(*num_pins, + sizeof(t_pb_graph_pin *)); + i = j = 0; + + ipb = pb_lsb; + + while (ipb != pb_msb + add_or_subtract_pin) { + ipin = pin_lsb; + j = 0; + while (ipin != pin_msb + add_or_subtract_pin) { + if (ipb < 0 || ipb >= max_pb_node_array) { + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] pb %d out of range [%d,%d]\n", line_num, ipb, + max_pb_node_array - 1, 0); + exit(1); + } + (*pb_graph_pins)[i * (abs(pin_msb - pin_lsb) + 1) + j] = + get_pb_graph_pin_from_name(port_name, &pb_node_array[ipb], + ipin); + if ((*pb_graph_pins)[i * (abs(pin_msb - pin_lsb) + 1) + j] == NULL ) { + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] Pin %s.%s[%d] cannot be found\n", line_num, + pb_node_array[ipb].pb_type->name, port_name, ipin); + exit(1); + } + iport = + (*pb_graph_pins)[i * (abs(pin_msb - pin_lsb) + 1) + j]->port; + if (!iport) { + return FALSE; + } + + /* Error checking before assignment */ + if (interconnect_error_check) { + if (pb_node_array == pb_graph_parent_node) { + if (is_input_to_interc) { + if (iport->type != IN_PORT) { + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] input to interconnect from parent is not an input or clock pin\n", + line_num); + return FALSE; + } + } else { + if (iport->type != OUT_PORT) { + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] output from interconnect from parent is not an input or clock pin\n", + line_num); + return FALSE; + } + } + } else { + if (is_input_to_interc) { + if (iport->type != OUT_PORT) { + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] output from interconnect from parent is not an input or clock pin\n", + line_num); + return FALSE; + } + } else { + if (iport->type != IN_PORT) { + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] input to interconnect from parent is not an input or clock pin\n", + line_num); + return FALSE; + } + } + } + } + + /* load pb_graph_pin for pin */ + + ipin += add_or_subtract_pin; + j++; + } + i++; + ipb += add_or_subtract_pb; + } + + assert((abs(pb_msb - pb_lsb) + 1) * (abs(pin_msb - pin_lsb) + 1) == i * j); + + return TRUE; +} + +static t_pb_graph_pin * get_pb_graph_pin_from_name(INP const char * port_name, + INP const t_pb_graph_node * pb, INP int pin) { + int i; + + for (i = 0; i < pb->num_input_ports; i++) { + if (0 == strcmp(port_name, pb->input_pins[i][0].port->name)) { + if (pin < pb->input_pins[i][0].port->num_pins) { + return &pb->input_pins[i][pin]; + } else { + return NULL ; + } + } + } + for (i = 0; i < pb->num_output_ports; i++) { + if (0 == strcmp(port_name, pb->output_pins[i][0].port->name)) { + if (pin < pb->output_pins[i][0].port->num_pins) { + return &pb->output_pins[i][pin]; + } else { + return NULL ; + } + } + } + for (i = 0; i < pb->num_clock_ports; i++) { + if (0 == strcmp(port_name, pb->clock_pins[i][0].port->name)) { + if (pin < pb->clock_pins[i][0].port->num_pins) { + return &pb->clock_pins[i][pin]; + } else { + return NULL ; + } + } + } + return NULL ; +} + +static void alloc_and_load_pin_locations_from_pb_graph(t_type_descriptor *type) { + int i, j, k, m, icapacity; + int num_sides; + int side_index; + int pin_num; + int count; + + int *num_pb_graph_node_pins; /* number of pins in a set [0..num_sets-1] */ + int num_pb_graph_node_sets; + t_pb_graph_pin*** pb_graph_node_pins; + + num_sides = 2 * (type->height + 1); + side_index = 0; + count = 0; + + if (type->pin_location_distribution == E_SPREAD_PIN_DISTR) { + pin_num = 0; + /* evenly distribute pins starting at bottom left corner */ + for (j = 0; j < 4; j++) { + for (i = 0; i < type->height; i++) { + if (j == TOP && i != type->height - 1) { + continue; + } + if (j == BOTTOM && i != 0) { + continue; + } + for (k = 0; k < (type->num_pins / num_sides) + 1; k++) { + pin_num = side_index + k * num_sides; + if (pin_num < type->num_pins) { + type->pinloc[i][j][pin_num] = 1; + type->pin_height[pin_num] = i; + count++; + } + } + side_index++; + } + } + assert(side_index == num_sides); + assert(count == type->num_pins); + } else { + assert(type->pin_location_distribution == E_CUSTOM_PIN_DISTR); + for (i = 0; i < type->height; i++) { + for (j = 0; j < 4; j++) { + if (j == TOP && i != type->height - 1) { + continue; + } + if (j == BOTTOM && i != 0) { + continue; + } + for (k = 0; k < type->num_pin_loc_assignments[i][j]; k++) { + pb_graph_node_pins = + alloc_and_load_port_pin_ptrs_from_string( + type->pb_type->modes[0].interconnect[0].line_num, + type->pb_graph_head, + type->pb_graph_head->child_pb_graph_nodes[0], + type->pin_loc_assignments[i][j][k], + &num_pb_graph_node_pins, + &num_pb_graph_node_sets, FALSE, FALSE); + assert(num_pb_graph_node_sets == 1); + + for (m = 0; m < num_pb_graph_node_pins[0]; m++) { + pin_num = + pb_graph_node_pins[0][m]->pin_count_in_cluster; + assert(pin_num < type->num_pins / type->capacity); + for (icapacity = 0; icapacity < type->capacity; + icapacity++) { + type->pinloc[i][j][pin_num + + icapacity * type->num_pins + / type->capacity] = 1; + type->pin_height[pin_num] = i; + assert(count < type->num_pins); + } + } + free(pb_graph_node_pins[0]); + free(pb_graph_node_pins); + free(num_pb_graph_node_pins); + } + } + } + } +} + +static void echo_pb_rec(const INP t_pb_graph_node *pb_graph_node, INP int level, + INP FILE *fp) { + int i, j, k; + + print_tabs(fp, level); + fprintf(fp, "Physical Block: type \"%s\" index %d num_children %d\n", + pb_graph_node->pb_type->name, pb_graph_node->placement_index, + pb_graph_node->pb_type->num_pb); + + if (pb_graph_node->parent_pb_graph_node) { + print_tabs(fp, level + 1); + fprintf(fp, "Parent Block: type \"%s\" index %d \n", + pb_graph_node->parent_pb_graph_node->pb_type->name, + pb_graph_node->parent_pb_graph_node->placement_index); + } + + print_tabs(fp, level); + fprintf(fp, "Input Ports: total ports %d\n", + pb_graph_node->num_input_ports); + echo_pb_pins(pb_graph_node->input_pins, pb_graph_node->num_input_ports, + level, fp); + print_tabs(fp, level); + fprintf(fp, "Output Ports: total ports %d\n", + pb_graph_node->num_output_ports); + echo_pb_pins(pb_graph_node->output_pins, pb_graph_node->num_output_ports, + level, fp); + print_tabs(fp, level); + fprintf(fp, "Clock Ports: total ports %d\n", + pb_graph_node->num_clock_ports); + echo_pb_pins(pb_graph_node->clock_pins, pb_graph_node->num_clock_ports, + level, fp); + print_tabs(fp, level); + for (i = 0; i < pb_graph_node->num_input_pin_class; i++) { + fprintf(fp, "Input class %d: %d pins, ", i, + pb_graph_node->input_pin_class_size[i]); + } + fprintf(fp, "\n"); + print_tabs(fp, level); + for (i = 0; i < pb_graph_node->num_output_pin_class; i++) { + fprintf(fp, "Output class %d: %d pins, ", i, + pb_graph_node->output_pin_class_size[i]); + } + fprintf(fp, "\n"); + + if (pb_graph_node->pb_type->num_modes > 0) { + print_tabs(fp, level); + fprintf(fp, "Children:\n"); + } + for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { + for (j = 0; j < pb_graph_node->pb_type->modes[i].num_pb_type_children; + j++) { + for (k = 0; + k + < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; + k++) { + echo_pb_rec(&pb_graph_node->child_pb_graph_nodes[i][j][k], + level + 1, fp); + } + } + } +} + +static void echo_pb_pins(INP t_pb_graph_pin **pb_graph_pins, INP int num_ports, + INP int level, INP FILE * fp) { + int i, j, k, m; + t_port *port; + + print_tabs(fp, level); + + for (i = 0; i < num_ports; i++) { + port = pb_graph_pins[i][0].port; + print_tabs(fp, level); + fprintf(fp, "Port \"%s\": num_pins %d type %d parent name \"%s\"\n", + port->name, port->num_pins, port->type, + port->parent_pb_type->name); + + for (j = 0; j < port->num_pins; j++) { + print_tabs(fp, level + 1); + assert(j == pb_graph_pins[i][j].pin_number); + assert(pb_graph_pins[i][j].port == port); + fprintf(fp, + "Pin %d port name \"%s\" num input edges %d num output edges %d parent type \"%s\" parent index %d\n", + pb_graph_pins[i][j].pin_number, + pb_graph_pins[i][j].port->name, + pb_graph_pins[i][j].num_input_edges, + pb_graph_pins[i][j].num_output_edges, + pb_graph_pins[i][j].parent_node->pb_type->name, + pb_graph_pins[i][j].parent_node->placement_index); + print_tabs(fp, level + 2); + if (pb_graph_pins[i][j].parent_node->pb_type->num_modes == 0) { + fprintf(fp, "pin class (depth, pin class): "); + for (k = 0; k < pb_graph_pins[i][j].parent_node->pb_type->depth; + k++) { + fprintf(fp, "(%d %d), ", k, + pb_graph_pins[i][j].parent_pin_class[k]); + } + fprintf(fp, "\n"); + if (pb_graph_pins[i][j].port->type == OUT_PORT) { + for (k = 0; + k < pb_graph_pins[i][j].parent_node->pb_type->depth; + k++) { + print_tabs(fp, level + 2); + fprintf(fp, + "connectable input pins within depth %d: %d\n", + k, + pb_graph_pins[i][j].num_connectable_primtive_input_pins[k]); + for (m = 0; + m + < pb_graph_pins[i][j].num_connectable_primtive_input_pins[k]; + m++) { + print_tabs(fp, level + 3); + fprintf(fp, "pb_graph_node %s[%d].%s[%d] \n", + pb_graph_pins[i][j].list_of_connectable_input_pin_ptrs[k][m]->parent_node->pb_type->name, + pb_graph_pins[i][j].list_of_connectable_input_pin_ptrs[k][m]->parent_node->placement_index, + pb_graph_pins[i][j].list_of_connectable_input_pin_ptrs[k][m]->port->name, + pb_graph_pins[i][j].list_of_connectable_input_pin_ptrs[k][m]->pin_number); + } + } + } + } else { + fprintf(fp, "pin class %d \n", pb_graph_pins[i][j].pin_class); + } + for (k = 0; k < pb_graph_pins[i][j].num_input_edges; k++) { + print_tabs(fp, level + 2); + fprintf(fp, "Input edge %d num inputs %d num outputs %d\n", k, + pb_graph_pins[i][j].input_edges[k]->num_input_pins, + pb_graph_pins[i][j].input_edges[k]->num_output_pins); + print_tabs(fp, level + 3); + fprintf(fp, "Input edge inputs\n"); + for (m = 0; + m < pb_graph_pins[i][j].input_edges[k]->num_input_pins; + m++) { + print_tabs(fp, level + 3); + fprintf(fp, "pin number %d port_name \"%s\"\n", + pb_graph_pins[i][j].input_edges[k]->input_pins[m]->pin_number, + pb_graph_pins[i][j].input_edges[k]->input_pins[m]->port->name); + } + print_tabs(fp, level + 3); + fprintf(fp, "Input edge outputs\n"); + for (m = 0; + m < pb_graph_pins[i][j].input_edges[k]->num_output_pins; + m++) { + print_tabs(fp, level + 3); + fprintf(fp, + "pin number %d port_name \"%s\" parent type \"%s\" parent index %d\n", + pb_graph_pins[i][j].input_edges[k]->output_pins[m]->pin_number, + pb_graph_pins[i][j].input_edges[k]->output_pins[m]->port->name, + pb_graph_pins[i][j].input_edges[k]->output_pins[m]->parent_node->pb_type->name, + pb_graph_pins[i][j].input_edges[k]->output_pins[m]->parent_node->placement_index); + } + } + for (k = 0; k < pb_graph_pins[i][j].num_output_edges; k++) { + print_tabs(fp, level + 2); + fprintf(fp, "Output edge %d num inputs %d num outputs %d\n", k, + pb_graph_pins[i][j].output_edges[k]->num_input_pins, + pb_graph_pins[i][j].output_edges[k]->num_output_pins); + print_tabs(fp, level + 3); + fprintf(fp, "Output edge inputs\n"); + for (m = 0; + m < pb_graph_pins[i][j].output_edges[k]->num_input_pins; + m++) { + print_tabs(fp, level + 3); + fprintf(fp, "pin number %d port_name \"%s\"\n", + pb_graph_pins[i][j].output_edges[k]->input_pins[m]->pin_number, + pb_graph_pins[i][j].output_edges[k]->input_pins[m]->port->name); + } + print_tabs(fp, level + 3); + fprintf(fp, "Output edge outputs\n"); + for (m = 0; + m < pb_graph_pins[i][j].output_edges[k]->num_output_pins; + m++) { + print_tabs(fp, level + 3); + fprintf(fp, + "pin number %d port_name \"%s\" parent type \"%s\" parent index %d\n", + pb_graph_pins[i][j].output_edges[k]->output_pins[m]->pin_number, + pb_graph_pins[i][j].output_edges[k]->output_pins[m]->port->name, + pb_graph_pins[i][j].output_edges[k]->output_pins[m]->parent_node->pb_type->name, + pb_graph_pins[i][j].output_edges[k]->output_pins[m]->parent_node->placement_index); + } + } + } + } +} + diff --git a/vpr7_rram/vpr/SRC/pack/pb_type_graph.h b/vpr7_rram/vpr/SRC/pack/pb_type_graph.h new file mode 100644 index 000000000..e4605df9c --- /dev/null +++ b/vpr7_rram/vpr/SRC/pack/pb_type_graph.h @@ -0,0 +1,16 @@ +#ifndef PB_TYPE_GRAPH_H +#define PB_TYPE_GRAPH_H + +void alloc_and_load_all_pb_graphs(boolean load_power_structures); +void echo_pb_graph(char * filename); +void free_all_pb_graph_nodes(void); +t_pb_graph_pin *** alloc_and_load_port_pin_ptrs_from_string(INP int line_num, + INP const t_pb_graph_node *pb_graph_parent_node, + INP t_pb_graph_node **pb_graph_children_nodes, + INP const char * port_string, + OUTP int ** num_ptrs, + OUTP int * num_sets, + INP boolean is_input_to_interc, + INP boolean interconnect_error_check); +#endif + diff --git a/vpr7_rram/vpr/SRC/pack/pb_type_graph_annotations.c b/vpr7_rram/vpr/SRC/pack/pb_type_graph_annotations.c new file mode 100755 index 000000000..83f631b03 --- /dev/null +++ b/vpr7_rram/vpr/SRC/pack/pb_type_graph_annotations.c @@ -0,0 +1,376 @@ +/* Jason Luu + April 15, 2011 + Loads statistical information (min/max delays, power) onto the pb_graph. */ + +#include +#include +#include +#include + +#include "util.h" +#include "arch_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "vpr_utils.h" +#include "pb_type_graph.h" +#include "token.h" +#include "pb_type_graph_annotations.h" + +static void load_pack_pattern_annotations(INP int line_num, INOUTP t_pb_graph_node *pb_graph_node, + INP int mode, INP char *annot_in_pins, INP char *annot_out_pins, + INP char *value); + +static void load_critical_path_annotations(INP int line_num, + INOUTP t_pb_graph_node *pb_graph_node, INP int mode, + INP enum e_pin_to_pin_annotation_format input_format, + INP enum e_pin_to_pin_delay_annotations delay_type, + INP char *annot_in_pins, INP char *annot_out_pins, INP char* value); + +void load_pb_graph_pin_to_pin_annotations(INOUTP t_pb_graph_node *pb_graph_node) { + int i, j, k, m; + const t_pb_type *pb_type; + t_pin_to_pin_annotation *annotations; + + pb_type = pb_graph_node->pb_type; + + /* Load primitive critical path delays */ + if (pb_type->num_modes == 0) { + annotations = pb_type->annotations; + for (i = 0; i < pb_type->num_annotations; i++) { + if (annotations[i].type == E_ANNOT_PIN_TO_PIN_DELAY) { + for (j = 0; j < annotations[i].num_value_prop_pairs; j++) { + if (annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_MAX + || annotations[i].prop[j] + == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX + || annotations[i].prop[j] + == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP) { + load_critical_path_annotations(annotations[i].line_num, pb_graph_node, OPEN, + annotations[i].format, (enum e_pin_to_pin_delay_annotations)annotations[i].prop[j], + annotations[i].input_pins, + annotations[i].output_pins, + annotations[i].value[j]); + } else { + assert( + annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_MIN || annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN || annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_THOLD); + } + } + } else { + /* Todo: + load_hold_time_constraints_annotations(pb_graph_node); + load_power_annotations(pb_graph_node); + */ + } + } + } else { + /* Load interconnect delays */ + for (i = 0; i < pb_type->num_modes; i++) { + for (j = 0; j < pb_type->modes[i].num_interconnect; j++) { + annotations = pb_type->modes[i].interconnect[j].annotations; + for (k = 0; + k < pb_type->modes[i].interconnect[j].num_annotations; + k++) { + if (annotations[k].type == E_ANNOT_PIN_TO_PIN_DELAY) { + for (m = 0; m < annotations[k].num_value_prop_pairs; + m++) { + if (annotations[k].prop[m] + == E_ANNOT_PIN_TO_PIN_DELAY_MAX + || annotations[k].prop[m] + == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX + || annotations[k].prop[m] + == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP) { + load_critical_path_annotations(annotations[k].line_num, pb_graph_node, i, + annotations[k].format, + (enum e_pin_to_pin_delay_annotations)annotations[k].prop[m], + annotations[k].input_pins, + annotations[k].output_pins, + annotations[k].value[m]); + } else { + assert( + annotations[k].prop[m] == E_ANNOT_PIN_TO_PIN_DELAY_MIN || annotations[k].prop[m] == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN || annotations[k].prop[m] == E_ANNOT_PIN_TO_PIN_DELAY_THOLD); + } + } + } else if (annotations[k].type + == E_ANNOT_PIN_TO_PIN_PACK_PATTERN) { + assert(annotations[k].num_value_prop_pairs == 1); + load_pack_pattern_annotations(annotations[k].line_num, pb_graph_node, i, + annotations[k].input_pins, + annotations[k].output_pins, + annotations[k].value[0]); + } else { + /* Todo: + load_hold_time_constraints_annotations(pb_graph_node); + load_power_annotations(pb_graph_node); + */ + } + } + } + } + } + + for (i = 0; i < pb_type->num_modes; i++) { + for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { + for (k = 0; k < pb_type->modes[i].pb_type_children[j].num_pb; k++) { + load_pb_graph_pin_to_pin_annotations( + &pb_graph_node->child_pb_graph_nodes[i][j][k]); + } + } + } +} + +/* + Add the pattern name to the pack_pattern field for each pb_graph_edge that is used in a pack pattern + */ +static void load_pack_pattern_annotations(INP int line_num, INOUTP t_pb_graph_node *pb_graph_node, + INP int mode, INP char *annot_in_pins, INP char *annot_out_pins, + INP char *value) { + int i, j, k, m, n, p, iedge; + t_pb_graph_pin ***in_port, ***out_port; + int *num_in_ptrs, *num_out_ptrs, num_in_sets, num_out_sets; + t_pb_graph_node **children = NULL; + + children = pb_graph_node->child_pb_graph_nodes[mode]; + in_port = alloc_and_load_port_pin_ptrs_from_string(line_num, pb_graph_node, children, + annot_in_pins, &num_in_ptrs, &num_in_sets, FALSE, FALSE); + out_port = alloc_and_load_port_pin_ptrs_from_string(line_num, pb_graph_node, children, + annot_out_pins, &num_out_ptrs, &num_out_sets, FALSE, FALSE); + + /* Discover edge then annotate edge with name of pack pattern */ + k = 0; + for (i = 0; i < num_in_sets; i++) { + for (j = 0; j < num_in_ptrs[i]; j++) { + p = 0; + for (m = 0; m < num_out_sets; m++) { + for (n = 0; n < num_out_ptrs[m]; n++) { + for (iedge = 0; iedge < in_port[i][j]->num_output_edges; + iedge++) { + if (in_port[i][j]->output_edges[iedge]->output_pins[0] + == out_port[m][n]) { + break; + } + } + /* jluu Todo: This is inefficient, I know the interconnect so I know what edges exist + can use this info to only annotate existing edges */ + if (iedge != in_port[i][j]->num_output_edges) { + in_port[i][j]->output_edges[iedge]->num_pack_patterns++; + in_port[i][j]->output_edges[iedge]->pack_pattern_names = (char**) + my_realloc( + in_port[i][j]->output_edges[iedge]->pack_pattern_names, + sizeof(char*) + * in_port[i][j]->output_edges[iedge]->num_pack_patterns); + in_port[i][j]->output_edges[iedge]->pack_pattern_names[in_port[i][j]->output_edges[iedge]->num_pack_patterns + - 1] = value; + } + p++; + } + } + k++; + } + } + + if (in_port != NULL) { + for (i = 0; i < num_in_sets; i++) { + free(in_port[i]); + } + free(in_port); + free(num_in_ptrs); + } + if (out_port != NULL) { + for (i = 0; i < num_out_sets; i++) { + free(out_port[i]); + } + free(out_port); + free(num_out_ptrs); + } +} + +static void load_critical_path_annotations(INP int line_num, + INOUTP t_pb_graph_node *pb_graph_node, INP int mode, + INP enum e_pin_to_pin_annotation_format input_format, + INP enum e_pin_to_pin_delay_annotations delay_type, + INP char *annot_in_pins, INP char *annot_out_pins, INP char* value) { + + int i, j, k, m, n, p, iedge; + t_pb_graph_pin ***in_port, ***out_port; + int *num_in_ptrs, *num_out_ptrs, num_in_sets, num_out_sets; + float **delay_matrix; + t_pb_graph_node **children = NULL; + + int count, prior_offset; + int num_inputs, num_outputs; + + in_port = out_port = NULL; + num_out_sets = num_in_sets = 0; + num_out_ptrs = num_in_ptrs = NULL; + + /* Primarily 3 kinds of delays that affect critical path: + 1. Intrablock interconnect delays + 2. Combinational primitives (pin-to-pin delays of primitive) + 3. Sequential primitives (setup and clock-to-q times) + + Note: Proper I/O modelling requires knowledge of the extra-chip world (eg. the load that pin is driving, drive strength, etc) + For now, I/O delays are modelled as a constant in the architecture file by setting the pad-I/O block interconnect delay to be a constant I/O delay + + Algorithm: Intrablock and combinational primitive delays apply to edges + Sequential delays apply to pins + 1. Determine if delay applies to pin or edge + 2. Format the delay information + 3. Load delay information + */ + + /* Determine what pins to read based on delay type */ + num_inputs = num_outputs = 0; + if (mode == OPEN) { + children = NULL; + } else { + children = pb_graph_node->child_pb_graph_nodes[mode]; + } + if (delay_type == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP) { + assert(pb_graph_node->pb_type->blif_model != NULL); + in_port = alloc_and_load_port_pin_ptrs_from_string(line_num, pb_graph_node, + children, annot_in_pins, &num_in_ptrs, &num_in_sets, FALSE, + FALSE); + } else if (delay_type == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX) { + assert(pb_graph_node->pb_type->blif_model != NULL); + in_port = alloc_and_load_port_pin_ptrs_from_string(line_num, pb_graph_node, + children, annot_in_pins, &num_in_ptrs, &num_in_sets, FALSE, + FALSE); + } else { + assert(delay_type == E_ANNOT_PIN_TO_PIN_DELAY_MAX); + in_port = alloc_and_load_port_pin_ptrs_from_string(line_num, pb_graph_node, + children, annot_in_pins, &num_in_ptrs, &num_in_sets, FALSE, + FALSE); + out_port = alloc_and_load_port_pin_ptrs_from_string(line_num, pb_graph_node, + children, annot_out_pins, &num_out_ptrs, &num_out_sets, FALSE, + FALSE); + } + + num_inputs = 0; + for (i = 0; i < num_in_sets; i++) { + num_inputs += num_in_ptrs[i]; + } + + if (out_port != NULL) { + num_outputs = 0; + for (i = 0; i < num_out_sets; i++) { + num_outputs += num_out_ptrs[i]; + } + } else { + num_outputs = 1; + } + + delay_matrix = (float**)my_malloc(sizeof(float*) * num_inputs); + for (i = 0; i < num_inputs; i++) { + delay_matrix[i] = (float*)my_malloc(sizeof(float) * num_outputs); + } + + if (input_format == E_ANNOT_PIN_TO_PIN_MATRIX) { + my_atof_2D(delay_matrix, num_inputs, num_outputs, value); + } else { + assert(input_format == E_ANNOT_PIN_TO_PIN_CONSTANT); + for (i = 0; i < num_inputs; i++) { + for (j = 0; j < num_outputs; j++) { + delay_matrix[i][j] = atof(value); + } + } + } + + if (delay_type == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP + || delay_type == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX) { + k = 0; + for (i = 0; i < num_in_sets; i++) { + for (j = 0; j < num_in_ptrs[i]; j++) { + in_port[i][j]->tsu_tco = delay_matrix[k][0]; + k++; + } + } + } else { + if (pb_graph_node->pb_type->num_modes != 0) { + /* Not a primitive, find pb_graph_edge */ + k = 0; + for (i = 0; i < num_in_sets; i++) { + for (j = 0; j < num_in_ptrs[i]; j++) { + p = 0; + for (m = 0; m < num_out_sets; m++) { + for (n = 0; n < num_out_ptrs[m]; n++) { + for (iedge = 0; + iedge < in_port[i][j]->num_output_edges; + iedge++) { + if (in_port[i][j]->output_edges[iedge]->output_pins[0] + == out_port[m][n]) { + assert( + in_port[i][j]->output_edges[iedge]->delay_max == 0); + break; + } + } + /* jluu Todo: This is inefficient, I know the interconnect so I know what edges exist + can use this info to only annotate existing edges */ + if (iedge != in_port[i][j]->num_output_edges) { + in_port[i][j]->output_edges[iedge]->delay_max = + delay_matrix[k][p]; + } + p++; + } + } + k++; + } + } + } else { + /* Primitive, allocate appropriate nodes */ + k = 0; + for (i = 0; i < num_in_sets; i++) { + for (j = 0; j < num_in_ptrs[i]; j++) { + count = p = 0; + for (m = 0; m < num_out_sets; m++) { + for (n = 0; n < num_out_ptrs[m]; n++) { + /* OPEN indicates that connection does not exist */ + if (delay_matrix[k][p] != OPEN) { + count++; + } + p++; + } + } + prior_offset = in_port[i][j]->num_pin_timing; + in_port[i][j]->num_pin_timing = prior_offset + count; + in_port[i][j]->pin_timing_del_max = (float*) my_realloc(in_port[i][j]->pin_timing_del_max, + sizeof(float) * in_port[i][j]->num_pin_timing); + in_port[i][j]->pin_timing = (t_pb_graph_pin**)my_realloc(in_port[i][j]->pin_timing, + sizeof(t_pb_graph_pin*) * in_port[i][j]->num_pin_timing); + p = 0; + count = 0; + for (m = 0; m < num_out_sets; m++) { + for (n = 0; n < num_out_ptrs[m]; n++) { + if (delay_matrix[k][p] != OPEN) { + in_port[i][j]->pin_timing_del_max[prior_offset + count] = + delay_matrix[k][p]; + in_port[i][j]->pin_timing[prior_offset + count] = + out_port[m][n]; + count++; + } + p++; + } + } + assert(in_port[i][j]->num_pin_timing == prior_offset + count); + k++; + } + } + } + } + if (in_port != NULL) { + for (i = 0; i < num_in_sets; i++) { + free(in_port[i]); + } + free(in_port); + free(num_in_ptrs); + } + if (out_port != NULL) { + for (i = 0; i < num_out_sets; i++) { + free(out_port[i]); + } + free(out_port); + free(num_out_ptrs); + } + for (i = 0; i < num_inputs; i++) { + free(delay_matrix[i]); + } + free(delay_matrix); +} diff --git a/vpr7_rram/vpr/SRC/pack/pb_type_graph_annotations.h b/vpr7_rram/vpr/SRC/pack/pb_type_graph_annotations.h new file mode 100755 index 000000000..425f02bd9 --- /dev/null +++ b/vpr7_rram/vpr/SRC/pack/pb_type_graph_annotations.h @@ -0,0 +1,12 @@ +/** + * Jason Luu + * April 15, 2011 + * pb_type_graph_annotations loads statistical information onto the different nodes/edges of a pb_type_graph. These statistical informations include delays, capacitance, etc. + */ + +#ifndef PB_TYPE_GRAPH_ANNOTATIONS_H +#define PB_TYPE_GRAPH_ANNOTATIONS_H + +void load_pb_graph_pin_to_pin_annotations(INOUTP t_pb_graph_node *pb_graph_node); + +#endif diff --git a/vpr7_rram/vpr/SRC/pack/prepack.c b/vpr7_rram/vpr/SRC/pack/prepack.c new file mode 100644 index 000000000..51f201515 --- /dev/null +++ b/vpr7_rram/vpr/SRC/pack/prepack.c @@ -0,0 +1,1065 @@ +/* + Prepacking: Group together technology-mapped netlist blocks before packing. This gives hints to the packer on what groups of blocks to keep together during packing. + Primary purpose 1) "Forced" packs (eg LUT+FF pair) + 2) Carry-chains + + + Duties: Find pack patterns in architecture, find pack patterns in netlist. + + Author: Jason Luu + March 12, 2012 + */ +#include +#include +#include + +#include "read_xml_arch_file.h" +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "hash.h" +#include "prepack.h" +#include "vpr_utils.h" +#include "ReadOptions.h" + +/*****************************************/ +/*Local Function Declaration */ +/*****************************************/ +static int add_pattern_name_to_hash(INOUTP struct s_hash **nhash, + INP char *pattern_name, INOUTP int *ncount); +static void discover_pattern_names_in_pb_graph_node( + INOUTP t_pb_graph_node *pb_graph_node, INOUTP struct s_hash **nhash, + INOUTP int *ncount); +static void forward_infer_pattern(INOUTP t_pb_graph_pin *pb_graph_pin); +static void backward_infer_pattern(INOUTP t_pb_graph_pin *pb_graph_pin); +static t_pack_patterns *alloc_and_init_pattern_list_from_hash(INP int ncount, + INOUTP struct s_hash **nhash); +static t_pb_graph_edge * find_expansion_edge_of_pattern(INP int pattern_index, + INP t_pb_graph_node *pb_graph_node); +static void forward_expand_pack_pattern_from_edge( + INP t_pb_graph_edge *expansion_edge, + INOUTP t_pack_patterns *list_of_packing_patterns, + INP int curr_pattern_index, INP int *L_num_blocks, INP boolean make_root_of_chain); +static void backward_expand_pack_pattern_from_edge( + INP t_pb_graph_edge* expansion_edge, + INOUTP t_pack_patterns *list_of_packing_patterns, + INP int curr_pattern_index, INP t_pb_graph_pin *destination_pin, + INP t_pack_pattern_block *destination_block, INP int *L_num_blocks); +static int compare_pack_pattern(const t_pack_patterns *pattern_a, const t_pack_patterns *pattern_b); +static void free_pack_pattern(INOUTP t_pack_pattern_block *pattern_block, INOUTP t_pack_pattern_block **pattern_block_list); +static t_pack_molecule *try_create_molecule( + INP t_pack_patterns *list_of_pack_patterns, INP int pack_pattern_index, + INP int block_index); +static boolean try_expand_molecule(INOUTP t_pack_molecule *molecule, + INP int logical_block_index, + INP t_pack_pattern_block *current_pattern_block); +static void print_pack_molecules(INP const char *fname, + INP t_pack_patterns *list_of_pack_patterns, INP int num_pack_patterns, + INP t_pack_molecule *list_of_molecules); +static t_pb_graph_node *get_expected_lowest_cost_primitive_for_logical_block(INP int ilogical_block); +static t_pb_graph_node *get_expected_lowest_cost_primitive_for_logical_block_in_pb_graph_node(INP int ilogical_block, INP t_pb_graph_node *curr_pb_graph_node, OUTP float *cost); +static int find_new_root_atom_for_chain(INP int block_index, INP t_pack_patterns *list_of_pack_pattern); + +/*****************************************/ +/*Function Definitions */ +/*****************************************/ + +/** + * Find all packing patterns in architecture + * [0..num_packing_patterns-1] + * + * Limitations: Currently assumes that forced pack nets must be single-fanout as this covers all the reasonable architectures we wanted. + More complicated structures should probably be handled either downstream (general packing) or upstream (in tech mapping) + * If this limitation is too constraining, code is designed so that this limitation can be removed + */ +t_pack_patterns *alloc_and_load_pack_patterns(OUTP int *num_packing_patterns) { + int i, j, ncount, k; + int L_num_blocks; + struct s_hash **nhash; + t_pack_patterns *list_of_packing_patterns; + t_pb_graph_edge *expansion_edge; + + /* alloc and initialize array of packing patterns based on architecture complex blocks */ + nhash = alloc_hash_table(); + ncount = 0; + for (i = 0; i < num_types; i++) { + discover_pattern_names_in_pb_graph_node(type_descriptors[i].pb_graph_head, nhash, &ncount); + } + + list_of_packing_patterns = alloc_and_init_pattern_list_from_hash(ncount, + nhash); + + /* load packing patterns by traversing the edges to find edges belonging to pattern */ + for (i = 0; i < ncount; i++) { + for (j = 0; j < num_types; j++) { + expansion_edge = find_expansion_edge_of_pattern(i, type_descriptors[j].pb_graph_head); + if (expansion_edge == NULL) { + continue; + } + L_num_blocks = 0; + list_of_packing_patterns[i].base_cost = 0; + backward_expand_pack_pattern_from_edge(expansion_edge, list_of_packing_patterns, i, NULL, NULL, &L_num_blocks); + list_of_packing_patterns[i].num_blocks = L_num_blocks; + + /* Default settings: A section of a netlist must match all blocks in a pack pattern before it can be made a molecule except for carry-chains. For carry-chains, since carry-chains are typically + quite flexible in terms of size, it is optional whether or not an atom in a netlist matches any particular block inside the chain */ + list_of_packing_patterns[i].is_block_optional = (boolean*) my_malloc(L_num_blocks * sizeof(boolean)); + for(k = 0; k < L_num_blocks; k++) { + list_of_packing_patterns[i].is_block_optional[k] = FALSE; + if(list_of_packing_patterns[i].is_chain && list_of_packing_patterns[i].root_block->block_id != k) { + list_of_packing_patterns[i].is_block_optional[k] = TRUE; + } + } + break; + } + } + + free_hash_table(nhash); + + *num_packing_patterns = ncount; + + return list_of_packing_patterns; +} + +/** + * Adds pack pattern name to hashtable of pack pattern names. + */ +static int add_pattern_name_to_hash(INOUTP struct s_hash **nhash, + INP char *pattern_name, INOUTP int *ncount) { + struct s_hash *hash_value; + + hash_value = insert_in_hash_table(nhash, pattern_name, *ncount); + if (hash_value->count == 1) { + assert(*ncount == hash_value->index); + (*ncount)++; + } + return hash_value->index; +} + +/** + * Locate all pattern names + * Side-effect: set all pb_graph_node temp_scratch_pad field to NULL + * For cases where a pattern inference is "obvious", mark it as obvious. + */ +static void discover_pattern_names_in_pb_graph_node( + INOUTP t_pb_graph_node *pb_graph_node, INOUTP struct s_hash **nhash, + INOUTP int *ncount) { + int i, j, k, m; + int index; + boolean hasPattern; + /* Iterate over all edges to discover if an edge in current physical block belongs to a pattern + If edge does, then record the name of the pattern in a hash table + */ + + if (pb_graph_node == NULL) { + return; + } + + pb_graph_node->temp_scratch_pad = NULL; + + for (i = 0; i < pb_graph_node->num_input_ports; i++) { + for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { + hasPattern = FALSE; + for (k = 0; k < pb_graph_node->input_pins[i][j].num_output_edges; k++) { + for (m = 0; m < pb_graph_node->input_pins[i][j].output_edges[k]->num_pack_patterns; m++) { + hasPattern = TRUE; + index = add_pattern_name_to_hash(nhash, + pb_graph_node->input_pins[i][j].output_edges[k]->pack_pattern_names[m], + ncount); + if (pb_graph_node->input_pins[i][j].output_edges[k]->pack_pattern_indices == NULL) { + pb_graph_node->input_pins[i][j].output_edges[k]->pack_pattern_indices = (int*) my_malloc(pb_graph_node->input_pins[i][j].output_edges[k]->num_pack_patterns * sizeof(int)); + } + pb_graph_node->input_pins[i][j].output_edges[k]->pack_pattern_indices[m] = index; + } + } + if (hasPattern == TRUE) { + forward_infer_pattern(&pb_graph_node->input_pins[i][j]); + backward_infer_pattern(&pb_graph_node->input_pins[i][j]); + } + } + } + + for (i = 0; i < pb_graph_node->num_output_ports; i++) { + for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { + hasPattern = FALSE; + for (k = 0; k < pb_graph_node->output_pins[i][j].num_output_edges; k++) { + for (m = 0; m < pb_graph_node->output_pins[i][j].output_edges[k]->num_pack_patterns; m++) { + hasPattern = TRUE; + index = add_pattern_name_to_hash(nhash, + pb_graph_node->output_pins[i][j].output_edges[k]->pack_pattern_names[m], + ncount); + if (pb_graph_node->output_pins[i][j].output_edges[k]->pack_pattern_indices == NULL) { + pb_graph_node->output_pins[i][j].output_edges[k]->pack_pattern_indices = (int*) my_malloc(pb_graph_node->output_pins[i][j].output_edges[k]->num_pack_patterns* sizeof(int)); + } + pb_graph_node->output_pins[i][j].output_edges[k]->pack_pattern_indices[m] = index; + } + } + if (hasPattern == TRUE) { + forward_infer_pattern(&pb_graph_node->output_pins[i][j]); + backward_infer_pattern(&pb_graph_node->output_pins[i][j]); + } + } + } + + for (i = 0; i < pb_graph_node->num_clock_ports; i++) { + for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { + hasPattern = FALSE; + for (k = 0; k < pb_graph_node->clock_pins[i][j].num_output_edges; k++) { + for (m = 0; m < pb_graph_node->clock_pins[i][j].output_edges[k]->num_pack_patterns; m++) { + hasPattern = TRUE; + index = add_pattern_name_to_hash(nhash, + pb_graph_node->clock_pins[i][j].output_edges[k]->pack_pattern_names[m], + ncount); + if (pb_graph_node->clock_pins[i][j].output_edges[k]->pack_pattern_indices == NULL) { + pb_graph_node->clock_pins[i][j].output_edges[k]->pack_pattern_indices = (int*) my_malloc(pb_graph_node->clock_pins[i][j].output_edges[k]->num_pack_patterns * sizeof(int)); + } + pb_graph_node->clock_pins[i][j].output_edges[k]->pack_pattern_indices[m] = index; + } + } + if (hasPattern == TRUE) { + forward_infer_pattern(&pb_graph_node->clock_pins[i][j]); + backward_infer_pattern(&pb_graph_node->clock_pins[i][j]); + } + } + } + + for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { + for (j = 0; j < pb_graph_node->pb_type->modes[i].num_pb_type_children; j++) { + for (k = 0; k < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; k++) { + discover_pattern_names_in_pb_graph_node(&pb_graph_node->child_pb_graph_nodes[i][j][k], nhash, ncount); + } + } + } +} + +/** + * In obvious cases where a pattern edge has only one path to go, set that path to be inferred + */ +static void forward_infer_pattern(INOUTP t_pb_graph_pin *pb_graph_pin) { + if (pb_graph_pin->num_output_edges == 1 && pb_graph_pin->output_edges[0]->num_pack_patterns == 0 && pb_graph_pin->output_edges[0]->infer_pattern == FALSE) { + pb_graph_pin->output_edges[0]->infer_pattern = TRUE; + if (pb_graph_pin->output_edges[0]->num_output_pins == 1) { + forward_infer_pattern(pb_graph_pin->output_edges[0]->output_pins[0]); + } + } +} +static void backward_infer_pattern(INOUTP t_pb_graph_pin *pb_graph_pin) { + if (pb_graph_pin->num_input_edges == 1 && pb_graph_pin->input_edges[0]->num_pack_patterns == 0 && pb_graph_pin->input_edges[0]->infer_pattern == FALSE) { + pb_graph_pin->input_edges[0]->infer_pattern = TRUE; + if (pb_graph_pin->input_edges[0]->num_input_pins == 1) { + backward_infer_pattern(pb_graph_pin->input_edges[0]->input_pins[0]); + } + } +} + +/** + * Allocates memory for models and loads the name of the packing pattern so that it can be identified and loaded with + * more complete information later + */ +static t_pack_patterns *alloc_and_init_pattern_list_from_hash(INP int ncount, + INOUTP struct s_hash **nhash) { + t_pack_patterns *nlist; + struct s_hash_iterator hash_iter; + struct s_hash *curr_pattern; + + nlist = (t_pack_patterns*)my_calloc(ncount, sizeof(t_pack_patterns)); + + hash_iter = start_hash_table_iterator(); + curr_pattern = get_next_hash(nhash, &hash_iter); + while (curr_pattern != NULL) { + assert(nlist[curr_pattern->index].name == NULL); + nlist[curr_pattern->index].name = my_strdup(curr_pattern->name); + nlist[curr_pattern->index].root_block = NULL; + nlist[curr_pattern->index].is_chain = FALSE; + nlist[curr_pattern->index].index = curr_pattern->index; + curr_pattern = get_next_hash(nhash, &hash_iter); + } + return nlist; +} + +void free_list_of_pack_patterns(INP t_pack_patterns *list_of_pack_patterns, INP int num_packing_patterns) { + int i, j, num_pack_pattern_blocks; + t_pack_pattern_block **pattern_block_list; + if (list_of_pack_patterns != NULL) { + for (i = 0; i < num_packing_patterns; i++) { + num_pack_pattern_blocks = list_of_pack_patterns[i].num_blocks; + pattern_block_list = (t_pack_pattern_block **)my_calloc(num_pack_pattern_blocks, sizeof(t_pack_pattern_block *)); + free(list_of_pack_patterns[i].name); + free(list_of_pack_patterns[i].is_block_optional); + free_pack_pattern(list_of_pack_patterns[i].root_block, pattern_block_list); + for (j = 0; j < num_pack_pattern_blocks; j++) { + free(pattern_block_list[j]); + } + free(pattern_block_list); + } + free(list_of_pack_patterns); + } +} + +/** + * Locate first edge that belongs to pattern index + */ +static t_pb_graph_edge * find_expansion_edge_of_pattern(INP int pattern_index, + INP t_pb_graph_node *pb_graph_node) { + int i, j, k, m; + t_pb_graph_edge * edge; + /* Iterate over all edges to discover if an edge in current physical block belongs to a pattern + If edge does, then return that edge + */ + + if (pb_graph_node == NULL) { + return NULL; + } + + for (i = 0; i < pb_graph_node->num_input_ports; i++) { + for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { + for (k = 0; k < pb_graph_node->input_pins[i][j].num_output_edges; k++) { + for (m = 0; m < pb_graph_node->input_pins[i][j].output_edges[k]->num_pack_patterns; m++) { + if (pb_graph_node->input_pins[i][j].output_edges[k]->pack_pattern_indices[m] == pattern_index) { + return pb_graph_node->input_pins[i][j].output_edges[k]; + } + } + } + } + } + + for (i = 0; i < pb_graph_node->num_output_ports; i++) { + for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { + for (k = 0; k < pb_graph_node->output_pins[i][j].num_output_edges; k++) { + for (m = 0; m < pb_graph_node->output_pins[i][j].output_edges[k]->num_pack_patterns; m++) { + if (pb_graph_node->output_pins[i][j].output_edges[k]->pack_pattern_indices[m] == pattern_index) { + return pb_graph_node->output_pins[i][j].output_edges[k]; + } + } + } + } + } + + for (i = 0; i < pb_graph_node->num_clock_ports; i++) { + for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { + for (k = 0; k < pb_graph_node->clock_pins[i][j].num_output_edges; k++) { + for (m = 0; m < pb_graph_node->clock_pins[i][j].output_edges[k]->num_pack_patterns; m++) { + if (pb_graph_node->clock_pins[i][j].output_edges[k]->pack_pattern_indices[m] == pattern_index) { + return pb_graph_node->clock_pins[i][j].output_edges[k]; + } + } + } + } + } + /* Xifan TANG's note: Go recursively downto the children pb_graph_node*/ + for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { + for (j = 0; j < pb_graph_node->pb_type->modes[i].num_pb_type_children; j++) { + for (k = 0; k < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; k++) { + edge = find_expansion_edge_of_pattern(pattern_index, &pb_graph_node->child_pb_graph_nodes[i][j][k]); + if (edge != NULL) { + return edge; + } + } + } + } + return NULL; +} + +/** + * Find if receiver of edge is in the same pattern, if yes, add to pattern + * Convention: Connections are made on backward expansion only (to make future multi-fanout support easier) so this function will not update connections + */ +static void forward_expand_pack_pattern_from_edge( + INP t_pb_graph_edge* expansion_edge, + INOUTP t_pack_patterns *list_of_packing_patterns, + INP int curr_pattern_index, INP int *L_num_blocks, INOUTP boolean make_root_of_chain) { + int i, j, k; + int iport, ipin, iedge; + boolean found; /* Error checking, ensure only one fan-out for each pattern net */ + t_pack_pattern_block *destination_block = NULL; + t_pb_graph_node *destination_pb_graph_node = NULL; + + found = expansion_edge->infer_pattern; + for (i = 0; !found && i < expansion_edge->num_pack_patterns; i++) { + if (expansion_edge->pack_pattern_indices[i] == curr_pattern_index) { + found = TRUE; + } + } + if (!found) { + return; + } + + found = FALSE; + for (i = 0; i < expansion_edge->num_output_pins; i++) { + if (expansion_edge->output_pins[i]->parent_node->pb_type->num_modes == 0) { + destination_pb_graph_node = expansion_edge->output_pins[i]->parent_node; + assert(found == FALSE); + /* Check assumption that each forced net has only one fan-out */ + /* This is the destination node */ + found = TRUE; + + /* If this pb_graph_node is part not of the current pattern index, put it in and expand all its edges */ + if (destination_pb_graph_node->temp_scratch_pad == NULL + || ((t_pack_pattern_block*) destination_pb_graph_node->temp_scratch_pad)->pattern_index != curr_pattern_index) { + destination_block = (t_pack_pattern_block*)my_calloc(1, sizeof(t_pack_pattern_block)); + list_of_packing_patterns[curr_pattern_index].base_cost += compute_primitive_base_cost(destination_pb_graph_node); + destination_block->block_id = *L_num_blocks; + (*L_num_blocks)++; + destination_pb_graph_node->temp_scratch_pad = (void *) destination_block; + destination_block->pattern_index = curr_pattern_index; + destination_block->pb_type = destination_pb_graph_node->pb_type; + for (iport = 0; iport < destination_pb_graph_node->num_input_ports; iport++) { + for (ipin = 0; ipin < destination_pb_graph_node->num_input_pins[iport]; ipin++) { + for (iedge = 0; iedge < destination_pb_graph_node->input_pins[iport][ipin].num_input_edges; iedge++) { + backward_expand_pack_pattern_from_edge( + destination_pb_graph_node->input_pins[iport][ipin].input_edges[iedge], + list_of_packing_patterns, + curr_pattern_index, + &destination_pb_graph_node->input_pins[iport][ipin], + destination_block, L_num_blocks); + } + } + } + for (iport = 0; iport < destination_pb_graph_node->num_output_ports; iport++) { + for (ipin = 0; ipin < destination_pb_graph_node->num_output_pins[iport]; ipin++) { + for (iedge = 0; iedge < destination_pb_graph_node->output_pins[iport][ipin].num_output_edges; iedge++) { + forward_expand_pack_pattern_from_edge( + destination_pb_graph_node->output_pins[iport][ipin].output_edges[iedge], + list_of_packing_patterns, + curr_pattern_index, L_num_blocks, FALSE); + } + } + } + for (iport = 0; iport < destination_pb_graph_node->num_clock_ports; iport++) { + for (ipin = 0;ipin < destination_pb_graph_node->num_clock_pins[iport]; ipin++) { + for (iedge = 0; iedge < destination_pb_graph_node->clock_pins[iport][ipin].num_input_edges; iedge++) { + backward_expand_pack_pattern_from_edge( + destination_pb_graph_node->clock_pins[iport][ipin].input_edges[iedge], + list_of_packing_patterns, + curr_pattern_index, + &destination_pb_graph_node->clock_pins[iport][ipin], + destination_block, L_num_blocks); + } + } + } + } + if (((t_pack_pattern_block*) destination_pb_graph_node->temp_scratch_pad)->pattern_index == curr_pattern_index) { + if(make_root_of_chain == TRUE) { + list_of_packing_patterns[curr_pattern_index].chain_root_pin = expansion_edge->output_pins[i]; + list_of_packing_patterns[curr_pattern_index].root_block = destination_block; + } + } + } else { + for (j = 0; j < expansion_edge->output_pins[i]->num_output_edges; j++) { + if (expansion_edge->output_pins[i]->output_edges[j]->infer_pattern == TRUE) { + forward_expand_pack_pattern_from_edge( + expansion_edge->output_pins[i]->output_edges[j], + list_of_packing_patterns, curr_pattern_index, + L_num_blocks, make_root_of_chain); + } else { + for (k = 0; k < expansion_edge->output_pins[i]->output_edges[j]->num_pack_patterns; k++) { + if (expansion_edge->output_pins[i]->output_edges[j]->pack_pattern_indices[k] == curr_pattern_index) { + if (found == FALSE) { + assert(found == FALSE); + } + /* Check assumption that each forced net has only one fan-out */ + found = TRUE; + forward_expand_pack_pattern_from_edge( + expansion_edge->output_pins[i]->output_edges[j], + list_of_packing_patterns, + curr_pattern_index, L_num_blocks, make_root_of_chain); + } + } + } + } + } + } + +} + +/** + * Find if driver of edge is in the same pattern, if yes, add to pattern + * Convention: Connections are made on backward expansion only (to make future multi-fanout support easier) so this function must update both source and destination blocks + */ +static void backward_expand_pack_pattern_from_edge( + INP t_pb_graph_edge* expansion_edge, + INOUTP t_pack_patterns *list_of_packing_patterns, + INP int curr_pattern_index, INP t_pb_graph_pin *destination_pin, + INP t_pack_pattern_block *destination_block, INP int *L_num_blocks) { + int i, j, k; + int iport, ipin, iedge; + boolean found; /* Error checking, ensure only one fan-out for each pattern net */ + t_pack_pattern_block *source_block = NULL; + t_pb_graph_node *source_pb_graph_node = NULL; + t_pack_pattern_connections *pack_pattern_connection = NULL; + + found = expansion_edge->infer_pattern; + for (i = 0; !found && i < expansion_edge->num_pack_patterns; i++) { + if (expansion_edge->pack_pattern_indices[i] == curr_pattern_index) { + found = TRUE; + } + } + if (!found) { + return; + } + + found = FALSE; + for (i = 0; i < expansion_edge->num_input_pins; i++) { + if (expansion_edge->input_pins[i]->parent_node->pb_type->num_modes == 0) { + source_pb_graph_node = expansion_edge->input_pins[i]->parent_node; + assert(found == FALSE); + /* Check assumption that each forced net has only one fan-out */ + /* This is the source node for destination */ + found = TRUE; + + /* If this pb_graph_node is part not of the current pattern index, put it in and expand all its edges */ + source_block = (t_pack_pattern_block*) source_pb_graph_node->temp_scratch_pad; + if (source_block == NULL + || source_block->pattern_index != curr_pattern_index) { + source_block = (t_pack_pattern_block *)my_calloc(1, sizeof(t_pack_pattern_block)); + source_block->block_id = *L_num_blocks; + (*L_num_blocks)++; + list_of_packing_patterns[curr_pattern_index].base_cost += compute_primitive_base_cost(source_pb_graph_node); + source_pb_graph_node->temp_scratch_pad = (void *) source_block; + source_block->pattern_index = curr_pattern_index; + source_block->pb_type = source_pb_graph_node->pb_type; + + if (list_of_packing_patterns[curr_pattern_index].root_block == NULL) { + list_of_packing_patterns[curr_pattern_index].root_block = source_block; + } + + for (iport = 0; iport < source_pb_graph_node->num_input_ports; iport++) { + for (ipin = 0; ipin < source_pb_graph_node->num_input_pins[iport]; ipin++) { + for (iedge = 0; iedge < source_pb_graph_node->input_pins[iport][ipin].num_input_edges; iedge++) { + backward_expand_pack_pattern_from_edge( + source_pb_graph_node->input_pins[iport][ipin].input_edges[iedge], + list_of_packing_patterns, + curr_pattern_index, + &source_pb_graph_node->input_pins[iport][ipin], + source_block, L_num_blocks); + } + } + } + for (iport = 0; iport < source_pb_graph_node->num_output_ports; iport++) { + for (ipin = 0; ipin < source_pb_graph_node->num_output_pins[iport]; ipin++) { + for (iedge = 0; iedge < source_pb_graph_node->output_pins[iport][ipin].num_output_edges; iedge++) { + forward_expand_pack_pattern_from_edge( + source_pb_graph_node->output_pins[iport][ipin].output_edges[iedge], + list_of_packing_patterns, + curr_pattern_index, L_num_blocks, FALSE); + } + } + } + for (iport = 0; iport < source_pb_graph_node->num_clock_ports; iport++) { + for (ipin = 0; ipin < source_pb_graph_node->num_clock_pins[iport]; ipin++) { + for (iedge = 0; iedge < source_pb_graph_node->clock_pins[iport][ipin].num_input_edges; iedge++) { + backward_expand_pack_pattern_from_edge( + source_pb_graph_node->clock_pins[iport][ipin].input_edges[iedge], + list_of_packing_patterns, + curr_pattern_index, + &source_pb_graph_node->clock_pins[iport][ipin], + source_block, L_num_blocks); + } + } + } + } + if (destination_pin != NULL) { + assert(((t_pack_pattern_block*)source_pb_graph_node->temp_scratch_pad)->pattern_index == curr_pattern_index); + source_block = (t_pack_pattern_block*) source_pb_graph_node->temp_scratch_pad; + pack_pattern_connection = (t_pack_pattern_connections *)my_calloc(1, sizeof(t_pack_pattern_connections)); + pack_pattern_connection->from_block = source_block; + pack_pattern_connection->from_pin = expansion_edge->input_pins[i]; + pack_pattern_connection->to_block = destination_block; + pack_pattern_connection->to_pin = destination_pin; + pack_pattern_connection->next = source_block->connections; + source_block->connections = pack_pattern_connection; + + pack_pattern_connection = (t_pack_pattern_connections *)my_calloc(1, sizeof(t_pack_pattern_connections)); + pack_pattern_connection->from_block = source_block; + pack_pattern_connection->from_pin = expansion_edge->input_pins[i]; + pack_pattern_connection->to_block = destination_block; + pack_pattern_connection->to_pin = destination_pin; + pack_pattern_connection->next = destination_block->connections; + destination_block->connections = pack_pattern_connection; + + if (source_block == destination_block) { + vpr_printf(TIO_MESSAGE_ERROR, "Invalid packing pattern defined. Source and destination block are the same (%s).\n", + source_block->pb_type->name); + } + } + } else { + if(expansion_edge->input_pins[i]->num_input_edges == 0) { + if(expansion_edge->input_pins[i]->parent_node->pb_type->parent_mode == NULL) { + /* This pack pattern extends to CLB input pin, thus it extends across multiple logic blocks, treat as a chain */ + list_of_packing_patterns[curr_pattern_index].is_chain = TRUE; + forward_expand_pack_pattern_from_edge( + expansion_edge, + list_of_packing_patterns, + curr_pattern_index, L_num_blocks, TRUE); + } + } else { + for (j = 0; j < expansion_edge->input_pins[i]->num_input_edges; j++) { + if (expansion_edge->input_pins[i]->input_edges[j]->infer_pattern == TRUE) { + backward_expand_pack_pattern_from_edge( + expansion_edge->input_pins[i]->input_edges[j], + list_of_packing_patterns, curr_pattern_index, + destination_pin, destination_block, L_num_blocks); + } else { + for (k = 0; k < expansion_edge->input_pins[i]->input_edges[j]->num_pack_patterns; k++) { + if (expansion_edge->input_pins[i]->input_edges[j]->pack_pattern_indices[k] == curr_pattern_index) { + if (found == FALSE) { + assert(found == FALSE); + } + /* Check assumption that each forced net has only one fan-out */ + found = TRUE; + backward_expand_pack_pattern_from_edge( + expansion_edge->input_pins[i]->input_edges[j], + list_of_packing_patterns, + curr_pattern_index, destination_pin, + destination_block, L_num_blocks); + } + } + } + } + } + } + } +} + +/** + * Pre-pack atoms in netlist to molecules + * 1. Single atoms are by definition a molecule. + * 2. Forced pack molecules are groupings of atoms that matches a t_pack_pattern definition. + * 3. Chained molecules are molecules that follow a carry-chain style pattern: ie. a single linear chain that can be split across multiple complex blocks + */ +t_pack_molecule *alloc_and_load_pack_molecules( + INP t_pack_patterns *list_of_pack_patterns, + INP int num_packing_patterns, OUTP int *num_pack_molecule) { + int i, j, best_pattern; + t_pack_molecule *list_of_molecules_head; + t_pack_molecule *cur_molecule; + boolean *is_used; + + is_used = (boolean*)my_calloc(num_packing_patterns, sizeof(boolean)); + + cur_molecule = list_of_molecules_head = NULL; + + /* Find forced pack patterns */ + /* Simplifying assumptions: Each atom can map to at most one molecule, use first-fit mapping based on priority of pattern */ + /* TODO: Need to investigate better mapping strategies than first-fit */ + for (i = 0; i < num_packing_patterns; i++) { + best_pattern = 0; + for(j = 1; j < num_packing_patterns; j++) { + if(is_used[best_pattern]) { + best_pattern = j; + } else if (is_used[j] == FALSE && compare_pack_pattern(&list_of_pack_patterns[j], &list_of_pack_patterns[best_pattern]) == 1) { + best_pattern = j; + } + } + assert(is_used[best_pattern] == FALSE); + is_used[best_pattern] = TRUE; + for (j = 0; j < num_logical_blocks; j++) { + cur_molecule = try_create_molecule(list_of_pack_patterns, best_pattern, j); + if (cur_molecule != NULL) { + cur_molecule->next = list_of_molecules_head; + /* In the event of multiple molecules with the same logical block pattern, bias to use the molecule with less costly physical resources first */ + /* TODO: Need to normalize magical number 100 */ + cur_molecule->base_gain = cur_molecule->num_blocks - (cur_molecule->pack_pattern->base_cost / 100); + list_of_molecules_head = cur_molecule; + if(logical_block[j].packed_molecules == NULL || logical_block[j].packed_molecules->data_vptr != cur_molecule) { + /* molecule did not cover current atom (possibly because molecule created is part of a long chain that extends past multiple logic blocks), try again */ + j--; + } + } + } + } + free(is_used); + + /* List all logical blocks as a molecule for blocks that do not belong to any molecules. + This allows the packer to be consistent as it now packs molecules only instead of atoms and molecules + + If a block belongs to a molecule, then carrying the single atoms around can make the packing problem + more difficult because now it needs to consider splitting molecules. + */ + for (i = 0; i < num_logical_blocks; i++) { + logical_block[i].expected_lowest_cost_primitive = get_expected_lowest_cost_primitive_for_logical_block(i); + if (logical_block[i].packed_molecules == NULL) { + cur_molecule = (t_pack_molecule*) my_calloc(1, + sizeof(t_pack_molecule)); + cur_molecule->valid = TRUE; + cur_molecule->type = MOLECULE_SINGLE_ATOM; + cur_molecule->num_blocks = 1; + cur_molecule->root = 0; + cur_molecule->num_ext_inputs = logical_block[i].used_input_pins; + cur_molecule->chain_pattern = NULL; + cur_molecule->pack_pattern = NULL; + cur_molecule->logical_block_ptrs = (t_logical_block**) my_malloc(1 * sizeof(t_logical_block*)); + cur_molecule->logical_block_ptrs[0] = &logical_block[i]; + cur_molecule->next = list_of_molecules_head; + cur_molecule->base_gain = 1; + list_of_molecules_head = cur_molecule; + + logical_block[i].packed_molecules = (struct s_linked_vptr*) my_calloc(1, + sizeof(struct s_linked_vptr)); + logical_block[i].packed_molecules->data_vptr = (void*) cur_molecule; + } + } + + if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_PRE_PACKING_MOLECULES_AND_PATTERNS)) { + print_pack_molecules(getEchoFileName(E_ECHO_PRE_PACKING_MOLECULES_AND_PATTERNS), + list_of_pack_patterns, num_packing_patterns, + list_of_molecules_head); + } + + return list_of_molecules_head; +} + + +static void free_pack_pattern(INOUTP t_pack_pattern_block *pattern_block, INOUTP t_pack_pattern_block **pattern_block_list) { + t_pack_pattern_connections *connection, *next; + if (pattern_block->block_id == OPEN) { + /* already traversed, return */ + return; + } + pattern_block_list[pattern_block->block_id] = pattern_block; + pattern_block->block_id = OPEN; + connection = pattern_block->connections; + while (connection) { + free_pack_pattern(connection->from_block, pattern_block_list); + free_pack_pattern(connection->to_block, pattern_block_list); + next = connection->next; + free(connection); + connection = next; + } +} + +/** + * Given a pattern and a logical block to serve as the root block, determine if the candidate logical block serving as the root node matches the pattern + * If yes, return the molecule with this logical block as the root, if not, return NULL + * Limitations: Currently assumes that forced pack nets must be single-fanout as this covers all the reasonable architectures we wanted + More complicated structures should probably be handled either downstream (general packing) or upstream (in tech mapping) + * If this limitation is too constraining, code is designed so that this limitation can be removed + * Side Effect: If successful, link atom to molecule + */ +static t_pack_molecule *try_create_molecule( + INP t_pack_patterns *list_of_pack_patterns, INP int pack_pattern_index, + INP int block_index) { + int i; + t_pack_molecule *molecule; + struct s_linked_vptr *molecule_linked_list; + + molecule = (t_pack_molecule*)my_calloc(1, sizeof(t_pack_molecule)); + molecule->valid = TRUE; + molecule->type = MOLECULE_FORCED_PACK; + molecule->pack_pattern = &list_of_pack_patterns[pack_pattern_index]; + molecule->logical_block_ptrs = (t_logical_block **)my_calloc(molecule->pack_pattern->num_blocks, + sizeof(t_logical_block *)); + molecule->num_blocks = list_of_pack_patterns[pack_pattern_index].num_blocks; + molecule->root = list_of_pack_patterns[pack_pattern_index].root_block->block_id; + molecule->num_ext_inputs = 0; + + if(list_of_pack_patterns[pack_pattern_index].is_chain == TRUE) { + /* A chain pattern extends beyond a single logic block so we must find the block_index that matches with the portion of a chain for this particular logic block */ + block_index = find_new_root_atom_for_chain(block_index, &list_of_pack_patterns[pack_pattern_index]); + } + + if (block_index != OPEN && try_expand_molecule(molecule, block_index, molecule->pack_pattern->root_block) == TRUE) { + /* Success! commit module */ + for (i = 0; i < molecule->pack_pattern->num_blocks; i++) { + if(molecule->logical_block_ptrs[i] == NULL) { + assert(list_of_pack_patterns[pack_pattern_index].is_block_optional[i] == TRUE); + continue; + } + molecule_linked_list = (struct s_linked_vptr*) my_calloc(1, sizeof(struct s_linked_vptr)); + molecule_linked_list->data_vptr = (void *) molecule; + molecule_linked_list->next = molecule->logical_block_ptrs[i]->packed_molecules; + molecule->logical_block_ptrs[i]->packed_molecules = molecule_linked_list; + } + } else { + /* Does not match pattern, free molecule */ + free(molecule->logical_block_ptrs); + free(molecule); + molecule = NULL; + } + + return molecule; +} + +/** + * Determine if logical block can match with the pattern to form a molecule + * return TRUE if it matches, return FALSE otherwise + */ +static boolean try_expand_molecule(INOUTP t_pack_molecule *molecule, + INP int logical_block_index, + INP t_pack_pattern_block *current_pattern_block) { + int iport, ipin, inet; + boolean success; + boolean is_optional; + boolean *is_block_optional; + t_pack_pattern_connections *cur_pack_pattern_connection; + is_block_optional = molecule->pack_pattern->is_block_optional; + is_optional = is_block_optional[current_pattern_block->block_id]; + + /* If the block in the pattern has already been visited, then there is no need to revisit it */ + if (molecule->logical_block_ptrs[current_pattern_block->block_id] != NULL) { + if (molecule->logical_block_ptrs[current_pattern_block->block_id] + != &logical_block[logical_block_index]) { + /* Mismatch between the visited block and the current block implies that the current netlist structure does not match the expected pattern, return whether or not this matters */ + return is_optional; + } else { + molecule->num_ext_inputs--; /* This block is revisited, implies net is entirely internal to molecule, reduce count */ + return TRUE; + } + } + + /* This node has never been visited */ + /* Simplifying assumption: An atom can only map to one molecule */ + if(logical_block[logical_block_index].packed_molecules != NULL) { + /* This block is already in a molecule, return whether or not this matters */ + return is_optional; + } + + if (primitive_type_feasible(logical_block_index, + current_pattern_block->pb_type)) { + + success = TRUE; + /* If the primitive types match, store it, expand it and explore neighbouring nodes */ + molecule->logical_block_ptrs[current_pattern_block->block_id] = + &logical_block[logical_block_index]; /* store that this node has been visited */ + molecule->num_ext_inputs += + logical_block[logical_block_index].used_input_pins; + + cur_pack_pattern_connection = current_pattern_block->connections; + while (cur_pack_pattern_connection != NULL && success == TRUE) { + if (cur_pack_pattern_connection->from_block + == current_pattern_block) { + /* find net corresponding to pattern */ + iport = + cur_pack_pattern_connection->from_pin->port->model_port->index; + ipin = cur_pack_pattern_connection->from_pin->pin_number; + inet = + logical_block[logical_block_index].output_nets[iport][ipin]; + + /* Check if net is valid */ + if (inet == OPEN || vpack_net[inet].num_sinks != 1) { /* One fanout assumption */ + success = is_block_optional[cur_pack_pattern_connection->to_block->block_id]; + } else { + success = try_expand_molecule(molecule, + vpack_net[inet].node_block[1], + cur_pack_pattern_connection->to_block); + } + } else { + assert( + cur_pack_pattern_connection->to_block == current_pattern_block); + /* find net corresponding to pattern */ + iport = + cur_pack_pattern_connection->to_pin->port->model_port->index; + ipin = cur_pack_pattern_connection->to_pin->pin_number; + if (cur_pack_pattern_connection->to_pin->port->model_port->is_clock) { + inet = logical_block[logical_block_index].clock_net; + } else { + inet = + logical_block[logical_block_index].input_nets[iport][ipin]; + } + /* Check if net is valid */ + if (inet == OPEN || vpack_net[inet].num_sinks != 1) { /* One fanout assumption */ + success = is_block_optional[cur_pack_pattern_connection->from_block->block_id]; + } else { + success = try_expand_molecule(molecule, + vpack_net[inet].node_block[0], + cur_pack_pattern_connection->from_block); + } + } + cur_pack_pattern_connection = cur_pack_pattern_connection->next; + } + } else { + success = is_optional; + } + + return success; +} + +static void print_pack_molecules(INP const char *fname, + INP t_pack_patterns *list_of_pack_patterns, INP int num_pack_patterns, + INP t_pack_molecule *list_of_molecules) { + int i; + FILE *fp; + t_pack_molecule *list_of_molecules_current; + + fp = my_fopen(fname, "w", 0); + fprintf(fp, "# of pack patterns %d\n", num_pack_patterns); + + for (i = 0; i < num_pack_patterns; i++) { + fprintf(fp, "pack pattern index %d block count %d name %s root %s\n", + list_of_pack_patterns[i].index, + list_of_pack_patterns[i].num_blocks, + list_of_pack_patterns[i].name, + list_of_pack_patterns[i].root_block->pb_type->name); + } + + list_of_molecules_current = list_of_molecules; + while (list_of_molecules_current != NULL) { + if (list_of_molecules_current->type == MOLECULE_SINGLE_ATOM) { + fprintf(fp, "\nmolecule type: atom\n"); + fprintf(fp, "\tpattern index %d: logical block [%d] name %s\n", i, + list_of_molecules_current->logical_block_ptrs[0]->index, + list_of_molecules_current->logical_block_ptrs[0]->name); + } else if (list_of_molecules_current->type == MOLECULE_FORCED_PACK) { + fprintf(fp, "\nmolecule type: %s\n", + list_of_molecules_current->pack_pattern->name); + for (i = 0; i < list_of_molecules_current->pack_pattern->num_blocks; + i++) { + if(list_of_molecules_current->logical_block_ptrs[i] == NULL) { + fprintf(fp, "\tpattern index %d: empty \n", i); + } else { + fprintf(fp, "\tpattern index %d: logical block [%d] name %s", + i, + list_of_molecules_current->logical_block_ptrs[i]->index, + list_of_molecules_current->logical_block_ptrs[i]->name); + if(list_of_molecules_current->pack_pattern->root_block->block_id == i) { + fprintf(fp, " root node\n"); + } else { + fprintf(fp, "\n"); + } + } + } + } else { + assert(0); + } + list_of_molecules_current = list_of_molecules_current->next; + } + + fclose(fp); +} + +/* Search through all primitives and return the lowest cost primitive that fits this logical block */ +static t_pb_graph_node *get_expected_lowest_cost_primitive_for_logical_block(INP int ilogical_block) { + int i; + float cost, best_cost; + t_pb_graph_node *current, *best; + + best_cost = UNDEFINED; + best = NULL; + current = NULL; + for(i = 0; i < num_types; i++) { + cost = UNDEFINED; + current = get_expected_lowest_cost_primitive_for_logical_block_in_pb_graph_node(ilogical_block, type_descriptors[i].pb_graph_head, &cost); + if(cost != UNDEFINED) { + if(best_cost == UNDEFINED || best_cost > cost) { + best_cost = cost; + best = current; + } + } + } + return best; +} + +static t_pb_graph_node *get_expected_lowest_cost_primitive_for_logical_block_in_pb_graph_node(INP int ilogical_block, INP t_pb_graph_node *curr_pb_graph_node, OUTP float *cost) { + t_pb_graph_node *best, *cur; + float cur_cost, best_cost; + int i, j; + + best = NULL; + best_cost = UNDEFINED; + if(curr_pb_graph_node == NULL) { + return NULL; + } + + if(curr_pb_graph_node->pb_type->blif_model != NULL) { + if(primitive_type_feasible(ilogical_block, curr_pb_graph_node->pb_type)) { + cur_cost = compute_primitive_base_cost(curr_pb_graph_node); + if(best_cost == UNDEFINED || best_cost > cur_cost) { + best_cost = cur_cost; + best = curr_pb_graph_node; + } + } + } else { + for(i = 0; i < curr_pb_graph_node->pb_type->num_modes; i++) { + for(j = 0; j < curr_pb_graph_node->pb_type->modes[i].num_pb_type_children; j++) { + *cost = UNDEFINED; + cur = get_expected_lowest_cost_primitive_for_logical_block_in_pb_graph_node(ilogical_block, &curr_pb_graph_node->child_pb_graph_nodes[i][j][0], cost); + if(cur != NULL) { + if(best == NULL || best_cost > *cost) { + best = cur; + best_cost = *cost; + } + } + } + } + } + + *cost = best_cost; + return best; +} + + +/* Determine which of two pack pattern should take priority */ +static int compare_pack_pattern(const t_pack_patterns *pattern_a, const t_pack_patterns *pattern_b) { + float base_gain_a, base_gain_b, diff; + + /* Bigger patterns should take higher priority than smaller patterns because they are harder to fit */ + if (pattern_a->num_blocks > pattern_b->num_blocks) { + return 1; + } else if (pattern_a->num_blocks < pattern_b->num_blocks) { + return -1; + } + + base_gain_a = pattern_a->base_cost; + base_gain_b = pattern_b->base_cost; + diff = base_gain_a - base_gain_b; + + /* Less costly patterns should be used before more costly patterns */ + if (diff < 0) { + return 1; + } + if (diff > 0) { + return -1; + } + return 0; +} + +/* A chain can extend across multiple logic blocks. Must segment the chain to fit in a logic block by identifying the actual atom that forms the root of the new chain. + * Returns OPEN if this block_index doesn't match up with any chain + * + * Assumes that the root of a chain is the primitive that starts the chain or is driven from outside the logic block + * block_index: index of current atom + * list_of_pack_pattern: ptr to current chain pattern + */ +static int find_new_root_atom_for_chain(INP int block_index, INP t_pack_patterns *list_of_pack_pattern) { + int new_index = OPEN; + t_pb_graph_pin *root_ipin; + t_pb_graph_node *root_pb_graph_node; + t_model_ports *model_port; + int driver_net, driver_block; + + assert(list_of_pack_pattern->is_chain == TRUE); + root_ipin = list_of_pack_pattern->chain_root_pin; + root_pb_graph_node = root_ipin->parent_node; + + if(primitive_type_feasible(block_index, root_pb_graph_node->pb_type) == FALSE) { + return OPEN; + } + + /* Xifan TANG: this is trying to find the root logical_block which is the head of a carry chain */ + /* Assign driver furthest up the chain that matches the root node and is unassigned to a molecule as the root */ + model_port = root_ipin->port->model_port; + driver_net = logical_block[block_index].input_nets[model_port->index][root_ipin->pin_number]; + if(driver_net == OPEN) { + /* The current block is the furthest up the chain, return it */ + return block_index; + } + + /* Xifan TANG: this is trying to find a possible starting logical block, whose preceding block is already assigned + * to another molecule + */ + driver_block = vpack_net[driver_net].node_block[0]; + if(logical_block[driver_block].packed_molecules != NULL) { + /* Driver is used/invalid, so current block is the furthest up the chain, return it */ + return block_index; + } + + new_index = find_new_root_atom_for_chain(driver_block, list_of_pack_pattern); + if(new_index == OPEN) { + return block_index; + } else { + return new_index; + } +} + + + diff --git a/vpr7_rram/vpr/SRC/pack/prepack.h b/vpr7_rram/vpr/SRC/pack/prepack.h new file mode 100644 index 000000000..bcb0d06c8 --- /dev/null +++ b/vpr7_rram/vpr/SRC/pack/prepack.h @@ -0,0 +1,19 @@ +/* + Prepacking: Group together technology-mapped netlist blocks before packing. This gives hints to the packer on what groups of blocks to keep together during packing. + Primary use 1) "Forced" packs (eg LUT+FF pair) + 2) Carry-chains + */ + +#ifndef PREPACK_H +#define PREPACK_H +#include "arch_types.h" +#include "util.h" + +t_pack_patterns *alloc_and_load_pack_patterns(OUTP int *num_packing_patterns); +void free_list_of_pack_patterns(INP t_pack_patterns *list_of_pack_patterns, INP int num_packing_patterns); + +t_pack_molecule *alloc_and_load_pack_molecules( + INP t_pack_patterns *list_of_pack_patterns, + INP int num_packing_patterns, OUTP int *num_pack_molecule); + +#endif diff --git a/vpr7_rram/vpr/SRC/pack/print_netlist.c b/vpr7_rram/vpr/SRC/pack/print_netlist.c new file mode 100644 index 000000000..2ce39550e --- /dev/null +++ b/vpr7_rram/vpr/SRC/pack/print_netlist.c @@ -0,0 +1,103 @@ +#include +#include +#include +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "print_netlist.h" +#include "read_xml_arch_file.h" + +/******************** Subroutines local to this module ***********************/ + +static void print_pinnum(FILE * fp, int pinnum); + +/********************* Subroutine definitions ********************************/ + +void print_netlist(char *foutput, char *net_file) { + + /* Prints out the netlist related data structures into the file * + * fname. */ + + int i, j, max_pin; + int num_global_nets; + int L_num_p_inputs, L_num_p_outputs; + FILE *fp; + + num_global_nets = 0; + L_num_p_inputs = 0; + L_num_p_outputs = 0; + + /* Count number of global nets */ + for (i = 0; i < num_nets; i++) { + if (clb_net[i].is_global) { + num_global_nets++; + } + } + + /* Count I/O input and output pads */ + for (i = 0; i < num_blocks; i++) { + if (block[i].type == IO_TYPE) { + for (j = 0; j < IO_TYPE->num_pins; j++) { + if (block[i].nets[j] != OPEN) { + if (IO_TYPE->class_inf[IO_TYPE->pin_class[j]].type + == DRIVER) { + L_num_p_inputs++; + } else { + assert( + IO_TYPE-> class_inf[IO_TYPE-> pin_class[j]]. type == RECEIVER); + L_num_p_outputs++; + } + } + } + } + } + + fp = my_fopen(foutput, "w", 0); + + fprintf(fp, "Input netlist file: %s\n", net_file); + fprintf(fp, "L_num_p_inputs: %d, L_num_p_outputs: %d, num_clbs: %d\n", + L_num_p_inputs, L_num_p_outputs, num_blocks); + fprintf(fp, "num_blocks: %d, num_nets: %d, num_globals: %d\n", num_blocks, + num_nets, num_global_nets); + fprintf(fp, "\nNet\tName\t\t#Pins\tDriver\t\tRecvs. (block, pin)\n"); + + for (i = 0; i < num_nets; i++) { + fprintf(fp, "\n%d\t%s\t", i, clb_net[i].name); + if (strlen(clb_net[i].name) < 8) + fprintf(fp, "\t"); /* Name field is 16 chars wide */ + fprintf(fp, "%d", clb_net[i].num_sinks + 1); + for (j = 0; j <= clb_net[i].num_sinks; j++) + fprintf(fp, "\t(%4d,%4d)", clb_net[i].node_block[j], + clb_net[i].node_block_pin[j]); + } + + fprintf(fp, "\nBlock\tName\t\tType\tPin Connections\n\n"); + + for (i = 0; i < num_blocks; i++) { + fprintf(fp, "\n%d\t%s\t", i, block[i].name); + if (strlen(block[i].name) < 8) + fprintf(fp, "\t"); /* Name field is 16 chars wide */ + fprintf(fp, "%s", block[i].type->name); + + max_pin = block[i].type->num_pins; + + for (j = 0; j < max_pin; j++) + print_pinnum(fp, block[i].nets[j]); + } + + fprintf(fp, "\n"); + + /* TODO: Print out pb info */ + + fclose(fp); +} + +static void print_pinnum(FILE * fp, int pinnum) { + + /* This routine prints out either OPEN or the pin number, to file fp. */ + + if (pinnum == OPEN) + fprintf(fp, "\tOPEN"); + else + fprintf(fp, "\t%d", pinnum); +} diff --git a/vpr7_rram/vpr/SRC/pack/print_netlist.h b/vpr7_rram/vpr/SRC/pack/print_netlist.h new file mode 100644 index 000000000..9d42a380b --- /dev/null +++ b/vpr7_rram/vpr/SRC/pack/print_netlist.h @@ -0,0 +1 @@ +void print_netlist(char *foutput, char *net_file); diff --git a/vpr7_rram/vpr/SRC/place/place.c b/vpr7_rram/vpr/SRC/place/place.c new file mode 100755 index 000000000..95cab13f3 --- /dev/null +++ b/vpr7_rram/vpr/SRC/place/place.c @@ -0,0 +1,3188 @@ +/*#include */ +#include +#include +#include +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "place.h" +#include "read_place.h" +#include "draw.h" +#include "place_and_route.h" +#include "net_delay.h" +#include "path_delay.h" +#include "timing_place_lookup.h" +#include "timing_place.h" +#include "place_stats.h" +#include "read_xml_arch_file.h" +#include "ReadOptions.h" +#include "vpr_utils.h" +#include "place_macro.h" + +/************** Types and defines local to place.c ***************************/ + +/* Cut off for incremental bounding box updates. * + * 4 is fastest -- I checked. */ +/* To turn off incremental bounding box updates, set this to a huge value */ +#define SMALL_NET 4 + +/* This defines the error tolerance for floating points variables used in * + * cost computation. 0.01 means that there is a 1% error tolerance. */ +#define ERROR_TOL .01 + +/* This defines the maximum number of swap attempts before invoking the * + * once-in-a-while placement legality check as well as floating point * + * variables round-offs check. */ +#define MAX_MOVES_BEFORE_RECOMPUTE 50000 + +/* The maximum number of tries when trying to place a carry chain at a * + * random location before trying exhaustive placement - find the fist * + * legal position and place it during initial placement. */ +#define MAX_NUM_TRIES_TO_PLACE_MACROS_RANDOMLY 4 + +/* Flags for the states of the bounding box. * + * Stored as char for memory efficiency. */ +#define NOT_UPDATED_YET 'N' +#define UPDATED_ONCE 'U' +#define GOT_FROM_SCRATCH 'S' + +/* For comp_cost. NORMAL means use the method that generates updateable * + * bounding boxes for speed. CHECK means compute all bounding boxes from * + * scratch using a very simple routine to allow checks of the other * + * costs. */ +enum cost_methods { + NORMAL, CHECK +}; + +/* This is for the placement swap routines. A swap attempt could be * + * rejected, accepted or aborted (due to the limitations placed on the * + * carry chain support at this point). */ +enum swap_result { + REJECTED, ACCEPTED, ABORTED +}; + +#define MAX_INV_TIMING_COST 1.e9 +/* Stops inverse timing cost from going to infinity with very lax timing constraints, +which avoids multiplying by a gigantic inverse_prev_timing_cost when auto-normalizing. +The exact value of this cost has relatively little impact, but should not be +large enough to be on the order of timing costs for normal constraints. */ + +/********************** Data Sturcture Definition ***************************/ +/* Stores the information of the move for a block that is * + * moved during placement * + * block_num: the index of the moved block * + * xold: the x_coord that the block is moved from * + * xnew: the x_coord that the block is moved to * + * yold: the y_coord that the block is moved from * + * xnew: the x_coord that the block is moved to * + */ +typedef struct s_pl_moved_block { + int block_num; + int xold; + int xnew; + int yold; + int ynew; + int zold; + int znew; + int swapped_to_empty; +}t_pl_moved_block; + +/* Stores the list of blocks to be moved in a swap during * + * placement. * + * num_moved_blocks: total number of blocks moved when * + * swapping two blocks. * + * moved blocks: a list of moved blocks data structure with * + * information on the move. * + * [0...num_moved_blocks-1] * + */ +typedef struct s_pl_blocks_to_be_moved { + int num_moved_blocks; + t_pl_moved_block * moved_blocks; +}t_pl_blocks_to_be_moved; + + +/********************** Variables local to place.c ***************************/ + +/* Cost of a net, and a temporary cost of a net used during move assessment. */ +static float *net_cost = NULL, *temp_net_cost = NULL; /* [0..num_nets-1] */ + +/* legal positions for type */ +typedef struct s_legal_pos { + int x; + int y; + int z; +}t_legal_pos; + +static t_legal_pos **legal_pos = NULL; /* [0..num_types-1][0..type_tsize - 1] */ +static int *num_legal_pos = NULL; /* [0..num_legal_pos-1] */ + +/* [0...num_nets-1] * + * A flag array to indicate whether the specific bounding box has been updated * + * in this particular swap or not. If it has been updated before, the code * + * must use the updated data, instead of the out-of-date data passed into the * + * subroutine, particularly used in try_swap(). The value NOT_UPDATED_YET * + * indicates that the net has not been updated before, UPDATED_ONCE indicated * + * that the net has been updated once, if it is going to be updated again, the * + * values from the previous update must be used. GOT_FROM_SCRATCH is only * + * applicable for nets larger than SMALL_NETS and it indicates that the * + * particular bounding box cannot be updated incrementally before, hence the * + * bounding box is got from scratch, so the bounding box would definitely be * + * right, DO NOT update again. * + * [0...num_nets-1] */ +static char * bb_updated_before = NULL; + +/* [0..num_nets-1][1..num_pins-1]. What is the value of the timing */ +/* driven portion of the cost function. These arrays will be set to */ +/* (criticality * delay) for each point to point connection. */ +static float **point_to_point_timing_cost = NULL; +static float **temp_point_to_point_timing_cost = NULL; + +/* [0..num_nets-1][1..num_pins-1]. What is the value of the delay */ +/* for each connection in the circuit */ +static float **point_to_point_delay_cost = NULL; +static float **temp_point_to_point_delay_cost = NULL; + +/* [0..num_blocks-1][0..pins_per_clb-1]. Indicates which pin on the net */ +/* this block corresponds to, this is only required during timing-driven */ +/* placement. It is used to allow us to update individual connections on */ +/* each net */ +static int **net_pin_index = NULL; + +/* [0..num_nets-1]. Store the bounding box coordinates and the number of * + * blocks on each of a net's bounding box (to allow efficient updates), * + * respectively. */ + +static struct s_bb *bb_coords = NULL, *bb_num_on_edges = NULL; + +/* Store the information on the blocks to be moved in a swap during * + * placement, in the form of array of structs instead of struct with * + * arrays for cache effifiency * + */ +static t_pl_blocks_to_be_moved blocks_affected; + +/* The arrays below are used to precompute the inverse of the average * + * number of tracks per channel between [subhigh] and [sublow]. Access * + * them as chan?_place_cost_fac[subhigh][sublow]. They are used to * + * speed up the computation of the cost function that takes the length * + * of the net bounding box in each dimension, divided by the average * + * number of tracks in that direction; for other cost functions they * + * will never be used. * + * [0...ny] [0...nx] */ +static float **chanx_place_cost_fac, **chany_place_cost_fac; + +/* The following arrays are used by the try_swap function for speed. */ +/* [0...num_nets-1] */ +static struct s_bb *ts_bb_coord_new = NULL; +static struct s_bb *ts_bb_edge_new = NULL; +static int *ts_nets_to_update = NULL; + +/* The pl_macros array stores all the carry chains placement macros. * + * [0...num_pl_macros-1] */ +static t_pl_macro * pl_macros = NULL; +static int num_pl_macros; + +/* These file-scoped variables keep track of the number of swaps * + * rejected, accepted or aborted. The total number of swap attempts * + * is the sum of the three number. */ +static int num_swap_rejected = 0; +static int num_swap_accepted = 0; +static int num_swap_aborted = 0; +static int num_ts_called = 0; + +/* Expected crossing counts for nets with different #'s of pins. From * + * ICCAD 94 pp. 690 - 695 (with linear interpolation applied by me). * + * Multiplied to bounding box of a net to better estimate wire length * + * for higher fanout nets. Each entry is the correction factor for the * + * fanout index-1 */ +static const float cross_count[50] = { /* [0..49] */1.0, 1.0, 1.0, 1.0828, 1.1536, 1.2206, 1.2823, 1.3385, 1.3991, 1.4493, 1.4974, + 1.5455, 1.5937, 1.6418, 1.6899, 1.7304, 1.7709, 1.8114, 1.8519, 1.8924, + 1.9288, 1.9652, 2.0015, 2.0379, 2.0743, 2.1061, 2.1379, 2.1698, 2.2016, + 2.2334, 2.2646, 2.2958, 2.3271, 2.3583, 2.3895, 2.4187, 2.4479, 2.4772, + 2.5064, 2.5356, 2.5610, 2.5864, 2.6117, 2.6371, 2.6625, 2.6887, 2.7148, + 2.7410, 2.7671, 2.7933 }; + +/********************* Static subroutines local to place.c *******************/ +#ifdef VERBOSE + static void print_clb_placement(const char *fname); +#endif + +static void alloc_and_load_placement_structs( + float place_cost_exp, float ***old_region_occ_x, + float ***old_region_occ_y, struct s_placer_opts placer_opts, + t_direct_inf *directs, int num_directs); + +static void alloc_and_load_try_swap_structs(); + +static void free_placement_structs( + float **old_region_occ_x, float **old_region_occ_y, + struct s_placer_opts placer_opts); + +static void alloc_and_load_for_fast_cost_update(float place_cost_exp); + +static void free_fast_cost_update(void); + +static void alloc_legal_placements(); +static void load_legal_placements(); + +static void free_legal_placements(); + +static int check_macro_can_be_placed(int imacro, int itype, int x, int y, int z); + +static int try_place_macro(int itype, int ichoice, int imacro, int * free_locations); + +static void initial_placement_pl_macros(int macros_max_num_tries, int * free_locations); + +static void initial_placement_blocks(int * free_locations, enum e_pad_loc_type pad_loc_type); + +static void initial_placement(enum e_pad_loc_type pad_loc_type, + char *pad_loc_file); + +static float comp_bb_cost(enum cost_methods method); + +static int setup_blocks_affected(int b_from, int x_to, int y_to, int z_to); + +static int find_affected_blocks(int b_from, int x_to, int y_to, int z_to); + +static enum swap_result try_swap(float t, float *cost, float *bb_cost, float *timing_cost, + float rlim, float **old_region_occ_x, + float **old_region_occ_y, + enum e_place_algorithm place_algorithm, float timing_tradeoff, + float inverse_prev_bb_cost, float inverse_prev_timing_cost, + float *delay_cost); + +static void check_place(float bb_cost, float timing_cost, + enum e_place_algorithm place_algorithm, + float delay_cost); + +static float starting_t(float *cost_ptr, float *bb_cost_ptr, + float *timing_cost_ptr, float **old_region_occ_x, + float **old_region_occ_y, + struct s_annealing_sched annealing_sched, int max_moves, float rlim, + enum e_place_algorithm place_algorithm, float timing_tradeoff, + float inverse_prev_bb_cost, float inverse_prev_timing_cost, + float *delay_cost_ptr); + +static void update_t(float *t, float std_dev, float rlim, float success_rat, + struct s_annealing_sched annealing_sched); + +static void update_rlim(float *rlim, float success_rat); + +static int exit_crit(float t, float cost, + struct s_annealing_sched annealing_sched); + +static int count_connections(void); + +static double get_std_dev(int n, double sum_x_squared, double av_x); + +static float recompute_bb_cost(void); + +static float comp_td_point_to_point_delay(int inet, int ipin); + +static void update_td_cost(void); + +static void comp_delta_td_cost(float *delta_timing, float *delta_delay); + +static void comp_td_costs(float *timing_cost, float *connection_delay_sum); + +static enum swap_result assess_swap(float delta_c, float t); + +static boolean find_to(int x_from, int y_from, t_type_ptr type, float rlim, int *x_to, int *y_to); + +static void get_non_updateable_bb(int inet, struct s_bb *bb_coord_new); + +static void update_bb(int inet, struct s_bb *bb_coord_new, + struct s_bb *bb_edge_new, int xold, int yold, int xnew, int ynew); + +static int find_affected_nets(int *nets_to_update); + +static float get_net_cost(int inet, struct s_bb *bb_ptr); + +static void get_bb_from_scratch(int inet, struct s_bb *coords, + struct s_bb *num_on_edges); + +static double get_net_wirelength_estimate(int inet, struct s_bb *bbptr); + +static void free_try_swap_arrays(void); + + +/*****************************************************************************/ +/* RESEARCH TODO: Bounding Box and rlim need to be redone for heterogeneous to prevent a QoR penalty */ +void try_place(struct s_placer_opts placer_opts, + struct s_annealing_sched annealing_sched, + t_chan_width_dist chan_width_dist, struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf, t_direct_inf *directs, int num_directs) { + + /* Does almost all the work of placing a circuit. Width_fac gives the * + * width of the widest channel. Place_cost_exp says what exponent the * + * width should be taken to when calculating costs. This allows a * + * greater bias for anisotropic architectures. */ + + int tot_iter, inner_iter, success_sum, move_lim, moves_since_cost_recompute, width_fac, + num_connections, inet, ipin, outer_crit_iter_count, inner_crit_iter_count, + inner_recompute_limit, swap_result; + float t, success_rat, rlim, cost, timing_cost, bb_cost, new_bb_cost, new_timing_cost, + delay_cost, new_delay_cost, place_delay_value, inverse_prev_bb_cost, inverse_prev_timing_cost, + oldt, **old_region_occ_x, **old_region_occ_y, **net_delay = NULL, crit_exponent, + first_rlim, final_rlim, inverse_delta_rlim, critical_path_delay = UNDEFINED, + **remember_net_delay_original_ptr; /*used to free net_delay if it is re-assigned */ + double av_cost, av_bb_cost, av_timing_cost, av_delay_cost, sum_of_squares, std_dev; + int total_swap_attempts; + float reject_rate; + float accept_rate; + float abort_rate; + char msg[BUFSIZE]; + t_slack * slacks = NULL; + + /* Allocated here because it goes into timing critical code where each memory allocation is expensive */ + + remember_net_delay_original_ptr = NULL; /*prevents compiler warning */ + + /* init file scope variables */ + num_swap_rejected = 0; + num_swap_accepted = 0; + num_swap_aborted = 0; + num_ts_called = 0; + + if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE + || placer_opts.place_algorithm == PATH_TIMING_DRIVEN_PLACE + || placer_opts.enable_timing_computations) { + /*do this before the initial placement to avoid messing up the initial placement */ + slacks = alloc_lookups_and_criticalities(chan_width_dist, router_opts, + det_routing_arch, segment_inf, timing_inf, &net_delay, directs, num_directs); + + remember_net_delay_original_ptr = net_delay; + + /*#define PRINT_LOWER_BOUND */ +#ifdef PRINT_LOWER_BOUND + /*print the crit_path, assuming delay between blocks that are* + *block_dist apart*/ + + if (placer_opts.block_dist <= nx) + place_delay_value = + delta_clb_to_clb[placer_opts.block_dist][0]; + else if (placer_opts.block_dist <= ny) + place_delay_value = + delta_clb_to_clb[0][placer_opts.block_dist]; + else + place_delay_value = delta_clb_to_clb[nx][ny]; + + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "Lower bound assuming delay of %g\n", place_delay_value); + + load_constant_net_delay(net_delay, place_delay_value); + load_timing_graph_net_delays(net_delay); + do_timing_analysis(slacks, FALSE, FALSE, TRUE); + + if (getEchoEnabled()) { + if(isEchoFileEnabled(E_ECHO_PLACEMENT_CRITICAL_PATH)) + print_critical_path(getEchoFileName(E_ECHO_PLACEMENT_CRITICAL_PATH)); + if(isEchoFileEnabled(E_ECHO_PLACEMENT_LOWER_BOUND_SINK_DELAYS)) + print_sink_delays(getEchoFileName(E_ECHO_PLACEMENT_LOWER_BOUND_SINK_DELAYS)); + if(isEchoFileEnabled(E_ECHO_PLACEMENT_LOGIC_SINK_DELAYS)) + print_sink_delays(getEchoFileName(E_ECHO_PLACEMENT_LOGIC_SINK_DELAYS)); + } + + /*also print sink delays assuming 0 delay between blocks, + * this tells us how much logic delay is on each path */ + + load_constant_net_delay(net_delay, 0); + load_timing_graph_net_delays(net_delay); + do_timing_analysis(slacks, FALSE, FALSE, TRUE); + +#endif + + } + + width_fac = placer_opts.place_chan_width; + + init_chan(width_fac, chan_width_dist); + + alloc_and_load_placement_structs( + placer_opts.place_cost_exp, + &old_region_occ_x, &old_region_occ_y, placer_opts, + directs, num_directs); + + initial_placement(placer_opts.pad_loc_type, placer_opts.pad_loc_file); + init_draw_coords((float) width_fac); + + /* Storing the number of pins on each type of block makes the swap routine * + * slightly more efficient. */ + + /* Gets initial cost and loads bounding boxes. */ + + if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE + || placer_opts.place_algorithm == PATH_TIMING_DRIVEN_PLACE) { + bb_cost = comp_bb_cost(NORMAL); + + crit_exponent = placer_opts.td_place_exp_first; /*this will be modified when rlim starts to change */ + + num_connections = count_connections(); + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "There are %d point to point connections in this circuit.\n", num_connections); + vpr_printf(TIO_MESSAGE_INFO, "\n"); + + if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE) { + for (inet = 0; inet < num_nets; inet++) + for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) + timing_place_crit[inet][ipin] = 0; /*dummy crit values */ + + comp_td_costs(&timing_cost, &delay_cost); /*first pass gets delay_cost, which is used + * in criticality computations in the next call + * to comp_td_costs. */ + place_delay_value = delay_cost / num_connections; /*used for computing criticalities */ + load_constant_net_delay(net_delay, place_delay_value, clb_net, + num_nets); + + } else + place_delay_value = 0; + + if (placer_opts.place_algorithm == PATH_TIMING_DRIVEN_PLACE) { + net_delay = point_to_point_delay_cost; /*this keeps net_delay up to date with * + * *the same values that the placer is using * + * *point_to_point_delay_cost is computed each* + * *time that comp_td_costs is called, and is * + * *also updated after any swap is accepted */ + } + + load_timing_graph_net_delays(net_delay); + do_timing_analysis(slacks, FALSE, FALSE, FALSE); + load_criticalities(slacks, crit_exponent); + if (getEchoEnabled()) { + if(isEchoFileEnabled(E_ECHO_INITIAL_PLACEMENT_TIMING_GRAPH)) + print_timing_graph(getEchoFileName(E_ECHO_INITIAL_PLACEMENT_TIMING_GRAPH)); + if(isEchoFileEnabled(E_ECHO_INITIAL_PLACEMENT_SLACK)) + print_slack(slacks->slack, FALSE, getEchoFileName(E_ECHO_INITIAL_PLACEMENT_SLACK)); + if(isEchoFileEnabled(E_ECHO_INITIAL_PLACEMENT_CRITICALITY)) + print_criticality(slacks, FALSE, getEchoFileName(E_ECHO_INITIAL_PLACEMENT_CRITICALITY)); + } + outer_crit_iter_count = 1; + + /*now we can properly compute costs */ + comp_td_costs(&timing_cost, &delay_cost); /*also vpr_printf proper values into point_to_point_delay_cost */ + + inverse_prev_timing_cost = 1 / timing_cost; + inverse_prev_bb_cost = 1 / bb_cost; + cost = 1; /*our new cost function uses normalized values of */ + /*bb_cost and timing_cost, the value of cost will be reset */ + /*to 1 at each temperature when *_TIMING_DRIVEN_PLACE is true */ + } else { /*BOUNDING_BOX_PLACE */ + cost = bb_cost = comp_bb_cost(NORMAL); + timing_cost = 0; + delay_cost = 0; + place_delay_value = 0; + outer_crit_iter_count = 0; + num_connections = 0; + crit_exponent = 0; + + inverse_prev_timing_cost = 0; /*inverses not used */ + inverse_prev_bb_cost = 0; + } + + move_lim = (int) (annealing_sched.inner_num * pow(num_blocks, 1.3333)); + + if (placer_opts.inner_loop_recompute_divider != 0) + inner_recompute_limit = (int) (0.5 + + (float) move_lim + / (float) placer_opts.inner_loop_recompute_divider); + else + /*don't do an inner recompute */ + inner_recompute_limit = move_lim + 1; + + /* Sometimes I want to run the router with a random placement. Avoid * + * using 0 moves to stop division by 0 and 0 length vector problems, * + * by setting move_lim to 1 (which is still too small to do any * + * significant optimization). */ + + if (move_lim <= 0) + move_lim = 1; + + rlim = (float) std::max(nx + 1, ny + 1); + + first_rlim = rlim; /*used in timing-driven placement for exponent computation */ + final_rlim = 1; + inverse_delta_rlim = 1 / (first_rlim - final_rlim); + + t = starting_t(&cost, &bb_cost, &timing_cost, + old_region_occ_x, old_region_occ_y, + annealing_sched, move_lim, rlim, + placer_opts.place_algorithm, placer_opts.timing_tradeoff, + inverse_prev_bb_cost, inverse_prev_timing_cost, &delay_cost); + tot_iter = 0; + moves_since_cost_recompute = 0; + vpr_printf(TIO_MESSAGE_INFO, "Initial placement cost: %g bb_cost: %g td_cost: %g delay_cost: %g\n", + cost, bb_cost, timing_cost, delay_cost); + vpr_printf(TIO_MESSAGE_INFO, "\n"); + +#ifndef SPEC + vpr_printf(TIO_MESSAGE_INFO, "%9s %9s %11s %11s %11s %11s %8s %8s %7s %7s %7s %9s %7s\n", + "---------", "---------", "-----------", "-----------", "-----------", "-----------", + "--------", "--------", "-------", "-------", "-------", "---------", "-------"); + vpr_printf(TIO_MESSAGE_INFO, "%9s %9s %11s %11s %11s %11s %8s %8s %7s %7s %7s %9s %7s\n", + "T", "Cost", "Av BB Cost", "Av TD Cost", "Av Tot Del", + "P to P Del", "d_max", "Ac Rate", "Std Dev", "R limit", "Exp", + "Tot Moves", "Alpha"); + vpr_printf(TIO_MESSAGE_INFO, "%9s %9s %11s %11s %11s %11s %8s %8s %7s %7s %7s %9s %7s\n", + "---------", "---------", "-----------", "-----------", "-----------", "-----------", + "--------", "--------", "-------", "-------", "-------", "---------", "-------"); +#endif + + sprintf(msg, "Initial Placement. Cost: %g BB Cost: %g TD Cost %g Delay Cost: %g \t Channel Factor: %d", + cost, bb_cost, timing_cost, delay_cost, width_fac); + update_screen(MAJOR, msg, PLACEMENT, FALSE); + + while (exit_crit(t, cost, annealing_sched) == 0) { + + if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE + || placer_opts.place_algorithm == PATH_TIMING_DRIVEN_PLACE) { + cost = 1; + } + + av_cost = 0.; + av_bb_cost = 0.; + av_delay_cost = 0.; + av_timing_cost = 0.; + sum_of_squares = 0.; + success_sum = 0; + + if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE + || placer_opts.place_algorithm == PATH_TIMING_DRIVEN_PLACE) { + + if (outer_crit_iter_count >= placer_opts.recompute_crit_iter + || placer_opts.inner_loop_recompute_divider != 0) { +#ifdef VERBOSE + vpr_printf(TIO_MESSAGE_INFO, "Outer loop recompute criticalities\n"); +#endif + place_delay_value = delay_cost / num_connections; + + if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE) + load_constant_net_delay(net_delay, place_delay_value, + clb_net, num_nets); + /*note, for path_based, the net delay is not updated since it is current, + *because it accesses point_to_point_delay array */ + + load_timing_graph_net_delays(net_delay); + do_timing_analysis(slacks, FALSE, FALSE, FALSE); + load_criticalities(slacks, crit_exponent); + /*recompute costs from scratch, based on new criticalities */ + comp_td_costs(&timing_cost, &delay_cost); + outer_crit_iter_count = 0; + } + outer_crit_iter_count++; + + /*at each temperature change we update these values to be used */ + /*for normalizing the tradeoff between timing and wirelength (bb) */ + inverse_prev_bb_cost = 1 / bb_cost; + /*Prevent inverse timing cost from going to infinity */ + inverse_prev_timing_cost = std::min(1 / timing_cost, (float)MAX_INV_TIMING_COST); + } + + inner_crit_iter_count = 1; + + for (inner_iter = 0; inner_iter < move_lim; inner_iter++) { + swap_result = try_swap(t, &cost, &bb_cost, &timing_cost, rlim, + old_region_occ_x, + old_region_occ_y, + placer_opts.place_algorithm, placer_opts.timing_tradeoff, + inverse_prev_bb_cost, inverse_prev_timing_cost, &delay_cost); + if (swap_result == ACCEPTED) { + + /* Move was accepted. Update statistics that are useful for the annealing schedule. */ + success_sum++; + av_cost += cost; + av_bb_cost += bb_cost; + av_timing_cost += timing_cost; + av_delay_cost += delay_cost; + sum_of_squares += cost * cost; + num_swap_accepted++; + } else if (swap_result == ABORTED) { + num_swap_aborted++; + } else { // swap_result == REJECTED + num_swap_rejected++; + } + + + if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE + || placer_opts.place_algorithm + == PATH_TIMING_DRIVEN_PLACE) { + + /* Do we want to re-timing analyze the circuit to get updated slack and criticality values? + * We do this only once in a while, since it is expensive. + */ + if (inner_crit_iter_count >= inner_recompute_limit + && inner_iter != move_lim - 1) { /*on last iteration don't recompute */ + + inner_crit_iter_count = 0; +#ifdef VERBOSE + vpr_printf(TIO_MESSAGE_TRACE, "Inner loop recompute criticalities\n"); +#endif + if (placer_opts.place_algorithm + == NET_TIMING_DRIVEN_PLACE) { + /* Use a constant delay per connection as the delay estimate, rather than + * estimating based on the current placement. Not a great idea, but not the + * default. + */ + place_delay_value = delay_cost / num_connections; + load_constant_net_delay(net_delay, place_delay_value, + clb_net, num_nets); + } + + /* Using the delays in net_delay, do a timing analysis to update slacks and + * criticalities; then update the timing cost since it will change. + */ + load_timing_graph_net_delays(net_delay); + do_timing_analysis(slacks, FALSE, FALSE, FALSE); + load_criticalities(slacks, crit_exponent); + comp_td_costs(&timing_cost, &delay_cost); + } + inner_crit_iter_count++; + } +#ifdef VERBOSE + vpr_printf(TIO_MESSAGE_TRACE, "t = %g cost = %g bb_cost = %g timing_cost = %g move = %d dmax = %g\n", + t, cost, bb_cost, timing_cost, inner_iter, delay_cost); + if (fabs(bb_cost - comp_bb_cost(CHECK)) > bb_cost * ERROR_TOL) + exit(1); +#endif + } + + /* Lines below prevent too much round-off error from accumulating * + * in the cost over many iterations. This round-off can lead to * + * error checks failing because the cost is different from what * + * you get when you recompute from scratch. */ + + moves_since_cost_recompute += move_lim; + if (moves_since_cost_recompute > MAX_MOVES_BEFORE_RECOMPUTE) { + new_bb_cost = recompute_bb_cost(); + if (fabs(new_bb_cost - bb_cost) > bb_cost * ERROR_TOL) { + vpr_printf(TIO_MESSAGE_ERROR, "in try_place: new_bb_cost = %g, old bb_cost = %g\n", + new_bb_cost, bb_cost); + exit(1); + } + bb_cost = new_bb_cost; + + if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE + || placer_opts.place_algorithm + == PATH_TIMING_DRIVEN_PLACE) { + comp_td_costs(&new_timing_cost, &new_delay_cost); + if (fabs(new_timing_cost - timing_cost) > timing_cost * ERROR_TOL) { + vpr_printf(TIO_MESSAGE_ERROR, "in try_place: new_timing_cost = %g, old timing_cost = %g\n", + new_timing_cost, timing_cost); + exit(1); + } + if (fabs(new_delay_cost - delay_cost) > delay_cost * ERROR_TOL) { + vpr_printf(TIO_MESSAGE_ERROR, "in try_place: new_delay_cost = %g, old delay_cost = %g\n", + new_delay_cost, delay_cost); + exit(1); + } + timing_cost = new_timing_cost; + } + + if (placer_opts.place_algorithm == BOUNDING_BOX_PLACE) { + cost = new_bb_cost; + } + moves_since_cost_recompute = 0; + } + + tot_iter += move_lim; + success_rat = ((float) success_sum) / move_lim; + if (success_sum == 0) { + av_cost = cost; + av_bb_cost = bb_cost; + av_timing_cost = timing_cost; + av_delay_cost = delay_cost; + } else { + av_cost /= success_sum; + av_bb_cost /= success_sum; + av_timing_cost /= success_sum; + av_delay_cost /= success_sum; + } + std_dev = get_std_dev(success_sum, sum_of_squares, av_cost); + + oldt = t; /* for finding and printing alpha. */ + update_t(&t, std_dev, rlim, success_rat, annealing_sched); + +#ifndef SPEC + critical_path_delay = get_critical_path_delay(); + vpr_printf(TIO_MESSAGE_INFO, "%9.5f %9.5g %11.6g %11.6g %11.6g %11.6g %8.4f %8.4f %7.4f %7.4f %7.4f %9d %7.4f\n", + oldt, av_cost, av_bb_cost, av_timing_cost, av_delay_cost, place_delay_value, + critical_path_delay, success_rat, std_dev, rlim, crit_exponent, tot_iter, t / oldt); +#endif + + sprintf(msg, "Cost: %g BB Cost %g TD Cost %g Temperature: %g", + cost, bb_cost, timing_cost, t); + update_screen(MINOR, msg, PLACEMENT, FALSE); + update_rlim(&rlim, success_rat); + + if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE + || placer_opts.place_algorithm == PATH_TIMING_DRIVEN_PLACE) { + crit_exponent = (1 - (rlim - final_rlim) * inverse_delta_rlim) + * (placer_opts.td_place_exp_last + - placer_opts.td_place_exp_first) + + placer_opts.td_place_exp_first; + } +#ifdef VERBOSE + if (getEchoEnabled()) { + print_clb_placement("first_iteration_clb_placement.echo"); + } +#endif + } + + t = 0; /* freeze out */ + av_cost = 0.; + av_bb_cost = 0.; + av_timing_cost = 0.; + sum_of_squares = 0.; + av_delay_cost = 0.; + success_sum = 0; + + if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE + || placer_opts.place_algorithm == PATH_TIMING_DRIVEN_PLACE) { + /*at each temperature change we update these values to be used */ + /*for normalizing the tradeoff between timing and wirelength (bb) */ + if (outer_crit_iter_count >= placer_opts.recompute_crit_iter + || placer_opts.inner_loop_recompute_divider != 0) { + +#ifdef VERBOSE + vpr_printf(TIO_MESSAGE_INFO, "Outer loop recompute criticalities\n"); +#endif + place_delay_value = delay_cost / num_connections; + + if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE) + load_constant_net_delay(net_delay, place_delay_value, clb_net, + num_nets); + + load_timing_graph_net_delays(net_delay); + do_timing_analysis(slacks, FALSE, FALSE, FALSE); + load_criticalities(slacks, crit_exponent); + /*recompute criticaliies */ + comp_td_costs(&timing_cost, &delay_cost); + outer_crit_iter_count = 0; + } + outer_crit_iter_count++; + + inverse_prev_bb_cost = 1 / (bb_cost); + /*Prevent inverse timing cost from going to infinity */ + inverse_prev_timing_cost = std::min(1 / timing_cost, (float)MAX_INV_TIMING_COST); + } + + inner_crit_iter_count = 1; + + for (inner_iter = 0; inner_iter < move_lim; inner_iter++) { + swap_result = try_swap(t, &cost, &bb_cost, &timing_cost, rlim, + old_region_occ_x, old_region_occ_y, + placer_opts.place_algorithm, placer_opts.timing_tradeoff, + inverse_prev_bb_cost, inverse_prev_timing_cost, &delay_cost); + + if (swap_result == ACCEPTED) { + success_sum++; + av_cost += cost; + av_bb_cost += bb_cost; + av_delay_cost += delay_cost; + av_timing_cost += timing_cost; + sum_of_squares += cost * cost; + + if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE + || placer_opts.place_algorithm + == PATH_TIMING_DRIVEN_PLACE) { + + if (inner_crit_iter_count >= inner_recompute_limit + && inner_iter != move_lim - 1) { + + inner_crit_iter_count = 0; +#ifdef VERBOSE + vpr_printf(TIO_MESSAGE_TRACE, "Inner loop recompute criticalities\n"); +#endif + if (placer_opts.place_algorithm + == NET_TIMING_DRIVEN_PLACE) { + place_delay_value = delay_cost / num_connections; + load_constant_net_delay(net_delay, place_delay_value, + clb_net, num_nets); + } + + load_timing_graph_net_delays(net_delay); + do_timing_analysis(slacks, FALSE, FALSE, FALSE); + load_criticalities(slacks, crit_exponent); + comp_td_costs(&timing_cost, &delay_cost); + } + inner_crit_iter_count++; + } + num_swap_accepted++; + } else if (swap_result == ABORTED) { + num_swap_aborted++; + } else { + num_swap_rejected++; + } + +#ifdef VERBOSE + vpr_printf(TIO_MESSAGE_INFO, "t = %g, cost = %g, move = %d\n", t, cost, tot_iter); +#endif + } + tot_iter += move_lim; + success_rat = ((float) success_sum) / move_lim; + if (success_sum == 0) { + av_cost = cost; + av_bb_cost = bb_cost; + av_delay_cost = delay_cost; + av_timing_cost = timing_cost; + } else { + av_cost /= success_sum; + av_bb_cost /= success_sum; + av_delay_cost /= success_sum; + av_timing_cost /= success_sum; + } + + std_dev = get_std_dev(success_sum, sum_of_squares, av_cost); + +#ifndef SPEC + vpr_printf(TIO_MESSAGE_INFO, "%9.5f %9.5g %11.6g %11.6g %11.6g %11.6g %8s %8.4f %7.4f %7.4f %7.4f %9d\n", + t, av_cost, av_bb_cost, av_timing_cost, av_delay_cost, place_delay_value, + " ", success_rat, std_dev, rlim, crit_exponent, tot_iter); +#endif + + // TODO: + // 1. print a message about number of aborted moves. + // 2. add some subroutine hierarchy! Too big! + // 3. put statistics counters (av_cost, success_sum, etc.) in a struct so a + // pointer to it can be passed around. + +#ifdef VERBOSE + if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_END_CLB_PLACEMENT)) { + print_clb_placement(getEchoFileName(E_ECHO_END_CLB_PLACEMENT)); + } +#endif + + check_place(bb_cost, timing_cost, + placer_opts.place_algorithm, delay_cost); + + if (placer_opts.enable_timing_computations + && placer_opts.place_algorithm == BOUNDING_BOX_PLACE) { + /*need this done since the timing data has not been kept up to date* + *in bounding_box mode */ + for (inet = 0; inet < num_nets; inet++) + for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) + timing_place_crit[inet][ipin] = 0; /*dummy crit values */ + comp_td_costs(&timing_cost, &delay_cost); /*computes point_to_point_delay_cost */ + } + + if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE + || placer_opts.place_algorithm == PATH_TIMING_DRIVEN_PLACE + || placer_opts.enable_timing_computations) { + net_delay = point_to_point_delay_cost; /*this makes net_delay up to date with * + *the same values that the placer is using*/ + load_timing_graph_net_delays(net_delay); + + do_timing_analysis(slacks, FALSE, FALSE, FALSE); + + if (getEchoEnabled()) { + if(isEchoFileEnabled(E_ECHO_PLACEMENT_SINK_DELAYS)) + print_sink_delays(getEchoFileName(E_ECHO_PLACEMENT_SINK_DELAYS)); + if(isEchoFileEnabled(E_ECHO_FINAL_PLACEMENT_SLACK)) + print_slack(slacks->slack, FALSE, getEchoFileName(E_ECHO_FINAL_PLACEMENT_SLACK)); + if(isEchoFileEnabled(E_ECHO_FINAL_PLACEMENT_CRITICALITY)) + print_criticality(slacks, FALSE, getEchoFileName(E_ECHO_FINAL_PLACEMENT_CRITICALITY)); + if(isEchoFileEnabled(E_ECHO_FINAL_PLACEMENT_TIMING_GRAPH)) + print_timing_graph(getEchoFileName(E_ECHO_FINAL_PLACEMENT_TIMING_GRAPH)); + if(isEchoFileEnabled(E_ECHO_PLACEMENT_CRIT_PATH)) + print_critical_path(getEchoFileName(E_ECHO_PLACEMENT_CRIT_PATH)); + } + + /* Print critical path delay. */ + critical_path_delay = get_critical_path_delay(); + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "Placement estimated critical path delay: %g ns\n", critical_path_delay); + } + + sprintf(msg, "Placement. Cost: %g bb_cost: %g td_cost: %g Channel Factor: %d", + cost, bb_cost, timing_cost, width_fac); + vpr_printf(TIO_MESSAGE_INFO, "Placement cost: %g, bb_cost: %g, td_cost: %g, delay_cost: %g\n", + cost, bb_cost, timing_cost, delay_cost); + update_screen(MAJOR, msg, PLACEMENT, FALSE); + + // Print out swap statistics + total_swap_attempts = num_swap_rejected + num_swap_accepted + num_swap_aborted; + reject_rate = num_swap_rejected / total_swap_attempts; + accept_rate = num_swap_accepted / total_swap_attempts; + abort_rate = num_swap_aborted / total_swap_attempts; + vpr_printf(TIO_MESSAGE_INFO, "Placement total # of swap attempts: %d\n", total_swap_attempts); + vpr_printf(TIO_MESSAGE_INFO, "\tSwap reject rate: %g\n", reject_rate); + vpr_printf(TIO_MESSAGE_INFO, "\tSwap accept rate: %g\n", accept_rate); + vpr_printf(TIO_MESSAGE_INFO, "\tSwap abort rate: %g\n", abort_rate); + + +#ifdef SPEC + vpr_printf(TIO_MESSAGE_INFO, "Total moves attempted: %d.0\n", tot_iter); +#endif + + free_placement_structs( + old_region_occ_x, old_region_occ_y, + placer_opts); + if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE + || placer_opts.place_algorithm == PATH_TIMING_DRIVEN_PLACE + || placer_opts.enable_timing_computations) { + + net_delay = remember_net_delay_original_ptr; + free_lookups_and_criticalities(&net_delay, slacks); + } + + free_try_swap_arrays(); +} + +static int count_connections() { + /*only count non-global connections */ + + int count, inet; + + count = 0; + + for (inet = 0; inet < num_nets; inet++) { + + if (clb_net[inet].is_global) + continue; + + count += clb_net[inet].num_sinks; + } + return (count); +} + +static double get_std_dev(int n, double sum_x_squared, double av_x) { + + /* Returns the standard deviation of data set x. There are n sample points, * + * sum_x_squared is the summation over n of x^2 and av_x is the average x. * + * All operations are done in double precision, since round off error can be * + * a problem in the initial temp. std_dev calculation for big circuits. */ + + double std_dev; + + if (n <= 1) + std_dev = 0.; + else + std_dev = (sum_x_squared - n * av_x * av_x) / (double) (n - 1); + + if (std_dev > 0.) /* Very small variances sometimes round negative */ + std_dev = sqrt(std_dev); + else + std_dev = 0.; + + return (std_dev); +} + +static void update_rlim(float *rlim, float success_rat) { + + /* Update the range limited to keep acceptance prob. near 0.44. Use * + * a floating point rlim to allow gradual transitions at low temps. */ + + float upper_lim; + + *rlim = (*rlim) * (1. - 0.44 + success_rat); + upper_lim = std::max(nx + 1, ny + 1); + *rlim = std::min(*rlim, upper_lim); + *rlim = std::max(*rlim, (float)1.); +} + +/* Update the temperature according to the annealing schedule selected. */ +static void update_t(float *t, float std_dev, float rlim, float success_rat, + struct s_annealing_sched annealing_sched) { + + /* float fac; */ + + if (annealing_sched.type == USER_SCHED) { + *t = annealing_sched.alpha_t * (*t); + } + + /* Old standard deviation based stuff is below. This bogs down horribly + * for big circuits (alu4 and especially bigkey_mod). */ + /* #define LAMBDA .7 */ + /* ------------------------------------ */ +#if 0 + else if (std_dev == 0.) + { + *t = 0.; + } + else + { + fac = exp(-LAMBDA * (*t) / std_dev); + fac = max(0.5, fac); + *t = (*t) * fac; + } +#endif + /* ------------------------------------- */ + + else { /* AUTO_SCHED */ + if (success_rat > 0.96) { + *t = (*t) * 0.5; + } else if (success_rat > 0.8) { + *t = (*t) * 0.9; + } else if (success_rat > 0.15 || rlim > 1.) { + *t = (*t) * 0.95; + } else { + *t = (*t) * 0.8; + } + } +} + +static int exit_crit(float t, float cost, + struct s_annealing_sched annealing_sched) { + + /* Return 1 when the exit criterion is met. */ + + if (annealing_sched.type == USER_SCHED) { + if (t < annealing_sched.exit_t) { + return (1); + } else { + return (0); + } + } + + /* Automatic annealing schedule */ + + if (t < 0.005 * cost / num_nets) { + return (1); + } else { + return (0); + } +} + +static float starting_t(float *cost_ptr, float *bb_cost_ptr, + float *timing_cost_ptr, float **old_region_occ_x, + float **old_region_occ_y, + struct s_annealing_sched annealing_sched, int max_moves, float rlim, + enum e_place_algorithm place_algorithm, float timing_tradeoff, + float inverse_prev_bb_cost, float inverse_prev_timing_cost, + float *delay_cost_ptr) { + + /* Finds the starting temperature (hot condition). */ + + int i, num_accepted, move_lim, swap_result; + double std_dev, av, sum_of_squares; /* Double important to avoid round off */ + + if (annealing_sched.type == USER_SCHED) + return (annealing_sched.init_t); + + move_lim = std::min(max_moves, num_blocks); + + num_accepted = 0; + av = 0.; + sum_of_squares = 0.; + + /* Try one move per block. Set t high so essentially all accepted. */ + + for (i = 0; i < move_lim; i++) { + swap_result = try_swap(HUGE_POSITIVE_FLOAT, cost_ptr, bb_cost_ptr, timing_cost_ptr, rlim, + old_region_occ_x, old_region_occ_y, + place_algorithm, timing_tradeoff, + inverse_prev_bb_cost, inverse_prev_timing_cost, delay_cost_ptr); + + if (swap_result == ACCEPTED) { + num_accepted++; + av += *cost_ptr; + sum_of_squares += *cost_ptr * (*cost_ptr); + num_swap_accepted++; + } else if (swap_result == ABORTED) { + num_swap_aborted++; + } else { + num_swap_rejected++; + } + } + + if (num_accepted != 0) + av /= num_accepted; + else + av = 0.; + + std_dev = get_std_dev(num_accepted, sum_of_squares, av); + +#ifdef DEBUG + if (num_accepted != move_lim) { + vpr_printf(TIO_MESSAGE_WARNING, "Starting t: %d of %d configurations accepted.\n", num_accepted, move_lim); + } +#endif + +#ifdef VERBOSE + vpr_printf(TIO_MESSAGE_INFO, "std_dev: %g, average cost: %g, starting temp: %g\n", std_dev, av, 20. * std_dev); +#endif + + /* Set the initial temperature to 20 times the standard of deviation */ + /* so that the initial temperature adjusts according to the circuit */ + return (20. * std_dev); +} + + +static int setup_blocks_affected(int b_from, int x_to, int y_to, int z_to) { + + /* Find all the blocks affected when b_from is swapped with b_to. + * Returns abort_swap. */ + + int imoved_blk, imacro; + int x_from, y_from, z_from, b_to; + int abort_swap = FALSE; + + /* Xifan TANG: support swap between macros */ + /* int from_macro; */ + + x_from = block[b_from].x; + y_from = block[b_from].y; + z_from = block[b_from].z; + + b_to = grid[x_to][y_to].blocks[z_to]; + + // Check whether the to_location is empty + if (b_to == EMPTY) { + + // Swap the block, dont swap the nets yet + block[b_from].x = x_to; + block[b_from].y = y_to; + block[b_from].z = z_to; + + // Sets up the blocks moved + imoved_blk = blocks_affected.num_moved_blocks; + blocks_affected.moved_blocks[imoved_blk].block_num = b_from; + blocks_affected.moved_blocks[imoved_blk].xold = x_from; + blocks_affected.moved_blocks[imoved_blk].xnew = x_to; + blocks_affected.moved_blocks[imoved_blk].yold = y_from; + blocks_affected.moved_blocks[imoved_blk].ynew = y_to; + blocks_affected.moved_blocks[imoved_blk].zold = z_from; + blocks_affected.moved_blocks[imoved_blk].znew = z_to; + blocks_affected.moved_blocks[imoved_blk].swapped_to_empty = TRUE; + blocks_affected.num_moved_blocks ++; + + } else { + + // Does not allow a swap with a macro yet + /* Xifan TANG: allow macro swapping...*/ + get_imacro_from_iblk(&imacro, b_to, pl_macros, num_pl_macros); + /* get_imacro_from_iblk(&from_macro, b_from, pl_macros, num_pl_macros); + if (((-1 != from_macro)||(imacro != -1)) + &&(!((-1 != from_macro)&&(imacro != -1)))) { + */ + if (imacro != -1) { + abort_swap = TRUE; + return (abort_swap); + } + + // Swap the block, dont swap the nets yet + block[b_to].x = x_from; + block[b_to].y = y_from; + block[b_to].z = z_from; + + block[b_from].x = x_to; + block[b_from].y = y_to; + block[b_from].z = z_to; + + // Sets up the blocks moved + imoved_blk = blocks_affected.num_moved_blocks; + blocks_affected.moved_blocks[imoved_blk].block_num = b_from; + blocks_affected.moved_blocks[imoved_blk].xold = x_from; + blocks_affected.moved_blocks[imoved_blk].xnew = x_to; + blocks_affected.moved_blocks[imoved_blk].yold = y_from; + blocks_affected.moved_blocks[imoved_blk].ynew = y_to; + blocks_affected.moved_blocks[imoved_blk].zold = z_from; + blocks_affected.moved_blocks[imoved_blk].znew = z_to; + blocks_affected.moved_blocks[imoved_blk].swapped_to_empty = FALSE; + blocks_affected.num_moved_blocks ++; + + imoved_blk = blocks_affected.num_moved_blocks; + blocks_affected.moved_blocks[imoved_blk].block_num = b_to; + blocks_affected.moved_blocks[imoved_blk].xold = x_to; + blocks_affected.moved_blocks[imoved_blk].xnew = x_from; + blocks_affected.moved_blocks[imoved_blk].yold = y_to; + blocks_affected.moved_blocks[imoved_blk].ynew = y_from; + blocks_affected.moved_blocks[imoved_blk].zold = z_to; + blocks_affected.moved_blocks[imoved_blk].znew = z_from; + blocks_affected.moved_blocks[imoved_blk].swapped_to_empty = FALSE; + blocks_affected.num_moved_blocks ++; + + } // Finish swapping the blocks and setting up blocks_affected + + return (abort_swap); + +} + +static int find_affected_blocks(int b_from, int x_to, int y_to, int z_to) { + + /* Finds and set ups the affected_blocks array. + * Returns abort_swap. */ + + int imacro, imember; + int x_swap_offset, y_swap_offset, z_swap_offset, x_from, y_from, z_from, b_to; + int curr_b_from, curr_x_from, curr_y_from, curr_z_from, curr_b_to, curr_x_to, curr_y_to, curr_z_to; + int abort_swap = FALSE; + + /* int to_imacro;*/ /* Xifan TANG: for more checking */ + + x_from = block[b_from].x; + y_from = block[b_from].y; + z_from = block[b_from].z; + + b_to = grid[x_to][y_to].blocks[z_to]; + + get_imacro_from_iblk(&imacro, b_from, pl_macros, num_pl_macros); + if ( imacro != -1) { + // b_from is part of a macro, I need to swap the whole macro + + // Record down the relative position of the swap + x_swap_offset = x_to - x_from; + y_swap_offset = y_to - y_from; + z_swap_offset = z_to - z_from; + + for (imember = 0; imember < pl_macros[imacro].num_blocks && abort_swap == FALSE; imember++) { + + // Gets the new from and to info for every block in the macro + // cannot use the old from and to info + curr_b_from = pl_macros[imacro].members[imember].blk_index; + + curr_x_from = block[curr_b_from].x; + curr_y_from = block[curr_b_from].y; + curr_z_from = block[curr_b_from].z; + + curr_x_to = curr_x_from + x_swap_offset; + curr_y_to = curr_y_from + y_swap_offset; + curr_z_to = curr_z_from + z_swap_offset; + + /* Xifan TANG: double check*/ + assert(block[curr_b_from].type == grid[curr_x_from][curr_y_from].type); + + // Make sure that the swap_to location is still on the chip + if (curr_x_to < 1 || curr_x_to > nx || curr_y_to < 1 || curr_y_to > ny || curr_z_to < 0) { + abort_swap = TRUE; + /* Xifan TANG: We need to check if the swap_to location has the same type! */ + /* + } else if (grid[curr_x_from][curr_y_from].type != grid[curr_x_to][curr_y_to].type) { + abort_swap = TRUE; + */ + } else { + /* Xifan TANG: Check if the to_x, to_y is also a marco... + * If the follow cases are true then we should abort the swap + * 1. length of to_macro is larger than this macro + * 2. length of to_macro is the same as this macro, but its starting point is not align with this macro. + * 2. length of to_macro is less this macro, but its starting/ending point is out of the range of this macro. + */ + /* + curr_b_to = grid[curr_x_to][curr_y_to].blocks[curr_z_to]; + if (OPEN != curr_b_to) { + get_imacro_from_iblk(&to_imacro, curr_b_to, pl_macros, num_pl_macros); + } + if (OPEN != to_imacro) { + if (pl_macros[imacro].num_blocks < pl_macros[to_imacro].num_blocks) { + abort_swap = TRUE; + } else if ((pl_macros[imacro].num_blocks == pl_macros[to_imacro].num_blocks) + && (imember != spot_blk_position_in_a_macro(pl_macros[to_imacro],curr_b_to))) { + abort_swap = TRUE; + } else if ((pl_macros[imacro].num_blocks > pl_macros[to_imacro].num_blocks) + && (0 == check_macros_contained(pl_macros[imacro], pl_macros[to_imacro]))) { + abort_swap = TRUE; + } + } + } + } + */ + /* Xifan TANG: Only all the memebers in the macro pass the check, we can proceed to setup swap */ + /* + if (FALSE == abort_swap) { + for (imember = 0; imember < pl_macros[imacro].num_blocks && abort_swap == FALSE; imember++) { + // Gets the new from and to info for every block in the macro + // cannot use the old from and to info + curr_b_from = pl_macros[imacro].members[imember].blk_index; + + curr_x_from = block[curr_b_from].x; + curr_y_from = block[curr_b_from].y; + curr_z_from = block[curr_b_from].z; + + curr_x_to = curr_x_from + x_swap_offset; + curr_y_to = curr_y_from + y_swap_offset; + curr_z_to = curr_z_from + z_swap_offset; + */ + curr_b_to = grid[curr_x_to][curr_y_to].blocks[curr_z_to]; + abort_swap = setup_blocks_affected(curr_b_from, curr_x_to, curr_y_to, curr_z_to); + } // Finish going through all the blocks in the macro + } + } else { + + // This is not a macro - I could use the from and to info from before + abort_swap = setup_blocks_affected(b_from, x_to, y_to, z_to); + + } // Finish handling cases for blocks in macro and otherwise + + return (abort_swap); + +} + +static enum swap_result try_swap(float t, float *cost, float *bb_cost, float *timing_cost, + float rlim, float **old_region_occ_x, + float **old_region_occ_y, + enum e_place_algorithm place_algorithm, float timing_tradeoff, + float inverse_prev_bb_cost, float inverse_prev_timing_cost, + float *delay_cost) { + + /* Picks some block and moves it to another spot. If this spot is * + * occupied, switch the blocks. Assess the change in cost function * + * and accept or reject the move. If rejected, return 0. If * + * accepted return 1. Pass back the new value of the cost function. * + * rlim is the range limiter. */ + + enum swap_result keep_switch; + int b_from, x_from, y_from, z_from, x_to, y_to, z_to, b_to; + int num_nets_affected; + float delta_c, bb_delta_c, timing_delta_c, delay_delta_c; + int inet, iblk, bnum, iblk_pin, inet_affected; + int abort_swap = FALSE; + + num_ts_called ++; + + /* I'm using negative values of temp_net_cost as a flag, so DO NOT * + * use cost functions that can go negative. */ + + delta_c = 0; /* Change in cost due to this swap. */ + bb_delta_c = 0; + timing_delta_c = 0; + delay_delta_c = 0.0; + + /* Pick a random block to be swapped with another random block */ + b_from = my_irand(num_blocks - 1); + + /* If the pins are fixed we never move them from their initial * + * random locations. The code below could be made more efficient * + * by using the fact that pins appear first in the block list, * + * but this shouldn't cause any significant slowdown and won't be * + * broken if I ever change the parser so that the pins aren't * + * necessarily at the start of the block list. */ + while (block[b_from].isFixed == TRUE) { + b_from = my_irand(num_blocks - 1); + } + + x_from = block[b_from].x; + y_from = block[b_from].y; + z_from = block[b_from].z; + + if (!find_to(x_from, y_from, block[b_from].type, rlim, &x_to, + &y_to)) { + return REJECTED; + } + + z_to = 0; + if (grid[x_to][y_to].type->capacity > 1) { + z_to = my_irand(grid[x_to][y_to].type->capacity - 1); + } + + /* Make the switch in order to make computing the new bounding * + * box simpler. If the cost increase is too high, switch them * + * back. (block data structures switched, clbs not switched * + * until success of move is determined.) * + * Also check that whether those are the only 2 blocks * + * to be moved - check for carry chains and other placement * + * macros. */ + + /* Check whether the from_block is part of a macro first. * + * If it is, the whole macro has to be moved. Calculate the * + * x, y, z offsets of the swap to maintain relative placements * + * of the blocks. Abort the swap if the to_block is part of a * + * macro (not supported yet). */ + + abort_swap = find_affected_blocks(b_from, x_to, y_to, z_to); + + if (abort_swap == FALSE) { + + // Find all the nets affected by this swap + num_nets_affected = find_affected_nets(ts_nets_to_update); + + /* Go through all the pins in all the blocks moved and update the bounding boxes. * + * Do not update the net cost here since it should only be updated once per net, * + * not once per pin */ + for (iblk = 0; iblk < blocks_affected.num_moved_blocks; iblk++) + { + bnum = blocks_affected.moved_blocks[iblk].block_num; + + /* Go through all the pins in the moved block */ + for (iblk_pin = 0; iblk_pin < block[bnum].type->num_pins; iblk_pin++) + { + inet = block[bnum].nets[iblk_pin]; + if (inet == OPEN) + continue; + if (clb_net[inet].is_global) + continue; + + if (clb_net[inet].num_sinks < SMALL_NET) { + if(bb_updated_before[inet] == NOT_UPDATED_YET) + /* Brute force bounding box recomputation, once only for speed. */ + get_non_updateable_bb(inet, &ts_bb_coord_new[inet]); + } else { + update_bb(inet, &ts_bb_coord_new[inet], + &ts_bb_edge_new[inet], + blocks_affected.moved_blocks[iblk].xold, + blocks_affected.moved_blocks[iblk].yold + block[bnum].type->pin_height[iblk_pin], + blocks_affected.moved_blocks[iblk].xnew, + blocks_affected.moved_blocks[iblk].ynew + block[bnum].type->pin_height[iblk_pin]); + } + } + } + + /* Now update the cost function. The cost is only updated once for every net * + * May have to do major optimizations here later. */ + for (inet_affected = 0; inet_affected < num_nets_affected; inet_affected++) { + inet = ts_nets_to_update[inet_affected]; + + temp_net_cost[inet] = get_net_cost(inet, &ts_bb_coord_new[inet]); + bb_delta_c += temp_net_cost[inet] - net_cost[inet]; + } + + if (place_algorithm == NET_TIMING_DRIVEN_PLACE + || place_algorithm == PATH_TIMING_DRIVEN_PLACE) { + /*in this case we redefine delta_c as a combination of timing and bb. * + *additionally, we normalize all values, therefore delta_c is in * + *relation to 1*/ + + comp_delta_td_cost(&timing_delta_c, &delay_delta_c); + + delta_c = (1 - timing_tradeoff) * bb_delta_c * inverse_prev_bb_cost + + timing_tradeoff * timing_delta_c * inverse_prev_timing_cost; + } else { + delta_c = bb_delta_c; + } + + /* 1 -> move accepted, 0 -> rejected. */ + keep_switch = assess_swap(delta_c, t); + + if (keep_switch == ACCEPTED) { + *cost = *cost + delta_c; + *bb_cost = *bb_cost + bb_delta_c; + + if (place_algorithm == NET_TIMING_DRIVEN_PLACE + || place_algorithm == PATH_TIMING_DRIVEN_PLACE) { + /*update the point_to_point_timing_cost and point_to_point_delay_cost + * values from the temporary values */ + *timing_cost = *timing_cost + timing_delta_c; + *delay_cost = *delay_cost + delay_delta_c; + + update_td_cost(); + } + + /* update net cost functions and reset flags. */ + for (inet_affected = 0; inet_affected < num_nets_affected; inet_affected++) { + inet = ts_nets_to_update[inet_affected]; + + bb_coords[inet] = ts_bb_coord_new[inet]; + if (clb_net[inet].num_sinks >= SMALL_NET) + bb_num_on_edges[inet] = ts_bb_edge_new[inet]; + + net_cost[inet] = temp_net_cost[inet]; + + /* negative temp_net_cost value is acting as a flag. */ + temp_net_cost[inet] = -1; + bb_updated_before[inet] = NOT_UPDATED_YET; + } + + /* Update clb data structures since we kept the move. */ + /* Swap physical location */ + for (iblk = 0; iblk < blocks_affected.num_moved_blocks; iblk++) { + + x_to = blocks_affected.moved_blocks[iblk].xnew; + y_to = blocks_affected.moved_blocks[iblk].ynew; + z_to = blocks_affected.moved_blocks[iblk].znew; + /* Xifan TANG: not sure if this is needed */ + //b_to = grid[x_to][y_to].blocks[z_to]; + + x_from = blocks_affected.moved_blocks[iblk].xold; + y_from = blocks_affected.moved_blocks[iblk].yold; + z_from = blocks_affected.moved_blocks[iblk].zold; + + b_from = blocks_affected.moved_blocks[iblk].block_num; + + grid[x_to][y_to].blocks[z_to] = b_from; + /* Xifan TANG: not sure if this is needed */ + //grid[x_from][y_from].blocks[z_from] = b_to; + + if (blocks_affected.moved_blocks[iblk].swapped_to_empty == TRUE) { + grid[x_to][y_to].usage++; + grid[x_from][y_from].usage--; + grid[x_from][y_from].blocks[z_from] = -1; + } + + } // Finish updating clb for all blocks + + } else { /* Move was rejected. */ + + /* Reset the net cost function flags first. */ + for (inet_affected = 0; inet_affected < num_nets_affected; inet_affected++) { + inet = ts_nets_to_update[inet_affected]; + temp_net_cost[inet] = -1; + bb_updated_before[inet] = NOT_UPDATED_YET; + } + + /* Restore the block data structures to their state before the move. */ + for (iblk = 0; iblk < blocks_affected.num_moved_blocks; iblk++) { + b_from = blocks_affected.moved_blocks[iblk].block_num; + + block[b_from].x = blocks_affected.moved_blocks[iblk].xold; + block[b_from].y = blocks_affected.moved_blocks[iblk].yold; + block[b_from].z = blocks_affected.moved_blocks[iblk].zold; + } + } + + /* Resets the num_moved_blocks, but do not free blocks_moved array. Defensive Coding */ + blocks_affected.num_moved_blocks = 0; + + //check_place(*bb_cost, *timing_cost, place_algorithm, *delay_cost); + + return (keep_switch); + } else { + + /* Restore the block data structures to their state before the move. */ + for (iblk = 0; iblk < blocks_affected.num_moved_blocks; iblk++) { + b_from = blocks_affected.moved_blocks[iblk].block_num; + + block[b_from].x = blocks_affected.moved_blocks[iblk].xold; + block[b_from].y = blocks_affected.moved_blocks[iblk].yold; + block[b_from].z = blocks_affected.moved_blocks[iblk].zold; + } + + /* Resets the num_moved_blocks, but do not free blocks_moved array. Defensive Coding */ + blocks_affected.num_moved_blocks = 0; + + return ABORTED; + } +} + +static int find_affected_nets(int *nets_to_update) { + + /* Puts a list of all the nets that are changed by the swap into * + * nets_to_update. Returns the number of affected nets. */ + + int iblk, iblk_pin, inet, bnum, num_affected_nets; + + num_affected_nets = 0; + /* Go through all the blocks moved */ + for (iblk = 0; iblk < blocks_affected.num_moved_blocks; iblk++) + { + bnum = blocks_affected.moved_blocks[iblk].block_num; + + /* Go through all the pins in the moved block */ + for (iblk_pin = 0; iblk_pin < block[bnum].type->num_pins; iblk_pin++) + { + /* Updates the pins_to_nets array, set to -1 if * + * that pin is not connected to any net or it is a * + * global pin that does not need to be updated */ + inet = block[bnum].nets[iblk_pin]; + if (inet == OPEN) + continue; + if (clb_net[inet].is_global) + continue; + + if (temp_net_cost[inet] < 0.) { + /* Net not marked yet. */ + nets_to_update[num_affected_nets] = inet; + num_affected_nets++; + + /* Flag to say we've marked this net. */ + temp_net_cost[inet] = 1.; + } + } + } + return num_affected_nets; +} + +static boolean find_to(int x_from, int y_from, t_type_ptr type, float rlim, int *x_to, int *y_to) { + + /* Returns the point to which I want to swap, properly range limited. + * rlim must always be between 1 and nx (inclusive) for this routine + * to work. Assumes that a column only contains blocks of the same type. + */ + + int x_rel, y_rel, rlx, rly, min_x, max_x, min_y, max_y; + int num_tries; + int active_area; + boolean is_legal; + int block_index, ipos; + + if (type != grid[x_from][y_from].type) { + assert(type == grid[x_from][y_from].type); + } + + rlx = (int)std::min((float)nx + 1, rlim); + rly = (int)std::min((float)ny + 1, rlim); /* Added rly for aspect_ratio != 1 case. */ + active_area = 4 * rlx * rly; + + min_x = std::max(0, x_from - rlx); + max_x = std::min(nx + 1, x_from + rlx); + min_y = std::max(0, y_from - rly); + max_y = std::min(ny + 1, y_from + rly); + +#ifdef DEBUG + if (rlx < 1 || rlx > nx + 1) { + vpr_printf(TIO_MESSAGE_ERROR, "in find_to: rlx = %d\n", rlx); + exit(1); + } +#endif + + num_tries = 0; + block_index = type->index; + + do { /* Until legal */ + is_legal = TRUE; + + /* Limit the number of tries when searching for an alternative position */ + if(num_tries >= 2 * std::min(active_area / type->height, num_legal_pos[block_index]) + 10) { + /* Tried randomly searching for a suitable position */ + return FALSE; + } else { + num_tries++; + } + if(nx / 4 < rlx || + ny / 4 < rly || + num_legal_pos[block_index] < active_area) { + ipos = my_irand(num_legal_pos[block_index] - 1); + *x_to = legal_pos[block_index][ipos].x; + *y_to = legal_pos[block_index][ipos].y; + } else { + x_rel = my_irand(std::max(0, max_x - min_x)); + *x_to = min_x + x_rel; + y_rel = my_irand(std::max(0, max_y - min_y)); + *y_to = min_y + y_rel; + *y_to = (*y_to) - grid[*x_to][*y_to].offset; /* align it */ + } + + if((x_from == *x_to) && (y_from == *y_to)) { + is_legal = FALSE; + } else if(*x_to > max_x || *x_to < min_x || *y_to > max_y || *y_to < min_y) { + is_legal = FALSE; + } else if(grid[*x_to][*y_to].type != grid[x_from][y_from].type) { + is_legal = FALSE; + } + + assert(*x_to >= 0 && *x_to <= nx + 1); + assert(*y_to >= 0 && *y_to <= ny + 1); + } while (is_legal == FALSE); + +#ifdef DEBUG + if (*x_to < 0 || *x_to > nx + 1 || *y_to < 0 || *y_to > ny + 1) { + vpr_printf(TIO_MESSAGE_ERROR, "in routine find_to: (x_to,y_to) = (%d,%d)\n", *x_to, *y_to); + exit(1); + } +#endif + assert(type == grid[*x_to][*y_to].type); + return TRUE; +} + +static enum swap_result assess_swap(float delta_c, float t) { + + /* Returns: 1 -> move accepted, 0 -> rejected. */ + + enum swap_result accept; + float prob_fac, fnum; + + if (delta_c <= 0) { + +#ifdef SPEC /* Reduce variation in final solution due to round off */ + fnum = my_frand(); +#endif + + accept = ACCEPTED; + return (accept); + } + + if (t == 0.) + return (REJECTED); + + fnum = my_frand(); + prob_fac = exp(-delta_c / t); + if (prob_fac > fnum) { + accept = ACCEPTED; + } else { + accept = REJECTED; + } + return (accept); +} + +static float recompute_bb_cost(void) { + + /* Recomputes the cost to eliminate roundoff that may have accrued. * + * This routine does as little work as possible to compute this new * + * cost. */ + + int inet; + float cost; + + cost = 0; + + for (inet = 0; inet < num_nets; inet++) { /* for each net ... */ + if (clb_net[inet].is_global == FALSE) { /* Do only if not global. */ + + /* Bounding boxes don't have to be recomputed; they're correct. */ + cost += net_cost[inet]; + } + } + + return (cost); +} + +static float comp_td_point_to_point_delay(int inet, int ipin) { + + /*returns the delay of one point to point connection */ + + int source_block, sink_block; + int delta_x, delta_y; + t_type_ptr source_type, sink_type; + float delay_source_to_sink; + + delay_source_to_sink = 0.; + + source_block = clb_net[inet].node_block[0]; + source_type = block[source_block].type; + + sink_block = clb_net[inet].node_block[ipin]; + sink_type = block[sink_block].type; + + assert(source_type != NULL); + assert(sink_type != NULL); + + delta_x = abs(block[sink_block].x - block[source_block].x); + delta_y = abs(block[sink_block].y - block[source_block].y); + + /* TODO low priority: Could be merged into one look-up table */ + /* Note: This heuristic is terrible on Quality of Results. + * A much better heuristic is to create a more comprehensive lookup table but + * it's too late in the release cycle to do this. Pushing until the next release */ + if (source_type == IO_TYPE) { + if (sink_type == IO_TYPE) + delay_source_to_sink = delta_io_to_io[delta_x][delta_y]; + else + delay_source_to_sink = delta_io_to_clb[delta_x][delta_y]; + } else { + if (sink_type == IO_TYPE) + delay_source_to_sink = delta_clb_to_io[delta_x][delta_y]; + else + delay_source_to_sink = delta_clb_to_clb[delta_x][delta_y]; + } + if (delay_source_to_sink < 0) { + vpr_printf(TIO_MESSAGE_ERROR, "in comp_td_point_to_point_delay: Bad delay_source_to_sink value delta(%d, %d) delay of %g\n", delta_x, delta_y, delay_source_to_sink); + vpr_printf(TIO_MESSAGE_ERROR, "in comp_td_point_to_point_delay: Delay is less than 0\n"); + exit(1); + } + + return (delay_source_to_sink); +} + +static void update_td_cost(void) { + /* Update the point_to_point_timing_cost values from the temporary * + * values for all connections that have changed. */ + + int iblk_pin, net_pin, inet, ipin; + int iblk, iblk2, bnum, driven_by_moved_block; + + /* Go through all the blocks moved. */ + for (iblk = 0; iblk < blocks_affected.num_moved_blocks; iblk++) + { + bnum = blocks_affected.moved_blocks[iblk].block_num; + for (iblk_pin = 0; iblk_pin < block[bnum].type->num_pins; iblk_pin++) { + + inet = block[bnum].nets[iblk_pin]; + + if (inet == OPEN) + continue; + + if (clb_net[inet].is_global) + continue; + + net_pin = net_pin_index[bnum][iblk_pin]; + + if (net_pin != 0) { + + driven_by_moved_block = FALSE; + for (iblk2 = 0; iblk2 < blocks_affected.num_moved_blocks; iblk2++) + { if (clb_net[inet].node_block[0] == blocks_affected.moved_blocks[iblk2].block_num) + driven_by_moved_block = TRUE; + } + + /* The following "if" prevents the value from being updated twice. */ + if (driven_by_moved_block == FALSE) { + point_to_point_delay_cost[inet][net_pin] = + temp_point_to_point_delay_cost[inet][net_pin]; + temp_point_to_point_delay_cost[inet][net_pin] = -1; + point_to_point_timing_cost[inet][net_pin] = + temp_point_to_point_timing_cost[inet][net_pin]; + temp_point_to_point_timing_cost[inet][net_pin] = -1; + } + } else { /* This net is being driven by a moved block, recompute */ + /* All point to point connections on this net. */ + for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) { + point_to_point_delay_cost[inet][ipin] = + temp_point_to_point_delay_cost[inet][ipin]; + temp_point_to_point_delay_cost[inet][ipin] = -1; + point_to_point_timing_cost[inet][ipin] = + temp_point_to_point_timing_cost[inet][ipin]; + temp_point_to_point_timing_cost[inet][ipin] = -1; + } /* Finished updating the pin */ + } + } /* Finished going through all the pins in the moved block */ + } /* Finished going through all the blocks moved */ +} + +static void comp_delta_td_cost(float *delta_timing, float *delta_delay) { + + /*a net that is being driven by a moved block must have all of its */ + /*sink timing costs recomputed. A net that is driving a moved block */ + /*must only have the timing cost on the connection driving the input */ + /*pin computed */ + + int inet, net_pin, ipin; + float delta_timing_cost, delta_delay_cost, temp_delay; + int iblk, iblk2, bnum, iblk_pin, driven_by_moved_block; + + delta_timing_cost = 0.; + delta_delay_cost = 0.; + + /* Go through all the blocks moved */ + for (iblk = 0; iblk < blocks_affected.num_moved_blocks; iblk++) + { + bnum = blocks_affected.moved_blocks[iblk].block_num; + /* Go through all the pins in the moved block */ + for (iblk_pin = 0; iblk_pin < block[bnum].type->num_pins; iblk_pin++) { + inet = block[bnum].nets[iblk_pin]; + + if (inet == OPEN) + continue; + + if (clb_net[inet].is_global) + continue; + + net_pin = net_pin_index[bnum][iblk_pin]; + + if (net_pin != 0) { + /* If this net is being driven by a block that has moved, we do not * + * need to compute the change in the timing cost (here) since it will * + * be computed in the fanout of the net on the driving block, also * + * computing it here would double count the change, and mess up the * + * delta_timing_cost value. */ + driven_by_moved_block = FALSE; + for (iblk2 = 0; iblk2 < blocks_affected.num_moved_blocks; iblk2++) + { if (clb_net[inet].node_block[0] == blocks_affected.moved_blocks[iblk2].block_num) + driven_by_moved_block = TRUE; + } + + if (driven_by_moved_block == FALSE) { + temp_delay = comp_td_point_to_point_delay(inet, net_pin); + temp_point_to_point_delay_cost[inet][net_pin] = temp_delay; + + temp_point_to_point_timing_cost[inet][net_pin] = + timing_place_crit[inet][net_pin] * temp_delay; + delta_timing_cost += temp_point_to_point_timing_cost[inet][net_pin] + - point_to_point_timing_cost[inet][net_pin]; + delta_delay_cost += temp_point_to_point_delay_cost[inet][net_pin] + - point_to_point_delay_cost[inet][net_pin]; + } + } else { /* This net is being driven by a moved block, recompute */ + /* All point to point connections on this net. */ + for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) { + temp_delay = comp_td_point_to_point_delay(inet, ipin); + temp_point_to_point_delay_cost[inet][ipin] = temp_delay; + + temp_point_to_point_timing_cost[inet][ipin] = + timing_place_crit[inet][ipin] * temp_delay; + delta_timing_cost += temp_point_to_point_timing_cost[inet][ipin] + - point_to_point_timing_cost[inet][ipin]; + delta_delay_cost += temp_point_to_point_delay_cost[inet][ipin] + - point_to_point_delay_cost[inet][ipin]; + + } /* Finished updating the pin */ + } + } /* Finished going through all the pins in the moved block */ + } /* Finished going through all the blocks moved */ + + *delta_timing = delta_timing_cost; + *delta_delay = delta_delay_cost; +} + +static void comp_td_costs(float *timing_cost, float *connection_delay_sum) { + /* Computes the cost (from scratch) due to the delays and criticalities * + * on all point to point connections, we define the timing cost of * + * each connection as criticality*delay. */ + + int inet, ipin; + float loc_timing_cost, loc_connection_delay_sum, temp_delay_cost, + temp_timing_cost; + + loc_timing_cost = 0.; + loc_connection_delay_sum = 0.; + + for (inet = 0; inet < num_nets; inet++) { /* For each net ... */ + if (clb_net[inet].is_global == FALSE) { /* Do only if not global. */ + + for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) { + + temp_delay_cost = comp_td_point_to_point_delay(inet, ipin); + temp_timing_cost = temp_delay_cost * timing_place_crit[inet][ipin]; + + loc_connection_delay_sum += temp_delay_cost; + point_to_point_delay_cost[inet][ipin] = temp_delay_cost; + temp_point_to_point_delay_cost[inet][ipin] = -1; /* Undefined */ + + point_to_point_timing_cost[inet][ipin] = temp_timing_cost; + temp_point_to_point_timing_cost[inet][ipin] = -1; /* Undefined */ + loc_timing_cost += temp_timing_cost; + } + } + } + + /* Make sure timing cost does not go above MIN_TIMING_COST. */ + *timing_cost = loc_timing_cost; + + *connection_delay_sum = loc_connection_delay_sum; +} + +static float comp_bb_cost(enum cost_methods method) { + + /* Finds the cost from scratch. Done only when the placement * + * has been radically changed (i.e. after initial placement). * + * Otherwise find the cost change incrementally. If method * + * check is NORMAL, we find bounding boxes that are updateable * + * for the larger nets. If method is CHECK, all bounding boxes * + * are found via the non_updateable_bb routine, to provide a * + * cost which can be used to check the correctness of the * + * other routine. */ + + int inet; + float cost; + double expected_wirelength; + + cost = 0; + expected_wirelength = 0.0; + + for (inet = 0; inet < num_nets; inet++) { /* for each net ... */ + + if (clb_net[inet].is_global == FALSE) { /* Do only if not global. */ + + /* Small nets don't use incremental updating on their bounding boxes, * + * so they can use a fast bounding box calculator. */ + + if (clb_net[inet].num_sinks >= SMALL_NET && method == NORMAL) { + get_bb_from_scratch(inet, &bb_coords[inet], + &bb_num_on_edges[inet]); + } else { + get_non_updateable_bb(inet, &bb_coords[inet]); + } + + net_cost[inet] = get_net_cost(inet, &bb_coords[inet]); + cost += net_cost[inet]; + if (method == CHECK) + expected_wirelength += get_net_wirelength_estimate(inet, + &bb_coords[inet]); + } + } + + if (method == CHECK) { + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "BB estimate of min-dist (placement) wirelength: %.0f\n", expected_wirelength); + } + return (cost); +} + +static void free_placement_structs( + float **old_region_occ_x, float **old_region_occ_y, + struct s_placer_opts placer_opts) { + + /* Frees the major structures needed by the placer (and not needed * + * elsewhere). */ + + int inet, imacro; + + free_legal_placements(); + free_fast_cost_update(); + + if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE + || placer_opts.place_algorithm == PATH_TIMING_DRIVEN_PLACE + || placer_opts.enable_timing_computations) { + for (inet = 0; inet < num_nets; inet++) { + /*add one to the address since it is indexed from 1 not 0 */ + + point_to_point_delay_cost[inet]++; + free(point_to_point_delay_cost[inet]); + + point_to_point_timing_cost[inet]++; + free(point_to_point_timing_cost[inet]); + + temp_point_to_point_delay_cost[inet]++; + free(temp_point_to_point_delay_cost[inet]); + + temp_point_to_point_timing_cost[inet]++; + free(temp_point_to_point_timing_cost[inet]); + } + free(point_to_point_delay_cost); + free(temp_point_to_point_delay_cost); + + free(point_to_point_timing_cost); + free(temp_point_to_point_timing_cost); + + free_matrix(net_pin_index, 0, num_blocks - 1, 0, sizeof(int)); + } + + free(net_cost); + free(temp_net_cost); + free(bb_num_on_edges); + free(bb_coords); + + free_placement_macros_structs(); + + for (imacro = 0; imacro < num_pl_macros; imacro ++) + free(pl_macros[imacro].members); + free(pl_macros); + + net_cost = NULL; /* Defensive coding. */ + temp_net_cost = NULL; + bb_num_on_edges = NULL; + bb_coords = NULL; + pl_macros = NULL; + + /* Frees up all the data structure used in vpr_utils. */ + free_port_pin_from_blk_pin(); + free_blk_pin_from_port_pin(); + +} + +static void alloc_and_load_placement_structs( + float place_cost_exp, float ***old_region_occ_x, + float ***old_region_occ_y, struct s_placer_opts placer_opts, + t_direct_inf *directs, int num_directs) { + + /* Allocates the major structures needed only by the placer, primarily for * + * computing costs quickly and such. */ + + int inet, ipin, max_pins_per_clb, i; + + alloc_legal_placements(); + load_legal_placements(); + + max_pins_per_clb = 0; + for (i = 0; i < num_types; i++) { + max_pins_per_clb = std::max(max_pins_per_clb, type_descriptors[i].num_pins); + } + + if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE + || placer_opts.place_algorithm == PATH_TIMING_DRIVEN_PLACE + || placer_opts.enable_timing_computations) { + /* Allocate structures associated with timing driven placement */ + /* [0..num_nets-1][1..num_pins-1] */ + point_to_point_delay_cost = (float **) my_malloc( + num_nets * sizeof(float *)); + temp_point_to_point_delay_cost = (float **) my_malloc( + num_nets * sizeof(float *)); + + point_to_point_timing_cost = (float **) my_malloc( + num_nets * sizeof(float *)); + temp_point_to_point_timing_cost = (float **) my_malloc( + num_nets * sizeof(float *)); + + for (inet = 0; inet < num_nets; inet++) { + + /* In the following, subract one so index starts at * + * 1 instead of 0 */ + point_to_point_delay_cost[inet] = (float *) my_malloc( + clb_net[inet].num_sinks * sizeof(float)); + point_to_point_delay_cost[inet]--; + + temp_point_to_point_delay_cost[inet] = (float *) my_malloc( + clb_net[inet].num_sinks * sizeof(float)); + temp_point_to_point_delay_cost[inet]--; + + point_to_point_timing_cost[inet] = (float *) my_malloc( + clb_net[inet].num_sinks * sizeof(float)); + point_to_point_timing_cost[inet]--; + + temp_point_to_point_timing_cost[inet] = (float *) my_malloc( + clb_net[inet].num_sinks * sizeof(float)); + temp_point_to_point_timing_cost[inet]--; + } + for (inet = 0; inet < num_nets; inet++) { + for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) { + point_to_point_delay_cost[inet][ipin] = 0; + temp_point_to_point_delay_cost[inet][ipin] = 0; + } + } + } + + net_cost = (float *) my_malloc(num_nets * sizeof(float)); + temp_net_cost = (float *) my_malloc(num_nets * sizeof(float)); + bb_updated_before = (char*)my_calloc(num_nets, sizeof(char)); + + /* Used to store costs for moves not yet made and to indicate when a net's * + * cost has been recomputed. temp_net_cost[inet] < 0 means net's cost hasn't * + * been recomputed. */ + + for (inet = 0; inet < num_nets; inet++){ + bb_updated_before[inet] = NOT_UPDATED_YET; + temp_net_cost[inet] = -1.; + } + + bb_coords = (struct s_bb *) my_malloc(num_nets * sizeof(struct s_bb)); + bb_num_on_edges = (struct s_bb *) my_malloc(num_nets * sizeof(struct s_bb)); + + /* Shouldn't use them; crash hard if I do! */ + *old_region_occ_x = NULL; + *old_region_occ_y = NULL; + + alloc_and_load_for_fast_cost_update(place_cost_exp); + + net_pin_index = alloc_and_load_net_pin_index(); + + alloc_and_load_try_swap_structs(); + + num_pl_macros = alloc_and_load_placement_macros(directs, num_directs, &pl_macros); +} + +static void alloc_and_load_try_swap_structs() { + /* Allocate the local bb_coordinate storage, etc. only once. */ + /* Allocate with size num_nets for any number of nets affected. */ + ts_bb_coord_new = (struct s_bb *) my_calloc( + num_nets, sizeof(struct s_bb)); + ts_bb_edge_new = (struct s_bb *) my_calloc( + num_nets, sizeof(struct s_bb)); + ts_nets_to_update = (int *) my_calloc(num_nets, sizeof(int)); + + /* Allocate with size num_blocks for any number of moved block. */ + blocks_affected.moved_blocks = (t_pl_moved_block*)my_calloc( + num_blocks, sizeof(t_pl_moved_block) ); + blocks_affected.num_moved_blocks = 0; + +} + +static void get_bb_from_scratch(int inet, struct s_bb *coords, + struct s_bb *num_on_edges) { + + /* This routine finds the bounding box of each net from scratch (i.e. * + * from only the block location information). It updates both the * + * coordinate and number of pins on each edge information. It * + * should only be called when the bounding box information is not valid. */ + + int ipin, bnum, pnum, x, y, xmin, xmax, ymin, ymax; + int xmin_edge, xmax_edge, ymin_edge, ymax_edge; + int n_pins; + + n_pins = clb_net[inet].num_sinks + 1; + + bnum = clb_net[inet].node_block[0]; + pnum = clb_net[inet].node_block_pin[0]; + + x = block[bnum].x; + y = block[bnum].y + block[bnum].type->pin_height[pnum]; + + x = std::max(std::min(x, nx), 1); + y = std::max(std::min(y, ny), 1); + + xmin = x; + ymin = y; + xmax = x; + ymax = y; + xmin_edge = 1; + ymin_edge = 1; + xmax_edge = 1; + ymax_edge = 1; + + for (ipin = 1; ipin < n_pins; ipin++) { + bnum = clb_net[inet].node_block[ipin]; + pnum = clb_net[inet].node_block_pin[ipin]; + x = block[bnum].x; + y = block[bnum].y + block[bnum].type->pin_height[pnum]; + + /* Code below counts IO blocks as being within the 1..nx, 1..ny clb array. * + * This is because channels do not go out of the 0..nx, 0..ny range, and * + * I always take all channels impinging on the bounding box to be within * + * that bounding box. Hence, this "movement" of IO blocks does not affect * + * the which channels are included within the bounding box, and it * + * simplifies the code a lot. */ + + x = std::max(std::min(x, nx), 1); + y = std::max(std::min(y, ny), 1); + + if (x == xmin) { + xmin_edge++; + } + if (x == xmax) { /* Recall that xmin could equal xmax -- don't use else */ + xmax_edge++; + } else if (x < xmin) { + xmin = x; + xmin_edge = 1; + } else if (x > xmax) { + xmax = x; + xmax_edge = 1; + } + + if (y == ymin) { + ymin_edge++; + } + if (y == ymax) { + ymax_edge++; + } else if (y < ymin) { + ymin = y; + ymin_edge = 1; + } else if (y > ymax) { + ymax = y; + ymax_edge = 1; + } + } + + /* Copy the coordinates and number on edges information into the proper * + * structures. */ + coords->xmin = xmin; + coords->xmax = xmax; + coords->ymin = ymin; + coords->ymax = ymax; + + num_on_edges->xmin = xmin_edge; + num_on_edges->xmax = xmax_edge; + num_on_edges->ymin = ymin_edge; + num_on_edges->ymax = ymax_edge; +} + +static double get_net_wirelength_estimate(int inet, struct s_bb *bbptr) { + + /* WMF: Finds the estimate of wirelength due to one net by looking at * + * its coordinate bounding box. */ + + double ncost, crossing; + + /* Get the expected "crossing count" of a net, based on its number * + * of pins. Extrapolate for very large nets. */ + + if (((clb_net[inet].num_sinks + 1) > 50) + && ((clb_net[inet].num_sinks + 1) < 85)) { + crossing = 2.7933 + 0.02616 * ((clb_net[inet].num_sinks + 1) - 50); + } else if ((clb_net[inet].num_sinks + 1) >= 85) { + crossing = 2.7933 + 0.011 * (clb_net[inet].num_sinks + 1) + - 0.0000018 * (clb_net[inet].num_sinks + 1) + * (clb_net[inet].num_sinks + 1); + } else { + crossing = cross_count[(clb_net[inet].num_sinks + 1) - 1]; + } + + /* Could insert a check for xmin == xmax. In that case, assume * + * connection will be made with no bends and hence no x-cost. * + * Same thing for y-cost. */ + + /* Cost = wire length along channel * cross_count / average * + * channel capacity. Do this for x, then y direction and add. */ + + ncost = (bbptr->xmax - bbptr->xmin + 1) * crossing; + + ncost += (bbptr->ymax - bbptr->ymin + 1) * crossing; + + return (ncost); +} + +static float get_net_cost(int inet, struct s_bb *bbptr) { + + /* Finds the cost due to one net by looking at its coordinate bounding * + * box. */ + + float ncost, crossing; + + /* Get the expected "crossing count" of a net, based on its number * + * of pins. Extrapolate for very large nets. */ + + if ((clb_net[inet].num_sinks + 1) > 50) { + crossing = 2.7933 + 0.02616 * ((clb_net[inet].num_sinks + 1) - 50); + /* crossing = 3.0; Old value */ + } else { + crossing = cross_count[(clb_net[inet].num_sinks + 1) - 1]; + } + + /* Could insert a check for xmin == xmax. In that case, assume * + * connection will be made with no bends and hence no x-cost. * + * Same thing for y-cost. */ + + /* Cost = wire length along channel * cross_count / average * + * channel capacity. Do this for x, then y direction and add. */ + + ncost = (bbptr->xmax - bbptr->xmin + 1) * crossing + * chanx_place_cost_fac[bbptr->ymax][bbptr->ymin - 1]; + + ncost += (bbptr->ymax - bbptr->ymin + 1) * crossing + * chany_place_cost_fac[bbptr->xmax][bbptr->xmin - 1]; + + return (ncost); +} + +static void get_non_updateable_bb(int inet, struct s_bb *bb_coord_new) { + + /* Finds the bounding box of a net and stores its coordinates in the * + * bb_coord_new data structure. This routine should only be called * + * for small nets, since it does not determine enough information for * + * the bounding box to be updated incrementally later. * + * Currently assumes channels on both sides of the CLBs forming the * + * edges of the bounding box can be used. Essentially, I am assuming * + * the pins always lie on the outside of the bounding box. */ + + int k, xmax, ymax, xmin, ymin, x, y; + int bnum, pnum; + + bnum = clb_net[inet].node_block[0]; + pnum = clb_net[inet].node_block_pin[0]; + x = block[bnum].x; + y = block[bnum].y + block[bnum].type->pin_height[pnum]; + + xmin = x; + ymin = y; + xmax = x; + ymax = y; + + for (k = 1; k < (clb_net[inet].num_sinks + 1); k++) { + bnum = clb_net[inet].node_block[k]; + pnum = clb_net[inet].node_block_pin[k]; + x = block[bnum].x; + y = block[bnum].y + block[bnum].type->pin_height[pnum]; + + if (x < xmin) { + xmin = x; + } else if (x > xmax) { + xmax = x; + } + + if (y < ymin) { + ymin = y; + } else if (y > ymax) { + ymax = y; + } + } + + /* Now I've found the coordinates of the bounding box. There are no * + * channels beyond nx and ny, so I want to clip to that. As well, * + * since I'll always include the channel immediately below and the * + * channel immediately to the left of the bounding box, I want to * + * clip to 1 in both directions as well (since minimum channel index * + * is 0). See route.c for a channel diagram. */ + + bb_coord_new->xmin = std::max(std::min(xmin, nx), 1); + bb_coord_new->ymin = std::max(std::min(ymin, ny), 1); + bb_coord_new->xmax = std::max(std::min(xmax, nx), 1); + bb_coord_new->ymax = std::max(std::min(ymax, ny), 1); +} + +static void update_bb(int inet, struct s_bb *bb_coord_new, + struct s_bb *bb_edge_new, int xold, int yold, int xnew, int ynew) { + + /* Updates the bounding box of a net by storing its coordinates in * + * the bb_coord_new data structure and the number of blocks on each * + * edge in the bb_edge_new data structure. This routine should only * + * be called for large nets, since it has some overhead relative to * + * just doing a brute force bounding box calculation. The bounding * + * box coordinate and edge information for inet must be valid before * + * this routine is called. * + * Currently assumes channels on both sides of the CLBs forming the * + * edges of the bounding box can be used. Essentially, I am assuming * + * the pins always lie on the outside of the bounding box. * + * The x and y coordinates are the pin's x and y coordinates. */ + /* IO blocks are considered to be one cell in for simplicity. */ + + struct s_bb *curr_bb_edge, *curr_bb_coord; + + xnew = std::max(std::min(xnew, nx), 1); + ynew = std::max(std::min(ynew, ny), 1); + xold = std::max(std::min(xold, nx), 1); + yold = std::max(std::min(yold, ny), 1); + + /* Check if the net had been updated before. */ + if (bb_updated_before[inet] == GOT_FROM_SCRATCH) + { /* The net had been updated from scratch, DO NOT update again! */ + return; + } + else if (bb_updated_before[inet] == NOT_UPDATED_YET) + { /* The net had NOT been updated before, could use the old values */ + curr_bb_coord = &bb_coords[inet]; + curr_bb_edge = &bb_num_on_edges[inet]; + bb_updated_before[inet] = UPDATED_ONCE; + } + else + { /* The net had been updated before, must use the new values */ + curr_bb_coord = bb_coord_new; + curr_bb_edge = bb_edge_new; + } + + /* Check if I can update the bounding box incrementally. */ + + if (xnew < xold) { /* Move to left. */ + + /* Update the xmax fields for coordinates and number of edges first. */ + + if (xold == curr_bb_coord->xmax) { /* Old position at xmax. */ + if (curr_bb_edge->xmax == 1) { + get_bb_from_scratch(inet, bb_coord_new, bb_edge_new); + bb_updated_before[inet] = GOT_FROM_SCRATCH; + return; + } else { + bb_edge_new->xmax = curr_bb_edge->xmax - 1; + bb_coord_new->xmax = curr_bb_coord->xmax; + } + } + + else { /* Move to left, old postion was not at xmax. */ + bb_coord_new->xmax = curr_bb_coord->xmax; + bb_edge_new->xmax = curr_bb_edge->xmax; + } + + /* Now do the xmin fields for coordinates and number of edges. */ + + if (xnew < curr_bb_coord->xmin) { /* Moved past xmin */ + bb_coord_new->xmin = xnew; + bb_edge_new->xmin = 1; + } + + else if (xnew == curr_bb_coord->xmin) { /* Moved to xmin */ + bb_coord_new->xmin = xnew; + bb_edge_new->xmin = curr_bb_edge->xmin + 1; + } + + else { /* Xmin unchanged. */ + bb_coord_new->xmin = curr_bb_coord->xmin; + bb_edge_new->xmin = curr_bb_edge->xmin; + } + } + + /* End of move to left case. */ + else if (xnew > xold) { /* Move to right. */ + + /* Update the xmin fields for coordinates and number of edges first. */ + + if (xold == curr_bb_coord->xmin) { /* Old position at xmin. */ + if (curr_bb_edge->xmin == 1) { + get_bb_from_scratch(inet, bb_coord_new, bb_edge_new); + bb_updated_before[inet] = GOT_FROM_SCRATCH; + return; + } else { + bb_edge_new->xmin = curr_bb_edge->xmin - 1; + bb_coord_new->xmin = curr_bb_coord->xmin; + } + } + + else { /* Move to right, old position was not at xmin. */ + bb_coord_new->xmin = curr_bb_coord->xmin; + bb_edge_new->xmin = curr_bb_edge->xmin; + } + + /* Now do the xmax fields for coordinates and number of edges. */ + + if (xnew > curr_bb_coord->xmax) { /* Moved past xmax. */ + bb_coord_new->xmax = xnew; + bb_edge_new->xmax = 1; + } + + else if (xnew == curr_bb_coord->xmax) { /* Moved to xmax */ + bb_coord_new->xmax = xnew; + bb_edge_new->xmax = curr_bb_edge->xmax + 1; + } + + else { /* Xmax unchanged. */ + bb_coord_new->xmax = curr_bb_coord->xmax; + bb_edge_new->xmax = curr_bb_edge->xmax; + } + } + /* End of move to right case. */ + else { /* xnew == xold -- no x motion. */ + bb_coord_new->xmin = curr_bb_coord->xmin; + bb_coord_new->xmax = curr_bb_coord->xmax; + bb_edge_new->xmin = curr_bb_edge->xmin; + bb_edge_new->xmax = curr_bb_edge->xmax; + } + + /* Now account for the y-direction motion. */ + + if (ynew < yold) { /* Move down. */ + + /* Update the ymax fields for coordinates and number of edges first. */ + + if (yold == curr_bb_coord->ymax) { /* Old position at ymax. */ + if (curr_bb_edge->ymax == 1) { + get_bb_from_scratch(inet, bb_coord_new, bb_edge_new); + bb_updated_before[inet] = GOT_FROM_SCRATCH; + return; + } else { + bb_edge_new->ymax = curr_bb_edge->ymax - 1; + bb_coord_new->ymax = curr_bb_coord->ymax; + } + } + + else { /* Move down, old postion was not at ymax. */ + bb_coord_new->ymax = curr_bb_coord->ymax; + bb_edge_new->ymax = curr_bb_edge->ymax; + } + + /* Now do the ymin fields for coordinates and number of edges. */ + + if (ynew < curr_bb_coord->ymin) { /* Moved past ymin */ + bb_coord_new->ymin = ynew; + bb_edge_new->ymin = 1; + } + + else if (ynew == curr_bb_coord->ymin) { /* Moved to ymin */ + bb_coord_new->ymin = ynew; + bb_edge_new->ymin = curr_bb_edge->ymin + 1; + } + + else { /* ymin unchanged. */ + bb_coord_new->ymin = curr_bb_coord->ymin; + bb_edge_new->ymin = curr_bb_edge->ymin; + } + } + /* End of move down case. */ + else if (ynew > yold) { /* Moved up. */ + + /* Update the ymin fields for coordinates and number of edges first. */ + + if (yold == curr_bb_coord->ymin) { /* Old position at ymin. */ + if (curr_bb_edge->ymin == 1) { + get_bb_from_scratch(inet, bb_coord_new, bb_edge_new); + bb_updated_before[inet] = GOT_FROM_SCRATCH; + return; + } else { + bb_edge_new->ymin = curr_bb_edge->ymin - 1; + bb_coord_new->ymin = curr_bb_coord->ymin; + } + } + + else { /* Moved up, old position was not at ymin. */ + bb_coord_new->ymin = curr_bb_coord->ymin; + bb_edge_new->ymin = curr_bb_edge->ymin; + } + + /* Now do the ymax fields for coordinates and number of edges. */ + + if (ynew > curr_bb_coord->ymax) { /* Moved past ymax. */ + bb_coord_new->ymax = ynew; + bb_edge_new->ymax = 1; + } + + else if (ynew == curr_bb_coord->ymax) { /* Moved to ymax */ + bb_coord_new->ymax = ynew; + bb_edge_new->ymax = curr_bb_edge->ymax + 1; + } + + else { /* ymax unchanged. */ + bb_coord_new->ymax = curr_bb_coord->ymax; + bb_edge_new->ymax = curr_bb_edge->ymax; + } + } + /* End of move up case. */ + else { /* ynew == yold -- no y motion. */ + bb_coord_new->ymin = curr_bb_coord->ymin; + bb_coord_new->ymax = curr_bb_coord->ymax; + bb_edge_new->ymin = curr_bb_edge->ymin; + bb_edge_new->ymax = curr_bb_edge->ymax; + } + + if (bb_updated_before[inet] == NOT_UPDATED_YET) + bb_updated_before[inet] = UPDATED_ONCE; +} + +static void alloc_legal_placements() { + int i, j, k; + + legal_pos = (t_legal_pos **) my_malloc(num_types * sizeof(t_legal_pos *)); + num_legal_pos = (int *) my_calloc(num_types, sizeof(int)); + + /* Initialize all occupancy to zero. */ + + for (i = 0; i <= nx + 1; i++) { + for (j = 0; j <= ny + 1; j++) { + grid[i][j].usage = 0; + for (k = 0; k < grid[i][j].type->capacity; k++) { + grid[i][j].blocks[k] = EMPTY; + if (grid[i][j].offset == 0) { + num_legal_pos[grid[i][j].type->index]++; + } + } + } + } + + for (i = 0; i < num_types; i++) { + legal_pos[i] = (t_legal_pos *) my_malloc(num_legal_pos[i] * sizeof(t_legal_pos)); + } +} + +static void load_legal_placements() { + int i, j, k, itype; + int *index; + + index = (int *) my_calloc(num_types, sizeof(int)); + + for (i = 0; i <= nx + 1; i++) { + for (j = 0; j <= ny + 1; j++) { + for (k = 0; k < grid[i][j].type->capacity; k++) { + if (grid[i][j].offset == 0) { + itype = grid[i][j].type->index; + legal_pos[itype][index[itype]].x = i; + legal_pos[itype][index[itype]].y = j; + legal_pos[itype][index[itype]].z = k; + index[itype]++; + } + } + } + } + free(index); +} + +static void free_legal_placements() { + int i; + for (i = 0; i < num_types; i++) { + free(legal_pos[i]); + } + free(legal_pos); /* Free the mapping list */ + free(num_legal_pos); +} + + + +static int check_macro_can_be_placed(int imacro, int itype, int x, int y, int z) { + + int imember; + int member_x, member_y, member_z; + + // Every macro can be placed until proven otherwise + int macro_can_be_placed = TRUE; + + // Check whether all the members can be placed + for (imember = 0; imember < pl_macros[imacro].num_blocks; imember++) { + member_x = x + pl_macros[imacro].members[imember].x_offset; + member_y = y + pl_macros[imacro].members[imember].y_offset; + member_z = z + pl_macros[imacro].members[imember].z_offset; + + // Check whether the location could accept block of this type + // Then check whether the location could still accomodate more blocks + // Also check whether the member position is valid, that is the member's location + // still within the chip's dimemsion and the member_z is allowed at that location on the grid + if (member_x <= nx+1 && member_y <= ny+1 + && grid[member_x][member_y].type->index == itype + && grid[member_x][member_y].blocks[member_z] == OPEN) { + // Can still accomodate blocks here, check the next position + continue; + } else { + // Cant be placed here - skip to the next try + macro_can_be_placed = FALSE; + break; + } + } + + return (macro_can_be_placed); +} + + +static int try_place_macro(int itype, int ichoice, int imacro, int * free_locations){ + + int x, y, z, member_x, member_y, member_z, imember; + + int macro_placed = FALSE; + + // Choose a random position for the head + x = legal_pos[itype][ichoice].x; + y = legal_pos[itype][ichoice].y; + z = legal_pos[itype][ichoice].z; + + // If that location is occupied, do nothing. + if (grid[x][y].blocks[z] != OPEN) { + return (macro_placed); + } + + int macro_can_be_placed = check_macro_can_be_placed(imacro, itype, x, y, z); + + if (macro_can_be_placed == TRUE) { + + // Place down the macro + macro_placed = TRUE; + for (imember = 0; imember < pl_macros[imacro].num_blocks; imember++) { + + member_x = x + pl_macros[imacro].members[imember].x_offset; + member_y = y + pl_macros[imacro].members[imember].y_offset; + member_z = z + pl_macros[imacro].members[imember].z_offset; + + block[pl_macros[imacro].members[imember].blk_index].x = member_x; + block[pl_macros[imacro].members[imember].blk_index].y = member_y; + block[pl_macros[imacro].members[imember].blk_index].z = member_z; + + grid[member_x][member_y].blocks[member_z] = pl_macros[imacro].members[imember].blk_index; + grid[member_x][member_y].usage++; + + // Could not ensure that the randomiser would not pick this location again + // So, would have to do a lazy removal - whenever I come across a block that could not be placed, + // go ahead and remove it from the legal_pos[][] array + + } // Finish placing all the members in the macro + + } // End of this choice of legal_pos + + return (macro_placed); + +} + + +static void initial_placement_pl_macros(int macros_max_num_tries, int * free_locations) { + + int macro_placed; + int imacro, iblk, itype, itry, ichoice; + + /* Macros are harder to place. Do them first */ + for (imacro = 0; imacro < num_pl_macros; imacro++) { + + // Every macro are not placed in the beginnning + macro_placed = FALSE; + + // Assume that all the blocks in the macro are of the same type + iblk = pl_macros[imacro].members[0].blk_index; + itype = block[iblk].type->index; + if (free_locations[itype] < pl_macros[imacro].num_blocks) { + vpr_printf (TIO_MESSAGE_ERROR, "Initial placement failed.\n"); + vpr_printf (TIO_MESSAGE_ERROR, "Could not place macro length %d with head block %s (#%d); not enough free locations of type %s (#%d).\n", + pl_macros[imacro].num_blocks, block[iblk].name, iblk, type_descriptors[itype].name, itype); + vpr_printf (TIO_MESSAGE_INFO, "VPR cannot auto-size for your circuit, please resize the FPGA manually.\n"); + exit(1); + } + + // Try to place the macro first, if can be placed - place them, otherwise try again + for (itry = 0; itry < macros_max_num_tries && macro_placed == FALSE; itry++) { + + // Choose a random position for the head + ichoice = my_irand(free_locations[itype] - 1); + + // Try to place the macro + macro_placed = try_place_macro(itype, ichoice, imacro, free_locations); + + } // Finished all tries + + + if (macro_placed == FALSE){ + // if a macro still could not be placed after macros_max_num_tries times, + // go through the chip exhaustively to find a legal placement for the macro + // place the macro on the first location that is legal + // then set macro_placed = TRUE; + // if there are no legal positions, error out + + // Exhaustive placement of carry macros + for (ichoice = 0; ichoice < free_locations[itype] && macro_placed == FALSE; ichoice++) { + + // Try to place the macro + macro_placed = try_place_macro(itype, ichoice, imacro, free_locations); + + } // Exhausted all the legal placement position for this macro + + // If macro could not be placed after exhaustive placement, error out + if (macro_placed == FALSE) { + // Error out + vpr_printf (TIO_MESSAGE_ERROR, "Initial placement failed.\n"); + vpr_printf (TIO_MESSAGE_ERROR, "Could not place macro length %d with head block %s (#%d); not enough free locations of type %s (#%d).\n", + pl_macros[imacro].num_blocks, block[iblk].name, iblk, type_descriptors[itype].name, itype); + vpr_printf (TIO_MESSAGE_INFO, "Please manually size the FPGA because VPR can't do this yet.\n"); + exit(1); + } + + } else { + // This macro has been placed successfully, proceed to place the next macro + continue; + } + } // Finish placing all the pl_macros successfully +} + +static void initial_placement_blocks(int * free_locations, enum e_pad_loc_type pad_loc_type) { + + /* Place blocks that are NOT a part of any macro. + * We'll randomly place each block in the clustered netlist, one by one. + */ + + int iblk, itype; + int ichoice, x, y, z; + + for (iblk = 0; iblk < num_blocks; iblk++) { + + if (block[iblk].x != -1) { + // block placed. + continue; + } + /* Don't do IOs if the user specifies IOs; we'll read those locations later. */ + if (!(block[iblk].type == IO_TYPE && pad_loc_type == USER)) { + + /* Randomly select a free location of the appropriate type + * for iblk. We have a linearized list of all the free locations + * that can accomodate a block of that type in free_locations[itype]. + * Choose one randomly and put iblk there. Then we don't want to pick that + * location again, so remove it from the free_locations array. + */ + itype = block[iblk].type->index; + if (free_locations[itype] <= 0) { + vpr_printf (TIO_MESSAGE_ERROR, "Initial placement failed.\n"); + vpr_printf (TIO_MESSAGE_ERROR, "Could not place block %s (#%d); no free locations of type %s (#%d).\n", + block[iblk].name, iblk, type_descriptors[itype].name, itype); + exit(1); + } + + ichoice = my_irand(free_locations[itype] - 1); + x = legal_pos[itype][ichoice].x; + y = legal_pos[itype][ichoice].y; + z = legal_pos[itype][ichoice].z; + + // Make sure that the position is OPEN before placing the block down + assert (grid[x][y].blocks[z] == OPEN); + + grid[x][y].blocks[z] = iblk; + grid[x][y].usage++; + + block[iblk].x = x; + block[iblk].y = y; + block[iblk].z = z; + + /* Ensure randomizer doesn't pick this location again, since it's occupied. Could shift all the + * legal positions in legal_pos to remove the entry (choice) we just used, but faster to + * just move the last entry in legal_pos to the spot we just used and decrement the + * count of free_locations. + */ + legal_pos[itype][ichoice] = legal_pos[itype][free_locations[itype] - 1]; /* overwrite used block position */ + free_locations[itype]--; + + } + } +} + +static void initial_placement(enum e_pad_loc_type pad_loc_type, + char *pad_loc_file) { + + /* Randomly places the blocks to create an initial placement. We rely on + * the legal_pos array already being loaded. That legal_pos[itype] is an + * array that gives every legal value of (x,y,z) that can accomodate a block. + * The number of such locations is given by num_legal_pos[itype]. + */ + int i, j, k, iblk, itype, x, y, z, ichoice; + int *free_locations; /* [0..num_types-1]. + * Stores how many locations there are for this type that *might* still be free. + * That is, this stores the number of entries in legal_pos[itype] that are worth considering + * as you look for a free location. + */ + + free_locations = (int *) my_malloc(num_types * sizeof(int)); + for (itype = 0; itype < num_types; itype++) { + free_locations[itype] = num_legal_pos[itype]; + } + + /* We'll use the grid to record where everything goes. Initialize to the grid has no + * blocks placed anywhere. + */ + for (i = 0; i <= nx + 1; i++) { + for (j = 0; j <= ny + 1; j++) { + grid[i][j].usage = 0; + itype = grid[i][j].type->index; + for (k = 0; k < type_descriptors[itype].capacity; k++) { + grid[i][j].blocks[k] = OPEN; + } + } + } + + /* Similarly, mark all blocks as not being placed yet. */ + for (iblk = 0; iblk < num_blocks; iblk++) { + block[iblk].x = -1; + block[iblk].y = -1; + block[iblk].z = -1; + } + + initial_placement_pl_macros(MAX_NUM_TRIES_TO_PLACE_MACROS_RANDOMLY, free_locations); + + // All the macros are placed, update the legal_pos[][] array + for (itype = 0; itype < num_types; itype++) { + assert (free_locations[itype] >= 0); + for (ichoice = 0; ichoice < free_locations[itype]; ichoice++) { + x = legal_pos[itype][ichoice].x; + y = legal_pos[itype][ichoice].y; + z = legal_pos[itype][ichoice].z; + + // Check if that location is occupied. If it is, remove from legal_pos + if (grid[x][y].blocks[z] != OPEN) { + legal_pos[itype][ichoice] = legal_pos[itype][free_locations[itype] - 1]; + free_locations[itype]--; + + // After the move, I need to check this particular entry again + ichoice--; + continue; + } + } + } // Finish updating the legal_pos[][] and free_locations[] array + + initial_placement_blocks(free_locations, pad_loc_type); + + if (pad_loc_type == USER) { + read_user_pad_loc(pad_loc_file); + } + + /* Restore legal_pos */ + load_legal_placements(); + +#ifdef VERBOSE + vpr_printf(TIO_MESSAGE_INFO, "At end of initial_placement.\n"); + if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_INITIAL_CLB_PLACEMENT)) { + print_clb_placement(getEchoFileName(E_ECHO_INITIAL_CLB_PLACEMENT)); + } +#endif + free(free_locations); +} + +static void free_fast_cost_update(void) { + int i; + + for (i = 0; i <= ny; i++) + free(chanx_place_cost_fac[i]); + free(chanx_place_cost_fac); + chanx_place_cost_fac = NULL; + + for (i = 0; i <= nx; i++) + free(chany_place_cost_fac[i]); + free(chany_place_cost_fac); + chany_place_cost_fac = NULL; +} + +static void alloc_and_load_for_fast_cost_update(float place_cost_exp) { + + /* Allocates and loads the chanx_place_cost_fac and chany_place_cost_fac * + * arrays with the inverse of the average number of tracks per channel * + * between [subhigh] and [sublow]. This is only useful for the cost * + * function that takes the length of the net bounding box in each * + * dimension divided by the average number of tracks in that direction. * + * For other cost functions, you don't have to bother calling this * + * routine; when using the cost function described above, however, you * + * must always call this routine after you call init_chan and before * + * you do any placement cost determination. The place_cost_exp factor * + * specifies to what power the width of the channel should be taken -- * + * larger numbers make narrower channels more expensive. */ + + int low, high, i; + + /* Access arrays below as chan?_place_cost_fac[subhigh][sublow]. Since * + * subhigh must be greater than or equal to sublow, we only need to * + * allocate storage for the lower half of a matrix. */ + + chanx_place_cost_fac = (float **) my_malloc((ny + 1) * sizeof(float *)); + for (i = 0; i <= ny; i++) + chanx_place_cost_fac[i] = (float *) my_malloc((i + 1) * sizeof(float)); + + chany_place_cost_fac = (float **) my_malloc((nx + 1) * sizeof(float *)); + for (i = 0; i <= nx; i++) + chany_place_cost_fac[i] = (float *) my_malloc((i + 1) * sizeof(float)); + + /* First compute the number of tracks between channel high and channel * + * low, inclusive, in an efficient manner. */ + + chanx_place_cost_fac[0][0] = chan_width_x[0]; + + for (high = 1; high <= ny; high++) { + chanx_place_cost_fac[high][high] = chan_width_x[high]; + for (low = 0; low < high; low++) { + chanx_place_cost_fac[high][low] = + chanx_place_cost_fac[high - 1][low] + chan_width_x[high]; + } + } + + /* Now compute the inverse of the average number of tracks per channel * + * between high and low. The cost function divides by the average * + * number of tracks per channel, so by storing the inverse I convert * + * this to a faster multiplication. Take this final number to the * + * place_cost_exp power -- numbers other than one mean this is no * + * longer a simple "average number of tracks"; it is some power of * + * that, allowing greater penalization of narrow channels. */ + + for (high = 0; high <= ny; high++) + for (low = 0; low <= high; low++) { + chanx_place_cost_fac[high][low] = (high - low + 1.) + / chanx_place_cost_fac[high][low]; + chanx_place_cost_fac[high][low] = pow( + (double) chanx_place_cost_fac[high][low], + (double) place_cost_exp); + } + + /* Now do the same thing for the y-directed channels. First get the * + * number of tracks between channel high and channel low, inclusive. */ + + chany_place_cost_fac[0][0] = chan_width_y[0]; + + for (high = 1; high <= nx; high++) { + chany_place_cost_fac[high][high] = chan_width_y[high]; + for (low = 0; low < high; low++) { + chany_place_cost_fac[high][low] = + chany_place_cost_fac[high - 1][low] + chan_width_y[high]; + } + } + + /* Now compute the inverse of the average number of tracks per channel * + * between high and low. Take to specified power. */ + + for (high = 0; high <= nx; high++) + for (low = 0; low <= high; low++) { + chany_place_cost_fac[high][low] = (high - low + 1.) + / chany_place_cost_fac[high][low]; + chany_place_cost_fac[high][low] = pow( + (double) chany_place_cost_fac[high][low], + (double) place_cost_exp); + } +} + +static void check_place(float bb_cost, float timing_cost, + enum e_place_algorithm place_algorithm, + float delay_cost) { + + /* Checks that the placement has not confused our data structures. * + * i.e. the clb and block structures agree about the locations of * + * every block, blocks are in legal spots, etc. Also recomputes * + * the final placement cost from scratch and makes sure it is * + * within roundoff of what we think the cost is. */ + + static int *bdone; + int i, j, k, error = 0, bnum; + float bb_cost_check; + int usage_check; + float timing_cost_check, delay_cost_check; + int imacro, imember, head_iblk, member_iblk, member_x, member_y, member_z; + + bb_cost_check = comp_bb_cost(CHECK); + vpr_printf(TIO_MESSAGE_INFO, "bb_cost recomputed from scratch: %g\n", bb_cost_check); + if (fabs(bb_cost_check - bb_cost) > bb_cost * ERROR_TOL) { + vpr_printf(TIO_MESSAGE_ERROR, "bb_cost_check: %g and bb_cost: %g differ in check_place.\n", bb_cost_check, bb_cost); + error++; + } + + if (place_algorithm == NET_TIMING_DRIVEN_PLACE + || place_algorithm == PATH_TIMING_DRIVEN_PLACE) { + comp_td_costs(&timing_cost_check, &delay_cost_check); + vpr_printf(TIO_MESSAGE_INFO, "timing_cost recomputed from scratch: %g\n", timing_cost_check); + if (fabs(timing_cost_check - timing_cost) > timing_cost * ERROR_TOL) { + vpr_printf(TIO_MESSAGE_ERROR, "timing_cost_check: %g and timing_cost: %g differ in check_place.\n", + timing_cost_check, timing_cost); + error++; + } + vpr_printf(TIO_MESSAGE_INFO, "delay_cost recomputed from scratch: %g\n", delay_cost_check); + if (fabs(delay_cost_check - delay_cost) > delay_cost * ERROR_TOL) { + vpr_printf(TIO_MESSAGE_ERROR, "delay_cost_check: %g and delay_cost: %g differ in check_place.\n", + delay_cost_check, delay_cost); + error++; + } + } + + bdone = (int *) my_malloc(num_blocks * sizeof(int)); + for (i = 0; i < num_blocks; i++) + bdone[i] = 0; + + /* Step through grid array. Check it against block array. */ + for (i = 0; i <= (nx + 1); i++) + for (j = 0; j <= (ny + 1); j++) { + if (grid[i][j].usage > grid[i][j].type->capacity) { + vpr_printf(TIO_MESSAGE_ERROR, "Block at grid location (%d,%d) overused. Usage is %d.\n", + i, j, grid[i][j].usage); + error++; + } + usage_check = 0; + for (k = 0; k < grid[i][j].type->capacity; k++) { + bnum = grid[i][j].blocks[k]; + if (EMPTY == bnum) + continue; + + if (block[bnum].type != grid[i][j].type) { + vpr_printf(TIO_MESSAGE_ERROR, "Block %d type does not match grid location (%d,%d) type.\n", + bnum, i, j); + error++; + } + if ((block[bnum].x != i) || (block[bnum].y != j)) { + vpr_printf(TIO_MESSAGE_ERROR, "Block %d location conflicts with grid(%d,%d) data.\n", + bnum, i, j); + error++; + } + ++usage_check; + bdone[bnum]++; + } + if (usage_check != grid[i][j].usage) { + vpr_printf(TIO_MESSAGE_ERROR, "Location (%d,%d) usage is %d, but has actual usage %d.\n", + i, j, grid[i][j].usage, usage_check); + error++; + } + } + + /* Check that every block exists in the grid and block arrays somewhere. */ + for (i = 0; i < num_blocks; i++) + if (bdone[i] != 1) { + vpr_printf(TIO_MESSAGE_ERROR, "Block %d listed %d times in data structures.\n", + i, bdone[i]); + error++; + } + free(bdone); + + /* Check the pl_macro placement are legal - blocks are in the proper relative position. */ + for (imacro = 0; imacro < num_pl_macros; imacro++) { + + head_iblk = pl_macros[imacro].members[0].blk_index; + + for (imember = 0; imember < pl_macros[imacro].num_blocks; imember++) { + + member_iblk = pl_macros[imacro].members[imember].blk_index; + + // Compute the suppossed member's x,y,z location + member_x = block[head_iblk].x + pl_macros[imacro].members[imember].x_offset; + member_y = block[head_iblk].y + pl_macros[imacro].members[imember].y_offset; + member_z = block[head_iblk].z + pl_macros[imacro].members[imember].z_offset; + + // Check the block data structure first + if (block[member_iblk].x != member_x + || block[member_iblk].y != member_y + || block[member_iblk].z != member_z) { + vpr_printf(TIO_MESSAGE_ERROR, "Block %d in pl_macro #%d is not placed in the proper orientation.\n", + member_iblk, imacro); + error++; + } + + // Then check the grid data structure + if (grid[member_x][member_y].blocks[member_z] != member_iblk) { + vpr_printf(TIO_MESSAGE_ERROR, "Block %d in pl_macro #%d is not placed in the proper orientation.\n", + member_iblk, imacro); + error++; + } + } // Finish going through all the members + } // Finish going through all the macros + + if (error == 0) { + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "Completed placement consistency check successfully.\n"); + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "Swaps called: %d\n", num_ts_called); + +#ifdef PRINT_REL_POS_DISTR + print_relative_pos_distr(void); +#endif + } else { + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_ERROR, "Completed placement consistency check, %d errors found.\n", error); + vpr_printf(TIO_MESSAGE_INFO, "Aborting program.\n"); + exit(1); + } + +} + +#ifdef VERBOSE +static void print_clb_placement(const char *fname) { + + /* Prints out the clb placements to a file. */ + + FILE *fp; + int i; + + fp = my_fopen(fname, "w", 0); + fprintf(fp, "Complex block placements:\n\n"); + + fprintf(fp, "Block #\tName\t(X, Y, Z).\n"); + for(i = 0; i < num_blocks; i++) { + fprintf(fp, "#%d\t%s\t(%d, %d, %d).\n", i, block[i].name, block[i].x, block[i].y, block[i].z); + } + + fclose(fp); +} +#endif + +static void free_try_swap_arrays(void) { + if(ts_bb_coord_new != NULL) { + free(ts_bb_coord_new); + free(ts_bb_edge_new); + free(ts_nets_to_update); + free(blocks_affected.moved_blocks); + free(bb_updated_before); + + ts_bb_coord_new = NULL; + ts_bb_edge_new = NULL; + ts_nets_to_update = NULL; + blocks_affected.moved_blocks = NULL; + blocks_affected.num_moved_blocks = 0; + bb_updated_before = NULL; + } +} + diff --git a/vpr7_rram/vpr/SRC/place/place.h b/vpr7_rram/vpr/SRC/place/place.h new file mode 100755 index 000000000..2d9d2c8cd --- /dev/null +++ b/vpr7_rram/vpr/SRC/place/place.h @@ -0,0 +1,5 @@ +void try_place(struct s_placer_opts placer_opts, + struct s_annealing_sched annealing_sched, + t_chan_width_dist chan_width_dist, struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf, t_direct_inf *directs, int num_directs); diff --git a/vpr7_rram/vpr/SRC/place/place_macro.c b/vpr7_rram/vpr/SRC/place/place_macro.c new file mode 100644 index 000000000..daa1ea137 --- /dev/null +++ b/vpr7_rram/vpr/SRC/place/place_macro.c @@ -0,0 +1,553 @@ +/**************************************************************************************** + Y.G.THIEN + 29 AUG 2012 + + This file contains functions related to placement macros. The term "placement macros" + refers to a structure that contains information on blocks that need special treatment + during placement and possibly routing. + + An example of placement macros is a carry chain. Blocks in a carry chain have to be + placed in a specific orientation or relative placement so that the carry_in's and the + carry_out's are properly aligned. With that, the carry chains would be able to use the + direct connections specified in the arch file. Direct connections with the pin's + fc_value 0 would be treated specially in routing where the whole carry chain would be + treated as a unit and regular routing would not be used to connect the carry_in's and + carry_out's. Floorplanning constraints may also be an example of placement macros. + + The function alloc_and_load_placement_macros allocates and loads the placement + macros in the following steps: + (1) First, go through all the block types and mark down the pins that could possibly + be part of a placement macros. + (2) Then, go through the netlist of all the pins marked in (1) to find out all the + heads of the placement macros using criteria depending on the type of placement + macros. For carry chains, the heads of the placement macros are blocks with + carry_in's not connected to any nets (OPEN) while the carry_out's connected to the + netlist with only 1 SINK. + (3) Traverse from the heads to the tails of the placement macros and load the + information in the t_pl_macro data structure. Similar to (2), tails are identified + with criteria depending on the type of placement macros. For carry chains, the + tails are blocks with carry_out's not connected to any nets (OPEN) while the + carry_in's is connected to the netlist which has only 1 SINK. + + The only placement macros supported at the moment are the carry chains with limited + functionality. + + Current support for placement macros are: + (1) The arch parser for direct connections is working. The specifications of the direct + connections are specified in sample_adder_arch.xml and also in the + VPR_User_Manual.doc + (2) The placement macros allocator and loader is working. + (3) The initial placement of placement macros that respects the restrictions of the + placement macros is working. + (4) The post-placement legality check for placement macros is working. + + Current limitations on placement macros are: + (1) One block could only be a part of a carry chain. In the future, if a block is part + of multiple placement macros, we should load 1 huge placement macro instead of + multiple placement macros that contain the same block. + (2) Bus direct connections (direct connections with multiple bits) are supported. + However, a 2-bit carry chain when loaded would become 2 1-bit carry chains. + And because of (1), only 1 1-bit carry chain would be loaded. In the future, + placement macros with multiple-bit connections or multiple 1-bit connections + should be allowed. + (3) Placement macros that span longer or wider than the chip would cause an error. + In the future, we *might* expand the size of the chip to accommodate such + placement macros that are crucial. + + In order for the carry chain support to work, two changes are required in the + arch file. + (1) For carry chain support, added in a new child in called . + specifies a list of available direct connections on the FPGA chip + that are necessary for direct carry chain connections. These direct connections + would be treated specially in routing if the fc_value for the pins is specified + as 0. Note that only direct connections that has fc_value 0 could be used as a + carry chain. + + A may have 0 or more children called . For each , + there are the following fields: + 1) name: This specifies the name given to this particular direct connection. + 2) from_pin: This specifies the SOURCEs for this direct connection. The format + could be as following: + a) type_name.port_name, for all the pins in this port. + b) type_name.port_name [end_pin_index:start_pin_index], for a + single pin, the end_pin_index and start_pin_index could be + the same. + 3) to_pin: This specifies the SINKs for this direct connection. The format is + the same as from_pin. + Note that the width of the from_pin and to_pin has to match. + 4) x_offset: This specifies the x direction that this connection is going from + SOURCEs to SINKs. + 5) y_offset: This specifies the y direction that this connection is going from + SOURCEs to SINKs. + Note that the x_offset and y_offset could not both be 0. + 6) z_offset: This specifies the z sublocations that all the blocks in this + direct connection to be at. + + The example of a direct connection specification below shows a possible carry chain + connection going north on the FPGA chip: + _______________________________________________________________________________ + | | + | | + | | + |_______________________________________________________________________________| + A corresponding arch file that has this direct connection is sample_adder_arch.xml + A corresponding blif file that uses this direct connection is adder.blif + + (2) As mentioned in (1), carry chain connections using the directs would only be + recognized if the pin's fc_value is 0. In order to achieve this, pin-based fc_value + is required. Hence, the new tag replaces both and tags. + + A tag may have 0 or more children called . For each , there are the + following fields: + 1) default_in_type: This specifies the default fc_type for input pins. They could + be "frac", "abs" or "full". + 2) default_in_val: This specifies the default fc_value for input pins. + 3) default_out_type: This specifies the default fc_type for output pins. They could + be "frac", "abs" or "full". + 4) default_out_val: This specifies the default fc_value for output pins. + + As for the children, there are the following fields: + 1) name: This specifies the name of the port/pin that the fc_type and fc_value + apply to. The name have to be in the format "port_name" or + "port_name [end_pin_index:start_pin_index]" where port_name is the name + of the port it apply to while end_pin_index and start_pin_index could + be specified to apply the fc_type and fc_value that follows to part of + a bus (multi-pin) port. + 2) fc_type: This specifies the fc_type that would be applied to the specified pins. + 3) fc_val: This specifies the fc_value that would be applied to the specified pins. + + The example of a pin-based fc_value specification below shows that the fc_values for + the cout and the cin ports are 0: + _______________________________________________________________________________ + | | + | | + | | + | | + |_______________________________________________________________________________| + A corresponding arch file that has this direct connection is sample_adder_arch.xml + A corresponding blif file that uses this direct connection is adder.blif + +****************************************************************************************/ + + +#include +#include +#include +#include +#include "util.h" +#include "vpr_types.h" +#include "physical_types.h" +#include "globals.h" +#include "place.h" +#include "read_xml_arch_file.h" +#include "ReadOptions.h" +#include "place_macro.h" +#include "vpr_utils.h" + + +/******************** File-scope variables delcarations **********************/ + +/* f_idirect_from_blk_pin array allow us to quickly find pins that could be in a * + * direct connection. Values stored is the index of the possible direct connection * + * as specified in the arch file, OPEN (-1) is stored for pins that could not be * + * part of a direct chain conneciton. * + * [0...num_types-1][0...num_pins-1] */ +static int ** f_idirect_from_blk_pin = NULL; + +/* f_direct_type_from_blk_pin array stores the value SOURCE if the pin is the * + * from_pin, SINK if the pin is the to_pin in the direct connection as specified in * + * the arch file, OPEN (-1) is stored for pins that could not be part of a direct * + * chain conneciton. * + * [0...num_types-1][0...num_pins-1] */ +static int ** f_direct_type_from_blk_pin = NULL; + +/* f_imacro_from_blk_pin maps a blk_num to the corresponding macro index. * + * If the block is not part of a macro, the value OPEN (-1) is stored. * + * [0...num_blocks-1] */ +static int * f_imacro_from_iblk = NULL; + + +/******************** Subroutine declarations ********************************/ + +static void find_all_the_macro (int * num_of_macro, int * pl_macro_member_blk_num_of_this_blk, + int * pl_macro_idirect, int * pl_macro_num_members, int ** pl_macro_member_blk_num); + +static void free_imacro_from_iblk(void); + +static void alloc_and_load_imacro_from_iblk(t_pl_macro * macros, int num_macros); + +/******************** Subroutine definitions *********************************/ + +static void find_all_the_macro (int * num_of_macro, int * pl_macro_member_blk_num_of_this_blk, + int * pl_macro_idirect, int * pl_macro_num_members, int ** pl_macro_member_blk_num) { + + /* Compute required size: * + * Go through all the pins with possible direct connections in * + * f_idirect_from_blk_pin. Count the number of heads (which is the same * + * as the number macros) and also the length of each macro * + * Head - blocks with to_pin OPEN and from_pin connected * + * Tail - blocks with to_pin connected and from_pin OPEN */ + + int iblk, from_iblk_pin, to_iblk_pin, from_inet, to_inet, from_idirect, to_idirect, + from_src_or_sink, to_src_or_sink; + int next_iblk, curr_iblk, next_inet, curr_inet; + int num_blk_pins, num_macro; + int imember; + + num_macro = 0; + for (iblk = 0; iblk < num_blocks; iblk++) { + + num_blk_pins = block[iblk].type->num_pins; + for (to_iblk_pin = 0; to_iblk_pin < num_blk_pins; to_iblk_pin++) { + + to_inet = block[iblk].nets[to_iblk_pin]; + to_idirect = f_idirect_from_blk_pin[block[iblk].type->index][to_iblk_pin]; + to_src_or_sink = f_direct_type_from_blk_pin[block[iblk].type->index][to_iblk_pin]; + + // Find to_pins (SINKs) with possible direct connection but are not + // connected to any net (Possible head of macro) + if ( to_src_or_sink == SINK && to_idirect != OPEN && to_inet == OPEN ) { + + for (from_iblk_pin = 0; from_iblk_pin < num_blk_pins; from_iblk_pin++) { + from_inet = block[iblk].nets[from_iblk_pin]; + from_idirect = f_idirect_from_blk_pin[block[iblk].type->index][from_iblk_pin]; + from_src_or_sink = f_direct_type_from_blk_pin[block[iblk].type->index][from_iblk_pin]; + + // Find from_pins with the same possible direct connection that are connected. + // Confirmed head of macro + if ( from_src_or_sink == SOURCE && to_idirect == from_idirect && from_inet != OPEN) { + + // Mark down that this is the first block in the macro + pl_macro_member_blk_num_of_this_blk[0] = iblk; + pl_macro_idirect[num_macro] = to_idirect; + + // Increment the num_member count. + pl_macro_num_members[num_macro]++; + + // Also find out how many members are in the macros, + // there are at least 2 members - 1 head and 1 tail. + + // Initialize the variables + next_inet = from_inet; + next_iblk = iblk; + + // Start finding the other members + while (next_inet != OPEN) { + + curr_iblk = next_iblk; + curr_inet = next_inet; + + // Assume that carry chains only has 1 sink - direct connection + if (clb_net[curr_inet].num_sinks != 1) { + assert(clb_net[curr_inet].num_sinks == 1); + } + next_iblk = clb_net[curr_inet].node_block[1]; + + // Assume that the from_iblk_pin index is the same for the next block + assert (f_idirect_from_blk_pin[block[next_iblk].type->index][from_iblk_pin] == from_idirect + && f_direct_type_from_blk_pin[block[next_iblk].type->index][from_iblk_pin] == SOURCE); + next_inet = block[next_iblk].nets[from_iblk_pin]; + + // Mark down this block as a member of the macro + imember = pl_macro_num_members[num_macro]; + pl_macro_member_blk_num_of_this_blk[imember] = next_iblk; + /* Xifan TANG: Should detect if there is a combinational loop inside */ + if (1 == spot_int_in_array(imember, pl_macro_member_blk_num_of_this_blk, next_iblk )) { + vpr_printf(TIO_MESSAGE_INFO, "Find a combinational loop in macro placement! More info:\n"); + vpr_printf(TIO_MESSAGE_ERROR,"next_inet: %d, num_macro: %d, imember: %d, next_iblk: %d.\n", + next_inet, num_macro, imember, next_iblk); + exit(1); + } + // Increment the num_member count. + pl_macro_num_members[num_macro]++; + + } // Found all the members of this macro at this point + + // Allocate the second dimension of the blk_num array since I now know the size + pl_macro_member_blk_num[num_macro] = + (int *) my_calloc (pl_macro_num_members[num_macro] , sizeof(int)); + // Copy the data from the temporary array to the newly allocated array. + for (imember = 0; imember < pl_macro_num_members[num_macro]; imember ++) + pl_macro_member_blk_num[num_macro][imember] = pl_macro_member_blk_num_of_this_blk[imember]; + + // Increment the macro count + num_macro ++; + + } // Do nothing if the from_pins does not have same possible direct connection. + } // Finish going through all the pins for from_pins. + } // Do nothing if the to_pins does not have same possible direct connection. + } // Finish going through all the pins for to_pins. + } // Finish going through all blocks. + + // Now, all the data is readily stored in the temporary data structures. + *num_of_macro = num_macro; +} + + +int alloc_and_load_placement_macros(t_direct_inf* directs, int num_directs, t_pl_macro ** macros){ + + /* This function allocates and loads the macros placement macros * + * and returns the total number of macros in 2 steps. * + * 1) Allocate temporary data structure for maximum possible * + * size and loops through all the blocks storing the data * + * relevant to the carry chains. At the same time, also count * + * the amount of memory required for the actual variables. * + * 2) Allocate the actual variables with the exact amount of * + * memory. Then loads the data from the temporary data * + * structures before freeing them. * + * * + * For pl_macro_member_blk_num, allocate for the first dimension * + * only at first. Allocate for the second dimemsion when I know * + * the size. Otherwise, the array is going to be of size * + * num_blocks^2 (There are big benckmarks VPR that have num_blocks * + * in the 100k's range). * + * * + * The placement macro array is freed by the caller(s). */ + + /* Declaration of local variables */ + int imacro, imember, num_macro; + int *pl_macro_idirect, *pl_macro_num_members, **pl_macro_member_blk_num, + *pl_macro_member_blk_num_of_this_blk; + + t_pl_macro * macro = NULL; + + /* Sets up the required variables. */ + alloc_and_load_idirect_from_blk_pin(directs, num_directs, + &f_idirect_from_blk_pin, &f_direct_type_from_blk_pin); + + /* Allocate maximum memory for temporary variables. */ + pl_macro_num_members = (int *) my_calloc (num_blocks , sizeof(int)); + pl_macro_idirect = (int *) my_calloc (num_blocks , sizeof(int)); + pl_macro_member_blk_num = (int **) my_calloc (num_blocks , sizeof(int*)); + pl_macro_member_blk_num_of_this_blk = (int *) my_calloc (num_blocks , sizeof(int)); + + /* Compute required size: * + * Go through all the pins with possible direct connections in * + * f_idirect_from_blk_pin. Count the number of heads (which is the same * + * as the number macros) and also the length of each macro * + * Head - blocks with to_pin OPEN and from_pin connected * + * Tail - blocks with to_pin connected and from_pin OPEN */ + num_macro = 0; + find_all_the_macro (&num_macro, pl_macro_member_blk_num_of_this_blk, + pl_macro_idirect, pl_macro_num_members, pl_macro_member_blk_num); + + /* Allocate the memories for the macro. */ + macro = (t_pl_macro *) my_malloc (num_macro * sizeof(t_pl_macro)); + + /* Allocate the memories for the chaim members. * + * Load the values from the temporary data structures. */ + for (imacro = 0; imacro < num_macro; imacro++) { + macro[imacro].num_blocks = pl_macro_num_members[imacro]; + macro[imacro].members = (t_pl_macro_member *) my_malloc + (macro[imacro].num_blocks * sizeof(t_pl_macro_member)); + + /* Load the values for each member of the macro */ + for (imember = 0; imember < macro[imacro].num_blocks; imember++) { + macro[imacro].members[imember].x_offset = imember * directs[pl_macro_idirect[imacro]].x_offset; + macro[imacro].members[imember].y_offset = imember * directs[pl_macro_idirect[imacro]].y_offset; + macro[imacro].members[imember].z_offset = directs[pl_macro_idirect[imacro]].z_offset; + macro[imacro].members[imember].blk_index = pl_macro_member_blk_num[imacro][imember]; + } + } + + /* Frees up the temporary data structures. */ + free(pl_macro_num_members); + free(pl_macro_idirect); + for(imacro=0; imacro < num_macro; imacro++) { + free(pl_macro_member_blk_num[imacro]); + } + free(pl_macro_member_blk_num); + free(pl_macro_member_blk_num_of_this_blk); + + /* Returns the pointer to the macro by reference. */ + *macros = macro; + return (num_macro); + +} + +void get_imacro_from_iblk(int * imacro, int iblk, t_pl_macro * macros, int num_macros) { + + /* This mapping is needed for fast lookup's whether the block with index * + * iblk belongs to a placement macro or not. * + * * + * The array f_imacro_from_iblk is used for the mapping for speed reason * + * [0...num_blocks-1] */ + + /* If the array is not allocated and loaded, allocate it. */ + if (f_imacro_from_iblk == NULL) { + alloc_and_load_imacro_from_iblk(macros, num_macros); + } + + /* Return the imacro for the block. */ + *imacro = f_imacro_from_iblk[iblk]; + +} + +static void free_imacro_from_iblk(void) { + + /* Frees the f_imacro_from_iblk array. * + * * + * This function is called when the arrays are freed in * + * free_placement_structs() */ + + if (f_imacro_from_iblk != NULL) { + free(f_imacro_from_iblk); + f_imacro_from_iblk = NULL; + } + +} + +static void alloc_and_load_imacro_from_iblk(t_pl_macro * macros, int num_macros) { + + /* Allocates and loads imacro_from_iblk array. * + * * + * The array is freed in free_placement_structs() */ + + int * temp_imacro_from_iblk = NULL; + int imacro, imember, iblk; + + /* Allocate and initialize the values to OPEN (-1). */ + temp_imacro_from_iblk = (int *)my_malloc(num_blocks * sizeof(int)); + for(iblk = 0; iblk < num_blocks; iblk ++) { + temp_imacro_from_iblk[iblk] = OPEN; + } + + /* Load the values */ + for (imacro = 0; imacro < num_macros; imacro++) { + for (imember = 0; imember < macros[imacro].num_blocks; imember++) { + iblk = macros[imacro].members[imember].blk_index; + temp_imacro_from_iblk[iblk] = imacro; + } + } + + /* Sets the file_scope variables to point at the arrays. */ + f_imacro_from_iblk = temp_imacro_from_iblk; +} + +void free_placement_macros_structs(void) { + + /* This function frees up all the static data structures used. */ + + // This frees up the two arrays and set the pointers to NULL + int itype; + if ( f_idirect_from_blk_pin != NULL ) { + for (itype = 1; itype < num_types; itype++) { + free(f_idirect_from_blk_pin[itype]); + } + free(f_idirect_from_blk_pin); + f_idirect_from_blk_pin = NULL; + } + + if ( f_direct_type_from_blk_pin != NULL ) { + for (itype = 1; itype < num_types; itype++) { + free(f_direct_type_from_blk_pin[itype]); + } + free(f_direct_type_from_blk_pin); + f_direct_type_from_blk_pin = NULL; + } + + // This frees up the imacro from iblk mapping array. + free_imacro_from_iblk(); + +} + +/* Xifan TANG: Find the position of a blk in a macro */ +int spot_blk_position_in_a_macro(t_pl_macro pl_macros, + int blk_idx) { + int imember; + + for (imember = 0; imember < pl_macros.num_blocks; imember++) { + if (blk_idx == pl_macros.members[imember].blk_index) { + return imember; + } + } + + return -1; +} + +/* Xifan TANG: Check if 1st macro contains the 2nd macro */ +void get_start_end_points_one_macro(t_pl_macro pl_macro, + int* upper_x, int* lower_x, + int* upper_y, int* lower_y) { + int imemb, iblk; + + /* Initialize */ + (*upper_x) = -1; + (*lower_x) = -1; + (*upper_y) = -1; + (*lower_y) = -1; + + /* Determine the upper/lower bound of x,y of macros*/ + for (imemb = 0; imemb < pl_macro.num_blocks; imemb++) { + iblk = pl_macro.members[imemb].blk_index; + if (0 == imemb) { + (*upper_x) = block[iblk].x; + (*upper_y) = block[iblk].y; + (*lower_x) = block[iblk].x; + (*lower_y) = block[iblk].y; + /* macro_a_upper_z = block[iblk_a].z; */ + } else { + if (block[iblk].x > (*upper_x)) { + (*upper_x) = block[iblk].x; + } + if (block[iblk].y > (*upper_y)) { + (*upper_y) = block[iblk].y; + } + if (block[iblk].x < (*lower_x)) { + (*lower_x) = block[iblk].x; + } + if (block[iblk].y < (*lower_y)) { + (*lower_y) = block[iblk].y; + } + } + } + /* check: this is currently true, as carry chain is vertical + * maybe changed if a new carry chain style is applied */ + if (!(((*upper_x) == (*lower_x))&&(((*upper_y) - (*lower_y) + 1) == (pl_macro.num_blocks)))) { + assert (((*upper_x) == (*lower_x))&&(((*upper_y) - (*lower_y) + 1) == (pl_macro.num_blocks))); + } +} + +/* Xifan TANG: Check if 1st macro contains the 2nd macro */ +int check_macros_contained(t_pl_macro pl_macro_a, + t_pl_macro pl_macro_b) { + int macro_a_upper_x, macro_a_upper_y; + int macro_a_lower_x, macro_a_lower_y; + int macro_b_upper_x, macro_b_upper_y; + int macro_b_lower_x, macro_b_lower_y; + + get_start_end_points_one_macro(pl_macro_a, ¯o_a_upper_x, ¯o_a_lower_x, + ¯o_a_upper_y, ¯o_a_lower_y); + + get_start_end_points_one_macro(pl_macro_b, ¯o_b_upper_x, ¯o_b_lower_x, + ¯o_b_upper_y, ¯o_b_lower_y); + + if ((macro_a_upper_y < macro_b_upper_y)||(macro_a_lower_y > macro_b_lower_y)) { + return 0; + } + + return 1; +} + +/* Xifan TANG: get the maximum length of macros */ +int max_len_pl_macros(int num_pl_macros, + t_pl_macro* pl_macros) { + int imacro; + int max_len = 0; + + if (0 == num_pl_macros) { + return max_len; + } + + assert(NULL != pl_macros); + + for (imacro = 0; imacro < num_pl_macros; imacro++) { + if (max_len < pl_macros[imacro].num_blocks) { + max_len = pl_macros[imacro].num_blocks; + } + } + + return max_len; +} diff --git a/vpr7_rram/vpr/SRC/place/place_macro.h b/vpr7_rram/vpr/SRC/place/place_macro.h new file mode 100644 index 000000000..c1914f277 --- /dev/null +++ b/vpr7_rram/vpr/SRC/place/place_macro.h @@ -0,0 +1,176 @@ +/**************************************************************************************** + Y.G.THIEN + 29 AUG 2012 + + This file contains functions related to placement macros. The term "placement macros" + refers to a structure that contains information on blocks that need special treatment + during placement and possibly routing. + + An example of placement macros is a carry chain. Blocks in a carry chain have to be + placed in a specific orientation or relative placement so that the carry_in's and the + carry_out's are properly aligned. With that, the carry chains would be able to use the + direct connections specified in the arch file. Direct connections with the pin's + fc_value 0 would be treated specially in routing where the whole carry chain would be + treated as a unit and regular routing would not be used to connect the carry_in's and + carry_out's. Floorplanning constraints may also be an example of placement macros. + + The function alloc_and_load_placement_macros allocates and loads the placement + macros in the following steps: + (1) First, go through all the block types and mark down the pins that could possibly + be part of a placement macros. + (2) Then, go through the netlist of all the pins marked in (1) to find out all the + heads of the placement macros using criteria depending on the type of placement + macros. For carry chains, the heads of the placement macros are blocks with + carry_in's not connected to any nets (OPEN) while the carry_out's connected to the + netlist with only 1 SINK. + (3) Traverse from the heads to the tails of the placement macros and load the + information in the t_pl_macro data structure. Similar to (2), tails are identified + with criteria depending on the type of placement macros. For carry chains, the + tails are blocks with carry_out's not connected to any nets (OPEN) while the + carry_in's is connected to the netlist which has only 1 SINK. + + The only placement macros supported at the moment are the carry chains with limited + functionality. + + Current support for placement macros are: + (1) The arch parser for direct connections is working. The specifications of the direct + connections are specified in sample_adder_arch.xml and also in the + VPR_User_Manual.doc + (2) The placement macros allocator and loader is working. + (3) The initial placement of placement macros that respects the restrictions of the + placement macros is working. + (4) The post-placement legality check for placement macros is working. + + Current limitations on placement macros are: + (1) One block could only be a part of a carry chain. In the future, if a block is part + of multiple placement macros, we should load 1 huge placement macro instead of + multiple placement macros that contain the same block. + (2) Bus direct connections (direct connections with multiple bits) are supported. + However, a 2-bit carry chain when loaded would become 2 1-bit carry chains. + And because of (1), only 1 1-bit carry chain would be loaded. In the future, + placement macros with multiple-bit connections or multiple 1-bit connections + should be allowed. + (3) Placement macros that span longer or wider than the chip would cause an error. + In the future, we *might* expand the size of the chip to accommodate such + placement macros that are crucial. + + In order for the carry chain support to work, two changes are required in the + arch file. + (1) For carry chain support, added in a new child in called . + specifies a list of available direct connections on the FPGA chip + that are necessary for direct carry chain connections. These direct connections + would be treated specially in routing if the fc_value for the pins is specified + as 0. Note that only direct connections that has fc_value 0 could be used as a + carry chain. + + A may have 0 or more children called . For each , + there are the following fields: + 1) name: This specifies the name given to this particular direct connection. + 2) from_pin: This specifies the SOURCEs for this direct connection. The format + could be as following: + a) type_name.port_name, for all the pins in this port. + b) type_name.port_name [end_pin_index:start_pin_index], for a + single pin, the end_pin_index and start_pin_index could be + the same. + 3) to_pin: This specifies the SINKs for this direct connection. The format is + the same as from_pin. + Note that the width of the from_pin and to_pin has to match. + 4) x_offset: This specifies the x direction that this connection is going from + SOURCEs to SINKs. + 5) y_offset: This specifies the y direction that this connection is going from + SOURCEs to SINKs. + Note that the x_offset and y_offset could not both be 0. + 6) z_offset: This specifies the z sublocations that all the blocks in this + direct connection to be at. + + The example of a direct connection specification below shows a possible carry chain + connection going north on the FPGA chip: + _______________________________________________________________________________ + | | + | | + | | + |_______________________________________________________________________________| + A corresponding arch file that has this direct connection is sample_adder_arch.xml + A corresponding blif file that uses this direct connection is adder.blif + + (2) As mentioned in (1), carry chain connections using the directs would only be + recognized if the pin's fc_value is 0. In order to achieve this, pin-based fc_value + is required. Hence, the new tag replaces both and tags. + + A tag may have 0 or more children called . For each , there are the + following fields: + 1) default_in_type: This specifies the default fc_type for input pins. They could + be "frac", "abs" or "full". + 2) default_in_val: This specifies the default fc_value for input pins. + 3) default_out_type: This specifies the default fc_type for output pins. They could + be "frac", "abs" or "full". + 4) default_out_val: This specifies the default fc_value for output pins. + + As for the children, there are the following fields: + 1) name: This specifies the name of the port/pin that the fc_type and fc_value + apply to. The name have to be in the format "port_name" or + "port_name [end_pin_index:start_pin_index]" where port_name is the name + of the port it apply to while end_pin_index and start_pin_index could + be specified to apply the fc_type and fc_value that follows to part of + a bus (multi-pin) port. + 2) fc_type: This specifies the fc_type that would be applied to the specified pins. + 3) fc_val: This specifies the fc_value that would be applied to the specified pins. + + The example of a pin-based fc_value specification below shows that the fc_values for + the cout and the cin ports are 0: + _______________________________________________________________________________ + | | + | | + | | + | | + |_______________________________________________________________________________| + A corresponding arch file that has this direct connection is sample_adder_arch.xml + A corresponding blif file that uses this direct connection is adder.blif + +****************************************************************************************/ + + +#ifndef PLACE_MACRO_H +#define PALCE_MACRO_H + +/* These are the placement macro structure. + * It is in the form of array of structs instead of + * structs of arrays for cache efficiency. + * Could have more data members for other macro type. + * blk_index: The block index of this block. + * x_offset: The x_offset of the previous block to this block. + * y_offset: The y_offset of the previous block to this block. + */ +typedef struct s_pl_macro_member{ + int blk_index; + int x_offset; + int y_offset; + int z_offset; +} t_pl_macro_member; + +/* num_blocks: The number of blocks this macro contains. + * members: An array of blocks in this macro [0กญnum_macro-1]. + * idirect: The direct index as specified in the arch file + */ +typedef struct s_pl_macro{ + int num_blocks; + t_pl_macro_member* members; +} t_pl_macro; + +/* These are the function declarations. */ +int alloc_and_load_placement_macros(t_direct_inf* directs, int num_directs, t_pl_macro ** chains); +void get_imacro_from_iblk(int * imacro, int iblk, t_pl_macro * macros, int num_macros); +void free_placement_macros_structs(void); + +/* Xifan TANG: spot the position of a block in a macro*/ +int spot_blk_position_in_a_macro(t_pl_macro pl_macros, int blk_idx); + +int check_macros_contained(t_pl_macro pl_macro_a, + t_pl_macro pl_macro_b); + +int max_len_pl_macros(int num_pl_macros, + t_pl_macro* pl_macros); + +#endif diff --git a/vpr7_rram/vpr/SRC/place/place_stats.c b/vpr7_rram/vpr/SRC/place/place_stats.c new file mode 100755 index 000000000..d7d1d3f26 --- /dev/null +++ b/vpr7_rram/vpr/SRC/place/place_stats.c @@ -0,0 +1,152 @@ +#include +#include +#include "util.h" +#include "vpr_types.h" +#include "globals.h" + +#define ABS_DIFF(X, Y) (((X) > (Y))? ((X) - (Y)):((Y) - (X))) +#define MAX_X 50 +#define MAX_LEN MAX_X*2 + +typedef struct relapos_rec_s { + int num_rp[MAX_LEN]; +} relapos_rec_t; + +#ifdef PRINT_REL_POS_DISTR +void +print_relative_pos_distr(void) +{ + + /* Prints out the probability distribution of the relative locations of * + * input pins on a net -- i.e. simulates 2-point net distance probability * + * distribution. */ +#ifdef PRINT_REL_POS_DISTR + FILE *out_bin_file; + relapos_rec_t rp_rec; +#endif /* PRINT_REL_POS_DISTR */ + + int inet, len, rp, src_x, src_y, dst_x, dst_y, del_x, del_y, min_del, + sink_pin, sum; + int *total_conn; + int **relapos; + double **relapos_distr; + + total_conn = (int *)my_malloc((nx + ny + 1) * sizeof(int)); + relapos = (int **)my_malloc((nx + ny + 1) * sizeof(int *)); + relapos_distr = (double **)my_malloc((nx + ny + 1) * sizeof(double *)); + for (len = 0; len <= nx + ny; len++) + { + relapos[len] = (int *)my_calloc(len / 2 + 1, sizeof(int)); + relapos_distr[len] = + (double *)my_calloc((len / 2 + 1), sizeof(double)); + } + + for (inet = 0; inet < num_nets; inet++) + { + if (clb_net[inet].is_global == FALSE) + { + + src_x = block[clb_net[inet].node_block[0]].x; + src_y = block[clb_net[inet].node_block[0]].y; + + for (sink_pin = 1; sink_pin <= clb_net[inet].num_sinks; + sink_pin++) + { + dst_x = block[clb_net[inet].node_block[sink_pin]].x; + dst_y = block[clb_net[inet].node_block[sink_pin]].y; + + del_x = ABS_DIFF(dst_x, src_x); + del_y = ABS_DIFF(dst_y, src_y); + + len = del_x + del_y; + + min_del = (del_x < del_y) ? del_x : del_y; + + if (!(min_del <= (len / 2))) + { + vpr_printf(TIO_MESSAGE_ERROR, "Error calculating relative location min_del = %d, len = %d\n", + min_del, len); + exit(1); + } + else + { + relapos[len][min_del]++; + } + } + } + } + +#ifdef PRINT_REL_POS_DISTR + out_bin_file = + fopen("/jayar/b/b5/fang/vpr_test/wirelength/relapos2.bin", "rb+"); +#endif /* PRINT_REL_POS_DISTR */ + + for (len = 0; len <= nx + ny; len++) + { + sum = 0; + for (rp = 0; rp <= len / 2; rp++) + { + sum += relapos[len][rp]; + } + if (sum != 0) + { +#ifdef PRINT_REL_POS_DISTR + fseek(out_bin_file, sizeof(relapos_rec_t) * len, + SEEK_SET); + fread(&rp_rec, sizeof(relapos_rec_t), 1, out_bin_file); +#endif /* PRINT_REL_POS_DISTR */ + + for (rp = 0; rp <= len / 2; rp++) + { + + relapos_distr[len][rp] = + (double)relapos[len][rp] / (double)sum; + + /* updating the binary record at "len" */ +#ifdef PRINT_REL_POS_DISTR + vpr_printf(TIO_MESSAGE_ERROR, "old %d increased by %d\n", rp_rec.num_rp[rp], relapos[len][rp]); + rp_rec.num_rp[rp] += relapos[len][rp]; + vpr_printf(TIO_MESSAGE_ERROR, "becomes %d\n", rp_rec.num_rp[rp]); +#endif /* PRINT_REL_POS_DISTR */ + } +#ifdef PRINT_REL_POS_DISTR + /* write back the updated record at "len" */ + fseek(out_bin_file, sizeof(relapos_rec_t) * len, + SEEK_SET); + fwrite(&rp_rec, sizeof(relapos_rec_t), 1, out_bin_file); +#endif /* PRINT_REL_POS_DISTR */ + + } + total_conn[len] = sum; + } + + fprintf(stdout, "Source to sink relative positions:\n"); + for (len = 1; len <= nx + ny; len++) + { + if (total_conn[len] != 0) + { + fprintf(stdout, "Of 2-pin distance %d exists %d\n\n", len, + total_conn[len]); + for (rp = 0; rp <= len / 2; rp++) + { + fprintf(stdout, "\trp%d\t%d\t\t(%.5f)\n", rp, + relapos[len][rp], relapos_distr[len][rp]); + } + fprintf(stdout, "----------------\n"); + } + } + + free((void *)total_conn); + for (len = 0; len <= nx + ny; len++) + { + free((void *)relapos[len]); + free((void *)relapos_distr[len]); + } + free((void *)relapos); + free((void *)relapos_distr); + +#ifdef PRINT_REL_POS_DISTR + fclose(out_bin_file); +#endif /* PRINT_REL_POS_DISTR */ +} +#endif diff --git a/vpr7_rram/vpr/SRC/place/place_stats.h b/vpr7_rram/vpr/SRC/place/place_stats.h new file mode 100755 index 000000000..67b451b18 --- /dev/null +++ b/vpr7_rram/vpr/SRC/place/place_stats.h @@ -0,0 +1,7 @@ +#ifdef PRINT_REL_POS_DISTR +void print_relative_pos_distr(void); + +/* Prints out the probability distribution of the relative locations of * + * input pins on a net -- i.e. simulates 2-point net length probability * + * distribution. */ +#endif diff --git a/vpr7_rram/vpr/SRC/place/timing_place.c b/vpr7_rram/vpr/SRC/place/timing_place.c new file mode 100755 index 000000000..c6805ae3d --- /dev/null +++ b/vpr7_rram/vpr/SRC/place/timing_place.c @@ -0,0 +1,152 @@ +#include +#include +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "path_delay.h" +#include "path_delay2.h" +#include "net_delay.h" +#include "timing_place_lookup.h" +#include "timing_place.h" + +float **timing_place_crit; /*available externally */ + +static t_chunk timing_place_crit_ch = {NULL, 0, NULL}; +static t_chunk net_delay_ch = {NULL, 0, NULL}; + +/*static struct s_linked_vptr *timing_place_crit_chunk_list_head; +static struct s_linked_vptr *net_delay_chunk_list_head;*/ + +/******** prototypes ******************/ +/*static float **alloc_crit(struct s_linked_vptr **chunk_list_head_ptr); + +static void free_crit(struct s_linked_vptr **chunk_list_head_ptr);*/ + +static float **alloc_crit(t_chunk *chunk_list_ptr); + +static void free_crit(t_chunk *chunk_list_ptr); + +/**************************************/ + +static float ** alloc_crit(t_chunk *chunk_list_ptr) { + + /* Allocates space for the timing_place_crit data structure * + * [0..num_nets-1][1..num_pins-1]. I chunk the data to save space on large * + * problems. */ + + float **local_crit; /* [0..num_nets-1][1..num_pins-1] */ + float *tmp_ptr; + int inet; + + local_crit = (float **) my_malloc(num_nets * sizeof(float *)); + + for (inet = 0; inet < num_nets; inet++) { + tmp_ptr = (float *) my_chunk_malloc( + (clb_net[inet].num_sinks) * sizeof(float), chunk_list_ptr); + local_crit[inet] = tmp_ptr - 1; /* [1..num_sinks] */ + } + + return (local_crit); +} + +/**************************************/ +static void free_crit(t_chunk *chunk_list_ptr){ + free_chunk_memory(chunk_list_ptr); +} + +/**************************************/ +void print_sink_delays(const char *fname) { + + int num_at_level, num_edges, inode, ilevel, i; + FILE *fp; + + fp = my_fopen(fname, "w", 0); + + for (ilevel = num_tnode_levels - 1; ilevel >= 0; ilevel--) { + num_at_level = tnodes_at_level[ilevel].nelem; + + for (i = 0; i < num_at_level; i++) { + inode = tnodes_at_level[ilevel].list[i]; + num_edges = tnode[inode].num_edges; + + if (num_edges == 0) { /* sink */ + fprintf(fp, "%g\n", tnode[inode].T_arr); + } + } + } + fclose(fp); +} + +/**************************************/ +void load_criticalities(t_slack * slacks, float crit_exponent) { + /* Performs a 1-to-1 mapping from criticality to timing_place_crit. + For every pin on every net (or, equivalently, for every tedge ending + in that pin), timing_place_crit = criticality^(criticality exponent) */ + + int inet, ipin; +#ifdef PATH_COUNTING + float timing_criticality, path_criticality; +#endif + + for (inet = 0; inet < num_nets; inet++) { + if (inet == OPEN) + continue; + if (clb_net[inet].is_global) + continue; + for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) { + if (slacks->timing_criticality[inet][ipin] < HUGE_NEGATIVE_FLOAT + 1) { + /* We didn't analyze this connection, so give it a timing_place_crit of 0. */ + timing_place_crit[inet][ipin] = 0.; + } else { +#ifdef PATH_COUNTING + /* Calculate criticality as a weighted sum of timing criticality and path + criticality. The placer likes a great deal of contrast between criticalities. + Since path criticality varies much more than timing, we "sharpen" timing + criticality by taking it to some power, crit_exponent (between 1 and 8 by default). */ + path_criticality = slacks->path_criticality[inet][ipin]; + timing_criticality = pow(slacks->timing_criticality[inet][ipin], crit_exponent); + + timing_place_crit[inet][ipin] = PLACE_PATH_WEIGHT * path_criticality + + (1 - PLACE_PATH_WEIGHT) * timing_criticality; +#else + /* Just take timing criticality to some power (crit_exponent). */ + timing_place_crit[inet][ipin] = pow(slacks->timing_criticality[inet][ipin], crit_exponent); +#endif + } + } + } +} + +/**************************************/ +t_slack * alloc_lookups_and_criticalities(t_chan_width_dist chan_width_dist, + struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf, float ***net_delay, INP t_direct_inf *directs, + INP int num_directs) { + + t_slack * slacks = alloc_and_load_timing_graph(timing_inf); + + (*net_delay) = alloc_net_delay(&net_delay_ch, clb_net, + num_nets); + + compute_delay_lookup_tables(router_opts, det_routing_arch, segment_inf, + timing_inf, chan_width_dist, directs, num_directs); + + timing_place_crit = alloc_crit(&timing_place_crit_ch); + + return slacks; +} + +/**************************************/ +void free_lookups_and_criticalities(float ***net_delay, t_slack * slacks) { + + free(timing_place_crit); + free_crit(&timing_place_crit_ch); + + free_timing_graph(slacks); + free_net_delay(*net_delay, &net_delay_ch); + + free_place_lookup_structs(); +} + +/**************************************/ diff --git a/vpr7_rram/vpr/SRC/place/timing_place.h b/vpr7_rram/vpr/SRC/place/timing_place.h new file mode 100755 index 000000000..c53dccaf9 --- /dev/null +++ b/vpr7_rram/vpr/SRC/place/timing_place.h @@ -0,0 +1,18 @@ +#ifndef TIMING_PLACE +#define TIMING_PLACE + +t_slack * alloc_lookups_and_criticalities(t_chan_width_dist chan_width_dist, + struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf, float ***net_delay, INP t_direct_inf *directs, + INP int num_directs); + +void free_lookups_and_criticalities(float ***net_delay, t_slack * slacks); + +void print_sink_delays(const char *fname); + +void load_criticalities(t_slack * slacks, float crit_exponent); + +extern float **timing_place_crit; + +#endif diff --git a/vpr7_rram/vpr/SRC/place/timing_place_lookup.c b/vpr7_rram/vpr/SRC/place/timing_place_lookup.c new file mode 100755 index 000000000..88a4e7a29 --- /dev/null +++ b/vpr7_rram/vpr/SRC/place/timing_place_lookup.c @@ -0,0 +1,1065 @@ +#include +#include +#include +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "route_common.h" +#include "place_and_route.h" +#include "route_tree_timing.h" +#include "route_timing.h" +#include "timing_place_lookup.h" +#include "rr_graph.h" +#include "route_export.h" +#include +#include "read_xml_arch_file.h" + +/* mrFPGA : Xifan TANG */ +#include "mrfpga_globals.h" +#include "net_delay_types.h" +#include "net_delay_local_void.h" +/* end */ + +/*this file contains routines that generate the array containing*/ +/*the delays between blocks, this is used in the timing driven */ +/*placement routines */ + +/*To compute delay between blocks we place temporary blocks at */ +/*different locations in the FPGA and route nets between */ +/*the blocks. From this procedure we generate a lookup table */ +/*which tells us the delay between different locations in */ +/*the FPGA */ + +/*Note: these routines assume that there is a uniform and even */ +/*distribution of the different wire segments. If this is not */ +/*the case, then this lookup table will be off */ + +/*Note: This code removes all heterogeneous types and creates an + artificial 1x1 tile. A good lookup for heterogeniety + requires more research */ + +#define NET_COUNT 1 /*we only use one net in these routines, */ +/*it is repeatedly routed and ripped up */ +/*to compute delays between different */ +/*locations, this value should not change */ +#define NET_USED 0 /*we use net at location zero of the net */ +/*structure */ +#define NET_USED_SOURCE_BLOCK 0 /*net.block[0] is source block */ +#define NET_USED_SINK_BLOCK 1 /*net.block[1] is sink block */ +#define SOURCE_BLOCK 0 /*block[0] is source */ +#define SINK_BLOCK 1 /*block[1] is sink */ + +#define BLOCK_COUNT 2 /*use 2 blocks to compute delay between */ +/*the various FPGA locations */ +/*do not change this number unless you */ +/*really know what you are doing, it is */ +/*assumed that the net only connects to */ +/*two blocks */ + +#define NUM_TYPES_USED 3 /* number of types used in look up */ + +#define DEBUG_TIMING_PLACE_LOOKUP /*initialize arrays to known state */ + +#define DUMPFILE "lookup_dump.echo" +/* #define PRINT_ARRAYS *//*only used during debugging, calls routine to */ +/*print out the various lookup arrays */ + +/***variables that are exported to other modules***/ + +/*the delta arrays are used to contain the best case routing delay */ +/*between different locations on the FPGA. */ + +float **delta_io_to_clb; +float **delta_clb_to_clb; +float **delta_clb_to_io; +float **delta_io_to_io; + +/*** Other Global Arrays ******/ +/* I could have allocated these as local variables, and passed them all */ +/* around, but was too lazy, since this is a small file, it should not */ +/* be a big problem */ + +static float **net_delay; +static float *pin_criticality; +static int *sink_order; +static t_rt_node **rt_node_of_sink; +static t_type_ptr IO_TYPE_BACKUP; +static t_type_ptr EMPTY_TYPE_BACKUP; +static t_type_ptr FILL_TYPE_BACKUP; +static t_type_descriptor dummy_type_descriptors[NUM_TYPES_USED]; +static t_type_descriptor *type_descriptors_backup; +static struct s_grid_tile **grid_backup; +static int num_types_backup; + +static t_ivec **clb_opins_used_locally; + +#ifdef PRINT_ARRAYS +static FILE *lookup_dump; /* If debugging mode is on, print out to + * the file defined in DUMPFILE */ +#endif /* PRINT_ARRAYS */ + +/*** Function Prototypes *****/ + +static void alloc_net(void); + +static void alloc_block(void); + +static void load_simplified_device(void); +static void restore_original_device(void); + +static void alloc_and_assign_internal_structures(struct s_net **original_net, + struct s_block **original_block, int *original_num_nets, + int *original_num_blocks); + +static void free_and_reset_internal_structures(struct s_net *original_net, + struct s_block *original_block, int original_num_nets, + int original_num_blocks); + +static void setup_chan_width(struct s_router_opts router_opts, + t_chan_width_dist chan_width_dist); + +static void alloc_routing_structs(struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf, INP t_direct_inf *directs, + INP int num_directs); + +static void free_routing_structs(struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf); + +static void assign_locations(t_type_ptr source_type, int source_x_loc, + int source_y_loc, int source_z_loc, t_type_ptr sink_type, + int sink_x_loc, int sink_y_loc, int sink_z_loc); + +static float assign_blocks_and_route_net(t_type_ptr source_type, + int source_x_loc, int source_y_loc, t_type_ptr sink_type, + int sink_x_loc, int sink_y_loc, struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf); + +static void alloc_delta_arrays(void); + +static void free_delta_arrays(void); + +static void generic_compute_matrix(float ***matrix_ptr, t_type_ptr source_type, + t_type_ptr sink_type, int source_x, int source_y, int start_x, + int end_x, int start_y, int end_y, struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf); + +static void compute_delta_clb_to_clb(struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf, int longest_length); + +static void compute_delta_io_to_clb(struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf); + +static void compute_delta_clb_to_io(struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf); + +static void compute_delta_io_to_io(struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf); + +static void compute_delta_arrays(struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf, int longest_length); + +static int get_first_pin(enum e_pin_type pintype, t_type_ptr type); + +static int get_longest_segment_length( + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf); +static void reset_placement(void); + +/* mrFPGA: Xifan TANG */ +void try_buffer_for_net( int inet, t_rc_node** rc_node_free_list, t_linked_rc_edge** rc_edge_free_list, t_linked_rc_ptr* rr_node_to_rc_node, float* net_delay ); + +static void buffer_net(float* cur_net_delay); +/* end */ + +#ifdef PRINT_ARRAYS +static void print_array(float **array_to_print, + int x1, + int x2, + int y1, + int y2); +#endif +/**************************************/ +static int get_first_pin(enum e_pin_type pintype, t_type_ptr type) { + + /*this code assumes logical equivilance between all driving pins */ + /*global pins are not hooked up to the temporary net */ + + int i, currpin; + + currpin = 0; + for (i = 0; i < type->num_class; i++) { + if (type->class_inf[i].type == pintype && !type->is_global_pin[currpin]) + return (type->class_inf[i].pinlist[0]); + else + currpin += type->class_inf[i].num_pins; + } + assert(0); + exit(0); /*should never hit this line */ +} + +/**************************************/ +static int get_longest_segment_length( + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf) { + + int i, length; + + length = 0; + for (i = 0; i < det_routing_arch.num_segment; i++) { + if (segment_inf[i].length > length) + length = segment_inf[i].length; + } + return (length); +} + +/**************************************/ +static void alloc_net(void) { + + int i, len; + + clb_net = (struct s_net *) my_malloc(num_nets * sizeof(struct s_net)); + for (i = 0; i < NET_COUNT; i++) { + /* FIXME: We *really* shouldn't be allocating write-once copies */ + len = strlen("TEMP_NET"); + clb_net[i].name = (char *) my_malloc((len + 1) * sizeof(char)); + clb_net[i].is_global = FALSE; + strcpy(clb_net[NET_USED].name, "TEMP_NET"); + + clb_net[i].num_sinks = (BLOCK_COUNT - 1); + clb_net[i].node_block = (int *) my_malloc(BLOCK_COUNT * sizeof(int)); + clb_net[i].node_block[NET_USED_SOURCE_BLOCK] = NET_USED_SOURCE_BLOCK; /*driving block */ + clb_net[i].node_block[NET_USED_SINK_BLOCK] = NET_USED_SINK_BLOCK; /*target block */ + + clb_net[i].node_block_pin = (int *) my_malloc( + BLOCK_COUNT * sizeof(int)); + /*the values for this are allocated in assign_blocks_and_route_net */ + + } +} + +/**************************************/ +static void alloc_block(void) { + + /*allocates block structure, and assigns values to known parameters */ + /*type and x,y fields are left undefined at this stage since they */ + /*are not known until we start moving blocks through the clb array */ + + int ix_b, ix_p, len, i; + int max_pins; + + max_pins = 0; + for (i = 0; i < NUM_TYPES_USED; i++) { + max_pins = std::max(max_pins, type_descriptors[i].num_pins); + } + + block = (struct s_block *) my_malloc(num_blocks * sizeof(struct s_block)); + + for (ix_b = 0; ix_b < BLOCK_COUNT; ix_b++) { + len = strlen("TEMP_BLOCK"); + block[ix_b].name = (char *) my_malloc((len + 1) * sizeof(char)); + strcpy(block[ix_b].name, "TEMP_BLOCK"); + + block[ix_b].nets = (int *) my_malloc(max_pins * sizeof(int)); + block[ix_b].nets[0] = 0; + for (ix_p = 1; ix_p < max_pins; ix_p++) + block[ix_b].nets[ix_p] = OPEN; + } +} + +/**************************************/ +static void load_simplified_device(void) { + int i, j; + + /* Backup original globals */ + EMPTY_TYPE_BACKUP = EMPTY_TYPE; + IO_TYPE_BACKUP = IO_TYPE; + FILL_TYPE_BACKUP = FILL_TYPE; + type_descriptors_backup = type_descriptors; + num_types_backup = num_types; + num_types = NUM_TYPES_USED; + + /* Fill in homogeneous core type info */ + dummy_type_descriptors[0] = *EMPTY_TYPE; + dummy_type_descriptors[0].index = 0; + dummy_type_descriptors[1] = *IO_TYPE; + dummy_type_descriptors[1].index = 1; + dummy_type_descriptors[2] = *FILL_TYPE; + dummy_type_descriptors[2].index = 2; + type_descriptors = dummy_type_descriptors; + EMPTY_TYPE = &dummy_type_descriptors[0]; + IO_TYPE = &dummy_type_descriptors[1]; + FILL_TYPE = &dummy_type_descriptors[2]; + + /* Fill in homogeneous core grid info */ + grid_backup = grid; + grid = (struct s_grid_tile **) alloc_matrix(0, nx + 1, 0, ny + 1, + sizeof(struct s_grid_tile)); + for (i = 0; i < nx + 2; i++) { + for (j = 0; j < ny + 2; j++) { + if ((i == 0 && j == 0) || (i == nx + 1 && j == 0) + || (i == 0 && j == ny + 1) + || (i == nx + 1 && j == ny + 1)) { + grid[i][j].type = EMPTY_TYPE; + } else if (i == 0 || i == nx + 1 || j == 0 || j == ny + 1) { + grid[i][j].type = IO_TYPE; + } else { + grid[i][j].type = FILL_TYPE; + } + grid[i][j].blocks = (int*)my_malloc( + grid[i][j].type->capacity * sizeof(int)); + grid[i][j].offset = 0; + } + } +} +static void restore_original_device(void) { + int i, j; + + /* restore previous globals */ + IO_TYPE = IO_TYPE_BACKUP; + EMPTY_TYPE = EMPTY_TYPE_BACKUP; + FILL_TYPE = FILL_TYPE_BACKUP; + type_descriptors = type_descriptors_backup; + num_types = num_types_backup; + + /* free allocatd data */ + for (i = 0; i < nx + 2; i++) { + for (j = 0; j < ny + 2; j++) { + free(grid[i][j].blocks); + } + } + free_matrix(grid, 0, nx + 1, 0, sizeof(struct s_grid_tile)); + grid = grid_backup; +} + +/**************************************/ +static void reset_placement(void) { + int i, j, k; + + for (i = 0; i <= nx + 1; i++) { + for (j = 0; j <= ny + 1; j++) { + grid[i][j].usage = 0; + for (k = 0; k < grid[i][j].type->capacity; k++) { + grid[i][j].blocks[k] = EMPTY; + } + } + } +} + +/**************************************/ +static void alloc_and_assign_internal_structures(struct s_net **original_net, + struct s_block **original_block, int *original_num_nets, + int *original_num_blocks) { + /*allocate new data structures to hold net, and block info */ + + *original_net = clb_net; + *original_num_nets = num_nets; + num_nets = NET_COUNT; + alloc_net(); + + *original_block = block; + *original_num_blocks = num_blocks; + num_blocks = BLOCK_COUNT; + alloc_block(); + + /* [0..num_nets-1][1..num_pins-1] */ + net_delay = (float **) alloc_matrix(0, NET_COUNT - 1, 1, BLOCK_COUNT - 1, + sizeof(float)); + + reset_placement(); +} + +/**************************************/ +static void free_and_reset_internal_structures(struct s_net *original_net, + struct s_block *original_block, int original_num_nets, + int original_num_blocks) { + /*reset gloabal data structures to the state that they were in before these */ + /*lookup computation routines were called */ + + int i; + + /*there should be only one net to free, but this is safer */ + for (i = 0; i < NET_COUNT; i++) { + free(clb_net[i].name); + free(clb_net[i].node_block); + free(clb_net[i].node_block_pin); + } + free(clb_net); + clb_net = original_net; + + for (i = 0; i < BLOCK_COUNT; i++) { + free(block[i].name); + free(block[i].nets); + } + free(block); + block = original_block; + + num_nets = original_num_nets; + num_blocks = original_num_blocks; + + free_matrix(net_delay, 0, NET_COUNT - 1, 1, sizeof(float)); + +} + +/**************************************/ +static void setup_chan_width(struct s_router_opts router_opts, + t_chan_width_dist chan_width_dist) { + /*we give plenty of tracks, this increases routability for the */ + /*lookup table generation */ + + int width_fac, i, max_pins_per_clb; + + max_pins_per_clb = 0; + for (i = 0; i < num_types; i++) { + max_pins_per_clb = std::max(max_pins_per_clb, type_descriptors[i].num_pins); + } + + if (router_opts.fixed_channel_width == NO_FIXED_CHANNEL_WIDTH) + width_fac = 4 * max_pins_per_clb; /*this is 2x the value that binary search starts */ + /*this should be enough to allow most pins to */ + /*connect to tracks in the architecture */ + else + width_fac = router_opts.fixed_channel_width; + + init_chan(width_fac, chan_width_dist); +} + +/**************************************/ +static void alloc_routing_structs(struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf, INP t_direct_inf *directs, + INP int num_directs) { + + int bb_factor; + int warnings; + t_graph_type graph_type; + + /*calls routines that set up routing resource graph and associated structures */ + + /*must set up dummy blocks for the first pass through to setup locally used opins */ + /* Only one block per tile */ + assign_locations(FILL_TYPE, 1, 1, 0, FILL_TYPE, nx, ny, 0); + + clb_opins_used_locally = alloc_route_structs(); + + free_rr_graph(); + + if (router_opts.route_type == GLOBAL) { + graph_type = GRAPH_GLOBAL; + } else { + graph_type = ( + det_routing_arch.directionality == BI_DIRECTIONAL ? + GRAPH_BIDIR : GRAPH_UNIDIR); + } + + build_rr_graph(graph_type, num_types, dummy_type_descriptors, nx, ny, grid, + chan_width_x[0], NULL, det_routing_arch.switch_block_type, + det_routing_arch.Fs, det_routing_arch.num_segment, + det_routing_arch.num_switch, segment_inf, + det_routing_arch.global_route_switch, + det_routing_arch.delayless_switch, timing_inf, + det_routing_arch.wire_to_ipin_switch, router_opts.base_cost_type, + NULL, 0, TRUE, /* do not send in direct connections because we care about general placement timing instead of special pin placement timing */ + &warnings, 0, NULL, FALSE, FALSE); + + alloc_and_load_rr_node_route_structs(); + + alloc_timing_driven_route_structs(&pin_criticality, &sink_order, + &rt_node_of_sink); + + bb_factor = nx + ny; /*set it to a huge value */ + init_route_structs(bb_factor); +} + +/**************************************/ +static void free_routing_structs(struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf) { + int i; + free_rr_graph(); + + free_rr_node_route_structs(); + free_route_structs(); + free_trace_structs(); + + free_timing_driven_route_structs(pin_criticality, sink_order, + rt_node_of_sink); + + if (clb_opins_used_locally != NULL) { + for (i = 0; i < num_blocks; i++) { + free_ivec_vector(clb_opins_used_locally[i], 0, + block[i].type->num_class - 1); + } + free(clb_opins_used_locally); + clb_opins_used_locally = NULL; + } +} + +/**************************************/ +static void assign_locations(t_type_ptr source_type, int source_x_loc, + int source_y_loc, int source_z_loc, t_type_ptr sink_type, + int sink_x_loc, int sink_y_loc, int sink_z_loc) { + /*all routing occurs between block 0 (source) and block 1 (sink) */ + block[SOURCE_BLOCK].type = source_type; + block[SOURCE_BLOCK].x = source_x_loc; + block[SOURCE_BLOCK].y = source_y_loc; + block[SOURCE_BLOCK].z = source_z_loc; + + block[SINK_BLOCK].type = sink_type; + block[SINK_BLOCK].x = sink_x_loc; + block[SINK_BLOCK].y = sink_y_loc; + block[SINK_BLOCK].z = sink_z_loc; + + grid[source_x_loc][source_y_loc].blocks[source_z_loc] = SOURCE_BLOCK; + grid[sink_x_loc][sink_y_loc].blocks[sink_z_loc] = SINK_BLOCK; + + clb_net[NET_USED].node_block_pin[NET_USED_SOURCE_BLOCK] = get_first_pin( + DRIVER, block[SOURCE_BLOCK].type); + clb_net[NET_USED].node_block_pin[NET_USED_SINK_BLOCK] = get_first_pin( + RECEIVER, block[SINK_BLOCK].type); + + grid[source_x_loc][source_y_loc].usage += 1; + grid[sink_x_loc][sink_y_loc].usage += 1; + +} + +/**************************************/ +static float assign_blocks_and_route_net(t_type_ptr source_type, + int source_x_loc, int source_y_loc, t_type_ptr sink_type, + int sink_x_loc, int sink_y_loc, struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf) { + /*places blocks at the specified locations, and routes a net between them */ + /*returns the delay of this net */ + + float pres_fac, net_delay_value; + + int source_z_loc, sink_z_loc; + + /* Only one block per tile */ + source_z_loc = 0; + sink_z_loc = 0; + + net_delay_value = IMPOSSIBLE; /*set to known value for debug purposes */ + + assign_locations(source_type, source_x_loc, source_y_loc, source_z_loc, + sink_type, sink_x_loc, sink_y_loc, sink_z_loc); + + load_net_rr_terminals(rr_node_indices); + + pres_fac = 0; /* ignore congestion */ + + /* Route this net with a dummy criticality of 0 by calling + timing_driven_route_net with slacks set to NULL. */ + timing_driven_route_net(NET_USED, pres_fac, + router_opts.max_criticality, router_opts.criticality_exp, + router_opts.astar_fac, router_opts.bend_cost, + pin_criticality, sink_order, rt_node_of_sink, + net_delay[NET_USED], NULL); + + /* mrFPGA */ + if (is_mrFPGA && is_wire_buffer) { + buffer_net(net_delay[NET_USED]); + } + /* end */ + + net_delay_value = net_delay[NET_USED][NET_USED_SINK_BLOCK]; + + grid[source_x_loc][source_y_loc].usage = 0; + grid[source_x_loc][source_y_loc].blocks[source_z_loc] = EMPTY; + grid[sink_x_loc][sink_y_loc].usage = 0; + grid[sink_x_loc][sink_y_loc].blocks[sink_z_loc] = EMPTY; + + return (net_delay_value); +} + +/**************************************/ +static void alloc_delta_arrays(void) { + int id_x, id_y; + + delta_clb_to_clb = (float **) alloc_matrix(0, nx - 1, 0, ny - 1, + sizeof(float)); + delta_io_to_clb = (float **) alloc_matrix(0, nx, 0, ny, sizeof(float)); + delta_clb_to_io = (float **) alloc_matrix(0, nx, 0, ny, sizeof(float)); + delta_io_to_io = (float **) alloc_matrix(0, nx + 1, 0, ny + 1, + sizeof(float)); + + /*initialize all of the array locations to -1 */ + + for (id_x = 0; id_x <= nx; id_x++) { + for (id_y = 0; id_y <= ny; id_y++) { + delta_io_to_clb[id_x][id_y] = IMPOSSIBLE; + } + } + for (id_x = 0; id_x <= nx - 1; id_x++) { + for (id_y = 0; id_y <= ny - 1; id_y++) { + delta_clb_to_clb[id_x][id_y] = IMPOSSIBLE; + } + } + for (id_x = 0; id_x <= nx; id_x++) { + for (id_y = 0; id_y <= ny; id_y++) { + delta_clb_to_io[id_x][id_y] = IMPOSSIBLE; + } + } + for (id_x = 0; id_x <= nx + 1; id_x++) { + for (id_y = 0; id_y <= ny + 1; id_y++) { + delta_io_to_io[id_x][id_y] = IMPOSSIBLE; + } + } +} + +/**************************************/ +static void free_delta_arrays(void) { + + free_matrix(delta_io_to_clb, 0, nx, 0, sizeof(float)); + free_matrix(delta_clb_to_clb, 0, nx - 1, 0, sizeof(float)); + free_matrix(delta_clb_to_io, 0, nx, 0, sizeof(float)); + free_matrix(delta_io_to_io, 0, nx + 1, 0, sizeof(float)); + +} + +/**************************************/ +static void generic_compute_matrix(float ***matrix_ptr, t_type_ptr source_type, + t_type_ptr sink_type, int source_x, int source_y, int start_x, + int end_x, int start_y, int end_y, struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf) { + + int delta_x, delta_y; + int sink_x, sink_y; + + for (sink_x = start_x; sink_x <= end_x; sink_x++) { + for (sink_y = start_y; sink_y <= end_y; sink_y++) { + delta_x = abs(sink_x - source_x); + delta_y = abs(sink_y - source_y); + + if (delta_x == 0 && delta_y == 0) + continue; /*do not compute distance from a block to itself */ + /*if a value is desired, pre-assign it somewhere else */ + + (*matrix_ptr)[delta_x][delta_y] = assign_blocks_and_route_net( + source_type, source_x, source_y, sink_type, sink_x, sink_y, + router_opts, det_routing_arch, segment_inf, timing_inf); + } + } +} + +/**************************************/ +static void compute_delta_clb_to_clb(struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf, int longest_length) { + + /*this routine must compute delay values in a slightly different way than the */ + /*other compute routines. We cannot use a location close to the edge as the */ + /*source location for the majority of the delay computations because this */ + /*would give gradually increasing delay values. To avoid this from happening */ + /*a clb that is at least longest_length away from an edge should be chosen */ + /*as a source , if longest_length is more than 0.5 of the total size then */ + /*choose a CLB at the center as the source CLB */ + + int source_x, source_y, sink_x, sink_y; + int start_x, start_y, end_x, end_y; + int delta_x, delta_y; + t_type_ptr source_type, sink_type; + + source_type = FILL_TYPE; + sink_type = FILL_TYPE; + + if (longest_length < 0.5 * (nx)) { + start_x = longest_length; + } else { + start_x = (int) (0.5 * nx); + } + end_x = nx; + source_x = start_x; + + if (longest_length < 0.5 * (ny)) { + start_y = longest_length; + } else { + start_y = (int) (0.5 * ny); + } + end_y = ny; + source_y = start_y; + + /*don't put the sink all the way to the corner, until it is necessary */ + for (sink_x = start_x; sink_x <= end_x - 1; sink_x++) { + for (sink_y = start_y; sink_y <= end_y - 1; sink_y++) { + delta_x = abs(sink_x - source_x); + delta_y = abs(sink_y - source_y); + + if (delta_x == 0 && delta_y == 0) { + delta_clb_to_clb[delta_x][delta_y] = 0.0; + continue; + } + delta_clb_to_clb[delta_x][delta_y] = assign_blocks_and_route_net( + source_type, source_x, source_y, sink_type, sink_x, sink_y, + router_opts, det_routing_arch, segment_inf, timing_inf); + } + + } + + sink_x = end_x - 1; + sink_y = end_y - 1; + + for (source_x = start_x - 1; source_x >= 1; source_x--) { + for (source_y = start_y; source_y <= end_y - 1; source_y++) { + delta_x = abs(sink_x - source_x); + delta_y = abs(sink_y - source_y); + + delta_clb_to_clb[delta_x][delta_y] = assign_blocks_and_route_net( + source_type, source_x, source_y, sink_type, sink_x, sink_y, + router_opts, det_routing_arch, segment_inf, timing_inf); + } + } + + for (source_x = 1; source_x <= end_x - 1; source_x++) { + for (source_y = 1; source_y < start_y; source_y++) { + delta_x = abs(sink_x - source_x); + delta_y = abs(sink_y - source_y); + + delta_clb_to_clb[delta_x][delta_y] = assign_blocks_and_route_net( + source_type, source_x, source_y, sink_type, sink_x, sink_y, + router_opts, det_routing_arch, segment_inf, timing_inf); + } + } + + /*now move sink into the top right corner */ + sink_x = end_x; + sink_y = end_y; + source_x = 1; + for (source_y = 1; source_y <= end_y; source_y++) { + delta_x = abs(sink_x - source_x); + delta_y = abs(sink_y - source_y); + + delta_clb_to_clb[delta_x][delta_y] = assign_blocks_and_route_net( + source_type, source_x, source_y, sink_type, sink_x, sink_y, + router_opts, det_routing_arch, segment_inf, timing_inf); + + } + + sink_x = end_x; + sink_y = end_y; + source_y = 1; + for (source_x = 1; source_x <= end_x; source_x++) { + delta_x = abs(sink_x - source_x); + delta_y = abs(sink_y - source_y); + + delta_clb_to_clb[delta_x][delta_y] = assign_blocks_and_route_net( + source_type, source_x, source_y, sink_type, sink_x, sink_y, + router_opts, det_routing_arch, segment_inf, timing_inf); + } +} + +/**************************************/ +static void compute_delta_io_to_clb(struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf) { + int source_x, source_y; + int start_x, start_y, end_x, end_y; + t_type_ptr source_type, sink_type; + + source_type = IO_TYPE; + sink_type = FILL_TYPE; + + delta_io_to_clb[0][0] = IMPOSSIBLE; + delta_io_to_clb[nx][ny] = IMPOSSIBLE; + + source_x = 0; + source_y = 1; + + start_x = 1; + end_x = nx; + start_y = 1; + end_y = ny; + generic_compute_matrix(&delta_io_to_clb, source_type, sink_type, source_x, + source_y, start_x, end_x, start_y, end_y, router_opts, + det_routing_arch, segment_inf, timing_inf); + + source_x = 1; + source_y = 0; + + start_x = 1; + end_x = 1; + start_y = 1; + end_y = ny; + generic_compute_matrix(&delta_io_to_clb, source_type, sink_type, source_x, + source_y, start_x, end_x, start_y, end_y, router_opts, + det_routing_arch, segment_inf, timing_inf); + + start_x = 1; + end_x = nx; + start_y = ny; + end_y = ny; + generic_compute_matrix(&delta_io_to_clb, source_type, sink_type, source_x, + source_y, start_x, end_x, start_y, end_y, router_opts, + det_routing_arch, segment_inf, timing_inf); +} + +/**************************************/ +static void compute_delta_clb_to_io(struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf) { + int source_x, source_y, sink_x, sink_y; + int delta_x, delta_y; + t_type_ptr source_type, sink_type; + + source_type = FILL_TYPE; + sink_type = IO_TYPE; + + delta_clb_to_io[0][0] = IMPOSSIBLE; + delta_clb_to_io[nx][ny] = IMPOSSIBLE; + + sink_x = 0; + sink_y = 1; + for (source_x = 1; source_x <= nx; source_x++) { + for (source_y = 1; source_y <= ny; source_y++) { + delta_x = abs(source_x - sink_x); + delta_y = abs(source_y - sink_y); + + delta_clb_to_io[delta_x][delta_y] = assign_blocks_and_route_net( + source_type, source_x, source_y, sink_type, sink_x, sink_y, + router_opts, det_routing_arch, segment_inf, timing_inf); + } + } + + sink_x = 1; + sink_y = 0; + source_x = 1; + delta_x = abs(source_x - sink_x); + for (source_y = 1; source_y <= ny; source_y++) { + delta_y = abs(source_y - sink_y); + delta_clb_to_io[delta_x][delta_y] = assign_blocks_and_route_net( + source_type, source_x, source_y, sink_type, sink_x, sink_y, + router_opts, det_routing_arch, segment_inf, timing_inf); + } + + sink_x = 1; + sink_y = 0; + source_y = ny; + delta_y = abs(source_y - sink_y); + for (source_x = 2; source_x <= nx; source_x++) { + delta_x = abs(source_x - sink_x); + delta_clb_to_io[delta_x][delta_y] = assign_blocks_and_route_net( + source_type, source_x, source_y, sink_type, sink_x, sink_y, + router_opts, det_routing_arch, segment_inf, timing_inf); + } +} + +/**************************************/ +static void compute_delta_io_to_io(struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf) { + int source_x, source_y, sink_x, sink_y; + int delta_x, delta_y; + t_type_ptr source_type, sink_type; + + source_type = IO_TYPE; + sink_type = IO_TYPE; + + delta_io_to_io[0][0] = 0; /*delay to itself is 0 (this can happen) */ + delta_io_to_io[nx + 1][ny + 1] = IMPOSSIBLE; + delta_io_to_io[0][ny] = IMPOSSIBLE; + delta_io_to_io[nx][0] = IMPOSSIBLE; + delta_io_to_io[nx][ny + 1] = IMPOSSIBLE; + delta_io_to_io[nx + 1][ny] = IMPOSSIBLE; + + source_x = 0; + source_y = 1; + sink_x = 0; + delta_x = abs(sink_x - source_x); + + for (sink_y = 2; sink_y <= ny; sink_y++) { + delta_y = abs(sink_y - source_y); + delta_io_to_io[delta_x][delta_y] = assign_blocks_and_route_net( + source_type, source_x, source_y, sink_type, sink_x, sink_y, + router_opts, det_routing_arch, segment_inf, timing_inf); + + } + + source_x = 0; + source_y = 1; + sink_x = nx + 1; + delta_x = abs(sink_x - source_x); + + for (sink_y = 1; sink_y <= ny; sink_y++) { + delta_y = abs(sink_y - source_y); + delta_io_to_io[delta_x][delta_y] = assign_blocks_and_route_net( + source_type, source_x, source_y, sink_type, sink_x, sink_y, + router_opts, det_routing_arch, segment_inf, timing_inf); + + } + + source_x = 1; + source_y = 0; + sink_y = 0; + delta_y = abs(sink_y - source_y); + + for (sink_x = 2; sink_x <= nx; sink_x++) { + delta_x = abs(sink_x - source_x); + delta_io_to_io[delta_x][delta_y] = assign_blocks_and_route_net( + source_type, source_x, source_y, sink_type, sink_x, sink_y, + router_opts, det_routing_arch, segment_inf, timing_inf); + + } + + source_x = 1; + source_y = 0; + sink_y = ny + 1; + delta_y = abs(sink_y - source_y); + + for (sink_x = 1; sink_x <= nx; sink_x++) { + delta_x = abs(sink_x - source_x); + delta_io_to_io[delta_x][delta_y] = assign_blocks_and_route_net( + source_type, source_x, source_y, sink_type, sink_x, sink_y, + router_opts, det_routing_arch, segment_inf, timing_inf); + + } + + source_x = 0; + sink_y = ny + 1; + for (source_y = 1; source_y <= ny; source_y++) { + for (sink_x = 1; sink_x <= nx; sink_x++) { + delta_y = abs(source_y - sink_y); + delta_x = abs(source_x - sink_x); + delta_io_to_io[delta_x][delta_y] = assign_blocks_and_route_net( + source_type, source_x, source_y, sink_type, sink_x, sink_y, + router_opts, det_routing_arch, segment_inf, timing_inf); + + } + } +} + +/**************************************/ +#ifdef PRINT_ARRAYS +static void +print_array(float **array_to_print, + int x1, + int x2, + int y1, + int y2) +{ + + int idx_x, idx_y; + + fprintf(lookup_dump, "\nPrinting Array \n\n"); + + for (idx_y = y2; idx_y >= y1; idx_y--) + { + for (idx_x = x1; idx_x <= x2; idx_x++) + { + fprintf(lookup_dump, " %9.2e", + array_to_print[idx_x][idx_y]); + } + fprintf(lookup_dump, "\n"); + } + fprintf(lookup_dump, "\n\n"); +} +#endif +/**************************************/ +static void compute_delta_arrays(struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf, int longest_length) { + + vpr_printf(TIO_MESSAGE_INFO, "Computing delta_io_to_io lookup matrix, may take a few seconds, please wait...\n"); + compute_delta_io_to_io(router_opts, det_routing_arch, segment_inf, timing_inf); + vpr_printf(TIO_MESSAGE_INFO, "Computing delta_io_to_clb lookup matrix, may take a few seconds, please wait...\n"); + compute_delta_io_to_clb(router_opts, det_routing_arch, segment_inf, timing_inf); + vpr_printf(TIO_MESSAGE_INFO, "Computing delta_clb_to_io lookup matrix, may take a few seconds, please wait...\n"); + compute_delta_clb_to_io(router_opts, det_routing_arch, segment_inf, timing_inf); + vpr_printf(TIO_MESSAGE_INFO, "Computing delta_clb_to_clb lookup matrix, may take a few seconds, please wait...\n"); + compute_delta_clb_to_clb(router_opts, det_routing_arch, segment_inf, timing_inf, longest_length); + +#ifdef PRINT_ARRAYS + lookup_dump = my_fopen(DUMPFILE, "w", 0); + fprintf(lookup_dump, "\n\nprinting delta_clb_to_clb\n"); + print_array(delta_clb_to_clb, 0, nx - 1, 0, ny - 1); + fprintf(lookup_dump, "\n\nprinting delta_io_to_clb\n"); + print_array(delta_io_to_clb, 0, nx, 0, ny); + fprintf(lookup_dump, "\n\nprinting delta_clb_to_io\n"); + print_array(delta_clb_to_io, 0, nx, 0, ny); + fprintf(lookup_dump, "\n\nprinting delta_io_to_io\n"); + print_array(delta_io_to_io, 0, nx + 1, 0, ny + 1); + fclose(lookup_dump); +#endif + +} + +/******* Globally Accessable Functions **********/ + +/**************************************/ +void compute_delay_lookup_tables(struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf, t_chan_width_dist chan_width_dist, INP t_direct_inf *directs, + INP int num_directs) { + + static struct s_net *original_net; /*this will be used as a pointer to remember what */ + + /*the "real" nets in the circuit are. This is */ + /*required because we are using the net structure */ + /*in these routines to find delays between blocks */ + static struct s_block *original_block; /*same def as original_nets, but for block */ + + static int original_num_nets; + static int original_num_blocks; + static int longest_length; + + load_simplified_device(); + + alloc_and_assign_internal_structures(&original_net, &original_block, + &original_num_nets, &original_num_blocks); + setup_chan_width(router_opts, chan_width_dist); + + alloc_routing_structs(router_opts, det_routing_arch, segment_inf, + timing_inf, directs, num_directs); + + longest_length = get_longest_segment_length(det_routing_arch, segment_inf); + + /*now setup and compute the actual arrays */ + alloc_delta_arrays(); + compute_delta_arrays(router_opts, det_routing_arch, segment_inf, timing_inf, + longest_length); + + /*free all data structures that are no longer needed */ + free_routing_structs(router_opts, det_routing_arch, segment_inf, + timing_inf); + + restore_original_device(); + + free_and_reset_internal_structures(original_net, original_block, + original_num_nets, original_num_blocks); +} + +/**************************************/ +void free_place_lookup_structs(void) { + + free_delta_arrays(); + +} + +/* mrFPGA */ +static void buffer_net( float* cur_net_delay ) +{ + t_rc_node *rc_node_free_list; + t_linked_rc_edge *rc_edge_free_list; + //int inet; + t_linked_rc_ptr *rr_node_to_rc_node; /* [0..num_rr_nodes-1] */ + + vpr_printf(TIO_MESSAGE_INFO, "mrFPGA: net delay before buffer: %g\n", cur_net_delay[NET_USED_SINK_BLOCK] ); + rr_node_to_rc_node = (t_linked_rc_ptr *) my_calloc (num_rr_nodes, + sizeof (t_linked_rc_ptr)); + + rc_node_free_list = NULL; + rc_edge_free_list = NULL; + try_buffer_for_net( NET_USED, &rc_node_free_list, &rc_edge_free_list, rr_node_to_rc_node, cur_net_delay ); + free_rc_node_free_list (rc_node_free_list); + free_rc_edge_free_list (rc_edge_free_list); + free (rr_node_to_rc_node); + vpr_printf(TIO_MESSAGE_INFO, "mrFPGA: net delay after buffer: %g\n", cur_net_delay[NET_USED_SINK_BLOCK] ); +} +/* end */ diff --git a/vpr7_rram/vpr/SRC/place/timing_place_lookup.h b/vpr7_rram/vpr/SRC/place/timing_place_lookup.h new file mode 100755 index 000000000..fd2406233 --- /dev/null +++ b/vpr7_rram/vpr/SRC/place/timing_place_lookup.h @@ -0,0 +1,13 @@ +#define IMPOSSIBLE -1 /*indicator of an array location that */ +/*should never be accessed */ + +void compute_delay_lookup_tables(struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf, t_chan_width_dist chan_width_dist, INP t_direct_inf *directs, + INP int num_directs); +void free_place_lookup_structs(void); + +extern float **delta_io_to_clb; +extern float **delta_clb_to_clb; +extern float **delta_clb_to_io; +extern float **delta_io_to_io; diff --git a/vpr7_rram/vpr/SRC/power/PowerSpicedComponent.c b/vpr7_rram/vpr/SRC/power/PowerSpicedComponent.c new file mode 100644 index 000000000..cc8acc8e1 --- /dev/null +++ b/vpr7_rram/vpr/SRC/power/PowerSpicedComponent.c @@ -0,0 +1,230 @@ +/************************* INCLUDES *********************************/ +#include +#include +#include +#include + +using namespace std; + +#include + +#include "util.h" +#include "PowerSpicedComponent.h" + +PowerCallibInputs::PowerCallibInputs(PowerSpicedComponent * parent_, + float inputs) : + parent(parent_), num_inputs(inputs), sorted(false), done_callibration( + false) { + + /* Add min/max bounding entries */ + add_size(0); + add_size(std::numeric_limits::max()); +} + +void PowerCallibInputs::add_size(float transistor_size, float power) { + PowerCallibSize * entry = new PowerCallibSize(transistor_size, power); + entries.push_back(entry); + sorted = false; +} + +bool sorter_PowerCallibSize(PowerCallibSize * a, PowerCallibSize * b) { + return a->transistor_size < b->transistor_size; +} + +void PowerCallibInputs::sort_me() { + sort(entries.begin(), entries.end(), sorter_PowerCallibSize); + sorted = true; +} + +void PowerCallibInputs::callibrate() { + assert(entries.size() >= 2); + + for (vector::iterator it = entries.begin() + 1; + it != entries.end() - 1; it++) { + float est_power = parent->component_usage(num_inputs, + (*it)->transistor_size); + (*it)->factor = (*it)->power / est_power; + } + + /* Set min-value placeholder */ + entries[0]->factor = entries[1]->factor; + + /* Set max-value placeholder */ + entries[entries.size() - 1]->factor = entries[entries.size() - 2]->factor; + + done_callibration = true; +} + +PowerCallibSize * PowerCallibInputs::get_entry_bound(bool lower, + float transistor_size) { + PowerCallibSize * prev = entries[0]; + + assert(sorted); + for (vector::iterator it = entries.begin() + 1; + it != entries.end(); it++) { + if ((*it)->transistor_size > transistor_size) { + if (lower) + return prev; + else + return *it; + } + prev = *it; + } + return NULL; +} + +PowerSpicedComponent::PowerSpicedComponent( + float (*usage_fn)(int num_inputs, float transistor_size)) { + component_usage = usage_fn; + + /* Always pad with a high and low entry */ + add_entry(0); +// add_entry(std::numeric_limits::max()); + add_entry(1000000000); + + done_callibration = false; + sorted = true; +} + +PowerCallibInputs * PowerSpicedComponent::add_entry(int num_inputs) { + PowerCallibInputs * entry = new PowerCallibInputs(this, num_inputs); + entries.push_back(entry); + return entry; +} + +PowerCallibInputs * PowerSpicedComponent::get_entry(int num_inputs) { + vector::iterator it; + + for (it = entries.begin(); it != entries.end(); it++) { + if ((*it)->num_inputs == num_inputs) { + break; + } + } + + if (it == entries.end()) { + return add_entry(num_inputs); + } else { + return *it; + } +} + +PowerCallibInputs * PowerSpicedComponent::get_entry_bound(bool lower, + int num_inputs) { + PowerCallibInputs * prev = entries[0]; + + assert(sorted); + for (vector::iterator it = entries.begin() + 1; + it != entries.end(); it++) { + if ((*it)->num_inputs > num_inputs) { + if (lower) { + if (prev == entries[0]) + return NULL; + else + return prev; + } else { + if (*it == entries[entries.size() - 1]) + return NULL; + else + return *it; + } + } + prev = *it; + } + return NULL; +} + +void PowerSpicedComponent::add_data_point(int num_inputs, float transistor_size, + float power) { + assert(!done_callibration); + PowerCallibInputs * inputs_entry = get_entry(num_inputs); + inputs_entry->add_size(transistor_size, power); + sorted = false; +} + +float PowerSpicedComponent::scale_factor(int num_inputs, + float transistor_size) { + + PowerCallibInputs * inputs_lower; + PowerCallibInputs * inputs_upper; + + PowerCallibSize * size_lower; + PowerCallibSize * size_upper; + + float factor_lower = 0.; + float factor_upper = 0.; + float factor; + + float perc_upper; + + assert(done_callibration); + + inputs_lower = get_entry_bound(true, num_inputs); + inputs_upper = get_entry_bound(false, num_inputs); + + if (inputs_lower) { + /* Interpolation of factor between sizes for lower # inputs */ + assert(inputs_lower->done_callibration); + size_lower = inputs_lower->get_entry_bound(true, transistor_size); + size_upper = inputs_lower->get_entry_bound(false, transistor_size); + + perc_upper = (transistor_size - size_lower->transistor_size) + / (size_upper->transistor_size - size_lower->transistor_size); + factor_lower = perc_upper * size_upper->factor + + (1 - perc_upper) * size_lower->factor; + } + + if (inputs_upper) { + /* Interpolation of factor between sizes for upper # inputs */ + assert(inputs_upper->done_callibration); + size_lower = inputs_upper->get_entry_bound(true, transistor_size); + size_upper = inputs_upper->get_entry_bound(false, transistor_size); + + perc_upper = (transistor_size - size_lower->transistor_size) + / (size_upper->transistor_size - size_lower->transistor_size); + factor_upper = perc_upper * size_upper->factor + + (1 - perc_upper) * size_lower->factor; + } + + if (!inputs_lower) { + factor = factor_upper; + } else if (!inputs_upper) { + factor = factor_lower; + } else { + /* Interpolation of factor between inputs */ + perc_upper = + ((float) (num_inputs - inputs_lower->num_inputs)) + / ((float) (inputs_upper->num_inputs + - inputs_lower->num_inputs)); + factor = perc_upper * factor_upper + (1 - perc_upper) * factor_lower; + } + return factor; + +} + +bool sorter_PowerCallibInputs(PowerCallibInputs * a, PowerCallibInputs * b) { + return a->num_inputs < b->num_inputs; +} + +void PowerSpicedComponent::sort_me(void) { + sort(entries.begin(), entries.end(), sorter_PowerCallibInputs); + + for (vector::iterator it = entries.begin(); + it != entries.end(); it++) { + (*it)->sort_me(); + } + sorted = true; +} + +void PowerSpicedComponent::callibrate(void) { + sort_me(); + + for (vector::iterator it = entries.begin(); + it != entries.end(); it++) { + (*it)->callibrate(); + } + done_callibration = true; +} + +bool PowerSpicedComponent::is_done_callibration(void) { + return done_callibration; +} diff --git a/vpr7_rram/vpr/SRC/power/PowerSpicedComponent.h b/vpr7_rram/vpr/SRC/power/PowerSpicedComponent.h new file mode 100644 index 000000000..45c4c6516 --- /dev/null +++ b/vpr7_rram/vpr/SRC/power/PowerSpicedComponent.h @@ -0,0 +1,82 @@ +/********************************************************************* + * The following code is part of the power modelling feature of VTR. + * + * For support: + * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power + * + * or email: + * vtr.power.estimation@gmail.com + * + * If you are using power estimation for your researach please cite: + * + * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation + * for Diverse FPGA Architectures. In International Conference on + * Field Programmable Technology, 2012. + * + ********************************************************************/ + +#ifndef __POWER_POWERSPICEDCOMPONENT_NMOS_H__ +#define __POWER_POWERSPICEDCOMPONENT_NMOS_H__ + +#include + +/************************* STRUCTS **********************************/ +class PowerSpicedComponent; + +class PowerCallibSize { +public: + float transistor_size; + float power; + float factor; + + PowerCallibSize(float size, float power_) : + transistor_size(size), power(power_), factor(0.) { + } + const bool operator<(const PowerCallibSize & rhs) { + return transistor_size < rhs.transistor_size; + } +}; + +class PowerCallibInputs { +public: + PowerSpicedComponent * parent; + int num_inputs; + std::vector entries; + bool sorted; + + PowerCallibInputs(PowerSpicedComponent * parent, float num_inputs); + + void add_size(float transistor_size, float power = 0.); + PowerCallibSize * get_entry_bound(bool lower, float transistor_size); + void sort_me(); + bool done_callibration; + void callibrate(); +}; + +class PowerSpicedComponent { +public: + std::vector entries; + + /* Estimation function for this component */ + float (*component_usage)(int num_inputs, float transistor_size); + + bool sorted; + bool done_callibration; + + PowerCallibInputs * add_entry(int num_inputs); + PowerCallibInputs* get_entry(int num_inputs); + PowerCallibInputs * get_entry_bound(bool lower, int num_inputs); + + PowerSpicedComponent( + float (*usage_fn)(int num_inputs, float transistor_size)); + + void add_data_point(int num_inputs, float transistor_size, float power); + float scale_factor(int num_inputs, float transistor_size); + void sort_me(); + +// void update_scale_factor(float (*fn)(float size)); + void callibrate(void); + bool is_done_callibration(void); +}; + +#endif diff --git a/vpr7_rram/vpr/SRC/power/power.c b/vpr7_rram/vpr/SRC/power/power.c new file mode 100644 index 000000000..420b7e655 --- /dev/null +++ b/vpr7_rram/vpr/SRC/power/power.c @@ -0,0 +1,1918 @@ +/********************************************************************* + * The following code is part of the power modelling feature of VTR. + * + * For support: + * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power + * + * or email: + * vtr.power.estimation@gmail.com + * + * If you are using power estimation for your researach please cite: + * + * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation + * for Diverse FPGA Architectures. In International Conference on + * Field Programmable Technology, 2012. + * + ********************************************************************/ + +/** + * This is the top-level file for power estimation in VTR + */ + +/************************* INCLUDES *********************************/ +#include +#include +#include +#include +#include +#include +using namespace std; + +#include +#include + +#include "power.h" +#include "power_components.h" +#include "power_util.h" +#include "power_lowlevel.h" +#include "power_sizing.h" +#include "power_callibrate.h" +#include "power_cmos_tech.h" + +#include "physical_types.h" +#include "globals.h" +#include "rr_graph.h" +#include "vpr_utils.h" +#include "ezxml.h" +#include "read_xml_util.h" + +/************************* DEFINES **********************************/ +#define CONVERT_NM_PER_M 1000000000 +#define CONVERT_UM_PER_M 1000000 + +/************************* ENUMS ************************************/ +typedef enum { + POWER_BREAKDOWN_ENTRY_TYPE_TITLE = 0, + POWER_BREAKDOWN_ENTRY_TYPE_MODE, + POWER_BREAKDOWN_ENTRY_TYPE_COMPONENT, + POWER_BREAKDOWN_ENTRY_TYPE_PB, + POWER_BREAKDOWN_ENTRY_TYPE_INTERC, + POWER_BREAKDOWN_ENTRY_TYPE_BUFS_WIRES +} e_power_breakdown_entry_type; + +/************************* GLOBALS **********************************/ +t_solution_inf g_solution_inf; +t_power_output * g_power_output; +t_power_commonly_used * g_power_commonly_used; +t_power_tech * g_power_tech; +t_power_arch * g_power_arch; +static t_rr_node_power * rr_node_power; + +/************************* Function Declarations ********************/ +/* Routing */ +static void power_usage_routing(t_power_usage * power_usage, + t_det_routing_arch * routing_arch, t_segment_inf * segment_inf); + +/* Tiles */ +static void power_usage_blocks(t_power_usage * power_usage); +static void power_usage_pb(t_power_usage * power_usage, t_pb * pb, + t_pb_graph_node * pb_node); +static void power_usage_primitive(t_power_usage * power_usage, t_pb * pb, + t_pb_graph_node * pb_graph_node); +static void power_reset_tile_usage(void); +static void power_reset_pb_type(t_pb_type * pb_type); +static void power_usage_local_buffers_and_wires(t_power_usage * power_usage, + t_pb * pb, t_pb_graph_node * pb_node); + +/* Clock */ +static void power_usage_clock(t_power_usage * power_usage, + t_clock_arch * clock_arch); +static void power_usage_clock_single(t_power_usage * power_usage, + t_clock_network * clock_inf); + +/* Init/Uninit */ +static void dealloc_mux_graph(t_mux_node * node); +static void dealloc_mux_graph_rec(t_mux_node * node); + +/* Printing */ +static void power_print_breakdown_pb_rec(FILE * fp, t_pb_type * pb_type, + int indent); +static void power_print_summary(FILE * fp, t_vpr_setup vpr_setup); +//static void power_print_stats(FILE * fp); +static void power_print_breakdown_summary(FILE * fp); +static void power_print_breakdown_entry(FILE * fp, int indent, + e_power_breakdown_entry_type type, char * name, float power, + float total_power, float perc_dyn, char * method); +static void power_print_breakdown_component(FILE * fp, char * name, + e_power_component_type type, int indent_level); +static void power_print_breakdown_pb(FILE * fp); + +static char * power_estimation_method_name( + e_power_estimation_method power_method); + +/************************* FUNCTION DEFINITIONS *********************/ +/** + * This function calculates the power of primitives (ff, lut, etc), + * by calling the appropriate primitive function. + * - power_usage: (Return value) + * - pb: The pysical block + * - pb_graph_node: The physical block graph node + * - calc_dynamic: Calculate dynamic power? Otherwise ignore + * - calc_static: Calculate static power? Otherwise ignore + */ +static void power_usage_primitive(t_power_usage * power_usage, t_pb * pb, + t_pb_graph_node * pb_graph_node) { + t_power_usage sub_power_usage; + + power_zero_usage(power_usage); + power_zero_usage(&sub_power_usage); + + if (strcmp(pb_graph_node->pb_type->blif_model, ".names") == 0) { + /* LUT */ + + char * SRAM_values; + float * input_probabilities; + float * input_densities; + int LUT_size; + int pin_idx; + + assert(pb_graph_node->num_input_ports == 1); + + LUT_size = pb_graph_node->num_input_pins[0]; + + input_probabilities = (float*) my_calloc(LUT_size, sizeof(float)); + input_densities = (float*) my_calloc(LUT_size, sizeof(float)); + + for (pin_idx = 0; pin_idx < LUT_size; pin_idx++) { + t_pb_graph_pin * pin = &pb_graph_node->input_pins[0][pin_idx]; + + input_probabilities[pin_idx] = pin_prob(pb, pin); + input_densities[pin_idx] = pin_dens(pb, pin); + } + + if (pb) { + SRAM_values = alloc_SRAM_values_from_truth_table(LUT_size, + logical_block[pb->logical_block].truth_table); + } else { + SRAM_values = alloc_SRAM_values_from_truth_table(LUT_size, NULL); + } + power_usage_lut(&sub_power_usage, LUT_size, + g_power_arch->LUT_transistor_size, SRAM_values, + input_probabilities, input_densities, g_solution_inf.T_crit); + power_add_usage(power_usage, &sub_power_usage); + free(SRAM_values); + free(input_probabilities); + free(input_densities); + } else if (strcmp(pb_graph_node->pb_type->blif_model, ".latch") == 0) { + /* Flip-Flop */ + + t_pb_graph_pin * D_pin = &pb_graph_node->input_pins[0][0]; + t_pb_graph_pin * Q_pin = &pb_graph_node->output_pins[0][0]; + + float D_dens = 0.; + float D_prob = 0.; + float Q_prob = 0.; + float Q_dens = 0.; + float clk_dens = 0.; + float clk_prob = 0.; + + D_dens = pin_dens(pb, D_pin); + D_prob = pin_prob(pb, D_pin); + Q_dens = pin_dens(pb, Q_pin); + Q_prob = pin_prob(pb, Q_pin); + + clk_prob = g_clock_arch->clock_inf[0].prob; + clk_dens = g_clock_arch->clock_inf[0].dens; + + power_usage_ff(&sub_power_usage, g_power_arch->FF_size, D_prob, D_dens, + Q_prob, Q_dens, clk_prob, clk_dens, g_solution_inf.T_crit); + power_add_usage(power_usage, &sub_power_usage); + + } else { + char msg[BUFSIZE]; + sprintf(msg, "No dynamic power defined for BLIF model: %s", + pb_graph_node->pb_type->blif_model); + power_log_msg(POWER_LOG_WARNING, msg); + + sprintf(msg, "No leakage power defined for BLIF model: %s", + pb_graph_node->pb_type->blif_model); + power_log_msg(POWER_LOG_WARNING, msg); + + } +} + +void power_usage_local_pin_toggle(t_power_usage * power_usage, t_pb * pb, + t_pb_graph_pin * pin) { + float scale_factor; + + power_zero_usage(power_usage); + + if (pin->pin_power->scaled_by_pin) { + scale_factor = pin_prob(pb, pin->pin_power->scaled_by_pin); + if (pin->port->port_power->reverse_scaled) { + scale_factor = 1 - scale_factor; + } + } else { + scale_factor = 1.0; + } + + /* Divide by 2 because density is switches/cycle, but a toggle is 2 switches */ + power_usage->dynamic += scale_factor + * pin->port->port_power->energy_per_toggle * pin_dens(pb, pin) / 2.0 + / g_solution_inf.T_crit; +} + +void power_usage_local_pin_buffer_and_wire(t_power_usage * power_usage, + t_pb * pb, t_pb_graph_pin * pin) { + t_power_usage sub_power_usage; + float buffer_size = 0.; + double C_wire; + + power_zero_usage(power_usage); + + /* Wire switching */ + C_wire = pin->pin_power->C_wire; + power_usage_wire(&sub_power_usage, C_wire, pin_dens(pb, pin), + g_solution_inf.T_crit); + power_add_usage(power_usage, &sub_power_usage); + + /* Buffer power */ + buffer_size = pin->pin_power->buffer_size; + if (buffer_size) { + power_usage_buffer(&sub_power_usage, buffer_size, pin_prob(pb, pin), + pin_dens(pb, pin), FALSE, g_solution_inf.T_crit); + power_add_usage(power_usage, &sub_power_usage); + } +} + +static void power_usage_local_buffers_and_wires(t_power_usage * power_usage, + t_pb * pb, t_pb_graph_node * pb_node) { + int port_idx; + int pin_idx; + t_power_usage pin_power; + + power_zero_usage(power_usage); + + /* Input pins */ + for (port_idx = 0; port_idx < pb_node->num_input_ports; port_idx++) { + for (pin_idx = 0; pin_idx < pb_node->num_input_pins[port_idx]; + pin_idx++) { + power_usage_local_pin_buffer_and_wire(&pin_power, pb, + &pb_node->input_pins[port_idx][pin_idx]); + power_add_usage(power_usage, &pin_power); + } + } + + /* Output pins */ + for (port_idx = 0; port_idx < pb_node->num_output_ports; port_idx++) { + for (pin_idx = 0; pin_idx < pb_node->num_output_pins[port_idx]; + pin_idx++) { + power_usage_local_pin_buffer_and_wire(&pin_power, pb, + &pb_node->output_pins[port_idx][pin_idx]); + power_add_usage(power_usage, &pin_power); + } + } + + /* Clock pins */ + for (port_idx = 0; port_idx < pb_node->num_clock_ports; port_idx++) { + for (pin_idx = 0; pin_idx < pb_node->num_clock_pins[port_idx]; + pin_idx++) { + power_usage_local_pin_buffer_and_wire(&pin_power, pb, + &pb_node->clock_pins[port_idx][pin_idx]); + power_add_usage(power_usage, &pin_power); + } + } +} + +/** Calculates the power of a pb: + * First checks if dynamic/static power is provided by user in arch file. If not: + * - Calculate power of all interconnect + * - Call recursively for children + * - If no children, must be a primitive. Call primitive hander. + */ +static void power_usage_pb(t_power_usage * power_usage, t_pb * pb, + t_pb_graph_node * pb_node) { + + t_power_usage power_usage_bufs_wires; + t_power_usage power_usage_local_muxes; + t_power_usage power_usage_children; + t_power_usage power_usage_pin_toggle; + t_power_usage power_usage_sub; + + int pb_type_idx; + int pb_idx; + int interc_idx; + int pb_mode; + int port_idx; + int pin_idx; + float dens_avg; + int num_pins; + + power_zero_usage(power_usage); + + t_pb_type * pb_type = pb_node->pb_type; + t_pb_type_power * pb_power = pb_node->pb_type->pb_type_power; + + boolean estimate_buffers_and_wire = FALSE; + boolean estimate_multiplexers = FALSE; + boolean estimate_primitives = FALSE; + boolean recursive_children; + + /* Get mode */ + if (pb) { + pb_mode = pb->mode; + } else { + /* Default mode if not initialized (will only affect leakage power) */ + pb_mode = pb_type->pb_type_power->leakage_default_mode; + } + + recursive_children = power_method_is_recursive( + pb_node->pb_type->pb_type_power->estimation_method); + + power_zero_usage(&power_usage_sub); + + switch (pb_node->pb_type->pb_type_power->estimation_method) { + case POWER_METHOD_IGNORE: + case POWER_METHOD_SUM_OF_CHILDREN: + break; + + case POWER_METHOD_ABSOLUTE: + power_add_usage(power_usage, &pb_power->absolute_power_per_instance); + power_component_add_usage(&pb_power->absolute_power_per_instance, + POWER_COMPONENT_PB_OTHER); + break; + + case POWER_METHOD_C_INTERNAL: + power_zero_usage(&power_usage_sub); + + /* Just take the average density of inputs pins and use + * that with user-defined block capacitance and leakage */ + + /* Average the activity of all pins */ + num_pins = 0; + dens_avg = 0.; + for (port_idx = 0; port_idx < pb_node->num_input_ports; port_idx++) { + for (pin_idx = 0; pin_idx < pb_node->num_input_pins[port_idx]; + pin_idx++) { + dens_avg += pin_dens(pb, + &pb_node->input_pins[port_idx][pin_idx]); + num_pins++; + } + } + if (num_pins != 0) { + dens_avg = dens_avg / num_pins; + } + power_usage_sub.dynamic += power_calc_node_switching( + pb_power->C_internal, dens_avg, g_solution_inf.T_crit); + + /* Leakage is an absolute */ + power_usage_sub.leakage += + pb_power->absolute_power_per_instance.leakage; + + /* Add to power of this PB */ + power_add_usage(power_usage, &power_usage_sub); + + // Add to component type + power_component_add_usage(&power_usage_sub, POWER_COMPONENT_PB_OTHER); + break; + + case POWER_METHOD_TOGGLE_PINS: + power_zero_usage(&power_usage_pin_toggle); + + /* Add toggle power of each input pin */ + for (port_idx = 0; port_idx < pb_node->num_input_ports; port_idx++) { + for (pin_idx = 0; pin_idx < pb_node->num_input_pins[port_idx]; + pin_idx++) { + t_power_usage pin_power; + power_usage_local_pin_toggle(&pin_power, pb, + &pb_node->input_pins[port_idx][pin_idx]); + power_add_usage(&power_usage_pin_toggle, &pin_power); + } + } + + /* Add toggle power of each output pin */ + for (port_idx = 0; port_idx < pb_node->num_output_ports; port_idx++) { + for (pin_idx = 0; pin_idx < pb_node->num_output_pins[port_idx]; + pin_idx++) { + t_power_usage pin_power; + power_usage_local_pin_toggle(&pin_power, pb, + &pb_node->output_pins[port_idx][pin_idx]); + power_add_usage(&power_usage_pin_toggle, &pin_power); + } + } + + /* Add toggle power of each clock pin */ + for (port_idx = 0; port_idx < pb_node->num_clock_ports; port_idx++) { + for (pin_idx = 0; pin_idx < pb_node->num_clock_pins[port_idx]; + pin_idx++) { + t_power_usage pin_power; + power_usage_local_pin_toggle(&pin_power, pb, + &pb_node->clock_pins[port_idx][pin_idx]); + power_add_usage(&power_usage_pin_toggle, &pin_power); + } + } + + /* Static is supplied as an absolute */ + power_usage_pin_toggle.leakage += + pb_power->absolute_power_per_instance.leakage; + + // Add to this PB power + power_add_usage(power_usage, &power_usage_pin_toggle); + + // Add to component type power + power_component_add_usage(&power_usage_pin_toggle, + POWER_COMPONENT_PB_OTHER); + break; + case POWER_METHOD_SPECIFY_SIZES: + estimate_buffers_and_wire = TRUE; + estimate_multiplexers = TRUE; + estimate_primitives = TRUE; + break; + case POWER_METHOD_AUTO_SIZES: + estimate_buffers_and_wire = TRUE; + estimate_multiplexers = TRUE; + estimate_primitives = TRUE; + break; + case POWER_METHOD_UNDEFINED: + default: + assert(0); + break; + } + + if (pb_node->pb_type->class_type == LUT_CLASS) { + /* LUTs will have a child node that is used to indicate pin + * equivalence for routing purposes. + * There is a crossbar to the child node; however, + * this interconnect does not exist in FPGA hardware and should + * be ignored for power calculations. */ + estimate_buffers_and_wire = FALSE; + estimate_multiplexers = FALSE; + } + + if (pb_node->pb_type->num_modes == 0) { + /* This is a leaf node, which is a primitive (lut, ff, etc) */ + if (estimate_primitives) { + assert(pb_node->pb_type->blif_model); + power_usage_primitive(&power_usage_sub, pb, pb_node); + + // Add to power of this PB + power_add_usage(power_usage, &power_usage_sub); + + // Add to power of component type + power_component_add_usage(&power_usage_sub, + POWER_COMPONENT_PB_PRIMITIVES); + + } + + } else { + /* This node had children. The power of this node is the sum of: + * - Buffers/Wires in Interconnect from Parent to children + * - Multiplexers in Interconnect from Parent to children + * - Child nodes + */ + + if (estimate_buffers_and_wire) { + /* Check pins of all interconnect */ + power_usage_local_buffers_and_wires(&power_usage_bufs_wires, pb, + pb_node); + power_component_add_usage(&power_usage_bufs_wires, + POWER_COMPONENT_PB_BUFS_WIRE); + power_add_usage( + &pb_node->pb_type->pb_type_power->power_usage_bufs_wires, + &power_usage_bufs_wires); + power_add_usage(power_usage, &power_usage_bufs_wires); + } + + /* Interconnect Structures (multiplexers) */ + if (estimate_multiplexers) { + power_zero_usage(&power_usage_local_muxes); + for (interc_idx = 0; + interc_idx < pb_type->modes[pb_mode].num_interconnect; + interc_idx++) { + power_usage_local_interc_mux(&power_usage_sub, pb, + &pb_node->interconnect_pins[pb_mode][interc_idx]); + power_add_usage(&power_usage_local_muxes, &power_usage_sub); + + } + // Add to power of this PB + power_add_usage(power_usage, &power_usage_local_muxes); + + // Add to component type power + power_component_add_usage(&power_usage_local_muxes, + POWER_COMPONENT_PB_INTERC_MUXES); + + // Add to power of this mode + power_add_usage( + &pb_node->pb_type->modes[pb_mode].mode_power->power_usage, + &power_usage_local_muxes); + } + + /* Add power for children */ + if (recursive_children) { + power_zero_usage(&power_usage_children); + for (pb_type_idx = 0; + pb_type_idx + < pb_node->pb_type->modes[pb_mode].num_pb_type_children; + pb_type_idx++) { + for (pb_idx = 0; + pb_idx + < pb_node->pb_type->modes[pb_mode].pb_type_children[pb_type_idx].num_pb; + pb_idx++) { + t_pb * child_pb = NULL; + t_pb_graph_node * child_pb_graph_node; + + if (pb && pb->child_pbs[pb_type_idx][pb_idx].name) { + /* Child is initialized */ + child_pb = &pb->child_pbs[pb_type_idx][pb_idx]; + } + child_pb_graph_node = + &pb_node->child_pb_graph_nodes[pb_mode][pb_type_idx][pb_idx]; + + power_usage_pb(&power_usage_sub, child_pb, + child_pb_graph_node); + power_add_usage(&power_usage_children, &power_usage_sub); + } + } + // Add to power of this PB + power_add_usage(power_usage, &power_usage_children); + + // Add to power of this mode + power_add_usage( + &pb_node->pb_type->modes[pb_mode].mode_power->power_usage, + &power_usage_children); + } + } + + power_add_usage(&pb_node->pb_type->pb_type_power->power_usage, power_usage); +} + +/* Resets the power stats for all physical blocks */ +static void power_reset_pb_type(t_pb_type * pb_type) { + int mode_idx; + int child_idx; + int interc_idx; + + power_zero_usage(&pb_type->pb_type_power->power_usage); + power_zero_usage(&pb_type->pb_type_power->power_usage_bufs_wires); + + for (mode_idx = 0; mode_idx < pb_type->num_modes; mode_idx++) { + power_zero_usage(&pb_type->modes[mode_idx].mode_power->power_usage); + + for (child_idx = 0; + child_idx < pb_type->modes[mode_idx].num_pb_type_children; + child_idx++) { + power_reset_pb_type( + &pb_type->modes[mode_idx].pb_type_children[child_idx]); + } + for (interc_idx = 0; + interc_idx < pb_type->modes[mode_idx].num_interconnect; + interc_idx++) { + power_zero_usage( + &pb_type->modes[mode_idx].interconnect[interc_idx].interconnect_power->power_usage); + } + } +} + +/** + * Resets the power usage for all tile types + */ +static void power_reset_tile_usage(void) { + int type_idx; + + for (type_idx = 0; type_idx < num_types; type_idx++) { + if (type_descriptors[type_idx].pb_type) { + power_reset_pb_type(type_descriptors[type_idx].pb_type); + } + } +} + +/* + * Calcultes the power usage of all tiles in the FPGA + */ +static void power_usage_blocks(t_power_usage * power_usage) { + int x, y, z; + + power_zero_usage(power_usage); + + power_reset_tile_usage(); + + /* Loop through all grid locations */ + for (x = 0; x < nx + 2; x++) { + for (y = 0; y < ny + 2; y++) { + + if ((grid[x][y].offset != 0) || (grid[x][y].type == EMPTY_TYPE)) { + continue; + } + + for (z = 0; z < grid[x][y].type->capacity; z++) { + t_pb * pb = NULL; + t_power_usage pb_power; + + if (grid[x][y].blocks[z] != OPEN) { + pb = block[grid[x][y].blocks[z]].pb; + } + + /* Calculate power of this CLB */ + power_usage_pb(&pb_power, pb, grid[x][y].type->pb_graph_head); + power_add_usage(power_usage, &pb_power); + } + } + } + return; +} + +/** + * Calculates the total power usage from the clock network + */ +static void power_usage_clock(t_power_usage * power_usage, + t_clock_arch * clock_arch) { + int clock_idx; + + /* Initialization */ + power_usage->dynamic = 0.; + power_usage->leakage = 0.; + + /* if no global clock, then return */ + if (clock_arch->num_global_clocks == 0) { + return; + } + + for (clock_idx = 0; clock_idx < clock_arch->num_global_clocks; + clock_idx++) { + t_power_usage clock_power; + + /* Assume the global clock is active even for combinational circuits */ + if (clock_arch->num_global_clocks == 1) { + if (clock_arch->clock_inf[clock_idx].dens == 0) { + clock_arch->clock_inf[clock_idx].dens = 2; + clock_arch->clock_inf[clock_idx].prob = 0.5; + + // This will need to change for multi-clock + clock_arch->clock_inf[clock_idx].period = g_solution_inf.T_crit; + } + } + /* find the power dissipated by each clock network */ + power_usage_clock_single(&clock_power, + &clock_arch->clock_inf[clock_idx]); + power_add_usage(power_usage, &clock_power); + } + + return; +} + +/** + * Calculates the power from a single spine-and-rib global clock + */ +static void power_usage_clock_single(t_power_usage * power_usage, + t_clock_network * single_clock) { + + /* + * + * The following code assumes a spine-and-rib clock network as shown below. + * This is comprised of 3 main combonents: + * 1. A single wire from the io pad to the center of the chip + * 2. A H-structure which provides a 'spine' to all 4 quadrants + * 3. Ribs connect each spine with an entire column of blocks + + ___________________ + | | + | |_|_|_2__|_|_|_ | + | | | | | | | | | + | |3| | | | | | | + | | | + | | | | | | | | | + | |_|_|__|_|_|_|_ | + | | | | | | | | | + |_______1|________| + * It is assumed that there are a single-inverter buffers placed along each wire, + * with spacing equal to the FPGA block size (1 buffer/block) */ + t_power_usage clock_buffer_power; + int length; + t_power_usage buffer_power; + t_power_usage wire_power; + float C_segment; + float buffer_size; + + power_usage->dynamic = 0.; + power_usage->leakage = 0.; + + /* Check if this clock is active - this is used for calculating leakage */ + if (single_clock->dens) { + } else { + assert(0); + } + + C_segment = g_power_commonly_used->tile_length * single_clock->C_wire; + if (single_clock->autosize_buffer) { + buffer_size = 1 + C_segment / g_power_commonly_used->INV_1X_C_in; + } else { + buffer_size = single_clock->buffer_size; + } + + /* Calculate the capacitance and leakage power for the clock buffer */ + power_usage_inverter(&clock_buffer_power, single_clock->dens, + single_clock->prob, buffer_size, single_clock->period); + + length = 0; + + /* 1. IO to chip center */ + length += (ny + 2) / 2; + + /* 2. H-Tree to 4 quadrants */ + length += ny / 2 + 2 * nx; + + /* 3. Ribs - to */ + length += nx / 2 * ny; + + buffer_power.dynamic = length * clock_buffer_power.dynamic; + buffer_power.leakage = length * clock_buffer_power.leakage; + + power_add_usage(power_usage, &buffer_power); + power_component_add_usage(&buffer_power, POWER_COMPONENT_CLOCK_BUFFER); + + power_usage_wire(&wire_power, length * C_segment, single_clock->dens, + single_clock->period); + power_add_usage(power_usage, &wire_power); + power_component_add_usage(&wire_power, POWER_COMPONENT_CLOCK_WIRE); + + return; +} + +/* Frees a multiplexer graph */ +static void dealloc_mux_graph(t_mux_node * node) { + dealloc_mux_graph_rec(node); + free(node); +} + +static void dealloc_mux_graph_rec(t_mux_node * node) { + int child_idx; + + /* Dealloc Children */ + if (node->level != 0) { + for (child_idx = 0; child_idx < node->num_inputs; child_idx++) { + dealloc_mux_graph_rec(&node->children[child_idx]); + } + free(node->children); + } +} + +/** + * Calculates the power of the entire routing fabric (not local routing + */ +static void power_usage_routing(t_power_usage * power_usage, + t_det_routing_arch * routing_arch, t_segment_inf * segment_inf) { + int rr_node_idx; + int net_idx; + int edge_idx; + + power_zero_usage(power_usage); + + /* Reset routing statistics */ + g_power_commonly_used->num_sb_buffers = 0; + g_power_commonly_used->total_sb_buffer_size = 0.; + g_power_commonly_used->num_cb_buffers = 0; + g_power_commonly_used->total_cb_buffer_size = 0.; + + /* Reset rr graph net indices */ + for (rr_node_idx = 0; rr_node_idx < num_rr_nodes; rr_node_idx++) { + rr_node[rr_node_idx].net_num = OPEN; + rr_node_power[rr_node_idx].num_inputs = 0; + rr_node_power[rr_node_idx].selected_input = 0; + } + + /* Populate net indices into rr graph */ + for (net_idx = 0; net_idx < num_nets; net_idx++) { + struct s_trace * trace; + + for (trace = trace_head[net_idx]; trace != NULL; trace = trace->next) { + rr_node_power[trace->index].visited = FALSE; + } + } + + /* Populate net indices into rr graph */ + for (net_idx = 0; net_idx < num_nets; net_idx++) { + /* Xifan TANG: Skip the global nets and dangling nets*/ + if ((FALSE == clb_net[net_idx].is_global)||(FALSE == clb_net[net_idx].num_sinks)) { + continue; + } + struct s_trace * trace; + + for (trace = trace_head[net_idx]; trace != NULL; trace = trace->next) { + t_rr_node * node = &rr_node[trace->index]; + t_rr_node_power * node_power = &rr_node_power[trace->index]; + + if (node_power->visited) { + continue; + } + + node->net_num = net_idx; + + for (edge_idx = 0; edge_idx < node->num_edges; edge_idx++) { + if (node->edges[edge_idx] != OPEN) { + t_rr_node * next_node = &rr_node[node->edges[edge_idx]]; + t_rr_node_power * next_node_power = + &rr_node_power[node->edges[edge_idx]]; + + switch (next_node->type) { + case CHANX: + case CHANY: + case IPIN: + if (next_node->net_num == node->net_num) { + next_node_power->selected_input = + next_node_power->num_inputs; + } + next_node_power->in_dens[next_node_power->num_inputs] = + clb_net_density(node->net_num); + next_node_power->in_prob[next_node_power->num_inputs] = + clb_net_prob(node->net_num); + next_node_power->num_inputs++; + if (next_node_power->num_inputs > next_node->fan_in) { + printf("%d %d\n", next_node_power->num_inputs, + next_node->fan_in); + fflush(0); + assert(0); + } + break; + default: + /* Do nothing */ + break; + } + } + } + node_power->visited = TRUE; + } + } + + /* Calculate power of all routing entities */ + for (rr_node_idx = 0; rr_node_idx < num_rr_nodes; rr_node_idx++) { + t_power_usage sub_power_usage; + t_rr_node * node = &rr_node[rr_node_idx]; + t_rr_node_power * node_power = &rr_node_power[rr_node_idx]; + float C_wire; + float buffer_size; + int switch_idx; + int connectionbox_fanout; + int switchbox_fanout; + //float C_per_seg_split; + int wire_length; + + switch (node->type) { + case SOURCE: + case SINK: + case OPIN: + /* No power usage for these types */ + break; + case IPIN: + /* This is part of the connectionbox. The connection box is comprised of: + * - Driver (accounted for at end of CHANX/Y - see below) + * - Multiplexor */ + + if (node->fan_in) { + assert(node_power->in_dens); + assert(node_power->in_prob); + + /* Multiplexor */ + power_usage_mux_multilevel(&sub_power_usage, + power_get_mux_arch(node->fan_in, + g_power_arch->mux_transistor_size), + node_power->in_prob, node_power->in_dens, + node_power->selected_input, TRUE, + g_solution_inf.T_crit); + power_add_usage(power_usage, &sub_power_usage); + power_component_add_usage(&sub_power_usage, + POWER_COMPONENT_ROUTE_CB); + } + break; + case CHANX: + case CHANY: + /* This is a wire driven by a switchbox, which includes: + * - The Multiplexor at the beginning of the wire + * - A buffer, after the mux to drive the wire + * - The wire itself + * - A buffer at the end of the wire, going to switchbox/connectionbox */ + assert(node_power->in_dens); + assert(node_power->in_prob); + + wire_length = 0; + if (node->type == CHANX) { + wire_length = node->xhigh - node->xlow + 1; + } else if (node->type == CHANY) { + wire_length = node->yhigh - node->ylow + 1; + } + C_wire = + wire_length + * segment_inf[rr_indexed_data[node->cost_index].seg_index].Cmetal; + //(double)g_power_commonly_used->tile_length); + assert(node_power->selected_input < node->fan_in); + + /* Multiplexor */ + power_usage_mux_multilevel(&sub_power_usage, + power_get_mux_arch(node->fan_in, + g_power_arch->mux_transistor_size), + node_power->in_prob, node_power->in_dens, + node_power->selected_input, TRUE, g_solution_inf.T_crit); + power_add_usage(power_usage, &sub_power_usage); + power_component_add_usage(&sub_power_usage, + POWER_COMPONENT_ROUTE_SB); + + /* Buffer Size */ + switch (switch_inf[node_power->driver_switch_type].power_buffer_type) { + case POWER_BUFFER_TYPE_AUTO: + /* + C_per_seg_split = ((float) node->num_edges + * g_power_commonly_used->INV_1X_C_in + C_wire); + // / (float) g_power_arch->seg_buffer_split; + buffer_size = power_buffer_size_from_logical_effort( + C_per_seg_split); + buffer_size = max(buffer_size, 1.0F); + */ + buffer_size = power_calc_buffer_size_from_Cout( + switch_inf[node_power->driver_switch_type].Cout); + break; + case POWER_BUFFER_TYPE_ABSOLUTE_SIZE: + buffer_size = + switch_inf[node_power->driver_switch_type].power_buffer_size; + buffer_size = max(buffer_size, 1.0F); + break; + case POWER_BUFFER_TYPE_NONE: + buffer_size = 0.; + break; + default: + buffer_size = 0.; + assert(0); + break; + } + + g_power_commonly_used->num_sb_buffers++; + g_power_commonly_used->total_sb_buffer_size += buffer_size; + + /* + g_power_commonly_used->num_sb_buffers += + g_power_arch->seg_buffer_split; + g_power_commonly_used->total_sb_buffer_size += buffer_size + * g_power_arch->seg_buffer_split; + */ + + /* Buffer */ + power_usage_buffer(&sub_power_usage, buffer_size, + node_power->in_prob[node_power->selected_input], + node_power->in_dens[node_power->selected_input], TRUE, + g_solution_inf.T_crit); + power_add_usage(power_usage, &sub_power_usage); + power_component_add_usage(&sub_power_usage, + POWER_COMPONENT_ROUTE_SB); + + /* Wire Capacitance */ + power_usage_wire(&sub_power_usage, C_wire, + clb_net_density(node->net_num), g_solution_inf.T_crit); + power_add_usage(power_usage, &sub_power_usage); + power_component_add_usage(&sub_power_usage, + POWER_COMPONENT_ROUTE_GLB_WIRE); + + /* Determine types of switches that this wire drives */ + connectionbox_fanout = 0; + switchbox_fanout = 0; + for (switch_idx = 0; switch_idx < node->num_edges; switch_idx++) { + if (node->switches[switch_idx] + == routing_arch->wire_to_ipin_switch) { + connectionbox_fanout++; + } else if (node->switches[switch_idx] + == routing_arch->delayless_switch) { + /* Do nothing */ + } else { + switchbox_fanout++; + } + } + + /* Buffer to next Switchbox */ + if (switchbox_fanout) { + buffer_size = power_buffer_size_from_logical_effort( + switchbox_fanout * g_power_commonly_used->NMOS_1X_C_d); + power_usage_buffer(&sub_power_usage, buffer_size, + 1 - node_power->in_prob[node_power->selected_input], + node_power->in_dens[node_power->selected_input], FALSE, + g_solution_inf.T_crit); + power_add_usage(power_usage, &sub_power_usage); + power_component_add_usage(&sub_power_usage, + POWER_COMPONENT_ROUTE_SB); + } + + /* Driver for ConnectionBox */ + if (connectionbox_fanout) { + + buffer_size = power_buffer_size_from_logical_effort( + connectionbox_fanout + * g_power_commonly_used->NMOS_1X_C_d); + + power_usage_buffer(&sub_power_usage, buffer_size, + node_power->in_dens[node_power->selected_input], + 1 - node_power->in_prob[node_power->selected_input], + FALSE, g_solution_inf.T_crit); + power_add_usage(power_usage, &sub_power_usage); + power_component_add_usage(&sub_power_usage, + POWER_COMPONENT_ROUTE_CB); + + g_power_commonly_used->num_cb_buffers++; + g_power_commonly_used->total_cb_buffer_size += buffer_size; + } + break; + case INTRA_CLUSTER_EDGE: + assert(0); + break; + default: + power_log_msg(POWER_LOG_WARNING, + "The global routing-resource graph contains an unknown node type."); + break; + } + } +} + +void power_alloc_and_init_pb_pin(t_pb_graph_pin * pin) { + int port_idx; + t_port * port_to_find; + t_pb_graph_node * node = pin->parent_node; + boolean found; + + pin->pin_power = (t_pb_graph_pin_power*) malloc( + sizeof(t_pb_graph_pin_power)); + pin->pin_power->C_wire = 0.; + pin->pin_power->buffer_size = 0.; + pin->pin_power->scaled_by_pin = NULL; + + if (pin->port->port_power->scaled_by_port) { + + port_to_find = pin->port->port_power->scaled_by_port; + + /*pin->pin_power->scaled_by_pin = + get_pb_graph_node_pin_from_model_port_pin( + port_to_find->model_port, + pin->port->port_power->scaled_by_port_pin_idx, + pin->parent_node);*/ + /* Search input, output, clock ports */ + + found = FALSE; + for (port_idx = 0; port_idx < node->num_input_ports; port_idx++) { + if (node->input_pins[port_idx][0].port == port_to_find) { + pin->pin_power->scaled_by_pin = + &node->input_pins[port_idx][pin->port->port_power->scaled_by_port_pin_idx]; + found = TRUE; + break; + } + } + if (!found) { + for (port_idx = 0; port_idx < node->num_output_ports; port_idx++) { + if (node->output_pins[port_idx][0].port == port_to_find) { + pin->pin_power->scaled_by_pin = + &node->output_pins[port_idx][pin->port->port_power->scaled_by_port_pin_idx]; + found = TRUE; + break; + } + } + } + if (!found) { + for (port_idx = 0; port_idx < node->num_clock_ports; port_idx++) { + if (node->clock_pins[port_idx][0].port == port_to_find) { + pin->pin_power->scaled_by_pin = + &node->clock_pins[port_idx][pin->port->port_power->scaled_by_port_pin_idx]; + found = TRUE; + break; + } + } + } + assert(found); + + assert(pin->pin_power->scaled_by_pin); + } +} + +void power_init_pb_pins_rec(t_pb_graph_node * pb_node) { + int mode; + int type; + int pb; + int port_idx; + int pin_idx; + + for (port_idx = 0; port_idx < pb_node->num_input_ports; port_idx++) { + for (pin_idx = 0; pin_idx < pb_node->num_input_pins[port_idx]; + pin_idx++) { + power_alloc_and_init_pb_pin( + &pb_node->input_pins[port_idx][pin_idx]); + } + } + + for (port_idx = 0; port_idx < pb_node->num_output_ports; port_idx++) { + for (pin_idx = 0; pin_idx < pb_node->num_output_pins[port_idx]; + pin_idx++) { + power_alloc_and_init_pb_pin( + &pb_node->output_pins[port_idx][pin_idx]); + } + } + + for (port_idx = 0; port_idx < pb_node->num_clock_ports; port_idx++) { + for (pin_idx = 0; pin_idx < pb_node->num_clock_pins[port_idx]; + pin_idx++) { + power_alloc_and_init_pb_pin( + &pb_node->clock_pins[port_idx][pin_idx]); + } + } + + for (mode = 0; mode < pb_node->pb_type->num_modes; mode++) { + for (type = 0; + type < pb_node->pb_type->modes[mode].num_pb_type_children; + type++) { + for (pb = 0; + pb + < pb_node->pb_type->modes[mode].pb_type_children[type].num_pb; + pb++) { + power_init_pb_pins_rec( + &pb_node->child_pb_graph_nodes[mode][type][pb]); + } + } + } +} + +void power_pb_pins_init() { + int type_idx; + + for (type_idx = 0; type_idx < num_types; type_idx++) { + if (type_descriptors[type_idx].pb_graph_head) { + power_init_pb_pins_rec(type_descriptors[type_idx].pb_graph_head); + } + } +} + +void power_routing_init(t_det_routing_arch * routing_arch) { + int net_idx; + int rr_node_idx; + int max_fanin; + int max_IPIN_fanin; + int max_seg_to_IPIN_fanout; + int max_seg_to_seg_fanout; + int max_seg_fanout; + + /* Copy probability/density values to new netlist */ + for (net_idx = 0; net_idx < num_nets; net_idx++) { + if (!clb_net[net_idx].net_power) { + clb_net[net_idx].net_power = new t_net_power; + } + clb_net[net_idx].net_power->probability = + vpack_net[clb_to_vpack_net_mapping[net_idx]].net_power->probability; + clb_net[net_idx].net_power->density = + vpack_net[clb_to_vpack_net_mapping[net_idx]].net_power->density; + } + + /* Initialize RR Graph Structures */ + rr_node_power = (t_rr_node_power*) my_calloc(num_rr_nodes, + sizeof(t_rr_node_power)); + for (rr_node_idx = 0; rr_node_idx < num_rr_nodes; rr_node_idx++) { + rr_node_power[rr_node_idx].driver_switch_type = OPEN; + + } + + /* Initialize Mux Architectures */ + max_fanin = 0; + max_IPIN_fanin = 0; + max_seg_to_seg_fanout = 0; + max_seg_to_IPIN_fanout = 0; + for (rr_node_idx = 0; rr_node_idx < num_rr_nodes; rr_node_idx++) { + int switch_idx; + int fanout_to_IPIN = 0; + int fanout_to_seg = 0; + t_rr_node * node = &rr_node[rr_node_idx]; + t_rr_node_power * node_power = &rr_node_power[rr_node_idx]; + + switch (node->type) { + case IPIN: + max_IPIN_fanin = max(max_IPIN_fanin, + static_cast(node->fan_in)); + max_fanin = max(max_fanin, static_cast(node->fan_in)); + + node_power->in_dens = (float*) my_calloc(node->fan_in, + sizeof(float)); + node_power->in_prob = (float*) my_calloc(node->fan_in, + sizeof(float)); + break; + case CHANX: + case CHANY: + for (switch_idx = 0; switch_idx < node->num_edges; switch_idx++) { + if (node->switches[switch_idx] + == routing_arch->wire_to_ipin_switch) { + fanout_to_IPIN++; + } else if (node->switches[switch_idx] + != routing_arch->delayless_switch) { + fanout_to_seg++; + } + } + max_seg_to_IPIN_fanout = max(max_seg_to_IPIN_fanout, + fanout_to_IPIN); + max_seg_to_seg_fanout = max(max_seg_to_seg_fanout, fanout_to_seg); + max_fanin = max(max_fanin, static_cast(node->fan_in)); + + node_power->in_dens = (float*) my_calloc(node->fan_in, + sizeof(float)); + node_power->in_prob = (float*) my_calloc(node->fan_in, + sizeof(float)); + break; + default: + /* Do nothing */ + break; + } + } + g_power_commonly_used->max_routing_mux_size = max_fanin; + g_power_commonly_used->max_IPIN_fanin = max_IPIN_fanin; + g_power_commonly_used->max_seg_to_seg_fanout = max_seg_to_seg_fanout; + g_power_commonly_used->max_seg_to_IPIN_fanout = max_seg_to_IPIN_fanout; + +#if (PRINT_SPICE_COMPARISON) + g_power_commonly_used->max_routing_mux_size = + max(g_power_commonly_used->max_routing_mux_size, 26); +#endif + + /* Populate driver switch type */ + for (rr_node_idx = 0; rr_node_idx < num_rr_nodes; rr_node_idx++) { + t_rr_node * node = &rr_node[rr_node_idx]; + int edge_idx; + + for (edge_idx = 0; edge_idx < node->num_edges; edge_idx++) { + if (node->edges[edge_idx] != OPEN) { + if (rr_node_power[node->edges[edge_idx]].driver_switch_type + == OPEN) { + rr_node_power[node->edges[edge_idx]].driver_switch_type = + node->switches[edge_idx]; + /* Xifan TANG: Switch Segment Pattern Support */ + } else if (rr_node[node->edges[edge_idx]].unbuf_switched) { + rr_node_power[node->edges[edge_idx]].driver_switch_type = rr_node[node->edges[edge_idx]].driver_switch; + /* END */ + } else { + assert(rr_node_power[node->edges[edge_idx]].driver_switch_type == node->switches[edge_idx]); + } + } + } + } + + /* Find Max Fanout of Routing Buffer */ + max_seg_fanout = 0; + for (rr_node_idx = 0; rr_node_idx < num_rr_nodes; rr_node_idx++) { + t_rr_node * node = &rr_node[rr_node_idx]; + + switch (node->type) { + case CHANX: + case CHANY: + if (node->num_edges > max_seg_fanout) { + max_seg_fanout = node->num_edges; + } + break; + default: + /* Do nothing */ + break; + } + } + g_power_commonly_used->max_seg_fanout = max_seg_fanout; +} + +/** + * Initialization for all power-related functions + */ +boolean power_init(char * power_out_filepath, + char * cmos_tech_behavior_filepath, t_arch * arch, + t_det_routing_arch * routing_arch) { + boolean error = FALSE; + + /* Set global power architecture & options */ + g_power_arch = arch->power; + g_power_commonly_used = new t_power_commonly_used; + g_power_tech = (t_power_tech*) my_malloc(sizeof(t_power_tech)); + g_power_output = (t_power_output*) my_malloc(sizeof(t_power_output)); + + /* Set up Logs */ + g_power_output->num_logs = POWER_LOG_NUM_TYPES; + g_power_output->logs = (t_log*) my_calloc(g_power_output->num_logs, + sizeof(t_log)); + g_power_output->logs[POWER_LOG_ERROR].name = my_strdup("Errors"); + g_power_output->logs[POWER_LOG_WARNING].name = my_strdup("Warnings"); + + /* Initialize output file */ + if (!error) { + g_power_output->out = NULL; + g_power_output->out = my_fopen(power_out_filepath, "w", 0); + if (!g_power_output->out) { + error = TRUE; + } + } + + /* Load technology properties */ + power_tech_init(cmos_tech_behavior_filepath); + + /* Low-Level Initialization */ + power_lowlevel_init(); + + /* Initialize sub-modules */ + power_components_init(); + + /* Perform callibration */ + power_callibrate(); + + /* Initialize routing information */ + power_routing_init(routing_arch); + +// Allocates power structures for each pb pin + power_pb_pins_init(); + + /* Size all components */ + power_sizing_init(arch); + + //power_print_spice_comparison(); + + return error; +} + +/** + * Uninitialize power module + */ +boolean power_uninit(void) { + int mux_size; + int log_idx; + int rr_node_idx; + int msg_idx; + boolean error = FALSE; + + for (rr_node_idx = 0; rr_node_idx < num_rr_nodes; rr_node_idx++) { + t_rr_node * node = &rr_node[rr_node_idx]; + t_rr_node_power * node_power = &rr_node_power[rr_node_idx]; + + switch (node->type) { + case CHANX: + case CHANY: + case IPIN: + if (node->fan_in) { + free(node_power->in_dens); + free(node_power->in_prob); + } + break; + default: + /* Do nothing */ + break; + } + } + free(rr_node_power); + + /* Free mux architectures */ + for (std::map::iterator it = + g_power_commonly_used->mux_info.begin(); + it != g_power_commonly_used->mux_info.end(); it++) { + t_power_mux_info * mux_info = it->second; + for (mux_size = 1; mux_size <= mux_info->mux_arch_max_size; + mux_size++) { + dealloc_mux_graph(mux_info->mux_arch[mux_size].mux_graph_head); + } + delete mux_info; + } + free(g_power_commonly_used); + + if (g_power_output->out) { + fclose(g_power_output->out); + } + + /* Free logs */ + for (log_idx = 0; log_idx < g_power_output->num_logs; log_idx++) { + for (msg_idx = 0; msg_idx < g_power_output->logs[log_idx].num_messages; + msg_idx++) { + free(g_power_output->logs[log_idx].messages[msg_idx]); + } + free(g_power_output->logs[log_idx].messages); + free(g_power_output->logs[log_idx].name); + } + free(g_power_output->logs); + free(g_power_output); + + return error; +} + +#if 0 +/** + * Prints the power of all pb structures, in an xml format that matches the archicture file + */ +static void power_print_pb_usage_recursive(FILE * fp, t_pb_type * type, + int indent_level, float parent_power, float total_power) { + int mode_idx; + int mode_indent; + int child_idx; + int interc_idx; + float pb_type_power; + + pb_type_power = type->pb_type_power->power_usage.dynamic + + type->pb_type_power->power_usage.leakage; + + print_tabs(fp, indent_level); + fprintf(fp, + "\n", + type->name, pb_type_power, pb_type_power / parent_power * 100, + pb_type_power / total_power * 100, + type->pb_type_power->power_usage.dynamic / pb_type_power); + + mode_indent = 0; + if (type->num_modes > 1) { + mode_indent = 1; + } + + for (mode_idx = 0; mode_idx < type->num_modes; mode_idx++) { + float mode_power; + mode_power = type->modes[mode_idx].mode_power->power_usage.dynamic + + type->modes[mode_idx].mode_power->power_usage.leakage; + + if (type->num_modes > 1) { + print_tabs(fp, indent_level + mode_indent); + fprintf(fp, + "\n", + type->modes[mode_idx].name, mode_power, + mode_power / pb_type_power * 100, + mode_power / total_power * 100, + type->modes[mode_idx].mode_power->power_usage.dynamic + / mode_power); + } + + if (type->modes[mode_idx].num_interconnect) { + /* Sum the interconnect power */ + t_power_usage interc_power_usage; + float interc_total_power; + + power_zero_usage(&interc_power_usage); + for (interc_idx = 0; + interc_idx < type->modes[mode_idx].num_interconnect; + interc_idx++) { + power_add_usage(&interc_power_usage, + &type->modes[mode_idx].interconnect[interc_idx].interconnect_power->power_usage); + } + interc_total_power = interc_power_usage.dynamic + + interc_power_usage.leakage; + + /* All interconnect */ + print_tabs(fp, indent_level + mode_indent + 1); + fprintf(fp, + "\n", + interc_total_power, interc_total_power / mode_power * 100, + interc_total_power / total_power * 100, + interc_power_usage.dynamic / interc_total_power); + for (interc_idx = 0; + interc_idx < type->modes[mode_idx].num_interconnect; + interc_idx++) { + float interc_power = + type->modes[mode_idx].interconnect[interc_idx].interconnect_power->power_usage.dynamic + + type->modes[mode_idx].interconnect[interc_idx].interconnect_power->power_usage.leakage; + /* Each interconnect */ + print_tabs(fp, indent_level + mode_indent + 2); + fprintf(fp, + "<%s name=\"%s\" P=\"%.4g\" P_parent=\"%.3g\" P_total=\"%.3g\" P_dyn=\"%.3g\"/>\n", + interconnect_type_name( + type->modes[mode_idx].interconnect[interc_idx].type), + type->modes[mode_idx].interconnect[interc_idx].name, + interc_power, interc_power / interc_total_power * 100, + interc_power / total_power * 100, + type->modes[mode_idx].interconnect[interc_idx].interconnect_power->power_usage.dynamic + / interc_power); + } + print_tabs(fp, indent_level + mode_indent + 1); + fprintf(fp, "\n"); + } + + for (child_idx = 0; + child_idx < type->modes[mode_idx].num_pb_type_children; + child_idx++) { + power_print_pb_usage_recursive(fp, + &type->modes[mode_idx].pb_type_children[child_idx], + indent_level + mode_indent + 1, + type->modes[mode_idx].mode_power->power_usage.dynamic + + type->modes[mode_idx].mode_power->power_usage.leakage, + total_power); + } + + if (type->num_modes > 1) { + print_tabs(fp, indent_level + mode_indent); + fprintf(fp, "\n"); + } + } + + print_tabs(fp, indent_level); + fprintf(fp, "\n"); +} + +static void power_print_clb_detailed(FILE * fp) { + int type_idx; + + float clb_power_total = power_component_get_usage_sum( + POWER_COMPONENT_PB); + for (type_idx = 0; type_idx < num_types; type_idx++) { + if (!type_descriptors[type_idx].pb_type) { + continue; + } + + power_print_pb_usage_recursive(fp, type_descriptors[type_idx].pb_type, + 0, clb_power_total, clb_power_total); + } +} +#endif + +/* + static void power_print_stats(FILE * fp) { + fprintf(fp, "Max Segment Fanout: %d\n", + g_power_commonly_used->max_seg_fanout); + fprintf(fp, "Max Segment->Segment Fanout: %d\n", + g_power_commonly_used->max_seg_to_seg_fanout); + fprintf(fp, "Max Segment->IPIN Fanout: %d\n", + g_power_commonly_used->max_seg_to_IPIN_fanout); + fprintf(fp, "Max IPIN fanin: %d\n", g_power_commonly_used->max_IPIN_fanin); + fprintf(fp, "Average SB Buffer Size: %.1f\n", + g_power_commonly_used->total_sb_buffer_size + / (float) g_power_commonly_used->num_sb_buffers); + fprintf(fp, "SB Buffer Transistors: %g\n", + power_count_transistors_buffer( + g_power_commonly_used->total_sb_buffer_size + / (float) g_power_commonly_used->num_sb_buffers)); + fprintf(fp, "Average CB Buffer Size: %.1f\n", + g_power_commonly_used->total_cb_buffer_size + / (float) g_power_commonly_used->num_cb_buffers); + fprintf(fp, "Tile length (um): %.2f\n", + g_power_commonly_used->tile_length * CONVERT_UM_PER_M); + fprintf(fp, "1X Inverter C_in: %g\n", g_power_commonly_used->INV_1X_C_in); + fprintf(fp, "\n"); + } + */ + +static char * power_estimation_method_name( + e_power_estimation_method power_method) { + switch (power_method) { + case POWER_METHOD_UNDEFINED: + return "Undefined"; + case POWER_METHOD_IGNORE: + return "Ignore"; + case POWER_METHOD_AUTO_SIZES: + return "Transistor Auto-Size"; + case POWER_METHOD_SPECIFY_SIZES: + return "Transistor Specify-Size"; + case POWER_METHOD_TOGGLE_PINS: + return "Pin-Toggle"; + case POWER_METHOD_C_INTERNAL: + return "C-Internal"; + case POWER_METHOD_ABSOLUTE: + return "Absolute"; + case POWER_METHOD_SUM_OF_CHILDREN: + return "Sum of Children"; + default: + return "Unkown"; + } +} + +static void power_print_breakdown_pb_rec(FILE * fp, t_pb_type * pb_type, + int indent) { + int mode_idx; + int child_idx; + int i; + char buf[51]; + int child_indent; + int interc_idx; + t_mode * mode; + t_power_usage interc_usage; + e_power_estimation_method est_method = + pb_type->pb_type_power->estimation_method; + float total_power = power_component_get_usage_sum(POWER_COMPONENT_TOTAL); + t_pb_type_power * pb_power = pb_type->pb_type_power; + + for (i = 0; i < indent; i++) { + buf[i] = ' '; + } + strncpy(buf + indent, pb_type->name, 50 - indent); + buf[50] = '\0'; + buf[strlen((pb_type->name)) + indent] = '\0'; + power_print_breakdown_entry(fp, indent, POWER_BREAKDOWN_ENTRY_TYPE_PB, + pb_type->name, power_sum_usage(&pb_power->power_usage), total_power, + power_perc_dynamic(&pb_power->power_usage), + power_estimation_method_name( + pb_type->pb_type_power->estimation_method)); + + if (power_method_is_transistor_level( + pb_type->pb_type_power->estimation_method)) { + /* Local bufs and wires */ + power_print_breakdown_entry(fp, indent + 1, + POWER_BREAKDOWN_ENTRY_TYPE_BUFS_WIRES, "Bufs/Wires", + power_sum_usage(&pb_power->power_usage_bufs_wires), total_power, + power_perc_dynamic(&pb_power->power_usage_bufs_wires), NULL); + } + + if (power_method_is_recursive(est_method)) { + if (pb_type->num_modes > 1) { + child_indent = indent + 2; + } else { + child_indent = indent + 1; + } + + for (mode_idx = 0; mode_idx < pb_type->num_modes; mode_idx++) { + mode = &pb_type->modes[mode_idx]; + + if (pb_type->num_modes > 1) { + power_print_breakdown_entry(fp, indent + 1, + POWER_BREAKDOWN_ENTRY_TYPE_MODE, mode->name, + power_sum_usage(&mode->mode_power->power_usage), + total_power, + power_perc_dynamic(&mode->mode_power->power_usage), + NULL); + } + + /* Interconnect Power */ + power_zero_usage(&interc_usage); + + /* Sum the interconnect */ + if (power_method_is_transistor_level(est_method)) { + for (interc_idx = 0; interc_idx < mode->num_interconnect; + interc_idx++) { + power_add_usage(&interc_usage, + &mode->interconnect[interc_idx].interconnect_power->power_usage); + } + if (mode->num_interconnect) { + power_print_breakdown_entry(fp, child_indent, + POWER_BREAKDOWN_ENTRY_TYPE_INTERC, "Interc:", + power_sum_usage(&interc_usage), total_power, + power_perc_dynamic(&interc_usage), NULL); + } + + /* Print Interconnect Breakdown */ + for (interc_idx = 0; interc_idx < mode->num_interconnect; + interc_idx++) { + t_interconnect * interc = &mode->interconnect[interc_idx]; + if (interc->type == DIRECT_INTERC) { + // no power - skip + } else { + power_print_breakdown_entry(fp, child_indent + 1, + POWER_BREAKDOWN_ENTRY_TYPE_INTERC, interc->name, + power_sum_usage( + &interc->interconnect_power->power_usage), + total_power, + power_perc_dynamic( + &interc->interconnect_power->power_usage), + NULL); + } + } + } + + for (child_idx = 0; + child_idx < pb_type->modes[mode_idx].num_pb_type_children; + child_idx++) { + power_print_breakdown_pb_rec(fp, + &pb_type->modes[mode_idx].pb_type_children[child_idx], + child_indent); + } + } + } +} + +static void power_print_summary(FILE * fp, t_vpr_setup vpr_setup) { + char * arch; + char * arch_new; + + /* Extract filename from full path */ + arch = vpr_setup.FileNameOpts.ArchFile; + + arch_new = strrchr(vpr_setup.FileNameOpts.ArchFile, '/'); + if (arch_new) + arch = arch_new + 1; + + arch_new = strrchr(vpr_setup.FileNameOpts.ArchFile, '\\'); + if (arch_new) + arch = arch_new + 1; + + fprintf(g_power_output->out, "Circuit: %s\n", + vpr_setup.FileNameOpts.CircuitName); + fprintf(g_power_output->out, "Architecture: %s\n", arch); + fprintf(fp, "Technology (nm): %.0f\n", + g_power_tech->tech_size * CONVERT_NM_PER_M); + fprintf(fp, "Voltage: %.2f\n", g_power_tech->Vdd); + fprintf(fp, "Temperature: %g\n", g_power_tech->temperature); + fprintf(fp, "Critical Path: %g\n", g_solution_inf.T_crit); + fprintf(fp, "Size of FPGA: %d x %d\n", nx, ny); + fprintf(fp, "Channel Width: %d\n", g_solution_inf.channel_width); + fprintf(fp, "\n"); +} + +/* + * Top-level function for the power module. + * Calculates the average power of the entire FPGA (watts), + * and prints it to the output file + * - run_time_s: (Return value) The total runtime in seconds (us accuracy) + */ +e_power_ret_code power_total(float * run_time_s, t_vpr_setup vpr_setup, + t_arch * arch, t_det_routing_arch * routing_arch) { + t_power_usage total_power; + t_power_usage sub_power_usage; + clock_t t_start; + clock_t t_end; + t_power_usage clb_power_usage; + + t_start = clock(); + + power_zero_usage(&total_power); + + if (routing_arch->directionality == BI_DIRECTIONAL) { + power_log_msg(POWER_LOG_ERROR, + "Cannot calculate routing power for bi-directional architectures"); + return POWER_RET_CODE_ERRORS; + } + + /* Calculate Power */ + /* Routing */ + power_usage_routing(&sub_power_usage, routing_arch, arch->Segments); + power_add_usage(&total_power, &sub_power_usage); + power_component_add_usage(&sub_power_usage, POWER_COMPONENT_ROUTING); + + /* Clock */ + power_usage_clock(&sub_power_usage, arch->clocks); + power_add_usage(&total_power, &sub_power_usage); + power_component_add_usage(&sub_power_usage, POWER_COMPONENT_CLOCK); + + /* CLBs */ + power_usage_blocks(&clb_power_usage); + power_add_usage(&total_power, &clb_power_usage); + power_component_add_usage(&clb_power_usage, POWER_COMPONENT_PB); + + power_component_add_usage(&total_power, POWER_COMPONENT_TOTAL); + + power_print_title(g_power_output->out, "Summary"); + power_print_summary(g_power_output->out, vpr_setup); + + /* Print Error & Warning Logs */ + output_logs(g_power_output->out, g_power_output->logs, + g_power_output->num_logs); + + //power_print_title(g_power_output->out, "Statistics"); + //power_print_stats(g_power_output->out); + + power_print_title(g_power_output->out, "Power Breakdown"); + power_print_breakdown_summary(g_power_output->out); + + power_print_title(g_power_output->out, "Power Breakdown by PB"); + power_print_breakdown_pb(g_power_output->out); + + //power_print_title(g_power_output->out, "Spice Comparison"); + //power_print_spice_comparison(); + + t_end = clock(); + + *run_time_s = (float) (t_end - t_start) / CLOCKS_PER_SEC; + + /* Return code */ + if (g_power_output->logs[POWER_LOG_ERROR].num_messages) { + return POWER_RET_CODE_ERRORS; + } else if (g_power_output->logs[POWER_LOG_WARNING].num_messages) { + return POWER_RET_CODE_WARNINGS; + } else { + return POWER_RET_CODE_SUCCESS; + } +} + +/** + * Prints the power usage for all components + * - fp: File descripter to print out to + */ +static void power_print_breakdown_summary(FILE * fp) { + power_print_breakdown_entry(fp, 0, POWER_BREAKDOWN_ENTRY_TYPE_TITLE, NULL, + 0., 0., 0., NULL); + power_print_breakdown_component(fp, "Total", POWER_COMPONENT_TOTAL, 0); + fprintf(fp, "\n"); +} + +static void power_print_breakdown_pb(FILE * fp) { + fprintf(fp, + "This sections provides a detailed breakdown of power usage by PB (physical\n" + "block). For each PB, the power is listed, which is the sum power of all\n" + "instances of the block. It also indicates its percentage of total power (entire\n" + "FPGA), as well as the percentage of its power that is dynamic (vs. static). It\n" + "also indicates the method used for power estimation.\n\n" + "The data includes:\n" + "\tModes:\t\tWhen a pb contains multiple modes, each mode is " + "listed, with\n\t\t\t\tits power statistics.\n" + "\tBufs/Wires:\tPower of all local " + "buffers and local wire switching\n" + "\t\t\t\t(transistor-level estimation only).\n" + "\tInterc:\t\tPower of local interconnect multiplexers (transistor-\n" + "\t\t\t\tlevel estimation only)\n\n" + "Description of Estimation Methods:\n" + "\tTransistor Auto-Size: Transistor-level power estimation. Local buffers and\n" + "\t\twire lengths are automatically sized. This is the default estimation\n" + "\t\tmethod.\n" + "\tTransistor Specify-Size: Transistor-level power estimation. Local buffers\n" + "\t\tand wire lengths are only inserted where specified by the user in the\n" + "\t\tarchitecture file.\n" + "\tPin-Toggle: Dynamic power is calculated using enery-per-toggle of the PB\n" + "\t\tinput pins. Static power is absolute.\n" + "\tC-Internal: Dynamic power is calculated using an internal equivalent\n" + "\t\tcapacitance for PB type. Static power is absolute.\n" + "\tAbsolute: Dynamic and static power are absolutes from the architecture file.\n" + "\tSum of Children: Power of PB is only the sum of all child PBs; interconnect\n" + "\t\tbetween the PB and its children is ignored.\n" + "\tIgnore: Power of PB is ignored.\n\n\n"); + + power_print_breakdown_entry(fp, 0, POWER_BREAKDOWN_ENTRY_TYPE_TITLE, NULL, + 0., 0., 0., NULL); + + for (int type_idx = 0; type_idx < num_types; type_idx++) { + if (type_descriptors[type_idx].pb_type) { + power_print_breakdown_pb_rec(g_power_output->out, + type_descriptors[type_idx].pb_type, 0); + } + } + fprintf(fp, "\n"); +} + +/** + * Internal recurseive function, used by power_component_print_usage + */ +static void power_print_breakdown_component(FILE * fp, char * name, + e_power_component_type type, int indent_level) { + power_print_breakdown_entry(fp, indent_level, + POWER_BREAKDOWN_ENTRY_TYPE_COMPONENT, name, + power_sum_usage(&g_power_by_component.components[type]), + power_sum_usage( + &g_power_by_component.components[POWER_COMPONENT_TOTAL]), + power_perc_dynamic(&g_power_by_component.components[type]), NULL); + + switch (type) { + case (POWER_COMPONENT_TOTAL): + power_print_breakdown_component(fp, "Routing", POWER_COMPONENT_ROUTING, + indent_level + 1); + power_print_breakdown_component(fp, "PB Types", POWER_COMPONENT_PB, + indent_level + 1); + power_print_breakdown_component(fp, "Clock", POWER_COMPONENT_CLOCK, + indent_level + 1); + break; + case (POWER_COMPONENT_ROUTING): + power_print_breakdown_component(fp, "Switch Box", + POWER_COMPONENT_ROUTE_SB, indent_level + 1); + power_print_breakdown_component(fp, "Connection Box", + POWER_COMPONENT_ROUTE_CB, indent_level + 1); + power_print_breakdown_component(fp, "Global Wires", + POWER_COMPONENT_ROUTE_GLB_WIRE, indent_level + 1); + break; + case (POWER_COMPONENT_CLOCK): + /* + power_print_breakdown_component(fp, "Clock Buffers", + POWER_COMPONENT_CLOCK_BUFFER, indent_level + 1); + power_print_breakdown_component(fp, "Clock Wires", + POWER_COMPONENT_CLOCK_WIRE, indent_level + 1); + */ + break; + case (POWER_COMPONENT_PB): + power_print_breakdown_component(fp, "Primitives", + POWER_COMPONENT_PB_PRIMITIVES, indent_level + 1); + power_print_breakdown_component(fp, "Interc Structures", + POWER_COMPONENT_PB_INTERC_MUXES, indent_level + 1); + power_print_breakdown_component(fp, "Buffers and Wires", + POWER_COMPONENT_PB_BUFS_WIRE, indent_level + 1); + power_print_breakdown_component(fp, "Other Estimation Methods", + POWER_COMPONENT_PB_OTHER, indent_level + 1); + break; + default: + break; + } +} + +static void power_print_breakdown_entry(FILE * fp, int indent, + e_power_breakdown_entry_type type, char * name, float power, + float total_power, float perc_dyn, char * method) { + const int buf_size = 32; + char buf[buf_size]; + + switch (type) { + case POWER_BREAKDOWN_ENTRY_TYPE_TITLE: + fprintf(fp, "%-*s%-12s%-12s%-12s%-12s\n\n", buf_size, "Component", + "Power (W)", "%-Total", "%-Dynamic", "Method"); + break; + case POWER_BREAKDOWN_ENTRY_TYPE_MODE: + for (int i = 0; i < indent; i++) + buf[i] = ' '; + strcpy(buf + indent, "Mode:"); + strncpy(buf + indent + 5, name, buf_size - indent - 6); + fprintf(fp, "%-*s%-12.4g%-12.4g%-12.4g\n", buf_size, buf, power, + power / total_power, perc_dyn); + break; + case POWER_BREAKDOWN_ENTRY_TYPE_COMPONENT: + case POWER_BREAKDOWN_ENTRY_TYPE_INTERC: + case POWER_BREAKDOWN_ENTRY_TYPE_BUFS_WIRES: + for (int i = 0; i < indent; i++) + buf[i] = ' '; + strncpy(buf + indent, name, buf_size - indent - 1); + buf[buf_size - 1] = '\0'; + + fprintf(fp, "%-*s%-12.4g%-12.4g%-12.4g\n", buf_size, buf, power, + power / total_power, perc_dyn); + break; + case POWER_BREAKDOWN_ENTRY_TYPE_PB: + for (int i = 0; i < indent; i++) + buf[i] = ' '; + strncpy(buf + indent, name, buf_size - indent - 1); + buf[buf_size - 1] = '\0'; + + fprintf(fp, "%-*s%-12.4g%-12.4g%-12.4g%-12s\n", buf_size, buf, power, + power / total_power, perc_dyn, method); + break; + default: + break; + } +} diff --git a/vpr7_rram/vpr/SRC/power/power.h b/vpr7_rram/vpr/SRC/power/power.h new file mode 100644 index 000000000..331db2eed --- /dev/null +++ b/vpr7_rram/vpr/SRC/power/power.h @@ -0,0 +1,319 @@ +/********************************************************************* + * The following code is part of the power modelling feature of VTR. + * + * For support: + * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power + * + * or email: + * vtr.power.estimation@gmail.com + * + * If you are using power estimation for your researach please cite: + * + * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation + * for Diverse FPGA Architectures. In International Conference on + * Field Programmable Technology, 2012. + * + ********************************************************************/ + +/** + * This is the top-level file for power estimation in VTR + */ + +#ifndef __POWER_H__ +#define __POWER_H__ + +/************************* INCLUDES *********************************/ +#include + +#include "vpr_types.h" +#include "PowerSpicedComponent.h" + +/************************* DEFINES ***********************************/ +/* Maximum size of logs */ +#define MAX_LOGS 10000 + +/* Default clock behaviour */ +#define CLOCK_PROB 0.5 +#define CLOCK_DENS 2 + +/************************* ENUMS ************************************/ + +/* Return code used by power functions */ +typedef enum { + POWER_RET_CODE_SUCCESS = 0, POWER_RET_CODE_ERRORS, POWER_RET_CODE_WARNINGS +} e_power_ret_code; + +/* Power log types */ +typedef enum { + POWER_LOG_ERROR, POWER_LOG_WARNING, POWER_LOG_NUM_TYPES +} e_power_log_type; + +/* Multiplexer select encoding types */ +#if 0 +typedef enum { + ENCODING_ONE_HOT, /* One SRAM bit per mux input */ + ENCODING_DECODER /* Log2(mux_inputs) SRAM bits */ +}e_encoding_type; +#endif + +/************************* STRUCTS **********************************/ +typedef struct s_power_output t_power_output; +typedef struct s_log t_log; +typedef struct s_power_commonly_used t_power_commonly_used; +typedef struct s_power_mux_volt_inf t_power_mux_volt_inf; +typedef struct s_power_mux_volt_pair t_power_mux_volt_pair; +typedef struct s_power_nmos_leakages t_power_nmos_leakages; +typedef struct s_power_nmos_leakage_pair t_power_nmos_leakage_pair; +typedef struct s_power_buffer_sc_levr_inf t_power_buffer_sc_levr_inf; +typedef struct s_power_tech t_power_tech; +typedef struct s_transistor_inf t_transistor_inf; +typedef struct s_transistor_size_inf t_transistor_size_inf; +typedef struct s_rr_node_power t_rr_node_power; +typedef struct s_power_buffer_size_inf t_power_buffer_size_inf; +typedef struct s_power_buffer_strength_inf t_power_buffer_strength_inf; +typedef struct s_mux_node t_mux_node; +typedef struct s_mux_arch t_mux_arch; +typedef struct s_solution_inf t_solution_inf; +typedef struct s_power_nmos_mux_inf t_power_nmos_mux_inf; +typedef struct s_power_nmos_leakage_inf t_power_nmos_leakage_inf; +typedef struct s_power_mux_info t_power_mux_info; + +/* Information on the solution obtained by VPR */ +struct s_solution_inf { + float T_crit; + int channel_width; +}; + +/* two types of transisters */ +typedef enum { + NMOS, PMOS +} e_tx_type; + +/* Information for a given transistor size */ +struct s_transistor_size_inf { + float size; + + /* Subthreshold leakage, for Vds = Vdd */ + float leakage_subthreshold; + + /* Gate leakage for Vgd/Vgs = Vdd */ + float leakage_gate; + + /* Gate, Source, Drain capacitance */ + float C_g; + float C_s; + float C_d; +}; + +/** + * Transistor information + */ +struct s_transistor_inf { + int num_size_entries; + t_transistor_size_inf * size_inf; /* Array of transistor sizes */ + t_transistor_size_inf * long_trans_inf; /* Long transistor (W=1,L=2) */ +}; + +struct s_power_nmos_mux_inf { + float nmos_size; + int max_mux_sl_size; + t_power_mux_volt_inf * mux_voltage_inf; +}; + +struct s_power_nmos_leakage_inf { + float nmos_size; + int num_leakage_pairs; + t_power_nmos_leakage_pair * leakage_pairs; +}; + +/* CMOS technology properties, populated from data in xml file */ +struct s_power_tech { + float PN_ratio; /* Ratio of PMOS to NMOS in inverter */ + float Vdd; + + float tech_size; /* Tech size in nm, for example 90e-9 for 90nm */ + float temperature; /* Temp in C */ + + t_transistor_inf NMOS_inf; + t_transistor_inf PMOS_inf; + + /* Pass Multiplexor Voltage Information */ + int num_nmos_mux_info; + t_power_nmos_mux_inf * nmos_mux_info; + + /* NMOS Leakage by Vds */ + int num_nmos_leakage_info; + t_power_nmos_leakage_inf * nmos_leakage_info; + + /* Buffer Info */ + int max_buffer_size; + t_power_buffer_size_inf * buffer_size_inf; +}; + +/* Buffer information for a given size (# of stages) */ +struct s_power_buffer_size_inf { + int num_strengths; + t_power_buffer_strength_inf * strength_inf; +}; + +/* Set of I/O Voltages for a single-level multiplexer */ +struct s_power_mux_volt_inf { + int num_voltage_pairs; + t_power_mux_volt_pair * mux_voltage_pairs; +}; + +/* Single I/O voltage for a single-level multiplexer */ +struct s_power_mux_volt_pair { + float v_in; + float v_out_min; + float v_out_max; +}; + +/* Buffer information for a given buffer stength */ +struct s_power_buffer_strength_inf { + float stage_gain; + + /* Short circuit factor - no level restorer */ + float sc_no_levr; + + /* Short circuit factors - level restorers */ + int num_levr_entries; + t_power_buffer_sc_levr_inf * sc_levr_inf; +}; + +/* Buffer short-circuit information for a given input mux size */ +struct s_power_buffer_sc_levr_inf { + int mux_size; + + /* Short circuit factor */ + float sc_levr; +}; + +/* Vds/Ids subthreshold leakage pair */ +struct s_power_nmos_leakage_pair { + float v_ds; + float i_ds; +}; + +/* Output details of the power estimation */ +struct s_power_output { + FILE * out; + t_log * logs; + int num_logs; +}; + +struct s_log { + char * name; + char ** messages; + int num_messages; +}; + +struct s_power_mux_info { + /* Mux architecture information for 0..mux_arch_max_size */ + int mux_arch_max_size; + t_mux_arch * mux_arch; +}; + +/** + * Commonly used values that are cached here instead of recalculting each time, + * also includes statistics. + */ +struct s_power_commonly_used { + + /* Capacitances */ + float NMOS_1X_C_g; + float NMOS_1X_C_d; + float NMOS_1X_C_s; + + float PMOS_1X_C_g; + float PMOS_1X_C_d; + float PMOS_1X_C_s; + + float INV_1X_C_in; + float INV_1X_C; + float INV_2X_C; + + /* Component Callibrations Array [0..POWER_CALLIB_COMPONENT_MAX-1] */ + PowerSpicedComponent ** component_callibration; + + /* Subthreshold leakages */ + float NMOS_1X_st_leakage; + float NMOS_2X_st_leakage; + float PMOS_1X_st_leakage; + float PMOS_2X_st_leakage; + + std::map mux_info; + + /* Routing stats */ + int max_routing_mux_size; + int max_IPIN_fanin; + int max_seg_fanout; + int max_seg_to_IPIN_fanout; + int max_seg_to_seg_fanout; + + /* Physical length of a tile (meters) */ + float tile_length; + + /* Size of switch and connection box buffers */ + int num_sb_buffers; + float total_sb_buffer_size; + + int num_cb_buffers; + float total_cb_buffer_size; +}; + +/* 1-to-1 data structure with t_rr_node + */ +struct s_rr_node_power { + boolean visited; /* When traversing netlist, need to track whether the node has been processed */ + float * in_dens; /* Switching density of inputs */ + float * in_prob; /* Static probability of inputs */ + short num_inputs; /* Number of inputs */ + short selected_input; /* Input index that is selected */ + short driver_switch_type; /* Switch type that drives this resource */ +}; + +/* Architecture information for a multiplexer. + * This is used to specify transistor sizes, encoding, etc. + */ +struct s_mux_arch { + int levels; + int num_inputs; + float transistor_size; + //enum e_encoding_type * encoding_types; + t_mux_node * mux_graph_head; +}; + +/* A single-level multiplexer data structure. + * These are combined in a hierarchy to represent + * multi-level multiplexers + */ +struct s_mux_node { + int num_inputs; /* Number of inputs */ + t_mux_node * children; /* Multiplexers that drive the inputs [0..num_inputs-1] */ + int starting_pin_idx; /* Applicable to level 0 only, the overall mux primary input index */ + int level; /* Level in the full multilevel mux - 0 = primary inputs to mux */ + boolean level_restorer; /* Whether the output of this mux is level restored */ +}; + +/************************* GLOBALS **********************************/ +extern t_solution_inf g_solution_inf; +extern t_power_output * g_power_output; +extern t_power_commonly_used * g_power_commonly_used; +extern t_power_tech * g_power_tech; +extern t_power_arch * g_power_arch; + +/************************* FUNCTION DECLARATIONS ********************/ + +/* Call before using power module */ +boolean power_init(char * power_out_filepath, + char * cmos_tech_behavior_filepath, t_arch * arch, + t_det_routing_arch * routing_arch); + +boolean power_uninit(void); + +/* Top-Level Function */ +e_power_ret_code power_total(float * run_time_s, t_vpr_setup vpr_setup, + t_arch * arch, t_det_routing_arch * routing_arch); + +#endif /* __POWER_H__ */ diff --git a/vpr7_rram/vpr/SRC/power/power_callibrate.c b/vpr7_rram/vpr/SRC/power/power_callibrate.c new file mode 100644 index 000000000..566b98751 --- /dev/null +++ b/vpr7_rram/vpr/SRC/power/power_callibrate.c @@ -0,0 +1,402 @@ +/********************************************************************* + * The following code is part of the power modelling feature of VTR. + * + * For support: + * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power + * + * or email: + * vtr.power.estimation@gmail.com + * + * If you are using power estimation for your researach please cite: + * + * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation + * for Diverse FPGA Architectures. In International Conference on + * Field Programmable Technology, 2012. + * + ********************************************************************/ + +/* This file provides functions used to verify the power estimations + * againt SPICE. + */ + +/************************* INCLUDES *********************************/ +#include + +#include "power_callibrate.h" +#include "power_components.h" +#include "power_lowlevel.h" +#include "power_util.h" +#include "power_cmos_tech.h" +#include "globals.h" + +/************************* FUNCTION DECLARATIONS ********************/ +static char binary_not(char c); + +/************************* FUNCTION DEFINITIONS *********************/ + +/* This function prints high-activitiy and zero-activity single-cycle + * energy estimations for a variety of components and sizes. + */ +void power_print_spice_comparison(void) { +// + t_power_usage sub_power_usage; +// +// float inv_sizes[5] = { 1, 8, 16, 32, 64 }; +// +// float buffer_sizes[3] = { 16, 25, 64 }; +// + unsigned int LUT_sizes[3] = { 6 }; +// +// float sb_buffer_sizes[6] = { 9, 9, 16, 16, 25, 25 }; +// unsigned int sb_mux_sizes[6] = { 4, 8, 12, 16, 20, 25 }; +// +// unsigned int mux_sizes[5] = { 4, 8, 12, 16, 20 }; +// + unsigned int i, j; + float * dens = NULL; + float * prob = NULL; + char * SRAM_bits = NULL; + int sram_idx; +// + g_solution_inf.T_crit = 1.0e-8; +// +// +// fprintf(g_power_output->out, "Energy of INV (High Activity)\n"); +// for (i = 0; i < (sizeof(inv_sizes) / sizeof(float)); i++) { +// power_usage_inverter(&sub_power_usage, 2, 0.5, inv_sizes[i], +// power_callib_period); +// fprintf(g_power_output->out, "%g\t%g\n", inv_sizes[i], +// (sub_power_usage.dynamic + sub_power_usage.leakage) +// * g_solution_inf.T_crit); +// } +// +// fprintf(g_power_output->out, "Energy of INV (No Activity)\n"); +// for (i = 0; i < (sizeof(inv_sizes) / sizeof(float)); i++) { +// power_usage_inverter(&sub_power_usage, 0, 1, inv_sizes[i], +// power_callib_period); +// fprintf(g_power_output->out, "%g\t%g\n", inv_sizes[i], +// (sub_power_usage.dynamic + sub_power_usage.leakage) +// * g_solution_inf.T_crit); +// } +// } +// +// fprintf(g_power_output->out, "Energy of Mux (High Activity)\n"); +// for (i = 0; i < (sizeof(mux_sizes) / sizeof(int)); i++) { +// t_power_usage mux_power_usage; +// +// power_zero_usage(&mux_power_usage); +// +// dens = (float*) my_realloc(dens, mux_sizes[i] * sizeof(float)); +// prob = (float*) my_realloc(prob, mux_sizes[i] * sizeof(float)); +// for (j = 0; j < mux_sizes[i]; j++) { +// dens[j] = 2; +// prob[j] = 0.5; +// } +// power_usage_mux_multilevel(&mux_power_usage, +// power_get_mux_arch(mux_sizes[i]), prob, dens, 0, FALSE, +// power_callib_period); +// fprintf(g_power_output->out, "%d\t%g\n", mux_sizes[i], +// (mux_power_usage.dynamic + mux_power_usage.leakage) +// * g_solution_inf.T_crit); +// } +// +// fprintf(g_power_output->out, "Energy of Mux (No Activity)\n"); +// for (i = 0; i < (sizeof(mux_sizes) / sizeof(int)); i++) { +// t_power_usage mux_power_usage; +// +// power_zero_usage(&mux_power_usage); +// +// dens = (float*) my_realloc(dens, mux_sizes[i] * sizeof(float)); +// prob = (float*) my_realloc(prob, mux_sizes[i] * sizeof(float)); +// for (j = 0; j < mux_sizes[i]; j++) { +// if (j == 0) { +// dens[j] = 0; +// prob[j] = 1; +// } else { +// dens[j] = 0; +// prob[j] = 0; +// } +// } +// power_usage_mux_multilevel(&mux_power_usage, +// power_get_mux_arch(mux_sizes[i]), prob, dens, 0, FALSE, +// power_callib_period); +// fprintf(g_power_output->out, "%d\t%g\n", mux_sizes[i], +// (mux_power_usage.dynamic + mux_power_usage.leakage) +// * g_solution_inf.T_crit); +// } +// +// fprintf(g_power_output->out, "Energy of Buffer (High Activity)\n"); +// for (i = 0; i < (sizeof(buffer_sizes) / sizeof(float)); i++) { +// power_usage_buffer(&sub_power_usage, buffer_sizes[i], 0.5, 2, FALSE, +// power_callib_period); +// fprintf(g_power_output->out, "%g\t%g\n", buffer_sizes[i], +// (sub_power_usage.dynamic + sub_power_usage.leakage) +// * g_solution_inf.T_crit); +// } +// +// fprintf(g_power_output->out, "Energy of Buffer (No Activity)\n"); +// for (i = 0; i < (sizeof(buffer_sizes) / sizeof(float)); i++) { +// power_usage_buffer(&sub_power_usage, buffer_sizes[i], 1, 0, FALSE, +// power_callib_period); +// fprintf(g_power_output->out, "%g\t%g\n", buffer_sizes[i], +// (sub_power_usage.dynamic + sub_power_usage.leakage) +// * g_solution_inf.T_crit); +// } +// + fprintf(g_power_output->out, "Energy of LUT (High Activity)\n"); + for (i = 0; i < (sizeof(LUT_sizes) / sizeof(int)); i++) { + for (j = 1; j <= LUT_sizes[i]; j++) { + SRAM_bits = (char*) my_realloc(SRAM_bits, + ((1 << j) + 1) * sizeof(char)); + if (j == 1) { + SRAM_bits[0] = '1'; + SRAM_bits[1] = '0'; + } else { + for (sram_idx = 0; sram_idx < (1 << (j - 1)); sram_idx++) { + SRAM_bits[sram_idx + (1 << (j - 1))] = binary_not( + SRAM_bits[sram_idx]); + } + } + SRAM_bits[1 << j] = '\0'; + } + + dens = (float*) my_realloc(dens, LUT_sizes[i] * sizeof(float)); + prob = (float*) my_realloc(prob, LUT_sizes[i] * sizeof(float)); + for (j = 0; j < LUT_sizes[i]; j++) { + dens[j] = 1.0 / (float) LUT_sizes[i]; + prob[j] = 0.5; + } + power_usage_lut(&sub_power_usage, LUT_sizes[i], 1.0, SRAM_bits, prob, + dens, power_callib_period); + + t_power_usage power_usage_mux; + + float p[6] = { 0.5, 0.5, 0.5, 0.5, 0.5, 0.5 }; + float d[6] = { 1, 1, 1, 1, 1, 1 }; + power_usage_mux_multilevel(&power_usage_mux, power_get_mux_arch(6, 1.0), + p, d, 0, TRUE, g_solution_inf.T_crit); + + power_add_usage(&sub_power_usage, &power_usage_mux); + + fprintf(g_power_output->out, "%d\t%g\n", LUT_sizes[i], + power_sum_usage(&sub_power_usage)); + } +// +// fprintf(g_power_output->out, "Energy of LUT (No Activity)\n"); +// for (i = 0; i < (sizeof(LUT_sizes) / sizeof(int)); i++) { +// for (j = 1; j <= LUT_sizes[i]; j++) { +// SRAM_bits = (char*) my_realloc(SRAM_bits, +// ((1 << j) + 1) * sizeof(char)); +// if (j == 1) { +// SRAM_bits[0] = '1'; +// SRAM_bits[1] = '0'; +// } else { +// for (sram_idx = 0; sram_idx < (1 << (j - 1)); sram_idx++) { +// SRAM_bits[sram_idx + (1 << (j - 1))] = binary_not( +// SRAM_bits[sram_idx]); +// } +// } +// SRAM_bits[1 << j] = '\0'; +// } +// +// dens = (float*) my_realloc(dens, LUT_sizes[i] * sizeof(float)); +// prob = (float*) my_realloc(prob, LUT_sizes[i] * sizeof(float)); +// for (j = 0; j < LUT_sizes[i]; j++) { +// dens[j] = 0; +// prob[j] = 1; +// } +// power_usage_lut(&sub_power_usage, LUT_sizes[i], SRAM_bits, prob, dens, +// power_callib_period); +// fprintf(g_power_output->out, "%d\t%g\n", LUT_sizes[i], +// (sub_power_usage.dynamic + sub_power_usage.leakage) +// * g_solution_inf.T_crit * 2); +// } +// + fprintf(g_power_output->out, "Energy of FF (High Activity)\n"); + power_usage_ff(&sub_power_usage, 1.0, 0.5, 3, 0.5, 1, 0.5, 2, + power_callib_period); + fprintf(g_power_output->out, "%g\n", + (sub_power_usage.dynamic + sub_power_usage.leakage)); +// +// fprintf(g_power_output->out, "Energy of FF (No Activity)\n"); +// power_usage_ff(&sub_power_usage, 1, 0, 1, 0, 1, 0, power_callib_period); +// fprintf(g_power_output->out, "%g\n", +// (sub_power_usage.dynamic + sub_power_usage.leakage) +// * g_solution_inf.T_crit * 2); +// +// fprintf(g_power_output->out, "Energy of SB (High Activity)\n"); +// for (i = 0; i < (sizeof(sb_buffer_sizes) / sizeof(float)); i++) { +// t_power_usage sb_power_usage; +// +// power_zero_usage(&sb_power_usage); +// +// dens = (float*) my_realloc(dens, sb_mux_sizes[i] * sizeof(float)); +// prob = (float*) my_realloc(prob, sb_mux_sizes[i] * sizeof(float)); +// for (j = 0; j < sb_mux_sizes[i]; j++) { +// dens[j] = 2; +// prob[j] = 0.5; +// } +// +// power_usage_mux_multilevel(&sub_power_usage, +// power_get_mux_arch(sb_mux_sizes[i]), prob, dens, 0, TRUE, +// power_callib_period); +// power_add_usage(&sb_power_usage, &sub_power_usage); +// +// power_usage_buffer(&sub_power_usage, sb_buffer_sizes[i], 0.5, 2, TRUE, +// power_callib_period); +// power_add_usage(&sb_power_usage, &sub_power_usage); +// +// fprintf(g_power_output->out, "%d\t%.0f\t%g\n", sb_mux_sizes[i], +// sb_buffer_sizes[i], +// (sb_power_usage.dynamic + sb_power_usage.leakage) +// * g_solution_inf.T_crit); +// } +// +// fprintf(g_power_output->out, "Energy of SB (No Activity)\n"); +// for (i = 0; i < (sizeof(sb_buffer_sizes) / sizeof(float)); i++) { +// t_power_usage sb_power_usage; +// +// power_zero_usage(&sb_power_usage); +// +// dens = (float*) my_realloc(dens, sb_mux_sizes[i] * sizeof(float)); +// prob = (float*) my_realloc(prob, sb_mux_sizes[i] * sizeof(float)); +// for (j = 0; j < sb_mux_sizes[i]; j++) { +// if (j == 0) { +// dens[j] = 0; +// prob[j] = 1; +// } else { +// dens[j] = 0; +// prob[j] = 0; +// } +// } +// +// power_usage_mux_multilevel(&sub_power_usage, +// power_get_mux_arch(sb_mux_sizes[i]), prob, dens, 0, TRUE, +// power_callib_period); +// power_add_usage(&sb_power_usage, &sub_power_usage); +// +// power_usage_buffer(&sub_power_usage, sb_buffer_sizes[i], 1, 0, TRUE, +// power_callib_period); +// power_add_usage(&sb_power_usage, &sub_power_usage); +// +// fprintf(g_power_output->out, "%d\t%.0f\t%g\n", sb_mux_sizes[i], +// sb_buffer_sizes[i], +// (sb_power_usage.dynamic + sb_power_usage.leakage) +// * g_solution_inf.T_crit); +//} + +} + +static char binary_not(char c) { + if (c == '1') { + return '0'; + } else { + return '1'; + } +} + +float power_usage_buf_for_callibration(int num_inputs, float transistor_size) { + t_power_usage power_usage; + + assert(num_inputs == 1); + + power_usage_buffer(&power_usage, transistor_size, 0.5, 2.0, FALSE, + power_callib_period); + + return power_sum_usage(&power_usage); +} + +float power_usage_buf_levr_for_callibration(int num_inputs, + float transistor_size) { + t_power_usage power_usage; + + assert(num_inputs == 1); + + power_usage_buffer(&power_usage, transistor_size, 0.5, 2.0, TRUE, + power_callib_period); + + return power_sum_usage(&power_usage); +} + +float power_usage_mux_for_callibration(int num_inputs, float transistor_size) { + t_power_usage power_usage; + float * dens; + float * prob; + + dens = (float*) my_malloc(num_inputs * sizeof(float)); + prob = (float*) my_malloc(num_inputs * sizeof(float)); + for (int i = 0; i < num_inputs; i++) { + dens[i] = 2; + prob[i] = 0.5; + } + + power_usage_mux_multilevel(&power_usage, + power_get_mux_arch(num_inputs, transistor_size), prob, dens, 0, + FALSE, power_callib_period); + + free(dens); + free(prob); + + return power_sum_usage(&power_usage); +} + +float power_usage_lut_for_callibration(int num_inputs, float transistor_size) { + t_power_usage power_usage; + char * SRAM_bits; + float * dens; + float * prob; + int lut_size = num_inputs; + + /* Initialize an SRAM pattern that guarantees the outputs toggle with + * every input toggle. + */ + SRAM_bits = (char*) my_malloc(((1 << lut_size) + 1) * sizeof(char)); + for (int i = 1; i <= lut_size; i++) { + if (i == 1) { + SRAM_bits[0] = '1'; + SRAM_bits[1] = '0'; + } else { + for (int sram_idx = 0; sram_idx < (1 << (i - 1)); sram_idx++) { + SRAM_bits[sram_idx + (1 << (i - 1))] = binary_not( + SRAM_bits[sram_idx]); + } + } + SRAM_bits[1 << i] = '\0'; + } + + dens = (float*) my_malloc(lut_size * sizeof(float)); + prob = (float*) my_malloc(lut_size * sizeof(float)); + for (int i = 0; i < lut_size; i++) { + dens[i] = 1; + prob[i] = 0.5; + } + power_usage_lut(&power_usage, lut_size, transistor_size, SRAM_bits, prob, + dens, power_callib_period); + + free(SRAM_bits); + free(dens); + free(prob); + + return power_sum_usage(&power_usage); +} + +float power_usage_ff_for_callibration(int num_inputs, float transistor_size) { + t_power_usage power_usage; + + assert(num_inputs == 1); + + power_usage_ff(&power_usage, transistor_size, 0.5, 3, 0.5, 1, 0.5, 2, + power_callib_period); + + return power_sum_usage(&power_usage); +} + +void power_callibrate(void) { + /* Buffers and Mux must be done before LUT/FF */ + + g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_BUFFER]->callibrate(); + g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_BUFFER_WITH_LEVR]->callibrate(); + g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_MUX]->callibrate(); + g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_LUT]->callibrate(); + g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_FF]->callibrate(); +} diff --git a/vpr7_rram/vpr/SRC/power/power_callibrate.h b/vpr7_rram/vpr/SRC/power/power_callibrate.h new file mode 100644 index 000000000..3e6a5d1db --- /dev/null +++ b/vpr7_rram/vpr/SRC/power/power_callibrate.h @@ -0,0 +1,52 @@ +/********************************************************************* + * The following code is part of the power modelling feature of VTR. + * + * For support: + * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power + * + * or email: + * vtr.power.estimation@gmail.com + * + * If you are using power estimation for your researach please cite: + * + * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation + * for Diverse FPGA Architectures. In International Conference on + * Field Programmable Technology, 2012. + * + ********************************************************************/ + +/* This file provides functions used to verify the power estimations + * againt SPICE. + */ + +#ifndef __POWER_MISC_H__ +#define __POWER_MISC_H__ + +/************************* INCLUDES *********************************/ +#include "power.h" + +/************************* DEFINES **********************************/ +const float power_callib_period = 5e-9; + +/************************* STRUCTS **********************************/ +/************************* ENUMS ************************************/ +typedef enum { + POWER_CALLIB_COMPONENT_BUFFER = 0, + POWER_CALLIB_COMPONENT_BUFFER_WITH_LEVR, + POWER_CALLIB_COMPONENT_FF, + POWER_CALLIB_COMPONENT_MUX, + POWER_CALLIB_COMPONENT_LUT, + POWER_CALLIB_COMPONENT_MAX +} e_power_callib_component; + +/************************* FUNCTION DECLARATIONS ********************/ +void power_print_spice_comparison(void); +void power_callibrate(void); +float power_usage_buf_for_callibration(int num_inputs, float transistor_size); +float power_usage_buf_levr_for_callibration(int num_inputs, + float transistor_size); +float power_usage_mux_for_callibration(int num_inputs, float transistor_size); +float power_usage_lut_for_callibration(int num_inputs, float transistor_size); +float power_usage_ff_for_callibration(int num_inputs, float transistor_size); + +#endif diff --git a/vpr7_rram/vpr/SRC/power/power_cmos_tech.c b/vpr7_rram/vpr/SRC/power/power_cmos_tech.c new file mode 100644 index 000000000..8f87726b5 --- /dev/null +++ b/vpr7_rram/vpr/SRC/power/power_cmos_tech.c @@ -0,0 +1,899 @@ +/********************************************************************* + * The following code is part of the power modelling feature of VTR. + * + * For support: + * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power + * + * or email: + * vtr.power.estimation@gmail.com + * + * If you are using power estimation for your researach please cite: + * + * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation + * for Diverse FPGA Architectures. In International Conference on + * Field Programmable Technology, 2012. + * + ********************************************************************/ + +/** + * This file provides functions relating to the cmos technology. It + * includes functions to read the transistor characteristics from the + * xml file into data structures, and functions to search within + * these data structures. + */ + +/************************* INCLUDES *********************************/ +#include +using namespace std; + +#include + +#include "power_cmos_tech.h" +#include "power.h" +#include "power_util.h" +#include "ezxml.h" +#include "util.h" +#include "read_xml_util.h" +#include "PowerSpicedComponent.h" +#include "power_callibrate.h" + +/************************* GLOBALS **********************************/ +static t_transistor_inf * g_transistor_last_searched; +static t_power_buffer_strength_inf * g_buffer_strength_last_searched; +static t_power_mux_volt_inf * g_mux_volt_last_searched; + +/************************* FUNCTION DECLARATIONS ********************/ + +static void power_tech_load_xml_file(char * cmos_tech_behavior_filepath); +static void process_tech_xml_load_transistor_info(ezxml_t parent); +static void power_tech_xml_load_multiplexer_info(ezxml_t parent); +static void power_tech_xml_load_nmos_st_leakages(ezxml_t parent); +static int power_compare_transistor_size(const void * key_void, + const void * elem_void); +static int power_compare_voltage_pair(const void * key_void, + const void * elem_void); +static int power_compare_leakage_pair(const void * key_void, + const void * elem_void); +//static void power_tech_xml_load_sc(ezxml_t parent); +static int power_compare_buffer_strength(const void * key_void, + const void * elem_void); +static int power_compare_buffer_sc_levr(const void * key_void, + const void * elem_void); +static void power_tech_xml_load_components(ezxml_t parent); +static void power_tech_xml_load_component(ezxml_t parent, + PowerSpicedComponent ** component, char * name, + float (*usage_fn)(int num_inputs, float transistor_size)); +/************************* FUNCTION DEFINITIONS *********************/ + +void power_tech_init(char * cmos_tech_behavior_filepath) { + power_tech_load_xml_file(cmos_tech_behavior_filepath); +} + +/** + * Reads the transistor properties from the .xml file + */ +void power_tech_load_xml_file(char * cmos_tech_behavior_filepath) { + ezxml_t cur, child, prev; + const char * prop; + char msg[BUFSIZE]; + + if (!file_exists(cmos_tech_behavior_filepath)) { + /* .xml transistor characteristics is missing */ + sprintf(msg, + "The CMOS technology behavior file ('%s') does not exist. No power information will be calculated.", + cmos_tech_behavior_filepath); + power_log_msg(POWER_LOG_ERROR, msg); + + g_power_tech->NMOS_inf.num_size_entries = 0; + g_power_tech->NMOS_inf.long_trans_inf = NULL; + g_power_tech->NMOS_inf.size_inf = NULL; + + g_power_tech->PMOS_inf.num_size_entries = 0; + g_power_tech->PMOS_inf.long_trans_inf = NULL; + g_power_tech->PMOS_inf.size_inf = NULL; + + g_power_tech->Vdd = 0.; + g_power_tech->temperature = 85; + g_power_tech->PN_ratio = 1.; + return; + } + cur = ezxml_parse_file(cmos_tech_behavior_filepath); + + prop = FindProperty(cur, "file", TRUE); + ezxml_set_attr(cur, "file", NULL); + + prop = FindProperty(cur, "size", TRUE); + g_power_tech->tech_size = atof(prop); + ezxml_set_attr(cur, "size", NULL); + + child = FindElement(cur, "operating_point", TRUE); + g_power_tech->temperature = GetFloatProperty(child, "temperature", TRUE, 0); + g_power_tech->Vdd = GetFloatProperty(child, "Vdd", TRUE, 0); + FreeNode(child); + + child = FindElement(cur, "p_to_n", TRUE); + g_power_tech->PN_ratio = GetFloatProperty(child, "ratio", TRUE, 0); + FreeNode(child); + + /* Transistor Information */ + child = FindFirstElement(cur, "transistor", TRUE); + process_tech_xml_load_transistor_info(child); + + prev = child; + child = child->next; + FreeNode(prev); + + process_tech_xml_load_transistor_info(child); + FreeNode(child); + + /* Multiplexer Voltage Information */ + child = FindElement(cur, "multiplexers", TRUE); + power_tech_xml_load_multiplexer_info(child); + FreeNode(child); + + /* Vds Leakage Information */ + child = FindElement(cur, "nmos_leakages", TRUE); + power_tech_xml_load_nmos_st_leakages(child); + FreeNode(child); + + /* Buffer SC Info */ + /* + child = FindElement(cur, "buffer_sc", TRUE); + power_tech_xml_load_sc(child); + FreeNode(child); + */ + + /* Components */ + child = FindElement(cur, "components", TRUE); + power_tech_xml_load_components(child); + FreeNode(child); + + FreeNode(cur); +} + +static void power_tech_xml_load_component(ezxml_t parent, + PowerSpicedComponent ** component, char * name, + float (*usage_fn)(int num_inputs, float transistor_size)) { + ezxml_t cur, child, gc, prev; + + *component = new PowerSpicedComponent(usage_fn); + + cur = FindElement(parent, name, TRUE); + + child = FindFirstElement(cur, "inputs", TRUE); + while (child) { + int num_inputs = GetIntProperty(child, "num_inputs", TRUE, 0); + + gc = FindFirstElement(child, "size", TRUE); + while (gc) { + float transistor_size = GetFloatProperty(gc, "transistor_size", + TRUE, 0.); + float power = GetFloatProperty(gc, "power", TRUE, 0.); + (*component)->add_data_point(num_inputs, transistor_size, power); + + prev = gc; + gc = gc->next; + FreeNode(prev); + } + prev = child; + child = child->next; + FreeNode(prev); + } + FreeNode(cur); +} + +static void power_tech_xml_load_components(ezxml_t parent) { + + g_power_commonly_used->component_callibration = + (PowerSpicedComponent**) my_calloc(POWER_CALLIB_COMPONENT_MAX, + sizeof(PowerSpicedComponent*)); + + power_tech_xml_load_component(parent, + &g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_BUFFER], + "buf", power_usage_buf_for_callibration); + + power_tech_xml_load_component(parent, + &g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_BUFFER_WITH_LEVR], + "buf_levr", power_usage_buf_levr_for_callibration); + + power_tech_xml_load_component(parent, + &g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_FF], + "dff", power_usage_ff_for_callibration); + + power_tech_xml_load_component(parent, + &g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_MUX], + "mux", power_usage_mux_for_callibration); + + power_tech_xml_load_component(parent, + &g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_LUT], + "lut", power_usage_lut_for_callibration); + +} + +/** + * Read short-circuit buffer information from the transistor .xml file. + * This contains values for buffers of various 1) # Stages 2) Stage strength 3) Input type & capacitance + */ +#if 0 +static void power_tech_xml_load_sc(ezxml_t parent) { + ezxml_t child, prev, gc, ggc; + int i, j, k; + int num_buffer_sizes; + + /* Information for buffers, based on # of stages in buffer */ + num_buffer_sizes = CountChildren(parent, "stages", 1); + g_power_tech->max_buffer_size = num_buffer_sizes; /* buffer size starts at 1, not 0 */ + g_power_tech->buffer_size_inf = (t_power_buffer_size_inf*) my_calloc( + g_power_tech->max_buffer_size + 1, sizeof(t_power_buffer_size_inf)); + + child = FindFirstElement(parent, "stages", TRUE); + i = 1; + while (child) { + t_power_buffer_size_inf * size_inf = &g_power_tech->buffer_size_inf[i]; + + GetIntProperty(child, "num_stages", TRUE, 1); + + /* For the given # of stages, find the records for the strength of each stage */ + size_inf->num_strengths = CountChildren(child, "strength", 1); + size_inf->strength_inf = (t_power_buffer_strength_inf*) my_calloc( + size_inf->num_strengths, sizeof(t_power_buffer_strength_inf)); + + gc = FindFirstElement(child, "strength", TRUE); + j = 0; + while (gc) { + t_power_buffer_strength_inf * strength_inf = + &size_inf->strength_inf[j]; + + /* Get the short circuit factor for a buffer with no level restorer at the input */ + strength_inf->stage_gain = GetFloatProperty(gc, "gain", TRUE, 0.0); + strength_inf->sc_no_levr = GetFloatProperty(gc, "sc_nolevr", TRUE, + 0.0); + + /* Get the short circuit factor for buffers with level restorers at the input */ + strength_inf->num_levr_entries = CountChildren(gc, "input_cap", 1); + strength_inf->sc_levr_inf = (t_power_buffer_sc_levr_inf*) my_calloc( + strength_inf->num_levr_entries, + sizeof(t_power_buffer_sc_levr_inf)); + + ggc = FindFirstElement(gc, "input_cap", TRUE); + k = 0; + while (ggc) { + t_power_buffer_sc_levr_inf * levr_inf = + &strength_inf->sc_levr_inf[k]; + + /* Short circuit factor is depdent on size of mux that drives the buffer */ + levr_inf->mux_size = GetIntProperty(ggc, "mux_size", TRUE, 0); + levr_inf->sc_levr = GetFloatProperty(ggc, "sc_levr", TRUE, 0.0); + + prev = ggc; + ggc = ggc->next; + FreeNode(prev); + k++; + } + + prev = gc; + gc = gc->next; + FreeNode(prev); + j++; + } + + prev = child; + child = child->next; + FreeNode(prev); + i++; + } +} +#endif + +/** + * Read NMOS subthreshold leakage currents from the .xml transistor characteristics + * This builds a table of (Vds,Ids) value pairs + * */ +static void power_tech_xml_load_nmos_st_leakages(ezxml_t parent) { + ezxml_t me, child, prev; + int num_nmos_sizes; + int num_leakage_pairs; + int i; + int nmos_idx; + + num_nmos_sizes = CountChildren(parent, "nmos", 1); + g_power_tech->num_nmos_leakage_info = num_nmos_sizes; + g_power_tech->nmos_leakage_info = (t_power_nmos_leakage_inf*) my_calloc( + num_nmos_sizes, sizeof(t_power_nmos_leakage_inf)); + + me = FindFirstElement(parent, "nmos", TRUE); + nmos_idx = 0; + while (me) { + t_power_nmos_leakage_inf * nmos_info = + &g_power_tech->nmos_leakage_info[nmos_idx]; + nmos_info->nmos_size = GetFloatProperty(me, "size", TRUE, 0.); + + num_leakage_pairs = CountChildren(me, "nmos_leakage", 1); + nmos_info->num_leakage_pairs = num_leakage_pairs; + nmos_info->leakage_pairs = (t_power_nmos_leakage_pair*) my_calloc( + num_leakage_pairs, sizeof(t_power_nmos_leakage_pair)); + + child = FindFirstElement(me, "nmos_leakage", TRUE); + i = 0; + while (child) { + nmos_info->leakage_pairs[i].v_ds = GetFloatProperty(child, "Vds", + TRUE, 0.0); + nmos_info->leakage_pairs[i].i_ds = GetFloatProperty(child, "Ids", + TRUE, 0.0); + + prev = child; + child = child->next; + FreeNode(prev); + i++; + } + + prev = me; + me = me->next; + FreeNode(prev); + nmos_idx++; + } + +} + +/** + * Read multiplexer information from the .xml transistor characteristics. + * This contains the estimates of mux output voltages, depending on 1) Mux Size 2) Mux Vin + * */ +static void power_tech_xml_load_multiplexer_info(ezxml_t parent) { + ezxml_t me, child, prev, gc; + int num_nmos_sizes; + int num_mux_sizes; + int i, j, nmos_idx; + + /* Process all nmos sizes */ + num_nmos_sizes = CountChildren(parent, "nmos", 1); + g_power_tech->num_nmos_mux_info = num_nmos_sizes; + g_power_tech->nmos_mux_info = (t_power_nmos_mux_inf*) my_calloc( + num_nmos_sizes, sizeof(t_power_nmos_mux_inf)); + + me = FindFirstElement(parent, "nmos", TRUE); + nmos_idx = 0; + while (me) { + t_power_nmos_mux_inf * nmos_inf = &g_power_tech->nmos_mux_info[nmos_idx]; + nmos_inf->nmos_size = GetFloatProperty(me, "size", TRUE, 0.0); +// ezxml_set_attr(me, "size", NULL); + + /* Process all multiplexer sizes */ + num_mux_sizes = CountChildren(me, "multiplexer", 1); + + /* Add entries for 0 and 1, for convenience, although + * they will never be used + */ + nmos_inf->max_mux_sl_size = 1 + num_mux_sizes; + nmos_inf->mux_voltage_inf = (t_power_mux_volt_inf*) my_calloc( + nmos_inf->max_mux_sl_size + 1, sizeof(t_power_mux_volt_inf)); + + child = FindFirstElement(me, "multiplexer", TRUE); + i = 1; + while (child) { + int num_voltages; + + assert(i == GetFloatProperty(child, "size", TRUE, 0)); + + /* For each mux size, process all of the Vin levels */ + num_voltages = CountChildren(child, "voltages", 1); + + nmos_inf->mux_voltage_inf[i].num_voltage_pairs = num_voltages; + nmos_inf->mux_voltage_inf[i].mux_voltage_pairs = + (t_power_mux_volt_pair*) my_calloc(num_voltages, + sizeof(t_power_mux_volt_pair)); + + gc = FindFirstElement(child, "voltages", TRUE); + j = 0; + while (gc) { + /* For each mux size, and Vin level, get the min/max V_out */ + nmos_inf->mux_voltage_inf[i].mux_voltage_pairs[j].v_in = + GetFloatProperty(gc, "in", TRUE, 0.0); + nmos_inf->mux_voltage_inf[i].mux_voltage_pairs[j].v_out_min = + GetFloatProperty(gc, "out_min", TRUE, 0.0); + nmos_inf->mux_voltage_inf[i].mux_voltage_pairs[j].v_out_max = + GetFloatProperty(gc, "out_max", TRUE, 0.0); + + prev = gc; + gc = gc->next; + FreeNode(prev); + j++; + } + + prev = child; + child = child->next; + FreeNode(prev); + i++; + } + + prev = me; + me = me->next; + FreeNode(prev); + nmos_idx++; + } + +} + +/** + * Read the transistor information from the .xml transistor characteristics. + * For each transistor size, it extracts the: + * - transistor node capacitances + * - subthreshold leakage + * - gate leakage + */ +static void process_tech_xml_load_transistor_info(ezxml_t parent) { + t_transistor_inf * trans_inf; + const char * prop; + ezxml_t child, prev, grandchild; + int i; + + /* Get transistor type: NMOS or PMOS */ + prop = FindProperty(parent, "type", TRUE); + trans_inf = NULL; + if (strcmp(prop, "nmos") == 0) { + trans_inf = &g_power_tech->NMOS_inf; + } else if (strcmp(prop, "pmos") == 0) { + trans_inf = &g_power_tech->PMOS_inf; + } else { + assert(0); + } + ezxml_set_attr(parent, "type", NULL); + + /* Get long transistor information (W=1,L=2) */ + trans_inf->long_trans_inf = (t_transistor_size_inf*) my_malloc( + sizeof(t_transistor_size_inf)); + + child = FindElement(parent, "long_size", TRUE); + assert(GetIntProperty(child, "L", TRUE, 0) == 2); + trans_inf->long_trans_inf->size = GetFloatProperty(child, "W", TRUE, 0); + + grandchild = FindElement(child, "leakage_current", TRUE); + trans_inf->long_trans_inf->leakage_subthreshold = GetFloatProperty( + grandchild, "subthreshold", TRUE, 0); + FreeNode(grandchild); + + grandchild = FindElement(child, "capacitance", TRUE); + trans_inf->long_trans_inf->C_g = GetFloatProperty(grandchild, "C_g", TRUE, + 0); + trans_inf->long_trans_inf->C_d = GetFloatProperty(grandchild, "C_d", TRUE, + 0); + trans_inf->long_trans_inf->C_s = GetFloatProperty(grandchild, "C_s", TRUE, + 0); + FreeNode(grandchild); + + /* Process all transistor sizes */ + trans_inf->num_size_entries = CountChildren(parent, "size", 1); + trans_inf->size_inf = (t_transistor_size_inf*) my_calloc( + trans_inf->num_size_entries, sizeof(t_transistor_size_inf)); + FreeNode(child); + + child = FindFirstElement(parent, "size", TRUE); + i = 0; + while (child) { + assert(GetIntProperty(child, "L", TRUE, 0) == 1); + + trans_inf->size_inf[i].size = GetFloatProperty(child, "W", TRUE, 0); + + /* Get leakage currents */ + grandchild = FindElement(child, "leakage_current", TRUE); + trans_inf->size_inf[i].leakage_subthreshold = GetFloatProperty( + grandchild, "subthreshold", TRUE, 0); + trans_inf->size_inf[i].leakage_gate = GetFloatProperty(grandchild, + "gate", TRUE, 0); + FreeNode(grandchild); + + /* Get node capacitances */ + grandchild = FindElement(child, "capacitance", TRUE); + trans_inf->size_inf[i].C_g = GetFloatProperty(grandchild, "C_g", TRUE, + 0); + trans_inf->size_inf[i].C_s = GetFloatProperty(grandchild, "C_s", TRUE, + 0); + trans_inf->size_inf[i].C_d = GetFloatProperty(grandchild, "C_d", TRUE, + 0); + FreeNode(grandchild); + + prev = child; + child = child->next; + FreeNode(prev); + i++; + } +} + +/** + * This function searches for a transistor by size + * - lower: (Return value) The lower-bound matching transistor + * - upper: (Return value) The upper-bound matching transistor + * - type: The transistor type to search for + * - size: The transistor size to search for (size = W/L) + */ +boolean power_find_transistor_info(t_transistor_size_inf ** lower, + t_transistor_size_inf ** upper, e_tx_type type, float size) { + char msg[1024]; + t_transistor_size_inf key; + t_transistor_size_inf * found; + t_transistor_inf * trans_info; + float min_size, max_size; + boolean error = FALSE; + + key.size = size; + + /* Find the appropriate global transistor records */ + trans_info = NULL; + if (type == NMOS) { + trans_info = &g_power_tech->NMOS_inf; + } else if (type == PMOS) { + trans_info = &g_power_tech->PMOS_inf; + } else { + assert(0); + } + + /* No transistor data exists */ + if (trans_info->size_inf == NULL) { + power_log_msg(POWER_LOG_ERROR, + "No transistor information exists. Cannot determine transistor properties."); + error = TRUE; + return error; + } + + /* Make note of the transistor record we are searching in, and the bounds */ + g_transistor_last_searched = trans_info; + min_size = trans_info->size_inf[0].size; + max_size = trans_info->size_inf[trans_info->num_size_entries - 1].size; + + found = (t_transistor_size_inf*) bsearch(&key, trans_info->size_inf, + trans_info->num_size_entries, sizeof(t_transistor_size_inf), + &power_compare_transistor_size); + assert(found); + + if (size < min_size) { + /* Too small */ + assert(found == &trans_info->size_inf[0]); + sprintf(msg, + "Using %s transistor of size '%f', which is smaller than the smallest modeled transistor (%f) in the technology behavior file.", + transistor_type_name(type), size, min_size); + power_log_msg(POWER_LOG_WARNING, msg); + *lower = NULL; + *upper = found; + } else if (size > max_size) { + /* Too large */ + assert( + found + == &trans_info->size_inf[trans_info->num_size_entries + - 1]); + sprintf(msg, + "Using %s transistor of size '%f', which is larger than the largest modeled transistor (%f) in the technology behavior file.", + transistor_type_name(type), size, max_size); + power_log_msg(POWER_LOG_WARNING, msg); + *lower = found; + *upper = NULL; + } else { + *lower = found; + *upper = found + 1; + } + + return error; +} + +/** + * This function searches for the Ids leakage current, based on a given Vds. + * This function is used for minimum-sized NMOS transistors (used in muxs). + * - lower: (Return value) The lower-bound matching V/I pair + * - upper: (Return value) The upper-bound matching V/I pair + * - v_ds: The drain/source voltage to search for + */ +t_power_nmos_leakage_inf * g_power_searching_nmos_leakage_info; +void power_find_nmos_leakage(t_power_nmos_leakage_inf * nmos_leakage_info, + t_power_nmos_leakage_pair ** lower, t_power_nmos_leakage_pair ** upper, + float v_ds) { + t_power_nmos_leakage_pair key; + t_power_nmos_leakage_pair * found; + + key.v_ds = v_ds; + + g_power_searching_nmos_leakage_info = nmos_leakage_info; + + found = (t_power_nmos_leakage_pair*) bsearch(&key, + nmos_leakage_info->leakage_pairs, + nmos_leakage_info->num_leakage_pairs, + sizeof(t_power_nmos_leakage_pair), power_compare_leakage_pair); + assert(found); + + if (found + == &nmos_leakage_info->leakage_pairs[nmos_leakage_info->num_leakage_pairs + - 1]) { + /* The results equal to the max voltage (Vdd) */ + *lower = found; + *upper = NULL; + } else { + *lower = found; + *upper = found + 1; + } +} + +/** + * This function searches for the information for a given buffer strength. + * - lower: (Return value) The lower-bound matching record + * - upper: (Return value) The upper-bound matching record + * - stage_gain: The buffer strength to search for + */ +void power_find_buffer_strength_inf(t_power_buffer_strength_inf ** lower, + t_power_buffer_strength_inf ** upper, + t_power_buffer_size_inf * size_inf, float stage_gain) { + t_power_buffer_strength_inf key; + t_power_buffer_strength_inf * found; + + float min_size; + float max_size; + + min_size = size_inf->strength_inf[0].stage_gain; + max_size = size_inf->strength_inf[size_inf->num_strengths - 1].stage_gain; + + assert(stage_gain >= min_size && stage_gain <= max_size); + + key.stage_gain = stage_gain; + + found = (t_power_buffer_strength_inf*) bsearch(&key, size_inf->strength_inf, + size_inf->num_strengths, sizeof(t_power_buffer_strength_inf), + power_compare_buffer_strength); + + if (stage_gain == max_size) { + *lower = found; + *upper = NULL; + } else { + *lower = found; + *upper = found + 1; + } +} + +/** + * This function searches for short-circuit current information for a level-restoring buffer, + * based on the size of the multiplexer driving the input + * - lower: (Return value) The lower-bound matching record + * - upper: (Return value) The upper-bound matching record + * - buffer_strength: The set of records to search withing, which are for a specific buffer size/strength + * - input_mux_size: The input mux size to search for + */ +void power_find_buffer_sc_levr(t_power_buffer_sc_levr_inf ** lower, + t_power_buffer_sc_levr_inf ** upper, + t_power_buffer_strength_inf * buffer_strength, int input_mux_size) { + t_power_buffer_sc_levr_inf key; + t_power_buffer_sc_levr_inf * found; + char msg[1024]; + int max_size; + + assert(input_mux_size >= 1); + + key.mux_size = input_mux_size; + + g_buffer_strength_last_searched = buffer_strength; + found = (t_power_buffer_sc_levr_inf*) bsearch(&key, + buffer_strength->sc_levr_inf, buffer_strength->num_levr_entries, + sizeof(t_power_buffer_sc_levr_inf), power_compare_buffer_sc_levr); + + max_size = buffer_strength->sc_levr_inf[buffer_strength->num_levr_entries + - 1].mux_size; + if (input_mux_size > max_size) { + /* Input mux too large */ + assert( + found + == &buffer_strength->sc_levr_inf[buffer_strength->num_levr_entries + - 1]); + sprintf(msg, + "Using buffer driven by mux of size '%d', which is larger than the largest modeled size (%d) in the technology behavior file.", + input_mux_size, max_size); + power_log_msg(POWER_LOG_WARNING, msg); + *lower = found; + *upper = NULL; + } else { + *lower = found; + *upper = found + 1; + } +} + +/** + * Comparison function, used by power_find_nmos_leakage + */ +static int power_compare_leakage_pair(const void * key_void, + const void * elem_void) { + const t_power_nmos_leakage_pair * key = + (const t_power_nmos_leakage_pair*) key_void; + const t_power_nmos_leakage_pair * elem = + (const t_power_nmos_leakage_pair*) elem_void; + const t_power_nmos_leakage_pair * next = + (const t_power_nmos_leakage_pair*) elem + 1; + + /* Compare against last? */ + if (elem + == &g_power_searching_nmos_leakage_info->leakage_pairs[g_power_searching_nmos_leakage_info->num_leakage_pairs + - 1]) { + if (key->v_ds >= elem->v_ds) { + return 0; + } else { + return -1; + } + } + + /* Check for exact match to Vdd (upper end) */ + if (key->v_ds == elem->v_ds) { + return 0; + } else if (key->v_ds < elem->v_ds) { + return -1; + } else if (key->v_ds > next->v_ds) { + return 1; + } else { + return 0; + } +} + +/** + * This function searches for multiplexer output voltage information, based on input voltage + * - lower: (Return value) The lower-bound matching record + * - upper: (Return value) The upper-bound matching record + * - volt_inf: The set of records to search within, which are for a specific mux size + * - v_in: The input voltage to search for + */ +void power_find_mux_volt_inf(t_power_mux_volt_pair ** lower, + t_power_mux_volt_pair ** upper, t_power_mux_volt_inf * volt_inf, + float v_in) { + t_power_mux_volt_pair key; + t_power_mux_volt_pair * found; + + key.v_in = v_in; + + g_mux_volt_last_searched = volt_inf; + found = (t_power_mux_volt_pair*) bsearch(&key, volt_inf->mux_voltage_pairs, + volt_inf->num_voltage_pairs, sizeof(t_power_mux_volt_pair), + power_compare_voltage_pair); + assert(found); + + if (found + == &volt_inf->mux_voltage_pairs[volt_inf->num_voltage_pairs - 1]) { + *lower = found; + *upper = NULL; + } else { + *lower = found; + *upper = found + 1; + } +} + +/** + * Comparison function, used by power_find_buffer_sc_levr + */ +static int power_compare_buffer_sc_levr(const void * key_void, + const void * elem_void) { + const t_power_buffer_sc_levr_inf * key = + (const t_power_buffer_sc_levr_inf*) key_void; + const t_power_buffer_sc_levr_inf * elem = + (const t_power_buffer_sc_levr_inf*) elem_void; + const t_power_buffer_sc_levr_inf * next; + + /* Compare against last? */ + if (elem + == &g_buffer_strength_last_searched->sc_levr_inf[g_buffer_strength_last_searched->num_levr_entries + - 1]) { + if (key->mux_size >= elem->mux_size) { + return 0; + } else { + return -1; + } + } + + /* Compare against first? */ + if (elem == &g_buffer_strength_last_searched->sc_levr_inf[0]) { + if (key->mux_size < elem->mux_size) { + return 0; + } + } + + /* Check if the key is between elem and the next element */ + next = elem + 1; + if (key->mux_size > next->mux_size) { + return 1; + } else if (key->mux_size < elem->mux_size) { + return -1; + } else { + return 0; + } +} + +/** + * Comparison function, used by power_find_buffer_strength_inf + */ +static int power_compare_buffer_strength(const void * key_void, + const void * elem_void) { + const t_power_buffer_strength_inf * key = + (const t_power_buffer_strength_inf*) key_void; + const t_power_buffer_strength_inf * elem = + (const t_power_buffer_strength_inf*) elem_void; + const t_power_buffer_strength_inf * next = + (const t_power_buffer_strength_inf*) elem + 1; + + /* Check for exact match */ + if (key->stage_gain == elem->stage_gain) { + return 0; + } else if (key->stage_gain < elem->stage_gain) { + return -1; + } else if (key->stage_gain > next->stage_gain) { + return 1; + } else { + return 0; + } +} + +/** + * Comparison function, used by power_find_transistor_info + */ +static int power_compare_transistor_size(const void * key_void, + const void * elem_void) { + const t_transistor_size_inf * key = (const t_transistor_size_inf*) key_void; + const t_transistor_size_inf * elem = + (const t_transistor_size_inf*) elem_void; + const t_transistor_size_inf * next; + + /* Check if we are comparing against the last element */ + if (elem + == &g_transistor_last_searched->size_inf[g_transistor_last_searched->num_size_entries + - 1]) { + /* Match if the desired value is larger than the largest item in the list */ + if (key->size >= elem->size) { + return 0; + } else { + return -1; + } + } + + /* Check if we are comparing against the first element */ + if (elem == &g_transistor_last_searched->size_inf[0]) { + /* Match the smallest if it is smaller than the smallest */ + if (key->size < elem->size) { + return 0; + } + } + + /* Check if the key is between elem and the next element */ + next = elem + 1; + if (key->size > next->size) { + return 1; + } else if (key->size < elem->size) { + return -1; + } else { + return 0; + } + +} + +/** + * Comparison function, used by power_find_mux_volt_inf + */ +static int power_compare_voltage_pair(const void * key_void, + const void * elem_void) { + const t_power_mux_volt_pair * key = (const t_power_mux_volt_pair *) key_void; + const t_power_mux_volt_pair * elem = + (const t_power_mux_volt_pair *) elem_void; + const t_power_mux_volt_pair * next = (const t_power_mux_volt_pair *) elem + + 1; + + /* Check if we are comparing against the last element */ + if (elem + == &g_mux_volt_last_searched->mux_voltage_pairs[g_mux_volt_last_searched->num_voltage_pairs + - 1]) { + /* Match if the desired value is larger than the largest item in the list */ + if (key->v_in >= elem->v_in) { + return 0; + } else { + return -1; + } + } + + /* Check for exact match to Vdd (upper end) */ + if (key->v_in == elem->v_in) { + return 0; + } else if (key->v_in < elem->v_in) { + return -1; + } else if (key->v_in > next->v_in) { + return 1; + } else { + return 0; + } +} + diff --git a/vpr7_rram/vpr/SRC/power/power_cmos_tech.h b/vpr7_rram/vpr/SRC/power/power_cmos_tech.h new file mode 100644 index 000000000..383d52e5c --- /dev/null +++ b/vpr7_rram/vpr/SRC/power/power_cmos_tech.h @@ -0,0 +1,47 @@ +/********************************************************************* + * The following code is part of the power modelling feature of VTR. + * + * For support: + * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power + * + * or email: + * vtr.power.estimation@gmail.com + * + * If you are using power estimation for your researach please cite: + * + * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation + * for Diverse FPGA Architectures. In International Conference on + * Field Programmable Technology, 2012. + * + ********************************************************************/ + +/** + * This file provides functions relating to the cmos technology. It + * includes functions to read the transistor characteristics from the + * xml file into data structures, and functions to search within + * these data structures. + */ + +#ifndef __POWER_CMOS_TECH_H__ +#define __POWER_CMOS_TECH_H__ + +/************************* INCLUDES *********************************/ +#include "power.h" + +/************************* FUNCTION DECLARATIONS ********************/ +void power_tech_init(char * cmos_tech_behavior_filepath); +boolean power_find_transistor_info(t_transistor_size_inf ** lower, + t_transistor_size_inf ** upper, e_tx_type type, float size); +void power_find_mux_volt_inf(t_power_mux_volt_pair ** lower, + t_power_mux_volt_pair ** upper, t_power_mux_volt_inf * volt_inf, + float v_in); +void power_find_nmos_leakage(t_power_nmos_leakage_inf * nmos_leakage_info, + t_power_nmos_leakage_pair ** lower, t_power_nmos_leakage_pair ** upper, + float v_ds); +void power_find_buffer_strength_inf(t_power_buffer_strength_inf ** lower, + t_power_buffer_strength_inf ** upper, + t_power_buffer_size_inf * size_inf, float stage_gain); +void power_find_buffer_sc_levr(t_power_buffer_sc_levr_inf ** lower, + t_power_buffer_sc_levr_inf ** upper, + t_power_buffer_strength_inf * buffer_sc, int input_mux_size); +#endif diff --git a/vpr7_rram/vpr/SRC/power/power_components.c b/vpr7_rram/vpr/SRC/power/power_components.c new file mode 100644 index 000000000..06f44b1e7 --- /dev/null +++ b/vpr7_rram/vpr/SRC/power/power_components.c @@ -0,0 +1,697 @@ +/********************************************************************* + * The following code is part of the power modelling feature of VTR. + * + * For support: + * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power + * + * or email: + * vtr.power.estimation@gmail.com + * + * If you are using power estimation for your researach please cite: + * + * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation + * for Diverse FPGA Architectures. In International Conference on + * Field Programmable Technology, 2012. + * + ********************************************************************/ + +/** + * This file offers functions to estimate power of major components + * within the FPGA (flip-flops, LUTs, interconnect structures, etc). + */ + +/************************* INCLUDES *********************************/ +#include +using namespace std; + +#include + +#include "power_components.h" +#include "power_lowlevel.h" +#include "power_util.h" +#include "power_callibrate.h" +#include "globals.h" + +/************************* STRUCTS **********************************/ + +/************************* GLOBALS **********************************/ +t_power_components g_power_by_component; + +/************************* FUNCTION DECLARATIONS ********************/ +static void power_usage_mux_rec(t_power_usage * power_usage, float * out_prob, + float * out_dens, float * v_out, t_mux_node * mux_node, + t_mux_arch * mux_arch, int * selector_values, + float * primary_input_prob, float * primary_input_dens, + boolean v_out_restored, float period); + +/************************* FUNCTION DEFINITIONS *********************/ + +/** + * Module initializer function, called by power_init + */ +void power_components_init(void) { + int i; + + g_power_by_component.components = (t_power_usage*) my_calloc( + POWER_COMPONENT_MAX_NUM, sizeof(t_power_usage)); + for (i = 0; i < POWER_COMPONENT_MAX_NUM; i++) { + power_zero_usage(&g_power_by_component.components[i]); + } +} + +/** + * Module un-initializer function, called by power_uninit + */ +void power_components_uninit(void) { + free(g_power_by_component.components); +} + +/** + * Adds power usage for a component to the global component tracker + * - power_usage: Power usage to add + * - component_idx: Type of component + */ +void power_component_add_usage(t_power_usage * power_usage, + e_power_component_type component_idx) { + power_add_usage(&g_power_by_component.components[component_idx], + power_usage); +} + +/** + * Gets power usage for a component + * - power_usage: (Return value) Power usage for the given component + * - component_idx: Type of component + */ +void power_component_get_usage(t_power_usage * power_usage, + e_power_component_type component_idx) { + memcpy(power_usage, &g_power_by_component.components[component_idx], + sizeof(t_power_usage)); +} + +/** + * Returns total power for a given component + * - component_idx: Type of component + */ +float power_component_get_usage_sum(e_power_component_type component_idx) { + return power_sum_usage(&g_power_by_component.components[component_idx]); +} + +/** + * Calculates power of a D flip-flop + * - power_usage: (Return value) power usage of the flip-flop + * - D_prob: Signal probability of the input + * - D_dens: Transition density of the input + * - Q_prob: Signal probability of the output + * - Q_dens: Transition density of the output + * - clk_prob: Signal probability of the clock + * - clk_dens: Transition density of the clock + */ +void power_usage_ff(t_power_usage * power_usage, float size, float D_prob, + float D_dens, float Q_prob, float Q_dens, float clk_prob, + float clk_dens, float period) { + t_power_usage sub_power_usage; + float mux_in_dens[2]; + float mux_in_prob[2]; + PowerSpicedComponent * callibration; + float scale_factor; + + power_zero_usage(power_usage); + + /* DFF is build using a master loop and slave loop. + * Each loop begins with a MUX and contains 2 inverters + * in a feedback loop to the mux. + * Each mux is built using two transmission gates. + */ + + /* Master */ + mux_in_dens[0] = D_dens; + mux_in_dens[1] = (1 - clk_prob) * D_dens; + mux_in_prob[0] = D_prob; + mux_in_prob[1] = D_prob; + power_usage_MUX2_transmission(&sub_power_usage, size, mux_in_dens, + mux_in_prob, clk_dens, (1 - clk_prob) * D_dens, period); + power_add_usage(power_usage, &sub_power_usage); + + power_usage_inverter(&sub_power_usage, (1 - clk_prob) * D_dens, D_prob, + size, period); + power_add_usage(power_usage, &sub_power_usage); + + power_usage_inverter(&sub_power_usage, (1 - clk_prob) * D_dens, 1 - D_prob, + size, period); + power_add_usage(power_usage, &sub_power_usage); + + /* Slave */ + mux_in_dens[0] = Q_dens; + mux_in_dens[1] = (1 - clk_prob) * D_dens; + mux_in_prob[0] = (1 - Q_prob); + mux_in_prob[1] = (1 - D_prob); + power_usage_MUX2_transmission(&sub_power_usage, size, mux_in_dens, + mux_in_prob, clk_dens, Q_dens, period); + power_add_usage(power_usage, &sub_power_usage); + + power_usage_inverter(&sub_power_usage, Q_dens, 1 - Q_prob, size, period); + power_add_usage(power_usage, &sub_power_usage); + + power_usage_inverter(&sub_power_usage, Q_dens, Q_prob, size, period); + power_add_usage(power_usage, &sub_power_usage); + + /* Callibration */ + callibration = + g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_FF]; + if (callibration->is_done_callibration()) { + scale_factor = callibration->scale_factor(1, size); + power_scale_usage(power_usage, scale_factor); + } + + return; +} + +/** + * Calculated power of a look-up table (LUT) + * - power_usage: (Return value) The power usage of the LUT + * - LUT_size: Number of LUT inputs + * - SRAM_values: The 2^(LUT_size) truth table values. String of '0' and '1' characters. + * First characters is for all inputs = 0 and last characters is for all inputs = 1. + * - input_prob: Array of input signal probabilities + * - input_dens: Array of input transition densities + * + * NOTE: The following provides a diagram of a 3-LUT, the sram bit ordering, and + * the input array ordering. + * + * X - NMOS gate controlled by complement of input + * Z - NMOS gate controlled by input + * + * S + * R I I I + * A N N N + * M 2 1 0 + * | | | | + * v v | | + * v | + * 0 _X_ | + * |_X_ v + * 1 _Z_| | + * |_X_ + * 2 _X_ | | + * |_Z_| | + * 3 _Z_| | + * |------ out + * 4 _X_ | + * |_X_ | + * 5 _Z_| | | + * |_Z_| + * 6 _X_ | + * |_Z_| + * 7 _Z_| + * + */ +void power_usage_lut(t_power_usage * power_usage, int lut_size, + float transistor_size, char * SRAM_values, float * input_prob, + float * input_dens, float period) { + float **internal_prob; + float **internal_dens; + float **internal_v; + int i; + int level_idx; + PowerSpicedComponent * callibration; + float scale_factor; + + int num_SRAM_bits; + + boolean level_restorer_this_level = FALSE; + + power_zero_usage(power_usage); + + num_SRAM_bits = 1 << lut_size; + + /* Initialize internal node data */ + internal_prob = (float**) my_calloc(lut_size + 1, sizeof(float*)); + internal_dens = (float**) my_calloc(lut_size + 1, sizeof(float*)); + internal_v = (float**) my_calloc(lut_size + 1, sizeof(float*)); + for (i = 0; i <= lut_size; i++) { + internal_prob[i] = (float*) my_calloc(1 << (lut_size - i), + sizeof(float)); + internal_dens[i] = (float*) my_calloc(1 << (lut_size - i), + sizeof(float)); + internal_v[i] = (float*) my_calloc(1 << (lut_size - i), sizeof(float)); + } + + /* Initialize internal probabilities/densities from SRAM bits */ + for (i = 0; i < num_SRAM_bits; i++) { + if (SRAM_values[i] == '0') { + internal_prob[0][i] = 0.; + } else { + internal_prob[0][i] = 1.; + } + internal_dens[0][i] = 0.; + internal_v[0][i] = g_power_tech->Vdd; + } + + for (level_idx = 0; level_idx < lut_size; level_idx++) { + t_power_usage driver_power_usage; + int MUXs_this_level; + int MUX_idx; + int reverse_idx = lut_size - level_idx - 1; + + MUXs_this_level = 1 << (reverse_idx); + + /* Power of input drivers */ + power_usage_inverter(&driver_power_usage, input_dens[reverse_idx], + input_prob[reverse_idx], 1.0, period); + power_add_usage(power_usage, &driver_power_usage); + + power_usage_inverter(&driver_power_usage, input_dens[reverse_idx], + input_prob[reverse_idx], 2.0, period); + power_add_usage(power_usage, &driver_power_usage); + + power_usage_inverter(&driver_power_usage, input_dens[reverse_idx], + 1 - input_prob[reverse_idx], 2.0, period); + power_add_usage(power_usage, &driver_power_usage); + + /* Add level restorer after every 2 stages (level_idx %2 == 1) + * But if there is an odd # of stages, just put one at the last + * stage (level_idx == LUT_size - 1) and not at the stage just before + * the last stage (level_idx != LUT_size - 2) + */ + if (((level_idx % 2 == 1) && (level_idx != lut_size - 2)) + || (level_idx == lut_size - 1)) { + level_restorer_this_level = TRUE; + } else { + level_restorer_this_level = FALSE; + } + + /* Loop through the 2-muxs at each level */ + for (MUX_idx = 0; MUX_idx < MUXs_this_level; MUX_idx++) { + t_power_usage sub_power; + float out_prob; + float out_dens; + float sum_prob = 0; + int sram_offset = MUX_idx * ipow(2, level_idx + 1); + int sram_per_branch = ipow(2, level_idx); + int branch_lvl_idx; + int sram_idx; + float v_out; + + /* Calculate output probability of multiplexer */ + out_prob = internal_prob[level_idx][MUX_idx * 2] + * (1 - input_prob[reverse_idx]) + + internal_prob[level_idx][MUX_idx * 2 + 1] + * input_prob[reverse_idx]; + + /* Calculate output density of multiplexer */ + out_dens = internal_dens[level_idx][MUX_idx * 2] + * (1 - input_prob[reverse_idx]) + + internal_dens[level_idx][MUX_idx * 2 + 1] + * input_prob[reverse_idx]; + +#ifdef POWER_LUT_FAST + out_dens += ((1 - internal_prob[level_idx][MUX_idx * 2]) * internal_prob[level_idx][MUX_idx * 2 + 1] + + internal_prob[level_idx][MUX_idx * 2] * (1 - internal_prob[level_idx][MUX_idx * 2 + 1])) + * input_dens[reverse_idx]; +#elif defined(POWER_LUT_SLOW) + for (sram_idx = sram_offset; + sram_idx < sram_offset + sram_per_branch; sram_idx++) { + float branch_prob = 1.; + if (SRAM_values[sram_idx] + == SRAM_values[sram_idx + sram_per_branch]) { + continue; + } + for (branch_lvl_idx = 0; branch_lvl_idx < level_idx; + branch_lvl_idx++) { + int branch_lvl_reverse_idx = lut_size - branch_lvl_idx - 1; + int even_odd = sram_idx / ipow(2, branch_lvl_idx); + if (even_odd % 2 == 0) { + branch_prob *= (1 - input_prob[branch_lvl_reverse_idx]); + } else { + branch_prob *= input_prob[branch_lvl_reverse_idx]; + } + } + sum_prob += branch_prob; + } + out_dens += sum_prob * input_dens[reverse_idx]; +#endif + + /* Calculate output voltage of multiplexer */ + if (level_restorer_this_level) { + v_out = g_power_tech->Vdd; + } else { + v_out = (1 - input_prob[reverse_idx]) + * power_calc_mux_v_out(2, 1.0, + internal_v[level_idx][MUX_idx * 2], + internal_prob[level_idx][MUX_idx * 2 + 1]) + + input_prob[reverse_idx] + * power_calc_mux_v_out(2, 1.0, + internal_v[level_idx][MUX_idx * 2 + 1], + internal_prob[level_idx][MUX_idx * 2]); + } + + /* Save internal node info */ + internal_dens[level_idx + 1][MUX_idx] = out_dens; + internal_prob[level_idx + 1][MUX_idx] = out_prob; + internal_v[level_idx + 1][MUX_idx] = v_out; + + /* Calculate power of the 2-mux */ + power_usage_mux_singlelevel_dynamic(&sub_power, 2, + internal_dens[level_idx + 1][MUX_idx], + internal_v[level_idx + 1][MUX_idx], + &internal_prob[level_idx][MUX_idx * 2], + &internal_dens[level_idx][MUX_idx * 2], + &internal_v[level_idx][MUX_idx * 2], + input_dens[reverse_idx], input_prob[reverse_idx], + transistor_size, period); + power_add_usage(power_usage, &sub_power); + + /* Add the level-restoring buffer if necessary */ + if (level_restorer_this_level) { + /* Level restorer */ + power_usage_buffer(&sub_power, 1, + internal_prob[level_idx + 1][MUX_idx], + internal_dens[level_idx + 1][MUX_idx], TRUE, period); + power_add_usage(power_usage, &sub_power); + } + } + + } + + /* Free allocated memory */ + for (i = 0; i <= lut_size; i++) { + free(internal_prob[i]); + free(internal_dens[i]); + free(internal_v[i]); + } + free(internal_prob); + free(internal_dens); + free(internal_v); + + /* Callibration */ + callibration = + g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_LUT]; + if (callibration->is_done_callibration()) { + scale_factor = callibration->scale_factor(lut_size, transistor_size); + power_scale_usage(power_usage, scale_factor); + } + + return; +} + +/** + * This function calculates power of a local interconnect structure + * - power_usage: (Return value) Power usage of the structure + * - pb: The physical block to which this interconnect belongs + * - interc_pins: The interconnect input/ouput pin information + * - interc_length: The physical length spanned by the interconnect (meters) + */ +void power_usage_local_interc_mux(t_power_usage * power_usage, t_pb * pb, + t_interconnect_pins * interc_pins) { + int pin_idx; + int out_port_idx; + int in_port_idx; + float * in_dens; + float * in_prob; + t_power_usage MUX_power; + t_interconnect * interc = interc_pins->interconnect; + t_interconnect_power * interc_power = interc->interconnect_power; + + power_zero_usage(power_usage); + + /* Ensure port/pins are structured as expected */ + switch (interc_pins->interconnect->type) { + case DIRECT_INTERC: + assert(interc_power->num_input_ports == 1); + assert(interc_power->num_output_ports == 1); + break; + case MUX_INTERC: + assert(interc_power->num_output_ports == 1); + break; + case COMPLETE_INTERC: + break; + } + + /* Power of transistors to build interconnect structure */ + switch (interc_pins->interconnect->type) { + case DIRECT_INTERC: + /* Direct connections require no transistors */ + break; + case MUX_INTERC: + case COMPLETE_INTERC: + /* Many-to-1, or Many-to-Many + * Implemented as a multiplexer for each output + * */ + in_dens = (float*) my_calloc( + interc->interconnect_power->num_input_ports, sizeof(float)); + in_prob = (float*) my_calloc( + interc->interconnect_power->num_input_ports, sizeof(float)); + + for (out_port_idx = 0; + out_port_idx < interc->interconnect_power->num_output_ports; + out_port_idx++) { + for (pin_idx = 0; + pin_idx < interc->interconnect_power->num_pins_per_port; + pin_idx++) { + + int selected_input = OPEN; + + /* Clear input densities */ + for (in_port_idx = 0; + in_port_idx + < interc->interconnect_power->num_input_ports; + in_port_idx++) { + in_dens[in_port_idx] = 0.; + in_prob[in_port_idx] = 0.; + } + + /* Get probability/density of input signals */ + if (pb) { + int output_pin_net = + pb->rr_graph[interc_pins->output_pins[out_port_idx][pin_idx]->pin_count_in_cluster].net_num; + + if (output_pin_net == OPEN) { + selected_input = 0; + } else { + for (in_port_idx = 0; + in_port_idx + < interc->interconnect_power->num_input_ports; + in_port_idx++) { + t_pb_graph_pin * input_pin = + interc_pins->input_pins[in_port_idx][pin_idx]; + int input_pin_net = + pb->rr_graph[input_pin->pin_count_in_cluster].net_num; + + /* Find input pin that connects through the mux to the output pin */ + if (output_pin_net == input_pin_net) { + selected_input = in_port_idx; + } + + /* Initialize input densities */ + if (input_pin_net != OPEN) { + in_dens[in_port_idx] = pin_dens(pb, input_pin); + in_prob[in_port_idx] = pin_prob(pb, input_pin); + } + } + + /* Check that the input pin was found with a matching net to the output pin */ + assert(selected_input != OPEN); + } + } else { + selected_input = 0; + } + + /* Calculate power of the multiplexer */ + power_usage_mux_multilevel(&MUX_power, + power_get_mux_arch( + interc_pins->interconnect->interconnect_power->num_input_ports, + g_power_arch->mux_transistor_size), in_prob, + in_dens, selected_input, TRUE, g_solution_inf.T_crit); + + power_add_usage(power_usage, &MUX_power); + } + } + + free(in_dens); + free(in_prob); + break; + default: + assert(0); + } + + power_add_usage(&interc_pins->interconnect->interconnect_power->power_usage, + power_usage); +} + +/** + * This calculates the power of a multilevel multiplexer, with static inputs + * - power_usage: (Return value) The power usage of the multiplexer + * - mux_arch: The information on the multiplexer architecture + * - in_prob: Array of input signal probabilities + * - in_dens: Array of input transition densitites + * - selected_input: The index of the input that has been statically selected + * - output_level_restored: Whether the output is level restored to Vdd. + */ +void power_usage_mux_multilevel(t_power_usage * power_usage, + t_mux_arch * mux_arch, float * in_prob, float * in_dens, + int selected_input, boolean output_level_restored, float period) { + float output_density; + float output_prob; + float V_out; + boolean found; + PowerSpicedComponent * callibration; + float scale_factor; + int * selector_values = (int*) my_calloc(mux_arch->levels, sizeof(int)); + + assert(selected_input != OPEN); + + power_zero_usage(power_usage); + + /* Find selection index at each level */ + found = mux_find_selector_values(selector_values, mux_arch->mux_graph_head, + selected_input); + + assert(found); + + /* Calculate power of the multiplexor stages, from final stage, to first stages */ + power_usage_mux_rec(power_usage, &output_density, &output_prob, &V_out, + mux_arch->mux_graph_head, mux_arch, selector_values, in_prob, + in_dens, output_level_restored, period); + + free(selector_values); + + callibration = + g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_MUX]; + if (callibration->is_done_callibration()) { + scale_factor = callibration->scale_factor(mux_arch->num_inputs, + mux_arch->transistor_size); + power_scale_usage(power_usage, scale_factor); + } + +} + +/** + * Internal function, used recursively by power_calc_mux + */ +static void power_usage_mux_rec(t_power_usage * power_usage, float * out_prob, + float * out_dens, float * v_out, t_mux_node * mux_node, + t_mux_arch * mux_arch, int * selector_values, + float * primary_input_prob, float * primary_input_dens, + boolean v_out_restored, float period) { + int input_idx; + float * in_prob; + float * in_dens; + float * v_in; + t_power_usage sub_power_usage; + + /* Single input mux is really just a wire, and has no power. + * Ensure that it has no children before returning. */ + if (mux_node->num_inputs == 1) { + assert(mux_node->level == 0); + return; + } + + v_in = (float*) my_calloc(mux_node->num_inputs, sizeof(float)); + if (mux_node->level == 0) { + /* First level of mux - inputs are primar inputs */ + in_prob = &primary_input_prob[mux_node->starting_pin_idx]; + in_dens = &primary_input_dens[mux_node->starting_pin_idx]; + + for (input_idx = 0; input_idx < mux_node->num_inputs; input_idx++) { + v_in[input_idx] = g_power_tech->Vdd; + } + } else { + /* Higher level of mux - inputs recursive from lower levels */ + in_prob = (float*) my_calloc(mux_node->num_inputs, sizeof(float)); + in_dens = (float*) my_calloc(mux_node->num_inputs, sizeof(float)); + + for (input_idx = 0; input_idx < mux_node->num_inputs; input_idx++) { + /* Call recursively for multiplexer driving the input */ + power_usage_mux_rec(power_usage, &in_prob[input_idx], + &in_dens[input_idx], &v_in[input_idx], + &mux_node->children[input_idx], mux_arch, selector_values, + primary_input_prob, primary_input_dens, FALSE, period); + } + } + + power_usage_mux_singlelevel_static(&sub_power_usage, out_prob, out_dens, + v_out, mux_node->num_inputs, selector_values[mux_node->level], + in_prob, in_dens, v_in, mux_arch->transistor_size, v_out_restored, + period); + power_add_usage(power_usage, &sub_power_usage); + + if (mux_node->level != 0) { + free(in_prob); + free(in_dens); + } +} + +/** + * This function calculates the power of a multistage buffer + * - power_usage: (Return value) Power usage of buffer + * - size: The size of the final buffer stage, relative to min-sized inverter + * - in_prob: The signal probability of the input + * - in_dens: The transition density of the input + * - level_restored: Whether this buffer must level restore the input + * - input_mux_size: If fed by a mux, the size of this mutliplexer + */ +void power_usage_buffer(t_power_usage * power_usage, float size, float in_prob, + float in_dens, boolean level_restorer, float period) { + t_power_usage sub_power_usage; + int i, num_stages; + float stage_effort; + float stage_inv_size; + float stage_in_prob; + float input_dyn_power; + float scale_factor; + PowerSpicedComponent * callibration; + + power_zero_usage(power_usage); + + if (size == 0.) { + return; + } + + num_stages = power_calc_buffer_num_stages(size, + g_power_arch->logical_effort_factor); + stage_effort = calc_buffer_stage_effort(num_stages, size); + + stage_in_prob = in_prob; + for (i = 0; i < num_stages; i++) { + stage_inv_size = pow(stage_effort, i); + + if (i == 0) { + if (level_restorer) { + /* Sense Buffer */ + power_usage_level_restorer(&sub_power_usage, &input_dyn_power, + in_dens, stage_in_prob, period); + } else { + power_usage_inverter(&sub_power_usage, in_dens, stage_in_prob, + stage_inv_size, period); + } + } else { + power_usage_inverter(&sub_power_usage, in_dens, stage_in_prob, + stage_inv_size, period); + } + power_add_usage(power_usage, &sub_power_usage); + + stage_in_prob = 1 - stage_in_prob; + } + + /* Callibration */ + if (level_restorer) { + callibration = + g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_BUFFER_WITH_LEVR]; + } else { + callibration = + g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_BUFFER]; + } + + if (callibration->is_done_callibration()) { + scale_factor = callibration->scale_factor(1, size); + power_scale_usage(power_usage, scale_factor); + } + + /* Short-circuit: add a factor to dynamic power, but the factor is not in addition to the input power + * Need to subtract input before adding factor - this matters for small buffers + */ + /*power_usage->dynamic += (power_usage->dynamic - input_dyn_power) + * power_calc_buffer_sc(num_stages, stage_effort, level_restorer, + input_mux_size); */ +} + diff --git a/vpr7_rram/vpr/SRC/power/power_components.h b/vpr7_rram/vpr/SRC/power/power_components.h new file mode 100644 index 000000000..6d36f72fc --- /dev/null +++ b/vpr7_rram/vpr/SRC/power/power_components.h @@ -0,0 +1,100 @@ +/********************************************************************* + * The following code is part of the power modelling feature of VTR. + * + * For support: + * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power + * + * or email: + * vtr.power.estimation@gmail.com + * + * If you are using power estimation for your researach please cite: + * + * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation + * for Diverse FPGA Architectures. In International Conference on + * Field Programmable Technology, 2012. + * + ********************************************************************/ + +/** + * This file offers functions to estimate power of major components + * within the FPGA (flip-flops, LUTs, interconnect structures, etc). + */ + +#ifndef __POWER_COMPONENTS_H__ +#define __POWER_COMPONENTS_H__ + +/************************* INCLUDES *********************************/ +#include "power.h" + +/************************* Defines **********************************/ + +/* This controlls the level of accuracy used for transition density + * calculations of internal LUT nodes. The more detailed model + * looks at SRAM values in deciding if toggles on the inputs will + * toggle the internal nets. The fast method uses only signal + * probabilities. + */ +#define POWER_LUT_SLOW +#if (!(defined(POWER_LUT_SLOW) || defined(POWER_LUT_FAST))) +#define POWER_LUT_SLOW +#endif + +/************************* ENUMS ************************************/ +typedef enum { + POWER_COMPONENT_IGNORE = 0, /* */ + POWER_COMPONENT_TOTAL, /* Total power for entire FPGA */ + + POWER_COMPONENT_ROUTING, /* Power for routing fabric (not local routing) */ + POWER_COMPONENT_ROUTE_SB, /* Switch-box */ + POWER_COMPONENT_ROUTE_CB, /* Connection box*/ + POWER_COMPONENT_ROUTE_GLB_WIRE, /* Wires */ + + POWER_COMPONENT_CLOCK, /* Clock network */ + POWER_COMPONENT_CLOCK_BUFFER, /* Buffers in clock network */ + POWER_COMPONENT_CLOCK_WIRE, /* Wires in clock network */ + + POWER_COMPONENT_PB, /* Logic Blocks, and other hard blocks */ + POWER_COMPONENT_PB_PRIMITIVES, /* Primitives (LUTs, FF, etc) */ + POWER_COMPONENT_PB_INTERC_MUXES, /* Local interconnect structures (muxes) */ + POWER_COMPONENT_PB_BUFS_WIRE, /* Local buffers and wire capacitance */ + + POWER_COMPONENT_PB_OTHER, /* Power from other estimation methods - not transistor-level */ + + POWER_COMPONENT_MAX_NUM +} e_power_component_type; + +/************************* STRUCTS **********************************/ +typedef struct s_power_breakdown t_power_components; + +struct s_power_breakdown { + t_power_usage * components; +}; + +/************************* FUNCTION DECLARATIONS ********************/ +extern t_power_components g_power_by_component; + +/************************* FUNCTION DECLARATIONS ********************/ + +void power_components_init(void); +void power_components_uninit(void); +void power_component_get_usage(t_power_usage * power_usage, + e_power_component_type component_idx); +void power_component_add_usage(t_power_usage * power_usage, + e_power_component_type component_idx); +float power_component_get_usage_sum(e_power_component_type component_idx); + +void power_usage_ff(t_power_usage * power_usage, float size, float D_prob, + float D_dens, float Q_prob, float Q_dens, float clk_prob, + float clk_dens, float period); +void power_usage_lut(t_power_usage * power_usage, int LUT_size, + float transistor_size, char * SRAM_values, float * input_densities, + float * input_probabilities, float period); +void power_usage_local_interc_mux(t_power_usage * power_usage, t_pb * pb, + t_interconnect_pins * interc_pins); +void power_usage_mux_multilevel(t_power_usage * power_usage, + t_mux_arch * mux_arch, float * in_prob, float * in_dens, + int selected_input, boolean output_level_restored, float period); +void power_usage_buffer(t_power_usage * power_usage, float size, float in_prob, + float in_dens, boolean level_restored, float period); + +#endif diff --git a/vpr7_rram/vpr/SRC/power/power_lowlevel.c b/vpr7_rram/vpr/SRC/power/power_lowlevel.c new file mode 100644 index 000000000..794a8fa4c --- /dev/null +++ b/vpr7_rram/vpr/SRC/power/power_lowlevel.c @@ -0,0 +1,893 @@ +/********************************************************************* + * The following code is part of the power modelling feature of VTR. + * + * For support: + * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power + * + * or email: + * vtr.power.estimation@gmail.com + * + * If you are using power estimation for your researach please cite: + * + * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation + * for Diverse FPGA Architectures. In International Conference on + * Field Programmable Technology, 2012. + * + ********************************************************************/ + +/** + * This file provides functions that calculate the power of low-level + * components (inverters, simple multiplexers, etc) + */ + +/************************* INCLUDES *********************************/ +#include + +#include "power_lowlevel.h" +#include "power_util.h" +#include "power_cmos_tech.h" +#include "globals.h" + +/************************* FUNCTION DELCARATIONS ********************/ +static float power_calc_node_switching_v(float capacitance, float density, + float period, float voltage); +static void power_calc_transistor_capacitance(float *C_d, float *C_s, + float *C_g, e_tx_type transistor_type, float size); +static float power_calc_leakage_st(e_tx_type transistor_type, float size); +static float power_calc_leakage_st_pass_transistor(float size, float v_ds); +static float power_calc_leakage_gate(e_tx_type transistor_type, float size); +/*static float power_calc_buffer_sc_levr( + t_power_buffer_strength_inf * buffer_strength, int input_mux_size);*/ + +/************************* FUNCTION DEFINITIONS *********************/ + +/** + * Initializer function for this module, called by power_init + */ +void power_lowlevel_init() { + float C_d, C_s, C_g; + + power_calc_transistor_capacitance(&C_d, &C_s, &C_g, NMOS, 1.0); + g_power_commonly_used->NMOS_1X_C_d = C_d; + g_power_commonly_used->NMOS_1X_C_g = C_g; + g_power_commonly_used->NMOS_1X_C_s = C_s; + + power_calc_transistor_capacitance(&C_d, &C_s, &C_g, PMOS, + g_power_tech->PN_ratio); + g_power_commonly_used->PMOS_1X_C_d = C_d; + g_power_commonly_used->PMOS_1X_C_g = C_g; + g_power_commonly_used->PMOS_1X_C_s = C_s; + + g_power_commonly_used->NMOS_1X_st_leakage = power_calc_leakage_st(NMOS, + 1.0); + g_power_commonly_used->PMOS_1X_st_leakage = power_calc_leakage_st(PMOS, + 1.0 * g_power_tech->PN_ratio); + + g_power_commonly_used->INV_1X_C_in = g_power_commonly_used->NMOS_1X_C_g + + g_power_commonly_used->PMOS_1X_C_g; + g_power_commonly_used->INV_1X_C = g_power_commonly_used->NMOS_1X_C_g + + g_power_commonly_used->PMOS_1X_C_g + + g_power_commonly_used->NMOS_1X_C_d + + g_power_commonly_used->PMOS_1X_C_d; + + power_calc_transistor_capacitance(&C_d, &C_s, &C_g, NMOS, 2.0); + g_power_commonly_used->INV_2X_C = C_g + C_d; + power_calc_transistor_capacitance(&C_d, &C_s, &C_g, PMOS, + 2.0 * g_power_tech->PN_ratio); + g_power_commonly_used->INV_2X_C += C_g + C_d; + +} + +/** + * Calculates the switching power of a node + * - capacitance: The capacitance of the nodoe + * - density: The transition density of the node + */ +float power_calc_node_switching(float capacitance, float density, + float period) { + return 0.5 * g_power_tech->Vdd * g_power_tech->Vdd * capacitance * density + / period; +} + +/** + * Calculates the switching power of a node, with non-Vdd voltage + * - capacitance: The capacitance of the nodoe + * - density: The transition density of the node + * - voltage: The voltage when the node is charged + */ +static float power_calc_node_switching_v(float capacitance, float density, + float period, float voltage) { + return 0.5 * voltage * g_power_tech->Vdd * capacitance * density / period; +} + +/** + * Calculates the power of an inverter + * - power_usage: (Return value) The power usage of the inverter + * - in_dens: The transition density of the input + * - in_prob: The signal probability of the input + * - size: The inverter size, relative to a min-size inverter + */ +void power_usage_inverter(t_power_usage * power_usage, float in_dens, + float in_prob, float size, float period) { + float C_drain, C_gate, C_source; + float C_inv; + + float PMOS_size = g_power_tech->PN_ratio * size; + float NMOS_size = size; + + power_usage->dynamic = 0.; + power_usage->leakage = 0.; + + C_inv = 0.; + + power_calc_transistor_capacitance(&C_drain, &C_source, &C_gate, NMOS, + NMOS_size); + C_inv += C_gate + C_drain; + + power_calc_transistor_capacitance(&C_drain, &C_source, &C_gate, PMOS, + PMOS_size); + C_inv += C_gate + C_drain; + + power_usage->dynamic = power_calc_node_switching(C_inv, in_dens, period); + + power_usage->leakage = in_prob * power_calc_leakage_st(PMOS, PMOS_size) + + (1 - in_prob) * power_calc_leakage_st(NMOS, NMOS_size); + + power_usage->leakage += in_prob * power_calc_leakage_gate(NMOS, NMOS_size) + + (1 - in_prob) * power_calc_leakage_gate(PMOS, PMOS_size); +} + +/** + * Calculates the power of an inverter, with irregular P/N ratio + * - power_usage: (Return value) The power usage of the inverter + * - dy_power_input: (Return value) The dynamic power of the input node + * - in_dens: The transition density of the input + * - in_prob: The signal probability of the input + * - PMOS_size: (W/L) of the PMOS + * - NMOS_size: (W/L) of the NMOS + */ +void power_usage_inverter_irregular(t_power_usage * power_usage, + float * dyn_power_input, float in_density, float in_probability, + float PMOS_size, float NMOS_size, float period) { + float C_drain, C_gate, C_source; + float C_inv; + float C_in; + + power_usage->dynamic = 0.; + power_usage->leakage = 0.; + + C_inv = 0.; + C_in = 0.; + + power_calc_transistor_capacitance(&C_drain, &C_source, &C_gate, NMOS, + NMOS_size); + C_inv += C_gate + C_drain; + C_in += C_gate; + + power_calc_transistor_capacitance(&C_drain, &C_source, &C_gate, PMOS, + PMOS_size); + C_inv += C_gate + C_drain; + C_in += C_gate; + + power_usage->dynamic = power_calc_node_switching(C_inv, in_density, period); + *dyn_power_input = power_calc_node_switching(C_in, in_density, period); + + power_usage->leakage = in_probability + * power_calc_leakage_st(PMOS, PMOS_size) + + (1 - in_probability) * power_calc_leakage_st(NMOS, NMOS_size); +} + +/** + * Calculates the power of an inverter, also returning dynamic power of the input + * - power_usage: (Return value) The power usage of the inverter + * - input_dynamic_power: (Return value) The dynamic power of the input node + * - in_dens: The transition density of the input + * - in_prob: The signal probability of the input + * - size: The inverter size, relative to a min-size inverter + */ +#if 0 +void power_calc_inverter_with_input(t_power_usage * power_usage, + float * input_dynamic_power, float in_density, float in_prob, + float size) { + float C_drain, C_gate, C_source; + float C_inv; + float C_in; + + float PMOS_size = g_power_tech->PN_ratio * size; + float NMOS_size = size; + + power_usage->dynamic = 0.; + power_usage->leakage = 0.; + + C_inv = 0.; + C_in = 0.; + + power_calc_transistor_capacitance(&C_drain, &C_source, &C_gate, NMOS, + NMOS_size); + C_inv += C_gate + C_drain; + C_in += C_gate; + + power_calc_transistor_capacitance(&C_drain, &C_source, &C_gate, PMOS, + PMOS_size); + C_inv += C_gate + C_drain; + C_in += C_gate; + + power_usage->dynamic = power_calc_node_switching(C_inv, in_density); + *input_dynamic_power = power_calc_node_switching(C_in, in_density); + + power_usage->leakage = in_prob * power_calc_leakage_st(PMOS, PMOS_size) + + (1 - in_prob) * power_calc_leakage_st(NMOS, NMOS_size); + + power_usage->leakage += in_prob * power_calc_leakage_gate(NMOS, NMOS_size) + + (1 - in_prob) * power_calc_leakage_gate(PMOS, PMOS_size); +} +#endif + +/** + * Calculate the capacitance for a transistor + * - C_d: (Return value) Drain capacitance + * - C_s: (Return value) Source capacitance + * - C_g: (Return value) Gate capacitance + * - transistor_type: NMOS or PMOS + * - size: (W/L) size of the transistor + */ +static void power_calc_transistor_capacitance(float *C_d, float *C_s, + float *C_g, e_tx_type transistor_type, float size) { + t_transistor_size_inf * tx_info_lower; + t_transistor_size_inf * tx_info_upper; + boolean error; + + /* Initialize to 0 */ + *C_d = 0.; + *C_s = 0.; + *C_g = 0.; + + error = power_find_transistor_info(&tx_info_lower, &tx_info_upper, + transistor_type, size); + if (error) { + return; + } + + if (tx_info_lower == NULL) { + /* No lower bound */ + *C_d = tx_info_upper->C_d; + *C_s = tx_info_upper->C_s; + *C_g = tx_info_upper->C_g; + } else if (tx_info_upper == NULL) { + /* No upper bound */ + *C_d = tx_info_lower->C_d; + *C_s = tx_info_lower->C_s; + *C_g = tx_info_lower->C_g; + } else { + /* Linear approximation between sizes */ + float percent_upper = (size - tx_info_lower->size) + / (tx_info_upper->size - tx_info_lower->size); + *C_d = (1 - percent_upper) * tx_info_lower->C_d + + percent_upper * tx_info_upper->C_d; + *C_s = (1 - percent_upper) * tx_info_lower->C_s + + percent_upper * tx_info_upper->C_s; + *C_g = (1 - percent_upper) * tx_info_lower->C_g + + percent_upper * tx_info_upper->C_g; + } + + return; +} + +/** + * Returns the subthreshold leakage power of a transistor, + * for V_ds = V_dd + * - transistor_type: NMOS or PMOS + * - size: (W/L) of transistor + */ +static float power_calc_leakage_st(e_tx_type transistor_type, float size) { + t_transistor_size_inf * tx_info_lower; + t_transistor_size_inf * tx_info_upper; + boolean error; + float current; + + error = power_find_transistor_info(&tx_info_lower, &tx_info_upper, + transistor_type, size); + if (error) { + return 0; + } + + if (tx_info_lower == NULL) { + /* No lower bound */ + current = tx_info_upper->leakage_subthreshold; + + } else if (tx_info_upper == NULL) { + /* No upper bound */ + current = tx_info_lower->leakage_subthreshold; + } else { + /* Linear approximation between sizes */ + float percent_upper = (size - tx_info_lower->size) + / (tx_info_upper->size - tx_info_lower->size); + current = (1 - percent_upper) * tx_info_lower->leakage_subthreshold + + percent_upper * tx_info_upper->leakage_subthreshold; + } + + return current * g_power_tech->Vdd; +} + +/** + * Returns the gate gate leakage power of a transistor + * - transistor_type: NMOS or PMOS + * - size: (W/L) of transistor + */ +static float power_calc_leakage_gate(e_tx_type transistor_type, float size) { + t_transistor_size_inf * tx_info_lower; + t_transistor_size_inf * tx_info_upper; + boolean error; + float current; + + error = power_find_transistor_info(&tx_info_lower, &tx_info_upper, + transistor_type, size); + if (error) { + return 0; + } + + if (tx_info_lower == NULL) { + /* No lower bound */ + current = tx_info_upper->leakage_gate; + + } else if (tx_info_upper == NULL) { + /* No upper bound */ + current = tx_info_lower->leakage_gate; + } else { + /* Linear approximation between sizes */ + float percent_upper = (size - tx_info_lower->size) + / (tx_info_upper->size - tx_info_lower->size); + current = (1 - percent_upper) * tx_info_lower->leakage_gate + + percent_upper * tx_info_upper->leakage_gate; + } + + return current * g_power_tech->Vdd; +} + +/** + * Returns the subthreshold leakage power of a pass-transistor, + * assumed to be a minimum-sized NMOS + * - size: (W/L) size of transistor (Must be 1.0) + * - v_ds: Drain-source voltage + */ +static float power_calc_leakage_st_pass_transistor(float size, float v_ds) { + t_power_nmos_leakage_inf * nmos_low = NULL; + t_power_nmos_leakage_inf * nmos_high = NULL; + + t_power_nmos_leakage_pair * lower; + t_power_nmos_leakage_pair * upper; + float i_ds; + float power_low; + float power_high; + bool over_range = false; + + assert(size >= 1.0); + + // Check if nmos size is beyond range + if (size + >= g_power_tech->nmos_leakage_info[g_power_tech->num_nmos_leakage_info + - 1].nmos_size) { + nmos_low = + &g_power_tech->nmos_leakage_info[g_power_tech->num_nmos_leakage_info + - 1]; + over_range = true; + } else { + for (int i = 1; i < g_power_tech->num_nmos_leakage_info; i++) { + if (size < g_power_tech->nmos_leakage_info[i].nmos_size) { + nmos_low = &g_power_tech->nmos_leakage_info[i - 1]; + nmos_high = &g_power_tech->nmos_leakage_info[i]; + break; + } + } + } + + if (size + > g_power_tech->nmos_leakage_info[g_power_tech->num_nmos_leakage_info + - 1].nmos_size) { + power_log_msg(POWER_LOG_ERROR, + "The architectures uses multiplexers with \ + transistors sizes larger than what is defined in the \ + section of the technology file."); + } + + power_find_nmos_leakage(nmos_low, &lower, &upper, v_ds); + if (lower->v_ds == v_ds || !upper) { + i_ds = lower->i_ds; + } else { + float perc_upper = (v_ds - lower->v_ds) / (upper->v_ds - lower->v_ds); + i_ds = (1 - perc_upper) * lower->i_ds + perc_upper * upper->i_ds; + } + power_low = i_ds * g_power_tech->Vdd; + + if (!over_range) { + power_find_nmos_leakage(nmos_high, &lower, &upper, v_ds); + if (lower->v_ds == v_ds || !upper) { + i_ds = lower->i_ds; + } else { + float perc_upper = (v_ds - lower->v_ds) + / (upper->v_ds - lower->v_ds); + i_ds = (1 - perc_upper) * lower->i_ds + perc_upper * upper->i_ds; + } + power_high = i_ds * g_power_tech->Vdd; + } + + if (over_range) { + return power_low; + } else { + float perc_upper = (size - nmos_low->nmos_size) + / (nmos_high->nmos_size - nmos_low->nmos_size); + return power_high * perc_upper + power_low * (1 - perc_upper); + } +} + +/** + * Calculates the power of a wire + * - power_usage: (Return value) Power usage of the wire + * - capacitance: Capacitance of the wire (F) + * - density: Transition density of the wire + */ +void power_usage_wire(t_power_usage * power_usage, float capacitance, + float density, float period) { + power_usage->leakage = 0.; + power_usage->dynamic = power_calc_node_switching(capacitance, density, + period); +} + +/** + * Calculates the power of a 2-input multiplexer, comprised of transmission gates + * - power_usage: (Return value) Power usage of the mux + * - in_dens: Array of input transition densities + * - in_prob: Array of input signal probabilities + * - sel_desn: Transition density of select line + * - sel_prob: Signal probability of select line + * - out_dens: Transition density of the output + */ +void power_usage_MUX2_transmission(t_power_usage * power_usage, float size, + float * in_dens, float * in_prob, float sel_dens, float out_dens, + float period) { + + power_zero_usage(power_usage); + + float leakage_n, leakage_p; + leakage_n = power_calc_leakage_st(NMOS, size); + leakage_p = power_calc_leakage_st(PMOS, size * g_power_tech->PN_ratio); + + float C_g_n, C_d_n, C_s_n; + power_calc_transistor_capacitance(&C_d_n, &C_s_n, &C_g_n, NMOS, size); + + float C_g_p, C_d_p, C_s_p; + power_calc_transistor_capacitance(&C_d_p, &C_s_p, &C_g_p, PMOS, + size * g_power_tech->PN_ratio); + + /* A transmission gate leaks if the selected input != other input */ + power_usage->leakage += (in_prob[0] * (1 - in_prob[1]) + + (1 - in_prob[0]) * in_prob[1]) * (leakage_n + leakage_p); + + /* Gate switching */ + power_usage->dynamic += 2 + * power_calc_node_switching(C_g_n + C_g_p, sel_dens, period); + + /* Input switching */ + power_usage->dynamic += power_calc_node_switching(C_d_n + C_s_p, in_dens[0], + period); + power_usage->dynamic += power_calc_node_switching(C_d_n + C_s_p, in_dens[1], + period); + + /* Output switching */ + power_usage->dynamic += power_calc_node_switching(2 * (C_s_n + C_d_p), + out_dens, period); +} + +/** + * Calucates the power of a static, single-level multiplexer + * - power_usage: (Return value) power usage of the mux + * - out_prob: (Return value) Signal probability of the output + * - out_dens: (Return value) Transition density of the output + * - num_inputs: Number of inputs of the mux + * - selected_idx: The input index that is selected by the select lines + * - in_prob: Array of input signal probabilities + * - in_dens: Array of input tranistion densities + * - v_in: Array of input max voltages + * - transistor_size: Size of the NMOS transistors (must be 1.0) + * - v_out_restored: Whether the output will be level restored to Vdd + */ +void power_usage_mux_singlelevel_static(t_power_usage * power_usage, + float * out_prob, float * out_dens, float * v_out, int num_inputs, + int selected_idx, float * in_prob, float * in_dens, float * v_in, + float transistor_size, boolean v_out_restored, float period) { + int input_idx; + float v_in_selected; + float in_prob_avg; + + power_zero_usage(power_usage); + + assert(transistor_size >= 1.0); + + if (selected_idx < num_inputs) { + *out_prob = in_prob[selected_idx]; + *out_dens = in_dens[selected_idx]; + v_in_selected = v_in[selected_idx]; + + } else { + /* In this case, the multiplexer is not symetrical. The + * other branch of the mux has more inputs than this one, + * and the selected input index is not a valid index for + * this portion of the mux. If the mux was actually built + * this way, there would likely be a weak pull-up to ensure + * that the node does not float. + */ + *out_prob = 1.0; + *out_dens = 0.0; + + v_in_selected = 0.; + for (input_idx = 0; input_idx < num_inputs; input_idx++) { + v_in_selected += v_in[input_idx]; + } + v_in_selected /= num_inputs; + } + + in_prob_avg = 0.; + + float C_d, C_g, C_s; + power_calc_transistor_capacitance(&C_d, &C_s, &C_g, NMOS, transistor_size); + + for (input_idx = 0; input_idx < num_inputs; input_idx++) { + /* Dynamic Power at Inputs */ + power_usage->dynamic += power_calc_node_switching_v(C_d, + in_dens[input_idx], period, v_in[input_idx]); + + if (input_idx != selected_idx) { + in_prob_avg += in_prob[input_idx]; + } + } + in_prob_avg /= (num_inputs - 1); + + if (v_out_restored) { + *v_out = g_power_tech->Vdd; + } else { + *v_out = power_calc_mux_v_out(num_inputs, transistor_size, + v_in_selected, in_prob_avg); + } + + for (input_idx = 0; input_idx < num_inputs; input_idx++) { + /* Leakage */ + /* The selected input will never leak */ + if (input_idx == selected_idx) { + continue; + } + + /* Output is high and this input is low */ + power_usage->leakage += (*out_prob) * (1 - in_prob[input_idx]) + * power_calc_leakage_st_pass_transistor(transistor_size, + *v_out); + + /* Output is low and this input is high */ + power_usage->leakage += (1 - *out_prob) * in_prob[input_idx] + * power_calc_leakage_st_pass_transistor(transistor_size, + v_in[input_idx]); + } + + /* Dynamic Power at Output */ + power_usage->dynamic += power_calc_node_switching_v(C_s * num_inputs, + *out_dens, period, *v_out); + +} + +/** + * This function calcualtes the output voltage of a single-level multiplexer + * - num_inputs: Number of inputs of the multiplexer + * - transistor_size: The size of the NMOS transistors (must be 1.0) + * - v_in: The input voltage of the selcted input + * - in_prob_avg: The average signal probabilities of the non-selected inputs + */ +float power_calc_mux_v_out(int num_inputs, float transistor_size, float v_in, + float in_prob_avg) { + t_power_mux_volt_inf * mux_volt_inf_low; + t_power_mux_volt_inf * mux_volt_inf_high; + t_power_mux_volt_pair * lower; + t_power_mux_volt_pair * upper; + float v_out_min, v_out_max; + float v_out_low; + float v_out_high; + bool over_range = false; + + assert(transistor_size >= 1.0); + + t_power_nmos_mux_inf * mux_nmos_inf_lower = NULL; + t_power_nmos_mux_inf * mux_nmos_inf_upper = NULL; + +// Check if nmos size is beyond range + if (transistor_size + >= g_power_tech->nmos_mux_info[g_power_tech->num_nmos_mux_info - 1].nmos_size) { + mux_nmos_inf_lower = + &g_power_tech->nmos_mux_info[g_power_tech->num_nmos_mux_info - 1]; + over_range = true; + } else { + for (int i = 1; i < g_power_tech->num_nmos_mux_info; i++) { + if (transistor_size < g_power_tech->nmos_mux_info[i].nmos_size) { + mux_nmos_inf_lower = &g_power_tech->nmos_mux_info[i - 1]; + mux_nmos_inf_upper = &g_power_tech->nmos_mux_info[i]; + break; + } + } + } + + if (transistor_size + > g_power_tech->nmos_mux_info[g_power_tech->num_nmos_mux_info - 1].nmos_size) { + power_log_msg(POWER_LOG_ERROR, + "The architectures uses multiplexers with \ + transistors sizes larger than what is defined in the \ + section of the technology file."); + } + + if (num_inputs > mux_nmos_inf_lower->max_mux_sl_size + || (!over_range && num_inputs > mux_nmos_inf_upper->max_mux_sl_size)) { + power_log_msg(POWER_LOG_ERROR, + "The circuit contains a single-level mux larger than \ + what is defined in the section of the \ + technology file."); + } + + mux_volt_inf_low = &mux_nmos_inf_lower->mux_voltage_inf[num_inputs]; + + power_find_mux_volt_inf(&lower, &upper, mux_volt_inf_low, v_in); + if (lower->v_in == v_in || !upper) { + v_out_min = lower->v_out_min; + v_out_max = lower->v_out_max; + } else { + float perc_upper = (v_in - lower->v_in) / (upper->v_in - lower->v_in); + v_out_min = (1 - perc_upper) * lower->v_out_min + + perc_upper * upper->v_out_min; + v_out_max = (1 - perc_upper) * lower->v_out_max + + perc_upper * upper->v_out_max; + } + v_out_low = in_prob_avg * v_out_max + (1 - in_prob_avg) * v_out_min; + + if (!over_range) { + mux_volt_inf_high = &mux_nmos_inf_upper->mux_voltage_inf[num_inputs]; + power_find_mux_volt_inf(&lower, &upper, mux_volt_inf_high, v_in); + if (lower->v_in == v_in || !upper) { + v_out_min = lower->v_out_min; + v_out_max = lower->v_out_max; + } else { + float perc_upper = (v_in - lower->v_in) + / (upper->v_in - lower->v_in); + v_out_min = (1 - perc_upper) * lower->v_out_min + + perc_upper * upper->v_out_min; + v_out_max = (1 - perc_upper) * lower->v_out_max + + perc_upper * upper->v_out_max; + } + v_out_high = in_prob_avg * v_out_max + (1 - in_prob_avg) * v_out_min; + } + + if (over_range) { + return v_out_low; + } else { + float perc_upper = + (transistor_size - mux_nmos_inf_lower->nmos_size) + / (mux_nmos_inf_upper->nmos_size + - mux_nmos_inf_lower->nmos_size); + return v_out_high * perc_upper + (1 - perc_upper) * v_out_low; + } +} + +/** This function calculates the power of a single-level multiplexer, where the + * select lines are dynamic + * - power_usage: (Return value) The power usage of the mux + * - num_inputs: Number of multiplexer inputs (must be 2) + * - out_density: The transition density of the output + * - out_prob: The signal probability of the output + * - v_out: The output max voltage + * - in_prob: Array of input signal probabilities + * - in_dens: Array of input tranistion densities + * - v_in: Array of input voltages + * - sel_dens: Transition density of the select line + * - sel_prob: Signal probability of the select line + * - tranisistor_size: NMOS transistor sizes (must be 1.0) + */ +void power_usage_mux_singlelevel_dynamic(t_power_usage * power_usage, + int num_inputs, float out_density, float v_out, float * in_prob, + float * in_dens, float * v_in, float sel_dens, float sel_prob, + float transistor_size, float period) { + + assert(num_inputs == 2); + + power_zero_usage(power_usage); + + /* Leakage occurs when input1 != input2. + * If the selected input is low, the other transistor leaks input->output + * If the selected input is high, the other transistor leaks output->input*/ + + /* 1st selected, 1st Low, 2nd High - Leakage from 2nd in->out */ + power_usage->leakage += (1 - sel_prob) * (1 - in_prob[0]) * in_prob[1] + * power_calc_leakage_st_pass_transistor(transistor_size, v_in[1]); + + /* 1st selected, 1st High, 2nd Low - Leakage from 2nd out->in */ + /* 2nd selected, 1st Low, 2nd High - Leakage from 1st out->in */ + power_usage->leakage += ((1 - sel_prob) * in_prob[0] * (1 - in_prob[1]) + + sel_prob * (1 - in_prob[0]) * in_prob[1]) + * power_calc_leakage_st_pass_transistor(transistor_size, v_out); + + /* 2nd selected, 1st High, 2nd Low - Leakage from 1st in->out */ + power_usage->leakage += sel_prob * in_prob[0] * (1 - in_prob[1]) + * power_calc_leakage_st_pass_transistor(transistor_size, v_in[0]); + + /* Gate switching */ + float C_d, C_s, C_g; + power_calc_transistor_capacitance(&C_d, &C_s, &C_g, NMOS, transistor_size); + power_usage->dynamic += 2 + * power_calc_node_switching(C_g, sel_dens, period); + + /* Input switching */ + power_usage->dynamic += power_calc_node_switching_v(C_d, in_dens[0], period, + v_in[0]); + power_usage->dynamic += power_calc_node_switching_v(C_d, in_dens[1], period, + v_in[1]); + + /* Output switching */ + power_usage->dynamic += power_calc_node_switching_v(2 * C_s, out_density, + period, v_out); +} + +/** + * This function calculates the power of a level restorer, which is a biased + * inverter with a pull-up PMOS transistor in feedback. + * - power_usage: (Return value) Power usage of the level restorer + * - dyn_power_in: (Return value) Dynamic power at the input + * - in_density: Transition density of the input + * - in_prob: Signal probability of the input + */ +void power_usage_level_restorer(t_power_usage * power_usage, + float * dyn_power_in, float in_dens, float in_prob, float period) { + t_power_usage sub_power_usage; + float C; + float C_in; + float input_dyn_power = 0.; + + power_zero_usage(power_usage); + + /* Inverter */ + power_usage_inverter_irregular(&sub_power_usage, &input_dyn_power, in_dens, + in_prob, 1.0, 2.0, period); + power_add_usage(power_usage, &sub_power_usage); + + /* Pull-up PMOS */ + if (g_power_tech->PMOS_inf.long_trans_inf == NULL) { + power_log_msg(POWER_LOG_ERROR, + "No long transistor information exists. Cannot determine transistor properties."); + return; + } + C = g_power_tech->PMOS_inf.long_trans_inf->C_d + + g_power_tech->PMOS_inf.long_trans_inf->C_g; + C_in = g_power_tech->PMOS_inf.long_trans_inf->C_d; + + input_dyn_power += power_calc_node_switching(C_in, in_dens, period); + power_usage->dynamic += power_calc_node_switching(C, in_dens, period); + power_usage->leakage += (1 - in_prob) + * g_power_tech->PMOS_inf.long_trans_inf->leakage_subthreshold; + + *dyn_power_in = input_dyn_power; +} + +/** + * This function calculates the short-circuit factor for a buffer. This factor + * represents the short-circuit power of a buffer, as a factor of switching power. + * - stages: Number of stages of the buffer + * - gain: The gain at each stage + * - level_restorer: Whether this buffer must level-restore the input to Vdd + * - input_mux_size: For level-restoring buffers, what is the size of the mux driving it + */ +// Not used anymore +#if 0 +float power_calc_buffer_sc(int stages, float gain, boolean level_restorer, + int input_mux_size) { + + t_power_buffer_size_inf * size_inf; + t_power_buffer_strength_inf * strength_lower; + t_power_buffer_strength_inf * strength_upper; + float sc; + + /* Find information for given buffer size */ + size_inf = &g_power_tech->buffer_size_inf[stages]; + + /* Find information for a given size/strength */ + power_find_buffer_strength_inf(&strength_lower, &strength_upper, size_inf, + gain); + + if (!level_restorer) { + if (strength_upper == NULL) { + sc = strength_lower->sc_no_levr; + } else { + float percent_upper = (gain - strength_lower->stage_gain) + / (strength_upper->stage_gain - strength_lower->stage_gain); + sc = (1 - percent_upper) * strength_lower->sc_no_levr + + percent_upper * strength_upper->sc_no_levr; + } + } else { + /* Level Restored - Short Circuit depends on input mux size */ + + if (strength_upper == NULL) { + sc = power_calc_buffer_sc_levr(strength_lower, input_mux_size); + } else { + float sc_buf_low; + float sc_buf_high; + + sc_buf_low = power_calc_buffer_sc_levr(strength_lower, + input_mux_size); + sc_buf_high = power_calc_buffer_sc_levr(strength_upper, + input_mux_size); + + float percent_upper = (gain - strength_lower->stage_gain) + / (strength_upper->stage_gain - strength_lower->stage_gain); + sc = (1 - percent_upper) * sc_buf_low + percent_upper * sc_buf_high; + } + } + return sc; +} + +/** + * This function calculates the short-circuit factor for a level-restoring buffer, + * used by power_calc_buffer_sc + * - buffer_strength: The buffer information, for a given size/strength + * - input_mux_size: The size of the mux driving this buffer + */ +static float power_calc_buffer_sc_levr( + t_power_buffer_strength_inf * buffer_strength, int input_mux_size) { + t_power_buffer_sc_levr_inf * mux_lower; + t_power_buffer_sc_levr_inf * mux_upper; + + power_find_buffer_sc_levr(&mux_lower, &mux_upper, buffer_strength, + input_mux_size); + if (mux_upper == NULL) { + return mux_lower->sc_levr; + } else { + float percent_upper = (input_mux_size - mux_lower->mux_size) + / (mux_upper->mux_size - mux_lower->mux_size); + return (1 - percent_upper) * mux_lower->sc_levr + + percent_upper * mux_upper->sc_levr; + } +} +#endif + +float power_calc_buffer_size_from_Cout(float C_out) { + int i; + float C_found; + + t_transistor_inf * nmos_info = &g_power_tech->NMOS_inf; + t_transistor_inf * pmos_info = &g_power_tech->PMOS_inf; + + assert(nmos_info->num_size_entries == pmos_info->num_size_entries); + + for (i = 0; i < nmos_info->num_size_entries; i++) { + C_found = nmos_info->size_inf[i].C_d + pmos_info->size_inf[i].C_d; + + /* Not likely, since floating point */ + if (C_out == C_found) { + return nmos_info->size_inf[i].size; + } + + /* Gone past */ + if (C_found > C_out) { + if (i == 0) { + power_log_msg(POWER_LOG_WARNING, + "Attempted to search for a transistor with a capacitance smaller than the smallest in the technology file.\n"); + return nmos_info->size_inf[i].size; + } else { + float C_prev = nmos_info->size_inf[i - 1].C_d + + pmos_info->size_inf[i - 1].C_d; + float percent_upper = (C_out - C_prev) / (C_found - C_prev); + return percent_upper * nmos_info->size_inf[i].size + + (1 - percent_upper) * nmos_info->size_inf[i - 1].size; + } + } + + /* Reached the End */ + if (i == nmos_info->num_size_entries - 1) { + power_log_msg(POWER_LOG_WARNING, + "Attempted to search for a transistor with a capacitance greater than the largest in the technology file.\n"); + return nmos_info->size_inf[i].size; + } + } + + return 0; +} diff --git a/vpr7_rram/vpr/SRC/power/power_lowlevel.h b/vpr7_rram/vpr/SRC/power/power_lowlevel.h new file mode 100644 index 000000000..7047194d1 --- /dev/null +++ b/vpr7_rram/vpr/SRC/power/power_lowlevel.h @@ -0,0 +1,77 @@ +/********************************************************************* + * The following code is part of the power modelling feature of VTR. + * + * For support: + * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power + * + * or email: + * vtr.power.estimation@gmail.com + * + * If you are using power estimation for your researach please cite: + * + * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation + * for Diverse FPGA Architectures. In International Conference on + * Field Programmable Technology, 2012. + * + ********************************************************************/ + +/** + * This file provides functions that calculate the power of low-level + * components (inverters, simple multiplexers, etc) + */ + +#ifndef __POWER_LOW_LEVEL_H__ +#define __POWER_LOW_LEVEL_H__ + +/************************* INCLUDES *********************************/ +#include "power.h" + +/************************* GLOBALS **********************************/ + +/************************* FUNCTION DECLARATION *********************/ +void power_lowlevel_init(); + +void power_usage_inverter(t_power_usage * power_usage, float in_dens, + float in_prob, float size, float period); +/*void power_calc_inverter_with_input(t_power_usage * power_usage, + float * input_dynamic_power, float in_density, float in_prob, + float size);*/ +void power_usage_inverter_irregular(t_power_usage * power_usage, + float * dyn_power_input, float in_density, float in_probability, + float PMOS_size, float NMOS_size, float period); + +void power_usage_wire(t_power_usage * power_usage, float capacitance, + float density, float period); + +void power_usage_mux_singlelevel_static(t_power_usage * power_usage, + float * out_prob, float * out_dens, float * V_out, int num_inputs, + int selected_idx, float * in_prob, float * in_dens, float * v_in, + float transistor_size, boolean v_out_restored, float period); + +void power_usage_MUX2_transmission(t_power_usage * power_usage, float size, + float * in_dens, float * in_prob, float sel_dens, float out_dens, + float period); + +void power_usage_mux_singlelevel_dynamic(t_power_usage * power_usage, + int num_inputs, float out_density, float v_out, float * in_prob, + float * in_density, float * v_in, float sel_dens, float sel_prob, + float transistor_size, float period); + +void power_usage_level_restorer(t_power_usage * power_usage, + float * dyn_power_in, float in_density, float in_probability, + float period); + +float power_calc_pb_switching_from_c_internal(t_pb * pb, + t_pb_graph_node * pb_graph_node); + +float power_calc_mux_v_out(int num_inputs, float transistor_size, float v_in, + float in_prob_avg); + +/*float power_calc_buffer_sc(int stages, float gain, boolean level_restored, + int input_mux_size);*/ + +float power_calc_node_switching(float capacitance, float density, float period); + +float power_calc_buffer_size_from_Cout(float C_out); + +#endif diff --git a/vpr7_rram/vpr/SRC/power/power_sizing.c b/vpr7_rram/vpr/SRC/power/power_sizing.c new file mode 100644 index 000000000..920c4eacb --- /dev/null +++ b/vpr7_rram/vpr/SRC/power/power_sizing.c @@ -0,0 +1,860 @@ +/********************************************************************* + * The following code is part of the power modelling feature of VTR. + * + * For support: + * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power + * + * or email: + * vtr.power.estimation@gmail.com + * + * If you are using power estimation for your researach please cite: + * + * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation + * for Diverse FPGA Architectures. In International Conference on + * Field Programmable Technology, 2012. + * + ********************************************************************/ + +/** + * The functions in this file are used to count the transistors in the + * FPGA, for physical size estimations + */ + +/************************* INCLUDES *********************************/ +#include +using namespace std; + +#include + +#include "power_sizing.h" +#include "power.h" +#include "globals.h" +#include "power_util.h" +/************************* GLOBALS **********************************/ +static double g_MTA_area; + +/************************* FUNCTION DELCARATIONS ********************/ +static double power_count_transistors_connectionbox(void); +static double power_count_transistors_mux(t_mux_arch * mux_arch); +static double power_count_transistors_mux_node(t_mux_node * mux_node, + float transistor_size); +static void power_mux_node_max_inputs(t_mux_node * mux_node, + float * max_inputs); +static double power_count_transistors_interc(t_interconnect * interc); +static double power_count_transistors_pb_node(t_pb_graph_node * pb_node); +static double power_count_transistors_switchbox(t_arch * arch); +static double power_count_transistors_primitive(t_pb_type * pb_type); +static double power_count_transistors_LUT(int LUT_inputs, + float transistor_size); +static double power_count_transistors_FF(float size); +static double power_count_transistor_SRAM_bit(void); +static double power_count_transistors_inv(float size); +static double power_count_transistors_trans_gate(float size); +static double power_count_transistors_levr(); +static double power_MTAs(float size); +static void power_size_pin_buffers_and_wires(t_pb_graph_pin * pin, + boolean pin_is_an_input); +static double power_transistors_for_pb_node(t_pb_graph_node * pb_node); +static double power_transistors_per_tile(t_arch * arch); +static void power_size_pb(void); +static void power_size_pb_rec(t_pb_graph_node * pb_node); +static void power_size_pin_to_interconnect(t_interconnect * interc, + int * fanout, float * wirelength); +static double power_MTAs(float W_size); +static double power_MTAs_L(float L_size); +/************************* FUNCTION DEFINITIONS *********************/ + +/** + * Counts the number of transistors in the largest connection box + */ +static double power_count_transistors_connectionbox(void) { + double transistor_cnt = 0.; + int CLB_inputs; + float buffer_size; + + //assert(FILL_TYPE->pb_graph_head->num_input_ports == 1); + CLB_inputs = FILL_TYPE->pb_graph_head->num_input_pins[0]; + + /* Buffers from Tracks */ + buffer_size = g_power_commonly_used->max_seg_to_IPIN_fanout + * (g_power_commonly_used->NMOS_1X_C_d + / g_power_commonly_used->INV_1X_C_in) + / g_power_arch->logical_effort_factor; + buffer_size = max(1.0F, buffer_size); + transistor_cnt += g_solution_inf.channel_width + * power_count_transistors_buffer(buffer_size); + + /* Muxes to IPINs */ + transistor_cnt += CLB_inputs + * power_count_transistors_mux( + power_get_mux_arch(g_power_commonly_used->max_IPIN_fanin, + g_power_arch->mux_transistor_size)); + + return transistor_cnt; +} + +/** + * Counts the number of transistors in a buffer. + * - buffer_size: The final stage size of the buffer, relative to a minimum sized inverter + */ +double power_count_transistors_buffer(float buffer_size) { + int stages; + float effort; + float stage_size; + int stage_idx; + double transistor_cnt = 0.; + + stages = power_calc_buffer_num_stages(buffer_size, + g_power_arch->logical_effort_factor); + effort = calc_buffer_stage_effort(stages, buffer_size); + + stage_size = 1; + for (stage_idx = 0; stage_idx < stages; stage_idx++) { + transistor_cnt += power_count_transistors_inv(stage_size); + stage_size *= effort; + } + + return transistor_cnt; +} + +/** + * Counts the number of transistors in a multiplexer + * - mux_arch: The architecture of the multiplexer + */ +static double power_count_transistors_mux(t_mux_arch * mux_arch) { + double transistor_cnt = 0.; + int lvl_idx; + float * max_inputs; + + /* SRAM bits */ + max_inputs = (float*) my_calloc(mux_arch->levels, sizeof(float)); + for (lvl_idx = 0; lvl_idx < mux_arch->levels; lvl_idx++) { + max_inputs[lvl_idx] = 0.; + } + power_mux_node_max_inputs(mux_arch->mux_graph_head, max_inputs); + + for (lvl_idx = 0; lvl_idx < mux_arch->levels; lvl_idx++) { + /* Assume there is decoder logic */ + transistor_cnt += ceil(log(max_inputs[lvl_idx]) / log((double) 2.0)) + * power_count_transistor_SRAM_bit(); + + /* + if (mux_arch->encoding_types[lvl_idx] == ENCODING_DECODER) { + transistor_cnt += ceil(log2((float)max_inputs[lvl_idx])) + * power_cnt_transistor_SRAM_bit(); + // TODO - Size of decoder + } else if (mux_arch->encoding_types[lvl_idx] == ENCODING_ONE_HOT) { + transistor_cnt += max_inputs[lvl_idx] + * power_cnt_transistor_SRAM_bit(); + } else { + assert(0); + } + */ + } + + transistor_cnt += power_count_transistors_mux_node(mux_arch->mux_graph_head, + mux_arch->transistor_size); + free(max_inputs); + return transistor_cnt; +} + +/** + * This function is used recursively to determine the largest single-level + * multiplexer at each level of a multi-level multiplexer + */ +static void power_mux_node_max_inputs(t_mux_node * mux_node, + float * max_inputs) { + + max_inputs[mux_node->level] = max(max_inputs[mux_node->level], + static_cast(mux_node->num_inputs)); + + if (mux_node->level != 0) { + int child_idx; + + for (child_idx = 0; child_idx < mux_node->num_inputs; child_idx++) { + power_mux_node_max_inputs(&mux_node->children[child_idx], + max_inputs); + } + } +} + +/** + * This function is used recursively to count the number of transistors in a multiplexer + */ +static double power_count_transistors_mux_node(t_mux_node * mux_node, + float transistor_size) { + int input_idx; + double transistor_cnt = 0.; + + if (mux_node->num_inputs != 1) { + for (input_idx = 0; input_idx < mux_node->num_inputs; input_idx++) { + /* Single Pass transistor */ + transistor_cnt += power_MTAs(transistor_size); + + /* Child MUX */ + if (mux_node->level != 0) { + transistor_cnt += power_count_transistors_mux_node( + &mux_node->children[input_idx], transistor_size); + } + } + } + + return transistor_cnt; +} + +/** + * This function returns the number of transistors in an interconnect structure + */ +static double power_count_transistors_interc(t_interconnect * interc) { + double transistor_cnt = 0.; + + switch (interc->type) { + case DIRECT_INTERC: + /* No transistors */ + break; + case MUX_INTERC: + case COMPLETE_INTERC: + /* Bus based interconnect: + * - Each output port requires a (num_input_ports:1) bus-based multiplexor. + * - The number of muxes required for bus based multiplexors is equivalent to + * the width of the bus (num_pins_per_port). + */ + transistor_cnt += interc->interconnect_power->num_output_ports + * interc->interconnect_power->num_pins_per_port + * power_count_transistors_mux( + power_get_mux_arch( + interc->interconnect_power->num_input_ports, + g_power_arch->mux_transistor_size)); + break; + default: + assert(0); + } + + interc->interconnect_power->transistor_cnt = transistor_cnt; + return transistor_cnt; +} + +void power_sizing_init(t_arch * arch) { + float transistors_per_tile; + + // tech size = 2 lambda, so lambda^2/4.0 = tech^2 + g_MTA_area = ((POWER_MTA_L * POWER_MTA_W)/ 4.0)*pow(g_power_tech->tech_size, + (float) 2.0); + + // Determines physical size of different PBs + power_size_pb(); + + /* Find # of transistors in each tile type */ + transistors_per_tile = power_transistors_per_tile(arch); + + /* Calculate CLB tile size + * - Assume a square tile + * - Assume min transistor size is Wx6L + * - Assume an overhead to space transistors + */ + g_power_commonly_used->tile_length = sqrt( + power_transistor_area(transistors_per_tile)); +} + +/** + * This functions counts the number of transistors in all structures in the FPGA. + * It returns the number of transistors in a grid of the FPGA (logic block, + * switch box, 2 connection boxes) + */ +static double power_transistors_per_tile(t_arch * arch) { + double transistor_cnt = 0.; + + transistor_cnt += power_transistors_for_pb_node(FILL_TYPE->pb_graph_head); + + transistor_cnt += 2 * power_count_transistors_switchbox(arch); + + transistor_cnt += 2 * power_count_transistors_connectionbox(); + + return transistor_cnt; +} + +static double power_transistors_for_pb_node(t_pb_graph_node * pb_node) { + return pb_node->pb_node_power->transistor_cnt_interc + + pb_node->pb_node_power->transistor_cnt_pb_children + + pb_node->pb_node_power->transistor_cnt_buffers; +} + +/** + * This function counts the number of transistors for a given physical block type + */ +static double power_count_transistors_pb_node(t_pb_graph_node * pb_node) { + int mode_idx; + int interc; + int child; + int pb_idx; + + double tc_children_max = 0; + double tc_interc_max = 0; + boolean ignore_interc = FALSE; + + t_pb_type * pb_type = pb_node->pb_type; + + /* Check if this is a leaf node, or whether it has children */ + if (pb_type->num_modes == 0) { + /* Leaf node */ + tc_interc_max = 0; + tc_children_max = power_count_transistors_primitive(pb_type); + } else { + /* Find max transistor count between all modes */ + for (mode_idx = 0; mode_idx < pb_type->num_modes; mode_idx++) { + + double tc_children = 0; + double tc_interc = 0; + + t_mode * mode = &pb_type->modes[mode_idx]; + + if (pb_type->class_type == LUT_CLASS) { + /* LUTs will have a child node that is used for routing purposes + * For the routing algorithms it is completely connected; however, + * this interconnect does not exist in FPGA hardware and should + * be ignored for power calculations. */ + ignore_interc = TRUE; + } + + /* Count Interconnect Transistors */ + if (!ignore_interc) { + for (interc = 0; interc < mode->num_interconnect; interc++) { + tc_interc += power_count_transistors_interc( + &mode->interconnect[interc]); + } + } + tc_interc_max = max(tc_interc_max, tc_interc); + + /* Count Child PB Types */ + for (child = 0; child < mode->num_pb_type_children; child++) { + t_pb_type * child_type = &mode->pb_type_children[child]; + + for (pb_idx = 0; pb_idx < child_type->num_pb; pb_idx++) { + tc_children += + power_transistors_for_pb_node( + &pb_node->child_pb_graph_nodes[mode_idx][child][pb_idx]); + } + } + + tc_children_max = max(tc_children_max, tc_children); + } + } + + pb_node->pb_node_power->transistor_cnt_interc = tc_interc_max; + pb_node->pb_node_power->transistor_cnt_pb_children = tc_children_max; + + return (tc_interc_max + tc_children_max); +} + +/** + * This function counts the maximum number of transistors in a switch box + */ +static double power_count_transistors_switchbox(t_arch * arch) { + double transistor_cnt = 0.; + double transistors_per_buf_mux = 0.; + int seg_idx; + + /* Buffer */ + transistors_per_buf_mux += power_count_transistors_buffer( + (float) g_power_commonly_used->max_seg_fanout + / g_power_arch->logical_effort_factor); + + /* Multiplexor */ + transistors_per_buf_mux += power_count_transistors_mux( + power_get_mux_arch(g_power_commonly_used->max_routing_mux_size, + g_power_arch->mux_transistor_size)); + + for (seg_idx = 0; seg_idx < arch->num_segments; seg_idx++) { + /* In each switchbox, the different types of segments occur with relative freqencies. + * Thus the total number of wires of each segment type is (#tracks * freq * 2). + * The (x2) factor accounts for vertical and horizontal tracks. + * Of the wires of each segment type only (1/seglength) will have a mux&buffer. + */ + float freq_frac = (float) arch->Segments[seg_idx].frequency + / (float) MAX_CHANNEL_WIDTH; + + transistor_cnt += transistors_per_buf_mux * 2 * freq_frac + * g_solution_inf.channel_width + * (1 / (float) arch->Segments[seg_idx].length); + } + + return transistor_cnt; +} + +/** + * This function calculates the number of transistors for a primitive physical block + */ +static double power_count_transistors_primitive(t_pb_type * pb_type) { + double transistor_cnt; + + if (strcmp(pb_type->blif_model, ".names") == 0) { + /* LUT */ + transistor_cnt = power_count_transistors_LUT(pb_type->num_input_pins, + g_power_arch->LUT_transistor_size); + } else if (strcmp(pb_type->blif_model, ".latch") == 0) { + /* Latch */ + transistor_cnt = power_count_transistors_FF(g_power_arch->FF_size); + } else { + /* Other */ + char msg[BUFSIZE]; + + sprintf(msg, "No transistor counter function for BLIF model: %s", + pb_type->blif_model); + power_log_msg(POWER_LOG_WARNING, msg); + transistor_cnt = 0; + } + + return transistor_cnt; +} + +/** + * Returns the transistor count of an SRAM cell + */ +static double power_count_transistor_SRAM_bit(void) { + return g_power_arch->transistors_per_SRAM_bit; +} + +static double power_count_transistors_levr() { + double transistor_cnt = 0.; + + /* Each level restorer has a P/N=1/2 inverter and a W/L=1/2 PMOS */ + + /* Inverter */ + transistor_cnt += power_MTAs(2); // NMOS + transistor_cnt += 1.0; // PMOS + + /* Pull-up */ + transistor_cnt += power_MTAs_L(2.0); // Double length + + return transistor_cnt; +} + +/** + * Returns the transistor count for a LUT + */ +static double power_count_transistors_LUT(int LUT_inputs, + float transistor_size) { + double transistor_cnt = 0.; + int level_idx; + + /* Each input driver has 1-1X and 2-2X inverters */ + transistor_cnt += (double) LUT_inputs + * (power_count_transistors_inv(1.0) + + 2 * power_count_transistors_inv(2.0)); + + /* SRAM bits */ + transistor_cnt += power_count_transistor_SRAM_bit() * (1 << LUT_inputs); + + for (level_idx = 0; level_idx < LUT_inputs; level_idx++) { + + /* Pass transistors */ + transistor_cnt += (1 << (LUT_inputs - level_idx)) + * power_MTAs(transistor_size); + + /* Add level restorer after every 2 stages (level_idx %2 == 1) + * But if there is an odd # of stages, just put one at the last + * stage (level_idx == LUT_size - 1) and not at the stage just before + * the last stage (level_idx != LUT_size - 2) + */ + if (((level_idx % 2 == 1) && (level_idx != LUT_inputs - 2)) + || (level_idx == LUT_inputs - 1)) { + transistor_cnt += power_count_transistors_levr(); + } + } + + return transistor_cnt; +} + +static double power_count_transistors_trans_gate(float size) { + double transistor_cnt = 0.; + + transistor_cnt += power_MTAs(size); + transistor_cnt += power_MTAs(size * g_power_tech->PN_ratio); + + return transistor_cnt; +} + +static double power_count_transistors_inv(float size) { + double transistor_cnt = 0.; + + /* NMOS */ + transistor_cnt += power_MTAs(size); + + /* PMOS */ + transistor_cnt += power_MTAs(g_power_tech->PN_ratio * size); + + return transistor_cnt; +} + +/** + * Returns the transistor count for a flip-flop + */ +static double power_count_transistors_FF(float size) { + double transistor_cnt = 0.; + + /* 4 1X Inverters */ + transistor_cnt += 4 * power_count_transistors_inv(size); + + /* 2 Muxes = 4 transmission gates */ + transistor_cnt += 4 * power_count_transistors_trans_gate(size); + + return transistor_cnt; +} + +double power_transistor_area(double num_MTAs) { + return num_MTAs * g_MTA_area; +} + +static double power_MTAs(float W_size) { + return 1 + (W_size - 1) * (POWER_DRC_MIN_W / POWER_MTA_W); +} + +static double power_MTAs_L(float L_size) { + return 1 + (L_size - 1) * (POWER_DRC_MIN_L / POWER_MTA_L); +} + +static void power_size_pb(void) { + int type_idx; + + for (type_idx = 0; type_idx < num_types; type_idx++) { + if (type_descriptors[type_idx].pb_graph_head) { + power_size_pb_rec(type_descriptors[type_idx].pb_graph_head); + } + } +} + +static void power_size_pb_rec(t_pb_graph_node * pb_node) { + int port_idx, pin_idx; + int mode_idx, type_idx, pb_idx; + boolean size_buffers_and_wires = TRUE; + + if (!power_method_is_transistor_level( + pb_node->pb_type->pb_type_power->estimation_method) + && pb_node != FILL_TYPE->pb_graph_head) { + /* Area information is only needed for: + * 1. Transistor-level estimation methods + * 2. the FILL_TYPE for tile size calculations + */ + return; + } + + /* Recursive call for all child pb nodes */ + for (mode_idx = 0; mode_idx < pb_node->pb_type->num_modes; mode_idx++) { + t_mode * mode = &pb_node->pb_type->modes[mode_idx]; + + for (type_idx = 0; type_idx < mode->num_pb_type_children; type_idx++) { + int num_pb = mode->pb_type_children[type_idx].num_pb; + + for (pb_idx = 0; pb_idx < num_pb; pb_idx++) { + + power_size_pb_rec( + &pb_node->child_pb_graph_nodes[mode_idx][type_idx][pb_idx]); + } + } + } + + /* Determine # of transistors for this node */ + power_count_transistors_pb_node(pb_node); + + if (pb_node->pb_type->class_type == LUT_CLASS) { + /* LUTs will have a child node that is used for routing purposes + * For the routing algorithms it is completely connected; however, + * this interconnect does not exist in FPGA hardware and should + * be ignored for power calculations. */ + size_buffers_and_wires = FALSE; + } + + if (!power_method_is_transistor_level( + pb_node->pb_type->pb_type_power->estimation_method)) { + size_buffers_and_wires = FALSE; + } + + /* Size all local buffers and wires */ + if (size_buffers_and_wires) { + for (port_idx = 0; port_idx < pb_node->num_input_ports; port_idx++) { + for (pin_idx = 0; pin_idx < pb_node->num_input_pins[port_idx]; + pin_idx++) { + power_size_pin_buffers_and_wires( + &pb_node->input_pins[port_idx][pin_idx], TRUE); + } + } + + for (port_idx = 0; port_idx < pb_node->num_output_ports; port_idx++) { + for (pin_idx = 0; pin_idx < pb_node->num_output_pins[port_idx]; + pin_idx++) { + power_size_pin_buffers_and_wires( + &pb_node->output_pins[port_idx][pin_idx], FALSE); + } + } + + for (port_idx = 0; port_idx < pb_node->num_clock_ports; port_idx++) { + for (pin_idx = 0; pin_idx < pb_node->num_clock_pins[port_idx]; + pin_idx++) { + power_size_pin_buffers_and_wires( + &pb_node->clock_pins[port_idx][pin_idx], TRUE); + } + } + } + +} + +/* Provides statistics about the connection between the pin and interconnect */ +static void power_size_pin_to_interconnect(t_interconnect * interc, + int * fanout, float * wirelength) { + + float this_interc_sidelength; + + /* Pin to interconnect wirelength */ + switch (interc->type) { + case DIRECT_INTERC: + *wirelength = 0; + *fanout = 1; + break; + case MUX_INTERC: + + case COMPLETE_INTERC: + /* The sidelength of this crossbar */ + this_interc_sidelength = sqrt( + power_transistor_area( + interc->interconnect_power->transistor_cnt)); + + /* Assume that inputs to the crossbar have a structure like this: + * + * A B|----- + * -----|---C- + * |----- + * + * A - wire from pin to point of fanout (grows pb interconnect area) + * B - fanout wire (sidelength of this crossbar) + * C - fanouts to crossbar muxes (grows with pb interconnect area) + */ + + *fanout = interc->interconnect_power->num_output_ports; + *wirelength = this_interc_sidelength; + //*wirelength = ((1 + *fanout) / 2.0) * g_power_arch->local_interc_factor + // * pb_interc_sidelength + this_interc_sidelength; + break; + default: + assert(0); + break; + } + +} + +static void power_size_pin_buffers_and_wires(t_pb_graph_pin * pin, + boolean pin_is_an_input) { + int edge_idx; + int list_cnt; + t_interconnect ** list; + boolean found; + int i; + + float C_load; + float this_pb_length; + + int fanout; + float wirelength_out = 0; + float wirelength_in = 0; + + int fanout_tmp; + float wirelength_tmp; + + float this_pb_interc_sidelength = 0; + float parent_pb_interc_sidelength = 0; + boolean top_level_pb; + + t_pb_type * this_pb_type = pin->parent_node->pb_type; + + /* + if (strcmp(pin->parent_node->pb_type->name, "clb") == 0) { + //printf("here\n"); + }*/ + + this_pb_interc_sidelength = sqrt( + power_transistor_area( + pin->parent_node->pb_node_power->transistor_cnt_interc)); + if (pin->parent_node->parent_pb_graph_node == NULL) { + top_level_pb = TRUE; + parent_pb_interc_sidelength = 0.; + } else { + top_level_pb = FALSE; + parent_pb_interc_sidelength = + sqrt( + power_transistor_area( + pin->parent_node->parent_pb_graph_node->pb_node_power->transistor_cnt_interc)); + } + + /* Pins are connected to a wire that is connected to: + * 1. Interconnect structures belonging its pb_node, and/or + * - The pb_node may have one or more modes, each with a set of + * interconnect. The capacitance is the worst-case capacitance + * between the different modes. + * + * 2. Interconnect structures belonging to its parent pb_node + */ + + /* We want to estimate the physical pin fan-out, unfortunately it is not defined in the architecture file. + * Instead, we know the modes of operation, and the fanout may differ depending on the mode. We assume + * that the physical fanout is the max of the connections to the various modes (although in reality it could + * be higher)*/ + + /* Loop through all edges, building a list of interconnect that this pin drives */ + list = NULL; + list_cnt = 0; + for (edge_idx = 0; edge_idx < pin->num_output_edges; edge_idx++) { + /* Check if its already in the list */ + found = FALSE; + for (i = 0; i < list_cnt; i++) { + if (list[i] == pin->output_edges[edge_idx]->interconnect) { + found = TRUE; + break; + } + } + + if (!found) { + list_cnt++; + list = (t_interconnect**) my_realloc(list, + list_cnt * sizeof(t_interconnect*)); + list[list_cnt - 1] = pin->output_edges[edge_idx]->interconnect; + } + } + + /* Determine the: + * 1. Wirelength connected to the pin + * 2. Fanout of the pin + */ + if (pin_is_an_input) { + /* Pin is an input to the PB. + * Thus, all interconnect it drives belong to the modes of the PB. + */ + int * fanout_per_mode; + float * wirelength_out_per_mode; + + fanout_per_mode = (int*) my_calloc(this_pb_type->num_modes, + sizeof(int)); + wirelength_out_per_mode = (float *) my_calloc(this_pb_type->num_modes, + sizeof(float)); + + for (i = 0; i < list_cnt; i++) { + int mode_idx = list[i]->parent_mode_index; + + power_size_pin_to_interconnect(list[i], &fanout_tmp, + &wirelength_tmp); + + fanout_per_mode[mode_idx] += fanout_tmp; + wirelength_out_per_mode[mode_idx] += wirelength_tmp; + } + + fanout = 0; + wirelength_out = 0.; + + /* Find worst-case between modes*/ + for (i = 0; i < this_pb_type->num_modes; i++) { + fanout = max(fanout, fanout_per_mode[i]); + wirelength_out = max(wirelength_out, wirelength_out_per_mode[i]); + } + if (wirelength_out != 0) { + wirelength_out += g_power_arch->local_interc_factor + * this_pb_interc_sidelength; + } + + free(fanout_per_mode); + free(wirelength_out_per_mode); + + /* Input wirelength - from parent PB */ + if (!top_level_pb) { + wirelength_in = g_power_arch->local_interc_factor + * parent_pb_interc_sidelength; + } + + } else { + /* Pin is an output of the PB. + * Thus, all interconnect it drives belong to the parent PB. + */ + fanout = 0; + wirelength_out = 0.; + + if (top_level_pb) { + /* Outputs of top-level pb should not drive interconnect */ + assert(list_cnt == 0); + } + + /* Loop through all interconnect that this pin drives */ + + for (i = 0; i < list_cnt; i++) { + power_size_pin_to_interconnect(list[i], &fanout_tmp, + &wirelength_tmp); + fanout += fanout_tmp; + wirelength_out += wirelength_tmp; + } + if (wirelength_out != 0) { + wirelength_out += g_power_arch->local_interc_factor + * parent_pb_interc_sidelength; + } + + /* Input wirelength - from this PB */ + wirelength_in = g_power_arch->local_interc_factor + * this_pb_interc_sidelength; + + } + free(list); + + /* Wirelength */ + switch (pin->port->port_power->wire_type) { + case POWER_WIRE_TYPE_IGNORED: + /* User is ignoring this wirelength */ + pin->pin_power->C_wire = 0.; + break; + case POWER_WIRE_TYPE_C: + pin->pin_power->C_wire = pin->port->port_power->wire.C; + break; + case POWER_WIRE_TYPE_ABSOLUTE_LENGTH: + pin->pin_power->C_wire = pin->port->port_power->wire.absolute_length + * g_power_arch->C_wire_local; + break; + case POWER_WIRE_TYPE_RELATIVE_LENGTH: + this_pb_length = sqrt( + power_transistor_area( + power_transistors_for_pb_node(pin->parent_node))); + pin->pin_power->C_wire = pin->port->port_power->wire.relative_length + * this_pb_length * g_power_arch->C_wire_local; + break; + + case POWER_WIRE_TYPE_AUTO: + pin->pin_power->C_wire += g_power_arch->C_wire_local + * (wirelength_in + wirelength_out); + break; + case POWER_WIRE_TYPE_UNDEFINED: + default: + assert(0); + break; + } + + /* Buffer */ + switch (pin->port->port_power->buffer_type) { + case POWER_BUFFER_TYPE_NONE: + /* User assumes no buffer */ + pin->pin_power->buffer_size = 0.; + break; + case POWER_BUFFER_TYPE_ABSOLUTE_SIZE: + pin->pin_power->buffer_size = pin->port->port_power->buffer_size; + break; + case POWER_BUFFER_TYPE_AUTO: + /* Asume the buffer drives the wire & fanout muxes */ + C_load = pin->pin_power->C_wire + + (fanout) * g_power_commonly_used->INV_1X_C_in; //g_power_commonly_used->NMOS_1X_C_d; + if (C_load > g_power_commonly_used->INV_1X_C_in) { + pin->pin_power->buffer_size = power_buffer_size_from_logical_effort( + C_load); + } else { + pin->pin_power->buffer_size = 0.; + } + break; + case POWER_BUFFER_TYPE_UNDEFINED: + default: + assert(0); + } + + pin->parent_node->pb_node_power->transistor_cnt_buffers += + power_count_transistors_buffer(pin->pin_power->buffer_size); +} diff --git a/vpr7_rram/vpr/SRC/power/power_sizing.h b/vpr7_rram/vpr/SRC/power/power_sizing.h new file mode 100644 index 000000000..4135c30bc --- /dev/null +++ b/vpr7_rram/vpr/SRC/power/power_sizing.h @@ -0,0 +1,45 @@ +/********************************************************************* + * The following code is part of the power modelling feature of VTR. + * + * For support: + * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power + * + * or email: + * vtr.power.estimation@gmail.com + * + * If you are using power estimation for your researach please cite: + * + * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation + * for Diverse FPGA Architectures. In International Conference on + * Field Programmable Technology, 2012. + * + ********************************************************************/ + +/** + * The functions in this file are used to count the transistors in the + * FPGA, for physical size estimations + */ + +#ifndef __POWER_TRANSISTOR_CNT_H__ +#define __POWER_TRANSISTOR_CNT_H__ + +/************************* INCLUDES *********************************/ +#include "physical_types.h" + +/************************* DEFINES **********************************/ + +/* Design rules, values in LAMBDA, where tech size = 2 LAMBDA */ +#define POWER_DRC_MIN_L 2.0 +#define POWER_DRC_MIN_W 5.0 +#define POWER_DRC_MIN_DIFF_L 5.5 +#define POWER_DRC_SPACING 3.0 +#define POWER_DRC_POLY_OVERHANG 2.5 + +#define POWER_MTA_W (POWER_DRC_MIN_W + POWER_DRC_POLY_OVERHANG + POWER_DRC_SPACING) +#define POWER_MTA_L (POWER_DRC_MIN_L + 2 * POWER_DRC_MIN_DIFF_L + POWER_DRC_SPACING) + +/************************* FUNCTION DECLARATION *********************/ +void power_sizing_init(t_arch * arch); +double power_count_transistors_buffer(float buffer_size); +double power_transistor_area(double num_transistors); +#endif diff --git a/vpr7_rram/vpr/SRC/power/power_util.c b/vpr7_rram/vpr/SRC/power/power_util.c new file mode 100644 index 000000000..a7d1264e3 --- /dev/null +++ b/vpr7_rram/vpr/SRC/power/power_util.c @@ -0,0 +1,606 @@ +/********************************************************************* + * The following code is part of the power modelling feature of VTR. + * + * For support: + * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power + * + * or email: + * vtr.power.estimation@gmail.com + * + * If you are using power estimation for your researach please cite: + * + * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation + * for Diverse FPGA Architectures. In International Conference on + * Field Programmable Technology, 2012. + * + ********************************************************************/ + +/** + * This file provides utility functions used by power estimation. + */ + +/************************* INCLUDES *********************************/ +#include +#include +using namespace std; + +#include + +#include "power_util.h" +#include "globals.h" + +/************************* GLOBALS **********************************/ + +/************************* FUNCTION DECLARATIONS*********************/ +static void log_msg(t_log * log_ptr, char * msg); +static void int_2_binary_str(char * binary_str, int value, int str_length); +static void init_mux_arch_default(t_mux_arch * mux_arch, int levels, + int num_inputs, float transistor_size); +static void alloc_and_load_mux_graph_recursive(t_mux_node * node, + int num_primary_inputs, int level, int starting_pin_idx); +static t_mux_node * alloc_and_load_mux_graph(int num_inputs, int levels); + +/************************* FUNCTION DEFINITIONS *********************/ +void power_zero_usage(t_power_usage * power_usage) { + power_usage->dynamic = 0.; + power_usage->leakage = 0.; +} + +void power_add_usage(t_power_usage * dest, const t_power_usage * src) { + dest->dynamic += src->dynamic; + dest->leakage += src->leakage; +} + +void power_scale_usage(t_power_usage * power_usage, float scale_factor) { + power_usage->dynamic *= scale_factor; + power_usage->leakage *= scale_factor; +} + +float power_sum_usage(t_power_usage * power_usage) { + return power_usage->dynamic + power_usage->leakage; +} + +float power_perc_dynamic(t_power_usage * power_usage) { + return power_usage->dynamic / power_sum_usage(power_usage); +} + +void power_log_msg(e_power_log_type log_type, char * msg) { + log_msg(&g_power_output->logs[log_type], msg); +} + +char * transistor_type_name(e_tx_type type) { + if (type == NMOS) { + return "NMOS"; + } else if (type == PMOS) { + return "PMOS"; + } else { + return "Unknown"; + } +} + +float pin_dens(t_pb * pb, t_pb_graph_pin * pin) { + float density = 0.; + + if (pb) { + int net_num; + net_num = pb->rr_graph[pin->pin_count_in_cluster].net_num; + + if (net_num != OPEN) { + density = vpack_net[net_num].net_power->density; + } + } + + return density; +} + +float pin_prob(t_pb * pb, t_pb_graph_pin * pin) { + /* Assumed pull-up on unused interconnect */ + float prob = 1.; + + if (pb) { + int net_num; + net_num = pb->rr_graph[pin->pin_count_in_cluster].net_num; + + if (net_num != OPEN) { + prob = vpack_net[net_num].net_power->probability; + } + } + + return prob; +} + +/** + * This function determines the values of the selectors in a static mux, based + * on the routing information. + * - selector_values: (Return values) selected index at each mux level + * - mux_node: + * - selected_input_pin: The input index to the multi-level mux that is chosen + */ +boolean mux_find_selector_values(int * selector_values, t_mux_node * mux_node, + int selected_input_pin) { + if (mux_node->level == 0) { + if ((selected_input_pin >= mux_node->starting_pin_idx) + && (selected_input_pin + <= (mux_node->starting_pin_idx + mux_node->num_inputs))) { + selector_values[mux_node->level] = selected_input_pin + - mux_node->starting_pin_idx; + return TRUE; + } + } else { + int input_idx; + for (input_idx = 0; input_idx < mux_node->num_inputs; input_idx++) { + if (mux_find_selector_values(selector_values, + &mux_node->children[input_idx], selected_input_pin)) { + selector_values[mux_node->level] = input_idx; + return TRUE; + } + } + } + return FALSE; +} + +static void log_msg(t_log * log_ptr, char * msg) { + int msg_idx; + + /* Check if this message is already in the log */ + for (msg_idx = 0; msg_idx < log_ptr->num_messages; msg_idx++) { + if (strcmp(log_ptr->messages[msg_idx], msg) == 0) { + return; + } + } + + if (log_ptr->num_messages <= MAX_LOGS) { + log_ptr->num_messages++; + log_ptr->messages = (char**) my_realloc(log_ptr->messages, + log_ptr->num_messages * sizeof(char*)); + } else { + /* Can't add any more messages */ + return; + } + + if (log_ptr->num_messages == (MAX_LOGS + 1)) { + const char * full_msg = "\n***LOG IS FULL***\n"; + log_ptr->messages[log_ptr->num_messages - 1] = (char*) my_calloc( + strlen(full_msg) + 1, sizeof(char)); + strncpy(log_ptr->messages[log_ptr->num_messages - 1], full_msg, + strlen(full_msg)); + } else { + log_ptr->messages[log_ptr->num_messages - 1] = (char*) my_calloc( + strlen(msg) + 1, sizeof(char)); + strncpy(log_ptr->messages[log_ptr->num_messages - 1], msg, strlen(msg)); + } +} + +/** + * Calculates the number of buffer stages required, to achieve a given buffer fanout + * final_stage_size: Size of the final inverter in the buffer, relative to a min size + * desired_stage_effort: The desired gain between stages, typically 4 + */ +int power_calc_buffer_num_stages(float final_stage_size, + float desired_stage_effort) { + int N = 1; + + if (final_stage_size <= 1.0) { + N = 1; + } else if (final_stage_size < desired_stage_effort) + N = 2; + else { + N = (int) (log(final_stage_size) / log(desired_stage_effort) + 1); + + /* We always round down. + * Perhaps N+1 would be closer to the desired stage effort, but the delay savings + * would likely not be worth the extra power/area + */ + } + + return N; +} + +/** + * Calculates the required effort of each stage of a buffer + * - N: The number of stages of the buffer + * - final_stage_size: Size of the final inverter in the buffer, relative to a min size + */ +float calc_buffer_stage_effort(int N, float final_stage_size) { + if (N > 1) + return pow((double) final_stage_size, (1.0 / ((double) N - 1))); + else + return 1.0; +} + +#if 0 +void integer_to_SRAMvalues(int SRAM_num, int input_integer, char SRAM_values[]) { + char binary_str[20]; + int binary_str_counter; + int local_integer; + int i; + + binary_str_counter = 0; + + local_integer = input_integer; + + while (local_integer > 0) { + if (local_integer % 2 == 0) { + SRAM_values[binary_str_counter++] = '0'; + } else { + SRAM_values[binary_str_counter++] = '1'; + } + local_integer = local_integer / 2; + } + + while (binary_str_counter < SRAM_num) { + SRAM_values[binary_str_counter++] = '0'; + } + + SRAM_values[binary_str_counter] = '\0'; + + for (i = 0; i < binary_str_counter; i++) { + binary_str[i] = SRAM_values[binary_str_counter - 1 - i]; + } + + binary_str[binary_str_counter] = '\0'; + +} +#endif + +/** + * This function converts an integer to a binary string + * - binary_str: (Return value) The created binary string + * - value: The integer value to convert + * - str_length: The length of the binary string + */ +static void int_2_binary_str(char * binary_str, int value, int str_length) { + int i; + int odd; + + binary_str[str_length] = '\0'; + + for (i = str_length - 1; i >= 0; i--, value >>= 1) { + odd = value % 2; + if (odd == 0) { + binary_str[i] = '0'; + } else { + binary_str[i] = '1'; + } + } +} + +/** + * This functions returns the LUT SRAM values from the given logic terms + * - LUT_size: The number of LUT inputs + * - truth_table: The logic terms saved from the BLIF file, in a linked list format + */ +char * alloc_SRAM_values_from_truth_table(int LUT_size, + t_linked_vptr * truth_table) { + char * SRAM_values; + int i; + int num_SRAM_bits; + char * binary_str; + char ** terms; + char * buffer; + char * str_loc; + boolean on_set; + t_linked_vptr * list_ptr; + int num_terms; + int term_idx; + int bit_idx; + int dont_care_start_pos; + + num_SRAM_bits = 1 << LUT_size; + SRAM_values = (char*) my_calloc(num_SRAM_bits + 1, sizeof(char)); + SRAM_values[num_SRAM_bits] = '\0'; + + if (!truth_table) { + for (i = 0; i < num_SRAM_bits; i++) { + SRAM_values[i] = '1'; + } + return SRAM_values; + } + + binary_str = (char*) my_calloc(LUT_size + 1, sizeof(char)); + buffer = (char*) my_calloc(LUT_size + 10, sizeof(char)); + + strcpy(buffer, (char*) truth_table->data_vptr); + + /* Check if this is an unconnected node - hopefully these will be + * ignored by VPR in the future + */ + if (strcmp(buffer, " 0") == 0) { + free(binary_str); + free(buffer); + return SRAM_values; + } else if (strcmp(buffer, " 1") == 0) { + for (i = 0; i < num_SRAM_bits; i++) { + SRAM_values[i] = '1'; + } + free(binary_str); + free(buffer); + return SRAM_values; + } + + /* If the LUT is larger than the terms, the lower significant bits will be don't cares */ + str_loc = strtok(buffer, " \t"); + dont_care_start_pos = strlen(str_loc); + + /* Find out if the truth table provides the ON-set or OFF-set */ + str_loc = strtok(NULL, " \t"); + on_set = TRUE; + if (str_loc[0] == '1') { + } else if (str_loc[0] == '0') { + on_set = FALSE; + } else { + assert(0); + } + + /* Count truth table terms */ + num_terms = 0; + for (list_ptr = truth_table; list_ptr != NULL; list_ptr = list_ptr->next) { + num_terms++; + } + terms = (char**) my_calloc(num_terms, sizeof(char *)); + + /* Extract truth table terms */ + for (list_ptr = truth_table, term_idx = 0; list_ptr != NULL; list_ptr = + list_ptr->next, term_idx++) { + terms[term_idx] = (char*) my_calloc(LUT_size + 1, sizeof(char)); + + strcpy(buffer, (char*) list_ptr->data_vptr); + str_loc = strtok(buffer, " \t"); + strcpy(terms[term_idx], str_loc); + + /* Fill don't cares for lower bits (when LUT is larger than term size) */ + for (bit_idx = dont_care_start_pos; bit_idx < LUT_size; bit_idx++) { + terms[term_idx][bit_idx] = '-'; + } + + /* Verify on/off consistency */ + str_loc = strtok(NULL, " \t"); + if (on_set) { + assert(str_loc[0] == '1'); + } else { + assert(str_loc[0] == '0'); + } + } + + /* Loop through all SRAM bits */ + for (i = 0; i < num_SRAM_bits; i++) { + /* Set default value */ + if (on_set) { + SRAM_values[i] = '0'; + } else { + SRAM_values[i] = '1'; + } + + /* Get binary number representing this SRAM index */ + int_2_binary_str(binary_str, i, LUT_size); + + /* Loop through truth table terms */ + for (term_idx = 0; term_idx < num_terms; term_idx++) { + boolean match = TRUE; + + for (bit_idx = 0; bit_idx < LUT_size; bit_idx++) { + if ((terms[term_idx][bit_idx] != '-') + && (terms[term_idx][bit_idx] != binary_str[bit_idx])) { + match = FALSE; + break; + } + } + + if (match) { + if (on_set) { + SRAM_values[i] = '1'; + } else { + SRAM_values[i] = '0'; + } + + /* No need to check the other terms, already matched */ + break; + } + } + + } + free(binary_str); + free(buffer); + for (term_idx = 0; term_idx < num_terms; term_idx++) { + free(terms[term_idx]); + } + free(terms); + + return SRAM_values; +} + +/* Reduce mux levels for multiplexers that are too small for the preset number of levels */ +void mux_arch_fix_levels(t_mux_arch * mux_arch) { + while (((1 << mux_arch->levels) > mux_arch->num_inputs) + && (mux_arch->levels > 1)) { + mux_arch->levels--; + } +} + +float clb_net_density(int net_idx) { + if (net_idx == OPEN) { + return 0.; + } else { + return clb_net[net_idx].net_power->density; + } +} + +float clb_net_prob(int net_idx) { + if (net_idx == OPEN) { + return 0.; + } else { + return clb_net[net_idx].net_power->probability; + } +} + +char * interconnect_type_name(enum e_interconnect type) { + switch (type) { + case COMPLETE_INTERC: + return "complete"; + case MUX_INTERC: + return "mux"; + case DIRECT_INTERC: + return "direct"; + default: + return ""; + } +} + +void output_log(t_log * log_ptr, FILE * fp) { + int msg_idx; + + for (msg_idx = 0; msg_idx < log_ptr->num_messages; msg_idx++) { + fprintf(fp, "%s\n", log_ptr->messages[msg_idx]); + } +} + +void output_logs(FILE * fp, t_log * logs, int num_logs) { + int log_idx; + + for (log_idx = 0; log_idx < num_logs; log_idx++) { + if (logs[log_idx].num_messages) { + power_print_title(fp, logs[log_idx].name); + output_log(&logs[log_idx], fp); + fprintf(fp, "\n"); + } + } +} + +float power_buffer_size_from_logical_effort(float C_load) { + return max(1.0f, + C_load / g_power_commonly_used->INV_1X_C_in + / (2 * g_power_arch->logical_effort_factor)); +} + +void power_print_title(FILE * fp, char * title) { + int i; + const int width = 80; + + int firsthalf = (width - strlen(title) - 2) / 2; + int secondhalf = width - strlen(title) - 2 - firsthalf; + + for (i = 1; i <= firsthalf; i++) + fprintf(fp, "-"); + fprintf(fp, " %s ", title); + for (i = 1; i <= secondhalf; i++) + fprintf(fp, "-"); + fprintf(fp, "\n"); +} + +t_mux_arch * power_get_mux_arch(int num_mux_inputs, float transistor_size) { + int i; + + t_power_mux_info * mux_info = NULL; + + /* Find the mux archs for the given transistor size */ + std::map::iterator it; + + it = g_power_commonly_used->mux_info.find(transistor_size); + + if (it == g_power_commonly_used->mux_info.end()) { + mux_info = new t_power_mux_info; + mux_info->mux_arch = NULL; + mux_info->mux_arch_max_size = 0; + g_power_commonly_used->mux_info[transistor_size] = mux_info; + } else { + mux_info = it->second; + } + + if (num_mux_inputs > mux_info->mux_arch_max_size) { + mux_info->mux_arch = (t_mux_arch*) my_realloc(mux_info->mux_arch, + (num_mux_inputs + 1) * sizeof(t_mux_arch)); + + for (i = mux_info->mux_arch_max_size + 1; i <= num_mux_inputs; i++) { + init_mux_arch_default(&mux_info->mux_arch[i], 2, i, + transistor_size); + } + mux_info->mux_arch_max_size = num_mux_inputs; + } + return &mux_info->mux_arch[num_mux_inputs]; +} + +/** + * Generates a default multiplexer architecture of given size and number of levels + */ +static void init_mux_arch_default(t_mux_arch * mux_arch, int levels, + int num_inputs, float transistor_size) { + + mux_arch->levels = levels; + mux_arch->num_inputs = num_inputs; + + mux_arch_fix_levels(mux_arch); + + mux_arch->transistor_size = transistor_size; + + mux_arch->mux_graph_head = alloc_and_load_mux_graph(num_inputs, + mux_arch->levels); +} + +/** + * Allocates a builds a multiplexer graph with given # inputs and levels + */ +static t_mux_node * alloc_and_load_mux_graph(int num_inputs, int levels) { + t_mux_node * node; + + node = (t_mux_node*) my_malloc(sizeof(t_mux_node)); + alloc_and_load_mux_graph_recursive(node, num_inputs, levels - 1, 0); + + return node; +} + +static void alloc_and_load_mux_graph_recursive(t_mux_node * node, + int num_primary_inputs, int level, int starting_pin_idx) { + int child_idx; + int pin_idx = starting_pin_idx; + + node->num_inputs = (int) (pow(num_primary_inputs, 1 / ((float) level + 1)) + + 0.5); + node->level = level; + node->starting_pin_idx = starting_pin_idx; + + if (level != 0) { + node->children = (t_mux_node*) my_calloc(node->num_inputs, + sizeof(t_mux_node)); + for (child_idx = 0; child_idx < node->num_inputs; child_idx++) { + int num_child_pi = num_primary_inputs / node->num_inputs; + if (child_idx < (num_primary_inputs % node->num_inputs)) { + num_child_pi++; + } + alloc_and_load_mux_graph_recursive(&node->children[child_idx], + num_child_pi, level - 1, pin_idx); + pin_idx += num_child_pi; + } + } +} + +boolean power_method_is_transistor_level( + e_power_estimation_method estimation_method) { + switch (estimation_method) { + case POWER_METHOD_AUTO_SIZES: + case POWER_METHOD_SPECIFY_SIZES: + return TRUE; + default: + return FALSE; + } +} + +boolean power_method_is_recursive(e_power_estimation_method method) { + switch (method) { + case POWER_METHOD_IGNORE: + case POWER_METHOD_TOGGLE_PINS: + case POWER_METHOD_C_INTERNAL: + case POWER_METHOD_ABSOLUTE: + return FALSE; + case POWER_METHOD_AUTO_SIZES: + case POWER_METHOD_SPECIFY_SIZES: + case POWER_METHOD_SUM_OF_CHILDREN: + return TRUE; + case POWER_METHOD_UNDEFINED: + default: + assert(0); + } + +// to get rid of warning + return FALSE; +} + diff --git a/vpr7_rram/vpr/SRC/power/power_util.h b/vpr7_rram/vpr/SRC/power/power_util.h new file mode 100644 index 000000000..80a5d124b --- /dev/null +++ b/vpr7_rram/vpr/SRC/power/power_util.h @@ -0,0 +1,78 @@ +/********************************************************************* + * The following code is part of the power modelling feature of VTR. + * + * For support: + * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power + * + * or email: + * vtr.power.estimation@gmail.com + * + * If you are using power estimation for your researach please cite: + * + * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation + * for Diverse FPGA Architectures. In International Conference on + * Field Programmable Technology, 2012. + * + ********************************************************************/ + +/** + * This file provides utility functions used by power estimation. + */ + +#ifndef __POWER_UTIL_H__ +#define __POWER_UTIL_H__ + +/************************* INCLUDES *********************************/ +#include "power.h" +#include "power_components.h" + +/************************* FUNCTION DECLARATIONS ********************/ + +/* Pins */ +float pin_dens(t_pb * pb, t_pb_graph_pin * pin); +float pin_prob(t_pb * pb, t_pb_graph_pin * pin); +int power_calc_pin_fanout(t_pb_graph_pin * pin, int mode_idx); +void pb_foreach_pin(t_pb_graph_node * pb_node, + void (*fn)(t_pb_graph_pin *, void *), void * context); + +/* Power Usage */ +void power_zero_usage(t_power_usage * power_usage); +void power_add_usage(t_power_usage * dest, const t_power_usage * src); +void power_scale_usage(t_power_usage * power_usage, float scale_factor); +float power_sum_usage(t_power_usage * power_usage); +float power_perc_dynamic(t_power_usage * power_usage); + +/* Message Logger */ +void power_log_msg(e_power_log_type log_type, char * msg); + +/* Buffers */ +int power_calc_buffer_num_stages(float final_stage_size, float desired_stage_effort); +float calc_buffer_stage_effort(int N, float final_stage_size); +float power_buffer_size_from_logical_effort(float C_load); + +/* Multiplexers */ +boolean mux_find_selector_values(int * selector_values, t_mux_node * mux_node, + int selected_input_pin); +t_mux_arch * power_get_mux_arch(int num_mux_inputs, float transistor_size); +void mux_arch_fix_levels(t_mux_arch * mux_arch); + +/* Power Methods */ +boolean power_method_is_transistor_level( + e_power_estimation_method estimation_method); +boolean power_method_is_recursive( + e_power_estimation_method method); + +char * transistor_type_name(e_tx_type type); +char * alloc_SRAM_values_from_truth_table(int LUT_size, + t_linked_vptr * truth_table); +float clb_net_density(int net_idx); +char * interconnect_type_name(enum e_interconnect type); +float clb_net_prob(int net_idx); + +void output_log(t_log * log_ptr, FILE * fp); + +void output_logs(FILE * fp, t_log * logs, int num_logs); + +void power_print_title(FILE * fp, char * title); + +#endif diff --git a/vpr7_rram/vpr/SRC/route/check_route.c b/vpr7_rram/vpr/SRC/route/check_route.c new file mode 100755 index 000000000..58c2a3646 --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/check_route.c @@ -0,0 +1,759 @@ +#include +#include +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "route_export.h" +#include "check_route.h" +#include "rr_graph.h" +#include "check_rr_graph.h" +#include "read_xml_arch_file.h" + +/* mrFPGA: Xifan TANG */ +#include "mrfpga_globals.h" +/* end */ + +/******************** Subroutines local to this module **********************/ +static void check_node_and_range(int inode, enum e_route_type route_type); +static void check_source(int inode, int inet); +static void check_sink(int inode, int inet, boolean * pin_done); +static void check_switch(struct s_trace *tptr, int num_switch); +static boolean check_adjacent(int from_node, int to_node); +static int pin_and_chan_adjacent(int pin_node, int chan_node); +static int chanx_chany_adjacent(int chanx_node, int chany_node); +static void reset_flags(int inet, boolean * connected_to_route); +static void recompute_occupancy_from_scratch(t_ivec ** clb_opins_used_locally); +static void check_locally_used_clb_opins(t_ivec ** clb_opins_used_locally, + enum e_route_type route_type); + +/************************ Subroutine definitions ****************************/ + +void check_route(enum e_route_type route_type, int num_switch, + t_ivec ** clb_opins_used_locally) { + + /* This routine checks that a routing: (1) Describes a properly * + * connected path for each net, (2) this path connects all the * + * pins spanned by that net, and (3) that no routing resources are * + * oversubscribed (the occupancy of everything is recomputed from * + * scratch). */ + + int inet, ipin, max_pins, inode, prev_node; + boolean valid, connects; + boolean * connected_to_route; /* [0 .. num_rr_nodes-1] */ + struct s_trace *tptr; + boolean * pin_done; + + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "Checking to ensure routing is legal...\n"); + + /* Recompute the occupancy from scratch and check for overuse of routing * + * resources. This was already checked in order to determine that this * + * is a successful routing, but I want to double check it here. */ + + recompute_occupancy_from_scratch(clb_opins_used_locally); + valid = feasible_routing(); + if (valid == FALSE) { + vpr_printf(TIO_MESSAGE_ERROR, "Error in check_route -- routing resources are overused.\n"); + exit(1); + } + + check_locally_used_clb_opins(clb_opins_used_locally, route_type); + + connected_to_route = (boolean *) my_calloc(num_rr_nodes, sizeof(boolean)); + + max_pins = 0; + for (inet = 0; inet < num_nets; inet++) + max_pins = std::max(max_pins, (clb_net[inet].num_sinks + 1)); + + pin_done = (boolean *) my_malloc(max_pins * sizeof(boolean)); + + /* Now check that all nets are indeed connected. */ + + for (inet = 0; inet < num_nets; inet++) { + + if (clb_net[inet].is_global || clb_net[inet].num_sinks == 0) /* Skip global nets. */ + continue; + + for (ipin = 0; ipin < (clb_net[inet].num_sinks + 1); ipin++) + pin_done[ipin] = FALSE; + + /* Check the SOURCE of the net. */ + + tptr = trace_head[inet]; + if (tptr == NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_route: net %d has no routing.\n", inet); + exit(1); + } + + inode = tptr->index; + check_node_and_range(inode, route_type); + check_switch(tptr, num_switch); + connected_to_route[inode] = TRUE; /* Mark as in path. */ + + check_source(inode, inet); + pin_done[0] = TRUE; + + prev_node = inode; + tptr = tptr->next; + + /* Check the rest of the net */ + + while (tptr != NULL) { + inode = tptr->index; + check_node_and_range(inode, route_type); + check_switch(tptr, num_switch); + + if (rr_node[prev_node].type == SINK) { + if (connected_to_route[inode] == FALSE) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_route: node %d does not link into existing routing for net %d.\n", inode, inet); + exit(1); + } + } + + else { + connects = check_adjacent(prev_node, inode); + if (!connects) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_route: found non-adjacent segments in traceback while checking net %d.\n", inet); + exit(1); + } + + if (connected_to_route[inode] && rr_node[inode].type != SINK) { + + /* Note: Can get multiple connections to the same logically-equivalent * + * SINK in some logic blocks. */ + + vpr_printf(TIO_MESSAGE_ERROR, "in check_route: net %d routing is not a tree.\n", inet); + exit(1); + } + + connected_to_route[inode] = TRUE; /* Mark as in path. */ + + if (rr_node[inode].type == SINK) + check_sink(inode, inet, pin_done); + + } /* End of prev_node type != SINK */ + prev_node = inode; + tptr = tptr->next; + } /* End while */ + + if (rr_node[prev_node].type != SINK) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_route: net %d does not end with a SINK.\n", inet); + exit(1); + } + + for (ipin = 0; ipin < (clb_net[inet].num_sinks + 1); ipin++) { + if (pin_done[ipin] == FALSE) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_route: net %d does not connect to pin %d.\n", inet, ipin); + exit(1); + } + } + + reset_flags(inet, connected_to_route); + + } /* End for each net */ + + free(pin_done); + free(connected_to_route); + vpr_printf(TIO_MESSAGE_INFO, "Completed routing consistency check successfully.\n"); + vpr_printf(TIO_MESSAGE_INFO, "\n"); +} + +static void check_sink(int inode, int inet, boolean * pin_done) { + + /* Checks that this SINK node is one of the terminals of inet, and marks * + * the appropriate pin as being reached. */ + + int i, j, ipin, ifound, ptc_num, bnum, iclass, node_block_pin, iblk; + t_type_ptr type; + + assert(rr_node[inode].type == SINK); + i = rr_node[inode].xlow; + j = rr_node[inode].ylow; + type = grid[i][j].type; + ptc_num = rr_node[inode].ptc_num; /* For sinks, ptc_num is the class */ + ifound = 0; + + for (iblk = 0; iblk < type->capacity; iblk++) { + bnum = grid[i][j].blocks[iblk]; /* Hardcoded to one block */ + for (ipin = 1; ipin < (clb_net[inet].num_sinks + 1); ipin++) { /* All net SINKs */ + if (clb_net[inet].node_block[ipin] == bnum) { + node_block_pin = clb_net[inet].node_block_pin[ipin]; + iclass = type->pin_class[node_block_pin]; + if (iclass == ptc_num) { + /* Could connect to same pin class on the same clb more than once. Only * + * update pin_done for a pin that hasn't been reached yet. */ + + if (pin_done[ipin] == FALSE) { + ifound++; + pin_done[ipin] = TRUE; + } + } + } + } + } + + if (ifound > 1 && type == IO_TYPE) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_sink: found %d terminals of net %d of pad %d at location (%d, %d).\n", ifound, inet, ptc_num, i, j); + exit(1); + } + + if (ifound < 1) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_sink: node %d does not connect to any terminal of net %s #%d.\n" + "This error is usually caused by incorrectly specified logical equivalence in your architecture file.\n" + "You should try to respecify what pins are equivalent or turn logical equivalence off.\n", inode, clb_net[inet].name, inet); + exit(1); + } +} + +static void check_source(int inode, int inet) { + + /* Checks that the node passed in is a valid source for this net. */ + + t_rr_type rr_type; + t_type_ptr type; + int i, j, ptc_num, bnum, node_block_pin, iclass; + + rr_type = rr_node[inode].type; + if (rr_type != SOURCE) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_source: net %d begins with a node of type %d.\n", inet, rr_type); + exit(1); + } + + i = rr_node[inode].xlow; + j = rr_node[inode].ylow; + ptc_num = rr_node[inode].ptc_num; /* for sinks and sources, ptc_num is class */ + bnum = clb_net[inet].node_block[0]; /* First node_block for net is the source */ + type = grid[i][j].type; + + if (block[bnum].x != i || block[bnum].y != j) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_source: net SOURCE is in wrong location (%d,%d).\n", i, j); + exit(1); + } + + node_block_pin = clb_net[inet].node_block_pin[0]; + iclass = type->pin_class[node_block_pin]; + + if (ptc_num != iclass) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_source: net SOURCE is of wrong class (%d).\n", ptc_num); + exit(1); + } +} + +static void check_switch(struct s_trace *tptr, int num_switch) { + + /* Checks that the switch leading from this traceback element to the next * + * one is a legal switch type. */ + + int inode; + short switch_type; + + inode = tptr->index; + switch_type = tptr->iswitch; + + if (rr_node[inode].type != SINK) { + if (switch_type < 0 || switch_type >= num_switch) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_switch: rr_node %d left via switch type %d.\n", inode, switch_type); + vpr_printf(TIO_MESSAGE_ERROR, "\tSwitch type is out of range.\n"); + exit(1); + } + } + + else { /* Is a SINK */ + + /* Without feedthroughs, there should be no switch. If feedthroughs are * + * allowed, change to treat a SINK like any other node (as above). */ + + if (switch_type != OPEN) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_switch: rr_node %d is a SINK, but attempts to use a switch of type %d.\n", + inode, switch_type); + exit(1); + } + } +} + +static void reset_flags(int inet, boolean * connected_to_route) { + + /* This routine resets the flags of all the channel segments contained * + * in the traceback of net inet to 0. This allows us to check the * + * next net for connectivity (and the default state of the flags * + * should always be zero after they have been used). */ + + struct s_trace *tptr; + int inode; + + tptr = trace_head[inet]; + + while (tptr != NULL) { + inode = tptr->index; + connected_to_route[inode] = FALSE; /* Not in routed path now. */ + tptr = tptr->next; + } +} + +static boolean check_adjacent(int from_node, int to_node) { + + /* This routine checks if the rr_node to_node is reachable from from_node. * + * It returns TRUE if is reachable and FALSE if it is not. Check_node has * + * already been used to verify that both nodes are valid rr_nodes, so only * + * adjacency is checked here. + * Special case: direct OPIN to IPIN connections need not be adjacent. These + * represent specially-crafted connections such as carry-chains or more advanced + * blocks where adjacency is overridden by the architect */ + + + int from_xlow, from_ylow, to_xlow, to_ylow, from_ptc, to_ptc, iclass; + int num_adj, to_xhigh, to_yhigh, from_xhigh, from_yhigh, iconn; + boolean reached; + t_rr_type from_type, to_type; + t_type_ptr from_grid_type, to_grid_type; + + reached = FALSE; + + for (iconn = 0; iconn < rr_node[from_node].num_edges; iconn++) { + if (rr_node[from_node].edges[iconn] == to_node) { + reached = TRUE; + break; + } + } + + if (!reached) + return (FALSE); + + /* Now we know the rr graph says these two nodes are adjacent. Double * + * check that this makes sense, to verify the rr graph. */ + + num_adj = 0; + + from_type = rr_node[from_node].type; + from_xlow = rr_node[from_node].xlow; + from_ylow = rr_node[from_node].ylow; + from_xhigh = rr_node[from_node].xhigh; + from_yhigh = rr_node[from_node].yhigh; + from_ptc = rr_node[from_node].ptc_num; + to_type = rr_node[to_node].type; + to_xlow = rr_node[to_node].xlow; + to_ylow = rr_node[to_node].ylow; + to_xhigh = rr_node[to_node].xhigh; + to_yhigh = rr_node[to_node].yhigh; + to_ptc = rr_node[to_node].ptc_num; + + switch (from_type) { + + case SOURCE: + assert(to_type == OPIN); + if (from_xlow == to_xlow && from_ylow == to_ylow + && from_xhigh == to_xhigh && from_yhigh == to_yhigh) { + + from_grid_type = grid[from_xlow][from_ylow].type; + to_grid_type = grid[to_xlow][to_ylow].type; + assert(from_grid_type == to_grid_type); + + iclass = to_grid_type->pin_class[to_ptc]; + if (iclass == from_ptc) { + num_adj++; + /* Xifan TANG: fully_capable network dirty hack: + * more rules, if they belong to the same port, we think they are adjacent + */ + } else if (OPEN != rr_node[from_node].net_num) { + num_adj++; + } + } + break; + + case SINK: + /* SINKS are adjacent to not connected */ + break; + + case OPIN: + if(to_type == CHANX || to_type == CHANY) { + /* Xifan TANG: a dirty hack for pin_equivalence auto detect */ + from_grid_type = grid[from_xlow][from_ylow].type; + if (TRUE == from_grid_type->output_ports_eq_auto_detect) { + num_adj = 1; + break; + } + /* END */ + /* Original VPR */ + num_adj += pin_and_chan_adjacent(from_node, to_node); + } else { + assert(to_type == IPIN); /* direct OPIN to IPIN connections not necessarily adjacent */ + return TRUE; /* Special case, direct OPIN to IPIN connections need not be adjacent */ + } + + break; + + case IPIN: + assert(to_type == SINK); + if (from_xlow == to_xlow && from_ylow == to_ylow + && from_xhigh == to_xhigh && from_yhigh == to_yhigh) { + + from_grid_type = grid[from_xlow][from_ylow].type; + to_grid_type = grid[to_xlow][to_ylow].type; + assert(from_grid_type == to_grid_type); + + iclass = from_grid_type->pin_class[from_ptc]; + if (iclass == to_ptc) + num_adj++; + } + break; + + case CHANX: + if (to_type == IPIN) { + num_adj += pin_and_chan_adjacent(to_node, from_node); + } else if (to_type == CHANX) { + /* mrFPGA: Xifan TANG */ + if (is_stack) { + if (from_xlow == to_xlow) { + if (to_yhigh == from_ylow-1 || from_yhigh == to_ylow-1) { + num_adj++; + } + } + } else { + /* end */ + /* Original VPR */ + from_xhigh = rr_node[from_node].xhigh; + to_xhigh = rr_node[to_node].xhigh; + if (from_ylow == to_ylow) { + /* UDSD Modification by WMF Begin */ + /*For Fs > 3, can connect to overlapping wire segment */ + if (to_xhigh == from_xlow - 1 || from_xhigh == to_xlow - 1) { + num_adj++; + } + /* Overlapping */ + else { + int i; + + for (i = from_xlow; i <= from_xhigh; i++) { + if (i >= to_xlow && i <= to_xhigh) { + num_adj++; + break; + } + } + } + /* UDSD Modification by WMF End */ + } + /* end */ + } + } else if (to_type == CHANY) { + num_adj += chanx_chany_adjacent(from_node, to_node); + } else { + assert(0); + } + break; + + case CHANY: + if (to_type == IPIN) { + num_adj += pin_and_chan_adjacent(to_node, from_node); + } else if (to_type == CHANY) { + /* mrFPGA: Xifan TANG */ + if (is_stack) { + if (from_ylow == to_ylow) { + if (to_xhigh == from_xlow-1 || from_xhigh == to_xlow-1) { + num_adj++; + } + } + } else { + /* end */ + /* Original VPR */ + from_yhigh = rr_node[from_node].yhigh; + to_yhigh = rr_node[to_node].yhigh; + if (from_xlow == to_xlow) { + /* UDSD Modification by WMF Begin */ + if (to_yhigh == from_ylow - 1 || from_yhigh == to_ylow - 1) { + num_adj++; + } + /* Overlapping */ + else { + int j; + + for (j = from_ylow; j <= from_yhigh; j++) { + if (j >= to_ylow && j <= to_yhigh) { + num_adj++; + break; + } + } + } + /* UDSD Modification by WMF End */ + } + /* end */ + } + } else if (to_type == CHANX) { + num_adj += chanx_chany_adjacent(to_node, from_node); + } else { + assert(0); + } + break; + + default: + break; + + } + + if (num_adj == 1) + return (TRUE); + else if (num_adj == 0) + return (FALSE); + + vpr_printf(TIO_MESSAGE_ERROR, "in check_adjacent: num_adj = %d. Expected 0 or 1.\n", num_adj); + exit(1); +} + +static int chanx_chany_adjacent(int chanx_node, int chany_node) { + + /* Returns 1 if the specified CHANX and CHANY nodes are adjacent, 0 * + * otherwise. */ + + int chanx_y, chanx_xlow, chanx_xhigh; + int chany_x, chany_ylow, chany_yhigh; + + /* mrFPGA: Xifan TANG */ + if (is_stack) { + if (rr_node[chanx_node].xlow > rr_node[chany_node].xhigh + 1 + || rr_node[chanx_node].xhigh < rr_node[chany_node].xlow) { + return 0; + } + if (rr_node[chany_node].ylow > rr_node[chanx_node].yhigh + 1 + || rr_node[chany_node].yhigh < rr_node[chanx_node].ylow) { + return 0; + } + return 1; + } + /* end */ + /* Original VPR */ + chanx_y = rr_node[chanx_node].ylow; + chanx_xlow = rr_node[chanx_node].xlow; + chanx_xhigh = rr_node[chanx_node].xhigh; + + chany_x = rr_node[chany_node].xlow; + chany_ylow = rr_node[chany_node].ylow; + chany_yhigh = rr_node[chany_node].yhigh; + + if (chany_ylow > chanx_y + 1 || chany_yhigh < chanx_y) + return (0); + + if (chanx_xlow > chany_x + 1 || chanx_xhigh < chany_x) + return (0); + + return (1); + /* end */ +} + +static int pin_and_chan_adjacent(int pin_node, int chan_node) { + + /* Checks if pin_node is adjacent to chan_node. It returns 1 if the two * + * nodes are adjacent and 0 if they are not (any other value means there's * + * a bug in this routine). */ + + int num_adj, pin_xlow, pin_ylow, pin_xhigh, pin_yhigh, chan_xlow, chan_ylow, + chan_xhigh, chan_yhigh; + int pin_ptc, i; + t_rr_type chan_type; + t_type_ptr pin_grid_type; + + num_adj = 0; + pin_xlow = rr_node[pin_node].xlow; + pin_ylow = rr_node[pin_node].ylow; + pin_xhigh = rr_node[pin_node].xhigh; + pin_yhigh = rr_node[pin_node].yhigh; + pin_grid_type = grid[pin_xlow][pin_ylow].type; + pin_ptc = rr_node[pin_node].ptc_num; + chan_type = rr_node[chan_node].type; + chan_xlow = rr_node[chan_node].xlow; + chan_ylow = rr_node[chan_node].ylow; + chan_xhigh = rr_node[chan_node].xhigh; + chan_yhigh = rr_node[chan_node].yhigh; + + if (chan_type == CHANX) { + /* mrFPGA: Xifan TANG */ + if (is_stack) { + for (i = 0; i < pin_grid_type->height; i++) { + /* CHANX below CLB */ + if (pin_grid_type->pinloc[i][BOTTOM][pin_ptc] == 1 + && pin_yhigh > chan_ylow + && pin_ylow <= chan_yhigh + 1 + && pin_xlow == chan_xlow + && pin_xlow == chan_xhigh) { + num_adj++; + } + /* CHANX above CLB */ + if (pin_grid_type->pinloc[i][TOP][pin_ptc] == 1 + && pin_yhigh >= chan_ylow + && pin_ylow <= chan_yhigh + && pin_xlow == chan_xlow + && pin_xlow == chan_xhigh) { + num_adj++; + } + } + } else { + /* end */ + if (chan_ylow == pin_yhigh) { /* CHANX above CLB */ + if (pin_grid_type->pinloc[pin_grid_type->height - 1][TOP][pin_ptc] + == 1 && pin_xlow <= chan_xhigh && pin_xhigh >= chan_xlow) + num_adj++; + } else if (chan_ylow == pin_ylow - 1) { /* CHANX below CLB */ + if (pin_grid_type->pinloc[0][BOTTOM][pin_ptc] == 1 + && pin_xlow <= chan_xhigh && pin_xhigh >= chan_xlow) + num_adj++; + } + } + } else if (chan_type == CHANY) { + /* mrFPGA: Xifan TANG */ + if (is_stack) { + for (i = 0; i < pin_grid_type->height; i++) { + /* CHANY to right of CLB */ + if (pin_grid_type->pinloc[i][RIGHT][pin_ptc] == 1 + && pin_ylow <= chan_yhigh + && pin_yhigh >= chan_ylow + && pin_xlow >= chan_xlow + && pin_xlow <= chan_xhigh) { + num_adj++; + } + /* CHANY to left of CLB */ + if (pin_grid_type->pinloc[i][LEFT][pin_ptc] == 1 + && pin_ylow <= chan_yhigh + && pin_yhigh >= chan_ylow + && pin_xlow > chan_xlow + && pin_xlow <= chan_xhigh + 1) { + num_adj++; + } + } + } else { + /* end */ + for (i = 0; i < pin_grid_type->height; i++) { + if (chan_xlow == pin_xhigh) { /* CHANY to right of CLB */ + if (pin_grid_type->pinloc[i][RIGHT][pin_ptc] == 1 + && pin_ylow <= chan_yhigh && pin_yhigh >= chan_ylow) + num_adj++; + } else if (chan_xlow == pin_xlow - 1) { /* CHANY to left of CLB */ + if (pin_grid_type->pinloc[i][LEFT][pin_ptc] == 1 + && pin_ylow <= chan_yhigh && pin_yhigh >= chan_ylow) + num_adj++; + } + } + } + } + return (num_adj); +} + +static void recompute_occupancy_from_scratch(t_ivec ** clb_opins_used_locally) { + + /* This routine updates the occ field in the rr_node structure according to * + * the resource usage of the current routing. It does a brute force * + * recompute from scratch that is useful for sanity checking. */ + + int inode, inet, iblk, iclass, ipin, num_local_opins; + struct s_trace *tptr; + + /* First set the occupancy of everything to zero. */ + + for (inode = 0; inode < num_rr_nodes; inode++) + rr_node[inode].occ = 0; + + /* Now go through each net and count the tracks and pins used everywhere */ + + for (inet = 0; inet < num_nets; inet++) { + + if (clb_net[inet].is_global) /* Skip global nets. */ + continue; + + tptr = trace_head[inet]; + if (tptr == NULL) + continue; + + for (;;) { + inode = tptr->index; + rr_node[inode].occ++; + + if (rr_node[inode].type == SINK) { + tptr = tptr->next; /* Skip next segment. */ + if (tptr == NULL) + break; + } + + tptr = tptr->next; + } + } + + /* Now update the occupancy of each of the "locally used" OPINs on each CLB * + * (CLB outputs used up by being directly wired to subblocks used only * + * locally). */ + + for (iblk = 0; iblk < num_blocks; iblk++) { + /* Xifan TANG: Bypass pin equivalence auto detect block */ + if (TRUE == block[iblk].type->output_ports_eq_auto_detect) { + continue; + } + /* Original VPR */ + for (iclass = 0; iclass < block[iblk].type->num_class; iclass++) { + num_local_opins = clb_opins_used_locally[iblk][iclass].nelem; + /* Will always be 0 for pads or SINK classes. */ + for (ipin = 0; ipin < num_local_opins; ipin++) { + inode = clb_opins_used_locally[iblk][iclass].list[ipin]; + rr_node[inode].occ++; + } + } + } +} + +static void check_locally_used_clb_opins(t_ivec ** clb_opins_used_locally, + enum e_route_type route_type) { + + /* Checks that enough OPINs on CLBs have been set aside (used up) to make a * + * legal routing if subblocks connect to OPINs directly. */ + + int iclass, iblk, num_local_opins, inode, ipin; + t_rr_type rr_type; + + for (iblk = 0; iblk < num_blocks; iblk++) { + /* Xifan TANG: do not check the class when pin equivalence auto-detect is turned on */ + if (TRUE == block[iblk].type->output_ports_eq_auto_detect) { + continue; + } + + for (iclass = 0; iclass < block[iblk].type->num_class; iclass++) { + num_local_opins = clb_opins_used_locally[iblk][iclass].nelem; + /* Always 0 for pads and for SINK classes */ + + for (ipin = 0; ipin < num_local_opins; ipin++) { + inode = clb_opins_used_locally[iblk][iclass].list[ipin]; + check_node_and_range(inode, route_type); /* Node makes sense? */ + + /* Now check that node is an OPIN of the right type. */ + + rr_type = rr_node[inode].type; + if (rr_type != OPIN) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_locally_used_opins: block #%d (%s)\n", + iblk, block[iblk].name); + vpr_printf(TIO_MESSAGE_ERROR, "\tClass %d local OPIN is wrong rr_type -- rr_node #%d of type %d.\n", + iclass, inode, rr_type); + exit(1); + } + + ipin = rr_node[inode].ptc_num; + if (block[iblk].type->pin_class[ipin] != iclass) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_locally_used_opins: block #%d (%s):\n", + iblk, block[iblk].name); + vpr_printf(TIO_MESSAGE_ERROR, "\tExpected class %d local OPIN has class %d -- rr_node #: %d.\n", + iclass, block[iblk].type->pin_class[ipin], inode); + /* Xifan TANG: reduce this error to warning when multi- fan_in is found */ + //if (1 == rr_node[inode].fan_in) { + exit(1); + //} + } + } + } + } +} + +static void check_node_and_range(int inode, enum e_route_type route_type) { + + /* Checks that inode is within the legal range, then calls check_node to * + * check that everything else about the node is OK. */ + + if (inode < 0 || inode >= num_rr_nodes) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_node_and_range: rr_node #%d is out of legal, range (0 to %d).\n", + inode, num_rr_nodes - 1); + exit(1); + } + check_node(inode, route_type); +} diff --git a/vpr7_rram/vpr/SRC/route/check_route.h b/vpr7_rram/vpr/SRC/route/check_route.h new file mode 100755 index 000000000..106b22d78 --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/check_route.h @@ -0,0 +1,2 @@ +void check_route(enum e_route_type route_type, int num_switch, + t_ivec ** clb_opins_used_locally); diff --git a/vpr7_rram/vpr/SRC/route/check_rr_graph.c b/vpr7_rram/vpr/SRC/route/check_rr_graph.c new file mode 100755 index 000000000..770dc130a --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/check_rr_graph.c @@ -0,0 +1,541 @@ +#include +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph.h" +#include "check_rr_graph.h" + +/* mrFPGA: Xifan TANG */ +#include "mrfpga_globals.h" +/* end */ + +/********************** Local defines and types *****************************/ + +#define BUF_FLAG 1 +#define PTRANS_FLAG 2 +#define BUF_AND_PTRANS_FLAG 3 + +/*********************** Subroutines local to this module *******************/ + +static boolean rr_node_is_global_clb_ipin(int inode); + +static void check_pass_transistors(int from_node); + +/************************ Subroutine definitions ****************************/ + +void check_rr_graph(INP t_graph_type graph_type, INP t_type_ptr types, + INP int L_nx, INP int L_ny, INP int nodes_per_chan, INP int Fs, + INP int num_seg_types, INP int num_switches, + INP t_segment_inf * segment_inf, INP int global_route_switch, + INP int delayless_switch, INP int wire_to_ipin_switch, + t_seg_details * seg_details, int **Fc_in, int **Fc_out, + int *****opin_to_track_map, int *****ipin_to_track_map, + t_ivec **** track_to_ipin_lookup, t_ivec *** switch_block_conn, + boolean * perturb_ipins) { + + int *num_edges_from_current_to_node; /* [0..num_rr_nodes-1] */ + int *total_edges_to_node; /* [0..num_rr_nodes-1] */ + char *switch_types_from_current_to_node; /* [0..num_rr_nodes-1] */ + int inode, iedge, to_node, num_edges; + short switch_type; + t_rr_type rr_type, to_rr_type; + enum e_route_type route_type; + boolean is_fringe_warning_sent; + t_type_ptr type; + + route_type = DETAILED; + if (graph_type == GRAPH_GLOBAL) { + route_type = GLOBAL; + } + + total_edges_to_node = (int *) my_calloc(num_rr_nodes, sizeof(int)); + num_edges_from_current_to_node = (int *) my_calloc(num_rr_nodes, + sizeof(int)); + switch_types_from_current_to_node = (char *) my_calloc(num_rr_nodes, + sizeof(char)); + + for (inode = 0; inode < num_rr_nodes; inode++) { + rr_type = rr_node[inode].type; + num_edges = rr_node[inode].num_edges; + + check_node(inode, route_type); + + /* Check all the connectivity (edges, etc.) information. */ + + for (iedge = 0; iedge < num_edges; iedge++) { + to_node = rr_node[inode].edges[iedge]; + + if (to_node < 0 || to_node >= num_rr_nodes) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_rr_graph: node %d has an edge %d.\n", inode, to_node); + vpr_printf(TIO_MESSAGE_ERROR, "\tEdge is out of range.\n"); + exit(1); + } + + num_edges_from_current_to_node[to_node]++; + total_edges_to_node[to_node]++; + + switch_type = rr_node[inode].switches[iedge]; + + if (switch_type < 0 || switch_type >= num_switches) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_rr_graph: node %d has a switch type %d.\n", inode, switch_type); + vpr_printf(TIO_MESSAGE_ERROR, "\tSwitch type is out of range.\n"); + exit(1); + } + + if (switch_inf[switch_type].buffered) + switch_types_from_current_to_node[to_node] |= BUF_FLAG; + else + switch_types_from_current_to_node[to_node] |= PTRANS_FLAG; + + } /* End for all edges of node. */ + + for (iedge = 0; iedge < num_edges; iedge++) { + to_node = rr_node[inode].edges[iedge]; + + if (num_edges_from_current_to_node[to_node] > 1) { + to_rr_type = rr_node[to_node].type; + + if ((to_rr_type != CHANX && to_rr_type != CHANY) + || (rr_type != CHANX && rr_type != CHANY)) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_rr_graph: node %d connects to node %d %d times.\n", + inode, to_node, num_edges_from_current_to_node[to_node]); + exit(1); + } + + /* Between two wire segments. Two connections are legal only if * + * one connection is a buffer and the other is a pass transistor. */ + + else if (num_edges_from_current_to_node[to_node] != 2 + || switch_types_from_current_to_node[to_node] != BUF_AND_PTRANS_FLAG) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_rr_graph: node %d connects to node %d %d times.\n", + inode, to_node, num_edges_from_current_to_node[to_node]); + exit(1); + } + } + + num_edges_from_current_to_node[to_node] = 0; + switch_types_from_current_to_node[to_node] = 0; + } + + /* Slow test below. Leave commented out most of the time. */ + +#ifdef DEBUG + check_pass_transistors(inode); +#endif + + } /* End for all rr_nodes */ + + /* I built a list of how many edges went to everything in the code above -- * + * now I check that everything is reachable. */ + is_fringe_warning_sent = FALSE; + + for (inode = 0; inode < num_rr_nodes; inode++) { + rr_type = rr_node[inode].type; + + if (rr_type != SOURCE) { + if (total_edges_to_node[inode] < 1 + && !rr_node_is_global_clb_ipin(inode)) { + boolean is_fringe; + boolean is_wire; + boolean is_chain = FALSE; + + /* A global CLB input pin will not have any edges, and neither will * + * a SOURCE or the start of a carry-chain. Anything else is an error. + * For simplicity, carry-chain input pin are entirely ignored in this test + */ + + if(rr_type == IPIN) { + type = grid[rr_node[inode].xlow][rr_node[inode].ylow].type; + if(Fc_in[type->index][rr_node[inode].ptc_num] == 0) { + is_chain = TRUE; + } + } + + is_fringe = (boolean)((rr_node[inode].xlow == 1) + || (rr_node[inode].ylow == 1) + || (rr_node[inode].xhigh == L_nx) + || (rr_node[inode].yhigh == L_ny)); + is_wire = (boolean)(rr_node[inode].type == CHANX + || rr_node[inode].type == CHANY); + + if (!is_chain && !is_fringe && !is_wire) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_rr_graph: node %d has no fanin.\n", inode); + exit(1); + } else if (!is_chain && !is_fringe_warning_sent) { + vpr_printf(TIO_MESSAGE_WARNING, "in check_rr_graph: fringe node %d has no fanin.\n", inode); + vpr_printf(TIO_MESSAGE_WARNING, "\tThis is possible on the fringe for low Fc_out, N, and certain Lengths\n"); + is_fringe_warning_sent = TRUE; + } + } + } + + else { /* SOURCE. No fanin for now; change if feedthroughs allowed. */ + if (total_edges_to_node[inode] != 0) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_rr_graph: SOURCE node %d has a fanin of %d, expected 0.\n", + inode, total_edges_to_node[inode]); + exit(1); + } + } + } + + free(num_edges_from_current_to_node); + free(total_edges_to_node); + free(switch_types_from_current_to_node); +} + +static boolean rr_node_is_global_clb_ipin(int inode) { + + /* Returns TRUE if inode refers to a global CLB input pin node. */ + + int ipin; + t_type_ptr type; + + type = grid[rr_node[inode].xlow][rr_node[inode].ylow].type; + + if (rr_node[inode].type != IPIN) + return (FALSE); + + ipin = rr_node[inode].ptc_num; + + return (type->is_global_pin[ipin]); +} + +void check_node(int inode, enum e_route_type route_type) { + + /* This routine checks that the rr_node is inside the grid and has a valid + * pin number, etc. + */ + + int xlow, ylow, xhigh, yhigh, ptc_num, capacity; + t_rr_type rr_type; + t_type_ptr type; + int nodes_per_chan, tracks_per_node, num_edges, cost_index; + float C, R; + + rr_type = rr_node[inode].type; + xlow = rr_node[inode].xlow; + xhigh = rr_node[inode].xhigh; + ylow = rr_node[inode].ylow; + yhigh = rr_node[inode].yhigh; + ptc_num = rr_node[inode].ptc_num; + capacity = rr_node[inode].capacity; + type = NULL; + + /* mrFPGA: Xifan TANG, check flag*/ + int check_flag; + + if (xlow > xhigh || ylow > yhigh) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: rr endpoints are (%d,%d) and (%d,%d).\n", + xlow, ylow, xhigh, yhigh); + exit(1); + } + + if (xlow < 0 || xhigh > nx + 1 || ylow < 0 || yhigh > ny + 1) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: rr endpoints (%d,%d) and (%d,%d) are out of range.\n", + xlow, ylow, xhigh, yhigh); + exit(1); + } + + if (ptc_num < 0) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) had a ptc_num of %d.\n", + inode, rr_type, ptc_num); + exit(1); + } + + /* Check that the segment is within the array and such. */ + + switch (rr_type) { + + case SOURCE: + case SINK: + case IPIN: + case OPIN: + /* This is used later as well */ + type = grid[xlow][ylow].type; + + if (type == NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: node %d (type %d) is at an illegal clb location (%d, %d).\n", + inode, rr_type, xlow, ylow); + exit(1); + } + if (xlow != xhigh || ylow != (yhigh - type->height + 1)) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: node %d (type %d) has endpoints (%d,%d) and (%d,%d)\n", + inode, rr_type, xlow, ylow, xhigh, yhigh); + exit(1); + } + break; + + case CHANX: + /* Original VPR */ + /* if (xlow < 1 || xhigh > nx || yhigh > ny || yhigh != ylow) { */ + /* end */ + /* mrFPGA : Xifan TANG */ + if (is_stack) { + check_flag = (xlow < 1 || xhigh > nx || yhigh > ny || ylow < 0 || xhigh != xlow); + } else { + check_flag = (xlow < 1 || xhigh > nx || yhigh > ny || yhigh != ylow); + } + if (check_flag) { + /* end */ + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: CHANX out of range for endpoints (%d,%d) and (%d,%d)\n", + xlow, ylow, xhigh, yhigh); + exit(1); + } + if (route_type == GLOBAL && xlow != xhigh) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: node %d spans multiple channel segments (not allowed for global routing).\n", + inode); + exit(1); + } + break; + + case CHANY: + /* Original VPR */ + /*if (xhigh > nx || ylow < 1 || yhigh > ny || xlow != xhigh) { */ + /* end */ + /* mrFPGA : Xifan TANG */ + if (is_stack) { + check_flag = (xhigh > nx || xlow < 0 || ylow < 1 || yhigh > ny || yhigh != ylow); + } else { + check_flag = (xhigh > nx || ylow < 1 || yhigh > ny || xlow != xhigh); + } + if (check_flag) { + /* end */ + vpr_printf(TIO_MESSAGE_ERROR, "Error in check_node: CHANY out of range for endpoints (%d,%d) and (%d,%d)\n", + xlow, ylow, xhigh, yhigh); + exit(1); + } + if (route_type == GLOBAL && ylow != yhigh) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: node %d spans multiple channel segments (not allowed for global routing).\n", + inode); + exit(1); + } + break; + + default: + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: Unexpected segment type: %d\n", rr_type); + exit(1); + } + + /* Check that it's capacities and such make sense. */ + + switch (rr_type) { + + case SOURCE: + + if (ptc_num >= type->num_class + || type->class_inf[ptc_num].type != DRIVER) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) had a ptc_num of %d.\n", + inode, rr_type, ptc_num); + exit(1); + } + if (type->class_inf[ptc_num].num_pins != capacity) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) had a capacity of %d.\n", + inode, rr_type, capacity); + exit(1); + } + break; + + case SINK: + + if (ptc_num >= type->num_class + || type->class_inf[ptc_num].type != RECEIVER) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) had a ptc_num of %d.\n", + inode, rr_type, ptc_num); + exit(1); + } + if (type->class_inf[ptc_num].num_pins != capacity) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) has a capacity of %d.\n", + inode, rr_type, capacity); + exit(1); + } + break; + + case OPIN: + + if (ptc_num >= type->num_pins + || type->class_inf[type->pin_class[ptc_num]].type != DRIVER) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) had a ptc_num of %d.\n", + inode, rr_type, ptc_num); + exit(1); + } + + if (capacity != 1) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) has a capacity of %d.\n", + inode, rr_type, capacity); + exit(1); + } + break; + + case IPIN: + if (ptc_num >= type->num_pins + || type->class_inf[type->pin_class[ptc_num]].type != RECEIVER) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) had a ptc_num of %d.\n", + inode, rr_type, ptc_num); + exit(1); + } + if (capacity != 1) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) has a capacity of %d.\n", + inode, rr_type, capacity); + exit(1); + } + break; + + case CHANX: + if (route_type == DETAILED) { + nodes_per_chan = chan_width_x[ylow]; + tracks_per_node = 1; + } else { + nodes_per_chan = 1; + tracks_per_node = chan_width_x[ylow]; + } + + if (ptc_num >= nodes_per_chan) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) has a ptc_num of %d.\n", + inode, rr_type, ptc_num); + exit(1); + } + + if (capacity != tracks_per_node) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) has a capacity of %d.\n", + inode, rr_type, capacity); + exit(1); + } + break; + + case CHANY: + if (route_type == DETAILED) { + nodes_per_chan = chan_width_y[xlow]; + tracks_per_node = 1; + } else { + nodes_per_chan = 1; + tracks_per_node = chan_width_y[xlow]; + } + + if (ptc_num >= nodes_per_chan) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) has a ptc_num of %d.\n", + inode, rr_type, ptc_num); + exit(1); + } + + if (capacity != tracks_per_node) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) has a capacity of %d.\n", + inode, rr_type, capacity); + exit(1); + } + break; + + default: + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: Unexpected segment type: %d\n", rr_type); + exit(1); + + } + + /* Check that the number of (out) edges is reasonable. */ + num_edges = rr_node[inode].num_edges; + + if (rr_type != SINK && rr_type != IPIN) { + if (num_edges <= 0) { + /* Just a warning, since a very poorly routable rr-graph could have nodes with no edges. * + * If such a node was ever used in a final routing (not just in an rr_graph), other * + * error checks in check_routing will catch it. */ + vpr_printf(TIO_MESSAGE_WARNING, "in check_node: node %d has no edges.\n", inode); + } + } + + else if (rr_type == SINK) { /* SINK -- remove this check if feedthroughs allowed */ + if (num_edges != 0) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: node %d is a sink, but has %d edges.\n", + inode, num_edges); + exit(1); + } + } + + /* Check that the capacitance, resistance and cost_index are reasonable. */ + + C = rr_node[inode].C; + R = rr_node[inode].R; + + if (rr_type == CHANX || rr_type == CHANY) { + if (C < 0. || R < 0.) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: node %d of type %d has R = %g and C = %g.\n", + inode, rr_type, R, C); + exit(1); + } + } + + else { + if (C != 0. || R != 0.) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: node %d of type %d has R = %g and C = %g.\n", + inode, rr_type, R, C); + exit(1); + } + } + + cost_index = rr_node[inode].cost_index; + if (cost_index < 0 || cost_index >= num_rr_indexed_data) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_node: node %d cost index (%d) is out of range.\n", + inode, cost_index); + exit(1); + } +} + +static void check_pass_transistors(int from_node) { + + /* This routine checks that all pass transistors in the routing truly are * + * bidirectional. It may be a slow check, so don't use it all the time. */ + + int from_edge, to_node, to_edge, from_num_edges, to_num_edges; + t_rr_type from_rr_type, to_rr_type; + short from_switch_type; + boolean trans_matched; + + from_rr_type = rr_node[from_node].type; + if (from_rr_type != CHANX && from_rr_type != CHANY) + return; + + from_num_edges = rr_node[from_node].num_edges; + + for (from_edge = 0; from_edge < from_num_edges; from_edge++) { + to_node = rr_node[from_node].edges[from_edge]; + to_rr_type = rr_node[to_node].type; + + if (to_rr_type != CHANX && to_rr_type != CHANY) + continue; + + from_switch_type = rr_node[from_node].switches[from_edge]; + + if (switch_inf[from_switch_type].buffered) + continue; + /* Xifan TANG: Switch Segment Support + * Skip the unbuffer mux as well + */ + if ((FALSE == switch_inf[from_switch_type].buffered)&&(0 == strcmp("unbuf_mux",switch_inf[from_switch_type].type))) { + continue; + } + + + /* We know that we have a pass transitor from from_node to to_node. Now * + * check that there is a corresponding edge from to_node back to * + * from_node. */ + + to_num_edges = rr_node[to_node].num_edges; + trans_matched = FALSE; + + for (to_edge = 0; to_edge < to_num_edges; to_edge++) { + if (rr_node[to_node].edges[to_edge] == from_node + && rr_node[to_node].switches[to_edge] == from_switch_type) { + trans_matched = TRUE; + break; + } + } + + if (trans_matched == FALSE) { + vpr_printf(TIO_MESSAGE_ERROR, "in check_pass_transistors:\n"); + vpr_printf(TIO_MESSAGE_ERROR, "connection from node %d to node %d uses a pass transistor (switch type %d)\n", + from_node, to_node, from_switch_type); + vpr_printf(TIO_MESSAGE_ERROR, "but there is no corresponding pass transistor edge in the other direction.\n"); + exit(1); + } + + } /* End for all from_node edges */ +} diff --git a/vpr7_rram/vpr/SRC/route/check_rr_graph.h b/vpr7_rram/vpr/SRC/route/check_rr_graph.h new file mode 100755 index 000000000..2dd21a124 --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/check_rr_graph.h @@ -0,0 +1,28 @@ +#ifndef CHECK_RR_GRAPH_H +#define CHECK_RR_GRAPH_H + +void check_rr_graph(INP t_graph_type graph_type, + INP t_type_ptr types, + INP int L_nx, + INP int L_ny, + INP int nodes_per_chan, + INP int Fs, + INP int num_seg_types, + INP int num_switches, + INP t_segment_inf * segment_inf, + INP int global_route_switch, + INP int delayless_switch, + INP int wire_to_ipin_switch, + t_seg_details * seg_details, + int ** Fc_in, + int ** Fc_out, + int *****opin_to_track_map, + int *****ipin_to_track_map, + t_ivec **** track_to_ipin_lookup, + t_ivec *** switch_block_conn, + boolean * perturb_ipins); + +void check_node(int inode, enum e_route_type route_type); + +#endif + diff --git a/vpr7_rram/vpr/SRC/route/pb_pin_eq_auto_detect.c b/vpr7_rram/vpr/SRC/route/pb_pin_eq_auto_detect.c new file mode 100644 index 000000000..aa21fe179 --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/pb_pin_eq_auto_detect.c @@ -0,0 +1,791 @@ +/* Xifan TANG: Auto detect the pin equivalence of type_descriptor + * by re-construct the class of pins in type_descriptor + */ +#include +#include +#include +#include +#include "util.h" +#include "vpr_types.h" +#include "physical_types.h" +#include "globals.h" +#include "vpr_utils.h" +#include "rr_graph_util.h" +#include "rr_graph.h" +#include "rr_graph2.h" +#include "linkedlist.h" + +typedef struct s_clb_to_clb_directs { + t_type_descriptor *from_clb_type; + int from_clb_pin_start_index; + int from_clb_pin_end_index; + t_type_descriptor *to_clb_type; + int to_clb_pin_start_index; + int to_clb_pin_end_index; +} t_clb_to_clb_directs; + +typedef struct s_num_mapped_opins_stats t_num_mapped_opins_stats; +struct s_num_mapped_opins_stats{ + int num_mapped_opins; + int net_cnt; +}; + + +/***** Subroutines *****/ + +boolean is_opin_in_direct_list(t_type_ptr cur_type_descriptor, + int opin_index, + int num_directs, + t_clb_to_clb_directs *clb_to_clb_directs) { + int idirect = 0; + + /* Corner case 1: no directs, return false */ + if (0 == num_directs) { + assert(NULL == clb_to_clb_directs); + return FALSE; + } + + for (idirect = 0; idirect < num_directs; idirect++) { + if ((cur_type_descriptor == clb_to_clb_directs[idirect].from_clb_type) + && ((clb_to_clb_directs[idirect].from_clb_pin_start_index < opin_index)||(clb_to_clb_directs[idirect].from_clb_pin_start_index == opin_index)) + && ((opin_index < clb_to_clb_directs[idirect].from_clb_pin_end_index)||(opin_index == clb_to_clb_directs[idirect].from_clb_pin_end_index))) { + return TRUE; + } + } + + return FALSE; +} + + +boolean is_des_rr_node_in_src_rr_node_edges(t_rr_node* src_rr_node, + t_rr_node* des_rr_node) { + int iedge; + boolean found = FALSE; + + for (iedge = 0; iedge < src_rr_node->num_edges; iedge++) { + if (des_rr_node == &(rr_node[src_rr_node->edges[iedge]])) { + found = TRUE; + break; + } + } + + return found; +} + +int alloc_and_add_fully_capacity_rr_edges_to_source_opin(t_type_ptr cur_type_descriptor, + int num_source_rr_node, + t_rr_node** source_rr_node, + t_rr_node** opin_rr_node) { + int ret = 0; + int isrc, iopin, offset, iedge; + + for (isrc = 0; isrc < num_source_rr_node; isrc++) { + source_rr_node[isrc]->capacity = 1; + source_rr_node[isrc]->num_edges = 0; + } + + /* We only do for two parts, first 0... num/2 and num/2 + 1 ... end */ + /* First part */ + for (iopin = 0; iopin < num_source_rr_node / 2; iopin++) { + offset = iopin; + /* Increase fan_in for opin_rr_node[iopin] */ + opin_rr_node[iopin]->fan_in = num_source_rr_node / 2 + 1; + /* Add rr_edges one by one */ + for (isrc = offset; isrc < offset + num_source_rr_node / 2 + 1; isrc++) { + /* Add rr_edges from source_rr_node[isrc] to opin_rr_node[iopin] */ + /* Make sure the to_node is not already in the child edges */ + if (TRUE == is_des_rr_node_in_src_rr_node_edges(source_rr_node[isrc], opin_rr_node[iopin])) { + continue; + } + /* Update fan_in for all the child rr_nodes */ + /* Increase num_edges for source_rr_node[isrc] */ + source_rr_node[isrc]->num_edges++; + source_rr_node[isrc]->edges = (int*)my_realloc(source_rr_node[isrc]->edges, source_rr_node[isrc]->num_edges * sizeof(int)); + source_rr_node[isrc]->switches = (short*)my_realloc(source_rr_node[isrc]->switches, source_rr_node[isrc]->num_edges * sizeof(short)); + source_rr_node[isrc]->edges[source_rr_node[isrc]->num_edges - 1] = opin_rr_node[iopin] - rr_node; + /* Add switches for src_rr_node */ + /* TODO: to be smarter */ + source_rr_node[isrc]->switches[source_rr_node[isrc]->num_edges - 1] = source_rr_node[isrc]->switches[0]; + /* Update capacity for src_rr_node */ + //source_rr_node[isrc]->capacity++; + /* Update counter */ + ret++; + } + } + + /* Second part */ + for (iopin = num_source_rr_node/2; iopin < num_source_rr_node; iopin++) { + offset = iopin - num_source_rr_node / 2; + /* Increase fan_in for opin_rr_node[iopin] */ + opin_rr_node[iopin]->fan_in = num_source_rr_node / 2 + 1; + /* Add rr_edges one by one */ + for (isrc = offset; isrc < offset + num_source_rr_node / 2 + 1; isrc++) { + /* Add rr_edges from source_rr_node[isrc] to opin_rr_node[iopin] */ + /* Make sure the to_node is not already in the child edges */ + if (TRUE == is_des_rr_node_in_src_rr_node_edges(source_rr_node[isrc], opin_rr_node[iopin])) { + continue; + } + /* Update fan_in for all the child rr_nodes */ + /* Increase num_edges for source_rr_node[isrc] */ + source_rr_node[isrc]->num_edges++; + source_rr_node[isrc]->edges = (int*)my_realloc(source_rr_node[isrc]->edges, source_rr_node[isrc]->num_edges * sizeof(int)); + source_rr_node[isrc]->switches = (short*)my_realloc(source_rr_node[isrc]->switches, source_rr_node[isrc]->num_edges * sizeof(short)); + source_rr_node[isrc]->edges[source_rr_node[isrc]->num_edges - 1] = opin_rr_node[iopin] - rr_node; + /* Add switches for src_rr_node */ + /* TODO: to be smarter */ + source_rr_node[isrc]->switches[source_rr_node[isrc]->num_edges - 1] = source_rr_node[isrc]->switches[0]; + /* Update capacity for src_rr_node */ + //source_rr_node[isrc]->capacity++; + /* Update counter */ + ret++; + } + } + + /* Print debug information */ + /* + vpr_printf(TIO_MESSAGE_INFO, "OPIN node:"); + for (iopin = 0; iopin < num_source_rr_node; iopin++) { + vpr_printf(TIO_MESSAGE_INFO, "%d,", opin_rr_node[iopin] - rr_node); + } + vpr_printf(TIO_MESSAGE_INFO, "\n"); + for (isrc = 0; isrc < num_source_rr_node; isrc++) { + vpr_printf(TIO_MESSAGE_INFO, "Source node: index=%d, num_edges=%d.\n", source_rr_node[isrc] - rr_node, source_rr_node[isrc]->num_edges); + vpr_printf(TIO_MESSAGE_INFO, "Edges:"); + for (iedge = 0; iedge < source_rr_node[isrc]->num_edges; iedge++) { + vpr_printf(TIO_MESSAGE_INFO, "%d,", source_rr_node[isrc]->edges[iedge]); + } + vpr_printf(TIO_MESSAGE_INFO, "\n"); + } + */ + + return ret; +} + +/* Build arrays for all the SOURCE rr_nodes, OPIN rr_nodes of a grid + * Also build arrays for all the OUT_PORT pb_graph_pins corresponding to SINK and OPIN + */ +int alloc_and_add_fully_capacity_rr_edges_to_one_grid(int grid_x, int grid_y, int grid_z, + t_block* cur_block, + t_ivec*** LL_rr_node_indices, + int num_directs, + t_clb_to_clb_directs *clb_to_clb_directs) { + int ret = 0; + int ipin, iclass, offset, inode; + t_type_ptr grid_type_descriptor = NULL; + t_pb_graph_node* top_pb_graph_node = NULL; + int num_opin_rr_nodes = 0; + int num_source_rr_nodes = 0; + t_rr_node** opin_rr_node = NULL; + t_rr_node** source_rr_node = NULL; + + /* Check */ + assert((!(0 > grid_x))&&(!(grid_x > (nx + 1)))); + assert((!(0 > grid_y))&&(!(grid_y > (ny + 1)))); + + /* Get grid type descriptor */ + grid_type_descriptor = grid[grid_x][grid_y].type; + top_pb_graph_node = grid[grid_x][grid_y].type->pb_graph_head; + + /* Check */ + assert(NULL != grid_type_descriptor); + assert(NULL != top_pb_graph_node); + + /* Search all the OPIN rr_nodes */ + for (ipin = 0; ipin < grid_type_descriptor->num_pins; ipin++) { + iclass = grid_type_descriptor->pin_class[ipin]; + /* Skip IPINs */ + if (DRIVER != grid_type_descriptor->class_inf[iclass].type) { + continue; + } + /* Skip direct pins */ + if (TRUE == is_opin_in_direct_list(grid_type_descriptor, ipin, num_directs, clb_to_clb_directs)) { + continue; + } + /* Get SOURCE rr_nodes */ + inode = get_rr_node_index(grid_x, grid_y, OPIN, + ipin, LL_rr_node_indices); + /* Check */ + assert((-1 < inode)&&(inode < num_rr_nodes)); + /* Update counter */ + num_opin_rr_nodes++; + } + + for (iclass = 0; iclass < grid_type_descriptor->num_class; iclass++) { + /* Skip IPINs */ + if (DRIVER != grid_type_descriptor->class_inf[iclass].type) { + continue; + } + /* Get SOURCE rr_node */ + inode = get_rr_node_index(grid_x, grid_y, SOURCE, + iclass, LL_rr_node_indices); + /* Check */ + assert((-1 < inode)&&(inode < num_rr_nodes)); + if (1 < rr_node[inode].num_edges) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])When output pin logic equivalence auto-detect is turned on.\nLogic equivalence of outputs should not be defined in arch. XML (type name: %s).\n", + __FILE__, __LINE__, grid_type_descriptor->name); + exit(1); + } + /* Skip direct pins */ + if (TRUE == is_opin_in_direct_list(grid_type_descriptor, rr_node[rr_node[inode].edges[0]].ptc_num, num_directs, clb_to_clb_directs)) { + continue; + } + /* Update counter */ + num_source_rr_nodes++; + } + + /* Check ? num_opin_rr_nodes == num_source_rr_nodes */ + if (num_opin_rr_nodes != num_source_rr_nodes) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])When output pin logic equivalence auto-detect is turned on.\nLogic equivalence of outputs should not be defined in arch. XML (type name: %s).\n", + __FILE__, __LINE__, grid_type_descriptor->name); + exit(1); + } + + /* Allocate */ + opin_rr_node = (t_rr_node**)my_malloc(num_opin_rr_nodes * sizeof(t_rr_node*)); + source_rr_node = (t_rr_node**)my_malloc(num_source_rr_nodes * sizeof(t_rr_node*)); + + /* Fill the array */ + offset = 0; + for (ipin = 0; ipin < grid_type_descriptor->num_pins; ipin++) { + iclass = grid_type_descriptor->pin_class[ipin]; + if (DRIVER != grid_type_descriptor->class_inf[iclass].type) { + continue; + } + /* Skip direct pins */ + if (TRUE == is_opin_in_direct_list(grid_type_descriptor, ipin, num_directs, clb_to_clb_directs)) { + continue; + } + /* Get SOURCE rr_nodes */ + inode = get_rr_node_index(grid_x, grid_y, OPIN, + ipin, LL_rr_node_indices); + /* Check */ + assert((-1 < inode)&&(inode < num_rr_nodes)); + assert(1 == rr_node[inode].fan_in); + /* Fill opin_rr_node array */ + opin_rr_node[offset] = &(rr_node[inode]); + offset++; + } + assert(offset == num_opin_rr_nodes); + + /* Fill the array */ + offset = 0; + for (iclass = 0; iclass < grid_type_descriptor->num_class; iclass++) { + if (DRIVER != grid_type_descriptor->class_inf[iclass].type) { + continue; + } + /* Get SOURCE rr_node */ + inode = get_rr_node_index(grid_x, grid_y, SOURCE, + iclass, LL_rr_node_indices); + /* Check */ + assert((-1 < inode)&&(inode < num_rr_nodes)); + if (1 < rr_node[inode].num_edges) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])When output pin logic equivalence auto-detect is turned on.\nLogic equivalence of outputs should not be defined in arch. XML (type name: %s).\n", + __FILE__, __LINE__, grid_type_descriptor->name); + exit(1); + } + /* Skip direct pins */ + if (TRUE == is_opin_in_direct_list(grid_type_descriptor, rr_node[rr_node[inode].edges[0]].ptc_num, num_directs, clb_to_clb_directs)) { + continue; + } + /* Fill opin_rr_node array */ + source_rr_node[offset] = &(rr_node[inode]); + offset++; + } + assert(offset == num_source_rr_nodes); + + /* Add full-capacity network between the two arrays */ + ret += alloc_and_add_fully_capacity_rr_edges_to_source_opin(grid_type_descriptor, num_source_rr_nodes, source_rr_node, opin_rr_node); + + /* Update num_pins in the class */ + for (inode = 0; inode < num_source_rr_nodes; inode++) { + iclass = source_rr_node[inode]->ptc_num; + if (DRIVER != grid_type_descriptor->class_inf[iclass].type) { + continue; + } + /* Skip direct pins */ + if (TRUE == is_opin_in_direct_list(grid_type_descriptor, opin_rr_node[inode]->ptc_num, num_directs, clb_to_clb_directs)) { + continue; + } + grid_type_descriptor->class_inf[iclass].num_pins = source_rr_node[inode]->capacity; + } + + /* Free */ + if (NULL != opin_rr_node) { + free(opin_rr_node); + } + if (NULL != source_rr_node) { + free(source_rr_node); + } + + return ret; +} + +/* Find the corresponding pb_graph_pin in a CLB with a net_num */ + +/* Top-level function + * Add additional edges for all the SOURCE rr_nodes with a net num + */ +int alloc_and_add_grids_fully_capacity_rr_edges(t_ivec*** LL_rr_node_indices, + int num_directs, + t_clb_to_clb_directs *clb_to_clb_directs) { + int ix, iy, iz, iblk, used_blk_id; + t_block* mapped_block = NULL; + int ret = 0; + + /* Go by grid to grid */ + for (ix = 0; ix < (nx + 2); ix++) { + for (iy = 0; iy < (ny + 2); iy++) { + /* Skip EMPTY_TYPE */ + if (EMPTY_TYPE == grid[ix][iy].type) { + continue; + } + /* Skip IO_TYPE */ + if (IO_TYPE == grid[ix][iy].type) { + continue; + } + /* We only care core grids */ + /* If not specified, we do not modify anything */ + if (FALSE == grid[ix][iy].type->output_ports_eq_auto_detect) { + continue; + } + for (iz = 0; iz < grid[ix][iy].type->capacity; iz++) { + /* Try to identify if this z block is used or not */ + mapped_block = NULL; + for (iblk = 0; iblk < grid[ix][iy].usage; iblk++) { + used_blk_id = grid[ix][iy].blocks[iblk]; + if (iz == block[used_blk_id].z) { + mapped_block = &(block[used_blk_id]); + break; + } + } + /* Allocate the add edges to this source node */ + ret += alloc_and_add_fully_capacity_rr_edges_to_one_grid(ix, iy, iz, mapped_block, LL_rr_node_indices, num_directs, clb_to_clb_directs); + } + } + } + + return ret; +} + +/* Detect which OPINs are used and update routing cost */ +void auto_detect_and_reserve_used_opins(float pres_fac) { + return; +} + +/* Search the linked list first, + * 1. If we find a matched element, increase the counter + * 2. if we cannot find, allocate a new element and initialize the counter + */ +t_llist* search_and_add_num_mapped_opin_llist(t_llist* head, + int cand_num_mapped_opins) { + + t_llist* new_head = NULL; + t_llist* temp = NULL; + t_num_mapped_opins_stats* cur_stats = NULL; + boolean found = FALSE; + + /* Search the linked list, try to find a matched element */ + temp = head; + while (temp) { + assert(NULL != temp->dptr); + cur_stats = (t_num_mapped_opins_stats*)(temp->dptr); + /* Find what we want! */ + if (cand_num_mapped_opins == cur_stats->num_mapped_opins) { + found = TRUE; + /* update counter */ + cur_stats->net_cnt++; + } + /* go to next */ + temp = temp->next; + } + + /* decide the next step */ + if (TRUE == found) { + /* We do not allocate anything, return the old head */ + return head; + } + + /* Initialize the data */ + cur_stats = (t_num_mapped_opins_stats*)my_malloc(sizeof(t_num_mapped_opins_stats)); + cur_stats->num_mapped_opins = cand_num_mapped_opins; + cur_stats->net_cnt = 1; + + /* Reach here. We need to allocate a new node */ + if (NULL == head) { + /* Empty llist, create a new llist, containing 1 node */ + new_head = create_llist(1); + new_head->dptr = (void*)(cur_stats); + } else { + /* Creata a new node */ + insert_llist_node(head); + head->next->dptr = (void*)(cur_stats); + new_head = head; + } + + return new_head; +} + +/* Print the stats, and once we print one node, we remove and free it */ +void print_net_opin_llist(t_llist* head) { + t_llist* cur_head = head; + t_llist* temp = NULL; + t_llist* min_node = NULL; + t_num_mapped_opins_stats* cur_stats = NULL; + + vpr_printf(TIO_MESSAGE_INFO, "Stats for OPIN occupancy: (number of nets = %d)\n", num_nets); + + /* Loop until the llist is empty */ + while (1) { + temp = cur_head; + /* Initialize min_node */ + min_node = NULL; + cur_stats = NULL; + /* each time, we find the lowest num_mapped_opins and print the node*/ + while (temp) { + assert(NULL != temp->dptr); + cur_stats = (t_num_mapped_opins_stats*)(temp->dptr); + if ((NULL == min_node)||(((t_num_mapped_opins_stats*)(min_node->dptr))->num_mapped_opins > cur_stats->num_mapped_opins)) { + min_node = temp; + } + /* go to next */ + temp = temp->next; + } + /* No min_node, the llist is empty */ + if (NULL == min_node) { + break; + } + /* Print */ + cur_stats = (t_num_mapped_opins_stats*)(min_node->dptr); + vpr_printf(TIO_MESSAGE_INFO, "\t%d (%g%) Nets is mapped to %d OPINs.\n", + cur_stats->net_cnt, + (float)(100 * cur_stats->net_cnt / num_nets), + cur_stats->num_mapped_opins); + /* Remove the node we find */ + /* If this is the head */ + if (min_node == cur_head) { + cur_head = cur_head->next; + free(min_node->dptr); + free(min_node); + continue; + } + /* Otherwise, we need a traversal */ + temp = cur_head; + while (temp) { + if (min_node == temp->next) { + free(min_node->dptr); + remove_llist_node(temp); + break; + } + /* go to next */ + temp = temp->next; + } + } + + return; +} + +/* Reset all the net_num of rr_nodes and update them according to routing results */ +void reassign_rr_node_net_num_from_scratch() { + + /* This routine updates the occ field in the rr_node structure according to * + * the resource usage of the current routing. It does a brute force * + * recompute from scratch that is useful for sanity checking. */ + + int inode, inet; + struct s_trace *tptr; + + /* First set the occupancy of everything to zero. */ + + for (inode = 0; inode < num_rr_nodes; inode++) + rr_node[inode].net_num = OPEN; + + /* Now go through each net and count the tracks and pins used everywhere */ + + for (inet = 0; inet < num_nets; inet++) { + + if (clb_net[inet].is_global) /* Skip global nets. */ + continue; + + tptr = trace_head[inet]; + if (tptr == NULL) + continue; + + for (;;) { + inode = tptr->index; + rr_node[inode].net_num = inet; + + if (rr_node[inode].type == SINK) { + tptr = tptr->next; /* Skip next segment. */ + if (tptr == NULL) + break; + } + + tptr = tptr->next; + } + } + + return; +} + + +/* Xifan TANG: Statisitcs for each net which has occupied more than 1 OPIN */ +void print_net_opin_occupancy() { + int inode, inet; + t_llist* head = NULL; + + reassign_rr_node_net_num_from_scratch(); + + /* Initialize counters */ + for (inet = 0; inet < num_nets; inet++) { + clb_net[inet].num_mapped_opins = 0; + } + + /* Search each OPIN in the rr_graph */ + for (inode = 0; inode < num_rr_nodes; inode++) { + if (OPIN != rr_node[inode].type) { + continue; + } + /* Find the net_num */ + inet = rr_node[inode].net_num; + if (OPEN == inet) { + continue; + } + /* Update the counter in clb_net */ + assert((-1 < inet)&&(inet < num_nets)); + clb_net[inet].num_mapped_opins++; + } + + /* Print stats */ + for (inet = 0; inet < num_nets; inet++) { + /* Global nets is not routed, set to 0 */ + if (TRUE == clb_net[inet].is_global) { + clb_net[inet].num_mapped_opins = 0; + } + /* Search in the linked list if there exists an element witht the same num_mapped_opins */ + head = search_and_add_num_mapped_opin_llist(head, clb_net[inet].num_mapped_opins); + } + + /* Print */ + print_net_opin_llist(head); + + /* Free */ + + return; +} + + +/* Functions to add fully-capable routing network to a SB connections */ +/* Add edges to a CHANX|CHANY node, establishing connections to a OPIN node list */ +int add_opin_rr_edges_to_chan_rr_node(t_rr_node* chan_rr_node, + int num_opin_rr_nodes, + t_rr_node** opin_rr_node) { + int inode; + int ret = 0; + + /* Check */ + assert((CHANX == chan_rr_node->type)||(CHANY == chan_rr_node->type)); + for (inode = 0; inode < num_opin_rr_nodes; inode++) { + assert(OPIN == opin_rr_node[inode]->type); + } + + for (inode = 0; inode < num_opin_rr_nodes; inode++) { + /* 1. For each OPIN_rr_node, check if the chan_rr_node is already connected ! */ + if (TRUE == is_des_rr_node_in_src_rr_node_edges(opin_rr_node[inode], chan_rr_node)) { + continue; /* Bypass this opin_rr_node then */ + } + /* 2. Reach here implying a new edge is needed */ + /* Update fan-in */ + chan_rr_node->fan_in++; + /* Reallocate the edges */ + /* Increase num_edges for source_rr_node[isrc] */ + opin_rr_node[inode]->num_edges++; + opin_rr_node[inode]->edges = (int*)my_realloc(opin_rr_node[inode]->edges, opin_rr_node[inode]->num_edges * sizeof(int)); + opin_rr_node[inode]->switches = (short*)my_realloc(opin_rr_node[inode]->switches, opin_rr_node[inode]->num_edges * sizeof(short)); + opin_rr_node[inode]->edges[opin_rr_node[inode]->num_edges - 1] = chan_rr_node - rr_node; + /* Add switches for src_rr_node */ + /* TODO: to be smarter */ + opin_rr_node[inode]->switches[opin_rr_node[inode]->num_edges - 1] = opin_rr_node[inode]->switches[0]; + /* Update counter */ + ret++; + } + + return ret; +} + +/* For the OPINs in each block that turns on output_ports_eq_auto_detect + * 1. Gather OPIN rr_nodes + * 2. Find the CHANX or CHANY that is driven by OPINs + * 3. For each CHANX|CHANY, create a opin_rr_node list + * 4. Add rr_edges + */ +int alloc_and_add_fully_capacity_sb_rr_edges_to_one_grid(int grid_x, int grid_y, int grid_z, + t_block* cur_block, + t_ivec*** LL_rr_node_indices, + int num_directs, + t_clb_to_clb_directs *clb_to_clb_directs) { + int ret = 0; + int ipin, offset, from_node, to_node, inode, iedge, iclass; + t_type_ptr grid_type_descriptor = NULL; + t_pb_graph_node* top_pb_graph_node = NULL; + int num_opin_rr_nodes = 0; + int num_chan_rr_nodes = 0; + t_rr_node** opin_rr_node = NULL; + t_rr_node** chan_rr_node = NULL; + boolean is_in_list = FALSE; + + /* Check */ + assert((!(0 > grid_x))&&(!(grid_x > (nx + 1)))); + assert((!(0 > grid_y))&&(!(grid_y > (ny + 1)))); + + /* Get grid type descriptor */ + grid_type_descriptor = grid[grid_x][grid_y].type; + top_pb_graph_node = grid[grid_x][grid_y].type->pb_graph_head; + + /* Check */ + assert(NULL != grid_type_descriptor); + assert(NULL != top_pb_graph_node); + + /* 1. Gather OPIN rr_nodes */ + num_opin_rr_nodes = 0; + /* Search all the OPIN rr_nodes */ + for (ipin = 0; ipin < grid_type_descriptor->num_pins; ipin++) { + iclass = grid_type_descriptor->pin_class[ipin]; + /* Skip IPINs */ + if (DRIVER != grid_type_descriptor->class_inf[iclass].type) { + continue; + } + /* Skip direct pins */ + if (TRUE == is_opin_in_direct_list(grid_type_descriptor, ipin, num_directs, clb_to_clb_directs)) { + continue; + } + /* Get SOURCE rr_nodes */ + inode = get_rr_node_index(grid_x, grid_y, OPIN, + ipin, LL_rr_node_indices); + /* Check */ + assert((-1 < inode)&&(inode < num_rr_nodes)); + /* Update counter */ + num_opin_rr_nodes++; + } + /* Allocate */ + opin_rr_node = (t_rr_node**)my_malloc(num_opin_rr_nodes * sizeof(t_rr_node*)); + + /* Fill the array */ + offset = 0; + for (ipin = 0; ipin < grid_type_descriptor->num_pins; ipin++) { + iclass = grid_type_descriptor->pin_class[ipin]; + /* Skip IPINs */ + if (DRIVER != grid_type_descriptor->class_inf[iclass].type) { + continue; + } + /* Skip direct pins */ + if (TRUE == is_opin_in_direct_list(grid_type_descriptor, ipin, num_directs, clb_to_clb_directs)) { + continue; + } + /* Get SOURCE rr_nodes */ + inode = get_rr_node_index(grid_x, grid_y, OPIN, + ipin, LL_rr_node_indices); + /* Check */ + assert((-1 < inode)&&(inode < num_rr_nodes)); + /* Update counter */ + /* Fill opin_rr_node array */ + opin_rr_node[offset] = &(rr_node[inode]); + offset++; + } + assert(offset == num_opin_rr_nodes); + + /* 2. Get chan_rr_nodes */ + /* Get the CHANX or CHANY that each OPIN rr_node is driving */ + for (from_node = 0; from_node < num_opin_rr_nodes; from_node++) { + /* Initialize chan_rr_node */ + num_chan_rr_nodes = 0; + chan_rr_node = NULL; + for (iedge = 0; iedge < opin_rr_node[from_node]->num_edges; iedge++) { + /* if CHANX or CHANY, increase the counter */ + to_node = opin_rr_node[from_node]->edges[iedge]; + if ((CHANX != rr_node[to_node].type) + &&(CHANY != rr_node[to_node].type)) { + continue; + } + /* Check */ + assert((CHANX == rr_node[to_node].type)||(CHANY == rr_node[to_node].type)); + /* Check if this node is already inside the list */ + is_in_list = FALSE; + for (inode = 0; inode < num_chan_rr_nodes; inode++) { + if (&(rr_node[to_node]) == chan_rr_node[inode]) { + is_in_list = TRUE; + break; + } + } + if (TRUE == is_in_list) { + continue; + } + /* Increase the counter and reallocate */ + num_chan_rr_nodes++; + /* Allocate */ + chan_rr_node = (t_rr_node**)my_realloc(chan_rr_node, num_chan_rr_nodes * sizeof(t_rr_node*)); + /* Update the array */ + chan_rr_node[num_chan_rr_nodes - 1] = &(rr_node[to_node]); + } + /* Add edges */ + /* generate offset */ + if (from_node < num_opin_rr_nodes / 2) { + offset = from_node; + } else { + offset = from_node - num_opin_rr_nodes / 2; + } + for (inode = 0; inode < num_chan_rr_nodes; inode++) { + ret += add_opin_rr_edges_to_chan_rr_node(chan_rr_node[inode], num_opin_rr_nodes / 2 + 1, opin_rr_node + offset); + } + /* Free */ + if (NULL != chan_rr_node) { + free(chan_rr_node); + } + } + + /* Free */ + if (NULL != opin_rr_node) { + free(opin_rr_node); + } + + return ret; +} + + +int alloc_and_add_grids_fully_capacity_sb_rr_edges(t_ivec*** LL_rr_node_indices, + int num_directs, + t_clb_to_clb_directs *clb_to_clb_directs) { + int ix, iy, iz, iblk, used_blk_id; + t_block* mapped_block = NULL; + int ret = 0; + + /* Go by grid to grid */ + for (ix = 0; ix < (nx + 2); ix++) { + for (iy = 0; iy < (ny + 2); iy++) { + /* Skip IO_TYPE */ + if (IO_TYPE == grid[ix][iy].type) { + continue; + } + /* We only care core grids */ + /* If not specified, we do not modify anything */ + if (FALSE == grid[ix][iy].type->output_ports_eq_auto_detect) { + continue; + } + for (iz = 0; iz < grid[ix][iy].type->capacity; iz++) { + /* Try to identify if this z block is used or not */ + mapped_block = NULL; + for (iblk = 0; iblk < grid[ix][iy].usage; iblk++) { + used_blk_id = grid[ix][iy].blocks[iblk]; + if (iz == block[used_blk_id].z) { + mapped_block = &(block[used_blk_id]); + break; + } + } + /* Allocate the add edges to this source node */ + ret += alloc_and_add_fully_capacity_sb_rr_edges_to_one_grid(ix, iy, iz, mapped_block, LL_rr_node_indices, num_directs, clb_to_clb_directs); + } + } + } + + return ret; +} + diff --git a/vpr7_rram/vpr/SRC/route/pb_pin_eq_auto_detect.h b/vpr7_rram/vpr/SRC/route/pb_pin_eq_auto_detect.h new file mode 100644 index 000000000..14656fbd5 --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/pb_pin_eq_auto_detect.h @@ -0,0 +1,15 @@ + +#ifndef PB_PIN_EQ_AUTO_DETECT_H +#define PB_PIN_EQ_AUTO_DETECT_H +int alloc_and_add_grids_fully_capacity_rr_edges(t_ivec*** LL_rr_node_indices, + int num_directs, + t_clb_to_clb_directs *clb_to_clb_directs); + +void print_net_opin_occupancy(); + +void auto_detect_and_reserve_used_opins(float pres_fac); + +int alloc_and_add_grids_fully_capacity_sb_rr_edges(t_ivec*** LL_rr_node_indices, + int num_directs, + t_clb_to_clb_directs *clb_to_clb_directs); +#endif diff --git a/vpr7_rram/vpr/SRC/route/route_breadth_first.c b/vpr7_rram/vpr/SRC/route/route_breadth_first.c new file mode 100755 index 000000000..c4c750c0c --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/route_breadth_first.c @@ -0,0 +1,305 @@ +#include +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "route_export.h" +#include "route_common.h" +#include "route_breadth_first.h" + +/********************* Subroutines local to this module *********************/ + +static boolean breadth_first_route_net(int inet, float bend_cost); + +static void breadth_first_expand_trace_segment(struct s_trace *start_ptr, + int remaining_connections_to_sink); + +static void breadth_first_expand_neighbours(int inode, float pcost, int inet, + float bend_cost); + +static void breadth_first_add_source_to_heap(int inet); + +/************************ Subroutine definitions ****************************/ + +boolean try_breadth_first_route(struct s_router_opts router_opts, + t_ivec ** clb_opins_used_locally, int width_fac) { + + /* Iterated maze router ala Pathfinder Negotiated Congestion algorithm, * + * (FPGA 95 p. 111). Returns TRUE if it can route this FPGA, FALSE if * + * it can't. */ + + float pres_fac; + boolean success, is_routable, rip_up_local_opins; + int itry, inet; + + /* Usually the first iteration uses a very small (or 0) pres_fac to find * + * the shortest path and get a congestion map. For fast compiles, I set * + * pres_fac high even for the first iteration. */ + + pres_fac = router_opts.first_iter_pres_fac; + + for (itry = 1; itry <= router_opts.max_router_iterations; itry++) { + + for (inet = 0; inet < num_nets; inet++) { + if (clb_net[inet].is_global == FALSE) { /* Skip global nets. */ + + pathfinder_update_one_cost(trace_head[inet], -1, pres_fac); + + is_routable = breadth_first_route_net(inet, + router_opts.bend_cost); + + /* Impossible to route? (disconnected rr_graph) */ + + if (!is_routable) { + vpr_printf(TIO_MESSAGE_INFO, "Routing failed.\n"); + return (FALSE); + } + + pathfinder_update_one_cost(trace_head[inet], 1, pres_fac); + + } + } + + /* Make sure any CLB OPINs used up by subblocks being hooked directly * + * to them are reserved for that purpose. */ + + if (itry == 1) + rip_up_local_opins = FALSE; + else + rip_up_local_opins = TRUE; + + reserve_locally_used_opins(pres_fac, rip_up_local_opins, + clb_opins_used_locally); + + success = feasible_routing(); + if (success) { + vpr_printf(TIO_MESSAGE_INFO, "Successfully routed after %d routing iterations.\n", itry); + return (TRUE); + } + + if (itry == 1) + pres_fac = router_opts.initial_pres_fac; + else + pres_fac *= router_opts.pres_fac_mult; + + pres_fac = std::min(pres_fac, static_cast(HUGE_POSITIVE_FLOAT / 1e5)); + + pathfinder_update_cost(pres_fac, router_opts.acc_fac); + } + + vpr_printf(TIO_MESSAGE_INFO, "Routing failed.\n"); + return (FALSE); +} + +static boolean breadth_first_route_net(int inet, float bend_cost) { + + /* Uses a maze routing (Dijkstra's) algorithm to route a net. The net * + * begins at the net output, and expands outward until it hits a target * + * pin. The algorithm is then restarted with the entire first wire segment * + * included as part of the source this time. For an n-pin net, the maze * + * router is invoked n-1 times to complete all the connections. Inet is * + * the index of the net to be routed. Bends are penalized by bend_cost * + * (which is typically zero for detailed routing and nonzero only for global * + * routing), since global routes with lots of bends are tougher to detailed * + * route (using a detailed router like SEGA). * + * If this routine finds that a net *cannot* be connected (due to a complete * + * lack of potential paths, rather than congestion), it returns FALSE, as * + * routing is impossible on this architecture. Otherwise it returns TRUE. */ + + int i, inode, prev_node, remaining_connections_to_sink; + float pcost, new_pcost; + struct s_heap *current; + struct s_trace *tptr; + + free_traceback(inet); + breadth_first_add_source_to_heap(inet); + mark_ends(inet); + + tptr = NULL; + remaining_connections_to_sink = 0; + + for (i = 1; i <= clb_net[inet].num_sinks; i++) { /* Need n-1 wires to connect n pins */ + breadth_first_expand_trace_segment(tptr, remaining_connections_to_sink); + current = get_heap_head(); + + if (current == NULL) { /* Infeasible routing. No possible path for net. */ + vpr_printf (TIO_MESSAGE_INFO, "Cannot route net #%d (%s) to sink #%d -- no possible path.\n", + inet, clb_net[inet].name, i); + reset_path_costs(); /* Clean up before leaving. */ + return (FALSE); + } + + inode = current->index; + + while (rr_node_route_inf[inode].target_flag == 0) { + pcost = rr_node_route_inf[inode].path_cost; + new_pcost = current->cost; + if (pcost > new_pcost) { /* New path is lowest cost. */ + rr_node_route_inf[inode].path_cost = new_pcost; + prev_node = current->u.prev_node; + rr_node_route_inf[inode].prev_node = prev_node; + rr_node_route_inf[inode].prev_edge = current->prev_edge; + + if (pcost > 0.99 * HUGE_POSITIVE_FLOAT) /* First time touched. */ + add_to_mod_list(&rr_node_route_inf[inode].path_cost); + + breadth_first_expand_neighbours(inode, new_pcost, inet, + bend_cost); + } + + free_heap_data(current); + current = get_heap_head(); + + if (current == NULL) { /* Impossible routing. No path for net. */ + vpr_printf (TIO_MESSAGE_INFO, "Cannot route net #%d (%s) to sink #%d -- no possible path.\n", + inet, clb_net[inet].name, i); + reset_path_costs(); + return (FALSE); + } + + inode = current->index; + } + + rr_node_route_inf[inode].target_flag--; /* Connected to this SINK. */ + remaining_connections_to_sink = rr_node_route_inf[inode].target_flag; + tptr = update_traceback(current, inet); + free_heap_data(current); + } + + empty_heap(); + reset_path_costs(); + return (TRUE); +} + +static void breadth_first_expand_trace_segment(struct s_trace *start_ptr, + int remaining_connections_to_sink) { + + /* Adds all the rr_nodes in the traceback segment starting at tptr (and * + * continuing to the end of the traceback) to the heap with a cost of zero. * + * This allows expansion to begin from the existing wiring. The * + * remaining_connections_to_sink value is 0 if the route segment ending * + * at this location is the last one to connect to the SINK ending the route * + * segment. This is the usual case. If it is not the last connection this * + * net must make to this SINK, I have a hack to ensure the next connection * + * to this SINK goes through a different IPIN. Without this hack, the * + * router would always put all the connections from this net to this SINK * + * through the same IPIN. With LUTs or cluster-based logic blocks, you * + * should never have a net connecting to two logically-equivalent pins on * + * the same logic block, so the hack will never execute. If your logic * + * block is an and-gate, however, nets might connect to two and-inputs on * + * the same logic block, and since the and-inputs are logically-equivalent, * + * this means two connections to the same SINK. */ + + struct s_trace *tptr, *next_ptr; + int inode, sink_node, last_ipin_node; + + tptr = start_ptr; + if(tptr != NULL && rr_node[tptr->index].type == SINK) { + /* During logical equivalence case, only use one opin */ + tptr = tptr->next; + } + + if (remaining_connections_to_sink == 0) { /* Usual case. */ + while (tptr != NULL) { + node_to_heap(tptr->index, 0., NO_PREVIOUS, NO_PREVIOUS, OPEN, OPEN); + tptr = tptr->next; + } + } + + else { /* This case never executes for most logic blocks. */ + + /* Weird case. Lots of hacks. The cleanest way to do this would be to empty * + * the heap, update the congestion due to the partially-completed route, put * + * the whole route so far (excluding IPINs and SINKs) on the heap with cost * + * 0., and expand till you hit the next SINK. That would be slow, so I * + * do some hacks to enable incremental wavefront expansion instead. */ + + if (tptr == NULL) + return; /* No route yet */ + + next_ptr = tptr->next; + last_ipin_node = OPEN; /* Stops compiler from complaining. */ + + /* Can't put last SINK on heap with NO_PREVIOUS, etc, since that won't let * + * us reach it again. Instead, leave the last traceback element (SINK) off * + * the heap. */ + + while (next_ptr != NULL) { + inode = tptr->index; + node_to_heap(inode, 0., NO_PREVIOUS, NO_PREVIOUS, OPEN, OPEN); + + if (rr_node[inode].type == IPIN) + last_ipin_node = inode; + + tptr = next_ptr; + next_ptr = tptr->next; + } + + /* This will stop the IPIN node used to get to this SINK from being * + * reexpanded for the remainder of this net's routing. This will make us * + * hook up more IPINs to this SINK (which is what we want). If IPIN * + * doglegs are allowed in the graph, we won't be able to use this IPIN to * + * do a dogleg, since it won't be re-expanded. Shouldn't be a big problem. */ + + rr_node_route_inf[last_ipin_node].path_cost = -HUGE_POSITIVE_FLOAT; + + /* Also need to mark the SINK as having high cost, so another connection can * + * be made to it. */ + + sink_node = tptr->index; + rr_node_route_inf[sink_node].path_cost = HUGE_POSITIVE_FLOAT; + + /* Finally, I need to remove any pending connections to this SINK via the * + * IPIN I just used (since they would result in congestion). Scan through * + * the heap to do this. */ + + invalidate_heap_entries(sink_node, last_ipin_node); + } +} + +static void breadth_first_expand_neighbours(int inode, float pcost, int inet, + float bend_cost) { + + /* Puts all the rr_nodes adjacent to inode on the heap. rr_nodes outside * + * the expanded bounding box specified in route_bb are not added to the * + * heap. pcost is the path_cost to get to inode. */ + + int iconn, to_node, num_edges; + t_rr_type from_type, to_type; + float tot_cost; + + num_edges = rr_node[inode].num_edges; + for (iconn = 0; iconn < num_edges; iconn++) { + to_node = rr_node[inode].edges[iconn]; + + if (rr_node[to_node].xhigh < route_bb[inet].xmin + || rr_node[to_node].xlow > route_bb[inet].xmax + || rr_node[to_node].yhigh < route_bb[inet].ymin + || rr_node[to_node].ylow > route_bb[inet].ymax) + continue; /* Node is outside (expanded) bounding box. */ + + tot_cost = pcost + get_rr_cong_cost(to_node); + + if (bend_cost != 0.) { + from_type = rr_node[inode].type; + to_type = rr_node[to_node].type; + if ((from_type == CHANX && to_type == CHANY) + || (from_type == CHANY && to_type == CHANX)) + tot_cost += bend_cost; + } + + node_to_heap(to_node, tot_cost, inode, iconn, OPEN, OPEN); + } +} + +static void breadth_first_add_source_to_heap(int inet) { + + /* Adds the SOURCE of this net to the heap. Used to start a net's routing. */ + + int inode; + float cost; + + inode = net_rr_terminals[inet][0]; /* SOURCE */ + cost = get_rr_cong_cost(inode); + + node_to_heap(inode, cost, NO_PREVIOUS, NO_PREVIOUS, OPEN, OPEN); +} diff --git a/vpr7_rram/vpr/SRC/route/route_breadth_first.h b/vpr7_rram/vpr/SRC/route/route_breadth_first.h new file mode 100755 index 000000000..b69219962 --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/route_breadth_first.h @@ -0,0 +1,2 @@ +boolean try_breadth_first_route(struct s_router_opts router_opts, + t_ivec ** clb_opins_used_locally, int width_fac); diff --git a/vpr7_rram/vpr/SRC/route/route_common.c b/vpr7_rram/vpr/SRC/route/route_common.c new file mode 100755 index 000000000..64cb41eb5 --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/route_common.c @@ -0,0 +1,1457 @@ +#include +#include +#include +#include +#include "util.h" +#include "vpr_types.h" +#include "vpr_utils.h" +#include "globals.h" +#include "route_export.h" +#include "route_common.h" +#include "route_tree_timing.h" +#include "route_timing.h" +#include "route_breadth_first.h" +#include "place_and_route.h" +#include "rr_graph.h" +#include "read_xml_arch_file.h" +#include "ReadOptions.h" +/* mrFPGA */ +#include "mrfpga_globals.h" +#include "buffer_insertion.h" +/* end */ + +/* Xifan TANG: useful functions for pb_pin_eq_auto_detect */ +void reassign_rr_node_net_num_from_scratch(); + +/***************** Variables shared only by route modules *******************/ + +t_rr_node_route_inf *rr_node_route_inf = NULL; /* [0..num_rr_nodes-1] */ + +struct s_bb *route_bb = NULL; /* [0..num_nets-1]. Limits area in which each */ + +/* net must be routed. */ + +/**************** Static variables local to route_common.c ******************/ + +static struct s_heap **heap; /* Indexed from [1..heap_size] */ +static int heap_size; /* Number of slots in the heap array */ +static int heap_tail; /* Index of first unused slot in the heap array */ + +/* For managing my own list of currently free heap data structures. */ +static struct s_heap *heap_free_head = NULL; +/* For keeping track of the sudo malloc memory for the heap*/ +static t_chunk heap_ch = {NULL, 0, NULL}; + +/* For managing my own list of currently free trace data structures. */ +static struct s_trace *trace_free_head = NULL; +/* For keeping track of the sudo malloc memory for the trace*/ +static t_chunk trace_ch = {NULL, 0, NULL}; + +#ifdef DEBUG +static int num_trace_allocated = 0; /* To watch for memory leaks. */ +static int num_heap_allocated = 0; +static int num_linked_f_pointer_allocated = 0; +#endif + +static struct s_linked_f_pointer *rr_modified_head = NULL; +static struct s_linked_f_pointer *linked_f_pointer_free_head = NULL; + +static t_chunk linked_f_pointer_ch = {NULL, 0, NULL}; + +/* The numbering relation between the channels and clbs is: * + * * + * | IO | chan_ | CLB | chan_ | CLB | * + * |grid[0][2] | y[0][2] |grid[1][2] | y[1][2] | grid[2][2]| * + * +-----------+ +-----------+ +-----------+ * + * } capacity in * + * No channel chan_x[1][1] chan_x[2][1] } chan_width * + * } _x[1] * + * +-----------+ +-----------+ +-----------+ * + * | | chan_ | | chan_ | | * + * | IO | y[0][1] | CLB | y[1][1] | CLB | * + * |grid[0][1] | |grid[1][1] | |grid[2][1] | * + * | | | | | | * + * +-----------+ +-----------+ +-----------+ * + * } capacity in * + * chan_x[1][0] chan_x[2][0] } chan_width * + * } _x[0] * + * +-----------+ +-----------+ * + * No | | No | | * + * Channel | IO | Channel | IO | * + * |grid[1][0] | |grid[2][0] | * + * | | | | * + * +-----------+ +-----------+ * + * * + * {=======} {=======} * + * Capacity in Capacity in * + * chan_width_y[0] chan_width_y[1] * + * */ + +/******************** Subroutines local to route_common.c *******************/ + +static void free_trace_data(struct s_trace *tptr); +static void load_route_bb(int bb_factor); + +static struct s_trace *alloc_trace_data(void); +static void add_to_heap(struct s_heap *hptr); +static struct s_heap *alloc_heap_data(void); +static struct s_linked_f_pointer *alloc_linked_f_pointer(void); + +static t_ivec **alloc_and_load_clb_opins_used_locally(void); +static void adjust_one_rr_occ_and_pcost(int inode, int add_or_sub, + float pres_fac); + +/************************** Subroutine definitions ***************************/ + +void save_routing(struct s_trace **best_routing, + t_ivec ** clb_opins_used_locally, + t_ivec ** saved_clb_opins_used_locally) { + + /* This routing frees any routing currently held in best routing, * + * then copies over the current routing (held in trace_head), and * + * finally sets trace_head and trace_tail to all NULLs so that the * + * connection to the saved routing is broken. This is necessary so * + * that the next iteration of the router does not free the saved * + * routing elements. Also saves any data about locally used clb_opins, * + * since this is also part of the routing. */ + + int inet, iblk, iclass, ipin, num_local_opins; + struct s_trace *tptr, *tempptr; + t_type_ptr type; + + for (inet = 0; inet < num_nets; inet++) { + + /* Free any previously saved routing. It is no longer best. */ + tptr = best_routing[inet]; + while (tptr != NULL) { + tempptr = tptr->next; + free_trace_data(tptr); + tptr = tempptr; + } + + /* Save a pointer to the current routing in best_routing. */ + best_routing[inet] = trace_head[inet]; + + /* Set the current (working) routing to NULL so the current trace * + * elements won't be reused by the memory allocator. */ + + trace_head[inet] = NULL; + trace_tail[inet] = NULL; + } + + /* Save which OPINs are locally used. */ + + for (iblk = 0; iblk < num_blocks; iblk++) { + type = block[iblk].type; + /* Xifan TANG: Bypass those with pin_equivalence auto-detect */ + if (TRUE == type->output_ports_eq_auto_detect) { + continue; + } + /* Xifan TANG: By pass IO */ + if (IO_TYPE == type) { + continue; + } + for (iclass = 0; iclass < type->num_class; iclass++) { + num_local_opins = clb_opins_used_locally[iblk][iclass].nelem; + for (ipin = 0; ipin < num_local_opins; ipin++) { + saved_clb_opins_used_locally[iblk][iclass].list[ipin] = + clb_opins_used_locally[iblk][iclass].list[ipin]; + } + } + } +} + +void restore_routing(struct s_trace **best_routing, + t_ivec ** clb_opins_used_locally, + t_ivec ** saved_clb_opins_used_locally) { + + /* Deallocates any current routing in trace_head, and replaces it with * + * the routing in best_routing. Best_routing is set to NULL to show that * + * it no longer points to a valid routing. NOTE: trace_tail is not * + * restored -- it is set to all NULLs since it is only used in * + * update_traceback. If you need trace_tail restored, modify this * + * routine. Also restores the locally used opin data. */ + + int inet, iblk, ipin, iclass, num_local_opins; + t_type_ptr type; + + /* mrFPGA : Xifan TANG*/ + if (is_mrFPGA && is_wire_buffer) { + load_best_buffer_list(); + } + /* end */ + + for (inet = 0; inet < num_nets; inet++) { + + /* Free any current routing. */ + free_traceback(inet); + + /* Set the current routing to the saved one. */ + trace_head[inet] = best_routing[inet]; + best_routing[inet] = NULL; /* No stored routing. */ + } + + /* Save which OPINs are locally used. */ + + for (iblk = 0; iblk < num_blocks; iblk++) { + type = block[iblk].type; + for (iclass = 0; iclass < type->num_class; iclass++) { + num_local_opins = clb_opins_used_locally[iblk][iclass].nelem; + for (ipin = 0; ipin < num_local_opins; ipin++) { + clb_opins_used_locally[iblk][iclass].list[ipin] = + saved_clb_opins_used_locally[iblk][iclass].list[ipin]; + } + } + + } +} + +void get_serial_num(void) { + + /* This routine finds a "magic cookie" for the routing and prints it. * + * Use this number as a routing serial number to ensure that programming * + * changes do not break the router. */ + + int inet, serial_num, inode; + struct s_trace *tptr; + + serial_num = 0; + + for (inet = 0; inet < num_nets; inet++) { + + /* Global nets will have null trace_heads (never routed) so they * + * are not included in the serial number calculation. */ + + tptr = trace_head[inet]; + while (tptr != NULL) { + inode = tptr->index; + serial_num += (inet + 1) + * (rr_node[inode].xlow * (nx + 1) - rr_node[inode].yhigh); + + serial_num -= rr_node[inode].ptc_num * (inet + 1) * 10; + + serial_num -= rr_node[inode].type * (inet + 1) * 100; + serial_num %= 2000000000; /* Prevent overflow */ + tptr = tptr->next; + } + } + vpr_printf(TIO_MESSAGE_INFO, "Serial number (magic cookie) for the routing is: %d\n", serial_num); +} + +boolean try_route(int width_fac, struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf, float **net_delay, t_slack * slacks, + t_chan_width_dist chan_width_dist, t_ivec ** clb_opins_used_locally, + boolean * Fc_clipped, t_direct_inf *directs, int num_directs, + /*Xifan TANG: Switch Segment Pattern Support*/ + t_swseg_pattern_inf* swseg_patterns) { + + /* Attempts a routing via an iterated maze router algorithm. Width_fac * + * specifies the relative width of the channels, while the members of * + * router_opts determine the value of the costs assigned to routing * + * resource node, etc. det_routing_arch describes the detailed routing * + * architecture (connection and switch boxes) of the FPGA; it is used * + * only if a DETAILED routing has been selected. */ + + int tmp; + clock_t begin, end; + boolean success; + t_graph_type graph_type; + + if (router_opts.route_type == GLOBAL) { + graph_type = GRAPH_GLOBAL; + } else { + graph_type = ( + det_routing_arch.directionality == BI_DIRECTIONAL ? + GRAPH_BIDIR : GRAPH_UNIDIR); + } + + /* Set the channel widths */ + + init_chan(width_fac, chan_width_dist); + + /* Free any old routing graph, if one exists. */ + + free_rr_graph(); + + begin = clock(); + + /* Set up the routing resource graph defined by this FPGA architecture. */ + + build_rr_graph(graph_type, num_types, type_descriptors, nx, ny, grid, + chan_width_x[0], NULL, det_routing_arch.switch_block_type, + det_routing_arch.Fs, det_routing_arch.num_segment, + det_routing_arch.num_switch, segment_inf, + det_routing_arch.global_route_switch, + det_routing_arch.delayless_switch, timing_inf, + det_routing_arch.wire_to_ipin_switch, router_opts.base_cost_type, + directs, num_directs, FALSE, + &tmp, + // Xifan TANG: Add Switch Segment Pattern Support + det_routing_arch.num_swseg_pattern, swseg_patterns, TRUE, TRUE); + + end = clock(); +#ifdef CLOCKS_PER_SEC + vpr_printf(TIO_MESSAGE_INFO, "Build rr_graph took %g seconds.\n", (float)(end - begin) / CLOCKS_PER_SEC); +#else + vpr_printf(TIO_MESSAGE_INFO, "Build rr_graph took %g seconds.\n", (float)(end - begin) / CLK_PER_SEC); +#endif + + /* Allocate and load some additional rr_graph information needed only by * + * the router. */ + + alloc_and_load_rr_node_route_structs(); + + init_route_structs(router_opts.bb_factor); + + if (router_opts.router_algorithm == BREADTH_FIRST) { + vpr_printf(TIO_MESSAGE_INFO, "Confirming Router Algorithm: BREADTH_FIRST.\n"); + success = try_breadth_first_route(router_opts, clb_opins_used_locally, + width_fac); + } else { /* TIMING_DRIVEN route */ + vpr_printf(TIO_MESSAGE_INFO, "Confirming Router Algorithm: TIMING_DRIVEN.\n"); + assert(router_opts.route_type != GLOBAL); + success = try_timing_driven_route(router_opts, net_delay, slacks, + clb_opins_used_locally,timing_inf.timing_analysis_enabled); + } + + free_rr_node_route_structs(); + + return (success); +} + +boolean feasible_routing(void) { + + /* This routine checks to see if this is a resource-feasible routing. * + * That is, are all rr_node capacity limitations respected? It assumes * + * that the occupancy arrays are up to date when it is called. */ + + int inode; + + for (inode = 0; inode < num_rr_nodes; inode++) { + if (rr_node[inode].occ > rr_node[inode].capacity) { + /* + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]rr_node[%d] occupancy(%d) exceeds its capacity(%d)!\n", + __FILE__, __LINE__, inode, rr_node[inode].occ, rr_node[inode].capacity); + */ + return (FALSE); + } + } + + return (TRUE); +} + +void pathfinder_update_one_cost(struct s_trace *route_segment_start, + int add_or_sub, float pres_fac) { + + /* This routine updates the occupancy and pres_cost of the rr_nodes that are * + * affected by the portion of the routing of one net that starts at * + * route_segment_start. If route_segment_start is trace_head[inet], the * + * cost of all the nodes in the routing of net inet are updated. If * + * add_or_sub is -1 the net (or net portion) is ripped up, if it is 1 the * + * net is added to the routing. The size of pres_fac determines how severly * + * oversubscribed rr_nodes are penalized. */ + + struct s_trace *tptr; + int inode, occ, capacity; + + tptr = route_segment_start; + if (tptr == NULL) /* No routing yet. */ + return; + + for (;;) { + inode = tptr->index; + + occ = rr_node[inode].occ + add_or_sub; + capacity = rr_node[inode].capacity; + + rr_node[inode].occ = occ; + + /* pres_cost is Pn in the Pathfinder paper. I set my pres_cost according to * + * the overuse that would result from having ONE MORE net use this routing * + * node. */ + + if (occ < capacity) { + rr_node_route_inf[inode].pres_cost = 1.; + } else { + rr_node_route_inf[inode].pres_cost = 1. + + (occ + 1 - capacity) * pres_fac; + } + + if (rr_node[inode].type == SINK) { + tptr = tptr->next; /* Skip next segment. */ + if (tptr == NULL) + break; + } + + tptr = tptr->next; + + } /* End while loop -- did an entire traceback. */ +} + +void pathfinder_update_cost(float pres_fac, float acc_fac) { + + /* This routine recomputes the pres_cost and acc_cost of each routing * + * resource for the pathfinder algorithm after all nets have been routed. * + * It updates the accumulated cost to by adding in the number of extra * + * signals sharing a resource right now (i.e. after each complete iteration) * + * times acc_fac. It also updates pres_cost, since pres_fac may have * + * changed. THIS ROUTINE ASSUMES THE OCCUPANCY VALUES IN RR_NODE ARE UP TO * + * DATE. */ + + int inode, occ, capacity; + + for (inode = 0; inode < num_rr_nodes; inode++) { + occ = rr_node[inode].occ; + capacity = rr_node[inode].capacity; + + if (occ > capacity) { + rr_node_route_inf[inode].acc_cost += (occ - capacity) * acc_fac; + rr_node_route_inf[inode].pres_cost = 1. + + (occ + 1 - capacity) * pres_fac; + } + + /* If occ == capacity, we don't need to increase acc_cost, but a change * + * in pres_fac could have made it necessary to recompute the cost anyway. */ + + else if (occ == capacity) { + rr_node_route_inf[inode].pres_cost = 1. + pres_fac; + } + } +} + +void init_route_structs(int bb_factor) { + + /* Call this before you route any nets. It frees any old traceback and * + * sets the list of rr_nodes touched to empty. */ + + int i; + + for (i = 0; i < num_nets; i++) + free_traceback(i); + + load_route_bb(bb_factor); + + /* Check that things that should have been emptied after the last routing * + * really were. */ + + if (rr_modified_head != NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "in init_route_structs. List of modified rr nodes is not empty.\n"); + exit(1); + } + + if (heap_tail != 1) { + vpr_printf(TIO_MESSAGE_ERROR, "in init_route_structs. Heap is not empty.\n"); + exit(1); + } +} + +struct s_trace * +update_traceback(struct s_heap *hptr, int inet) { + + /* This routine adds the most recently finished wire segment to the * + * traceback linked list. The first connection starts with the net SOURCE * + * and begins at the structure pointed to by trace_head[inet]. Each * + * connection ends with a SINK. After each SINK, the next connection * + * begins (if the net has more than 2 pins). The first element after the * + * SINK gives the routing node on a previous piece of the routing, which is * + * the link from the existing net to this new piece of the net. * + * In each traceback I start at the end of a path and trace back through * + * its predecessors to the beginning. I have stored information on the * + * predecesser of each node to make traceback easy -- this sacrificies some * + * memory for easier code maintenance. This routine returns a pointer to * + * the first "new" node in the traceback (node not previously in trace). */ + + struct s_trace *tptr, *prevptr, *temptail, *ret_ptr; + int inode; + short iedge; + +#ifdef DEBUG + t_rr_type rr_type; +#endif + + inode = hptr->index; + +#ifdef DEBUG + rr_type = rr_node[inode].type; + if (rr_type != SINK) { + vpr_printf(TIO_MESSAGE_ERROR, "in update_traceback. Expected type = SINK (%d).\n", SINK); + vpr_printf(TIO_MESSAGE_ERROR, "\tGot type = %d while tracing back net %d.\n", rr_type, inet); + exit(1); + } +#endif + + tptr = alloc_trace_data(); /* SINK on the end of the connection */ + tptr->index = inode; + tptr->iswitch = OPEN; + tptr->next = NULL; + temptail = tptr; /* This will become the new tail at the end */ + /* of the routine. */ + + /* Now do it's predecessor. */ + + inode = hptr->u.prev_node; + iedge = hptr->prev_edge; + + while (inode != NO_PREVIOUS) { + prevptr = alloc_trace_data(); + prevptr->index = inode; + prevptr->iswitch = rr_node[inode].switches[iedge]; + prevptr->next = tptr; + tptr = prevptr; + + iedge = rr_node_route_inf[inode].prev_edge; + inode = rr_node_route_inf[inode].prev_node; + } + + if (trace_tail[inet] != NULL) { + trace_tail[inet]->next = tptr; /* Traceback ends with tptr */ + ret_ptr = tptr->next; /* First new segment. */ + } else { /* This was the first "chunk" of the net's routing */ + trace_head[inet] = tptr; + ret_ptr = tptr; /* Whole traceback is new. */ + } + + trace_tail[inet] = temptail; + return (ret_ptr); +} + +void reset_path_costs(void) { + + /* The routine sets the path_cost to HUGE_POSITIVE_FLOAT for all channel segments * + * touched by previous routing phases. */ + + struct s_linked_f_pointer *mod_ptr; + +#ifdef DEBUG + int num_mod_ptrs; +#endif + + /* The traversal method below is slightly painful to make it faster. */ + + if (rr_modified_head != NULL) { + mod_ptr = rr_modified_head; + +#ifdef DEBUG + num_mod_ptrs = 1; +#endif + + while (mod_ptr->next != NULL) { + *(mod_ptr->fptr) = HUGE_POSITIVE_FLOAT; + mod_ptr = mod_ptr->next; +#ifdef DEBUG + num_mod_ptrs++; +#endif + } + *(mod_ptr->fptr) = HUGE_POSITIVE_FLOAT; /* Do last one. */ + + /* Reset the modified list and put all the elements back in the free * + * list. */ + + mod_ptr->next = linked_f_pointer_free_head; + linked_f_pointer_free_head = rr_modified_head; + rr_modified_head = NULL; + +#ifdef DEBUG + num_linked_f_pointer_allocated -= num_mod_ptrs; +#endif + } +} + +float get_rr_cong_cost(int inode) { + + /* Returns the *congestion* cost of using this rr_node. */ + + short cost_index; + float cost; + + cost_index = rr_node[inode].cost_index; + cost = rr_indexed_data[cost_index].base_cost + * rr_node_route_inf[inode].acc_cost + * rr_node_route_inf[inode].pres_cost; + return (cost); +} + +void mark_ends(int inet) { + + /* Mark all the SINKs of this net as targets by setting their target flags * + * to the number of times the net must connect to each SINK. Note that * + * this number can occassionally be greater than 1 -- think of connecting * + * the same net to two inputs of an and-gate (and-gate inputs are logically * + * equivalent, so both will connect to the same SINK). */ + + int ipin, inode; + + for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) { + inode = net_rr_terminals[inet][ipin]; + rr_node_route_inf[inode].target_flag++; + } +} + +void node_to_heap(int inode, float cost, int prev_node, int prev_edge, + float backward_path_cost, float R_upstream) { + + /* Puts an rr_node on the heap, if the new cost given is lower than the * + * current path_cost to this channel segment. The index of its predecessor * + * is stored to make traceback easy. The index of the edge used to get * + * from its predecessor to it is also stored to make timing analysis, etc. * + * easy. The backward_path_cost and R_upstream values are used only by the * + * timing-driven router -- the breadth-first router ignores them. */ + + struct s_heap *hptr; + + if (cost >= rr_node_route_inf[inode].path_cost) + return; + + hptr = alloc_heap_data(); + hptr->index = inode; + hptr->cost = cost; + hptr->u.prev_node = prev_node; + hptr->prev_edge = prev_edge; + hptr->backward_path_cost = backward_path_cost; + hptr->R_upstream = R_upstream; + add_to_heap(hptr); +} + +void free_traceback(int inet) { + + /* Puts the entire traceback (old routing) for this net on the free list * + * and sets the trace_head pointers etc. for the net to NULL. */ + + struct s_trace *tptr, *tempptr; + + if(trace_head == NULL) { + return; + } + + tptr = trace_head[inet]; + + while (tptr != NULL) { + tempptr = tptr->next; + free_trace_data(tptr); + tptr = tempptr; + } + + trace_head[inet] = NULL; + trace_tail[inet] = NULL; +} + +t_ivec ** +alloc_route_structs(void) { + + /* Allocates the data structures needed for routing. */ + + t_ivec **clb_opins_used_locally; + + alloc_route_static_structs(); + clb_opins_used_locally = alloc_and_load_clb_opins_used_locally(); + + return (clb_opins_used_locally); +} + +void alloc_route_static_structs(void) { + trace_head = (struct s_trace **) my_calloc(num_nets, + sizeof(struct s_trace *)); + trace_tail = (struct s_trace **) my_malloc( + num_nets * sizeof(struct s_trace *)); + + heap_size = nx * ny; + heap = (struct s_heap **) my_malloc(heap_size * sizeof(struct s_heap *)); + heap--; /* heap stores from [1..heap_size] */ + heap_tail = 1; + + route_bb = (struct s_bb *) my_malloc(num_nets * sizeof(struct s_bb)); +} + +struct s_trace ** +alloc_saved_routing(t_ivec ** clb_opins_used_locally, + t_ivec *** saved_clb_opins_used_locally_ptr) { + + /* Allocates data structures into which the key routing data can be saved, * + * allowing the routing to be recovered later (e.g. after a another routing * + * is attempted). */ + + struct s_trace **best_routing; + t_ivec **saved_clb_opins_used_locally; + int iblk, iclass, num_local_opins; + t_type_ptr type; + + best_routing = (struct s_trace **) my_calloc(num_nets, + sizeof(struct s_trace *)); + + saved_clb_opins_used_locally = (t_ivec **) my_malloc( + num_blocks * sizeof(t_ivec *)); + + for (iblk = 0; iblk < num_blocks; iblk++) { + type = block[iblk].type; + saved_clb_opins_used_locally[iblk] = (t_ivec *) my_malloc( + type->num_class * sizeof(t_ivec)); + for (iclass = 0; iclass < type->num_class; iclass++) { + num_local_opins = clb_opins_used_locally[iblk][iclass].nelem; + saved_clb_opins_used_locally[iblk][iclass].nelem = num_local_opins; + + if (num_local_opins == 0) { + saved_clb_opins_used_locally[iblk][iclass].list = NULL; + } else { + saved_clb_opins_used_locally[iblk][iclass].list = + (int *) my_malloc(num_local_opins * sizeof(int)); + } + } + } + + *saved_clb_opins_used_locally_ptr = saved_clb_opins_used_locally; + return (best_routing); +} + +/* TODO: super hacky, jluu comment, I need to rethink this whole function, without it, logically equivalent output pins incorrectly use more pins than needed. I force that CLB output pin uses at most one output pin */ +static t_ivec ** +alloc_and_load_clb_opins_used_locally(void) { + + /* Allocates and loads the data needed to make the router reserve some CLB * + * output pins for connections made locally within a CLB (if the netlist * + * specifies that this is necessary). */ + + t_ivec **clb_opins_used_locally; + int iblk, clb_pin, iclass, num_local_opins; + int class_low, class_high; + t_type_ptr type; + + clb_opins_used_locally = (t_ivec **) my_malloc( + num_blocks * sizeof(t_ivec *)); + + for (iblk = 0; iblk < num_blocks; iblk++) { + type = block[iblk].type; + get_class_range_for_block(iblk, &class_low, &class_high); + clb_opins_used_locally[iblk] = (t_ivec *) my_malloc( + type->num_class * sizeof(t_ivec)); + for (iclass = 0; iclass < type->num_class; iclass++) + clb_opins_used_locally[iblk][iclass].nelem = 0; + + for (clb_pin = 0; clb_pin < type->num_pins; clb_pin++) { + // another hack to avoid I/Os, whole function needs a rethink + if(type == IO_TYPE) { + continue; + } + /* Comment by Xifan TANG: count the number of unused clb OPINs ? Those pins may be used locally... + * It seems that jluu wants to force all these pins are used, even though there is no net mapped! + * Then router will not route with these unused clb_pins!!! + */ + if ((block[iblk].nets[clb_pin] != OPEN + && clb_net[block[iblk].nets[clb_pin]].num_sinks == 0) || block[iblk].nets[clb_pin] == OPEN + ) { + iclass = type->pin_class[clb_pin]; + if(type->class_inf[iclass].type == DRIVER) { + /* Check to make sure class is in same range as that assigned to block */ + assert(iclass >= class_low && iclass <= class_high); + clb_opins_used_locally[iblk][iclass].nelem++; + } + } + } + + for (iclass = 0; iclass < type->num_class; iclass++) { + num_local_opins = clb_opins_used_locally[iblk][iclass].nelem; + + if (num_local_opins == 0) + clb_opins_used_locally[iblk][iclass].list = NULL; + else + clb_opins_used_locally[iblk][iclass].list = (int *) my_malloc( + num_local_opins * sizeof(int)); + } + } + + return (clb_opins_used_locally); +} + +void free_trace_structs(void) { + /*the trace lists are only freed after use by the timing-driven placer */ + /*Do not free them after use by the router, since stats, and draw */ + /*routines use the trace values */ + int i; + + for (i = 0; i < num_nets; i++) + free_traceback(i); + + if(trace_head) { + free(trace_head); + free(trace_tail); + } + trace_head = NULL; + trace_tail = NULL; +} + +void free_route_structs() { + + /* Frees the temporary storage needed only during the routing. The * + * final routing result is not freed. */ + if(heap != NULL) { + free(heap + 1); + } + if(route_bb != NULL) { + free(route_bb); + } + + heap = NULL; /* Defensive coding: crash hard if I use these. */ + route_bb = NULL; + + /*free the memory chunks that were used by heap and linked f pointer */ + free_chunk_memory(&heap_ch); + free_chunk_memory(&linked_f_pointer_ch); + heap_free_head = NULL; + linked_f_pointer_free_head = NULL; +} + +void free_saved_routing(struct s_trace **best_routing, + t_ivec ** saved_clb_opins_used_locally) { + + /* Frees the data structures needed to save a routing. */ + int i; + + free(best_routing); + for (i = 0; i < num_blocks; i++) { + free_ivec_vector(saved_clb_opins_used_locally[i], 0, + block[i].type->num_class - 1); + } + free(saved_clb_opins_used_locally); +} + +void alloc_and_load_rr_node_route_structs(void) { + + /* Allocates some extra information about each rr_node that is used only * + * during routing. */ + + int inode; + + if (rr_node_route_inf != NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "in alloc_and_load_rr_node_route_structs: old rr_node_route_inf array exists.\n"); + exit(1); + } + + rr_node_route_inf = (t_rr_node_route_inf *) my_malloc(num_rr_nodes * sizeof(t_rr_node_route_inf)); + + for (inode = 0; inode < num_rr_nodes; inode++) { + rr_node_route_inf[inode].prev_node = NO_PREVIOUS; + rr_node_route_inf[inode].prev_edge = NO_PREVIOUS; + rr_node_route_inf[inode].pres_cost = 1.; + rr_node_route_inf[inode].acc_cost = 1.; + rr_node_route_inf[inode].path_cost = HUGE_POSITIVE_FLOAT; + rr_node_route_inf[inode].target_flag = 0; + } +} + +void reset_rr_node_route_structs(void) { + + /* Allocates some extra information about each rr_node that is used only * + * during routing. */ + + int inode; + + assert(rr_node_route_inf != NULL); + + for (inode = 0; inode < num_rr_nodes; inode++) { + rr_node_route_inf[inode].prev_node = NO_PREVIOUS; + rr_node_route_inf[inode].prev_edge = NO_PREVIOUS; + rr_node_route_inf[inode].pres_cost = 1.; + rr_node_route_inf[inode].acc_cost = 1.; + rr_node_route_inf[inode].path_cost = HUGE_POSITIVE_FLOAT; + rr_node_route_inf[inode].target_flag = 0; + } +} + +void free_rr_node_route_structs(void) { + + /* Frees the extra information about each rr_node that is needed only * + * during routing. */ + + free(rr_node_route_inf); + rr_node_route_inf = NULL; /* Mark as free */ +} + +/* RESEARCH TODO: Bounding box heuristic needs to be redone for heterogeneous blocks */ +static void load_route_bb(int bb_factor) { + + /* This routine loads the bounding box arrays used to limit the space * + * searched by the maze router when routing each net. The search is * + * limited to channels contained with the net bounding box expanded * + * by bb_factor channels on each side. For example, if bb_factor is * + * 0, the maze router must route each net within its bounding box. * + * If bb_factor = nx, the maze router will search every channel in * + * the FPGA if necessary. The bounding boxes returned by this routine * + * are different from the ones used by the placer in that they are * + * clipped to lie within (0,0) and (nx+1,ny+1) rather than (1,1) and * + * (nx,ny). */ + + int k, xmax, ymax, xmin, ymin, x, y, inet; + + for (inet = 0; inet < num_nets; inet++) { + x = block[clb_net[inet].node_block[0]].x; + y = + block[clb_net[inet].node_block[0]].y + + block[clb_net[inet].node_block[0]].type->pin_height[clb_net[inet].node_block_pin[0]]; + + xmin = x; + ymin = y; + xmax = x; + ymax = y; + + for (k = 1; k <= clb_net[inet].num_sinks; k++) { + x = block[clb_net[inet].node_block[k]].x; + y = + block[clb_net[inet].node_block[k]].y + + block[clb_net[inet].node_block[k]].type->pin_height[clb_net[inet].node_block_pin[k]]; + + if (x < xmin) { + xmin = x; + } else if (x > xmax) { + xmax = x; + } + + if (y < ymin) { + ymin = y; + } else if (y > ymax) { + ymax = y; + } + } + + /* Want the channels on all 4 sides to be usuable, even if bb_factor = 0. */ + + xmin -= 1; + ymin -= 1; + + /* Expand the net bounding box by bb_factor, then clip to the physical * + * chip area. */ + + route_bb[inet].xmin = std::max(xmin - bb_factor, 0); + route_bb[inet].xmax = std::min(xmax + bb_factor, nx + 1); + route_bb[inet].ymin = std::max(ymin - bb_factor, 0); + route_bb[inet].ymax = std::min(ymax + bb_factor, ny + 1); + } +} + +void add_to_mod_list(float *fptr) { + + /* This routine adds the floating point pointer (fptr) into a * + * linked list that indicates all the pathcosts that have been * + * modified thus far. */ + + struct s_linked_f_pointer *mod_ptr; + + mod_ptr = alloc_linked_f_pointer(); + + /* Add this element to the start of the modified list. */ + + mod_ptr->next = rr_modified_head; + mod_ptr->fptr = fptr; + rr_modified_head = mod_ptr; +} + +static void add_to_heap(struct s_heap *hptr) { + + /* Adds an item to the heap, expanding the heap if necessary. */ + + int ito, ifrom; + struct s_heap *temp_ptr; + + if (heap_tail > heap_size) { /* Heap is full */ + heap_size *= 2; + heap = (struct s_heap **) my_realloc((void *) (heap + 1), + heap_size * sizeof(struct s_heap *)); + heap--; /* heap goes from [1..heap_size] */ + } + + heap[heap_tail] = hptr; + ifrom = heap_tail; + ito = ifrom / 2; + heap_tail++; + + while ((ito >= 1) && (heap[ifrom]->cost < heap[ito]->cost)) { + temp_ptr = heap[ito]; + heap[ito] = heap[ifrom]; + heap[ifrom] = temp_ptr; + ifrom = ito; + ito = ifrom / 2; + } +} + +/*WMF: peeking accessor :) */ +boolean is_empty_heap(void) { + return (boolean)(heap_tail == 1); +} + +struct s_heap * +get_heap_head(void) { + + /* Returns a pointer to the smallest element on the heap, or NULL if the * + * heap is empty. Invalid (index == OPEN) entries on the heap are never * + * returned -- they are just skipped over. */ + + int ito, ifrom; + struct s_heap *heap_head, *temp_ptr; + + do { + if (heap_tail == 1) { /* Empty heap. */ + vpr_printf(TIO_MESSAGE_WARNING, "Empty heap occurred in get_heap_head.\n"); + vpr_printf(TIO_MESSAGE_WARNING, "Some blocks are impossible to connect in this architecture.\n"); + return (NULL); + } + + heap_head = heap[1]; /* Smallest element. */ + + /* Now fix up the heap */ + + heap_tail--; + heap[1] = heap[heap_tail]; + ifrom = 1; + ito = 2 * ifrom; + + while (ito < heap_tail) { + if (heap[ito + 1]->cost < heap[ito]->cost) + ito++; + if (heap[ito]->cost > heap[ifrom]->cost) + break; + temp_ptr = heap[ito]; + heap[ito] = heap[ifrom]; + heap[ifrom] = temp_ptr; + ifrom = ito; + ito = 2 * ifrom; + } + + } while (heap_head->index == OPEN); /* Get another one if invalid entry. */ + + return (heap_head); +} + +void empty_heap(void) { + + int i; + + for (i = 1; i < heap_tail; i++) + free_heap_data(heap[i]); + + heap_tail = 1; +} + +static struct s_heap * +alloc_heap_data(void) { + + struct s_heap *temp_ptr; + + if (heap_free_head == NULL) { /* No elements on the free list */ + heap_free_head = (struct s_heap *) my_chunk_malloc(sizeof(struct s_heap),&heap_ch); + heap_free_head->u.next = NULL; + } + + temp_ptr = heap_free_head; + heap_free_head = heap_free_head->u.next; +#ifdef DEBUG + num_heap_allocated++; +#endif + return (temp_ptr); +} + +void free_heap_data(struct s_heap *hptr) { + + hptr->u.next = heap_free_head; + heap_free_head = hptr; +#ifdef DEBUG + num_heap_allocated--; +#endif +} + +void invalidate_heap_entries(int sink_node, int ipin_node) { + + /* Marks all the heap entries consisting of sink_node, where it was reached * + * via ipin_node, as invalid (OPEN). Used only by the breadth_first router * + * and even then only in rare circumstances. */ + + int i; + + for (i = 1; i < heap_tail; i++) { + if (heap[i]->index == sink_node && heap[i]->u.prev_node == ipin_node) + heap[i]->index = OPEN; /* Invalid. */ + } +} + +static struct s_trace * +alloc_trace_data(void) { + + struct s_trace *temp_ptr; + + if (trace_free_head == NULL) { /* No elements on the free list */ + trace_free_head = (struct s_trace *) my_chunk_malloc(sizeof(struct s_trace),&trace_ch); + trace_free_head->next = NULL; + } + temp_ptr = trace_free_head; + trace_free_head = trace_free_head->next; +#ifdef DEBUG + num_trace_allocated++; +#endif + return (temp_ptr); +} + +static void free_trace_data(struct s_trace *tptr) { + + /* Puts the traceback structure pointed to by tptr on the free list. */ + + tptr->next = trace_free_head; + trace_free_head = tptr; +#ifdef DEBUG + num_trace_allocated--; +#endif +} + +static struct s_linked_f_pointer * +alloc_linked_f_pointer(void) { + + /* This routine returns a linked list element with a float pointer as * + * the node data. */ + + /*int i;*/ + struct s_linked_f_pointer *temp_ptr; + + if (linked_f_pointer_free_head == NULL) { + /* No elements on the free list */ + linked_f_pointer_free_head = (struct s_linked_f_pointer *) my_chunk_malloc(sizeof(struct s_linked_f_pointer),&linked_f_pointer_ch); + linked_f_pointer_free_head->next = NULL; + } + + temp_ptr = linked_f_pointer_free_head; + linked_f_pointer_free_head = linked_f_pointer_free_head->next; + +#ifdef DEBUG + num_linked_f_pointer_allocated++; +#endif + + return (temp_ptr); +} + +void print_route(char *route_file) { + + /* Prints out the routing to file route_file. */ + + int inet, inode, ipin, bnum, ilow, jlow, node_block_pin, iclass; + t_rr_type rr_type; + struct s_trace *tptr; + const char *name_type[] = { "SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY", + "INTRA_CLUSTER_EDGE" }; + FILE *fp; + + fp = fopen(route_file, "w"); + + fprintf(fp, "Array size: %d x %d logic blocks.\n", nx, ny); + fprintf(fp, "\nRouting:"); + for (inet = 0; inet < num_nets; inet++) { + if (clb_net[inet].is_global == FALSE) { + if (clb_net[inet].num_sinks == FALSE) { + fprintf(fp, "\n\nNet %d (%s)\n\n", inet, clb_net[inet].name); + fprintf(fp, "\n\nUsed in local cluster only, reserved one CLB pin\n\n"); + } else { + fprintf(fp, "\n\nNet %d (%s)\n\n", inet, clb_net[inet].name); + tptr = trace_head[inet]; + + while (tptr != NULL) { + inode = tptr->index; + rr_type = rr_node[inode].type; + ilow = rr_node[inode].xlow; + jlow = rr_node[inode].ylow; + + fprintf(fp, "Node:\t%d\t%6s (%d,%d) ", inode, name_type[rr_type], ilow, jlow); + + if ((ilow != rr_node[inode].xhigh) + || (jlow != rr_node[inode].yhigh)) + fprintf(fp, "to (%d,%d) ", rr_node[inode].xhigh, + rr_node[inode].yhigh); + + switch (rr_type) { + + case IPIN: + case OPIN: + if (grid[ilow][jlow].type == IO_TYPE) { + fprintf(fp, " Pad: "); + } else { /* IO Pad. */ + fprintf(fp, " Pin: "); + } + break; + + case CHANX: + case CHANY: + fprintf(fp, " Track: "); + break; + + case SOURCE: + case SINK: + if (grid[ilow][jlow].type == IO_TYPE) { + fprintf(fp, " Pad: "); + } else { /* IO Pad. */ + fprintf(fp, " Class: "); + } + break; + + default: + vpr_printf(TIO_MESSAGE_ERROR, "in print_route: Unexpected traceback element type: %d (%s).\n", + rr_type, name_type[rr_type]); + exit(1); + break; + } + + fprintf(fp, "%d ", rr_node[inode].ptc_num); + + /* Uncomment line below if you're debugging and want to see the switch types * + * used in the routing. */ + /* fprintf (fp, "Switch: %d", tptr->iswitch); */ + + fprintf(fp, "\n"); + + tptr = tptr->next; + } + } + } + + else { /* Global net. Never routed. */ + fprintf(fp, "\n\nNet %d (%s): global net connecting:\n\n", inet, + clb_net[inet].name); + + for (ipin = 0; ipin <= clb_net[inet].num_sinks; ipin++) { + bnum = clb_net[inet].node_block[ipin]; + + node_block_pin = clb_net[inet].node_block_pin[ipin]; + iclass = block[bnum].type->pin_class[node_block_pin]; + + fprintf(fp, "Block %s (#%d) at (%d, %d), Pin class %d.\n", + block[bnum].name, bnum, block[bnum].x, block[bnum].y, + iclass); + } + } + } + + fclose(fp); + + if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_MEM)) { + fp = my_fopen(getEchoFileName(E_ECHO_MEM), "w", 0); + fprintf(fp, "\nNum_heap_allocated: %d Num_trace_allocated: %d\n", + num_heap_allocated, num_trace_allocated); + fprintf(fp, "Num_linked_f_pointer_allocated: %d\n", + num_linked_f_pointer_allocated); + fclose(fp); + } + +} + +/* TODO: check if this is still necessary for speed */ +void reserve_locally_used_opins(float pres_fac, boolean rip_up_local_opins, + t_ivec ** clb_opins_used_locally) { + + /* In the past, this function implicitly allowed LUT duplication when there are free LUTs. + This was especially important for logical equivalence; however, now that we have a very general + logic cluster, it does not make sense to allow LUT duplication implicitly. we'll need to look into how we want to handle this case + + */ + + int iblk, num_local_opin, inode, from_node, iconn, num_edges, to_node; + int iclass, ipin; + float cost; + struct s_heap *heap_head_ptr; + t_type_ptr type; + + if (rip_up_local_opins) { + for (iblk = 0; iblk < num_blocks; iblk++) { + type = block[iblk].type; + for (iclass = 0; iclass < type->num_class; iclass++) { + num_local_opin = clb_opins_used_locally[iblk][iclass].nelem; + /* Always 0 for pads and for RECEIVER (IPIN) classes */ + for (ipin = 0; ipin < num_local_opin; ipin++) { + inode = clb_opins_used_locally[iblk][iclass].list[ipin]; + adjust_one_rr_occ_and_pcost(inode, -1, pres_fac); + } + } + } + } + + for (iblk = 0; iblk < num_blocks; iblk++) { + type = block[iblk].type; + /* By pass type_descriptors that turns on pin equivalence auto_detect */ + //if (TRUE == type->output_ports_eq_auto_detect) { + // continue; + //} + for (iclass = 0; iclass < type->num_class; iclass++) { + num_local_opin = clb_opins_used_locally[iblk][iclass].nelem; + /* Always 0 for pads and for RECEIVER (IPIN) classes */ + + if (num_local_opin != 0) { /* Have to reserve (use) some OPINs */ + from_node = rr_blk_source[iblk][iclass]; + num_edges = rr_node[from_node].num_edges; + for (iconn = 0; iconn < num_edges; iconn++) { + to_node = rr_node[from_node].edges[iconn]; + /* Xifan TANG: the to_node may not be the one should be reserved + * Need double check if the ptc_num of this node matches class_id + */ + //if (type->pin_class[rr_node[to_node].ptc_num] != iclass) { + // continue; + //} + /* Original VPR */ + cost = get_rr_cong_cost(to_node); + /* Push nodes to heap: + * Xifan TANG: + * Need to check we do not push a node twice into the heap! + */ + node_to_heap(to_node, cost, OPEN, OPEN, 0., 0.); + } + + for (ipin = 0; ipin < num_local_opin; ipin++) { + heap_head_ptr = get_heap_head(); + inode = heap_head_ptr->index; + /* Xifan TANG: we only modify occ for single driver OPIN ! */ + //if (1 == rr_node[inode].fan_in) { + adjust_one_rr_occ_and_pcost(inode, 1, pres_fac); + //} + clb_opins_used_locally[iblk][iclass].list[ipin] = inode; + free_heap_data(heap_head_ptr); + } + + empty_heap(); + } + } + } +} + +/* Xifan TANG: new function to auto detect and reserved locally used opins */ +void auto_detect_and_reserve_locally_used_opins(float pres_fac, boolean rip_up_local_opins, + t_ivec ** clb_opins_used_locally) { + + /* In the past, this function implicitly allowed LUT duplication when there are free LUTs. + This was especially important for logical equivalence; however, now that we have a very general + logic cluster, it does not make sense to allow LUT duplication implicitly. we'll need to look into how we want to handle this case + */ + + int iblk, num_local_opin, inode, from_node, iconn, num_edges, to_node; + int iclass, ipin; + float cost; + struct s_heap *heap_head_ptr; + t_type_ptr type; + + /* Xifan TANG: Update net_num for all the rr_nodes */ + reassign_rr_node_net_num_from_scratch(); + + /* VPR original method */ + if (rip_up_local_opins) { + for (iblk = 0; iblk < num_blocks; iblk++) { + type = block[iblk].type; + /* Bypass those with pin_equivalence auto-detect */ + if (TRUE == type->output_ports_eq_auto_detect) { + continue; + } + /* By pass IO */ + if (IO_TYPE == type) { + continue; + } + for (iclass = 0; iclass < type->num_class; iclass++) { + num_local_opin = clb_opins_used_locally[iblk][iclass].nelem; + /* Always 0 for pads and for RECEIVER (IPIN) classes */ + for (ipin = 0; ipin < num_local_opin; ipin++) { + inode = clb_opins_used_locally[iblk][iclass].list[ipin]; + adjust_one_rr_occ_and_pcost(inode, -1, pres_fac); + } + } + } + } + + for (iblk = 0; iblk < num_blocks; iblk++) { + type = block[iblk].type; + /* Bypass those with pin_equivalence auto-detect */ + if (TRUE == type->output_ports_eq_auto_detect) { + continue; + } + /* By pass IO */ + if (IO_TYPE == type) { + continue; + } + for (iclass = 0; iclass < type->num_class; iclass++) { + /* Bypass non driver class */ + if (DRIVER != type->class_inf[iclass].type) { + continue; + } + num_local_opin = clb_opins_used_locally[iblk][iclass].nelem; + /* Have to reserve (use) some OPINs */ + ipin = 0; + /* We push nodes into heap and then we can pop-up with a sort by cost */ + from_node = rr_blk_source[iblk][iclass]; + num_edges = rr_node[from_node].num_edges; + /* initialize rr_node element: is_in_heap */ + for (iconn = 0; iconn < num_edges; iconn++) { + to_node = rr_node[from_node].edges[iconn]; + rr_node[to_node].is_in_heap = FALSE; + } + /* Find unmapped pins and add to heap */ + for (iconn = 0; iconn < num_edges; iconn++) { + to_node = rr_node[from_node].edges[iconn]; + if (OPEN != rr_node[to_node].net_num) { + continue; + } + /* we search by net_num if this inode is used or not */ + if (FALSE == rr_node[to_node].is_in_heap) { + rr_node[to_node].is_in_heap = TRUE; + /* Original VPR */ + cost = get_rr_cong_cost(to_node); + /* Push nodes to heap: + * Xifan TANG: + * Need to check we do not push a node twice into the heap! + */ + node_to_heap(to_node, cost, OPEN, OPEN, 0., 0.); + ipin++; + } + } + /* Re-allocate the look-up table if needed */ + if (num_local_opin != ipin) { + clb_opins_used_locally[iblk][iclass].nelem = ipin; + if (0 == clb_opins_used_locally[iblk][iclass].nelem) { + clb_opins_used_locally[iblk][iclass].list = NULL; + } else { + clb_opins_used_locally[iblk][iclass].list = (int *) my_realloc(clb_opins_used_locally[iblk][iclass].list, + clb_opins_used_locally[iblk][iclass].nelem * sizeof(int)); + } + } + /* We want to re-build the list of locally used opins from lowest cost to highest */ + for (iconn = 0; iconn < clb_opins_used_locally[iblk][iclass].nelem; iconn++) { + heap_head_ptr = get_heap_head(); + inode = heap_head_ptr->index; + /* Only update used pins */ + assert(OPEN == rr_node[inode].net_num); + adjust_one_rr_occ_and_pcost(inode, 1, pres_fac); /* Reserve the pin ? */ + clb_opins_used_locally[iblk][iclass].list[iconn] = inode; + rr_node[inode].is_in_heap = FALSE; /* reset the flag */ + free_heap_data(heap_head_ptr); + } + + empty_heap(); + } + } +} + + +static void adjust_one_rr_occ_and_pcost(int inode, int add_or_sub, + float pres_fac) { + + /* Increments or decrements (depending on add_or_sub) the occupancy of * + * one rr_node, and adjusts the present cost of that node appropriately. */ + + int occ, capacity; + + occ = rr_node[inode].occ + add_or_sub; + capacity = rr_node[inode].capacity; + rr_node[inode].occ = occ; + + if (occ < capacity) { + rr_node_route_inf[inode].pres_cost = 1.; + } else { + rr_node_route_inf[inode].pres_cost = 1. + + (occ + 1 - capacity) * pres_fac; + } +} + + +void free_chunk_memory_trace(void) { + if (trace_ch.chunk_ptr_head != NULL) { + free_chunk_memory(&trace_ch); + } +} + + diff --git a/vpr7_rram/vpr/SRC/route/route_common.h b/vpr7_rram/vpr/SRC/route/route_common.h new file mode 100755 index 000000000..f7cc244fe --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/route_common.h @@ -0,0 +1,120 @@ +/************ Defines and types shared by all route files ********************/ + +struct s_heap { + int index; + float cost; + union { + int prev_node; + struct s_heap *next; + } u; + int prev_edge; + float backward_path_cost; + float R_upstream; +}; + +/* Used by the heap as its fundamental data structure. * + * index: Index (ID) of this routing resource node. * + * cost: Cost up to and including this node. * + * u.prev_node: Index (ID) of the predecessor to this node for * + * use in traceback. NO_PREVIOUS if none. * + * u.next: pointer to the next s_heap structure in the free * + * linked list. Not used when on the heap. * + * prev_edge: Index of the edge (between 0 and num_edges-1) used to * + * connect the previous node to this one. NO_PREVIOUS if * + * there is no previous node. * + * backward_path_cost: Used only by the timing-driven router. The "known" * + * cost of the path up to and including this node. * + * In this case, the .cost member contains not only * + * the known backward cost but also an expected cost * + * to the target. * + * R_upstream: Used only by the timing-driven router. Stores the upstream * + * resistance to ground from this node, including the * + * resistance of the node itself (rr_node[index].R). */ + +typedef struct { + int prev_node; + float pres_cost; + float acc_cost; + float path_cost; + float backward_path_cost; + short prev_edge; + short target_flag; +} t_rr_node_route_inf; + +/* Extra information about each rr_node needed only during routing (i.e. * + * during the maze expansion). * + * * + * prev_node: Index of the previous node used to reach this one; * + * used to generate the traceback. If there is no * + * predecessor, prev_node = NO_PREVIOUS. * + * pres_cost: Present congestion cost term for this node. * + * acc_cost: Accumulated cost term from previous Pathfinder iterations. * + * path_cost: Total cost of the path up to and including this node + * + * the expected cost to the target if the timing_driven router * + * is being used. * + * backward_path_cost: Total cost of the path up to and including this * + * node. Not used by breadth-first router. * + * prev_edge: Index of the edge (from 0 to num_edges-1) that was used * + * to reach this node from the previous node. If there is * + * no predecessor, prev_edge = NO_PREVIOUS. * + * target_flag: Is this node a target (sink) for the current routing? * + * Number of times this node must be reached to fully route. */ + +/**************** Variables shared by all route_files ***********************/ + +extern t_rr_node_route_inf *rr_node_route_inf; /* [0..num_rr_nodes-1] */ +extern struct s_bb *route_bb; /* [0..num_nets-1] */ + +/******* Subroutines in route_common used only by other router modules ******/ + +void pathfinder_update_one_cost(struct s_trace *route_segment_start, + int add_or_sub, float pres_fac); + +void pathfinder_update_cost(float pres_fac, float acc_fac); + +struct s_trace *update_traceback(struct s_heap *hptr, int inet); + +void reset_path_costs(void); + +float get_rr_cong_cost(int inode); + +void mark_ends(int inet); + +void node_to_heap(int inode, float cost, int prev_node, int prev_edge, + float backward_path_cost, float R_upstream); + +boolean is_empty_heap(void); + +void free_traceback(int inet); + +void add_to_mod_list(float *fptr); + +struct s_heap *get_heap_head(void); + +void empty_heap(void); + +void free_heap_data(struct s_heap *hptr); + +void invalidate_heap_entries(int sink_node, int ipin_node); + +void init_route_structs(int bb_factor); + +void free_rr_node_route_structs(void); + +void alloc_and_load_rr_node_route_structs(void); + +void reset_rr_node_route_structs(void); + +void alloc_route_static_structs(void); + +void free_trace_structs(void); + +void reserve_locally_used_opins(float pres_fac, boolean rip_up_local_opins, + t_ivec ** clb_opins_used_locally); + +void auto_detect_and_reserve_locally_used_opins(float pres_fac, boolean rip_up_local_opins, + t_ivec ** clb_opins_used_locally); + +void free_chunk_memory_trace(void); + + diff --git a/vpr7_rram/vpr/SRC/route/route_export.h b/vpr7_rram/vpr/SRC/route/route_export.h new file mode 100755 index 000000000..4bb2135c7 --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/route_export.h @@ -0,0 +1,34 @@ +/******** Function prototypes for functions in route_common.c that *********** + ******** are used outside the router modules. ***********/ + +boolean try_route(int width_fac, struct s_router_opts router_opts, + struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, + t_timing_inf timing_inf, float **net_delay, t_slack * slacks, + t_chan_width_dist chan_width_dist, t_ivec ** clb_opins_used_locally, + boolean * Fc_clipped, t_direct_inf *directs, int num_directs, + /*Xifan TANG: Switch Segment Pattern Support*/ + t_swseg_pattern_inf* swseg_patterns); + +boolean feasible_routing(void); + +t_ivec **alloc_route_structs(void); + +void free_route_structs(); + +struct s_trace **alloc_saved_routing(t_ivec ** clb_opins_used_locally, + t_ivec *** saved_clb_opins_used_locally_ptr); + +void free_saved_routing(struct s_trace **best_routing, + t_ivec ** saved_clb_opins_used_locally); + +void save_routing(struct s_trace **best_routing, + t_ivec ** clb_opins_used_locally, + t_ivec ** saved_clb_opins_used_locally); + +void restore_routing(struct s_trace **best_routing, + t_ivec ** clb_opins_used_locally, + t_ivec ** saved_clb_opins_used_locally); + +void get_serial_num(void); + +void print_route(char *name); diff --git a/vpr7_rram/vpr/SRC/route/route_timing.c b/vpr7_rram/vpr/SRC/route/route_timing.c new file mode 100755 index 000000000..c5d4764f5 --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/route_timing.c @@ -0,0 +1,926 @@ +#include +#include +#include +#include +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "route_export.h" +#include "route_common.h" +#include "route_tree_timing.h" +#include "route_timing.h" +#include "heapsort.h" +#include "path_delay.h" +#include "net_delay.h" +#include "stats.h" +#include "ReadOptions.h" + +/*mrFPGA: Xifan TANG*/ +#include "mrfpga_globals.h" +#include "buffer_insertion.h" +/* end */ + +/******************** Subroutines local to route_timing.c ********************/ + +static int get_max_pins_per_net(void); + +static void add_route_tree_to_heap(t_rt_node * rt_node, int target_node, + float target_criticality, float astar_fac); + +static void timing_driven_expand_neighbours(struct s_heap *current, int inet, + float bend_cost, float criticality_fac, int target_node, + float astar_fac, int highfanout_rlim); + +static float get_timing_driven_expected_cost(int inode, int target_node, + float criticality_fac, float R_upstream); + +static int get_expected_segs_to_target(int inode, int target_node, + int *num_segs_ortho_dir_ptr); + +static void update_rr_base_costs(int inet, float largest_criticality); + +static void timing_driven_check_net_delays(float **net_delay); + +static int mark_node_expansion_by_bin(int inet, int target_node, + t_rt_node * rt_node); + +/************************ Subroutine definitions *****************************/ + +boolean try_timing_driven_route(struct s_router_opts router_opts, + float **net_delay, t_slack * slacks, t_ivec ** clb_opins_used_locally, boolean timing_analysis_enabled) { + + /* Timing-driven routing algorithm. The timing graph (includes slack) * + * must have already been allocated, and net_delay must have been allocated. * + * Returns TRUE if the routing succeeds, FALSE otherwise. */ + + int itry, inet, ipin, i, bends, wirelength, total_wirelength, available_wirelength, + segments, *net_index, *sink_order /* [1..max_pins_per_net-1] */; + boolean success, is_routable, rip_up_local_opins; + float *pin_criticality /* [1..max_pins_per_net-1] */, pres_fac, *sinks, + critical_path_delay, init_timing_criticality_val; + t_rt_node **rt_node_of_sink; /* [1..max_pins_per_net-1] */ + clock_t begin,end; + sinks = (float*)my_malloc(sizeof(float) * num_nets); + net_index = (int*)my_malloc(sizeof(int) * num_nets); + + for (i = 0; i < num_nets; i++) { + sinks[i] = clb_net[i].num_sinks; + net_index[i] = i; + } + heapsort(net_index, sinks, num_nets, 1); + + alloc_timing_driven_route_structs(&pin_criticality, &sink_order, + &rt_node_of_sink); + + /* First do one routing iteration ignoring congestion to + get reasonable net delay estimates. Set criticalities to 1 + when timing analysis is on to optimize timing, and to 0 + when timing analysis is off to optimize routability. */ + + if (timing_analysis_enabled) { + init_timing_criticality_val = 1.; + } else { + init_timing_criticality_val = 0.; + } + + for (inet = 0; inet < num_nets; inet++) { + if (clb_net[inet].is_global == FALSE) { + for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) + slacks->timing_criticality[inet][ipin] = init_timing_criticality_val; +#ifdef PATH_COUNTING + slacks->path_criticality[inet][ipin] = init_timing_criticality_val; +#endif + } else { + /* Set delay of global signals to zero. Non-global net + delays are set by update_net_delays_from_route_tree() + inside timing_driven_route_net(), which is only called + for non-global nets. */ + for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) { + net_delay[inet][ipin] = 0.; + } + } + } + + pres_fac = router_opts.first_iter_pres_fac; /* Typically 0 -> ignore cong. */ + + for (itry = 1; itry <= router_opts.max_router_iterations; itry++) { + begin = clock(); + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "Routing iteration: %d\n", itry); + + for (i = 0; i < num_nets; i++) { + inet = net_index[i]; + if (clb_net[inet].is_global == FALSE) { /* Skip global nets. */ + //vpr_printf(TIO_MESSAGE_INFO, "try routing net(%s)...\n", clb_net[inet].name); + + is_routable = timing_driven_route_net(inet, pres_fac, + router_opts.max_criticality, + router_opts.criticality_exp, router_opts.astar_fac, + router_opts.bend_cost, pin_criticality, + sink_order, rt_node_of_sink, net_delay[inet], slacks); + + /* Impossible to route? (disconnected rr_graph) */ + + if (!is_routable) { + vpr_printf(TIO_MESSAGE_INFO, "Routing failed for net (%s).\n", clb_net[inet].name); + free_timing_driven_route_structs(pin_criticality, + sink_order, rt_node_of_sink); + free(net_index); + free(sinks); + return (FALSE); + } + } + } + + if (itry == 1) { + /* Early exit code for cases where it is obvious that a successful route will not be found + Heuristic: If total wirelength used in first routing iteration is X% of total available wirelength, exit + */ + total_wirelength = 0; + available_wirelength = 0; + + for (i = 0; i < num_rr_nodes; i++) { + if (rr_node[i].type == CHANX || rr_node[i].type == CHANY) { + available_wirelength += 1 + rr_node[i].xhigh + - rr_node[i].xlow + rr_node[i].yhigh + - rr_node[i].ylow; + } + } + + for (inet = 0; inet < num_nets; inet++) { + if (clb_net[inet].is_global == FALSE + && clb_net[inet].num_sinks != 0) { /* Globals don't count. */ + get_num_bends_and_length(inet, &bends, &wirelength, + &segments); + + total_wirelength += wirelength; + } + } + vpr_printf(TIO_MESSAGE_INFO, "Wire length after first iteration %d, total available wire length %d, ratio %g\n", + total_wirelength, available_wirelength, + (float) (total_wirelength) / (float) (available_wirelength)); + if ((float) (total_wirelength) / (float) (available_wirelength)> FIRST_ITER_WIRELENTH_LIMIT) { + vpr_printf(TIO_MESSAGE_INFO, "Wire length usage ratio exceeds limit of %g, fail routing.\n", + FIRST_ITER_WIRELENTH_LIMIT); + free_timing_driven_route_structs(pin_criticality, sink_order, + rt_node_of_sink); + free(net_index); + free(sinks); + return FALSE; + } + } + + /* Make sure any CLB OPINs used up by subblocks being hooked directly * + * to them are reserved for that purpose. */ + + if (itry == 1) + rip_up_local_opins = FALSE; + else + rip_up_local_opins = TRUE; + + /* Xifan TANG: may need a new function + * OPINs should only be reserved when it directly connected to a subblock! + */ + /* + reserve_locally_used_opins(pres_fac, rip_up_local_opins, + clb_opins_used_locally); + */ + /* Xifan TANG: a smart function to detect which OPINs are used and update routing cost */ + auto_detect_and_reserve_locally_used_opins(pres_fac, rip_up_local_opins, clb_opins_used_locally); + + /* Pathfinder guys quit after finding a feasible route. I may want to keep * + * going longer, trying to improve timing. Think about this some. */ + + success = feasible_routing(); + if (success) { + vpr_printf(TIO_MESSAGE_INFO, "Successfully routed after %d routing iterations.\n", itry); + free_timing_driven_route_structs(pin_criticality, sink_order, rt_node_of_sink); + /* mrFPGA: Xifan TANG*/ + clear_buffer(); + /* END */ +#ifdef DEBUG + timing_driven_check_net_delays(net_delay); +#endif + /* mrFPGA: Xifan TANG*/ + if (is_wire_buffer) { + try_buffer_for_routing(net_delay); + load_timing_graph_net_delays(net_delay); + /* Print critical path delay - convert to nanoseconds. */ + critical_path_delay = get_critical_path_delay(); + vpr_printf(TIO_MESSAGE_INFO, "After buffer insertion, Critical path: %g ns\n", critical_path_delay); + load_best_buffer_list(); +#ifdef DEBUG + timing_driven_check_net_delays(net_delay); +#endif + } + /* END */ + free(net_index); + free(sinks); + return (TRUE); + } + + if (itry == 1) { + pres_fac = router_opts.initial_pres_fac; + pathfinder_update_cost(pres_fac, 0.); /* Acc_fac=0 for first iter. */ + } else { + pres_fac *= router_opts.pres_fac_mult; + + /* Avoid overflow for high iteration counts, even if acc_cost is big */ + pres_fac = std::min(pres_fac, static_cast(HUGE_POSITIVE_FLOAT / 1e5)); + + pathfinder_update_cost(pres_fac, router_opts.acc_fac); + } + + if (timing_analysis_enabled) { + /* Update slack values by doing another timing analysis. * + * Timing_driven_route_net updated the net delay values. */ + + load_timing_graph_net_delays(net_delay); + + #ifdef HACK_LUT_PIN_SWAPPING + do_timing_analysis(slacks, FALSE, TRUE, FALSE); + #else + do_timing_analysis(slacks, FALSE, FALSE, FALSE); + #endif + + /* Print critical path delay - convert to nanoseconds. */ + critical_path_delay = get_critical_path_delay(); + vpr_printf(TIO_MESSAGE_INFO, "Critical path: %g ns\n", critical_path_delay); + } else { + /* If timing analysis is not enabled, make sure that the criticalities and the * + * net_delays stay as 0 so that wirelength can be optimized. */ + + for (inet = 0; inet < num_nets; inet++) { + for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) { + slacks->timing_criticality[inet][ipin] = 0.; +#ifdef PATH_COUNTING + slacks->path_criticality[inet][ipin] = 0.; +#endif + net_delay[inet][ipin] = 0.; + } + } + } + + end = clock(); + #ifdef CLOCKS_PER_SEC + vpr_printf(TIO_MESSAGE_INFO, "Routing iteration took %g seconds.\n", (float)(end - begin) / CLOCKS_PER_SEC); + #else + vpr_printf(TIO_MESSAGE_INFO, "Routing iteration took %g seconds.\n", (float)(end - begin) / CLK_PER_SEC); + #endif + + fflush(stdout); + } + + vpr_printf(TIO_MESSAGE_INFO, "Routing failed.\n"); + free_timing_driven_route_structs(pin_criticality, sink_order, + rt_node_of_sink); + free(net_index); + free(sinks); + return (FALSE); +} + +void alloc_timing_driven_route_structs(float **pin_criticality_ptr, + int **sink_order_ptr, t_rt_node *** rt_node_of_sink_ptr) { + + /* Allocates all the structures needed only by the timing-driven router. */ + + int max_pins_per_net; + float *pin_criticality; + int *sink_order; + t_rt_node **rt_node_of_sink; + + max_pins_per_net = get_max_pins_per_net(); + + pin_criticality = (float *) my_malloc( + (max_pins_per_net - 1) * sizeof(float)); + *pin_criticality_ptr = pin_criticality - 1; /* First sink is pin #1. */ + + sink_order = (int *) my_malloc((max_pins_per_net - 1) * sizeof(int)); + *sink_order_ptr = sink_order - 1; + + rt_node_of_sink = (t_rt_node **) my_malloc( + (max_pins_per_net - 1) * sizeof(t_rt_node *)); + *rt_node_of_sink_ptr = rt_node_of_sink - 1; + + alloc_route_tree_timing_structs(); +} + +void free_timing_driven_route_structs(float *pin_criticality, int *sink_order, + t_rt_node ** rt_node_of_sink) { + + /* Frees all the stuctures needed only by the timing-driven router. */ + + free(pin_criticality + 1); /* Starts at index 1. */ + free(sink_order + 1); + free(rt_node_of_sink + 1); + free_route_tree_timing_structs(); +} + +static int get_max_pins_per_net(void) { + + /* Returns the largest number of pins on any non-global net. */ + + int inet, max_pins_per_net; + + max_pins_per_net = 0; + for (inet = 0; inet < num_nets; inet++) { + if (clb_net[inet].is_global == FALSE) { + max_pins_per_net = std::max(max_pins_per_net, + (clb_net[inet].num_sinks + 1)); + } + } + + return (max_pins_per_net); +} + +boolean timing_driven_route_net(int inet, float pres_fac, float max_criticality, + float criticality_exp, float astar_fac, float bend_cost, + float *pin_criticality, int *sink_order, + t_rt_node ** rt_node_of_sink, float *net_delay, t_slack * slacks) { + + /* Returns TRUE as long is found some way to hook up this net, even if that * + * way resulted in overuse of resources (congestion). If there is no way * + * to route this net, even ignoring congestion, it returns FALSE. In this * + * case the rr_graph is disconnected and you can give up. If slacks = NULL, * + * give each net a dummy criticality of 0. */ + + int ipin, num_sinks, itarget, target_pin, target_node, inode; + float target_criticality, old_tcost, new_tcost, largest_criticality, + old_back_cost, new_back_cost; + t_rt_node *rt_root; + struct s_heap *current; + struct s_trace *new_route_start_tptr; + int highfanout_rlim; + + /* Rip-up any old routing. */ + + pathfinder_update_one_cost(trace_head[inet], -1, pres_fac); + free_traceback(inet); + + for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) { + if (!slacks) { + /* Use criticality of 1. This makes all nets critical. Note: There is a big difference between setting pin criticality to 0 + compared to 1. If pin criticality is set to 0, then the current path delay is completely ignored during routing. By setting + pin criticality to 1, the current path delay to the pin will always be considered and optimized for */ + pin_criticality[ipin] = 1.0; + } else { +#ifdef PATH_COUNTING + /* Pin criticality is based on a weighted sum of timing and path criticalities. */ + pin_criticality[ipin] = ROUTE_PATH_WEIGHT * slacks->path_criticality[inet][ipin] + + (1 - ROUTE_PATH_WEIGHT) * slacks->timing_criticality[inet][ipin]; +#else + /* Pin criticality is based on only timing criticality. */ + pin_criticality[ipin] = slacks->timing_criticality[inet][ipin]; +#endif + /* Currently, pin criticality is between 0 and 1. Now shift it downwards + by 1 - max_criticality (max_criticality is 0.99 by default, so shift down + by 0.01) and cut off at 0. This means that all pins with small criticalities + (<0.01) get criticality 0 and are ignored entirely, and everything + else becomes a bit less critical. This effect becomes more pronounced if + max_criticality is set lower. */ + assert(pin_criticality[ipin] > -0.01 && pin_criticality[ipin] < 1.01); + pin_criticality[ipin] = std::max(pin_criticality[ipin] - (1.0 - max_criticality), 0.0); + + /* Take pin criticality to some power (1 by default). */ + pin_criticality[ipin] = pow(pin_criticality[ipin], criticality_exp); + + /* Cut off pin criticality at max_criticality. */ + pin_criticality[ipin] = std::min(pin_criticality[ipin], max_criticality); + } + } + + num_sinks = clb_net[inet].num_sinks; + heapsort(sink_order, pin_criticality, num_sinks, 0); + + /* Update base costs according to fanout and criticality rules */ + + largest_criticality = pin_criticality[sink_order[1]]; + update_rr_base_costs(inet, largest_criticality); + + mark_ends(inet); /* Only needed to check for multiply-connected SINKs */ + + rt_root = init_route_tree_to_source(inet); + + for (itarget = 1; itarget <= num_sinks; itarget++) { + target_pin = sink_order[itarget]; + target_node = net_rr_terminals[inet][target_pin]; + + target_criticality = pin_criticality[target_pin]; + + highfanout_rlim = mark_node_expansion_by_bin(inet, target_node, + rt_root); + + add_route_tree_to_heap(rt_root, target_node, target_criticality, + astar_fac); + + current = get_heap_head(); + + if (current == NULL) { /* Infeasible routing. No possible path for net. */ + vpr_printf(TIO_MESSAGE_INFO, "Cannot route net #%d (%s) to sink #%d -- no possible path.\n", + inet, clb_net[inet].name, itarget); + reset_path_costs(); + free_route_tree(rt_root); + return (FALSE); + } + + inode = current->index; + + while (inode != target_node) { + old_tcost = rr_node_route_inf[inode].path_cost; + new_tcost = current->cost; + + if (old_tcost > 0.99 * HUGE_POSITIVE_FLOAT) /* First time touched. */ + old_back_cost = HUGE_POSITIVE_FLOAT; + else + old_back_cost = rr_node_route_inf[inode].backward_path_cost; + + new_back_cost = current->backward_path_cost; + + /* I only re-expand a node if both the "known" backward cost is lower * + * in the new expansion (this is necessary to prevent loops from * + * forming in the routing and causing havoc) *and* the expected total * + * cost to the sink is lower than the old value. Different R_upstream * + * values could make a path with lower back_path_cost less desirable * + * than one with higher cost. Test whether or not I should disallow * + * re-expansion based on a higher total cost. */ + + if (old_tcost > new_tcost && old_back_cost > new_back_cost) { + rr_node_route_inf[inode].prev_node = current->u.prev_node; + rr_node_route_inf[inode].prev_edge = current->prev_edge; + rr_node_route_inf[inode].path_cost = new_tcost; + rr_node_route_inf[inode].backward_path_cost = new_back_cost; + + if (old_tcost > 0.99 * HUGE_POSITIVE_FLOAT) /* First time touched. */ + add_to_mod_list(&rr_node_route_inf[inode].path_cost); + + timing_driven_expand_neighbours(current, inet, bend_cost, + target_criticality, target_node, astar_fac, + highfanout_rlim); + } + + free_heap_data(current); + current = get_heap_head(); + + if (current == NULL) { /* Impossible routing. No path for net. */ + vpr_printf(TIO_MESSAGE_INFO, "Cannot route net #%d (%s) to sink #%d -- no possible path.\n", + inet, clb_net[inet].name, itarget); + reset_path_costs(); + free_route_tree(rt_root); + return (FALSE); + } + + inode = current->index; + } + + /* NB: In the code below I keep two records of the partial routing: the * + * traceback and the route_tree. The route_tree enables fast recomputation * + * of the Elmore delay to each node in the partial routing. The traceback * + * lets me reuse all the routines written for breadth-first routing, which * + * all take a traceback structure as input. Before this routine exits the * + * route_tree structure is destroyed; only the traceback is needed at that * + * point. */ + + rr_node_route_inf[inode].target_flag--; /* Connected to this SINK. */ + new_route_start_tptr = update_traceback(current, inet); + rt_node_of_sink[target_pin] = update_route_tree(current); + free_heap_data(current); + pathfinder_update_one_cost(new_route_start_tptr, 1, pres_fac); + + empty_heap(); + reset_path_costs(); + } + + /* For later timing analysis. */ + + update_net_delays_from_route_tree(net_delay, rt_node_of_sink, inet); + free_route_tree(rt_root); + return (TRUE); +} + +static void add_route_tree_to_heap(t_rt_node * rt_node, int target_node, + float target_criticality, float astar_fac) { + + /* Puts the entire partial routing below and including rt_node onto the heap * + * (except for those parts marked as not to be expanded) by calling itself * + * recursively. */ + + int inode; + t_rt_node *child_node; + t_linked_rt_edge *linked_rt_edge; + float tot_cost, backward_path_cost, R_upstream; + + /* Pre-order depth-first traversal */ + + if (rt_node->re_expand) { + inode = rt_node->inode; + backward_path_cost = target_criticality * rt_node->Tdel; + R_upstream = rt_node->R_upstream; + tot_cost = backward_path_cost + + astar_fac + * get_timing_driven_expected_cost(inode, target_node, + target_criticality, R_upstream); + node_to_heap(inode, tot_cost, NO_PREVIOUS, NO_PREVIOUS, + backward_path_cost, R_upstream); + } + + linked_rt_edge = rt_node->u.child_list; + + while (linked_rt_edge != NULL) { + child_node = linked_rt_edge->child; + add_route_tree_to_heap(child_node, target_node, target_criticality, + astar_fac); + linked_rt_edge = linked_rt_edge->next; + } +} + +static void timing_driven_expand_neighbours(struct s_heap *current, int inet, + float bend_cost, float criticality_fac, int target_node, + float astar_fac, int highfanout_rlim) { + + /* Puts all the rr_nodes adjacent to current on the heap. rr_nodes outside * + * the expanded bounding box specified in route_bb are not added to the * + * heap. */ + + int iconn, to_node, num_edges, inode, iswitch, target_x, target_y; + t_rr_type from_type, to_type; + float new_tot_cost, old_back_pcost, new_back_pcost, R_upstream; + float new_R_upstream, Tdel; + + inode = current->index; + old_back_pcost = current->backward_path_cost; + R_upstream = current->R_upstream; + num_edges = rr_node[inode].num_edges; + + target_x = rr_node[target_node].xhigh; + target_y = rr_node[target_node].yhigh; + + for (iconn = 0; iconn < num_edges; iconn++) { + to_node = rr_node[inode].edges[iconn]; + + if (rr_node[to_node].xhigh < route_bb[inet].xmin + || rr_node[to_node].xlow > route_bb[inet].xmax + || rr_node[to_node].yhigh < route_bb[inet].ymin + || rr_node[to_node].ylow > route_bb[inet].ymax) + continue; /* Node is outside (expanded) bounding box. */ + + if (clb_net[inet].num_sinks >= HIGH_FANOUT_NET_LIM) { + if (rr_node[to_node].xhigh < target_x - highfanout_rlim + || rr_node[to_node].xlow > target_x + highfanout_rlim + || rr_node[to_node].yhigh < target_y - highfanout_rlim + || rr_node[to_node].ylow > target_y + highfanout_rlim) + continue; /* Node is outside high fanout bin. */ + } + + /* Prune away IPINs that lead to blocks other than the target one. Avoids * + * the issue of how to cost them properly so they don't get expanded before * + * more promising routes, but makes route-throughs (via CLBs) impossible. * + * Change this if you want to investigate route-throughs. */ + + to_type = rr_node[to_node].type; + if (to_type == IPIN + && (rr_node[to_node].xhigh != target_x + || rr_node[to_node].yhigh != target_y)) + continue; + + /* new_back_pcost stores the "known" part of the cost to this node -- the * + * congestion cost of all the routing resources back to the existing route * + * plus the known delay of the total path back to the source. new_tot_cost * + * is this "known" backward cost + an expected cost to get to the target. */ + + new_back_pcost = old_back_pcost + + (1. - criticality_fac) * get_rr_cong_cost(to_node); + + iswitch = rr_node[inode].switches[iconn]; + if (switch_inf[iswitch].buffered) { + new_R_upstream = switch_inf[iswitch].R; + } else { + new_R_upstream = R_upstream + switch_inf[iswitch].R; + } + + Tdel = rr_node[to_node].C * (new_R_upstream + 0.5 * rr_node[to_node].R); + Tdel += switch_inf[iswitch].Tdel; + new_R_upstream += rr_node[to_node].R; + new_back_pcost += criticality_fac * Tdel; + + if (bend_cost != 0.) { + from_type = rr_node[inode].type; + to_type = rr_node[to_node].type; + if ((from_type == CHANX && to_type == CHANY) + || (from_type == CHANY && to_type == CHANX)) + new_back_pcost += bend_cost; + } + + new_tot_cost = new_back_pcost + + astar_fac + * get_timing_driven_expected_cost(to_node, target_node, + criticality_fac, new_R_upstream); + + node_to_heap(to_node, new_tot_cost, inode, iconn, new_back_pcost, + new_R_upstream); + + } /* End for all neighbours */ +} + +static float get_timing_driven_expected_cost(int inode, int target_node, + float criticality_fac, float R_upstream) { + + /* Determines the expected cost (due to both delay and resouce cost) to reach * + * the target node from inode. It doesn't include the cost of inode -- * + * that's already in the "known" path_cost. */ + + t_rr_type rr_type; + int cost_index, ortho_cost_index, num_segs_same_dir, num_segs_ortho_dir; + float expected_cost, cong_cost, Tdel; + + rr_type = rr_node[inode].type; + + if (rr_type == CHANX || rr_type == CHANY) { + num_segs_same_dir = get_expected_segs_to_target(inode, target_node, + &num_segs_ortho_dir); + cost_index = rr_node[inode].cost_index; + ortho_cost_index = rr_indexed_data[cost_index].ortho_cost_index; + + cong_cost = num_segs_same_dir * rr_indexed_data[cost_index].base_cost + + num_segs_ortho_dir + * rr_indexed_data[ortho_cost_index].base_cost; + cong_cost += rr_indexed_data[IPIN_COST_INDEX].base_cost + + rr_indexed_data[SINK_COST_INDEX].base_cost; + + Tdel = + num_segs_same_dir * rr_indexed_data[cost_index].T_linear + + num_segs_ortho_dir + * rr_indexed_data[ortho_cost_index].T_linear + + num_segs_same_dir * num_segs_same_dir + * rr_indexed_data[cost_index].T_quadratic + + num_segs_ortho_dir * num_segs_ortho_dir + * rr_indexed_data[ortho_cost_index].T_quadratic + + R_upstream + * (num_segs_same_dir + * rr_indexed_data[cost_index].C_load + + num_segs_ortho_dir + * rr_indexed_data[ortho_cost_index].C_load); + + Tdel += rr_indexed_data[IPIN_COST_INDEX].T_linear; + + expected_cost = criticality_fac * Tdel + + (1. - criticality_fac) * cong_cost; + return (expected_cost); + } + + else if (rr_type == IPIN) { /* Change if you're allowing route-throughs */ + return (rr_indexed_data[SINK_COST_INDEX].base_cost); + } + + else { /* Change this if you want to investigate route-throughs */ + return (0.); + } +} + +/* Macro used below to ensure that fractions are rounded up, but floating * + * point values very close to an integer are rounded to that integer. */ + +#define ROUND_UP(x) (ceil (x - 0.001)) + +static int get_expected_segs_to_target(int inode, int target_node, + int *num_segs_ortho_dir_ptr) { + + /* Returns the number of segments the same type as inode that will be needed * + * to reach target_node (not including inode) in each direction (the same * + * direction (horizontal or vertical) as inode and the orthogonal direction).*/ + + t_rr_type rr_type; + int target_x, target_y, num_segs_same_dir, cost_index, ortho_cost_index; + int no_need_to_pass_by_clb; + float inv_length, ortho_inv_length, ylow, yhigh, xlow, xhigh; + + target_x = rr_node[target_node].xlow; + target_y = rr_node[target_node].ylow; + cost_index = rr_node[inode].cost_index; + inv_length = rr_indexed_data[cost_index].inv_length; + ortho_cost_index = rr_indexed_data[cost_index].ortho_cost_index; + ortho_inv_length = rr_indexed_data[ortho_cost_index].inv_length; + rr_type = rr_node[inode].type; + + if (rr_type == CHANX) { + ylow = rr_node[inode].ylow; + xhigh = rr_node[inode].xhigh; + xlow = rr_node[inode].xlow; + + /* Count vertical (orthogonal to inode) segs first. */ + + if (ylow > target_y) { /* Coming from a row above target? */ + *num_segs_ortho_dir_ptr = + (int)(ROUND_UP((ylow - target_y + 1.) * ortho_inv_length)); + no_need_to_pass_by_clb = 1; + } else if (ylow < target_y - 1) { /* Below the CLB bottom? */ + *num_segs_ortho_dir_ptr = (int)(ROUND_UP((target_y - ylow) * + ortho_inv_length)); + no_need_to_pass_by_clb = 1; + } else { /* In a row that passes by target CLB */ + *num_segs_ortho_dir_ptr = 0; + no_need_to_pass_by_clb = 0; + } + + /* Now count horizontal (same dir. as inode) segs. */ + + if (xlow > target_x + no_need_to_pass_by_clb) { + num_segs_same_dir = (int)(ROUND_UP((xlow - no_need_to_pass_by_clb - + target_x) * inv_length)); + } else if (xhigh < target_x - no_need_to_pass_by_clb) { + num_segs_same_dir = (int)(ROUND_UP((target_x - no_need_to_pass_by_clb - + xhigh) * inv_length)); + } else { + num_segs_same_dir = 0; + } + } + + else { /* inode is a CHANY */ + ylow = rr_node[inode].ylow; + yhigh = rr_node[inode].yhigh; + xlow = rr_node[inode].xlow; + + /* Count horizontal (orthogonal to inode) segs first. */ + + if (xlow > target_x) { /* Coming from a column right of target? */ + *num_segs_ortho_dir_ptr = (int)( + ROUND_UP((xlow - target_x + 1.) * ortho_inv_length)); + no_need_to_pass_by_clb = 1; + } else if (xlow < target_x - 1) { /* Left of and not adjacent to the CLB? */ + *num_segs_ortho_dir_ptr = (int)(ROUND_UP((target_x - xlow) * + ortho_inv_length)); + no_need_to_pass_by_clb = 1; + } else { /* In a column that passes by target CLB */ + *num_segs_ortho_dir_ptr = 0; + no_need_to_pass_by_clb = 0; + } + + /* Now count vertical (same dir. as inode) segs. */ + + if (ylow > target_y + no_need_to_pass_by_clb) { + num_segs_same_dir = (int)(ROUND_UP((ylow - no_need_to_pass_by_clb - + target_y) * inv_length)); + } else if (yhigh < target_y - no_need_to_pass_by_clb) { + num_segs_same_dir = (int)(ROUND_UP((target_y - no_need_to_pass_by_clb - + yhigh) * inv_length)); + } else { + num_segs_same_dir = 0; + } + } + + return (num_segs_same_dir); +} + +static void update_rr_base_costs(int inet, float largest_criticality) { + + /* Changes the base costs of different types of rr_nodes according to the * + * criticality, fanout, etc. of the current net being routed (inet). */ + + float fanout, factor; + int index; + + fanout = clb_net[inet].num_sinks; + + /* Other reasonable values for factor include fanout and 1 */ + factor = sqrt(fanout); + + for (index = CHANX_COST_INDEX_START; index < num_rr_indexed_data; index++) { + if (rr_indexed_data[index].T_quadratic > 0.) { /* pass transistor */ + rr_indexed_data[index].base_cost = + rr_indexed_data[index].saved_base_cost * factor; + } else { + rr_indexed_data[index].base_cost = + rr_indexed_data[index].saved_base_cost; + } + } +} + +/* Nets that have high fanout can take a very long time to route. Each sink should be routed contained within a bin instead of the entire bounding box to speed things up */ +static int mark_node_expansion_by_bin(int inet, int target_node, + t_rt_node * rt_node) { + int target_x, target_y; + int rlim = 1; + int inode; + float area; + boolean success; + t_linked_rt_edge *linked_rt_edge; + t_rt_node * child_node; + + target_x = rr_node[target_node].xlow; + target_y = rr_node[target_node].ylow; + + if (clb_net[inet].num_sinks < HIGH_FANOUT_NET_LIM) { + /* This algorithm only applies to high fanout nets */ + return 1; + } + + area = (route_bb[inet].xmax - route_bb[inet].xmin) + * (route_bb[inet].ymax - route_bb[inet].ymin); + if (area <= 0) { + area = 1; + } + + rlim = (int)(ceil(sqrt((float) area / (float) clb_net[inet].num_sinks))); + if (rt_node == NULL || rt_node->u.child_list == NULL) { + /* If unknown traceback, set radius of bin to be size of chip */ + rlim = std::max(nx + 2, ny + 2); + return rlim; + } + + success = FALSE; + /* determine quickly a feasible bin radius to route sink for high fanout nets + this is necessary to prevent super long runtimes for high fanout nets; in best case, a reduction in complexity from O(N^2logN) to O(NlogN) (Swartz fast router) + */ + linked_rt_edge = rt_node->u.child_list; + while (success == FALSE && linked_rt_edge != NULL) { + while (linked_rt_edge != NULL && success == FALSE) { + child_node = linked_rt_edge->child; + inode = child_node->inode; + if (!(rr_node[inode].type == IPIN || rr_node[inode].type == SINK)) { + if (rr_node[inode].xlow <= target_x + rlim + && rr_node[inode].xhigh >= target_x - rlim + && rr_node[inode].ylow <= target_y + rlim + && rr_node[inode].yhigh >= target_y - rlim) { + success = TRUE; + } + } + linked_rt_edge = linked_rt_edge->next; + } + + if (success == FALSE) { + if (rlim > std::max(nx + 2, ny + 2)) { + vpr_printf(TIO_MESSAGE_ERROR, "VPR internal error, net %s has paths that are not found in traceback.\n", + clb_net[inet].name); + exit(1); + } + /* if sink not in bin, increase bin size until fit */ + rlim *= 2; + } else { + /* Sometimes might just catch a wire in the end segment, need to give it some channel space to explore */ + rlim += 4; + } + linked_rt_edge = rt_node->u.child_list; + } + + /* redetermine expansion based on rlim */ + linked_rt_edge = rt_node->u.child_list; + while (linked_rt_edge != NULL) { + child_node = linked_rt_edge->child; + inode = child_node->inode; + if (!(rr_node[inode].type == IPIN || rr_node[inode].type == SINK)) { + if (rr_node[inode].xlow <= target_x + rlim + && rr_node[inode].xhigh >= target_x - rlim + && rr_node[inode].ylow <= target_y + rlim + && rr_node[inode].yhigh >= target_y - rlim) { + child_node->re_expand = TRUE; + } else { + child_node->re_expand = FALSE; + } + } + linked_rt_edge = linked_rt_edge->next; + } + return rlim; +} + +#define ERROR_TOL 0.0001 + +static void timing_driven_check_net_delays(float **net_delay) { + + /* Checks that the net delays computed incrementally during timing driven * + * routing match those computed from scratch by the net_delay.c module. */ + + int inet, ipin; + float **net_delay_check; + + t_chunk list_head_net_delay_check_ch = {NULL, 0, NULL}; + + /*struct s_linked_vptr *ch_list_head_net_delay_check;*/ + + net_delay_check = alloc_net_delay(&list_head_net_delay_check_ch, clb_net, + num_nets); + load_net_delay_from_routing(net_delay_check, clb_net, num_nets); + + for (inet = 0; inet < num_nets; inet++) { + for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) { + if (net_delay_check[inet][ipin] == 0.) { /* Should be only GLOBAL nets */ + if (fabs(net_delay[inet][ipin]) > ERROR_TOL) { + vpr_printf(TIO_MESSAGE_ERROR, "in timing_driven_check_net_delays: net %d pin %d.\n", + inet, ipin); + vpr_printf(TIO_MESSAGE_ERROR, "\tIncremental calc. net_delay is %g, but from scratch net delay is %g.\n", + net_delay[inet][ipin], net_delay_check[inet][ipin]); + exit(1); + } + } else { + if (fabs(1.0 - net_delay[inet][ipin] / net_delay_check[inet][ipin]) > ERROR_TOL) { + vpr_printf(TIO_MESSAGE_ERROR, "in timing_driven_check_net_delays: net %d pin %d.\n", + inet, ipin); + vpr_printf(TIO_MESSAGE_ERROR, "\tIncremental calc. net_delay is %g, but from scratch net delay is %g.\n", + net_delay[inet][ipin], net_delay_check[inet][ipin]); + exit(1); + } + } + } + } + + free_net_delay(net_delay_check, &list_head_net_delay_check_ch); + vpr_printf(TIO_MESSAGE_INFO, "Completed net delay value cross check successfully.\n"); +} diff --git a/vpr7_rram/vpr/SRC/route/route_timing.h b/vpr7_rram/vpr/SRC/route/route_timing.h new file mode 100755 index 000000000..d6f6192bc --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/route_timing.h @@ -0,0 +1,11 @@ +boolean try_timing_driven_route(struct s_router_opts router_opts, + float **net_delay, t_slack * slacks, t_ivec ** clb_opins_used_locally, + boolean timing_analysis_enabled); +boolean timing_driven_route_net(int inet, float pres_fac, float max_criticality, + float criticality_exp, float astar_fac, float bend_cost, + float *pin_criticality, int *sink_order, t_rt_node ** rt_node_of_sink, + float *net_delay, t_slack * slacks); +void alloc_timing_driven_route_structs(float **pin_criticality_ptr, + int **sink_order_ptr, t_rt_node *** rt_node_of_sink_ptr); +void free_timing_driven_route_structs(float *pin_criticality, int *sink_order, + t_rt_node ** rt_node_of_sink); diff --git a/vpr7_rram/vpr/SRC/route/route_tree_timing.c b/vpr7_rram/vpr/SRC/route/route_tree_timing.c new file mode 100755 index 000000000..409dac801 --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/route_tree_timing.c @@ -0,0 +1,519 @@ +#include +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "route_common.h" +#include "route_tree_timing.h" + +/* mrFPGA: Xifan TANG */ +#include "mrfpga_globals.h" +/* end */ + +/* This module keeps track of the partial routing tree for timing-driven * + * routing. The normal traceback structure doesn't provide enough info * + * about the partial routing during timing-driven routing, so the routines * + * in this module are used to keep a tree representation of the partial * + * routing during timing-driven routing. This allows rapid incremental * + * timing analysis. The net_delay module does timing analysis in one step * + * (not incrementally as pieces of the routing are added). I could probably * + * one day remove a lot of net_delay.c and call the corresponding routines * + * here, but it's useful to have a from-scratch delay calculator to check * + * the results of this one. */ + +/********************** Variables local to this module ***********************/ + +/* Array below allows mapping from any rr_node to any rt_node currently in * + * the rt_tree. */ + +static t_rt_node **rr_node_to_rt_node = NULL; /* [0..num_rr_nodes-1] */ + +/* Frees lists for fast addition and deletion of nodes and edges. */ + +static t_rt_node *rt_node_free_list = NULL; +static t_linked_rt_edge *rt_edge_free_list = NULL; + +/********************** Subroutines local to this module *********************/ + +static t_rt_node *alloc_rt_node(void); + +static void free_rt_node(t_rt_node * rt_node); + +static t_linked_rt_edge *alloc_linked_rt_edge(void); + +static void free_linked_rt_edge(t_linked_rt_edge * rt_edge); + +static t_rt_node *add_path_to_route_tree(struct s_heap *hptr, + t_rt_node ** sink_rt_node_ptr); + +static void load_new_path_R_upstream(t_rt_node * start_of_new_path_rt_node); + +static t_rt_node *update_unbuffered_ancestors_C_downstream( + t_rt_node * start_of_new_path_rt_node); + +static void load_rt_subtree_Tdel(t_rt_node * subtree_rt_root, float Tarrival); + +/************************** Subroutine definitions ***************************/ + +void alloc_route_tree_timing_structs(void) { + + /* Allocates any structures needed to build the routing trees. */ + + if (rr_node_to_rt_node != NULL || rt_node_free_list != NULL + || rt_node_free_list != NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "in alloc_route_tree_timing_structs: old structures already exist.\n"); + exit(1); + } + + rr_node_to_rt_node = (t_rt_node **) my_malloc( + num_rr_nodes * sizeof(t_rt_node *)); +} + +void free_route_tree_timing_structs(void) { + + /* Frees the structures needed to build routing trees, and really frees * + * (i.e. calls free) all the data on the free lists. */ + + t_rt_node *rt_node, *next_node; + t_linked_rt_edge *rt_edge, *next_edge; + + free(rr_node_to_rt_node); + rr_node_to_rt_node = NULL; + + rt_node = rt_node_free_list; + + while (rt_node != NULL) { + next_node = rt_node->u.next; + free(rt_node); + rt_node = next_node; + } + + rt_node_free_list = NULL; + + rt_edge = rt_edge_free_list; + + while (rt_edge != NULL) { + next_edge = rt_edge->next; + free(rt_edge); + rt_edge = next_edge; + } + + rt_edge_free_list = NULL; +} + +static t_rt_node * +alloc_rt_node(void) { + + /* Allocates a new rt_node, from the free list if possible, from the free * + * store otherwise. */ + + t_rt_node *rt_node; + + rt_node = rt_node_free_list; + + if (rt_node != NULL) { + rt_node_free_list = rt_node->u.next; + } else { + rt_node = (t_rt_node *) my_malloc(sizeof(t_rt_node)); + } + + return (rt_node); +} + +static void free_rt_node(t_rt_node * rt_node) { + + /* Adds rt_node to the proper free list. */ + + rt_node->u.next = rt_node_free_list; + rt_node_free_list = rt_node; +} + +static t_linked_rt_edge * +alloc_linked_rt_edge(void) { + + /* Allocates a new linked_rt_edge, from the free list if possible, from the * + * free store otherwise. */ + + t_linked_rt_edge *linked_rt_edge; + + linked_rt_edge = rt_edge_free_list; + + if (linked_rt_edge != NULL) { + rt_edge_free_list = linked_rt_edge->next; + } else { + linked_rt_edge = (t_linked_rt_edge *) my_malloc( + sizeof(t_linked_rt_edge)); + } + + return (linked_rt_edge); +} + +static void free_linked_rt_edge(t_linked_rt_edge * rt_edge) { + + /* Adds the rt_edge to the rt_edge free list. */ + + rt_edge->next = rt_edge_free_list; + rt_edge_free_list = rt_edge; +} + +t_rt_node * +init_route_tree_to_source(int inet) { + + /* Initializes the routing tree to just the net source, and returns the root * + * node of the rt_tree (which is just the net source). */ + + t_rt_node *rt_root; + int inode; + + rt_root = alloc_rt_node(); + rt_root->u.child_list = NULL; + rt_root->parent_node = NULL; + rt_root->parent_switch = OPEN; + rt_root->re_expand = TRUE; + + inode = net_rr_terminals[inet][0]; /* Net source */ + + rt_root->inode = inode; + rt_root->C_downstream = rr_node[inode].C; + rt_root->R_upstream = rr_node[inode].R; + rt_root->Tdel = 0.5 * rr_node[inode].R * rr_node[inode].C; + rr_node_to_rt_node[inode] = rt_root; + + return (rt_root); +} + +t_rt_node * +update_route_tree(struct s_heap * hptr) { + + /* Adds the most recently finished wire segment to the routing tree, and * + * updates the Tdel, etc. numbers for the rest of the routing tree. hptr * + * is the heap pointer of the SINK that was reached. This routine returns * + * a pointer to the rt_node of the SINK that it adds to the routing. */ + + t_rt_node *start_of_new_path_rt_node, *sink_rt_node; + t_rt_node *unbuffered_subtree_rt_root, *subtree_parent_rt_node; + float Tdel_start; + short iswitch; + + start_of_new_path_rt_node = add_path_to_route_tree(hptr, &sink_rt_node); + load_new_path_R_upstream(start_of_new_path_rt_node); + unbuffered_subtree_rt_root = update_unbuffered_ancestors_C_downstream( + start_of_new_path_rt_node); + + subtree_parent_rt_node = unbuffered_subtree_rt_root->parent_node; + + if (subtree_parent_rt_node != NULL) { /* Parent exists. */ + Tdel_start = subtree_parent_rt_node->Tdel; + iswitch = unbuffered_subtree_rt_root->parent_switch; + Tdel_start += switch_inf[iswitch].R + * unbuffered_subtree_rt_root->C_downstream; + Tdel_start += switch_inf[iswitch].Tdel; + } else { /* Subtree starts at SOURCE */ + Tdel_start = 0.; + } + + load_rt_subtree_Tdel(unbuffered_subtree_rt_root, Tdel_start); + + return (sink_rt_node); +} + +static t_rt_node * +add_path_to_route_tree(struct s_heap *hptr, t_rt_node ** sink_rt_node_ptr) { + + /* Adds the most recent wire segment, ending at the SINK indicated by hptr, * + * to the routing tree. It returns the first (most upstream) new rt_node, * + * and (via a pointer) the rt_node of the new SINK. */ + + int inode, remaining_connections_to_sink, no_route_throughs; + short iedge, iswitch; + float C_downstream; + t_rt_node *rt_node, *downstream_rt_node, *sink_rt_node; + t_linked_rt_edge *linked_rt_edge; + + inode = hptr->index; + +#ifdef DEBUG + if (rr_node[inode].type != SINK) { + vpr_printf(TIO_MESSAGE_ERROR, "in add_path_to_route_tree. Expected type = SINK (%d).\n", SINK); + vpr_printf(TIO_MESSAGE_INFO, "Got type = %d.", rr_node[inode].type); + exit(1); + } +#endif + + remaining_connections_to_sink = rr_node_route_inf[inode].target_flag; + sink_rt_node = alloc_rt_node(); + sink_rt_node->u.child_list = NULL; + sink_rt_node->inode = inode; + C_downstream = rr_node[inode].C; + sink_rt_node->C_downstream = C_downstream; + rr_node_to_rt_node[inode] = sink_rt_node; + + /* In the code below I'm marking SINKs and IPINs as not to be re-expanded. * + * Undefine NO_ROUTE_THROUGHS if you want route-throughs or ipin doglegs. * + * It makes the code more efficient (though not vastly) to prune this way * + * when there aren't route-throughs or ipin doglegs. */ + +#define NO_ROUTE_THROUGHS 1 /* Can't route through unused CLB outputs */ + no_route_throughs = 1; + if (no_route_throughs == 1) + sink_rt_node->re_expand = FALSE; + else { + if (remaining_connections_to_sink == 0) { /* Usual case */ + sink_rt_node->re_expand = TRUE; + } + + /* Weird case. This net connects several times to the same SINK. Thus I * + * can't re_expand this node as part of the partial routing for subsequent * + * connections, since I need to reach it again via another path. */ + + else { + sink_rt_node->re_expand = FALSE; + } + } + + /* Now do it's predecessor. */ + + downstream_rt_node = sink_rt_node; + inode = hptr->u.prev_node; + iedge = hptr->prev_edge; + iswitch = rr_node[inode].switches[iedge]; + + /* For all "new" nodes in the path */ + + while (rr_node_route_inf[inode].prev_node != NO_PREVIOUS) { + linked_rt_edge = alloc_linked_rt_edge(); + linked_rt_edge->child = downstream_rt_node; + linked_rt_edge->iswitch = iswitch; + linked_rt_edge->next = NULL; + + rt_node = alloc_rt_node(); + downstream_rt_node->parent_node = rt_node; + downstream_rt_node->parent_switch = iswitch; + + rt_node->u.child_list = linked_rt_edge; + rt_node->inode = inode; + + if (switch_inf[iswitch].buffered == FALSE) + C_downstream += rr_node[inode].C; + else + C_downstream = rr_node[inode].C; + + /* mrFPGA : Xifan TANG*/ + if (is_isolation) { + C_downstream += switch_inf[iswitch].Cin; + if (FALSE == switch_inf[iswitch].buffered) { + C_downstream += switch_inf[iswitch].Cout; + } + } + /* end */ + + rt_node->C_downstream = C_downstream; + rr_node_to_rt_node[inode] = rt_node; + + if (no_route_throughs == 1) + if (rr_node[inode].type == IPIN) + rt_node->re_expand = FALSE; + else + rt_node->re_expand = TRUE; + + else { + if (remaining_connections_to_sink == 0) { /* Normal case */ + rt_node->re_expand = TRUE; + } else { /* This is the IPIN before a multiply-connected SINK */ + rt_node->re_expand = FALSE; + + /* Reset flag so wire segments get reused */ + + remaining_connections_to_sink = 0; + } + } + + downstream_rt_node = rt_node; + iedge = rr_node_route_inf[inode].prev_edge; + inode = rr_node_route_inf[inode].prev_node; + iswitch = rr_node[inode].switches[iedge]; + } + + /* Inode is the join point to the old routing */ + + rt_node = rr_node_to_rt_node[inode]; + + linked_rt_edge = alloc_linked_rt_edge(); + linked_rt_edge->child = downstream_rt_node; + linked_rt_edge->iswitch = iswitch; + linked_rt_edge->next = rt_node->u.child_list; + rt_node->u.child_list = linked_rt_edge; + + downstream_rt_node->parent_node = rt_node; + downstream_rt_node->parent_switch = iswitch; + + *sink_rt_node_ptr = sink_rt_node; + return (downstream_rt_node); +} + +static void load_new_path_R_upstream(t_rt_node * start_of_new_path_rt_node) { + + /* Sets the R_upstream values of all the nodes in the new path to the * + * correct value. */ + + float R_upstream; + int inode; + short iswitch; + t_rt_node *rt_node, *parent_rt_node; + t_linked_rt_edge *linked_rt_edge; + + rt_node = start_of_new_path_rt_node; + iswitch = rt_node->parent_switch; + inode = rt_node->inode; + parent_rt_node = rt_node->parent_node; + + R_upstream = switch_inf[iswitch].R + rr_node[inode].R; + + if (switch_inf[iswitch].buffered == FALSE) + R_upstream += parent_rt_node->R_upstream; + + rt_node->R_upstream = R_upstream; + + /* Note: the traversal below makes use of the fact that this new path * + * really is a path (not a tree with branches) to do a traversal without * + * recursion, etc. */ + + linked_rt_edge = rt_node->u.child_list; + + while (linked_rt_edge != NULL) { /* While SINK not reached. */ + +#ifdef DEBUG + if (linked_rt_edge->next != NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "in load_new_path_R_upstream: new routing addition is a tree (not a path).\n"); + exit(1); + } +#endif + + rt_node = linked_rt_edge->child; + iswitch = linked_rt_edge->iswitch; + inode = rt_node->inode; + + if (switch_inf[iswitch].buffered) + R_upstream = switch_inf[iswitch].R + rr_node[inode].R; + else + R_upstream += switch_inf[iswitch].R + rr_node[inode].R; + + rt_node->R_upstream = R_upstream; + linked_rt_edge = rt_node->u.child_list; + } +} + +static t_rt_node * +update_unbuffered_ancestors_C_downstream(t_rt_node * start_of_new_path_rt_node) { + + /* Updates the C_downstream values for the ancestors of the new path. Once * + * a buffered switch is found amongst the ancestors, no more ancestors are * + * affected. Returns the root of the "unbuffered subtree" whose Tdel * + * values are affected by the new path's addition. */ + + t_rt_node *rt_node, *parent_rt_node; + short iswitch; + float C_downstream_addition; + + rt_node = start_of_new_path_rt_node; + C_downstream_addition = rt_node->C_downstream; + parent_rt_node = rt_node->parent_node; + iswitch = rt_node->parent_switch; + + /* mrFPGA: Xifan TANG */ + if (is_isolation) { + if (parent_rt_node != NULL && switch_inf[iswitch].buffered) { + rt_node = parent_rt_node; + C_downstream_addition = switch_inf[iswitch].Cin; + rt_node->C_downstream += C_downstream_addition; + parent_rt_node = rt_node->parent_node; + iswitch = rt_node->parent_switch; + } else { + C_downstream_addition += switch_inf[iswitch].Cin + switch_inf[iswitch].Cout; + } + } + /* end */ + + while (parent_rt_node != NULL && switch_inf[iswitch].buffered == FALSE) { + rt_node = parent_rt_node; + rt_node->C_downstream += C_downstream_addition; + parent_rt_node = rt_node->parent_node; + iswitch = rt_node->parent_switch; + } + + return (rt_node); +} + +static void load_rt_subtree_Tdel(t_rt_node * subtree_rt_root, float Tarrival) { + + /* Updates the Tdel values of the subtree rooted at subtree_rt_root by * + * by calling itself recursively. The C_downstream values of all the nodes * + * must be correct before this routine is called. Tarrival is the time at * + * at which the signal arrives at this node's *input*. */ + + int inode; + short iswitch; + t_rt_node *child_node; + t_linked_rt_edge *linked_rt_edge; + float Tdel, Tchild; + + inode = subtree_rt_root->inode; + + /* Assuming the downstream connections are, on average, connected halfway * + * along a wire segment's length. See discussion in net_delay.c if you want * + * to change this. */ + + Tdel = Tarrival + 0.5 * subtree_rt_root->C_downstream * rr_node[inode].R; + subtree_rt_root->Tdel = Tdel; + + /* Now expand the children of this node to load their Tdel values (depth- * + * first pre-order traversal). */ + + linked_rt_edge = subtree_rt_root->u.child_list; + + while (linked_rt_edge != NULL) { + iswitch = linked_rt_edge->iswitch; + child_node = linked_rt_edge->child; + + Tchild = Tdel + switch_inf[iswitch].R * child_node->C_downstream; + Tchild += switch_inf[iswitch].Tdel; /* Intrinsic switch delay. */ + load_rt_subtree_Tdel(child_node, Tchild); + + linked_rt_edge = linked_rt_edge->next; + } +} + +void free_route_tree(t_rt_node * rt_node) { + + /* Puts the rt_nodes and edges in the tree rooted at rt_node back on the * + * free lists. Recursive, depth-first post-order traversal. */ + + t_rt_node *child_node; + t_linked_rt_edge *rt_edge, *next_edge; + + rt_edge = rt_node->u.child_list; + + while (rt_edge != NULL) { /* For all children */ + child_node = rt_edge->child; + free_route_tree(child_node); + next_edge = rt_edge->next; + free_linked_rt_edge(rt_edge); + rt_edge = next_edge; + } + + free_rt_node(rt_node); +} + +void update_net_delays_from_route_tree(float *net_delay, + t_rt_node ** rt_node_of_sink, int inet) { + + /* Goes through all the sinks of this net and copies their delay values from * + * the route_tree to the net_delay array. */ + + int isink; + t_rt_node *sink_rt_node; + + for (isink = 1; isink <= clb_net[inet].num_sinks; isink++) { + sink_rt_node = rt_node_of_sink[isink]; + net_delay[isink] = sink_rt_node->Tdel; + } +} diff --git a/vpr7_rram/vpr/SRC/route/route_tree_timing.h b/vpr7_rram/vpr/SRC/route/route_tree_timing.h new file mode 100755 index 000000000..50d9d7c18 --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/route_tree_timing.h @@ -0,0 +1,68 @@ +/************** Types and defines exported by route_tree_timing.c ************/ + +struct s_linked_rt_edge { + struct s_rt_node *child; + short iswitch; + struct s_linked_rt_edge *next; +}; + +typedef struct s_linked_rt_edge t_linked_rt_edge; + +/* Linked list listing the children of an rt_node. * + * child: Pointer to an rt_node (child of the current node). * + * iswitch: Index of the switch type used to connect to the child node. * + * next: Pointer to the next linked_rt_edge in the linked list (allows * + * you to get the next child of the current rt_node). */ + +struct s_rt_node { + union { + t_linked_rt_edge *child_list; + struct s_rt_node *next; + } u; + struct s_rt_node *parent_node; + short parent_switch; + short re_expand; + int inode; + float C_downstream; + float R_upstream; + float Tdel; +}; + +typedef struct s_rt_node t_rt_node; + +/* Structure describing one node in a routing tree (used to get net delays * + * incrementally during routing, as pieces are being added). * + * u.child_list: Pointer to a linked list of linked_rt_edge. Each one of * + * the linked list entries gives a child of this node. * + * u.next: Used only when this node is on the free list. Gives the next * + * node on the free list. * + * parent_node: Pointer to the rt_node that is this node's parent (used to * + * make bottom to top traversals). * + * re_expand: (really boolean). Should this node be put on the heap as * + * part of the partial routing to act as a source for subsequent * + * connections? TRUE->yes, FALSE-> no. * + * parent_switch: Index of the switch type driving this node (by its * + * parent). * + * inode: index (ID) of the rr_node that corresponds to this rt_node. * + * C_downstream: Total downstream capacitance from this rt_node. That is, * + * the total C of the subtree rooted at the current node, * + * including the C of the current node. * + * R_upstream: Total upstream resistance from this rt_node to the net * + * source, including any rr_node[].R of this node. * + * Tdel: Time delay for the signal to get from the net source to this node. * + * Includes the time to go through this node. */ + +/**************** Subroutines exported by route_tree_timing.c ***************/ + +void alloc_route_tree_timing_structs(void); + +void free_route_tree_timing_structs(void); + +t_rt_node *init_route_tree_to_source(int inet); + +void free_route_tree(t_rt_node * rt_node); + +t_rt_node *update_route_tree(struct s_heap *hptr); + +void update_net_delays_from_route_tree(float *net_delay, + t_rt_node ** rt_node_of_sink, int inet); diff --git a/vpr7_rram/vpr/SRC/route/rr_graph.c b/vpr7_rram/vpr/SRC/route/rr_graph.c new file mode 100755 index 000000000..4cdca0a76 --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/rr_graph.c @@ -0,0 +1,2924 @@ +#include +#include +#include +#include +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph_util.h" +#include "rr_graph.h" +#include "rr_graph2.h" +#include "rr_graph_sbox.h" +#include "check_rr_graph.h" +#include "rr_graph_timing_params.h" +#include "rr_graph_indexed_data.h" +#include "vpr_utils.h" +#include "read_xml_arch_file.h" +#include "ReadOptions.h" + +/* Xifan TANG: SWSEG SUPPORT */ +#include "rr_graph_swseg.h" +/* end */ +/* Xifan TANG: opin_to_cb support */ +#include "rr_graph_opincb.h" +/* end */ + +/* mrFPGA: Xifan TANG */ +#include "mrfpga_globals.h" +/* end */ + +/* #define ENABLE_DUMP */ +/* #define MUX_SIZE_DIST_DISPLAY */ + +/* mux size statistic data structures */ + +typedef struct s_mux { + int size; + struct s_mux *next; +} t_mux; + +typedef struct s_mux_size_distribution { + int mux_count; + int max_index; + int *distr; + struct s_mux_size_distribution *next; +} t_mux_size_distribution; + +typedef struct s_clb_to_clb_directs { + t_type_descriptor *from_clb_type; + int from_clb_pin_start_index; + int from_clb_pin_end_index; + t_type_descriptor *to_clb_type; + int to_clb_pin_start_index; + int to_clb_pin_end_index; +} t_clb_to_clb_directs; + +/* Xifan TANG: opin_to_cb support */ +#include "pb_pin_eq_auto_detect.h" +/* end */ + +/* UDSD Modifications by WMF End */ + +/******************* Variables local to this module. ***********************/ + +/* Used to free "chunked" memory. If NULL, no rr_graph exists right now. */ +static t_chunk rr_mem_ch = {NULL, 0, NULL}; + +/* Status of current chunk being dished out by calls to my_chunk_malloc. */ + +/********************* Subroutines local to this module. *******************/ +static int ****alloc_and_load_pin_to_track_map(INP enum e_pin_type pin_type, + INP int nodes_per_chan, INP int *Fc, INP t_type_ptr Type, + INP boolean perturb_switch_pattern, + INP enum e_directionality directionality); + +static struct s_ivec ***alloc_and_load_track_to_pin_lookup( + INP int ****pin_to_track_map, INP int *Fc, INP int height, + INP int num_pins, INP int nodes_per_chan); + +static void build_bidir_rr_opins(INP int i, INP int j, + INOUTP t_rr_node * L_rr_node, INP t_ivec *** L_rr_node_indices, + INP int *****opin_to_track_map, INP int **Fc_out, + INP boolean * L_rr_edge_done, INP t_seg_details * seg_details, + INP struct s_grid_tile **L_grid, INP int delayless_switch, + INP t_direct_inf *directs, INP int num_directs, INP t_clb_to_clb_directs *clb_to_clb_directs); + +static void build_unidir_rr_opins(INP int i, INP int j, + INP struct s_grid_tile **L_grid, INP int **Fc_out, + INP int nodes_per_chan, INP t_seg_details * seg_details, + INOUTP int **Fc_xofs, INOUTP int **Fc_yofs, + INOUTP t_rr_node * L_rr_node, INOUTP boolean * L_rr_edge_done, + OUTP boolean * Fc_clipped, INP t_ivec *** L_rr_node_indices, INP int delayless_switch, + INP t_direct_inf *directs, INP int num_directs, INP t_clb_to_clb_directs *clb_to_clb_directs); + +static int get_opin_direct_connecions(int x, int y, int opin, INOUTP t_linked_edge ** edge_list_ptr, INP t_ivec *** L_rr_node_indices, + INP int delayless_switch, INP t_direct_inf *directs, INP int num_directs, INP t_clb_to_clb_directs *clb_to_clb_directs); + +static void alloc_and_load_rr_graph(INP int num_nodes, + INP t_rr_node * L_rr_node, INP int num_seg_types, + INP t_seg_details * seg_details, INP boolean * L_rr_edge_done, + INP struct s_ivec ****track_to_ipin_lookup, + INP int *****opin_to_track_map, INP struct s_ivec ***switch_block_conn, + INP struct s_grid_tile **L_grid, INP int L_nx, INP int L_ny, INP int Fs, + INP short *****sblock_pattern, INP int **Fc_out, INP int **Fc_xofs, + INP int **Fc_yofs, INP t_ivec *** L_rr_node_indices, + INP int nodes_per_chan, INP enum e_switch_block_type sb_type, + INP int delayless_switch, INP enum e_directionality directionality, + INP int wire_to_ipin_switch, OUTP boolean * Fc_clipped, INP t_direct_inf *directs, INP int num_directs, INP t_clb_to_clb_directs *clb_to_clb_directs); + +static void load_uniform_switch_pattern(INP t_type_ptr type, + INOUTP int ****tracks_connected_to_pin, INP int num_phys_pins, + INP int *pin_num_ordering, INP int *side_ordering, + INP int *offset_ordering, INP int nodes_per_chan, INP int Fc, + INP enum e_directionality directionality); + +static void load_perturbed_switch_pattern(INP t_type_ptr type, + INOUTP int ****tracks_connected_to_pin, INP int num_phys_pins, + INP int *pin_num_ordering, INP int *side_ordering, + INP int *offset_ordering, INP int nodes_per_chan, INP int Fc, + INP enum e_directionality directionality); + +static void check_all_tracks_reach_pins(t_type_ptr type, + int ****tracks_connected_to_pin, int nodes_per_chan, int Fc, + enum e_pin_type ipin_or_opin); + +static boolean *alloc_and_load_perturb_ipins(INP int nodes_per_chan, + INP int L_num_types, INP int **Fc_in, INP int **Fc_out, + INP enum e_directionality directionality); + +static void build_rr_sinks_sources(INP int i, INP int j, + INP t_rr_node * L_rr_node, INP t_ivec *** L_rr_node_indices, + INP int delayless_switch, INP struct s_grid_tile **L_grid); + +static void build_rr_xchan(INP int i, INP int j, + INP struct s_ivec ****track_to_ipin_lookup, + INP struct s_ivec ***switch_block_conn, INP int cost_index_offset, + INP int nodes_per_chan, INP int *opin_mux_size, + INP short *****sblock_pattern, INP int Fs_per_side, + INP t_seg_details * seg_details, INP t_ivec *** L_rr_node_indices, + INP boolean * L_rr_edge_done, INOUTP t_rr_node * L_rr_node, + INP int wire_to_ipin_switch, INP enum e_directionality directionality); + +static void build_rr_ychan(INP int i, INP int j, + INP struct s_ivec ****track_to_ipin_lookup, + INP struct s_ivec ***switch_block_conn, INP int cost_index_offset, + INP int nodes_per_chan, INP int *opin_mux_size, + INP short *****sblock_pattern, INP int Fs_per_side, + INP t_seg_details * seg_details, INP t_ivec *** L_rr_node_indices, + INP boolean * L_rr_edge_done, INOUTP t_rr_node * L_rr_node, + INP int wire_to_ipin_switch, INP enum e_directionality directionality); + +static void rr_graph_externals(t_timing_inf timing_inf, + t_segment_inf * segment_inf, int num_seg_types, int nodes_per_chan, + int wire_to_ipin_switch, enum e_base_cost_type base_cost_type); + +void alloc_and_load_edges_and_switches(INP t_rr_node * L_rr_node, INP int inode, + INP int num_edges, INP boolean * L_rr_edge_done, + INP t_linked_edge * edge_list_head); + +static void alloc_net_rr_terminals(void); + +static void alloc_and_load_rr_clb_source(t_ivec *** L_rr_node_indices); + +static t_clb_to_clb_directs *alloc_and_load_clb_to_clb_directs(INP t_direct_inf *directs, INP int num_directs); + +#if 0 +static void load_uniform_opin_switch_pattern_paired(INP int *Fc_out, + INP int num_pins, + INP int *pins_in_chan_seg, + INP int num_wire_inc_muxes, + INP int num_wire_dec_muxes, + INP int *wire_inc_muxes, + INP int *wire_dec_muxes, + INOUTP t_rr_node * L_rr_node, + INOUTP boolean * + L_rr_edge_done, + INP t_seg_details * + seg_details, + OUTP boolean * Fc_clipped); +#endif +void watch_edges(int inode, t_linked_edge * edge_list_head); +#if MUX_SIZE_DIST_DISPLAY +static void view_mux_size_distribution(t_ivec *** L_rr_node_indices, + int nodes_per_chan, + t_seg_details * seg_details_x, + t_seg_details * seg_details_y); +static void print_distribution(FILE * fptr, + t_mux_size_distribution * distr_struct); +#endif + +static void free_type_pin_to_track_map(int***** ipin_to_track_map, + t_type_ptr types); + +static void free_type_track_to_ipin_map(struct s_ivec**** track_to_pin_map, + t_type_ptr types, int nodes_per_chan); + +static t_seg_details *alloc_and_load_global_route_seg_details( + INP int nodes_per_chan, INP int global_route_switch); + +/* UDSD Modifications by WMF End */ + +static int **alloc_and_load_actual_fc(INP int L_num_types, INP t_type_ptr types, + INP int nodes_per_chan, INP boolean is_Fc_out, + INP enum e_directionality directionality, OUTP boolean * Fc_clipped, INP boolean ignore_Fc_0); + +/******************* Subroutine definitions *******************************/ + +void build_rr_graph(INP t_graph_type graph_type, INP int L_num_types, + INP t_type_ptr types, INP int L_nx, INP int L_ny, + INP struct s_grid_tile **L_grid, INP int chan_width, + INP struct s_chan_width_dist *chan_capacity_inf, + INP enum e_switch_block_type sb_type, INP int Fs, INP int num_seg_types, + INP int num_switches, INP t_segment_inf * segment_inf, + INP int global_route_switch, INP int delayless_switch, + INP t_timing_inf timing_inf, INP int wire_to_ipin_switch, + INP enum e_base_cost_type base_cost_type, INP t_direct_inf *directs, + INP int num_directs, INP boolean ignore_Fc_0, OUTP int *Warnings, + /*Xifan TANG: Switch Segment Pattern Support*/ + INP int num_swseg_pattern, INP t_swseg_pattern_inf* swseg_patterns, + INP boolean opin_to_cb_fast_edges, INP boolean opin_logic_eq_edges) { + /* Temp structures used to build graph */ + int nodes_per_chan, i, j; + t_seg_details *seg_details = NULL; + int **Fc_in = NULL; /* [0..num_types-1][0..num_pins-1] */ + int **Fc_out = NULL; /* [0..num_types-1][0..num_pins-1] */ + + int *****opin_to_track_map = NULL; /* [0..num_types-1][0..num_pins-1][0..height][0..3][0..Fc-1] */ + int *****ipin_to_track_map = NULL; /* [0..num_types-1][0..num_pins-1][0..height][0..3][0..Fc-1] */ + t_ivec ****track_to_ipin_lookup = NULL; /* [0..num_types-1][0..nodes_per_chan-1][0..height][0..3] */ + t_ivec ***switch_block_conn = NULL; + short *****unidir_sb_pattern = NULL; + boolean *L_rr_edge_done = NULL; + boolean is_global_graph; + boolean Fc_clipped; + boolean use_full_seg_groups; + boolean *perturb_ipins = NULL; + enum e_directionality directionality; + int **Fc_xofs = NULL; /* [0..ny-1][0..nx-1] */ + int **Fc_yofs = NULL; /* [0..nx-1][0..ny-1] */ + t_clb_to_clb_directs *clb_to_clb_directs; + + rr_node_indices = NULL; + rr_node = NULL; + num_rr_nodes = 0; + + /* Reset warning flag */ + *Warnings = RR_GRAPH_NO_WARN; + + /* Decode the graph_type */ + is_global_graph = FALSE; + if (GRAPH_GLOBAL == graph_type) { + is_global_graph = TRUE; + } + use_full_seg_groups = FALSE; + if (GRAPH_UNIDIR_TILEABLE == graph_type) { + use_full_seg_groups = TRUE; + } + directionality = UNI_DIRECTIONAL; + if (GRAPH_BIDIR == graph_type) { + directionality = BI_DIRECTIONAL; + } + if (is_global_graph) { + directionality = BI_DIRECTIONAL; + } + + /* Global routing uses a single longwire track */ + nodes_per_chan = (is_global_graph ? 1 : chan_width); + assert(nodes_per_chan > 0); + + clb_to_clb_directs = NULL; + if(num_directs > 0) { + clb_to_clb_directs = alloc_and_load_clb_to_clb_directs(directs, num_directs); + } + + /* START SEG_DETAILS */ + if (is_global_graph) { + /* Sets up a single unit length segment type for global routing. */ + seg_details = alloc_and_load_global_route_seg_details(nodes_per_chan, + global_route_switch); + } else { + /* Setup segments including distrubuting tracks and staggering. + * If use_full_seg_groups is specified, nodes_per_chan may be + * changed. Warning should be singled to caller if this happens. */ + seg_details = alloc_and_load_seg_details(&nodes_per_chan, + /* std::max(L_nx, L_ny), */ /* Original VPR */ + std::max(L_nx, L_ny) + ( is_stack ? 1 : 0 ), /* mrFPGA: Xifan TANG */ + num_seg_types, segment_inf, + use_full_seg_groups, is_global_graph, directionality); + if ((is_global_graph ? 1 : chan_width) != nodes_per_chan) { + *Warnings |= RR_GRAPH_WARN_CHAN_WIDTH_CHANGED; + } + if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_SEG_DETAILS)) { + dump_seg_details(seg_details, nodes_per_chan, + getEchoFileName(E_ECHO_SEG_DETAILS)); + } else + ; + } + /* END SEG_DETAILS */ + + /* START FC */ + /* Determine the actual value of Fc */ + if (is_global_graph) { + Fc_in = (int **) my_malloc(sizeof(int) * L_num_types); + Fc_out = (int **) my_malloc(sizeof(int) * L_num_types); + for (i = 0; i < L_num_types; ++i) { + for (j = 0; j < types[i].num_pins; ++j) { + Fc_in[i][j] = 1; + Fc_out[i][j] = 1; + } + } + } else { + Fc_clipped = FALSE; + Fc_in = alloc_and_load_actual_fc(L_num_types, types, nodes_per_chan, + FALSE, directionality, &Fc_clipped, ignore_Fc_0); + if (Fc_clipped) { + *Warnings |= RR_GRAPH_WARN_FC_CLIPPED; + } + Fc_clipped = FALSE; + Fc_out = alloc_and_load_actual_fc(L_num_types, types, nodes_per_chan, + TRUE, directionality, &Fc_clipped, ignore_Fc_0); + if (Fc_clipped) { + *Warnings |= RR_GRAPH_WARN_FC_CLIPPED; + } + +#ifdef VERBOSE + for (i = 1; i < L_num_types; ++i) { /* Skip "" */ + for (j = 0; j < type_descriptors[i].num_pins; ++j) { + if (type_descriptors[i].is_Fc_full_flex[j]) { + vpr_printf(TIO_MESSAGE_INFO, "Fc Actual Values: type = %s, Fc_out = full, Fc_in = %d.\n", + type_descriptors[i].name, Fc_in[i][j]); + } + else { + vpr_printf(TIO_MESSAGE_INFO, "Fc Actual Values: type = %s, Fc_out = %d, Fc_in = %d.\n", + type_descriptors[i].name, Fc_out[i][j], Fc_in[i][j]); + } + } + } +#endif /* VERBOSE */ + } + + perturb_ipins = alloc_and_load_perturb_ipins(nodes_per_chan, L_num_types, + Fc_in, Fc_out, directionality); + /* END FC */ + + /* Alloc node lookups, count nodes, alloc rr nodes */ + num_rr_nodes = 0; + rr_node_indices = alloc_and_load_rr_node_indices(nodes_per_chan, L_nx, L_ny, + &num_rr_nodes, seg_details); + rr_node = (t_rr_node *) my_malloc(sizeof(t_rr_node) * num_rr_nodes); + memset(rr_node, 0, sizeof(t_rr_node) * num_rr_nodes); + L_rr_edge_done = (boolean *) my_malloc(sizeof(boolean) * num_rr_nodes); + memset(L_rr_edge_done, 0, sizeof(boolean) * num_rr_nodes); + + /* These are data structures used by the the unidir opin mapping. */ + if (UNI_DIRECTIONAL == directionality) { + Fc_xofs = (int **) alloc_matrix(0, L_ny, 0, L_nx, sizeof(int)); + Fc_yofs = (int **) alloc_matrix(0, L_nx, 0, L_ny, sizeof(int)); + for (i = 0; i <= L_nx; ++i) { + for (j = 0; j <= L_ny; ++j) { + Fc_xofs[j][i] = 0; + Fc_yofs[i][j] = 0; + } + } + } + + /* START SB LOOKUP */ + /* Alloc and load the switch block lookup */ + if (is_global_graph) { + assert(nodes_per_chan == 1); + switch_block_conn = alloc_and_load_switch_block_conn(1, SUBSET, 3); + } else if (BI_DIRECTIONAL == directionality) { + switch_block_conn = alloc_and_load_switch_block_conn(nodes_per_chan, + sb_type, Fs); + } else { + assert(UNI_DIRECTIONAL == directionality); + + unidir_sb_pattern = alloc_sblock_pattern_lookup(L_nx, L_ny, + nodes_per_chan); + for (i = 0; i <= L_nx; i++) { + for (j = 0; j <= L_ny; j++) { + load_sblock_pattern_lookup(i, j, nodes_per_chan, seg_details, + Fs, sb_type, unidir_sb_pattern); + } + } + } + /* END SB LOOKUP */ + + /* START IPINP MAP */ + /* Create ipin map lookups */ + ipin_to_track_map = (int *****) my_malloc(sizeof(int ****) * L_num_types); + track_to_ipin_lookup = (struct s_ivec ****) my_malloc( + sizeof(struct s_ivec ***) * L_num_types); + for (i = 0; i < L_num_types; ++i) { + ipin_to_track_map[i] = alloc_and_load_pin_to_track_map(RECEIVER, + nodes_per_chan, Fc_in[i], &types[i], perturb_ipins[i], + directionality); + track_to_ipin_lookup[i] = alloc_and_load_track_to_pin_lookup( + ipin_to_track_map[i], Fc_in[i], types[i].height, + types[i].num_pins, nodes_per_chan); + } + /* END IPINP MAP */ + + /* START OPINP MAP */ + /* Create opin map lookups */ + if (BI_DIRECTIONAL == directionality) { + opin_to_track_map = (int *****) my_malloc( + sizeof(int ****) * L_num_types); + for (i = 0; i < L_num_types; ++i) { + opin_to_track_map[i] = alloc_and_load_pin_to_track_map(DRIVER, + nodes_per_chan, Fc_out[i], &types[i], FALSE, directionality); + } + } + /* END OPINP MAP */ + + /* UDSD Modifications by WMF begin */ + /* I'm adding 2 new fields to t_rr_node, and I want them initialized to 0. */ + for (i = 0; i < num_rr_nodes; i++) { + rr_node[i].num_wire_drivers = 0; + rr_node[i].num_opin_drivers = 0; + } + + alloc_and_load_rr_graph(num_rr_nodes, rr_node, num_seg_types, seg_details, + L_rr_edge_done, track_to_ipin_lookup, opin_to_track_map, + switch_block_conn, L_grid, L_nx, L_ny, Fs, unidir_sb_pattern, + Fc_out, Fc_xofs, Fc_yofs, rr_node_indices, nodes_per_chan, sb_type, + delayless_switch, directionality, wire_to_ipin_switch, &Fc_clipped, directs, num_directs, clb_to_clb_directs); + +#ifdef MUX_SIZE_DIST_DISPLAY + if (UNI_DIRECTIONAL == directionality) + { + view_mux_size_distribution(rr_node_indices, nodes_per_chan, + seg_details, seg_details); + } +#endif + + /* Update rr_nodes capacities if global routing */ + if (graph_type == GRAPH_GLOBAL) { + for (i = 0; i < num_rr_nodes; i++) { + if (rr_node[i].type == CHANX || rr_node[i].type == CHANY) { + rr_node[i].capacity = chan_width; + } + } + } + + /* Xifan TANG: Add Fast Interconnection from LB OPINs to adjacent LB IPINs*/ + if (TRUE == opin_to_cb_fast_edges) { // Do only detailed rr_graph is needed + vpr_printf(TIO_MESSAGE_INFO,"Adding %d fast edges from logic block OPIN to logic block IPIN ...\n", + add_rr_graph_fast_edge_opin_to_cb(rr_node_indices)); + } + /*END*/ + + /*Xifan TANG: Switch Segment Pattern Support*/ + if (NULL != swseg_patterns) { // Do only the pointer is not NULL + vpr_printf(TIO_MESSAGE_INFO,"Applying Switch Segment Pattern...\n"); + if (UNI_DIRECTIONAL == directionality) { + add_rr_graph_switch_segment_pattern(directionality,nodes_per_chan, num_swseg_pattern, swseg_patterns, rr_node_indices, seg_details, seg_details); + } else { + vpr_printf(TIO_MESSAGE_ERROR,"Switch Segment Pattern is only applicable to uni-directional routing architecture!\n"); + exit(1); + } + } + /*END*/ + + /* Xifan TANG: Check logic equivalence of LB OPINs and IPINs. Then modify the associated rr_graph */ + /* use net_rr_terminal array to find SOURCE rr_node for each net*/ + if (TRUE == opin_logic_eq_edges) { // Do only detailed rr_graph is needed + vpr_printf(TIO_MESSAGE_INFO,"Adding %d logic equivalent edges for logic block OPIN ...\n", + // alloc_and_add_grids_fully_capacity_sb_rr_edges(rr_node_indices, num_directs, clb_to_clb_directs)); + alloc_and_add_grids_fully_capacity_rr_edges(rr_node_indices, num_directs, clb_to_clb_directs)); + } + /*END*/ + + rr_graph_externals(timing_inf, segment_inf, num_seg_types, nodes_per_chan, + wire_to_ipin_switch, base_cost_type); + + if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_RR_GRAPH)) { + dump_rr_graph(getEchoFileName(E_ECHO_RR_GRAPH)); + } else + ; + + check_rr_graph(graph_type, types, L_nx, L_ny, nodes_per_chan, Fs, + num_seg_types, num_switches, segment_inf, global_route_switch, + delayless_switch, wire_to_ipin_switch, seg_details, Fc_in, Fc_out, + opin_to_track_map, ipin_to_track_map, track_to_ipin_lookup, + switch_block_conn, perturb_ipins); + + /* Free all temp structs */ + if (seg_details) { + free_seg_details(seg_details, nodes_per_chan); + seg_details = NULL; + } + if (Fc_in) { + free_matrix(Fc_in,0, L_num_types, 0, sizeof(int)); + Fc_in = NULL; + } + if (Fc_out) { + free_matrix(Fc_out,0, L_num_types, 0, sizeof(int)); + Fc_out = NULL; + } + if (perturb_ipins) { + free(perturb_ipins); + perturb_ipins = NULL; + } + if (switch_block_conn) { + free_switch_block_conn(switch_block_conn, nodes_per_chan); + switch_block_conn = NULL; + } + if (L_rr_edge_done) { + free(L_rr_edge_done); + L_rr_edge_done = NULL; + } + if (Fc_xofs) { + free_matrix(Fc_xofs, 0, L_ny, 0, sizeof(int)); + Fc_xofs = NULL; + } + if (Fc_yofs) { + free_matrix(Fc_yofs, 0, L_nx, 0, sizeof(int)); + Fc_yofs = NULL; + } + if (unidir_sb_pattern) { + free_sblock_pattern_lookup(unidir_sb_pattern); + unidir_sb_pattern = NULL; + } + if (opin_to_track_map) { + for (i = 0; i < L_num_types; ++i) { + free_matrix4(opin_to_track_map[i], 0, types[i].num_pins - 1, 0, + types[i].height - 1, 0, 3, 0, sizeof(int)); + } + free(opin_to_track_map); + } + + free_type_pin_to_track_map(ipin_to_track_map, types); + free_type_track_to_ipin_map(track_to_ipin_lookup, types, nodes_per_chan); + if(clb_to_clb_directs != NULL) { + free(clb_to_clb_directs); + } +} + +static void rr_graph_externals(t_timing_inf timing_inf, + t_segment_inf * segment_inf, int num_seg_types, int nodes_per_chan, + int wire_to_ipin_switch, enum e_base_cost_type base_cost_type) { + add_rr_graph_C_from_switches(timing_inf.C_ipin_cblock); + alloc_and_load_rr_indexed_data(segment_inf, num_seg_types, rr_node_indices, + nodes_per_chan, wire_to_ipin_switch, base_cost_type); + + alloc_net_rr_terminals(); + load_net_rr_terminals(rr_node_indices); + alloc_and_load_rr_clb_source(rr_node_indices); +} + +static boolean * +alloc_and_load_perturb_ipins(INP int nodes_per_chan, INP int L_num_types, + INP int **Fc_in, INP int **Fc_out, INP enum e_directionality directionality) { + int i; + float Fc_ratio; + boolean *result = NULL; + + result = (boolean *) my_malloc(L_num_types * sizeof(boolean)); + + if (BI_DIRECTIONAL == directionality) { + result[0] = FALSE; + for (i = 1; i < L_num_types; ++i) { + result[i] = FALSE; + + if (Fc_in[i][0] > Fc_out[i][0]) { + Fc_ratio = (float) Fc_in[i][0] / (float) Fc_out[i][0]; + } else { + Fc_ratio = (float) Fc_out[i][0] / (float) Fc_in[i][0]; + } + + if ((Fc_in[i][0] <= nodes_per_chan - 2) + && (fabs(Fc_ratio - nint(Fc_ratio)) + < (0.5 / (float) nodes_per_chan))) { + result[i] = TRUE; + } + } + } else { + /* Unidirectional routing uses mux balancing patterns and + * thus shouldn't need perturbation. */ + assert(UNI_DIRECTIONAL == directionality); + for (i = 0; i < L_num_types; ++i) { + result[i] = FALSE; + } + } + + return result; +} + +static t_seg_details * +alloc_and_load_global_route_seg_details(INP int nodes_per_chan, + INP int global_route_switch) { + t_seg_details *result = NULL; + + assert(nodes_per_chan == 1); + result = (t_seg_details *) my_malloc(sizeof(t_seg_details)); + + result->index = 0; + result->length = 1; + result->wire_switch = global_route_switch; + result->opin_switch = global_route_switch; + result->longline = FALSE; + result->direction = BI_DIRECTION; + result->Cmetal = 0.0; + result->Rmetal = 0.0; + result->start = 1; + result->drivers = MULTI_BUFFERED; + result->cb = (boolean *) my_malloc(sizeof(boolean) * 1); + result->cb[0] = TRUE; + result->sb = (boolean *) my_malloc(sizeof(boolean) * 2); + result->sb[0] = TRUE; + result->sb[1] = TRUE; + result->group_size = 1; + result->group_start = 0; + + return result; +} + +/* Calculates the actual Fc values for the given nodes_per_chan value */ +static int ** +alloc_and_load_actual_fc(INP int L_num_types, INP t_type_ptr types, + INP int nodes_per_chan, INP boolean is_Fc_out, + INP enum e_directionality directionality, OUTP boolean * Fc_clipped, INP boolean ignore_Fc_0) { + + int i, j; + int **Result = NULL; + int fac, num_sets; + + *Fc_clipped = FALSE; + + /* Unidir tracks formed in pairs, otherwise no effect. */ + fac = 1; + if (UNI_DIRECTIONAL == directionality) { + fac = 2; + } + + assert((nodes_per_chan % fac) == 0); + num_sets = nodes_per_chan / fac; + + int max_pins = types[0].num_pins; + for (i = 1; i < L_num_types; ++i) { + if (types[i].num_pins > max_pins) { + max_pins = types[i].num_pins; + } + } + + Result = (int **) alloc_matrix(0, L_num_types, 0, max_pins, sizeof(int)); + + for (i = 1; i < L_num_types; ++i) { + float *Fc = (float *) my_malloc(sizeof(float) * types[i].num_pins); /* [0..num_pins-1] */ + for (j = 0; j < types[i].num_pins; ++j) { + Fc[j] = types[i].Fc[j]; + + if(Fc[j] == 0 && ignore_Fc_0 == FALSE) { + /* Special case indicating that this pin does not connect to general-purpose routing */ + Result[i][j] = 0; + } else { + /* General case indicating that this pin connects to general-purpose routing */ + if (types[i].is_Fc_frac[j]) { + Result[i][j] = fac * nint(num_sets * Fc[j]); + } else { + Result[i][j] = (int)Fc[j]; + } + + if (is_Fc_out && types[i].is_Fc_full_flex[j]) { + Result[i][j] = nodes_per_chan; + } + + Result[i][j] = std::max(Result[i][j], fac); + if (Result[i][j] > nodes_per_chan) { + *Fc_clipped = TRUE; + Result[i][j] = nodes_per_chan; + } + } + assert(Result[i][j] % fac == 0); + } + free(Fc); + } + + return Result; +} + +/* frees the track to ipin mapping for each physical grid type */ +static void free_type_track_to_ipin_map(struct s_ivec**** track_to_pin_map, + t_type_ptr types, int nodes_per_chan) { + int i, itrack, ioff, iside; + for (i = 0; i < num_types; i++) { + if (track_to_pin_map[i] != NULL) { + for (itrack = 0; itrack < nodes_per_chan; itrack++) { + for (ioff = 0; ioff < types[i].height; ioff++) { + for (iside = 0; iside < 4; iside++) { + if (track_to_pin_map[i][itrack][ioff][iside].list + != NULL) { + free(track_to_pin_map[i][itrack][ioff][iside].list); + } + } + } + } + free_matrix3(track_to_pin_map[i], 0, nodes_per_chan - 1, 0, + types[i].height - 1, 0, sizeof(struct s_ivec)); + } + } + free(track_to_pin_map); +} + +/* frees the ipin to track mapping for each physical grid type */ +static void free_type_pin_to_track_map(int***** ipin_to_track_map, + t_type_ptr types) { + int i; + for (i = 0; i < num_types; i++) { + free_matrix4(ipin_to_track_map[i], 0, types[i].num_pins - 1, 0, + types[i].height - 1, 0, 3, 0, sizeof(int)); + } + free(ipin_to_track_map); +} + +/* Does the actual work of allocating the rr_graph and filling all the * + * appropriate values. Everything up to this was just a prelude! */ +static void alloc_and_load_rr_graph(INP int num_nodes, + INP t_rr_node * L_rr_node, INP int num_seg_types, + INP t_seg_details * seg_details, INP boolean * L_rr_edge_done, + INP struct s_ivec ****track_to_ipin_lookup, + INP int *****opin_to_track_map, INP struct s_ivec ***switch_block_conn, + INP struct s_grid_tile **L_grid, INP int L_nx, INP int L_ny, INP int Fs, + INP short *****sblock_pattern, INP int **Fc_out, INP int **Fc_xofs, + INP int **Fc_yofs, INP t_ivec *** L_rr_node_indices, + INP int nodes_per_chan, INP enum e_switch_block_type sb_type, + INP int delayless_switch, INP enum e_directionality directionality, + INP int wire_to_ipin_switch, OUTP boolean * Fc_clipped, + INP t_direct_inf *directs, INP int num_directs, + INP t_clb_to_clb_directs *clb_to_clb_directs) { + + int i, j; + boolean clipped; + int *opin_mux_size = NULL; + + /* If Fc gets clipped, this will be flagged to true */ + *Fc_clipped = FALSE; + + /* Connection SINKS and SOURCES to their pins. */ + for (i = 0; i <= (L_nx + 1); i++) { + for (j = 0; j <= (L_ny + 1); j++) { + build_rr_sinks_sources(i, j, L_rr_node, L_rr_node_indices, + delayless_switch, L_grid); + } + } + + /* Build opins */ + for (i = 0; i <= (L_nx + 1); ++i) { + for (j = 0; j <= (L_ny + 1); ++j) { + if (BI_DIRECTIONAL == directionality) { + build_bidir_rr_opins(i, j, L_rr_node, L_rr_node_indices, + opin_to_track_map, Fc_out, L_rr_edge_done, seg_details, + L_grid, delayless_switch, + directs, num_directs, clb_to_clb_directs); + } else { + assert(UNI_DIRECTIONAL == directionality); + build_unidir_rr_opins(i, j, L_grid, Fc_out, nodes_per_chan, + seg_details, Fc_xofs, Fc_yofs, L_rr_node, + L_rr_edge_done, &clipped, L_rr_node_indices, delayless_switch, + directs, num_directs, clb_to_clb_directs); + if (clipped) { + *Fc_clipped = TRUE; + } + } + } + } + + /* We make a copy of the current fanin values for the nodes to + * know the number of OPINs driving each mux presently */ + opin_mux_size = (int *) my_malloc(sizeof(int) * num_nodes); + for (i = 0; i < num_nodes; ++i) { + opin_mux_size[i] = L_rr_node[i].fan_in; + } + + /* Build channels */ + assert(Fs % 3 == 0); + for (i = 0; i <= L_nx; i++) { + for (j = 0; j <= L_ny; j++) { + if (i > 0) { + build_rr_xchan(i, j, track_to_ipin_lookup, switch_block_conn, + CHANX_COST_INDEX_START, nodes_per_chan, opin_mux_size, + sblock_pattern, Fs / 3, seg_details, L_rr_node_indices, + L_rr_edge_done, L_rr_node, wire_to_ipin_switch, + directionality); + } + if (j > 0) { + build_rr_ychan(i, j, track_to_ipin_lookup, switch_block_conn, + CHANX_COST_INDEX_START + num_seg_types, nodes_per_chan, + opin_mux_size, sblock_pattern, Fs / 3, seg_details, + L_rr_node_indices, L_rr_edge_done, L_rr_node, + wire_to_ipin_switch, directionality); + } + } + } + free(opin_mux_size); +} + +static void build_bidir_rr_opins(INP int i, INP int j, + INOUTP t_rr_node * L_rr_node, INP t_ivec *** L_rr_node_indices, + INP int *****opin_to_track_map, INP int **Fc_out, + INP boolean * L_rr_edge_done, INP t_seg_details * seg_details, + INP struct s_grid_tile **L_grid, INP int delayless_switch, + INP t_direct_inf *directs, INP int num_directs, INP t_clb_to_clb_directs *clb_to_clb_directs) { + + int ipin, inode, num_edges, *Fc, ofs; + t_type_ptr type; + struct s_linked_edge *edge_list, *next; + + /* OPINP edges need to be done at once so let the offset 0 + * block do the work. */ + if (L_grid[i][j].offset > 0) { + return; + } + + type = L_grid[i][j].type; + Fc = Fc_out[type->index]; + + for (ipin = 0; ipin < type->num_pins; ++ipin) { + /* We only are working with opins so skip non-drivers */ + if (type->class_inf[type->pin_class[ipin]].type != DRIVER) { + continue; + } + + num_edges = 0; + edge_list = NULL; + if(Fc[ipin] != 0) { + for (ofs = 0; ofs < type->height; ++ofs) { + num_edges += get_bidir_opin_connections(i, j + ofs, ipin, + &edge_list, opin_to_track_map, Fc[ipin], L_rr_edge_done, + L_rr_node_indices, seg_details); + } + } + + /* Add in direct connections */ + num_edges += get_opin_direct_connecions(i, j, ipin, &edge_list, L_rr_node_indices, delayless_switch, directs, num_directs, clb_to_clb_directs); + + inode = get_rr_node_index(i, j, OPIN, ipin, L_rr_node_indices); + alloc_and_load_edges_and_switches(L_rr_node, inode, num_edges, + L_rr_edge_done, edge_list); + while (edge_list != NULL) { + next = edge_list->next; + free(edge_list); + edge_list = next; + } + } +} + +void free_rr_graph(void) { + int i; + + /* Frees all the routing graph data structures, if they have been * + * allocated. I use rr_mem_chunk_list_head as a flag to indicate * + * whether or not the graph has been allocated -- if it is not NULL, * + * a routing graph exists and can be freed. Hence, you can call this * + * routine even if you're not sure of whether a rr_graph exists or not. */ + + if (rr_mem_ch.chunk_ptr_head == NULL) /* Nothing to free. */ + return; + + free_chunk_memory(&rr_mem_ch); /* Frees ALL "chunked" data */ + + /* Before adding any more free calls here, be sure the data is NOT chunk * + * allocated, as ALL the chunk allocated data is already free! */ + + if(net_rr_terminals != NULL) { + free(net_rr_terminals); + } + for (i = 0; i < num_rr_nodes; i++) { + if (rr_node[i].edges != NULL) { + free(rr_node[i].edges); + } + if (rr_node[i].switches != NULL) { + free(rr_node[i].switches); + } + } + + assert(rr_node_indices); + free_rr_node_indices(rr_node_indices); + free(rr_node); + free(rr_indexed_data); + for (i = 0; i < num_blocks; i++) { + free(rr_blk_source[i]); + } + free(rr_blk_source); + rr_blk_source = NULL; + net_rr_terminals = NULL; + rr_node = NULL; + rr_node_indices = NULL; + rr_indexed_data = NULL; + num_rr_nodes = 0; +} + +static void alloc_net_rr_terminals(void) { + int inet; + + net_rr_terminals = (int **) my_malloc(num_nets * sizeof(int *)); + + for (inet = 0; inet < num_nets; inet++) { + net_rr_terminals[inet] = (int *) my_chunk_malloc( + (clb_net[inet].num_sinks + 1) * sizeof(int), + &rr_mem_ch); + } +} + +void load_net_rr_terminals(t_ivec *** L_rr_node_indices) { + + /* Allocates and loads the net_rr_terminals data structure. For each net * + * it stores the rr_node index of the SOURCE of the net and all the SINKs * + * of the net. [0..num_nets-1][0..num_pins-1]. Entry [inet][pnum] stores * + * the rr index corresponding to the SOURCE (opin) or SINK (ipin) of pnum. */ + + int inet, ipin, inode, iblk, i, j, node_block_pin, iclass; + t_type_ptr type; + + for (inet = 0; inet < num_nets; inet++) { + for (ipin = 0; ipin <= clb_net[inet].num_sinks; ipin++) { + iblk = clb_net[inet].node_block[ipin]; + i = block[iblk].x; + j = block[iblk].y; + type = block[iblk].type; + + /* In the routing graph, each (x, y) location has unique pins on it + * so when there is capacity, blocks are packed and their pin numbers + * are offset to get their actual rr_node */ + node_block_pin = clb_net[inet].node_block_pin[ipin]; + + iclass = type->pin_class[node_block_pin]; + + inode = get_rr_node_index(i, j, (ipin == 0 ? SOURCE : SINK), /* First pin is driver */ + iclass, L_rr_node_indices); + net_rr_terminals[inet][ipin] = inode; + } + } +} + +static void alloc_and_load_rr_clb_source(t_ivec *** L_rr_node_indices) { + + /* Saves the rr_node corresponding to each SOURCE and SINK in each CLB * + * in the FPGA. Currently only the SOURCE rr_node values are used, and * + * they are used only to reserve pins for locally used OPINs in the router. * + * [0..num_blocks-1][0..num_class-1]. The values for blocks that are pads * + * are NOT valid. */ + + int iblk, i, j, iclass, inode; + int class_low, class_high; + t_rr_type rr_type; + t_type_ptr type; + + rr_blk_source = (int **) my_malloc(num_blocks * sizeof(int *)); + + for (iblk = 0; iblk < num_blocks; iblk++) { + type = block[iblk].type; + get_class_range_for_block(iblk, &class_low, &class_high); + rr_blk_source[iblk] = (int *) my_malloc(type->num_class * sizeof(int)); + for (iclass = 0; iclass < type->num_class; iclass++) { + if (iclass >= class_low && iclass <= class_high) { + i = block[iblk].x; + j = block[iblk].y; + + if (type->class_inf[iclass].type == DRIVER) + rr_type = SOURCE; + else + rr_type = SINK; + + inode = get_rr_node_index(i, j, rr_type, iclass, + L_rr_node_indices); + rr_blk_source[iblk][iclass] = inode; + } else { + rr_blk_source[iblk][iclass] = OPEN; + } + } + } +} + +static void build_rr_sinks_sources(INP int i, INP int j, + INP t_rr_node * L_rr_node, INP t_ivec *** L_rr_node_indices, + INP int delayless_switch, INP struct s_grid_tile **L_grid) { + + /* Loads IPIN, SINK, SOURCE, and OPIN. + * Loads IPINP to SINK edges, and SOURCE to OPINP edges */ + + int ipin, iclass, inode, pin_num, to_node, num_edges; + int num_class, num_pins; + t_type_ptr type; + struct s_class *class_inf; + int *pin_class; + const t_pb_graph_node *pb_graph_node; + int iport, ipb_pin, iporttype, z; + + /* Since we share nodes within a large block, only + * start tile can initialize sinks, sources, and pins */ + if (L_grid[i][j].offset > 0) + return; + + type = L_grid[i][j].type; + num_class = type->num_class; + class_inf = type->class_inf; + num_pins = type->num_pins; + pin_class = type->pin_class; + z = 0; + + /* SINKS and SOURCE to OPINP edges */ + for (iclass = 0; iclass < num_class; iclass++) { + if (class_inf[iclass].type == DRIVER) { /* SOURCE */ + inode = get_rr_node_index(i, j, SOURCE, iclass, L_rr_node_indices); + + num_edges = class_inf[iclass].num_pins; + L_rr_node[inode].num_edges = num_edges; + L_rr_node[inode].edges = (int *) my_malloc(num_edges * sizeof(int)); + L_rr_node[inode].switches = (short *) my_malloc( + num_edges * sizeof(short)); + + for (ipin = 0; ipin < class_inf[iclass].num_pins; ipin++) { + pin_num = class_inf[iclass].pinlist[ipin]; + to_node = get_rr_node_index(i, j, OPIN, pin_num, + L_rr_node_indices); + L_rr_node[inode].edges[ipin] = to_node; + L_rr_node[inode].switches[ipin] = delayless_switch; + + ++L_rr_node[to_node].fan_in; + } + + L_rr_node[inode].cost_index = SOURCE_COST_INDEX; + L_rr_node[inode].type = SOURCE; + } else { /* SINK */ + assert(class_inf[iclass].type == RECEIVER); + inode = get_rr_node_index(i, j, SINK, iclass, L_rr_node_indices); + + /* NOTE: To allow route throughs through clbs, change the lines below to * + * make an edge from the input SINK to the output SOURCE. Do for just the * + * special case of INPUTS = class 0 and OUTPUTS = class 1 and see what it * + * leads to. If route throughs are allowed, you may want to increase the * + * base cost of OPINs and/or SOURCES so they aren't used excessively. */ + + /* Initialize to unconnected to fix values */ + L_rr_node[inode].num_edges = 0; + L_rr_node[inode].edges = NULL; + L_rr_node[inode].switches = NULL; + + L_rr_node[inode].cost_index = SINK_COST_INDEX; + L_rr_node[inode].type = SINK; + } + + /* Things common to both SOURCEs and SINKs. */ + L_rr_node[inode].capacity = class_inf[iclass].num_pins; + L_rr_node[inode].occ = 0; + L_rr_node[inode].xlow = i; + L_rr_node[inode].xhigh = i; + L_rr_node[inode].ylow = j; + L_rr_node[inode].yhigh = j + type->height - 1; + L_rr_node[inode].R = 0; + L_rr_node[inode].C = 0; + L_rr_node[inode].ptc_num = iclass; + L_rr_node[inode].direction = (enum e_direction)OPEN; + L_rr_node[inode].drivers = (enum e_drivers)OPEN; + } + + iporttype = iport = ipb_pin = 0; + + pb_graph_node = type->pb_graph_head; + if(pb_graph_node != NULL && pb_graph_node->num_input_ports == 0) { + iporttype = 1; + } + /* Connect IPINS to SINKS and dummy for OPINS */ + for (ipin = 0; ipin < num_pins; ipin++) { + iclass = pin_class[ipin]; + z = ipin / (type->pb_type->num_clock_pins + type->pb_type->num_output_pins + type->pb_type->num_input_pins); + + if (class_inf[iclass].type == RECEIVER) { + inode = get_rr_node_index(i, j, IPIN, ipin, L_rr_node_indices); + to_node = get_rr_node_index(i, j, SINK, iclass, L_rr_node_indices); + + L_rr_node[inode].num_edges = 1; + L_rr_node[inode].edges = (int *) my_malloc(sizeof(int)); + L_rr_node[inode].switches = (short *) my_malloc(sizeof(short)); + + L_rr_node[inode].edges[0] = to_node; + L_rr_node[inode].switches[0] = delayless_switch; + + ++L_rr_node[to_node].fan_in; + + L_rr_node[inode].cost_index = IPIN_COST_INDEX; + L_rr_node[inode].type = IPIN; + + /* Add in information so that I can identify which cluster pin this rr_node connects to later */ + L_rr_node[inode].z = z; + if(iporttype == 0) { + L_rr_node[inode].pb_graph_pin = &pb_graph_node->input_pins[iport][ipb_pin]; + ipb_pin++; + if(ipb_pin >= pb_graph_node->num_input_pins[iport]) { + iport++; + ipb_pin = 0; + if(iport >= pb_graph_node->num_input_ports) { + iporttype++; + iport = 0; + if(pb_graph_node->num_clock_ports == 0) { + iporttype = 0; + } + } + } + } else { + assert(iporttype == 1); + L_rr_node[inode].pb_graph_pin = &pb_graph_node->clock_pins[iport][ipb_pin]; + ipb_pin++; /* Xifan TANG: Original VPR does not have this incremental!!! */ + if(ipb_pin >= pb_graph_node->num_clock_pins[iport]) { + iport++; + ipb_pin = 0; + if(iport >= pb_graph_node->num_clock_ports) { + iporttype = 0; + iport = 0; + if(pb_graph_node->num_input_ports == 0) { + iporttype = 1; + } + } + } + } + } else { + assert(class_inf[iclass].type == DRIVER); + + inode = get_rr_node_index(i, j, OPIN, ipin, L_rr_node_indices); + + /* Add in information so that I can identify which cluster pin this rr_node connects to later */ + L_rr_node[inode].z = z; + + L_rr_node[inode].num_edges = 0; + L_rr_node[inode].edges = NULL; + + L_rr_node[inode].switches = NULL; + + L_rr_node[inode].cost_index = OPIN_COST_INDEX; + L_rr_node[inode].type = OPIN; + + L_rr_node[inode].pb_graph_pin = &pb_graph_node->output_pins[iport][ipb_pin]; + ipb_pin++; /* Xifan TANG: Original VPR does not have this incremental!!! */ + if(ipb_pin >= pb_graph_node->num_output_pins[iport]) { + iport++; + ipb_pin = 0; + if(iport >= pb_graph_node->num_output_ports) { + iport = 0; + if(pb_graph_node->num_input_ports == 0) { + iporttype = 1; + } else { + iporttype = 0; + } + } + } + } + + /* Common to both DRIVERs and RECEIVERs */ + L_rr_node[inode].capacity = 1; + L_rr_node[inode].occ = 0; + L_rr_node[inode].xlow = i; + L_rr_node[inode].xhigh = i; + L_rr_node[inode].ylow = j; + L_rr_node[inode].yhigh = j + type->height - 1; + L_rr_node[inode].C = 0; + L_rr_node[inode].R = 0; + L_rr_node[inode].ptc_num = ipin; + L_rr_node[inode].direction = (enum e_direction)OPEN; + L_rr_node[inode].drivers = (enum e_drivers)OPEN; + } +} + +static void build_rr_xchan(INP int i, INP int j, + INP struct s_ivec ****track_to_ipin_lookup, + INP struct s_ivec ***switch_block_conn, INP int cost_index_offset, + INP int nodes_per_chan, INP int *opin_mux_size, + INP short *****sblock_pattern, INP int Fs_per_side, + INP t_seg_details * seg_details, INP t_ivec *** L_rr_node_indices, + INOUTP boolean * L_rr_edge_done, INOUTP t_rr_node * L_rr_node, + INP int wire_to_ipin_switch, INP enum e_directionality directionality) { + + /* Loads up all the routing resource nodes in the x-directed channel * + * segments starting at (i,j). */ + + int itrack, istart, iend, num_edges, inode, length; + struct s_linked_edge *edge_list, *next; + /* mrFPGA: Xifan TANG */ + int jstart, jend; + /* END */ + + for (itrack = 0; itrack < nodes_per_chan; itrack++) { + /* First count number of edges and put the edges in a linked list. */ + num_edges = 0; + edge_list = NULL; + + /* mrFPGA : Xifan TANG*/ + if ( is_stack ) { + jstart = get_seg_start (seg_details, itrack, i, j); + if ( jstart != j ) + continue; + jend = get_seg_end (seg_details, itrack, jstart, i, ny); + + istart = i; + iend = i; + + num_edges += get_track_to_ipins(jstart, i, itrack, &edge_list, L_rr_node_indices, + track_to_ipin_lookup, seg_details, CHANX, nx, wire_to_ipin_switch, + directionality); + + num_edges += get_track_to_tracks(i, jstart, itrack, CHANX, i-1, CHANY, ny, + nodes_per_chan, opin_mux_size, Fs_per_side, sblock_pattern, + &edge_list, seg_details, directionality, L_rr_node_indices, + L_rr_edge_done, switch_block_conn); + + num_edges += get_track_to_tracks(i, jstart, itrack, CHANX, i, CHANY, ny, + nodes_per_chan, opin_mux_size, Fs_per_side, sblock_pattern, + &edge_list, seg_details, directionality, L_rr_node_indices, + L_rr_edge_done, switch_block_conn); + + if( jstart > 0 ) { + num_edges += get_track_to_tracks(i, jstart, itrack, CHANX, jstart - 1, CHANX, ny, + nodes_per_chan, opin_mux_size, Fs_per_side,sblock_pattern, &edge_list, + seg_details, directionality, L_rr_node_indices, L_rr_edge_done, switch_block_conn); + } + if( jend < ny ) { + num_edges += get_track_to_tracks(i, jstart, itrack, CHANX, jend + 1, CHANX, ny, + nodes_per_chan, opin_mux_size, Fs_per_side, sblock_pattern, &edge_list, + seg_details, directionality, L_rr_node_indices, L_rr_edge_done, switch_block_conn); + } + } else { /* end */ + /* Xifan TANG: I remove the accurate part for Original VPR*/ + /* Original VPR part*/ + istart = get_seg_start(seg_details, itrack, j, i); + iend = get_seg_end(seg_details, itrack, istart, j, nx); + if (i > istart) + continue; /* Not the start of this segment. */ + jstart = j; + jend = j; + /* end */ + + /* First count number of edges and put the edges in a linked list. */ + num_edges = 0; + edge_list = NULL; + + num_edges += get_track_to_ipins(istart, j, itrack, &edge_list, + L_rr_node_indices, track_to_ipin_lookup, seg_details, CHANX, nx, + wire_to_ipin_switch, directionality); + + if (j > 0) { + num_edges += get_track_to_tracks(j, istart, itrack, CHANX, j, CHANY, + nx, nodes_per_chan, opin_mux_size, Fs_per_side, + sblock_pattern, &edge_list, seg_details, directionality, + L_rr_node_indices, L_rr_edge_done, switch_block_conn); + } + + if (j < ny) { + num_edges += get_track_to_tracks(j, istart, itrack, CHANX, j + 1, + CHANY, nx, nodes_per_chan, opin_mux_size, Fs_per_side, + sblock_pattern, &edge_list, seg_details, directionality, + L_rr_node_indices, L_rr_edge_done, switch_block_conn); + } + + if (istart > 1) { + num_edges += get_track_to_tracks(j, istart, itrack, CHANX, + istart - 1, CHANX, nx, nodes_per_chan, opin_mux_size, + Fs_per_side, sblock_pattern, &edge_list, seg_details, + directionality, L_rr_node_indices, L_rr_edge_done, + switch_block_conn); + } + + if (iend < nx) { + num_edges += get_track_to_tracks(j, istart, itrack, CHANX, iend + 1, + CHANX, nx, nodes_per_chan, opin_mux_size, Fs_per_side, + sblock_pattern, &edge_list, seg_details, directionality, + L_rr_node_indices, L_rr_edge_done, switch_block_conn); + } + } + /* END */ + + inode = get_rr_node_index(i, j, CHANX, itrack, L_rr_node_indices); + alloc_and_load_edges_and_switches(L_rr_node, inode, num_edges, + L_rr_edge_done, edge_list); + + while (edge_list != NULL) { + next = edge_list->next; + free(edge_list); + edge_list = next; + } + + /* Edge arrays have now been built up. Do everything else. */ + L_rr_node[inode].cost_index = cost_index_offset + + seg_details[itrack].index; + L_rr_node[inode].occ = 0; + + L_rr_node[inode].capacity = 1; /* GLOBAL routing handled elsewhere */ + + if (is_stack) { + /* mrFPGA: Xifan TANG */ + L_rr_node[inode].xlow = istart; + L_rr_node[inode].xhigh = iend; + L_rr_node[inode].ylow = jstart; + L_rr_node[inode].yhigh = jend; + } else { + /* Original VPR */ + L_rr_node[inode].xlow = istart; + L_rr_node[inode].xhigh = iend; + L_rr_node[inode].ylow = j; + L_rr_node[inode].yhigh = j; + } + + /* mrFPGA: Xifan TANG */ + length = is_stack ? (jend - jstart) : (iend - istart + 1); + //length = (iend - istart + 1); + /* END */ + + L_rr_node[inode].R = length * seg_details[itrack].Rmetal; + L_rr_node[inode].C = length * seg_details[itrack].Cmetal; + + L_rr_node[inode].ptc_num = itrack; + L_rr_node[inode].type = CHANX; + L_rr_node[inode].direction = seg_details[itrack].direction; + L_rr_node[inode].drivers = seg_details[itrack].drivers; + /* Xifan TANG:(For SPICE Modeling) Fill the segment inf */ + //LL_rr_node[inode].seg_index = seg_details[itrack].index; + } +} + +static void build_rr_ychan(INP int i, INP int j, + INP struct s_ivec ****track_to_ipin_lookup, + INP struct s_ivec ***switch_block_conn, INP int cost_index_offset, + INP int nodes_per_chan, INP int *opin_mux_size, + INP short *****sblock_pattern, INP int Fs_per_side, + INP t_seg_details * seg_details, INP t_ivec *** L_rr_node_indices, + INP boolean * L_rr_edge_done, INOUTP t_rr_node * L_rr_node, + INP int wire_to_ipin_switch, INP enum e_directionality directionality) { + + /* Loads up all the routing resource nodes in the y-directed channel * + * segments starting at (i,j). */ + + int itrack, istart, iend, num_edges, inode, length; + struct s_linked_edge *edge_list, *next; + + /* mrFPGA: Xifan TANG*/ + int jstart, jend; + /* END */ + + for (itrack = 0; itrack < nodes_per_chan; itrack++) { + /* First count number of edges and put the edges in a linked list. */ + num_edges = 0; + edge_list = NULL; + + /* mrFPGA */ + if ( is_stack ) { + istart = get_seg_start (seg_details, itrack, j, i); + if ( istart != i ) + continue; + iend = get_seg_end (seg_details, itrack, istart, j, nx); + /* mrFPGA: Xifan TANG */ + jstart = j; + jend = j; + /* end */ + + num_edges += get_track_to_ipins(istart, j, itrack, &edge_list, L_rr_node_indices, + track_to_ipin_lookup, seg_details, CHANY, nx, wire_to_ipin_switch, + directionality); + + num_edges += get_track_to_tracks(j, istart, itrack, CHANY, j-1, CHANX, nx, + nodes_per_chan, opin_mux_size, Fs_per_side, sblock_pattern, + &edge_list, seg_details, directionality, L_rr_node_indices, + L_rr_edge_done, switch_block_conn); + + num_edges += get_track_to_tracks(j, istart, itrack, CHANY, j, CHANX, nx, + nodes_per_chan, opin_mux_size, Fs_per_side, sblock_pattern, + &edge_list, seg_details, directionality, L_rr_node_indices, + L_rr_edge_done, switch_block_conn); + + if (istart > 0) { + num_edges += get_track_to_tracks(j, istart, itrack, CHANY, istart - 1, CHANY, nx, + nodes_per_chan, opin_mux_size, Fs_per_side, sblock_pattern, &edge_list, + seg_details, directionality, L_rr_node_indices, L_rr_edge_done, + switch_block_conn); + } + + if (iend < nx) { + num_edges += get_track_to_tracks(j, istart, itrack, CHANY, iend + 1, + CHANY, nx, nodes_per_chan, opin_mux_size, Fs_per_side, + sblock_pattern, &edge_list, seg_details, directionality, + L_rr_node_indices, L_rr_edge_done, switch_block_conn); + + } + } else { /* end */ + istart = get_seg_start(seg_details, itrack, i, j); + iend = get_seg_end(seg_details, itrack, istart, i, ny); + + if (j > istart) + continue; /* Not the start of this segment. */ + /* mrFPGA: Xifan TANG*/ + jstart = i; + jend = i; + /* END */ + + /* Original VPR */ + /* First count number of edges and put the edges in a linked list. */ + num_edges = 0; + edge_list = NULL; + + num_edges += get_track_to_ipins(istart, i, itrack, &edge_list, + L_rr_node_indices, track_to_ipin_lookup, seg_details, CHANY, ny, + wire_to_ipin_switch, directionality); + + if (i > 0) { + num_edges += get_track_to_tracks(i, istart, itrack, CHANY, i, CHANX, + ny, nodes_per_chan, opin_mux_size, Fs_per_side, + sblock_pattern, &edge_list, seg_details, directionality, + L_rr_node_indices, L_rr_edge_done, switch_block_conn); + } + + if (i < nx) { + num_edges += get_track_to_tracks(i, istart, itrack, CHANY, i + 1, + CHANX, ny, nodes_per_chan, opin_mux_size, Fs_per_side, + sblock_pattern, &edge_list, seg_details, directionality, + L_rr_node_indices, L_rr_edge_done, switch_block_conn); + } + + if (istart > 1) { + num_edges += get_track_to_tracks(i, istart, itrack, CHANY, + istart - 1, CHANY, ny, nodes_per_chan, opin_mux_size, + Fs_per_side, sblock_pattern, &edge_list, seg_details, + directionality, L_rr_node_indices, L_rr_edge_done, + switch_block_conn); + } + + if (iend < ny) { + num_edges += get_track_to_tracks(i, istart, itrack, CHANY, iend + 1, + CHANY, ny, nodes_per_chan, opin_mux_size, Fs_per_side, + sblock_pattern, &edge_list, seg_details, directionality, + L_rr_node_indices, L_rr_edge_done, switch_block_conn); + } + } + /* END */ + + inode = get_rr_node_index(i, j, CHANY, itrack, L_rr_node_indices); + alloc_and_load_edges_and_switches(L_rr_node, inode, num_edges, + L_rr_edge_done, edge_list); + + while (edge_list != NULL) { + next = edge_list->next; + free(edge_list); + edge_list = next; + } + + /* Edge arrays have now been built up. Do everything else. */ + L_rr_node[inode].cost_index = cost_index_offset + + seg_details[itrack].index; + L_rr_node[inode].occ = 0; + + L_rr_node[inode].capacity = 1; /* GLOBAL routing handled elsewhere */ + + if (is_stack) { + /* mrFPGA: Xifan TANG */ + L_rr_node[inode].xlow = istart; + L_rr_node[inode].xhigh = iend; + L_rr_node[inode].ylow = jstart; + L_rr_node[inode].yhigh = jend; + } else { + /* Original VPR */ + L_rr_node[inode].xlow = i; + L_rr_node[inode].xhigh = i; + L_rr_node[inode].ylow = istart; + L_rr_node[inode].yhigh = iend; + } + + /* mrFPGA : Xifan TANG*/ + length = is_stack ? (iend - istart) : (iend - istart + 1); + //length = (iend - istart + 1); + /* END */ + + L_rr_node[inode].R = length * seg_details[itrack].Rmetal; + L_rr_node[inode].C = length * seg_details[itrack].Cmetal; + + L_rr_node[inode].ptc_num = itrack; + L_rr_node[inode].type = CHANY; + L_rr_node[inode].direction = seg_details[itrack].direction; + L_rr_node[inode].drivers = seg_details[itrack].drivers; + /* Xifan TANG:(For SPICE Modeling) Fill the segment inf */ + //LL_rr_node[inode].seg_index = seg_details[itrack].index; + } +} + +void watch_edges(int inode, t_linked_edge * edge_list_head) { + t_linked_edge *list_ptr; + int i, to_node; + + list_ptr = edge_list_head; + i = 0; + + vpr_printf(TIO_MESSAGE_TRACE, "!!! Watching Node %d !!!!\n", inode); + print_rr_node(stdout, rr_node, inode); + vpr_printf(TIO_MESSAGE_TRACE, "Currently connects to:\n"); + while (list_ptr != NULL) { + to_node = list_ptr->edge; + print_rr_node(stdout, rr_node, to_node); + list_ptr = list_ptr->next; + i++; + } +} + +void alloc_and_load_edges_and_switches(INP t_rr_node * L_rr_node, INP int inode, + INP int num_edges, INOUTP boolean * L_rr_edge_done, + INP t_linked_edge * edge_list_head) { + + /* Sets up all the edge related information for rr_node inode (num_edges, * + * the edges array and the switches array). The edge_list_head points to * + * a list of the num_edges edges and switches to put in the arrays. This * + * linked list is freed by this routine. This routine also resets the * + * rr_edge_done array for the next rr_node (i.e. set it so that no edges * + * are marked as having been seen before). */ + + t_linked_edge *list_ptr; + int i; + + /* Check we aren't overwriting edges */ + assert(L_rr_node[inode].num_edges < 1); + assert(NULL == L_rr_node[inode].edges); + assert(NULL == L_rr_node[inode].switches); + + L_rr_node[inode].num_edges = num_edges; + L_rr_node[inode].edges = (int *) my_malloc(num_edges * sizeof(int)); + L_rr_node[inode].switches = (short *) my_malloc(num_edges * sizeof(short)); + + i = 0; + list_ptr = edge_list_head; + while (list_ptr && (i < num_edges)) { + L_rr_node[inode].edges[i] = list_ptr->edge; + L_rr_node[inode].switches[i] = list_ptr->iswitch; + + ++L_rr_node[list_ptr->edge].fan_in; + + /* Unmark the edge since we are done considering fanout from node. */ + L_rr_edge_done[list_ptr->edge] = FALSE; + + list_ptr = list_ptr->next; + ++i; + } + assert(list_ptr == NULL); + assert(i == num_edges); +} + +static int **** +alloc_and_load_pin_to_track_map(INP enum e_pin_type pin_type, + INP int nodes_per_chan, INP int *Fc, INP t_type_ptr Type, + INP boolean perturb_switch_pattern, + INP enum e_directionality directionality) { + + int **num_dir; /* [0..height][0..3] Number of *physical* pins on each side. */ + int ***dir_list; /* [0..height][0..3][0..num_pins-1] list of pins of correct type * + * * on each side. Max possible space alloced for simplicity */ + + int i, j, k, iside, ipin, iclass, num_phys_pins, pindex, ioff; + int *pin_num_ordering, *side_ordering, *offset_ordering; + int **num_done_per_dir; /* [0..height][0..3] */ + int ****tracks_connected_to_pin; /* [0..num_pins-1][0..height][0..3][0..Fc-1] */ + + /* NB: This wastes some space. Could set tracks_..._pin[ipin][ioff][iside] = + * NULL if there is no pin on that side, or that pin is of the wrong type. + * Probably not enough memory to worry about, esp. as it's temporary. + * If pin ipin on side iside does not exist or is of the wrong type, + * tracks_connected_to_pin[ipin][iside][0] = OPEN. */ + + if (Type->num_pins < 1) { + return NULL; + } + + /* Currently, only two possible Fc values exist: 0 or default. + * Finding the max. value of Fc in block will result in the + * default value, which works for now. In the future, when + * the Fc values of all pins can vary, the max value will continue + * to work for matrix (de)allocation purposes. However, all looping + * will have to be modified to account for pin-based Fc values. */ + int max_Fc = 0; + for (i = 0; i < Type->num_pins; ++i) { + iclass = Type->pin_class[i]; + if (Fc[i] > max_Fc && Type->class_inf[iclass].type == pin_type) { + max_Fc = Fc[i]; + } + } + + tracks_connected_to_pin = (int ****) alloc_matrix4(0, Type->num_pins - 1, 0, + Type->height - 1, 0, 3, 0, max_Fc, sizeof(int)); + + for (ipin = 0; ipin < Type->num_pins; ipin++) { + for (ioff = 0; ioff < Type->height; ioff++) { + for (iside = 0; iside < 4; iside++) { + for (i = 0; i < max_Fc; ++i) { + tracks_connected_to_pin[ipin][ioff][iside][i] = OPEN; /* Unconnected. */ + } + } + } + } + + num_dir = (int **) alloc_matrix(0, Type->height - 1, 0, 3, sizeof(int)); + dir_list = (int ***) alloc_matrix3(0, Type->height - 1, 0, 3, 0, + Type->num_pins - 1, sizeof(int)); + + /* Defensive coding. Try to crash hard if I use an unset entry. */ + for (i = 0; i < Type->height; i++) + for (j = 0; j < 4; j++) + for (k = 0; k < Type->num_pins; k++) + dir_list[i][j][k] = (-1); + + for (i = 0; i < Type->height; i++) + for (j = 0; j < 4; j++) + num_dir[i][j] = 0; + + for (ipin = 0; ipin < Type->num_pins; ipin++) { + iclass = Type->pin_class[ipin]; + if (Type->class_inf[iclass].type != pin_type) /* Doing either ipins OR opins */ + continue; + + /* Pins connecting only to global resources get no switches -> keeps the * + * area model accurate. */ + + if (Type->is_global_pin[ipin]) + continue; + for (ioff = 0; ioff < Type->height; ioff++) { + for (iside = 0; iside < 4; iside++) { + if (Type->pinloc[ioff][iside][ipin] == 1) { + dir_list[ioff][iside][num_dir[ioff][iside]] = ipin; + num_dir[ioff][iside]++; + } + } + } + } + + num_phys_pins = 0; + for (ioff = 0; ioff < Type->height; ioff++) { + for (iside = 0; iside < 4; iside++) + num_phys_pins += num_dir[ioff][iside]; /* Num. physical pins per type */ + } + num_done_per_dir = (int **) alloc_matrix(0, Type->height - 1, 0, 3, + sizeof(int)); + for (ioff = 0; ioff < Type->height; ioff++) { + for (iside = 0; iside < 4; iside++) { + num_done_per_dir[ioff][iside] = 0; + } + } + pin_num_ordering = (int *) my_malloc(num_phys_pins * sizeof(int)); + side_ordering = (int *) my_malloc(num_phys_pins * sizeof(int)); + offset_ordering = (int *) my_malloc(num_phys_pins * sizeof(int)); + + /* Connection block I use distributes pins evenly across the tracks * + * of ALL sides of the clb at once. Ensures that each pin connects * + * to spaced out tracks in its connection block, and that the other * + * pins (potentially in other C blocks) connect to the remaining tracks * + * first. Doesn't matter for large Fc, but should make a fairly * + * good low Fc block that leverages the fact that usually lots of pins * + * are logically equivalent. */ + + iside = LEFT; + ioff = Type->height - 1; + ipin = 0; + pindex = -1; + + while (ipin < num_phys_pins) { + if (iside == TOP) { + iside = RIGHT; + } else if (iside == RIGHT) { + if (ioff <= 0) { + iside = BOTTOM; + } else { + ioff--; + } + } else if (iside == BOTTOM) { + iside = LEFT; + } else { + assert(iside == LEFT); + if (ioff >= Type->height - 1) { + pindex++; + iside = TOP; + } else { + ioff++; + } + } + + assert(pindex < num_phys_pins); + /* Number of physical pins bounds number of logical pins */ + + if (num_done_per_dir[ioff][iside] >= num_dir[ioff][iside]) + continue; + pin_num_ordering[ipin] = dir_list[ioff][iside][pindex]; + side_ordering[ipin] = iside; + offset_ordering[ipin] = ioff; + assert(Type->pinloc[ioff][iside][dir_list[ioff][iside][pindex]]); + num_done_per_dir[ioff][iside]++; + ipin++; + } + + if (perturb_switch_pattern) { + load_perturbed_switch_pattern(Type, tracks_connected_to_pin, + num_phys_pins, pin_num_ordering, side_ordering, offset_ordering, + nodes_per_chan, max_Fc, directionality); + } else { + load_uniform_switch_pattern(Type, tracks_connected_to_pin, + num_phys_pins, pin_num_ordering, side_ordering, offset_ordering, + nodes_per_chan, max_Fc, directionality); + } + check_all_tracks_reach_pins(Type, tracks_connected_to_pin, nodes_per_chan, + max_Fc, pin_type); + + /* Free all temporary storage. */ + free_matrix(num_dir, 0, Type->height - 1, 0, sizeof(int)); + free_matrix3(dir_list, 0, Type->height - 1, 0, 3, 0, sizeof(int)); + free_matrix(num_done_per_dir, 0, Type->height - 1, 0, sizeof(int)); + free(pin_num_ordering); + free(side_ordering); + free(offset_ordering); + + return tracks_connected_to_pin; +} + +static void load_uniform_switch_pattern(INP t_type_ptr type, + INOUTP int ****tracks_connected_to_pin, INP int num_phys_pins, + INP int *pin_num_ordering, INP int *side_ordering, + INP int *offset_ordering, INP int nodes_per_chan, INP int Fc, + enum e_directionality directionality) { + + /* Loads the tracks_connected_to_pin array with an even distribution of * + * switches across the tracks for each pin. For example, each pin connects * + * to every 4.3rd track in a channel, with exactly which tracks a pin * + * connects to staggered from pin to pin. */ + + int i, j, ipin, iside, ioff, itrack, k; + float f_track, fc_step; + int group_size; + float step_size; + + /* Uni-directional drive is implemented to ensure no directional bias and this means + * two important comments noted below */ + /* 1. Spacing should be (W/2)/(Fc/2), and step_size should be spacing/(num_phys_pins), + * and lay down 2 switches on an adjacent pair of tracks at a time to ensure + * no directional bias. Basically, treat W (even) as W/2 pairs of tracks, and + * assign switches to a pair at a time. Can do this because W is guaranteed to + * be even-numbered; however same approach cannot be applied to Fc_out pattern + * when L > 1 and W <> 2L multiple. + * + * 2. This generic pattern should be considered the tileable physical layout, + * meaning all track # here are physical #'s, + * so later must use vpr_to_phy conversion to find actual logical #'s to connect. + * This also means I will not use get_output_block_companion_track to ensure + * no bias, since that describes a logical # -> that would confuse people. */ + + step_size = (float) nodes_per_chan / (float) (Fc * num_phys_pins); + + if (directionality == BI_DIRECTIONAL) { + group_size = 1; + } else { + assert(directionality == UNI_DIRECTIONAL); + group_size = 2; + } + + assert((nodes_per_chan % group_size == 0) && (Fc % group_size == 0)); + + fc_step = (float) nodes_per_chan / (float) Fc; + + for (i = 0; i < num_phys_pins; i++) { + ipin = pin_num_ordering[i]; + iside = side_ordering[i]; + ioff = offset_ordering[i]; + + /* Bi-directional treats each track separately, uni-directional works with pairs of tracks */ + for (j = 0; j < (Fc / group_size); j++) { + f_track = (i * step_size) + (j * fc_step); + itrack = ((int) f_track) * group_size; + + /* Catch possible floating point round error */ + itrack = std::min(itrack, nodes_per_chan - group_size); + + /* Assign the group of tracks for the Fc pattern */ + for (k = 0; k < group_size; ++k) { + tracks_connected_to_pin[ipin][ioff][iside][group_size * j + k] = + itrack + k; + } + } + } +} + +static void load_perturbed_switch_pattern(INP t_type_ptr type, + INOUTP int ****tracks_connected_to_pin, INP int num_phys_pins, + INP int *pin_num_ordering, INP int *side_ordering, + INP int *offset_ordering, INP int nodes_per_chan, INP int Fc, + enum e_directionality directionality) { + + /* Loads the tracks_connected_to_pin array with an unevenly distributed * + * set of switches across the channel. This is done for inputs when * + * Fc_input = Fc_output to avoid creating "pin domains" -- certain output * + * pins being able to talk only to certain input pins because their switch * + * patterns exactly line up. Distribute Fc/2 + 1 switches over half the * + * channel and Fc/2 - 1 switches over the other half to make the switch * + * pattern different from the uniform one of the outputs. Also, have half * + * the pins put the "dense" part of their connections in the first half of * + * the channel and the other half put the "dense" part in the second half, * + * to make sure each track can connect to about the same number of ipins. */ + + int i, j, ipin, iside, itrack, ihalf, iconn, ioff; + int Fc_dense, Fc_sparse, Fc_half[2]; + float f_track, spacing_dense, spacing_sparse, spacing[2]; + float step_size; + + assert(directionality == BI_DIRECTIONAL); + + step_size = (float) nodes_per_chan / (float) (Fc * num_phys_pins); + + Fc_dense = (Fc / 2) + 1; + Fc_sparse = Fc - Fc_dense; /* Works for even or odd Fc */ + + spacing_dense = (float) nodes_per_chan / (float) (2 * Fc_dense); + spacing_sparse = (float) nodes_per_chan / (float) (2 * Fc_sparse); + + for (i = 0; i < num_phys_pins; i++) { + ipin = pin_num_ordering[i]; + iside = side_ordering[i]; + ioff = offset_ordering[i]; + + /* Flip every pin to balance switch density */ + spacing[i % 2] = spacing_dense; + Fc_half[i % 2] = Fc_dense; + spacing[(i + 1) % 2] = spacing_sparse; + Fc_half[(i + 1) % 2] = Fc_sparse; + + f_track = i * step_size; /* Start point. Staggered from pin to pin */ + iconn = 0; + + for (ihalf = 0; ihalf < 2; ihalf++) { /* For both dense and sparse halves. */ + for (j = 0; j < Fc_half[ihalf]; ++j) { + itrack = (int) f_track; + + /* Can occasionally get wraparound due to floating point rounding. + This is okay because the starting position > 0 when this occurs + so connection is valid and fine */ + itrack = itrack % nodes_per_chan; + tracks_connected_to_pin[ipin][ioff][iside][iconn] = itrack; + + f_track += spacing[ihalf]; + iconn++; + } + } + } /* End for all physical pins. */ +} + +static void check_all_tracks_reach_pins(t_type_ptr type, + int ****tracks_connected_to_pin, int nodes_per_chan, int Fc, + enum e_pin_type ipin_or_opin) { + + /* Checks that all tracks can be reached by some pin. */ + + int iconn, iside, itrack, ipin, ioff; + int *num_conns_to_track; /* [0..nodes_per_chan-1] */ + + assert(nodes_per_chan > 0); + + num_conns_to_track = (int *) my_calloc(nodes_per_chan, sizeof(int)); + + for (ipin = 0; ipin < type->num_pins; ipin++) { + for (ioff = 0; ioff < type->height; ioff++) { + for (iside = 0; iside < 4; iside++) { + if (tracks_connected_to_pin[ipin][ioff][iside][0] != OPEN) { /* Pin exists */ + for (iconn = 0; iconn < Fc; iconn++) { + itrack = + tracks_connected_to_pin[ipin][ioff][iside][iconn]; + num_conns_to_track[itrack]++; + } + } + } + } + } + + for (itrack = 0; itrack < nodes_per_chan; itrack++) { + if (num_conns_to_track[itrack] <= 0) { + vpr_printf(TIO_MESSAGE_ERROR, "check_all_tracks_reach_pins: Track %d does not connect to any CLB %ss.\n", + itrack, (ipin_or_opin == DRIVER ? "OPIN" : "IPIN")); + } + } + + free(num_conns_to_track); +} + +/* Allocates and loads the track to ipin lookup for each physical grid type. This + * is the same information as the ipin_to_track map but accessed in a different way. */ + +static struct s_ivec *** +alloc_and_load_track_to_pin_lookup(INP int ****pin_to_track_map, INP int *Fc, + INP int height, INP int num_pins, INP int nodes_per_chan) { + int ipin, iside, itrack, iconn, ioff, pin_counter; + struct s_ivec ***track_to_pin_lookup; + + /* [0..nodes_per_chan-1][0..height][0..3]. For each track number it stores a vector + * for each of the four sides. x-directed channels will use the TOP and + * BOTTOM vectors to figure out what clb input pins they connect to above + * and below them, respectively, while y-directed channels use the LEFT + * and RIGHT vectors. Each vector contains an nelem field saying how many + * ipins it connects to. The list[0..nelem-1] array then gives the pin + * numbers. */ + + /* Note that a clb pin that connects to a channel on its RIGHT means that * + * that channel connects to a clb pin on its LEFT. The convention used * + * here is always in the perspective of the CLB */ + + if (num_pins < 1) { + return NULL; + } + + /* Alloc and zero the the lookup table */ + track_to_pin_lookup = (struct s_ivec ***) alloc_matrix3(0, + nodes_per_chan - 1, 0, height - 1, 0, 3, sizeof(struct s_ivec)); + for (itrack = 0; itrack < nodes_per_chan; itrack++) { + for (ioff = 0; ioff < height; ioff++) { + for (iside = 0; iside < 4; iside++) { + track_to_pin_lookup[itrack][ioff][iside].nelem = 0; + track_to_pin_lookup[itrack][ioff][iside].list = NULL; + } + } + } + + /* Counting pass. */ + for (ipin = 0; ipin < num_pins; ipin++) { + for (ioff = 0; ioff < height; ioff++) { + for (iside = 0; iside < 4; iside++) { + if (pin_to_track_map[ipin][ioff][iside][0] == OPEN) + continue; + + for (iconn = 0; iconn < Fc[ipin]; iconn++) { + itrack = pin_to_track_map[ipin][ioff][iside][iconn]; + track_to_pin_lookup[itrack][ioff][iside].nelem++; + } + } + } + } + + /* Allocate space. */ + for (itrack = 0; itrack < nodes_per_chan; itrack++) { + for (ioff = 0; ioff < height; ioff++) { + for (iside = 0; iside < 4; iside++) { + track_to_pin_lookup[itrack][ioff][iside].list = NULL; /* Defensive code */ + if (track_to_pin_lookup[itrack][ioff][iside].nelem != 0) { + track_to_pin_lookup[itrack][ioff][iside].list = + (int *) my_malloc( + track_to_pin_lookup[itrack][ioff][iside].nelem + * sizeof(int)); + track_to_pin_lookup[itrack][ioff][iside].nelem = 0; + } + } + } + } + + /* Loading pass. */ + for (ipin = 0; ipin < num_pins; ipin++) { + for (ioff = 0; ioff < height; ioff++) { + for (iside = 0; iside < 4; iside++) { + if (pin_to_track_map[ipin][ioff][iside][0] == OPEN) + continue; + + for (iconn = 0; iconn < Fc[ipin]; iconn++) { + itrack = pin_to_track_map[ipin][ioff][iside][iconn]; + pin_counter = + track_to_pin_lookup[itrack][ioff][iside].nelem; + track_to_pin_lookup[itrack][ioff][iside].list[pin_counter] = + ipin; + track_to_pin_lookup[itrack][ioff][iside].nelem++; + } + } + } + } + + return track_to_pin_lookup; +} + +/* A utility routine to dump the contents of the routing resource graph * + * (everything -- connectivity, occupancy, cost, etc.) into a file. Used * + * only for debugging. */ +void dump_rr_graph(INP const char *file_name) { + + int inode; + FILE *fp; + + fp = my_fopen(file_name, "w", 0); + + for (inode = 0; inode < num_rr_nodes; inode++) { + print_rr_node(fp, rr_node, inode); + fprintf(fp, "\n"); + } + +#if 0 + fprintf(fp, "\n\n%d rr_indexed_data entries.\n\n", num_rr_indexed_data); + + for (index = 0; index < num_rr_indexed_data; index++) + { + print_rr_indexed_data(fp, index); + fprintf(fp, "\n"); + } +#endif + + fclose(fp); +} + +/* Prints all the data about node inode to file fp. */ +void print_rr_node(FILE * fp, t_rr_node * L_rr_node, int inode) { + + static const char *name_type[] = { "SOURCE", "SINK", "IPIN", "OPIN", + "CHANX", "CHANY", "INTRA_CLUSTER_EDGE" }; + static const char *direction_name[] = { "OPEN", "INC_DIRECTION", + "DEC_DIRECTION", "BI_DIRECTION" }; + static const char *drivers_name[] = { "OPEN", "MULTI_BUFFER", "SINGLE" }; + + t_rr_type rr_type; + int iconn; + + rr_type = L_rr_node[inode].type; + + /* Make sure we don't overrun const arrays */ + assert((int)rr_type < (int)(sizeof(name_type) / sizeof(char *))); + assert( + (L_rr_node[inode].direction + 1) < (int)(sizeof(direction_name) / sizeof(char *))); + assert( + (L_rr_node[inode].drivers + 1) < (int)(sizeof(drivers_name) / sizeof(char *))); + + fprintf(fp, "Node: %d %s ", inode, name_type[rr_type]); + if ((L_rr_node[inode].xlow == L_rr_node[inode].xhigh) + && (L_rr_node[inode].ylow == L_rr_node[inode].yhigh)) { + fprintf(fp, "(%d, %d) ", L_rr_node[inode].xlow, L_rr_node[inode].ylow); + } else { + fprintf(fp, "(%d, %d) to (%d, %d) ", L_rr_node[inode].xlow, + L_rr_node[inode].ylow, L_rr_node[inode].xhigh, + L_rr_node[inode].yhigh); + } + fprintf(fp, "Ptc_num: %d ", L_rr_node[inode].ptc_num); + fprintf(fp, "Direction: %s ", + direction_name[L_rr_node[inode].direction + 1]); + fprintf(fp, "Drivers: %s ", drivers_name[L_rr_node[inode].drivers + 1]); + fprintf(fp, "\n"); + + fprintf(fp, "%d edge(s):", L_rr_node[inode].num_edges); + for (iconn = 0; iconn < L_rr_node[inode].num_edges; iconn++) + fprintf(fp, " %d", L_rr_node[inode].edges[iconn]); + fprintf(fp, "\n"); + + fprintf(fp, "Switch types:"); + for (iconn = 0; iconn < L_rr_node[inode].num_edges; iconn++) + fprintf(fp, " %d", L_rr_node[inode].switches[iconn]); + fprintf(fp, "\n"); + + fprintf(fp, "Occ: %d Capacity: %d\n", L_rr_node[inode].occ, + L_rr_node[inode].capacity); + if (rr_type != INTRA_CLUSTER_EDGE) { + fprintf(fp, "R: %g C: %g\n", L_rr_node[inode].R, L_rr_node[inode].C); + } + fprintf(fp, "Cost_index: %d\n", L_rr_node[inode].cost_index); +} + +/* Prints all the rr_indexed_data of index to file fp. */ +void print_rr_indexed_data(FILE * fp, int index) { + + fprintf(fp, "Index: %d\n", index); + + fprintf(fp, "ortho_cost_index: %d ", + rr_indexed_data[index].ortho_cost_index); + fprintf(fp, "base_cost: %g ", rr_indexed_data[index].saved_base_cost); + fprintf(fp, "saved_base_cost: %g\n", + rr_indexed_data[index].saved_base_cost); + + fprintf(fp, "Seg_index: %d ", rr_indexed_data[index].seg_index); + fprintf(fp, "inv_length: %g\n", rr_indexed_data[index].inv_length); + + fprintf(fp, "T_linear: %g ", rr_indexed_data[index].T_linear); + fprintf(fp, "T_quadratic: %g ", rr_indexed_data[index].T_quadratic); + fprintf(fp, "C_load: %g\n", rr_indexed_data[index].C_load); +} + +static void build_unidir_rr_opins(INP int i, INP int j, + INP struct s_grid_tile **L_grid, INP int **Fc_out, + INP int nodes_per_chan, INP t_seg_details * seg_details, + INOUTP int **Fc_xofs, INOUTP int **Fc_yofs, + INOUTP t_rr_node * L_rr_node, INOUTP boolean * L_rr_edge_done, + OUTP boolean * Fc_clipped, INP t_ivec *** L_rr_node_indices, INP int delayless_switch, + INP t_direct_inf *directs, INP int num_directs, INP t_clb_to_clb_directs *clb_to_clb_directs) { + /* This routine returns a list of the opins rr_nodes on each + * side/offset of the block. You must free the result with + * free_matrix. */ + + t_type_ptr type; + int ipin, iclass, ofs, chan, seg, max_len, inode, max_Fc = -1; + enum e_side side; + t_rr_type chan_type; + t_linked_edge *edge_list = NULL, *next; + boolean clipped, vert, pos_dir; + int num_edges; + int **Fc_ofs; + + *Fc_clipped = FALSE; + + /* Only the base block of a set should use this function */ + if (L_grid[i][j].offset > 0) { + return; + } + + type = L_grid[i][j].type; + + /* Currently, only two possible Fc values exist: 0 or default. + * Finding the max. value of Fc in block will result in the + * default value, which works for now. In the future, when + * the Fc values of all pins can vary, the max value will continue + * to work for matrix allocation purposes. However, all looping + * will have to be modified to account for pin-based Fc values. */ + if (type->index > 0) { + max_Fc = 0; + for (ipin = 0; ipin < type->num_pins; ++ipin) { + iclass = type->pin_class[ipin]; + if (Fc_out[type->index][ipin] > max_Fc && type->class_inf[iclass].type == DRIVER) { + max_Fc = Fc_out[type->index][ipin]; + } + } + } + + /* Go through each pin and find its fanout. */ + for (ipin = 0; ipin < type->num_pins; ++ipin) { + /* Skip global pins and ipins */ + iclass = type->pin_class[ipin]; + if (type->class_inf[iclass].type != DRIVER) { + continue; + } + if (type->is_global_pin[ipin]) { + continue; + } + + num_edges = 0; + edge_list = NULL; + if(Fc_out[type->index][ipin] != 0) { + for (ofs = 0; ofs < type->height; ++ofs) { + for (side = (enum e_side)0; side < 4; side = (enum e_side)(side + 1)) { + /* Can't do anything if pin isn't at this location */ + if (0 == type->pinloc[ofs][side][ipin]) { + continue; + } + + /* Figure out the chan seg at that side. + * side is the side of the logic or io block. */ + vert = (boolean) ((side == TOP) || (side == BOTTOM)); + /* mrFPGA */ + if (is_stack) { + vert = (boolean)(!vert); + } + /* END */ + pos_dir = (boolean) ((side == TOP) || (side == RIGHT)); + /* mrFPGA */ + //chan_type = (vert ? CHANX : CHANY); + chan_type = ((is_stack ? !vert : vert) ? CHANX : CHANY); + /* END */ + chan = (vert ? (j + ofs) : i); + seg = (vert ? i : (j + ofs)); + max_len = (vert ? nx : ny); + Fc_ofs = (vert ? Fc_xofs : Fc_yofs); + if (FALSE == pos_dir) { + /* mrFPGA */ + if (is_stack) { + --seg; + /* END */ + } else { + --chan; + } + } + + /* mrFPGA */ + /* Skip the location if there is no channel. */ + if (chan < (is_stack ? 1:0)) { + continue; + } + if (seg < (is_stack ? 0:1)) { + continue; + } + /* END */ + if (seg > (vert ? nx : ny)) { + continue; + } + if (chan > (vert ? ny : nx)) { + continue; + } + + /* Get the list of opin to mux connections for that chan seg. */ + num_edges += get_unidir_opin_connections(chan, seg, + max_Fc, chan_type, seg_details, &edge_list, + Fc_ofs, L_rr_edge_done, max_len, nodes_per_chan, + L_rr_node_indices, &clipped); + if (clipped) { + *Fc_clipped = TRUE; + } + } + } + } + + /* Add in direct connections */ + num_edges += get_opin_direct_connecions(i, j, ipin, &edge_list, L_rr_node_indices, delayless_switch, directs, num_directs, clb_to_clb_directs); + + /* Add the edges */ + inode = get_rr_node_index(i, j, OPIN, ipin, L_rr_node_indices); + alloc_and_load_edges_and_switches(rr_node, inode, num_edges, + L_rr_edge_done, edge_list); + while (edge_list != NULL) { + next = edge_list->next; + free(edge_list); + edge_list = next; + } + } +} +#if 0 +static void +load_uniform_opin_switch_pattern_paired(INP int *Fc_out, + INP int num_pins, + INP int *pins_in_chan_seg, + INP int num_wire_inc_muxes, + INP int num_wire_dec_muxes, + INP int *wire_inc_muxes, + INP int *wire_dec_muxes, + INOUTP t_rr_node * L_rr_node, + INOUTP boolean * L_rr_edge_done, + INP t_seg_details * seg_details, + OUTP boolean * Fc_clipped) +{ + + /* Directionality is assumed to be uni-directional */ + + /* Make turn-based assignment to avoid overlap when Fc_ouput is low. This is a bipartite + * matching problem. Out of "num_wire_muxes" muxes "Fc_output" of them is assigned + * to each outpin (total "num_pins" of them); assignment is uniform (spacing - spreadout) + * and staggered to avoid overlap when Fc_output is low. */ + + /* The natural order wires muxes are stored in wire_muxes is alternating in directionality + * already (by my implementation), so no need to do anything extra to avoid directional bias */ + + /* TODO: Due to spacing, it's possible to have directional bias: all Fc_out wires connected + * to one opin goes in either INC or DEC -> whereas I want a mix of both. + * SOLUTION: Use quantization of 2 to ensure that if an opin connects to one wire, it + * must also connect to its companion wire, which runs in the opposite direction. This + * means instead of having num_wire_muxes as the matching set, pick out the INC wires + * in num_wires_muxes as the matching set (the DEC wires are their companions) April 17, 2007 + * NEWS: That solution does not work, as treating wires in groups will lead to serious + * abnormal patterns (conns crossing multiple blocks) for W nonquantized to multiples of 2L. + * So, I'm chaning that approach to a new one that avoids directional bias: I will separate + * the INC muxes and DEC muxes into two sets. Each set is uniformly assigned to opins with + * Fc_output/2; this should be identical as before for normal cases and contains all conns + * in the same chan segment for the nonquantized cases. */ + + /* Finally, separated the two approaches: 1. Take all wire muxes and assign them to opins + * one at a time (load_uniform_opin_switch_pattern) 2. Take pairs (by companion) + * of wire muxes and assign them to opins a pair at a time (load_uniform_opin_switch_pattern_paired). + * The first is used for fringe channel segments (ends of channels, where + * there are lots of muxes due to partial wire segments) and the second is used in core */ + + /* float spacing, step_size, f_mux; */ + int ipin, iconn, num_edges, init_mux; + int from_node, to_node, to_track; + int xlow, ylow; + t_linked_edge *edge_list; + int *wire_muxes; + int k, num_wire_muxes, Fc_output_per_side, CurFc; + int count_inc, count_dec; + t_type_ptr type; + + *Fc_clipped = FALSE; + + count_inc = count_dec = 0; + + for (ipin = 0; ipin < num_pins; ipin++) + { + from_node = pins_in_chan_seg[ipin]; + xlow = L_rr_node[from_node].xlow; + ylow = L_rr_node[from_node].ylow; + type = grid[xlow][ylow].type; + edge_list = NULL; + num_edges = 0; + + /* Assigning the INC muxes first, then DEC muxes */ + for (k = 0; k < 2; ++k) + { + if (k == 0) + { + num_wire_muxes = num_wire_inc_muxes; + wire_muxes = wire_inc_muxes; + } + else + { + num_wire_muxes = num_wire_dec_muxes; + wire_muxes = wire_dec_muxes; + } + + /* Half the Fc will be assigned for each direction. */ + assert(Fc_out[type->index] % 2 == 0); + Fc_output_per_side = Fc_out[type->index] / 2; + + /* Clip the demand. Make sure to use a new variable so + * on the second pass it is not clipped. */ + CurFc = Fc_output_per_side; + if (Fc_output_per_side > num_wire_muxes) + { + *Fc_clipped = TRUE; + CurFc = num_wire_muxes; + } + + if (k == 0) + { + init_mux = (count_inc) % num_wire_muxes; + count_inc += CurFc; + } + else + { + init_mux = (count_dec) % num_wire_muxes; + count_dec += CurFc; + } + + for (iconn = 0; iconn < CurFc; iconn++) + { + /* FINALLY, make the outpin to mux connection */ + /* Latest update: I'm not using Uniform Pattern, but a similarly staggered pattern */ + to_node = + wire_muxes[(init_mux + + iconn) % num_wire_muxes]; + + L_rr_node[to_node].num_opin_drivers++; /* keep track of mux size */ + to_track = L_rr_node[to_node].ptc_num; + + if (FALSE == L_rr_edge_done[to_node]) + { + /* Use of alloc_and_load_edges_and_switches + * must be accompanied by rr_edge_done check. */ + L_rr_edge_done[to_node] = TRUE; + edge_list = + insert_in_edge_list(edge_list, + to_node, + seg_details + [to_track]. + wire_switch); + num_edges++; + } + } + } + + if (num_edges < 1) + { + vpr_printf(TIO_MESSAGE_ERROR, "opin %d at (%d,%d) does not connect to any tracks.\n", + L_rr_node[from_node].ptc_num, L_rr_node[from_node].xlow, L_rr_node[from_node].ylow); + exit(1); + } + + alloc_and_load_edges_and_switches(L_rr_node, from_node, num_edges, + L_rr_edge_done, edge_list); + } +} +#endif + +#if MUX_SIZE_DIST_DISPLAY +/* This routine prints and dumps statistics on the mux sizes on a sblock + * per sblock basis, over the entire chip. Mux sizes should be balanced (off by + * at most 1) for all muxes in the same sblock in the core, and corner sblocks. + * Fringe sblocks will have imbalance due to missing one side and constrains on + * where wires must connect. Comparing two core sblock sblocks, muxes need not + * be balanced if W is not quantized to 2L multiples, again for reasons that + * there could be sblocks with different number of muxes but same number of incoming + * wires that need to make connections to these muxes (we don't want to under-connect + * user-specified Fc and Fs). */ +static void +view_mux_size_distribution(t_ivec *** L_rr_node_indices, + int nodes_per_chan, + t_seg_details * seg_details_x, + t_seg_details * seg_details_y) +{ + + int i, j, itrack, seg_num, chan_num, max_len; + int start, end, inode, max_value, min_value; + int array_count, k, num_muxes; + short direction, side; + float *percent_range_array; + float percent_range, percent_range_sum, avg_percent_range; + float std_dev_percent_range, deviation_f; + int range, *range_array, global_max_range; + float avg_range, range_sum, std_dev_range; + t_seg_details *seg_details; + t_mux *new_mux, *sblock_mux_list_head, *current, *next; + +#ifdef ENABLE_DUMP + FILE *dump_file_per_sblock, *dump_file; +#endif /* ENABLE_DUMP */ + t_mux_size_distribution *distr_list, *distr_current, *new_distribution, + *distr_next; + +#ifdef ENABLE_DUMP + dump_file = my_fopen("mux_size_dump.txt", "w", 0); + dump_file_per_sblock = my_fopen("mux_size_per_sblock_dump.txt", "w", 0); +#endif /* ENABLE_DUMP */ + + sblock_mux_list_head = NULL; + percent_range_array = + (float *)my_malloc((nx - 1) * (ny - 1) * sizeof(float)); + range_array = (int *)my_malloc((nx - 1) * (ny - 1) * sizeof(int)); + array_count = 0; + percent_range_sum = 0.0; + range_sum = 0.0; + global_max_range = 0; + min_value = 0; + max_value = 0; + seg_num = 0; + chan_num = 0; + direction = 0; + seg_details = 0; + max_len = 0; + distr_list = NULL; + + /* With the specified range, I'm only looking at core sblocks */ + for (j = (ny - 1); j > 0; j--) + { + for (i = 1; i < nx; i++) + { + num_muxes = 0; + for (side = 0; side < 4; side++) + { + switch (side) + { + case LEFT: + seg_num = i; + chan_num = j; + direction = DEC_DIRECTION; /* only DEC have muxes in that sblock */ + seg_details = seg_details_x; + max_len = nx; + break; + + case RIGHT: + seg_num = i + 1; + chan_num = j; + direction = INC_DIRECTION; + seg_details = seg_details_x; + max_len = nx; + break; + + case TOP: + seg_num = j + 1; + chan_num = i; + direction = INC_DIRECTION; + seg_details = seg_details_y; + max_len = ny; + break; + + case BOTTOM: + seg_num = j; + chan_num = i; + direction = DEC_DIRECTION; + seg_details = seg_details_y; + max_len = ny; + break; + + default: + assert(FALSE); + } + + assert(nodes_per_chan > 0); + for (itrack = 0; itrack < nodes_per_chan; itrack++) + { + start = + get_seg_start(seg_details, itrack, + seg_num, chan_num); + end = + get_seg_end(seg_details, itrack, + start, chan_num, max_len); + + if ((seg_details[itrack].direction == + direction) && (((start == seg_num) + && (direction == + INC_DIRECTION)) + || ((end == seg_num) + && (direction == + DEC_DIRECTION)))) + { /* mux found */ + num_muxes++; + if (side == LEFT || side == RIGHT) + { /* CHANX */ + inode = + get_rr_node_index + (seg_num, chan_num, + CHANX, itrack, + L_rr_node_indices); + } + else + { + assert((side == TOP) || (side == BOTTOM)); /* CHANY */ + inode = + get_rr_node_index + (chan_num, seg_num, + CHANY, itrack, + L_rr_node_indices); + } + + new_mux = (t_mux *) + my_malloc(sizeof(t_mux)); + new_mux->size = + rr_node[inode]. + num_wire_drivers + + rr_node[inode]. + num_opin_drivers; + new_mux->next = NULL; + + /* insert in linked list, descending */ + if (sblock_mux_list_head == NULL) + { + /* first entry */ + sblock_mux_list_head = + new_mux; + } + else if (sblock_mux_list_head-> + size < new_mux->size) + { + /* insert before head */ + new_mux->next = + sblock_mux_list_head; + sblock_mux_list_head = + new_mux; + } + else + { + /* insert after head */ + current = + sblock_mux_list_head; + next = current->next; + + while ((next != NULL) + && (next->size > + new_mux->size)) + { + current = next; + next = + current->next; + } + + if (next == NULL) + { + current->next = + new_mux; + } + else + { + new_mux->next = + current->next; + current->next = + new_mux; + } + } + /* end of insert in linked list */ + } + } + } /* end of mux searching over all four sides of sblock */ + /* now sblock_mux_list_head holds a linked list of all muxes in this sblock */ + + current = sblock_mux_list_head; + +#ifdef ENABLE_DUMP + fprintf(dump_file_per_sblock, + "sblock at (%d, %d) has mux sizes: {", i, j); +#endif /* ENABLE_DUMP */ + + if (current != NULL) + { + max_value = min_value = current->size; + } + while (current != NULL) + { + if (max_value < current->size) + max_value = current->size; + if (min_value > current->size) + min_value = current->size; + +#ifdef ENABLE_DUMP + fprintf(dump_file_per_sblock, "%d ", + current->size); + fprintf(dump_file, "%d\n", current->size); +#endif /* ENABLE_DUMP */ + + current = current->next; + } + +#ifdef ENABLE_DUMP + fprintf(dump_file_per_sblock, "}\n\tmax: %d\tmin:%d", + max_value, min_value); +#endif /* ENABLE_DUMP */ + + range = max_value - min_value; + percent_range = ((float)range) / ((float)min_value); + + if (global_max_range < range) + global_max_range = range; + +#ifdef ENABLE_DUMP + fprintf(dump_file_per_sblock, + "\t\trange: %d\t\tpercent range:%.2f\n", + range, percent_range); +#endif /* ENABLE_DUMP */ + + percent_range_array[array_count] = percent_range; + range_array[array_count] = range; + + percent_range_sum += percent_range; + range_sum += range; + + array_count++; + + /* I will use a distribution for each (core) sblock type. + * There are more than 1 type of sblocks, + * when quantization of W to 2L multiples is not observed. */ + + distr_current = distr_list; + while (distr_current != NULL + && distr_current->mux_count != num_muxes) + { + distr_current = distr_current->next; + } + + if (distr_current == NULL) + { + /* Create a distribution for the new sblock type, + * and put it as head of linked list by convention */ + + new_distribution = (t_mux_size_distribution *) + my_malloc(sizeof(t_mux_size_distribution)); + new_distribution->mux_count = num_muxes; + new_distribution->max_index = max_value; + new_distribution->distr = + (int *)my_calloc(max_value + 1, sizeof(int)); + + /* filling in the distribution */ + current = sblock_mux_list_head; + while (current != NULL) + { + assert(current->size <= + new_distribution->max_index); + new_distribution->distr[current->size]++; + current = current->next; + } + + /* add it to head */ + new_distribution->next = distr_list; + distr_list = new_distribution; + } + else + { + /* distr_current->mux_count == num_muxes so add this sblock's mux sizes in this distribution */ + current = sblock_mux_list_head; + + while (current != NULL) + { + if (current->size > + distr_current->max_index) + { + /* needs to realloc to expand the distribution array to hold the new large-valued data */ + distr_current->distr = + my_realloc(distr_current-> + distr, + (current->size + + 1) * sizeof(int)); + + /* initializing the newly allocated elements */ + for (k = + (distr_current->max_index + + 1); k <= current->size; k++) + distr_current->distr[k] = 0; + + distr_current->max_index = + current->size; + distr_current->distr[current-> + size]++; + } + else + { + distr_current->distr[current-> + size]++; + } + current = current->next; + } + } + + /* done - now free memory */ + current = sblock_mux_list_head; + while (current != NULL) + { + next = current->next; + free(current); + current = next; + } + sblock_mux_list_head = NULL; + } + } + + avg_percent_range = (float)percent_range_sum / array_count; + avg_range = (float)range_sum / array_count; + + percent_range_sum = 0.0; + range_sum = 0.0; + for (k = 0; k < array_count; k++) + { + deviation_f = (percent_range_array[k] - avg_percent_range); + percent_range_sum += deviation_f * deviation_f; + + deviation_f = ((float)range_array[k] - avg_range); + range_sum += deviation_f * deviation_f; + } + std_dev_percent_range = + sqrt(percent_range_sum / ((float)array_count - 1.0)); + std_dev_range = sqrt(range_sum / ((float)array_count - 1.0)); + vpr_printf(TIO_MESSAGE_INFO, "==== MUX size statistics ====\n"); + vpr_printf(TIO_MESSAGE_INFO, "Max range of mux size within a sblock: %d\n", global_max_range); + vpr_printf(TIO_MESSAGE_INFO, "Average range of mux size within a sblock: %.2f\n", avg_range); + vpr_printf(TIO_MESSAGE_INFO, "Std dev of range of mux size within a sblock: %.2f\n", std_dev_range); + vpr_printf(TIO_MESSAGE_INFO, "Average percent range of mux size within a sblock: %.2f%%\n", avg_percent_range * 100.0); + vpr_printf(TIO_MESSAGE_INFO, "Std dev of percent range of mux size within a sblock: %.2f%%\n", std_dev_percent_range * 100.0); + + vpr_printf(TIO_MESSAGE_INFO, " -- Detailed MUX size distribution by sblock type -- \n"); + distr_current = distr_list; + while (distr_current != NULL) + { + print_distribution(stdout, distr_current); + + /* free */ + distr_next = distr_current->next; + + free(distr_current->distr); + free(distr_current); + + distr_current = distr_next; + } + + free(percent_range_array); + free(range_array); +#ifdef ENABLE_DUMP + fclose(dump_file_per_sblock); + fclose(dump_file); +#endif /* ENABLE_DUMP */ +} + +static void +print_distribution(FILE * fptr, + t_mux_size_distribution * distr_struct) +{ + int *distr; + int k; + float sum; + boolean zeros; + + distr = distr_struct->distr; + fprintf(fptr, + "For Sblocks containing %d MUXes, the MUX size distribution is:\n", + distr_struct->mux_count); + fprintf(fptr, "\t\t\tSize\t\t\tFrequency (percent)\n"); + + sum = 0.0; + for (k = 0; k <= distr_struct->max_index; k++) + sum += distr[k]; + + zeros = TRUE; + for (k = 0; k <= distr_struct->max_index; k++) + { + if (zeros && (distr[k] == 0)) + { + /* do nothing for leading string of zeros */ + } + else + { + zeros = FALSE; /* leading string of zeros ended */ + fprintf(fptr, "\t\t\t%d\t\t\t%d (%.2f%%)\n", k, distr[k], + (float)distr[k] / sum * 100.0); + } + } + fprintf(fptr, "\nEnd of this Sblock MUX size distribution.\n"); + +} +#endif + +/** + * Parse out which CLB pins should connect directly to which other CLB pins then store that in a clb_to_clb_directs data structure + * This data structure supplements the the info in the "directs" data structure + * TODO: The function that does this parsing in placement is poorly done because it lacks generality on heterogeniety, should replace with this one + */ +static t_clb_to_clb_directs * alloc_and_load_clb_to_clb_directs(INP t_direct_inf *directs, INP int num_directs) { + int i, j; + t_clb_to_clb_directs *clb_to_clb_directs; + char *pb_type_name, *port_name; + int start_pin_index, end_pin_index; + t_pb_type *pb_type; + + clb_to_clb_directs = (t_clb_to_clb_directs*)my_calloc(num_directs, sizeof(t_clb_to_clb_directs)); + + pb_type_name = NULL; + port_name = NULL; + + for(i = 0; i < num_directs; i++) { + pb_type_name = (char*)my_malloc((strlen(directs[i].from_pin) + strlen(directs[i].to_pin)) * sizeof(char)); + port_name = (char*)my_malloc((strlen(directs[i].from_pin) + strlen(directs[i].to_pin)) * sizeof(char)); + + // Load from pins + // Parse out the pb_type name, port name, and pin range + parse_direct_pin_name(directs[i].from_pin, directs[i].line, &start_pin_index, &end_pin_index, pb_type_name, port_name); + + // Figure out which type, port, and pin is used + for(j = 0; j < num_types; j++) { + if(strcmp(type_descriptors[j].name, pb_type_name) == 0) { + break; + } + } + assert(j < num_types); + clb_to_clb_directs[i].from_clb_type = &type_descriptors[j]; + pb_type = clb_to_clb_directs[i].from_clb_type->pb_type; + + for(j = 0; j < pb_type->num_ports; j++) { + if(strcmp(pb_type->ports[j].name, port_name) == 0) { + break; + } + } + assert(j < pb_type->num_ports); + + if(start_pin_index == OPEN) { + assert(start_pin_index == end_pin_index); + start_pin_index = 0; + end_pin_index = pb_type->ports[j].num_pins - 1; + } + get_blk_pin_from_port_pin(clb_to_clb_directs[i].from_clb_type->index, j, start_pin_index, &clb_to_clb_directs[i].from_clb_pin_start_index); + get_blk_pin_from_port_pin(clb_to_clb_directs[i].from_clb_type->index, j, end_pin_index, &clb_to_clb_directs[i].from_clb_pin_end_index); + + // Load to pins + // Parse out the pb_type name, port name, and pin range + parse_direct_pin_name(directs[i].to_pin, directs[i].line, &start_pin_index, &end_pin_index, pb_type_name, port_name); + + // Figure out which type, port, and pin is used + for(j = 0; j < num_types; j++) { + if(strcmp(type_descriptors[j].name, pb_type_name) == 0) { + break; + } + } + assert(j < num_types); + clb_to_clb_directs[i].to_clb_type = &type_descriptors[j]; + pb_type = clb_to_clb_directs[i].to_clb_type->pb_type; + + for(j = 0; j < pb_type->num_ports; j++) { + if(strcmp(pb_type->ports[j].name, port_name) == 0) { + break; + } + } + assert(j < pb_type->num_ports); + + if(start_pin_index == OPEN) { + assert(start_pin_index == end_pin_index); + start_pin_index = 0; + end_pin_index = pb_type->ports[j].num_pins - 1; + } + + get_blk_pin_from_port_pin(clb_to_clb_directs[i].to_clb_type->index, j, start_pin_index, &clb_to_clb_directs[i].to_clb_pin_start_index); + get_blk_pin_from_port_pin(clb_to_clb_directs[i].to_clb_type->index, j, end_pin_index, &clb_to_clb_directs[i].to_clb_pin_end_index); + + if(abs(clb_to_clb_directs[i].from_clb_pin_start_index - clb_to_clb_directs[i].from_clb_pin_end_index) != abs(clb_to_clb_directs[i].to_clb_pin_start_index - clb_to_clb_directs[i].to_clb_pin_end_index)) { + vpr_printf(TIO_MESSAGE_ERROR, "[LINE %d] Range mismatch from %s to %s.\n", directs[i].line, directs[i].from_pin, directs[i].to_pin); + exit(1); + } + + free(pb_type_name); + free(port_name); + } + return clb_to_clb_directs; +} + +/* Add all direct clb-pin-to-clb-pin edges to given opin */ +static int get_opin_direct_connecions(int x, int y, int opin, INOUTP t_linked_edge ** edge_list_ptr, INP t_ivec *** L_rr_node_indices, + INP int delayless_switch, INP t_direct_inf *directs, INP int num_directs, INP t_clb_to_clb_directs *clb_to_clb_directs) { + t_type_ptr type; + int grid_ofs; + int i, ipin, inode; + t_linked_edge *edge_list_head; + int max_index, min_index, offset, swap; + int new_edges; + + type = grid[x][y].type; + edge_list_head = *edge_list_ptr; + new_edges = 0; + + /* Iterate through all direct connections */ + for(i = 0; i < num_directs; i++) { + /* Find matching direct clb-to-clb connections with the same type as current grid location */ + if(clb_to_clb_directs[i].from_clb_type == type) { + /* Compute index of opin with regards to given pins */ + if(clb_to_clb_directs[i].from_clb_pin_start_index > clb_to_clb_directs[i].from_clb_pin_end_index) { + swap = TRUE; + max_index = clb_to_clb_directs[i].from_clb_pin_start_index; + min_index = clb_to_clb_directs[i].from_clb_pin_end_index; + } else { + swap = FALSE; + min_index = clb_to_clb_directs[i].from_clb_pin_start_index; + max_index = clb_to_clb_directs[i].from_clb_pin_end_index; + } + if(max_index >= opin && min_index <= opin) { + offset = opin - min_index; + /* This opin is specified to connect directly to an ipin, now compute which ipin to connect to */ + if(x + directs[i].x_offset < nx + 1 && + x + directs[i].x_offset > 0 && + y + directs[i].y_offset < ny + 1 && + y + directs[i].y_offset > 0) { + ipin = OPEN; + if(clb_to_clb_directs[i].to_clb_pin_start_index > clb_to_clb_directs[i].to_clb_pin_end_index) { + if(swap == TRUE) { + ipin = clb_to_clb_directs[i].to_clb_pin_end_index + offset; + } else { + ipin = clb_to_clb_directs[i].to_clb_pin_start_index - offset; + } + } else { + if(swap == TRUE) { + ipin = clb_to_clb_directs[i].to_clb_pin_end_index - offset; + } else { + ipin = clb_to_clb_directs[i].to_clb_pin_start_index + offset; + } + } + /* Add new ipin edge to list of edges */ + grid_ofs = grid[x + directs[i].x_offset][y + directs[i].y_offset].offset; + inode = get_rr_node_index(x + directs[i].x_offset, y + directs[i].y_offset - grid_ofs, IPIN, ipin, L_rr_node_indices); + edge_list_head = insert_in_edge_list(edge_list_head, inode, delayless_switch); + new_edges++; + } + } + } + } + *edge_list_ptr = edge_list_head; + return new_edges; +} + + + diff --git a/vpr7_rram/vpr/SRC/route/rr_graph.h b/vpr7_rram/vpr/SRC/route/rr_graph.h new file mode 100755 index 000000000..41f6315b7 --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/rr_graph.h @@ -0,0 +1,58 @@ +#ifndef RR_GRAPH_H +#define RR_GRAPH_H + +enum e_graph_type { + GRAPH_GLOBAL, /* One node per channel with wire capacity > 1 and full connectivity */ + GRAPH_BIDIR, /* Detailed bidirectional graph */ + GRAPH_UNIDIR, /* Detailed unidir graph, untilable */ + /* RESEARCH TODO: Get this option debugged */ + GRAPH_UNIDIR_TILEABLE /* Detail unidir graph with wire groups multiples of 2*L */ +}; +typedef enum e_graph_type t_graph_type; + +/* Warnings about the routing graph that can be returned. + * This is to avoid output messages during a value sweep */ +enum { + RR_GRAPH_NO_WARN = 0x00, + RR_GRAPH_WARN_FC_CLIPPED = 0x01, + RR_GRAPH_WARN_CHAN_WIDTH_CHANGED = 0x02 +}; + +void build_rr_graph(INP t_graph_type graph_type, + INP int L_num_types, + INP t_type_ptr types, + INP int L_nx, + INP int L_ny, + INP struct s_grid_tile **L_grid, + INP int chan_width, + INP struct s_chan_width_dist *chan_capacity_inf, + INP enum e_switch_block_type sb_type, + INP int Fs, + INP int num_seg_types, + INP int num_switches, + INP t_segment_inf * segment_inf, + INP int global_route_switch, + INP int delayless_switch, + INP t_timing_inf timing_inf, + INP int wire_to_ipin_switch, + INP enum e_base_cost_type base_cost_type, + INP t_direct_inf *directs, + INP int num_directs, + INP boolean ignore_Fc_0, + OUTP int *Warnings, + /* Xifan TANG: Switch Segment Pattern Support*/ + int num_swseg_pattern, + t_swseg_pattern_inf* swseg_patterns, + boolean opin_to_cb_fast_edges, + boolean opin_logic_eq_edges); + +void free_rr_graph(void); + +void dump_rr_graph(INP const char *file_name); +void print_rr_indexed_data(FILE * fp, int index); /* For debugging only */ +void load_net_rr_terminals(t_ivec *** L_rr_node_indices); + +void print_rr_node(FILE *fp, t_rr_node *L_rr_node, int inode); + +#endif + diff --git a/vpr7_rram/vpr/SRC/route/rr_graph2.c b/vpr7_rram/vpr/SRC/route/rr_graph2.c new file mode 100755 index 000000000..1012d3670 --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/rr_graph2.c @@ -0,0 +1,2365 @@ +#include +#include +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph_util.h" +#include "rr_graph2.h" +#include "rr_graph_sbox.h" +#include "read_xml_arch_file.h" + +/*mrFPGA: Xifan TANG */ +#include "mrfpga_globals.h" +#include "mrfpga_api.h" +/* end */ + +#define ALLOW_SWITCH_OFF + +/* WMF: May 07 I put this feature in, but on May 09 in my testing phase + * I found that for Wilton, this feature is bad, since Wilton is already doing + * a reverse. */ +#define ENABLE_REVERSE 0 + +#define SAME_TRACK -5 +#define UN_SET -1 +/* Variables below are the global variables shared only amongst the rr_graph * + ************************************ routines. ******************************/ + +/* Used to keep my own list of free linked integers, for speed reasons. */ + +t_linked_edge *free_edge_list_head = NULL; + +/*************************** Variables local to this module *****************/ + +/* Two arrays below give the rr_node_index of the channel segment at * + * (i,j,track) for fast index lookup. */ + +/* UDSD Modifications by WMF Begin */ + +/* The sblock_pattern_init_mux_lookup contains the assignment of incoming + * wires to muxes. More specifically, it only contains the assignment of + * M-to-N cases. WMF_BETTER_COMMENTS */ + +/* UDSD MOdifications by WMF End */ + +/************************** Subroutines local to this module ****************/ + +static void get_switch_type(boolean is_from_sbox, boolean is_to_sbox, + short from_node_switch, short to_node_switch, short switch_types[2]); + +static void load_chan_rr_indices(INP int nodes_per_chan, INP int chan_len, + INP int num_chans, INP t_rr_type type, INP t_seg_details * seg_details, + INOUTP int *index, INOUTP t_ivec *** indices); + +static int get_bidir_track_to_chan_seg(INP struct s_ivec conn_tracks, + INP t_ivec *** L_rr_node_indices, INP int to_chan, INP int to_seg, + INP int to_sb, INP t_rr_type to_type, INP t_seg_details * seg_details, + INP boolean from_is_sbox, INP int from_switch, + INOUTP boolean * L_rr_edge_done, + INP enum e_directionality directionality, + INOUTP struct s_linked_edge **edge_list); + +static int get_unidir_track_to_chan_seg(INP boolean is_end_sb, + INP int from_track, INP int to_chan, INP int to_seg, INP int to_sb, + INP t_rr_type to_type, INP int nodes_per_chan, INP int L_nx, + INP int L_ny, INP enum e_side from_side, INP enum e_side to_side, + INP int Fs_per_side, INP int *opin_mux_size, + INP short *****sblock_pattern, INP t_ivec *** L_rr_node_indices, + INP t_seg_details * seg_details, INOUTP boolean * L_rr_edge_done, + OUTP boolean * Fs_clipped, INOUTP struct s_linked_edge **edge_list); + +static int vpr_to_phy_track(INP int itrack, INP int chan_num, INP int seg_num, + INP t_seg_details * seg_details, + INP enum e_directionality directionality); + +static int *get_seg_track_counts(INP int num_sets, INP int num_seg_types, + INP t_segment_inf * segment_inf, INP boolean use_full_seg_groups); + +static int *label_wire_muxes(INP int chan_num, INP int seg_num, + INP t_seg_details * seg_details, INP int max_len, + INP enum e_direction dir, INP int nodes_per_chan, + OUTP int *num_wire_muxes); + +static int *label_wire_muxes_for_balance(INP int chan_num, INP int seg_num, + INP t_seg_details * seg_details, INP int max_len, + INP enum e_direction direction, INP int nodes_per_chan, + INP int *num_wire_muxes, INP t_rr_type chan_type, + INP int *opin_mux_size, INP t_ivec *** L_rr_node_indices); + +static int *label_incoming_wires(INP int chan_num, INP int seg_num, + INP int sb_seg, INP t_seg_details * seg_details, INP int max_len, + INP enum e_direction dir, INP int nodes_per_chan, + OUTP int *num_incoming_wires, OUTP int *num_ending_wires); + +static int find_label_of_track(int *wire_mux_on_track, int num_wire_muxes, + int from_track); + +/* mrFPGA : Xifan TANG*/ +/* +static int get_seg_to_seg(INP t_ivec*** L_rr_node_indices, + INP int to_chan, + INP int to_seg, + INP int track, + INP t_rr_type type, + INP t_seg_details* seg_details, + INOUTP struct s_linked_edge** edge_list); +*/ +/* end */ + +/******************** Subroutine definitions *******************************/ + +/* This assigns tracks (individually or pairs) to segment types. + * It tries to match requested ratio. If use_full_seg_groups is + * true, then segments are assigned only in multiples of their + * length. This is primarily used for making a tileable unidir + * layout. The effect of using this is that the number of tracks + * requested will not always be met and the result will sometimes + * be over and sometimes under. + * The pattern when using use_full_seg_groups is to keep adding + * one group of the track type that wants the largest number of + * groups of tracks. Each time a group is assigned, the types + * demand is reduced by 1 unit. The process stops when we are + * no longer less than the requested number of tracks. As a final + * step, if we were closer to target before last more, undo it + * and end up with a result that uses fewer tracks than given. */ +static int * +get_seg_track_counts(INP int num_sets, INP int num_seg_types, + INP t_segment_inf * segment_inf, INP boolean use_full_seg_groups) { + int *result; + double *demand; + int i, imax, freq_sum, assigned, size; + double scale, max, reduce; + + result = (int *) my_malloc(sizeof(int) * num_seg_types); + demand = (double *) my_malloc(sizeof(double) * num_seg_types); + + /* Scale factor so we can divide by any length + * and still use integers */ + scale = 1; + freq_sum = 0; + for (i = 0; i < num_seg_types; ++i) { + scale *= segment_inf[i].length; + freq_sum += segment_inf[i].frequency; + } + reduce = scale * freq_sum; + + /* Init assignments to 0 and set the demand values */ + for (i = 0; i < num_seg_types; ++i) { + result[i] = 0; + demand[i] = scale * num_sets * segment_inf[i].frequency; + if (use_full_seg_groups) { + demand[i] /= segment_inf[i].length; + } + } + + /* Keep assigning tracks until we use them up */ + assigned = 0; + size = 0; + imax = 0; + while (assigned < num_sets) { + /* Find current maximum demand */ + max = 0; + for (i = 0; i < num_seg_types; ++i) { + if (demand[i] > max) { + imax = i; + max = demand[i]; + } + } + + /* Assign tracks to the type and reduce the types demand */ + size = (use_full_seg_groups ? segment_inf[imax].length : 1); + demand[imax] -= reduce; + result[imax] += size; + assigned += size; + } + + /* Undo last assignment if we were closer to goal without it */ + if ((assigned - num_sets) > (size / 2)) { + result[imax] -= size; + } + + /* Free temps */ + if (demand) { + free(demand); + demand = NULL; + } + + /* This must be freed by caller */ + return result; +} + +t_seg_details * +alloc_and_load_seg_details(INOUTP int *nodes_per_chan, INP int max_len, + INP int num_seg_types, INP t_segment_inf * segment_inf, + INP boolean use_full_seg_groups, INP boolean is_global_graph, + INP enum e_directionality directionality) { + + /* Allocates and loads the seg_details data structure. Max_len gives the * + * maximum length of a segment (dimension of array). The code below tries * + * to: * + * (1) stagger the start points of segments of the same type evenly; * + * (2) spread out the limited number of connection boxes or switch boxes * + * evenly along the length of a segment, starting at the segment ends; * + * (3) stagger the connection and switch boxes on different long lines, * + * as they will not be staggered by different segment start points. */ + + int i, cur_track, ntracks, itrack, length, j, index; + int wire_switch, opin_switch, fac, num_sets, tmp; + int group_start, first_track; + int *sets_per_seg_type = NULL; + t_seg_details *seg_details = NULL; + boolean longline; + + /* Unidir tracks are assigned in pairs, and bidir tracks individually */ + if (directionality == BI_DIRECTIONAL) { + fac = 1; + } else { + assert(directionality == UNI_DIRECTIONAL); + fac = 2; + } + assert(*nodes_per_chan % fac == 0); + + /* Map segment type fractions and groupings to counts of tracks */ + sets_per_seg_type = get_seg_track_counts((*nodes_per_chan / fac), + num_seg_types, segment_inf, use_full_seg_groups); + + /* Count the number tracks actually assigned. */ + tmp = 0; + for (i = 0; i < num_seg_types; ++i) { + tmp += sets_per_seg_type[i] * fac; + } + assert(use_full_seg_groups || (tmp == *nodes_per_chan)); + *nodes_per_chan = tmp; + // Xifan TANG Note: Alloc segments + seg_details = (t_seg_details *) my_malloc( + *nodes_per_chan * sizeof(t_seg_details)); + + /* Setup the seg_details data */ + cur_track = 0; + for (i = 0; i < num_seg_types; ++i) { + first_track = cur_track; + + num_sets = sets_per_seg_type[i]; + ntracks = fac * num_sets; + if (ntracks < 1) { + continue; + } + /* Avoid divide by 0 if ntracks */ + longline = segment_inf[i].longline; + length = segment_inf[i].length; + if (longline) { + length = max_len; + } + // Xifan TANG Note: Set the input and output switches + wire_switch = segment_inf[i].wire_switch; + opin_switch = segment_inf[i].opin_switch; + /* Xifan TANG Note: I think it should be && not || in this assert, + * Uni-direcitonal routing architecture, wire_switch and opin_switch should be the same... + */ + //assert( + // (wire_switch == opin_switch) || (directionality != UNI_DIRECTIONAL)); + /* END */ + + /* mrFPGA: Xifan TANG */ + assert((wire_switch == opin_switch) + || (directionality != UNI_DIRECTIONAL) || (is_mrFPGA) ); + /* END */ + + /* Set up the tracks of same type */ + group_start = 0; + for (itrack = 0; itrack < ntracks; itrack++) { + + /* Remember the start track of the current wire group */ + if ((itrack / fac) % length == 0 && (itrack % fac) == 0) { + group_start = cur_track; + } + + seg_details[cur_track].length = length; + seg_details[cur_track].longline = longline; + + /* Stagger the start points in for each track set. The + * pin mappings should be aware of this when chosing an + * intelligent way of connecting pins and tracks. + * cur_track is used as an offset so that extra tracks + * from different segment types are hopefully better + * balanced. */ + /* Original VPR */ + /* seg_details[cur_track].start = (cur_track / fac) % length + 1; */ + /* end */ + /* mrFPGA: Xifan TANG */ + seg_details[cur_track].start = (cur_track / fac) % length + (is_stack ? 0 : 1); + /* end */ + + /* These properties are used for vpr_to_phy_track to determine + * * twisting of wires. */ + seg_details[cur_track].group_start = group_start; + seg_details[cur_track].group_size = + std::min(ntracks + first_track - group_start, + length * fac); + assert(0 == seg_details[cur_track].group_size % fac); + if (0 == seg_details[cur_track].group_size) { + seg_details[cur_track].group_size = length * fac; + } + + /* Setup the cb and sb patterns. Global route graphs can't depopulate cb and sb + * since this is a property of a detailed route. */ + seg_details[cur_track].cb = (boolean *) my_malloc( + length * sizeof(boolean)); + seg_details[cur_track].sb = (boolean *) my_malloc( + (length + 1) * sizeof(boolean)); + for (j = 0; j < length; ++j) { + if (is_global_graph) { + seg_details[cur_track].cb[j] = TRUE; + } else { + index = j; + + /* Rotate longline's so they vary across the FPGA */ + if (longline) { + index = (index + itrack) % length; + } + + /* Reverse the order for tracks going in DEC_DIRECTION */ + if (itrack % fac == 1) { + index = (length - 1) - j; + } + + /* Use the segment's pattern. */ + index = j % segment_inf[i].cb_len; + seg_details[cur_track].cb[j] = segment_inf[i].cb[index]; + } + } + for (j = 0; j < (length + 1); ++j) { + if (is_global_graph) { + seg_details[cur_track].sb[j] = TRUE; + } else { + index = j; + + /* Rotate longline's so they vary across the FPGA */ + if (longline) { + index = (index + itrack) % (length + 1); + } + + /* Reverse the order for tracks going in DEC_DIRECTION */ + if (itrack % fac == 1) { + index = ((length + 1) - 1) - j; + } + + /* Use the segment's pattern. */ + index = j % segment_inf[i].sb_len; + seg_details[cur_track].sb[j] = segment_inf[i].sb[index]; + } + } + + seg_details[cur_track].Rmetal = segment_inf[i].Rmetal; + seg_details[cur_track].Cmetal = segment_inf[i].Cmetal; + //seg_details[cur_track].Cmetal_per_m = segment_inf[i].Cmetal_per_m; + + seg_details[cur_track].wire_switch = wire_switch; + seg_details[cur_track].opin_switch = opin_switch; + + if (BI_DIRECTIONAL == directionality) { + seg_details[cur_track].direction = BI_DIRECTION; + } else { + assert(UNI_DIRECTIONAL == directionality); + seg_details[cur_track].direction = + (itrack % 2) ? DEC_DIRECTION : INC_DIRECTION; + } + + switch (segment_inf[i].directionality) { + case UNI_DIRECTIONAL: + seg_details[cur_track].drivers = SINGLE; + break; + case BI_DIRECTIONAL: + seg_details[cur_track].drivers = MULTI_BUFFERED; + break; + } + + seg_details[cur_track].index = i; + + ++cur_track; + } + } /* End for each segment type. */ + + /* free variables */ + free(sets_per_seg_type); + + return seg_details; +} + +void free_seg_details(t_seg_details * seg_details, int nodes_per_chan) { + + /* Frees all the memory allocated to an array of seg_details structures. */ + + int i; + + for (i = 0; i < nodes_per_chan; i++) { + free(seg_details[i].cb); + free(seg_details[i].sb); + } + free(seg_details); +} + +/* Dumps out an array of seg_details structures to file fname. Used only * + * for debugging. */ +void dump_seg_details(t_seg_details * seg_details, int nodes_per_chan, + const char *fname) { + + FILE *fp; + int i, j; + const char *drivers_names[] = { "multi_buffered", "single" }; + const char *direction_names[] = { "inc_direction", "dec_direction", + "bi_direction" }; + + fp = my_fopen(fname, "w", 0); + + for (i = 0; i < nodes_per_chan; i++) { + fprintf(fp, "Track: %d.\n", i); + fprintf(fp, "Length: %d, Start: %d, Long line: %d " + "wire_switch: %d opin_switch: %d.\n", seg_details[i].length, + seg_details[i].start, seg_details[i].longline, + seg_details[i].wire_switch, seg_details[i].opin_switch); + + fprintf(fp, "Rmetal: %g Cmetal: %g\n", seg_details[i].Rmetal, + seg_details[i].Cmetal); + + fprintf(fp, "Direction: %s Drivers: %s\n", + direction_names[seg_details[i].direction], + drivers_names[seg_details[i].drivers]); + + fprintf(fp, "cb list: "); + for (j = 0; j < seg_details[i].length; j++) + fprintf(fp, "%d ", seg_details[i].cb[j]); + fprintf(fp, "\n"); + + fprintf(fp, "sb list: "); + for (j = 0; j <= seg_details[i].length; j++) + fprintf(fp, "%d ", seg_details[i].sb[j]); + fprintf(fp, "\n"); + + fprintf(fp, "\n"); + } + + fclose(fp); +} + +/* Returns the segment number at which the segment this track lies on * + * started. */ +int get_seg_start(INP t_seg_details * seg_details, INP int itrack, + INP int chan_num, INP int seg_num) { + + int seg_start, length, start; + + seg_start = 1; + if (FALSE == seg_details[itrack].longline) { + + length = seg_details[itrack].length; + start = seg_details[itrack].start; + + /* Start is guaranteed to be between 1 and length. Hence adding length to * + * the quantity in brackets below guarantees it will be nonnegative. */ + /* Original VPR */ + /* assert(start > 0); */ + /* end */ + /* mrFPGA: Xifan TANG */ + assert(is_stack ? start >= 0: start > 0); + /* end */ + assert(start <= length); + + /* NOTE: Start points are staggered between different channels. + * The start point must stagger backwards as chan_num increases. + * Unidirectional routing expects this to allow the N-to-N + * assumption to be made with respect to ending wires in the core. */ + /* mrFPGA: Xifan TANG */ + seg_start = seg_num - (seg_num - (is_stack ? 1 : 0) + length + chan_num - start) % length; + seg_start = std::max(seg_start, is_stack ? 0 : 1); + /* end */ + /* Original VPR */ + /* + seg_start = seg_num - (seg_num + length + chan_num - start) % length; + if (seg_start < 1) { + seg_start = 1; + } + */ + /* end */ + } + + return seg_start; +} + +int get_seg_end(INP t_seg_details * seg_details, INP int itrack, INP int istart, + INP int chan_num, INP int seg_max) { + int len, ofs, end, first_full; + + len = seg_details[itrack].length; + ofs = seg_details[itrack].start; + + /* Normal endpoint */ + end = istart + len - 1; + + /* If start is against edge it may have been clipped */ + /* Original VPR*/ + /* if (1 == istart) { */ + /* end */ + /* mrFPGA: Xifan TANG */ + if ((is_stack ? 0 : 1) == istart) { + /* end */ + /* If the (staggered) startpoint of first full wire wasn't + * also 1, we must be the clipped wire */ + /* Original VPR*/ + /* first_full = (len - (chan_num % len) + ofs - 1) % len + 1; */ + /* end */ + /* mrFPGA: Xifan TANG */ + first_full = (len - (chan_num - (is_stack ? 1 : 0)) % len + ofs + (is_stack ? 1: 0) - 1) % len + + (is_stack ? 0 : 1); + /* end */ + /* Original VPR*/ + /* if (first_full > 1) { */ + /* end */ + /* mrFPGA: Xifan TANG */ + if (first_full > (is_stack ? 0 : 1)) { + /* end */ + /* then we stop just before the first full seg */ + end = first_full - 1; + } + } + + /* Clip against far edge */ + if (end > seg_max) { + end = seg_max; + } + + return end; +} + +/* Returns the number of tracks to which clb opin #ipin at (i,j) connects. * + * Also stores the nodes to which this pin connects in the linked list * + * pointed to by *edge_list_ptr. */ +int get_bidir_opin_connections(INP int i, INP int j, INP int ipin, + INP struct s_linked_edge **edge_list, INP int *****opin_to_track_map, + INP int Fc, INP boolean * L_rr_edge_done, + INP t_ivec *** L_rr_node_indices, INP t_seg_details * seg_details) { + + int iside, num_conn, ofs, tr_i, tr_j, chan, seg; + int to_track, to_switch, to_node, iconn; + int is_connected_track; + t_type_ptr type; + t_rr_type to_type; + + type = grid[i][j].type; + ofs = grid[i][j].offset; + + num_conn = 0; + + /* [0..num_types-1][0..num_pins-1][0..height][0..3][0..Fc-1] */ + for (iside = 0; iside < 4; iside++) { + + /* Figure out coords of channel segment based on side */ + tr_i = ((iside == LEFT) ? (i - 1) : i); + tr_j = ((iside == BOTTOM) ? (j - 1) : j); + + to_type = ((iside == LEFT) || (iside == RIGHT)) ? CHANY : CHANX; + + chan = ((to_type == CHANX) ? tr_j : tr_i); + seg = ((to_type == CHANX) ? tr_i : tr_j); + + /* Don't connect where no tracks on fringes */ + if ((tr_i < 0) || (tr_i > nx)) { + continue; + } + if ((tr_j < 0) || (tr_j > ny)) { + continue; + } + if ((CHANX == to_type) && (tr_i < 1)) { + continue; + } + if ((CHANY == to_type) && (tr_j < 1)) { + continue; + } + + is_connected_track = FALSE; + + /* Itterate of the opin to track connections */ + for (iconn = 0; iconn < Fc; ++iconn) { + to_track = opin_to_track_map[type->index][ipin][ofs][iside][iconn]; + + /* Skip unconnected connections */ + if (OPEN == to_track || is_connected_track) { + is_connected_track = TRUE; + assert( + OPEN == opin_to_track_map[type-> index][ipin][ofs][iside] [0]); + continue; + } + + /* Only connect to wire if there is a CB */ + if (is_cbox(chan, seg, to_track, seg_details, BI_DIRECTIONAL)) { + to_switch = seg_details[to_track].wire_switch; + to_node = get_rr_node_index(tr_i, tr_j, to_type, to_track, + L_rr_node_indices); + + *edge_list = insert_in_edge_list(*edge_list, to_node, + to_switch); + L_rr_edge_done[to_node] = TRUE; + ++num_conn; + } + } + } + + return num_conn; +} + +int get_unidir_opin_connections(INP int chan, INP int seg, INP int Fc, + INP t_rr_type chan_type, INP t_seg_details * seg_details, + INOUTP t_linked_edge ** edge_list_ptr, INOUTP int **Fc_ofs, + INOUTP boolean * L_rr_edge_done, INP int max_len, + INP int nodes_per_chan, INP t_ivec *** L_rr_node_indices, + OUTP boolean * Fc_clipped) { + /* Gets a linked list of Fc nodes to connect to in given + * chan seg. Fc_ofs is used for the for the opin staggering + * pattern. */ + + int *inc_muxes = NULL; + int *dec_muxes = NULL; + int num_inc_muxes, num_dec_muxes, iconn; + int inc_inode, dec_inode; + int inc_mux, dec_mux; + int inc_track, dec_track; + int x, y; + int num_edges; + + *Fc_clipped = FALSE; + + /* Fc is assigned in pairs so check it is even. */ + assert(Fc % 2 == 0); + + /* get_rr_node_indices needs x and y coords. */ + /* Original VPR */ + /* + x = ((CHANX == chan_type) ? seg : chan); + y = ((CHANX == chan_type) ? chan : seg); + */ + /* end */ + /* mrFPGA : Xifan TANG */ + x = (((is_stack ? CHANY : CHANX) == chan_type) ? seg : chan); + y = (((is_stack ? CHANY : CHANX) == chan_type) ? chan : seg); + /* end */ + + /* Get the lists of possible muxes. */ + inc_muxes = label_wire_muxes(chan, seg, seg_details, max_len, INC_DIRECTION, + nodes_per_chan, &num_inc_muxes); + dec_muxes = label_wire_muxes(chan, seg, seg_details, max_len, DEC_DIRECTION, + nodes_per_chan, &num_dec_muxes); + + /* Clip Fc to the number of muxes. */ + if (((Fc / 2) > num_inc_muxes) || ((Fc / 2) > num_dec_muxes)) { + *Fc_clipped = TRUE; + Fc = 2 * std::min(num_inc_muxes, num_dec_muxes); + } + + /* Assign tracks to meet Fc demand */ + num_edges = 0; + for (iconn = 0; iconn < (Fc / 2); ++iconn) { + /* Figure of the next mux to use */ + inc_mux = Fc_ofs[chan][seg] % num_inc_muxes; + dec_mux = Fc_ofs[chan][seg] % num_dec_muxes; + ++Fc_ofs[chan][seg]; + + /* Figure out the track it corresponds to. */ + inc_track = inc_muxes[inc_mux]; + dec_track = dec_muxes[dec_mux]; + + /* Figure the inodes of those muxes */ + inc_inode = get_rr_node_index(x, y, chan_type, inc_track, + L_rr_node_indices); + dec_inode = get_rr_node_index(x, y, chan_type, dec_track, + L_rr_node_indices); + + /* Add to the list. */ + if (FALSE == L_rr_edge_done[inc_inode]) { + L_rr_edge_done[inc_inode] = TRUE; + *edge_list_ptr = insert_in_edge_list(*edge_list_ptr, inc_inode, + seg_details[inc_track].opin_switch); + ++num_edges; + } + if (FALSE == L_rr_edge_done[dec_inode]) { + L_rr_edge_done[dec_inode] = TRUE; + *edge_list_ptr = insert_in_edge_list(*edge_list_ptr, dec_inode, + seg_details[dec_track].opin_switch); + ++num_edges; + } + } + + if (inc_muxes) { + free(inc_muxes); + inc_muxes = NULL; + } + if (dec_muxes) { + free(dec_muxes); + dec_muxes = NULL; + } + + return num_edges; +} + +boolean is_cbox(INP int chan, INP int seg, INP int track, + INP t_seg_details * seg_details, + INP enum e_directionality directionality) { + + int length, ofs, start_seg; + + length = seg_details[track].length; + + /* Make sure they gave us correct start */ + start_seg = get_seg_start(seg_details, track, chan, seg); + + ofs = seg - start_seg; + + assert(ofs >= 0); + assert(ofs < length); + + /* If unidir segment that is going backwards, we need to flip the ofs */ + if (DEC_DIRECTION == seg_details[track].direction) { + ofs = (length - 1) - ofs; + } + + return seg_details[track].cb[ofs]; +} + +static void load_chan_rr_indices(INP int nodes_per_chan, INP int chan_len, + INP int num_chans, INP t_rr_type type, INP t_seg_details * seg_details, + INOUTP int *index, INOUTP t_ivec *** indices) { + int chan, seg, track, start, inode; + + indices[type] = (t_ivec **) my_malloc(sizeof(t_ivec *) * num_chans); + for (chan = 0; chan < num_chans; ++chan) { + indices[type][chan] = (t_ivec *) my_malloc(sizeof(t_ivec) * chan_len); + + indices[type][chan][0].nelem = 0; + indices[type][chan][0].list = NULL; + + /* Original VPR */ + /* for (seg = 1; seg < chan_len; ++seg) { */ + /* end */ + /* mrFPGA: Xifan TANG */ + for (seg = (is_stack ? 0 : 1); seg < chan_len; ++seg) { + /* end */ + /* Alloc the track inode lookup list */ + indices[type][chan][seg].nelem = nodes_per_chan; + indices[type][chan][seg].list = (int *) my_malloc( + sizeof(int) * nodes_per_chan); + for (track = 0; track < nodes_per_chan; ++track) { + indices[type][chan][seg].list[track] = OPEN; + } + } + } + + /* Original VPR */ + /* + for (chan = 0; chan < num_chans; ++chan) { + for (seg = 1; seg < chan_len; ++seg) { + */ + /* end */ + /* mrFPGA: Xifan TANG */ + for (chan = (is_stack ? 1 : 0); chan < num_chans; ++chan) { + for (seg = (is_stack ? 0 : 1); seg < chan_len; ++seg) { + /* end */ + /* Assign an inode to the starts of tracks */ + for (track = 0; track < indices[type][chan][seg].nelem; ++track) { + start = get_seg_start(seg_details, track, chan, seg); + /* Original VPR */ + /* If the start of the wire doesn't have a inode, + * assign one to it. */ + inode = indices[type][chan][start].list[track]; + if (OPEN == inode) { + inode = *index; + ++(*index); + + indices[type][chan][start].list[track] = inode; + } + /* end */ + /* Assign inode of start of wire to current position */ + indices[type][chan][seg].list[track] = inode; + } + } + } +} + +struct s_ivec *** +alloc_and_load_rr_node_indices(INP int nodes_per_chan, INP int L_nx, + INP int L_ny, INOUTP int *index, INP t_seg_details * seg_details) { + + /* Allocates and loads all the structures needed for fast lookups of the * + * index of an rr_node. rr_node_indices is a matrix containing the index * + * of the *first* rr_node at a given (i,j) location. */ + + int i, j, k, ofs; + t_ivec ***indices; + t_ivec tmp; + t_type_ptr type; + + /* Alloc the lookup table */ + indices = (t_ivec ***) my_malloc(sizeof(t_ivec **) * NUM_RR_TYPES); + indices[IPIN] = (t_ivec **) my_malloc(sizeof(t_ivec *) * (L_nx + 2)); + indices[SINK] = (t_ivec **) my_malloc(sizeof(t_ivec *) * (L_nx + 2)); + for (i = 0; i <= (L_nx + 1); ++i) { + indices[IPIN][i] = (t_ivec *) my_malloc(sizeof(t_ivec) * (L_ny + 2)); + indices[SINK][i] = (t_ivec *) my_malloc(sizeof(t_ivec) * (L_ny + 2)); + for (j = 0; j <= (L_ny + 1); ++j) { + indices[IPIN][i][j].nelem = 0; + indices[IPIN][i][j].list = NULL; + + indices[SINK][i][j].nelem = 0; + indices[SINK][i][j].list = NULL; + } + } + + /* Count indices for block nodes */ + for (i = 0; i <= (L_nx + 1); i++) { + for (j = 0; j <= (L_ny + 1); j++) { + ofs = grid[i][j].offset; + if (0 == ofs) { + type = grid[i][j].type; + + /* Load the pin class lookups. The ptc nums for SINK and SOURCE + * are disjoint so they can share the list. */ + tmp.nelem = type->num_class; + tmp.list = NULL; + if (tmp.nelem > 0) { + tmp.list = (int *) my_malloc(sizeof(int) * tmp.nelem); + for (k = 0; k < tmp.nelem; ++k) { + tmp.list[k] = *index; + ++(*index); + } + } + indices[SINK][i][j] = tmp; + + /* Load the pin lookups. The ptc nums for IPIN and OPIN + * are disjoint so they can share the list. */ + tmp.nelem = type->num_pins; + tmp.list = NULL; + if (tmp.nelem > 0) { + tmp.list = (int *) my_malloc(sizeof(int) * tmp.nelem); + for (k = 0; k < tmp.nelem; ++k) { + tmp.list[k] = *index; + ++(*index); + } + } + indices[IPIN][i][j] = tmp; + } + } + } + + /* Point offset blocks of a large block to base block */ + for (i = 0; i <= (L_nx + 1); i++) { + for (j = 0; j <= (L_ny + 1); j++) { + ofs = grid[i][j].offset; + if (ofs > 0) { + /* NOTE: this only supports vertical large blocks */ + indices[SINK][i][j] = indices[SINK][i][j - ofs]; + indices[IPIN][i][j] = indices[IPIN][i][j - ofs]; + } + } + } + + /* SOURCE and SINK have unique ptc values so their data can be shared. + * IPIN and OPIN have unique ptc values so their data can be shared. */ + indices[SOURCE] = indices[SINK]; + indices[OPIN] = indices[IPIN]; + + /* Original VPR */ + /* Load the data for x and y channels */ + /* + load_chan_rr_indices(nodes_per_chan, L_nx + 1, L_ny + 1, CHANX, seg_details, + index, indices); + load_chan_rr_indices(nodes_per_chan, L_ny + 1, L_nx + 1, CHANY, seg_details, + index, indices); + */ + /* end */ + /* mrFPGA : Xifan TANG */ + load_chan_rr_indices(nodes_per_chan, (is_stack ? L_ny + 1 : L_nx + 1), (is_stack ? L_nx + 1 : L_ny + 1), + CHANX, seg_details, index, indices); + load_chan_rr_indices(nodes_per_chan, (is_stack ? L_nx + 1 : L_ny + 1), (is_stack ? L_ny + 1 : L_nx + 1), + CHANY, seg_details, index, indices); + /* end */ + + return indices; +} + +void free_rr_node_indices(INP t_ivec *** L_rr_node_indices) { + int i, j, ofs; + /* This function must unallocate the structure allocated in + * alloc_and_load_rr_node_indices. */ + for (i = 0; i <= (nx + 1); ++i) { + for (j = 0; j <= (ny + 1); ++j) { + ofs = grid[i][j].offset; + if (ofs > 0) { + /* Vertical large blocks reference is same as offset 0 */ + L_rr_node_indices[SINK][i][j].list = NULL; + L_rr_node_indices[IPIN][i][j].list = NULL; + continue; + } + if (L_rr_node_indices[SINK][i][j].list != NULL) { + free(L_rr_node_indices[SINK][i][j].list); + } + if (L_rr_node_indices[IPIN][i][j].list != NULL) { + free(L_rr_node_indices[IPIN][i][j].list); + } + } + free(L_rr_node_indices[SINK][i]); + free(L_rr_node_indices[IPIN][i]); + } + free(L_rr_node_indices[SINK]); + free(L_rr_node_indices[IPIN]); + + for (i = 0; i < (nx + 1); ++i) { + for (j = 0; j < (ny + 1); ++j) { + if (L_rr_node_indices[CHANY][i][j].list != NULL) { + free(L_rr_node_indices[CHANY][i][j].list); + } + } + free(L_rr_node_indices[CHANY][i]); + } + free(L_rr_node_indices[CHANY]); + + for (i = 0; i < (ny + 1); ++i) { + for (j = 0; j < (nx + 1); ++j) { + if (L_rr_node_indices[CHANX][i][j].list != NULL) { + free(L_rr_node_indices[CHANX][i][j].list); + } + } + free(L_rr_node_indices[CHANX][i]); + } + free(L_rr_node_indices[CHANX]); + + free(L_rr_node_indices); +} + +int get_rr_node_index(int x, int y, t_rr_type rr_type, int ptc, + t_ivec *** L_rr_node_indices) { + /* Returns the index of the specified routing resource node. (x,y) are * + * the location within the FPGA, rr_type specifies the type of resource, * + * and ptc gives the number of this resource. ptc is the class number, * + * pin number or track number, depending on what type of resource this * + * is. All ptcs start at 0 and go up to pins_per_clb-1 or the equivalent. * + * The order within a clb is: SOURCEs + SINKs (type->num_class of them); IPINs, * + * and OPINs (pins_per_clb of them); CHANX; and CHANY (nodes_per_chan of * + * each). For (x,y) locations that point at pads the order is: type->capacity * + * occurances of SOURCE, SINK, OPIN, IPIN (one for each pad), then one * + * associated channel (if there is a channel at (x,y)). All IO pads are * + * bidirectional, so while each will be used only as an INPAD or as an * + * OUTPAD, all the switches necessary to do both must be in each pad. * + * * + * Note that for segments (CHANX and CHANY) of length > 1, the segment is * + * given an rr_index based on the (x,y) location at which it starts (i.e. * + * lowest (x,y) location at which this segment exists). * + * This routine also performs error checking to make sure the node in * + * question exists. */ + + int iclass, tmp; + t_type_ptr type; + t_ivec lookup; + + assert(ptc >= 0); + assert(x >= 0 && x <= (nx + 1)); + assert(y >= 0 && y <= (ny + 1)); + + type = grid[x][y].type; + + /* Currently need to swap x and y for CHANX because of chan, seg convention */ + /* Original VPR */ + /* + if (CHANX == rr_type) { + tmp = x; + x = y; + y = tmp; + } + */ + /* end */ + /* mrFPGA: Xifan TANG*/ + if ((is_stack ? CHANY : CHANX) == rr_type) { + tmp = x; + x = y; + y = tmp; + } + /* end */ + + /* Start of that block. */ + lookup = L_rr_node_indices[rr_type][x][y]; + + /* Check valid ptc num */ + assert(ptc >= 0); + assert(ptc < lookup.nelem); + +#ifdef DEBUG + switch (rr_type) { + case SOURCE: + assert(ptc < type->num_class); + assert(type->class_inf[ptc].type == DRIVER); + break; + + case SINK: + assert(ptc < type->num_class); + assert(type->class_inf[ptc].type == RECEIVER); + break; + + case OPIN: + assert(ptc < type->num_pins); + iclass = type->pin_class[ptc]; + assert(type->class_inf[iclass].type == DRIVER); + break; + + case IPIN: + assert(ptc < type->num_pins); + iclass = type->pin_class[ptc]; + assert(type->class_inf[iclass].type == RECEIVER); + break; + + case CHANX: + case CHANY: + break; + + default: + vpr_printf(TIO_MESSAGE_ERROR, "Bad rr_node passed to get_rr_node_index.\n"); + vpr_printf(TIO_MESSAGE_ERROR, "Request for type=%d ptc=%d at (%d, %d).\n", rr_type, ptc, x, y); + exit(1); + } +#endif + + return lookup.list[ptc]; +} + +int get_track_to_ipins(int seg, int chan, int track, + t_linked_edge ** edge_list_ptr, t_ivec *** L_rr_node_indices, + struct s_ivec ****track_to_ipin_lookup, t_seg_details * seg_details, + enum e_rr_type chan_type, int chan_length, int wire_to_ipin_switch, + enum e_directionality directionality) { + + /* This counts the fan-out from wire segment (chan, seg, track) to blocks on either side */ + + t_linked_edge *edge_list_head; + int j, pass, iconn, phy_track, end, to_node, max_conn, ipin, side, x, y, + num_conn; + t_type_ptr type; + int off; + + /* End of this wire */ + /* Original VPR */ + /* end = get_seg_end(seg_details, track, seg, chan, chan_length); */ + /* end */ + /* mrFPGA: Xifan TANG */ + end = get_seg_end(seg_details, track, seg, chan, chan_length); + /* end */ + + edge_list_head = *edge_list_ptr; + num_conn = 0; + + for (j = seg; j <= end; j++) { + if (is_cbox(chan, j, track, seg_details, directionality)) { + for (pass = 0; pass < 2; ++pass) { + /* mrFPGA: Xifan TANG */ + if (is_stack) { + if (CHANX == chan_type) { + x = chan; + y = j + pass; + side = (0 == pass ? TOP : BOTTOM); + } else { + assert(CHANY == chan_type); + x = j + pass; + y = chan; + side = (0 == pass ? RIGHT : LEFT); + } + /* end */ + } else { + /* Original VPR */ + if (CHANX == chan_type) { + x = j; + y = chan + pass; + side = (0 == pass ? TOP : BOTTOM); + } else { + assert(CHANY == chan_type); + x = chan + pass; + y = j; + side = (0 == pass ? RIGHT : LEFT); + } + /* end */ + } + /* PAJ - if the pointed to is an EMPTY then shouldn't look for ipins */ + if (grid[x][y].type == EMPTY_TYPE) + continue; + + /* Move from logical (straight) to physical (twisted) track index + * - algorithm assigns ipin connections to same physical track index + * so that the logical track gets distributed uniformly */ + phy_track = vpr_to_phy_track(track, chan, j, seg_details, + directionality); + + /* We need the type to find the ipin map for this type */ + type = grid[x][y].type; + off = grid[x][y].offset; + + max_conn = + track_to_ipin_lookup[type->index][phy_track][off][side].nelem; + for (iconn = 0; iconn < max_conn; iconn++) { + ipin = + track_to_ipin_lookup[type->index][phy_track][off][side].list[iconn]; + + /* Check there is a connection and Fc map isn't wrong */ + assert(type->pinloc[off][side][ipin]); + assert(type->is_global_pin[ipin] == FALSE); + + to_node = get_rr_node_index(x, y, IPIN, ipin, + L_rr_node_indices); + edge_list_head = insert_in_edge_list(edge_list_head, + to_node, wire_to_ipin_switch); + } + num_conn += max_conn; + } + } + } + + *edge_list_ptr = edge_list_head; + return (num_conn); +} + +/* Counts how many connections should be made from this segment to the y- * + * segments in the adjacent channels at to_j. It returns the number of * + * connections, and updates edge_list_ptr to point at the head of the * + * (extended) linked list giving the nodes to which this segment connects * + * and the switch type used to connect to each. * + * * + * An edge is added from this segment to a y-segment if: * + * (1) this segment should have a switch box at that location, or * + * (2) the y-segment to which it would connect has a switch box, and the * + * switch type of that y-segment is unbuffered (bidirectional pass * + * transistor). * + * * + * For bidirectional: * + * If the switch in each direction is a pass transistor (unbuffered), both * + * switches are marked as being of the types of the larger (lower R) pass * + * transistor. */ +int get_track_to_tracks(INP int from_chan, INP int from_seg, INP int from_track, + INP t_rr_type from_type, INP int to_seg, INP t_rr_type to_type, + INP int chan_len, INP int nodes_per_chan, INP int *opin_mux_size, + INP int Fs_per_side, INP short *****sblock_pattern, + INOUTP struct s_linked_edge **edge_list, + INP t_seg_details * seg_details, + INP enum e_directionality directionality, + INP t_ivec *** L_rr_node_indices, INOUTP boolean * L_rr_edge_done, + INP struct s_ivec ***switch_block_conn) { + int num_conn; + int from_switch, from_end, from_sb, from_first; + int to_chan, to_sb; + int start, end; + struct s_ivec conn_tracks; + boolean from_is_sbox, is_behind, Fs_clipped; + enum e_side from_side_a, from_side_b, to_side; + + /* mrFPGA: Xifan TANG */ + //int true_from_start, true_from_end; + + /* Original VPR */ + assert( + from_seg == get_seg_start(seg_details, from_track, from_chan, from_seg)); + + from_end = get_seg_end(seg_details, from_track, from_seg, from_chan, + chan_len); + /* end */ + + from_switch = seg_details[from_track].wire_switch; + + /* mrFPGA : Xifan TANG*/ + if (is_stack) { + from_end = from_end + 1; + from_first = from_seg; + /* end */ + } else { + /* Original VPR */ + from_first = from_seg - 1; + } + /* end */ + + /* mrFPGA : Xifan TANG*/ + if (is_stack ? (CHANY == from_type) : (CHANX == from_type)) { + from_side_a = RIGHT; + from_side_b = LEFT; + } else { + assert(is_stack ? (CHANX == from_type) : (CHANY == from_type)); + from_side_a = TOP; + from_side_b = BOTTOM; + } + /* end */ + + /* Original VPR */ + /* Figure out the sides of SB the from_wire will use */ + /* + if (CHANX == from_type) { + from_side_a = RIGHT; + from_side_b = LEFT; + } else { + assert(CHANY == from_type); + from_side_a = TOP; + from_side_b = BOTTOM; + } + */ + /* end */ + + /* Figure out if the to_wire is connecting to a SB + * that is behind it. */ + is_behind = FALSE; + if (to_type == from_type) { + /* Original VPR */ + /* If inline, check that they only are trying + * to connect at endpoints. */ + /* + assert((to_seg == (from_end + 1)) || (to_seg == (from_seg - 1))); + if (to_seg > from_end) { + is_behind = TRUE; + } + */ + /* end */ + /* mrFPGA: Xifan TANG */ + assert((to_seg == (from_end + (is_stack ? 0 : 1))) || (to_seg == (from_seg - 1))); + if (is_stack ? to_seg >= from_end : to_seg > from_end) { + is_behind = TRUE; + } + /* end */ + } else { + /* Original VPR */ + /* If bending, check that they are adjacent to + * our channel. */ + /* + assert((to_seg == from_chan) || (to_seg == (from_chan + 1))); + if (to_seg > from_chan) { + is_behind = TRUE; + } + */ + /* end */ + /* mrFPGA: Xifan TANG */ + if (is_stack) { + assert((to_seg == (from_chan - 1)) || (to_seg == from_chan)); + } else { + assert((to_seg == from_chan) || (to_seg == (from_chan + 1))); + } + if (is_stack ? (to_seg >= from_chan) : (to_seg > from_chan)) { + is_behind = TRUE; + } + /* end */ + } + + /* Original VPR */ + /* Figure out the side of SB the to_wires will use. + * The to_seg and from_chan are in same direction. */ + /* + if (CHANX == to_type) { + to_side = (is_behind ? RIGHT : LEFT); + } else { + assert(CHANY == to_type); + to_side = (is_behind ? TOP : BOTTOM); + } + */ + /* end */ + + /* mrFPGA: Xifan TANG */ + if (is_stack ? (CHANY == to_type) : (CHANX == to_type)) { + to_side = (is_behind ? RIGHT : LEFT); + } else { + assert(is_stack ? (CHANX == to_type) : (CHANY == to_type)); + to_side = (is_behind ? TOP : BOTTOM); + } + /* end */ + + /* Set the loop bounds */ + start = from_first; + end = from_end; + + /* If we are connecting in same direction the connection is + * on one of the two sides so clip the bounds to the SB of + * interest and proceed normally. */ + if (to_type == from_type) { + start = (is_behind ? end : start); + end = start; + } + + /* Iterate over the SBs */ + num_conn = 0; + for (from_sb = start; from_sb <= end; ++from_sb) { + /* mrFPGA: Xifan TANG */ + if (is_stack) { + if (CHANX == from_type) { + if ((0 == from_sb)||((ny + 1) == from_sb)) { + continue; + } + } else { + assert(CHANY == from_type); + if ((0 == from_sb)||((nx + 1) == from_sb)) { + continue; + } + } + } + /* end */ + + /* Figure out if we are at a sbox */ + from_is_sbox = is_sbox(from_chan, from_seg, from_sb, from_track, + seg_details, directionality); + /* end of wire must be an sbox */ + if (from_sb == from_end || from_sb == from_first) { + from_is_sbox = TRUE; /* Endpoints always default to true */ + } + + /* to_chan is the current segment if different directions, + * otherwise to_chan is the from_chan */ + to_chan = from_sb; + to_sb = from_chan; + if (from_type == to_type) { + to_chan = from_chan; + to_sb = from_sb; + } + + /* Do the edges going to the left or down */ + if (from_sb < from_end) { + if (BI_DIRECTIONAL == directionality) { + conn_tracks = + switch_block_conn[from_side_a][to_side][from_track]; + num_conn += get_bidir_track_to_chan_seg(conn_tracks, + L_rr_node_indices, to_chan, to_seg, to_sb, to_type, + seg_details, from_is_sbox, from_switch, L_rr_edge_done, + directionality, edge_list); + } + if (UNI_DIRECTIONAL == directionality) { + /* No fanout if no SB. */ + /* We are connecting from the top or right of SB so it + * makes the most sense to only there from DEC_DIRECTION wires. */ + if ((from_is_sbox) + && (DEC_DIRECTION == seg_details[from_track].direction)) { + num_conn += get_unidir_track_to_chan_seg( + (boolean)(from_sb == from_first), from_track, to_chan, + to_seg, to_sb, to_type, nodes_per_chan, nx, ny, + from_side_a, to_side, Fs_per_side, opin_mux_size, + sblock_pattern, L_rr_node_indices, seg_details, + L_rr_edge_done, &Fs_clipped, edge_list); + } + } + } + + /* Do the edges going to the right or up */ + if (from_sb > from_first) { + if (BI_DIRECTIONAL == directionality) { + conn_tracks = + switch_block_conn[from_side_b][to_side][from_track]; + num_conn += get_bidir_track_to_chan_seg(conn_tracks, + L_rr_node_indices, to_chan, to_seg, to_sb, to_type, + seg_details, from_is_sbox, from_switch, L_rr_edge_done, + directionality, edge_list); + } + if (UNI_DIRECTIONAL == directionality) { + /* No fanout if no SB. */ + /* We are connecting from the bottom or left of SB so it + * makes the most sense to only there from INC_DIRECTION wires. */ + if ((from_is_sbox) + && (INC_DIRECTION == seg_details[from_track].direction)) { + num_conn += get_unidir_track_to_chan_seg( + (boolean)(from_sb == from_end), from_track, to_chan, to_seg, + to_sb, to_type, nodes_per_chan, nx, ny, from_side_b, + to_side, Fs_per_side, opin_mux_size, sblock_pattern, + L_rr_node_indices, seg_details, L_rr_edge_done, + &Fs_clipped, edge_list); + } + } + } + } + + return num_conn; +} + +/* mrFPGA : Xifan TANG, Abolish */ +/* +static int get_seg_to_seg(INP t_ivec*** L_rr_node_indices, + INP int to_chan, + INP int to_seg, + INP int track, + INP t_rr_type type, + INP t_seg_details* seg_details, + INOUTP struct s_linked_edge** edge_list) { + int to_x, to_y, to_node; + + if ((is_stack ? CHANY : CHANX) == type) { + to_x = to_seg; + to_y = to_chan; + } else { + assert((is_stack ? CHANX : CHANY) == type); + to_x = to_chan; + to_y = to_seg; + } + to_node = get_rr_node_index(to_x, to_y, type, track, L_rr_node_indices); + *edge_list = insert_in_edge_list(*edge_list, to_node, seg_details[track].seg_switch); + + return 1; +} +*/ +/* END */ + + +static int get_bidir_track_to_chan_seg(INP struct s_ivec conn_tracks, + INP t_ivec *** L_rr_node_indices, INP int to_chan, INP int to_seg, + INP int to_sb, INP t_rr_type to_type, INP t_seg_details * seg_details, + INP boolean from_is_sbox, INP int from_switch, + INOUTP boolean * L_rr_edge_done, + INP enum e_directionality directionality, + INOUTP struct s_linked_edge **edge_list) { + int iconn, to_track, to_node, to_switch, num_conn, to_x, to_y, i; + boolean to_is_sbox; + short switch_types[2]; + + /* Original VPR */ + /* x, y coords for get_rr_node lookups */ + /* + if (CHANX == to_type) { + to_x = to_seg; + to_y = to_chan; + } else { + assert(CHANY == to_type); + to_x = to_chan; + to_y = to_seg; + } + */ + /* END */ + /* mrFPGA : Xifan TANG*/ + if ((is_stack ? CHANY : CHANX) == to_type) { + to_x = to_seg; + to_y = to_chan; + } else { + assert((is_stack ? CHANX : CHANY) == to_type); + to_x = to_chan; + to_y = to_seg; + } + /* END */ + + /* Go through the list of tracks we can connect to */ + num_conn = 0; + for (iconn = 0; iconn < conn_tracks.nelem; ++iconn) { + to_track = conn_tracks.list[iconn]; + to_node = get_rr_node_index(to_x, to_y, to_type, to_track, + L_rr_node_indices); + + /* Skip edge if already done */ + if (L_rr_edge_done[to_node]) { + continue; + } + + /* Get the switches for any edges between the two tracks */ + to_switch = seg_details[to_track].wire_switch; + + to_is_sbox = is_sbox(to_chan, to_seg, to_sb, to_track, seg_details, + directionality); + get_switch_type(from_is_sbox, to_is_sbox, from_switch, to_switch, + switch_types); + + /* There are up to two switch edges allowed from track to track */ + for (i = 0; i < 2; ++i) { + /* If the switch_type entry is empty, skip it */ + if (OPEN == switch_types[i]) { + continue; + } + + /* Add the edge to the list */ + *edge_list = insert_in_edge_list(*edge_list, to_node, + switch_types[i]); + /* Mark the edge as now done */ + L_rr_edge_done[to_node] = TRUE; + ++num_conn; + } + } + + return num_conn; +} + +static int get_unidir_track_to_chan_seg(INP boolean is_end_sb, + INP int from_track, INP int to_chan, INP int to_seg, INP int to_sb, + INP t_rr_type to_type, INP int nodes_per_chan, INP int L_nx, + INP int L_ny, INP enum e_side from_side, INP enum e_side to_side, + INP int Fs_per_side, INP int *opin_mux_size, + INP short *****sblock_pattern, INP t_ivec *** L_rr_node_indices, + INP t_seg_details * seg_details, INOUTP boolean * L_rr_edge_done, + OUTP boolean * Fs_clipped, INOUTP struct s_linked_edge **edge_list) { + int to_track, to_mux, to_node, to_x, to_y, i, max_len, num_labels; + int sb_x, sb_y, count; + int *mux_labels = NULL; + enum e_direction to_dir; + boolean is_fringe, is_core, is_corner, is_straight; + + /* x, y coords for get_rr_node lookups */ + /* Original VPR */ + /* + if (CHANX == to_type) { + to_x = to_seg; + to_y = to_chan; + sb_x = to_sb; + sb_y = to_chan; + max_len = L_nx; + } else { + assert(CHANY == to_type); + to_x = to_chan; + to_y = to_seg; + sb_x = to_chan; + sb_y = to_sb; + max_len = L_ny; + } + */ + /* end */ + /* mrFPGA: Xifan TANG*/ + if ((is_stack ? CHANY : CHANX) == to_type) { + to_x = to_seg; + to_y = to_chan; + sb_x = to_sb; + sb_y = to_chan; + max_len = L_nx; + } else { + assert((is_stack ? CHANX : CHANY) == to_type); + to_x = to_chan; + to_y = to_seg; + sb_x = to_chan; + sb_y = to_sb; + max_len = L_ny; + } + /* end */ + + to_dir = DEC_DIRECTION; + if (to_sb < to_seg) { + to_dir = INC_DIRECTION; + } + + *Fs_clipped = FALSE; + + /* SBs go from (0, 0) to (nx, ny) */ + is_corner = (boolean)(((sb_x < 1) || (sb_x >= L_nx)) + && ((sb_y < 1) || (sb_y >= L_ny))); + is_fringe = (boolean)((FALSE == is_corner) + && ((sb_x < 1) || (sb_y < 1) || (sb_x >= L_nx) || (sb_y >= L_ny))); + is_core = (boolean)((FALSE == is_corner) && (FALSE == is_fringe)); + is_straight = (boolean)((from_side == RIGHT && to_side == LEFT) + || (from_side == LEFT && to_side == RIGHT) + || (from_side == TOP && to_side == BOTTOM) + || (from_side == BOTTOM && to_side == TOP)); + + /* Ending wires use N-to-N mapping if not fringe or if goes straight */ + if (is_end_sb && (is_core || is_corner || is_straight)) { + /* Get the list of possible muxes for the N-to-N mapping. */ + mux_labels = label_wire_muxes(to_chan, to_seg, seg_details, max_len, + to_dir, nodes_per_chan, &num_labels); + } else { + assert(is_fringe || !is_end_sb); + + mux_labels = label_wire_muxes_for_balance(to_chan, to_seg, seg_details, + max_len, to_dir, nodes_per_chan, &num_labels, to_type, + opin_mux_size, L_rr_node_indices); + } + + /* Can't connect if no muxes. */ + if (num_labels < 1) { + if (mux_labels) { + free(mux_labels); + mux_labels = NULL; + } + return 0; + } + + /* Check if Fs demand was too high. */ + if (Fs_per_side > num_labels) { + *Fs_clipped = TRUE; + } + + /* Get the target label */ + to_mux = sblock_pattern[sb_x][sb_y][from_side][to_side][from_track]; + assert(to_mux != UN_SET); + + /* Handle Fs > 3 but assigning consecutive muxes. */ + count = 0; + for (i = 0; i < Fs_per_side; ++i) { + /* Use the balanced labeling for passing and fringe wires */ + to_track = mux_labels[(to_mux + i) % num_labels]; + to_node = get_rr_node_index(to_x, to_y, to_type, to_track, + L_rr_node_indices); + + /* Add edge to list. */ + if (FALSE == L_rr_edge_done[to_node]) { + L_rr_edge_done[to_node] = TRUE; + *edge_list = insert_in_edge_list(*edge_list, to_node, + seg_details[to_track].wire_switch); + ++count; + } + } + + if (mux_labels) { + free(mux_labels); + mux_labels = NULL; + } + + return count; +} + +boolean is_sbox(INP int chan, INP int wire_seg, INP int sb_seg, INP int track, + INP t_seg_details * seg_details, + INP enum e_directionality directionality) { + + int length, ofs, fac; + + fac = 1; + if (UNI_DIRECTIONAL == directionality) { + fac = 2; + } + + length = seg_details[track].length; + + /* Make sure they gave us correct start */ + wire_seg = get_seg_start(seg_details, track, chan, wire_seg); + + /* original VPR */ + /* Ofset 0 is behind us, so add 1 */ + /* ofs = sb_seg - wire_seg + 1; */ + /* end */ + + /* mrFPGA: Xifan TANG */ + ofs = sb_seg - wire_seg + (is_stack ? 0 : 1); + /* end */ + + assert(ofs >= 0); + assert(ofs < (length + 1)); + + /* If unidir segment that is going backwards, we need to flip the ofs */ + if ((ofs % fac) > 0) { + ofs = length - ofs; + } + + return seg_details[track].sb[ofs]; +} + +static void get_switch_type(boolean is_from_sbox, boolean is_to_sbox, + short from_node_switch, short to_node_switch, short switch_types[2]) { + /* This routine looks at whether the from_node and to_node want a switch, * + * and what type of switch is used to connect *to* each type of node * + * (from_node_switch and to_node_switch). It decides what type of switch, * + * if any, should be used to go from from_node to to_node. If no switch * + * should be inserted (i.e. no connection), it returns OPEN. Its returned * + * values are in the switch_types array. It needs to return an array * + * because one topology (a buffer in the forward direction and a pass * + * transistor in the backward direction) results in *two* switches. */ + + boolean forward_pass_trans; + boolean backward_pass_trans; + int used, min_switch, max_switch; + + /* mrFPGA: Xifan TANG */ + if (is_mrFPGA) { + get_mrfpga_switch_type(is_from_sbox, is_to_sbox, from_node_switch, + to_node_switch, switch_types); + return; + } + /* end */ + + switch_types[0] = OPEN; /* No switch */ + switch_types[1] = OPEN; + used = 0; + forward_pass_trans = FALSE; + backward_pass_trans = FALSE; + + /* Connect forward if we are a sbox */ + if (is_from_sbox) { + switch_types[used] = to_node_switch; + if (FALSE == switch_inf[to_node_switch].buffered) { + forward_pass_trans = TRUE; + } + ++used; + } + + /* Check for pass_trans coming backwards */ + if (is_to_sbox) { + if (FALSE == switch_inf[from_node_switch].buffered) { + switch_types[used] = from_node_switch; + backward_pass_trans = TRUE; + ++used; + } + } + + /* Take the larger pass trans if there are two */ + if (forward_pass_trans && backward_pass_trans) { + min_switch = std::min(to_node_switch, from_node_switch); + max_switch = std::max(to_node_switch, from_node_switch); + + /* Take the smaller index unless the other + * pass_trans is bigger (smaller R). */ + switch_types[used] = min_switch; + if (switch_inf[max_switch].R < switch_inf[min_switch].R) { + switch_types[used] = max_switch; + } + ++used; + } +} + +static int vpr_to_phy_track(INP int itrack, INP int chan_num, INP int seg_num, + INP t_seg_details * seg_details, + INP enum e_directionality directionality) { + int group_start, group_size; + int vpr_offset_for_first_phy_track; + int vpr_offset, phy_offset; + int phy_track; + int fac; + + /* Assign in pairs if unidir. */ + fac = 1; + if (UNI_DIRECTIONAL == directionality) { + fac = 2; + } + + group_start = seg_details[itrack].group_start; + group_size = seg_details[itrack].group_size; + + vpr_offset_for_first_phy_track = (chan_num + seg_num - 1) + % (group_size / fac); + vpr_offset = (itrack - group_start) / fac; + phy_offset = (vpr_offset_for_first_phy_track + vpr_offset) + % (group_size / fac); + phy_track = group_start + (fac * phy_offset) + (itrack - group_start) % fac; + + return phy_track; +} + +short ***** +alloc_sblock_pattern_lookup(INP int L_nx, INP int L_ny, INP int nodes_per_chan) { + int i, j, from_side, to_side, itrack, items; + short *****result; + short *****i_list; + short ****j_list; + short ***from_list; + short **to_list; + short *track_list; + + /* loading up the sblock connection pattern matrix. It's a huge matrix because + * for nonquantized W, it's impossible to make simple permutations to figure out + * where muxes are and how to connect to them such that their sizes are balanced */ + + /* Do chunked allocations to make freeing easier, speed up malloc and free, and + * reduce some of the memory overhead. Could use fewer malloc's but this way + * avoids all considerations of pointer sizes and allignment. */ + + /* Alloc each list of pointers in one go. items is a running product that increases + * with each new dimension of the matrix. */ + items = 1; + items *= (L_nx + 1); + i_list = (short *****) my_malloc(sizeof(short ****) * items); + items *= (L_ny + 1); + j_list = (short ****) my_malloc(sizeof(short ***) * items); + items *= (4); + from_list = (short ***) my_malloc(sizeof(short **) * items); + items *= (4); + to_list = (short **) my_malloc(sizeof(short *) * items); + items *= (nodes_per_chan); + track_list = (short *) my_malloc(sizeof(short) * items); + + /* Build the pointer lists to form the multidimensional array */ + result = i_list; + i_list += (L_nx + 1); /* Skip forward nx+1 items */ + for (i = 0; i < (L_nx + 1); ++i) { + + result[i] = j_list; + j_list += (L_ny + 1); /* Skip forward ny+1 items */ + for (j = 0; j < (L_ny + 1); ++j) { + + result[i][j] = from_list; + from_list += (4); /* Skip forward 4 items */ + for (from_side = 0; from_side < 4; ++from_side) { + + result[i][j][from_side] = to_list; + to_list += (4); /* Skip forward 4 items */ + for (to_side = 0; to_side < 4; ++to_side) { + + result[i][j][from_side][to_side] = track_list; + track_list += (nodes_per_chan); /* Skip forward nodes_per_chan items */ + for (itrack = 0; itrack < nodes_per_chan; itrack++) { + + /* Set initial value to be unset */ + result[i][j][from_side][to_side][itrack] = UN_SET; + } + } + } + } + } + + /* This is the outer pointer to the full matrix */ + return result; +} + +void free_sblock_pattern_lookup(INOUTP short *****sblock_pattern) { + /* This free function corresponds to the chunked matrix + * allocation above and there should only be one free + * call for each dimension. */ + + /* Free dimensions from the inner one, outwards so + * we can still access them. The comments beside + * each one indicate the corresponding name used when + * allocating them. */ + free(****sblock_pattern); /* track_list */ + free(***sblock_pattern); /* to_list */ + free(**sblock_pattern); /* from_list */ + free(*sblock_pattern); /* j_list */ + free(sblock_pattern); /* i_list */ +} + +void load_sblock_pattern_lookup(INP int i, INP int j, INP int nodes_per_chan, + INP t_seg_details * seg_details, INP int Fs, + INP enum e_switch_block_type switch_block_type, + INOUTP short *****sblock_pattern) { + + /* This routine loads a lookup table for sblock topology. The lookup table is huge + * because the sblock varies from location to location. The i, j means the owning + * location of the sblock under investigation. */ + + int side_cw_incoming_wire_count, side_ccw_incoming_wire_count, + opp_incoming_wire_count; + int to_side, side, side_cw, side_ccw, side_opp, itrack; + int Fs_per_side, chan, seg, chan_len, sb_seg; + boolean is_core_sblock, is_corner_sblock, x_edge, y_edge; + int *incoming_wire_label[4]; + int *wire_mux_on_track[4]; + int num_incoming_wires[4]; + int num_ending_wires[4]; + int num_wire_muxes[4]; + boolean skip, vert, pos_dir; + enum e_direction dir; + + Fs_per_side = 1; + if (Fs != -1) { + Fs_per_side = Fs / 3; + } + + /* SB's have coords from (0, 0) to (nx, ny) */ + assert(i >= 0); + assert(i <= nx); + assert(j >= 0); + assert(j <= ny); + + /* May 12 - 15, 2007 + * + * I identify three types of sblocks in the chip: 1) The core sblock, whose special + * property is that the number of muxes (and ending wires) on each side is the same (very useful + * property, since it leads to a N-to-N assignment problem with ending wires). 2) The corner sblock + * which is same as a L=1 core sblock with 2 sides only (again N-to-N assignment problem). 3) The + * fringe / chip edge sblock which is most troublesome, as balance in each side of muxes is + * attainable but balance in the entire sblock is not. The following code first identifies the + * incoming wires, which can be classified into incoming passing wires with sbox and incoming + * ending wires (the word "incoming" is sometimes dropped for ease of discussion). It appropriately + * labels all the wires on each side by the following order: By the call to label_incoming_wires, + * which labels for one side, the order is such that the incoming ending wires (always with sbox) + * are labelled first 0,1,2,... p-1, then the incoming passing wires with sbox are labelled + * p,p+1,p+2,... k-1 (for total of k). By this convention, one can easily distinguish the ending + * wires from the passing wires by checking a label against num_ending_wires variable. + * + * After labelling all the incoming wires, this routine labels the muxes on the side we're currently + * connecting to (iterated for four sides of the sblock), called the to_side. The label scheme is + * the natural order of the muxes by their track #. Also we find the number of muxes. + * + * For each to_side, the total incoming wires that connect to the muxes on to_side + * come from three sides: side_1 (to_side's right), side_2 (to_side's left) and opp_side. + * The problem of balancing mux size is then: considering all incoming passing wires + * with sbox on side_1, side_2 and opp_side, how to assign them to the muxes on to_side + * (with specified Fs) in a way that mux size is imbalanced by at most 1. I solve this + * problem by this approach: the first incoming passing wire will connect to 0, 1, 2, + * ..., Fs_per_side - 1, then the next incoming passing wire will connect to + * Fs_per_side, Fs_per_side+1, ..., Fs_per_side*2-1, and so on. This consistent STAGGERING + * ensures N-to-N assignment is perfectly balanced and M-to-N assignment is imbalanced by no + * more than 1. + * + * For the sblock_pattern_init_mux_lookup lookup table, I will only need the lookup + * table to remember the first/init mux to connect, since the convention is Fs_per_side consecutive + * muxes to connect. Then how do I determine the order of the incoming wires? I use the labels + * on side_1, then labels on side_2, then labels on opp_side. Effectively I listed all + * incoming passing wires from the three sides, and order them to each make Fs_per_side + * consecutive connections to muxes, and use % to rotate to keep imbalance at most 1. + */ + + /* SB's range from (0, 0) to (nx, ny) */ + /* First find all four sides' incoming wires */ + x_edge = (boolean)((i < 1) || (i >= nx)); + y_edge = (boolean)((j < 1) || (j >= ny)); + + is_corner_sblock = (boolean)(x_edge && y_edge); + is_core_sblock = (boolean)(!x_edge && !y_edge); + + /* "Label" the wires around the switch block by connectivity. */ + for (side = 0; side < 4; ++side) { + /* Assume the channel segment doesn't exist. */ + wire_mux_on_track[side] = NULL; + incoming_wire_label[side] = NULL; + num_incoming_wires[side] = 0; + num_ending_wires[side] = 0; + num_wire_muxes[side] = 0; + + /* Skip the side and leave the zero'd value if the + * channel segment doesn't exist. */ + skip = TRUE; + switch (side) { + /* Original VPR */ + /* + case TOP: + if (j < ny) { + skip = FALSE; + } + ; + break; + case RIGHT: + if (i < nx) { + skip = FALSE; + } + break; + case BOTTOM: + if (j > 0) { + skip = FALSE; + } + break; + case LEFT: + if (i > 0) { + skip = FALSE; + } + break; + } + */ + /* end */ + /* mrFPGA : Xifan TANG*/ + case TOP: + if (j < (is_stack ? ny+1 : ny)) { + skip = FALSE; + } + ; + break; + case RIGHT: + if (i < (is_stack ? nx+1 : nx)) { + skip = FALSE; + } + break; + case BOTTOM: + if (j > 0) { + skip = FALSE; + } + break; + case LEFT: + if (i > 0) { + skip = FALSE; + } + break; + } + /* end */ + if (skip) { + continue; + } + + /* Figure out the channel and segment for a certain direction */ + vert = (boolean) ((side == TOP) || (side == BOTTOM)); + pos_dir = (boolean) ((side == TOP) || (side == RIGHT)); + chan = (vert ? i : j); + sb_seg = (vert ? j : i); + /* Original VPR */ + /* seg = (pos_dir ? (sb_seg + 1) : sb_seg); */ + /* end */ + /* mrFPGA : Xifan TANG*/ + seg = (pos_dir ? (sb_seg + 1) : sb_seg) - (is_stack ? 1 : 0); + /* end */ + chan_len = (vert ? ny : nx); + + /* Figure out all the tracks on a side that are ending and the + * ones that are passing through and have a SB. */ + dir = (pos_dir ? DEC_DIRECTION : INC_DIRECTION); + incoming_wire_label[side] = label_incoming_wires(chan, seg, sb_seg, + seg_details, chan_len, dir, nodes_per_chan, + &num_incoming_wires[side], &num_ending_wires[side]); + + /* Figure out all the tracks on a side that are starting. */ + dir = (pos_dir ? INC_DIRECTION : DEC_DIRECTION); + wire_mux_on_track[side] = label_wire_muxes(chan, seg, seg_details, + chan_len, dir, nodes_per_chan, &num_wire_muxes[side]); + } + + for (to_side = 0; to_side < 4; to_side++) { + /* Can't do anything if no muxes on this side. */ + if (0 == num_wire_muxes[to_side]) { + continue; + } + + /* Figure out side rotations */ + assert((TOP == 0) && (RIGHT == 1) && (BOTTOM == 2) && (LEFT == 3)); + side_cw = (to_side + 1) % 4; + side_opp = (to_side + 2) % 4; + side_ccw = (to_side + 3) % 4; + + /* For the core sblock: + * The new order for passing wires should appear as + * 0,1,2..,scw-1, for passing wires with sbox on side_cw + * scw,scw+1,...,sccw-1, for passing wires with sbox on side_ccw + * sccw,sccw+1,... for passing wires with sbox on side_opp. + * This way, I can keep the imbalance to at most 1. + * + * For the fringe sblocks, I don't distinguish between + * passing and ending wires so the above statement still holds + * if you replace "passing" by "incoming" */ + + side_cw_incoming_wire_count = 0; + if (incoming_wire_label[side_cw]) { + for (itrack = 0; itrack < nodes_per_chan; itrack++) { + /* Ending wire, or passing wire with sbox. */ + if (incoming_wire_label[side_cw][itrack] != UN_SET) { + + if ((is_corner_sblock || is_core_sblock) + && (incoming_wire_label[side_cw][itrack] + < num_ending_wires[side_cw])) { + /* The ending wires in core sblocks form N-to-N assignment + * problem, so can use any pattern such as Wilton. This N-to-N + * mapping depends on the fact that start points stagger across + * channels. */ + assert( + num_ending_wires[side_cw] == num_wire_muxes[to_side]); + sblock_pattern[i][j][side_cw][to_side][itrack] = + get_simple_switch_block_track((enum e_side)side_cw, (enum e_side)to_side, + incoming_wire_label[side_cw][itrack], + switch_block_type, + num_wire_muxes[to_side]); + + } else { + + /* These are passing wires with sbox only for core sblocks + * or passing and ending wires (for fringe cases). */ + sblock_pattern[i][j][side_cw][to_side][itrack] = + (side_cw_incoming_wire_count * Fs_per_side) + % num_wire_muxes[to_side]; + side_cw_incoming_wire_count++; + } + } + } + } + + side_ccw_incoming_wire_count = 0; + for (itrack = 0; itrack < nodes_per_chan; itrack++) { + + /* if that side has no channel segment skip it */ + if (incoming_wire_label[side_ccw] == NULL) + break; + + /* not ending wire nor passing wire with sbox */ + if (incoming_wire_label[side_ccw][itrack] != UN_SET) { + + if ((is_corner_sblock || is_core_sblock) + && (incoming_wire_label[side_ccw][itrack] + < num_ending_wires[side_ccw])) { + /* The ending wires in core sblocks form N-to-N assignment problem, so can + * use any pattern such as Wilton */ + assert( + incoming_wire_label[side_ccw] [itrack] < num_wire_muxes[to_side]); + sblock_pattern[i][j][side_ccw][to_side][itrack] = + get_simple_switch_block_track((enum e_side)side_ccw, (enum e_side)to_side, + incoming_wire_label[side_ccw][itrack], + switch_block_type, num_wire_muxes[to_side]); + } else { + + /* These are passing wires with sbox only for core sblocks + * or passing and ending wires (for fringe cases). */ + sblock_pattern[i][j][side_ccw][to_side][itrack] = + ((side_ccw_incoming_wire_count + + side_cw_incoming_wire_count) * Fs_per_side) + % num_wire_muxes[to_side]; + side_ccw_incoming_wire_count++; + } + } + } + + opp_incoming_wire_count = 0; + if (incoming_wire_label[side_opp]) { + for (itrack = 0; itrack < nodes_per_chan; itrack++) { + /* not ending wire nor passing wire with sbox */ + if (incoming_wire_label[side_opp][itrack] != UN_SET) { + + /* corner sblocks for sure have no opposite channel segments so don't care about them */ + if (is_core_sblock) { + if (incoming_wire_label[side_opp][itrack] + < num_ending_wires[side_opp]) { + /* The ending wires in core sblocks form N-to-N assignment problem, so can + * use any pattern such as Wilton */ + /* In the direct connect case, I know for sure the init mux is at the same track # + * as this ending wire, but still need to find the init mux label for Fs > 3 */ + sblock_pattern[i][j][side_opp][to_side][itrack] = + find_label_of_track( + wire_mux_on_track[to_side], + num_wire_muxes[to_side], itrack); + } else { + /* These are passing wires with sbox for core sblocks */ + sblock_pattern[i][j][side_opp][to_side][itrack] = + ((side_ccw_incoming_wire_count + + side_cw_incoming_wire_count) + * Fs_per_side + + opp_incoming_wire_count + * (Fs_per_side - 1)) + % num_wire_muxes[to_side]; + opp_incoming_wire_count++; + } + } else { + if (incoming_wire_label[side_opp][itrack] + < num_ending_wires[side_opp]) { + sblock_pattern[i][j][side_opp][to_side][itrack] = + find_label_of_track( + wire_mux_on_track[to_side], + num_wire_muxes[to_side], itrack); + } else { + /* These are passing wires with sbox for fringe sblocks */ + sblock_pattern[i][j][side_opp][to_side][itrack] = + ((side_ccw_incoming_wire_count + + side_cw_incoming_wire_count) + * Fs_per_side + + opp_incoming_wire_count + * (Fs_per_side - 1)) + % num_wire_muxes[to_side]; + opp_incoming_wire_count++; + } + } + } + } + } + } + + for (side = 0; side < 4; ++side) { + if (incoming_wire_label[side]) { + free(incoming_wire_label[side]); + } + if (wire_mux_on_track[side]) { + free(wire_mux_on_track[side]); + } + } +} + +static int * +label_wire_muxes_for_balance(INP int chan_num, INP int seg_num, + INP t_seg_details * seg_details, INP int max_len, + INP enum e_direction direction, INP int nodes_per_chan, + INP int *num_wire_muxes, INP t_rr_type chan_type, + INP int *opin_mux_size, INP t_ivec *** L_rr_node_indices) { + + /* Labels the muxes on that side (seg_num, chan_num, direction). The returned array + * maps a label to the actual track #: array[0] = */ + + /* Sblock (aka wire2mux) pattern generation occurs after opin2mux connections have been + * made. Since opin2muxes are done with a pattern with which I guarantee imbalance of at most 1 due + * to them, we will observe that, for each side of an sblock some muxes have one fewer size + * than the others, considering only the contribution from opins. I refer to these muxes as "holes" + * as they have one fewer opin connection going to them than the rest (like missing one electron)*/ + + /* Before May 14, I was labelling wire muxes in the natural order of their track # (lowest first). + * Now I want to label wire muxes like this: first label the holes in order of their track #, + * then label the non-holes in order of their track #. This way the wire2mux generation will + * not overlap its own "holes" with the opin "holes", thus creating imbalance greater than 1. */ + + /* The best approach in sblock generation is do one assignment of all incoming wires from 3 other + * sides to the muxes on the fourth side, connecting the "opin hole" muxes first (i.e. filling + * the holes) then the rest -> this means after all opin2mux and wire2mux connections the + * mux size imbalance on one side is at most 1. The mux size imbalance in one sblock is thus + * also one, since the number of muxes per side is identical for all four sides, and they number + * of incoming wires per side is identical for full pop, and almost the same for depop (due to + * staggering) within +1 or -1. For different tiles (different sblocks) the imbalance is irrelevant, + * since if the tiles are different in mux count then they have to be designed with a different + * physical tile. */ + + int num_labels, max_opin_mux_size, min_opin_mux_size; + int inode, i, j, x, y; + int *pre_labels, *final_labels; + + if (chan_type == CHANX) { + x = seg_num; + y = chan_num; + } else if (chan_type == CHANY) { + x = chan_num; + y = seg_num; + } else { + vpr_printf(TIO_MESSAGE_ERROR, "Bad channel type (%d).\n", chan_type); + exit(1); + } + + /* Generate the normal labels list as the baseline. */ + pre_labels = label_wire_muxes(chan_num, seg_num, seg_details, max_len, + direction, nodes_per_chan, &num_labels); + + /* Find the min and max mux size. */ + min_opin_mux_size = MAX_SHORT; + max_opin_mux_size = 0; + for (i = 0; i < num_labels; ++i) { + inode = get_rr_node_index(x, y, chan_type, pre_labels[i], + L_rr_node_indices); + if (opin_mux_size[inode] < min_opin_mux_size) { + min_opin_mux_size = opin_mux_size[inode]; + } + if (opin_mux_size[inode] > max_opin_mux_size) { + max_opin_mux_size = opin_mux_size[inode]; + } + } + if (max_opin_mux_size > (min_opin_mux_size + 1)) { + vpr_printf(TIO_MESSAGE_ERROR, "opin muxes are not balanced!\n"); + vpr_printf(TIO_MESSAGE_ERROR, "max_opin_mux_size %d min_opin_mux_size %d chan_type %d x %d y %d\n", + max_opin_mux_size, min_opin_mux_size, chan_type, x, y); + exit(1); + } + + /* Create a new list that we will move the muxes with 'holes' to the start of list. */ + final_labels = (int *) my_malloc(sizeof(int) * num_labels); + j = 0; + for (i = 0; i < num_labels; ++i) { + inode = pre_labels[i]; + if (opin_mux_size[inode] < max_opin_mux_size) { + final_labels[j] = inode; + ++j; + } + } + for (i = 0; i < num_labels; ++i) { + inode = pre_labels[i]; + if (opin_mux_size[inode] >= max_opin_mux_size) { + final_labels[j] = inode; + ++j; + } + } + + /* Free the baseline labelling. */ + if (pre_labels) { + free(pre_labels); + pre_labels = NULL; + } + + *num_wire_muxes = num_labels; + return final_labels; +} + +static int * +label_wire_muxes(INP int chan_num, INP int seg_num, + INP t_seg_details * seg_details, INP int max_len, + INP enum e_direction dir, INP int nodes_per_chan, + OUTP int *num_wire_muxes) { + + /* Labels the muxes on that side (seg_num, chan_num, direction). The returned array + * maps a label to the actual track #: array[0] = + * This routine orders wire muxes by their natural order, i.e. track # */ + + int itrack, start, end, num_labels, pass; + int *labels = NULL; + boolean is_endpoint; + + /* COUNT pass then a LOAD pass */ + num_labels = 0; + for (pass = 0; pass < 2; ++pass) { + /* Alloc the list on LOAD pass */ + if (pass > 0) { + labels = (int *) my_malloc(sizeof(int) * num_labels); + num_labels = 0; + } + + /* Find the tracks that are starting. */ + for (itrack = 0; itrack < nodes_per_chan; ++itrack) { + start = get_seg_start(seg_details, itrack, chan_num, seg_num); + end = get_seg_end(seg_details, itrack, start, chan_num, max_len); + + /* Skip tracks going the wrong way */ + if (seg_details[itrack].direction != dir) { + continue; + } + + /* Determine if we are a wire startpoint */ + is_endpoint = (boolean)(seg_num == start); + if (DEC_DIRECTION == seg_details[itrack].direction) { + is_endpoint = (boolean)(seg_num == end); + } + + /* Count the labels and load if LOAD pass */ + if (is_endpoint) { + if (pass > 0) { + labels[num_labels] = itrack; + } + ++num_labels; + } + } + } + + *num_wire_muxes = num_labels; + return labels; +} + +static int * +label_incoming_wires(INP int chan_num, INP int seg_num, INP int sb_seg, + INP t_seg_details * seg_details, INP int max_len, + INP enum e_direction dir, INP int nodes_per_chan, + OUTP int *num_incoming_wires, OUTP int *num_ending_wires) { + + /* Labels the incoming wires on that side (seg_num, chan_num, direction). + * The returned array maps a track # to a label: array[0] = , + * the labels 0,1,2,.. identify consecutive incoming wires that have sbox (passing wires with sbox and ending wires) */ + + int itrack, start, end, i, num_passing, num_ending, pass; + int *labels; + boolean sbox_exists, is_endpoint; + + /* Alloc the list of labels for the tracks */ + labels = (int *) my_malloc(nodes_per_chan * sizeof(int)); + for (i = 0; i < nodes_per_chan; ++i) { + labels[i] = UN_SET; /* crash hard if unset */ + } + + num_ending = 0; + num_passing = 0; + for (pass = 0; pass < 2; ++pass) { + for (itrack = 0; itrack < nodes_per_chan; ++itrack) { + if (seg_details[itrack].direction == dir) { + start = get_seg_start(seg_details, itrack, chan_num, seg_num); + end = get_seg_end(seg_details, itrack, start, chan_num, + max_len); + + /* Determine if we are a wire endpoint */ + is_endpoint = (boolean)(seg_num == end); + if (DEC_DIRECTION == seg_details[itrack].direction) { + is_endpoint = (boolean)(seg_num == start); + } + + /* Determine if we have a sbox on the wire */ + sbox_exists = is_sbox(chan_num, seg_num, sb_seg, itrack, + seg_details, UNI_DIRECTIONAL); + + switch (pass) { + /* On first pass, only load ending wire labels. */ + case 0: + if (is_endpoint) { + labels[itrack] = num_ending; + ++num_ending; + } + break; + + /* On second pass, load the passing wire labels. They + * will follow after the ending wire labels. */ + case 1: + if ((FALSE == is_endpoint) && sbox_exists) { + labels[itrack] = num_ending + num_passing; + ++num_passing; + } + break; + } + } + } + } + + *num_incoming_wires = num_passing + num_ending; + *num_ending_wires = num_ending; + return labels; +} + +static int find_label_of_track(int *wire_mux_on_track, int num_wire_muxes, + int from_track) { + int i; + + /* Returns the index/label in array wire_mux_on_track whose entry equals from_track. If none are + * found, then returns the index of the entry whose value is the largest */ + + for (i = 0; i < num_wire_muxes; i++) { + if (wire_mux_on_track[i] == from_track) { + return i; /* matched, return now */ + } + } + + vpr_printf(TIO_MESSAGE_ERROR, "Expected mux not found.\n"); + exit(1); +} diff --git a/vpr7_rram/vpr/SRC/route/rr_graph2.h b/vpr7_rram/vpr/SRC/route/rr_graph2.h new file mode 100755 index 000000000..132c0dea4 --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/rr_graph2.h @@ -0,0 +1,122 @@ +#ifndef RR_GRAPH2_H +#define RR_GRAPH2_H + +/************** Global variables shared only by the rr_* modules. ************/ + +extern boolean *rr_edge_done; /* [0..num_rr_nodes-1]. Used to keep track * + * of whether or not a node has been put in * + * an edge list yet. TRUE if a node is already listed in the edges array * + * that's being constructed. Ensure that there are no duplicate edges. */ + +/******************* Subroutines exported by rr_graph2.c *********************/ + +struct s_ivec ***alloc_and_load_rr_node_indices(INP int nodes_per_chan, + INP int L_nx, + INP int L_ny, + INOUTP int *index, + INP t_seg_details * seg_details) ; + +void free_rr_node_indices(INP t_ivec *** L_rr_node_indices); + +int get_rr_node_index(int x, int y, t_rr_type rr_type, int ptc, + t_ivec *** L_rr_node_indices); + +void free_seg_details(t_seg_details * seg_details, int nodes_per_chan); + +t_seg_details *alloc_and_load_seg_details(INOUTP int *nodes_per_chan, + INP int max_len, + INP int num_seg_types, + INP t_segment_inf * segment_inf, + INP boolean use_full_seg_groups, + INP boolean is_global_graph, + INP enum e_directionality + directionality); + +void dump_seg_details(t_seg_details * seg_details, int nodes_per_chan, + const char *fname); + +int get_seg_start(INP t_seg_details * seg_details, + INP int itrack, + INP int chan_num, + INP int seg_num); + +int get_seg_end(INP t_seg_details * seg_details, + INP int itrack, + INP int istart, + INP int chan_num, + INP int seg_max); + +boolean is_cbox(INP int chan, + INP int seg, + INP int track, + INP t_seg_details * seg_details, + INP enum e_directionality directionality); + +boolean is_sbox(INP int chan, + INP int wire_seg, + INP int sb_seg, + INP int track, + INP t_seg_details * seg_details, + INP enum e_directionality directionality); + +int get_bidir_opin_connections(INP int i, + INP int j, + INP int ipin, + INP struct s_linked_edge **edge_list, + INP int *****opin_to_track_map, + INP int Fc, + INP boolean * L_rr_edge_done, + INP t_ivec *** L_rr_node_indices, + INP t_seg_details * seg_details); + +int get_unidir_opin_connections(INP int chan, + INP int seg, + INP int Fc, + INP t_rr_type chan_type, + INP t_seg_details * seg_details, + INOUTP t_linked_edge ** edge_list_ptr, + INOUTP int **Fc_ofs, + INOUTP boolean * L_rr_edge_done, + INP int max_len, + INP int nodes_per_chan, + INP t_ivec *** L_rr_node_indices, + OUTP boolean * Fc_clipped); + +int get_track_to_ipins(int seg, int chan, int track, + t_linked_edge ** edge_list_ptr, t_ivec *** L_rr_node_indices, + struct s_ivec ****track_to_ipin_lookup, t_seg_details * seg_details, + enum e_rr_type chan_type, int chan_length, int wire_to_ipin_switch, + enum e_directionality directionality); + +int get_track_to_tracks(INP int from_chan, + INP int from_seg, + INP int from_track, + INP t_rr_type from_type, + INP int to_seg, + INP t_rr_type to_type, + INP int chan_len, + INP int nodes_per_chan, + INP int *opin_mux_size, + INP int Fs_per_side, + INP short *****sblock_pattern, + INOUTP struct s_linked_edge **edge_list, + INP t_seg_details * seg_details, + INP enum e_directionality directionality, + INP t_ivec *** L_rr_node_indices, + INOUTP boolean * L_rr_edge_done, + INP struct s_ivec ***switch_block_conn); + +short *****alloc_sblock_pattern_lookup(INP int L_nx, + INP int L_ny, + INP int nodes_per_chan); +void free_sblock_pattern_lookup(INOUTP short *****sblock_pattern); +void load_sblock_pattern_lookup(INP int i, + INP int j, + INP int nodes_per_chan, + INP t_seg_details * seg_details, + INP int Fs, + INP enum e_switch_block_type switch_block_type, + INOUTP short *****sblock_pattern); + +#endif + diff --git a/vpr7_rram/vpr/SRC/route/rr_graph_area.c b/vpr7_rram/vpr/SRC/route/rr_graph_area.c new file mode 100755 index 000000000..254ec5712 --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/rr_graph_area.c @@ -0,0 +1,733 @@ +#include +#include +#include "util.h" +#include "vpr_types.h" +#include +#include "globals.h" +#include "rr_graph_util.h" +#include "rr_graph_area.h" + +/* Some useful subroutines in Spice utils*/ +int determine_tree_mux_level(int mux_size); +int determine_num_input_basis_multilevel_mux(int mux_size, int mux_level); + +/************************ Subroutines local to this module *******************/ + +static void count_bidir_routing_transistors(int num_switch, float R_minW_nmos, + float R_minW_pmos, float sram_area); + +static void count_unidir_routing_transistors(t_segment_inf * segment_inf, + float R_minW_nmos, float R_minW_pmos, float sram_area); + +static float get_cblock_trans(int *num_inputs_to_cblock, int* switches_to_cblock, + int max_inputs_to_cblock, float trans_cblock_to_lblock_buf, + float trans_sram_bit); + +static float *alloc_and_load_unsharable_switch_trans(int num_switch, + float trans_sram_bit, float R_minW_nmos); + +static float *alloc_and_load_sharable_switch_trans(int num_switch, + float trans_sram_bit, float R_minW_nmos, float R_minW_pmos); + +/* mrFPGA: Xifan TANG*/ +//static +//float trans_per_buf(float Rbuf, float R_minW_nmos, float R_minW_pmos); +/*end */ + +static float trans_per_mux(int num_inputs, float trans_sram_bit, + float pass_trans_area, t_switch_inf target_switch); + +static float trans_per_R(float Rtrans, float R_minW_trans); + +/*************************** Subroutine definitions **************************/ + +void count_routing_transistors(enum e_directionality directionality, + int num_switch, t_segment_inf * segment_inf, float R_minW_nmos, + float R_minW_pmos, float sram_area) { + + /* Counts how many transistors are needed to implement the FPGA routing * + * resources. Call this only when an rr_graph exists. It does not count * + * the transistors used in logic blocks, but it counts the transistors in * + * the input connection block multiplexers and in the output pin drivers and * + * pass transistors. NB: this routine assumes pass transistors always * + * generate two edges (one forward, one backward) between two nodes. * + * Physically, this is what happens -- make sure your rr_graph does it. * + * * + * I assume a minimum width transistor takes 1 unit of area. A double-width * + * transistor takes the twice the diffusion width, but the same spacing, so * + * I assume it takes 1.5x the area of a minimum-width transitor. */ + if (directionality == BI_DIRECTIONAL) { + count_bidir_routing_transistors(num_switch, R_minW_nmos, R_minW_pmos, sram_area); + } else { + assert(directionality == UNI_DIRECTIONAL); + count_unidir_routing_transistors(segment_inf, R_minW_nmos, R_minW_pmos, sram_area); + } +} + +void count_bidir_routing_transistors(int num_switch, float R_minW_nmos, + float R_minW_pmos, float sram_area) { + + /* Tri-state buffers are designed as a buffer followed by a pass transistor. * + * I make Rbuffer = Rpass_transitor = 1/2 Rtri-state_buffer. * + * I make the pull-up and pull-down sides of the buffer the same strength -- * + * i.e. I make the p transistor R_minW_pmos / R_minW_nmos wider than the n * + * transistor. * + * * + * I generate two area numbers in this routine: ntrans_sharing and * + * ntrans_no_sharing. ntrans_sharing exactly reflects what the timing * + * analyzer, etc. works with -- each switch is a completely self contained * + * pass transistor or tri-state buffer. In the case of tri-state buffers * + * this is rather pessimisitic. The inverter chain part of the buffer (as * + * opposed to the pass transistor + SRAM output part) can be shared by * + * several switches in the same location. Obviously all the switches from * + * an OPIN can share one buffer. Also, CHANX and CHANY switches at the same * + * spot (i,j) on a single segment can share a buffer. For a more realistic * + * area number I assume all buffered switches from a node that are at the * + * *same (i,j) location* can share one buffer. Only the lowest resistance * + * (largest) buffer is implemented. In practice, you might want to build * + * something that is 1.5x or 2x the largest buffer, so this may be a bit * + * optimistic (but I still think it's pretty reasonable). */ + + int *num_inputs_to_cblock; /* [0..num_rr_nodes-1], but all entries not */ + /* Xifan TANG: cb switches*/ + int *switches_to_cblock; /* [0..num_rr_nodes-1], but all entries not */ + /* END */ + + /* corresponding to IPINs will be 0. */ + + boolean * cblock_counted; /* [0..max(nx,ny)] -- 0th element unused. */ + float *shared_buffer_trans; /* [0..max_nx,ny)] */ + float *unsharable_switch_trans, *sharable_switch_trans; /* [0..num_switch-1] */ + + t_rr_type from_rr_type, to_rr_type; + int from_node, to_node, iedge, num_edges, maxlen; + int iswitch, i, j, iseg, max_inputs_to_cblock; + float input_cblock_trans, shared_opin_buffer_trans; + const float trans_sram_bit = sram_area; + + /* Two variables below are the accumulator variables that add up all the * + * transistors in the routing. Make doubles so that they don't stop * + * incrementing once adding a switch makes a change of less than 1 part in * + * 10^7 to the total. If this still isn't good enough (adding 1 part in * + * 10^15 will still be thrown away), compute the transistor count in * + * "chunks", by adding up inodes 1 to 1000, 1001 to 2000 and then summing * + * the partial sums together. */ + + double ntrans_sharing, ntrans_no_sharing; + + /* Buffers from the routing to the ipin cblock inputs, and from the ipin * + * cblock outputs to the logic block, respectively. Assume minimum size n * + * transistors, and ptransistors sized to make the pull-up R = pull-down R. */ + + float trans_track_to_cblock_buf; + float trans_cblock_to_lblock_buf; + + ntrans_sharing = 0.; + ntrans_no_sharing = 0.; + max_inputs_to_cblock = 0; + + /* Assume the two buffers below are 4x minimum drive strength (enough to * + * drive a fanout of up to 16 pretty nicely -- should cover a reasonable * + * wiring C plus the fanout. */ + + trans_track_to_cblock_buf = trans_per_buf(R_minW_nmos / 4., R_minW_nmos, + R_minW_pmos); + + trans_cblock_to_lblock_buf = trans_per_buf(R_minW_nmos / 4., R_minW_nmos, + R_minW_pmos); + + num_inputs_to_cblock = (int *) my_calloc(num_rr_nodes, sizeof(int)); + + /* Xifan TANG: cb switches*/ + switches_to_cblock = (int *) my_calloc(num_rr_nodes, sizeof(int)); + for (i = 0; i < num_rr_nodes; i++) { + switches_to_cblock[i] = OPEN; + } + /* END */ + + maxlen = std::max(nx, ny) + 1; + cblock_counted = (boolean *) my_calloc(maxlen, sizeof(boolean)); + shared_buffer_trans = (float *) my_calloc(maxlen, sizeof(float)); + + unsharable_switch_trans = alloc_and_load_unsharable_switch_trans(num_switch, + trans_sram_bit, R_minW_nmos); + + sharable_switch_trans = alloc_and_load_sharable_switch_trans(num_switch, + trans_sram_bit, R_minW_nmos, R_minW_pmos); + + for (from_node = 0; from_node < num_rr_nodes; from_node++) { + + from_rr_type = rr_node[from_node].type; + + switch (from_rr_type) { + + case CHANX: + case CHANY: + num_edges = rr_node[from_node].num_edges; + + for (iedge = 0; iedge < num_edges; iedge++) { + + to_node = rr_node[from_node].edges[iedge]; + to_rr_type = rr_node[to_node].type; + + switch (to_rr_type) { + + case CHANX: + case CHANY: + iswitch = rr_node[from_node].switches[iedge]; + + if (switch_inf[iswitch].buffered) { + iseg = seg_index_of_sblock(from_node, to_node); + shared_buffer_trans[iseg] = std::max( + shared_buffer_trans[iseg], + sharable_switch_trans[iswitch]); + + ntrans_no_sharing += unsharable_switch_trans[iswitch] + + sharable_switch_trans[iswitch]; + ntrans_sharing += unsharable_switch_trans[iswitch]; + } else if (from_node < to_node) { + + /* Pass transistor shared by two edges -- only count once. * + * Also, no part of a pass transistor is sharable. */ + + ntrans_no_sharing += unsharable_switch_trans[iswitch]; + ntrans_sharing += unsharable_switch_trans[iswitch]; + } + break; + + case IPIN: + num_inputs_to_cblock[to_node]++; + max_inputs_to_cblock = std::max(max_inputs_to_cblock, + num_inputs_to_cblock[to_node]); + + iseg = seg_index_of_cblock(from_rr_type, to_node); + /* Xifan TANG: cb switches*/ + if (OPEN == switches_to_cblock[to_node]) { + switches_to_cblock[to_node] = rr_node[from_node].switches[iedge]; + } else { + assert(switches_to_cblock[to_node] == rr_node[from_node].switches[iedge]); + } + /* END */ + + if (cblock_counted[iseg] == FALSE) { + cblock_counted[iseg] = TRUE; + ntrans_sharing += trans_track_to_cblock_buf; + ntrans_no_sharing += trans_track_to_cblock_buf; + } + break; + + default: + vpr_printf(TIO_MESSAGE_ERROR, "in count_routing_transistors:\n"); + vpr_printf(TIO_MESSAGE_ERROR, "\tUnexpected connection from node %d (type %d) to node %d (type %d).\n", + from_node, from_rr_type, to_node, to_rr_type); + exit(1); + break; + + } /* End switch on to_rr_type. */ + + } /* End for each edge. */ + + /* Now add in the shared buffer transistors, and reset some flags. */ + + if (from_rr_type == CHANX) { + for (i = rr_node[from_node].xlow - 1; + i <= rr_node[from_node].xhigh; i++) { + ntrans_sharing += shared_buffer_trans[i]; + shared_buffer_trans[i] = 0.; + } + + for (i = rr_node[from_node].xlow; i <= rr_node[from_node].xhigh; + i++) + cblock_counted[i] = FALSE; + + } else { /* CHANY */ + for (j = rr_node[from_node].ylow - 1; + j <= rr_node[from_node].yhigh; j++) { + ntrans_sharing += shared_buffer_trans[j]; + shared_buffer_trans[j] = 0.; + } + + for (j = rr_node[from_node].ylow; j <= rr_node[from_node].yhigh; + j++) + cblock_counted[j] = FALSE; + + } + break; + + case OPIN: + num_edges = rr_node[from_node].num_edges; + shared_opin_buffer_trans = 0.; + + for (iedge = 0; iedge < num_edges; iedge++) { + iswitch = rr_node[from_node].switches[iedge]; + ntrans_no_sharing += unsharable_switch_trans[iswitch] + + sharable_switch_trans[iswitch]; + ntrans_sharing += unsharable_switch_trans[iswitch]; + + shared_opin_buffer_trans = std::max(shared_opin_buffer_trans, + sharable_switch_trans[iswitch]); + } + + ntrans_sharing += shared_opin_buffer_trans; + break; + + default: + break; + + } /* End switch on from_rr_type */ + } /* End for all nodes */ + + free(cblock_counted); + free(shared_buffer_trans); + free(unsharable_switch_trans); + free(sharable_switch_trans); + + /* Now add in the input connection block transistors. */ + + input_cblock_trans = get_cblock_trans(num_inputs_to_cblock, /*Xifan TANG:*/switches_to_cblock, + max_inputs_to_cblock, trans_cblock_to_lblock_buf, trans_sram_bit); + + free(num_inputs_to_cblock); + + /* Xifan TANG: cb switches */ + free(switches_to_cblock); + /* END */ + + ntrans_sharing += input_cblock_trans; + ntrans_no_sharing += input_cblock_trans; + + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "Routing area (in minimum width transistor areas)...\n"); + vpr_printf(TIO_MESSAGE_INFO, "\tAssuming no buffer sharing (pessimistic). Total: %#g, per logic tile: %#g\n", + ntrans_no_sharing, ntrans_no_sharing / (float) (nx * ny)); + vpr_printf(TIO_MESSAGE_INFO, "\tAssuming buffer sharing (slightly optimistic). Total: %#g, per logic tile: %#g\n", + ntrans_sharing, ntrans_sharing / (float) (nx * ny)); + vpr_printf(TIO_MESSAGE_INFO, "\n"); +} + +void count_unidir_routing_transistors(t_segment_inf * segment_inf, + float R_minW_nmos, float R_minW_pmos, float sram_area) { + boolean * cblock_counted; /* [0..max(nx,ny)] -- 0th element unused. */ + int *num_inputs_to_cblock; /* [0..num_rr_nodes-1], but all entries not */ + /* Xifan TANG: cb switches*/ + int *switches_to_cblock; /* [0..num_rr_nodes-1], but all entries not */ + /* END */ + + /* corresponding to IPINs will be 0. */ + + t_rr_type from_rr_type, to_rr_type; + int i, j, iseg, from_node, to_node, iedge, num_edges, maxlen; + int max_inputs_to_cblock, cost_index, seg_type, switch_type; + float input_cblock_trans; + const float trans_sram_bit = sram_area; + + /* Two variables below are the accumulator variables that add up all the * + * transistors in the routing. Make doubles so that they don't stop * + * incrementing once adding a switch makes a change of less than 1 part in * + * 10^7 to the total. If this still isn't good enough (adding 1 part in * + * 10^15 will still be thrown away), compute the transistor count in * + * "chunks", by adding up inodes 1 to 1000, 1001 to 2000 and then summing * + * the partial sums together. */ + + double ntrans; + + /* Buffers from the routing to the ipin cblock inputs, and from the ipin * + * cblock outputs to the logic block, respectively. Assume minimum size n * + * transistors, and ptransistors sized to make the pull-up R = pull-down R. */ + + float trans_track_to_cblock_buf; + float trans_cblock_to_lblock_buf; + + max_inputs_to_cblock = 0; + + /* Assume the two buffers below are 4x minimum drive strength (enough to * + * drive a fanout of up to 16 pretty nicely -- should cover a reasonable * + * wiring C plus the fanout. */ + + trans_track_to_cblock_buf = trans_per_buf(R_minW_nmos / 4., R_minW_nmos, + R_minW_pmos); + + trans_cblock_to_lblock_buf = trans_per_buf(R_minW_nmos / 4., R_minW_nmos, + R_minW_pmos); + + num_inputs_to_cblock = (int *) my_calloc(num_rr_nodes, sizeof(int)); + + /* Xifan TANG: cb switches*/ + switches_to_cblock = (int *) my_calloc(num_rr_nodes, sizeof(int)); + for (i = 0; i < num_rr_nodes; i++) { + switches_to_cblock[i] = OPEN; + } + /* END */ + + maxlen = std::max(nx, ny) + 1; + cblock_counted = (boolean *) my_calloc(maxlen, sizeof(boolean)); + + ntrans = 0; + for (from_node = 0; from_node < num_rr_nodes; from_node++) { + + from_rr_type = rr_node[from_node].type; + + switch (from_rr_type) { + + case CHANX: + case CHANY: + num_edges = rr_node[from_node].num_edges; + cost_index = rr_node[from_node].cost_index; + seg_type = rr_indexed_data[cost_index].seg_index; + /* Xifan TANG: Switch Segment Pattern Support + * we should consider the switch no in the segment but in the rr_node + */ + if (rr_node[from_node].unbuf_switched) { + switch_type = rr_node[from_node].driver_switch; + } else { + switch_type = segment_inf[seg_type].wire_switch; + assert( + segment_inf[seg_type].wire_switch == segment_inf[seg_type].opin_switch); + } + assert(switch_inf[switch_type].mux_trans_size >= 1); + /* can't be smaller than min sized transistor */ + + assert(rr_node[from_node].num_opin_drivers == 0); + /* undir has no opin or wire switches */ + assert(rr_node[from_node].num_wire_drivers == 0); + /* undir has no opin or wire switches */ + + /* Each wire segment begins with a multipexer followed by a driver for unidirectional */ + /* Each multiplexer contains all the fan-in to that routing node */ + /* Add up area of multiplexer */ + ntrans += trans_per_mux(rr_node[from_node].fan_in, trans_sram_bit, + switch_inf[switch_type].mux_trans_size, switch_inf[switch_type]); + + /* Add up area of buffer */ + /* Xifan TANG: Switch Segment Pattern Support*/ + if ((switch_inf[switch_type].buf_size == 0)&&(0 != strcmp("unbuf_mux",switch_inf[switch_type].type))) { + ntrans += trans_per_buf(switch_inf[switch_type].R, R_minW_nmos, + R_minW_pmos); + } else { + ntrans += switch_inf[switch_type].buf_size; + } + + for (iedge = 0; iedge < num_edges; iedge++) { + + to_node = rr_node[from_node].edges[iedge]; + to_rr_type = rr_node[to_node].type; + + switch (to_rr_type) { + + case CHANX: + case CHANY: + break; + + case IPIN: + num_inputs_to_cblock[to_node]++; + max_inputs_to_cblock = std::max(max_inputs_to_cblock, + num_inputs_to_cblock[to_node]); + iseg = seg_index_of_cblock(from_rr_type, to_node); + + /* Xifan TANG: cb switches*/ + if (OPEN == switches_to_cblock[to_node]) { + switches_to_cblock[to_node] = switch_type; + } else { + assert(switches_to_cblock[to_node] == switch_type); + } + /* END */ + + if (cblock_counted[iseg] == FALSE) { + cblock_counted[iseg] = TRUE; + ntrans += trans_track_to_cblock_buf; + } + break; + + default: + vpr_printf(TIO_MESSAGE_ERROR, "in count_routing_transistors:\n"); + vpr_printf(TIO_MESSAGE_ERROR, "\tUnexpected connection from node %d (type %d) to node %d (type %d).\n", + from_node, from_rr_type, to_node, to_rr_type); + exit(1); + break; + + } /* End switch on to_rr_type. */ + + } /* End for each edge. */ + + /* Reset some flags */ + if (from_rr_type == CHANX) { + for (i = rr_node[from_node].xlow; i <= rr_node[from_node].xhigh; + i++) + cblock_counted[i] = FALSE; + + } else { /* CHANY */ + for (j = rr_node[from_node].ylow; j <= rr_node[from_node].yhigh; + j++) + cblock_counted[j] = FALSE; + + } + break; + case OPIN: + break; + + default: + break; + + } /* End switch on from_rr_type */ + } /* End for all nodes */ + + /* Now add in the input connection block transistors. */ + + input_cblock_trans = get_cblock_trans(num_inputs_to_cblock, /*Xifan TANG*/switches_to_cblock, + max_inputs_to_cblock, trans_cblock_to_lblock_buf, trans_sram_bit); + + free(cblock_counted); + free(num_inputs_to_cblock); + + /* Xifan TANG: cb switches */ + free(switches_to_cblock); + /* END */ + + ntrans += input_cblock_trans; + + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "Routing area (in minimum width transistor areas)...\n"); + vpr_printf(TIO_MESSAGE_INFO, "\tTotal routing area: %#g, per logic tile: %#g\n", ntrans, ntrans / (float) (nx * ny)); +} + +static float get_cblock_trans(int *num_inputs_to_cblock, int* switches_to_cblock, + int max_inputs_to_cblock, float trans_cblock_to_lblock_buf, + float trans_sram_bit) { + + /* Computes the transistors in the input connection block multiplexers and * + * the buffers from connection block outputs to the logic block input pins. * + * For speed, I precompute the number of transistors in the multiplexers of * + * interest. */ + + float *trans_per_cblock; /* [0..max_inputs_to_cblock] */ + float trans_count; + int i, num_inputs; + + trans_per_cblock = (float *) my_malloc( + (max_inputs_to_cblock + 1) * sizeof(float)); + + trans_per_cblock[0] = 0.; /* i.e., not an IPIN or no inputs */ + + /* With one or more inputs, add the mux and output buffer. I add the output * + * buffer even when the number of inputs = 1 (i.e. no mux) because I assume * + * I need the drivability just for metal capacitance. */ + /* + for (i = 1; i <= max_inputs_to_cblock; i++) + trans_per_cblock[i] = trans_per_mux(i, trans_sram_bit, + ipin_mux_trans_size) + trans_cblock_to_lblock_buf; + */ + + trans_count = 0.; + + for (i = 0; i < num_rr_nodes; i++) { + num_inputs = num_inputs_to_cblock[i]; + /* Xifan TANG: consider cblock structure in area estimation */ + assert((0 < num_inputs)||(0 == num_inputs)); + if (0 < num_inputs) { + assert(OPEN != switches_to_cblock[i]); + trans_count += trans_per_mux(num_inputs, trans_sram_bit, + ipin_mux_trans_size, switch_inf[switches_to_cblock[i]]) + trans_cblock_to_lblock_buf; + } + /* END */ + /* trans_count += trans_per_cblock[num_inputs]; */ + } + + free(trans_per_cblock); + return (trans_count); +} + +static float * +alloc_and_load_unsharable_switch_trans(int num_switch, float trans_sram_bit, + float R_minW_nmos) { + + /* Loads up an array that says how many transistors are needed to implement * + * the unsharable portion of each switch type. The SRAM bit of a switch and * + * the pass transistor (forming either the entire switch or the output part * + * of a tri-state buffer) are both unsharable. */ + + float *unsharable_switch_trans, Rpass; + int i; + + unsharable_switch_trans = (float *) my_malloc(num_switch * sizeof(float)); + + for (i = 0; i < num_switch; i++) { + + if (switch_inf[i].buffered == FALSE) { + Rpass = switch_inf[i].R; + } else { /* Buffer. Set Rpass = Rbuf = 1/2 Rtotal. */ + Rpass = switch_inf[i].R / 2.; + } + + unsharable_switch_trans[i] = trans_per_R(Rpass, R_minW_nmos) + + trans_sram_bit; + } + + return (unsharable_switch_trans); +} + +static float * +alloc_and_load_sharable_switch_trans(int num_switch, float trans_sram_bit, + float R_minW_nmos, float R_minW_pmos) { + + /* Loads up an array that says how many transistor are needed to implement * + * the sharable portion of each switch type. The SRAM bit of a switch and * + * the pass transistor (forming either the entire switch or the output part * + * of a tri-state buffer) are both unsharable. Only the buffer part of a * + * buffer switch is sharable. */ + + float *sharable_switch_trans, Rbuf; + int i; + + sharable_switch_trans = (float *) my_malloc(num_switch * sizeof(float)); + + for (i = 0; i < num_switch; i++) { + + if (switch_inf[i].buffered == FALSE) { + sharable_switch_trans[i] = 0.; + } else { /* Buffer. Set Rbuf = Rpass = 1/2 Rtotal. */ + Rbuf = switch_inf[i].R / 2.; + sharable_switch_trans[i] = trans_per_buf(Rbuf, R_minW_nmos, + R_minW_pmos); + } + } + + return (sharable_switch_trans); +} + +/*mrFPGA: Xifan TANG, make this function accessible out of this source file*/ +//static +/*end */ +float trans_per_buf(float Rbuf, float R_minW_nmos, float R_minW_pmos) { + + /* Returns the number of minimum width transistor area equivalents needed to * + * implement this buffer. Assumes a stage ratio of 4, and equal strength * + * pull-up and pull-down paths. */ + + int num_stage, istage; + float trans_count, stage_ratio, Rstage; + + if (Rbuf > 0.6 * R_minW_nmos || Rbuf <= 0.) { /* Use a single-stage buffer */ + trans_count = trans_per_R(Rbuf, R_minW_nmos) + + trans_per_R(Rbuf, R_minW_pmos); + } else { /* Use a multi-stage buffer */ + + /* Target stage ratio = 4. 1 minimum width buffer, then num_stage bigger * + * ones. */ + + num_stage = nint(log10(R_minW_nmos / Rbuf) / log10(4.)); + num_stage = std::max(num_stage, 1); + stage_ratio = pow((float)(R_minW_nmos / Rbuf), (float)( 1. / (float) num_stage)); + + Rstage = R_minW_nmos; + trans_count = 0.; + + for (istage = 0; istage <= num_stage; istage++) { + trans_count += trans_per_R(Rstage, R_minW_nmos) + + trans_per_R(Rstage, R_minW_pmos); + Rstage /= stage_ratio; + } + } + + return (trans_count); +} + +static float trans_per_mux(int num_inputs, float trans_sram_bit, + float pass_trans_area, t_switch_inf target_switch) { + + /* Returns the number of transistors needed to build a pass transistor mux. * + * DOES NOT include input buffers or any output buffer. * + * Attempts to select smart multiplexer size depending on number of inputs * + * For multiplexers with inputs 4 or less, one level is used, more has two * + * levels. */ + float ntrans, sram_trans, pass_trans; + int num_second_stage_trans; + int mux_basis = 0; + + /* Xifan TANG: Original VPR area function is below, I replace them by considering more physical design parameters */ + /* + if (num_inputs <= 1) { + return (0); + } else if (num_inputs == 2) { + pass_trans = 2 * pass_trans_area; + sram_trans = 1 * trans_sram_bit; + } else if (num_inputs <= 4) { + */ + /* One-hot encoding */ + /* + pass_trans = num_inputs * pass_trans_area; + sram_trans = num_inputs * trans_sram_bit; + } else { + */ + /* This is a large multiplexer so design it using a two-level multiplexer * + * + 0.00001 is to make sure exact square roots two don't get rounded down * + * to one lower level. */ + /* + num_second_stage_trans = (int)floor((float)sqrt((float)num_inputs) + 0.00001); + pass_trans = (num_inputs + num_second_stage_trans) * pass_trans_area; + sram_trans = (ceil( + (float) num_inputs / num_second_stage_trans - 0.00001) + + num_second_stage_trans) * trans_sram_bit; + if (num_second_stage_trans == 2) { + */ + /* Can use one-bit instead of a two-bit one-hot encoding for the second stage */ + /* Eliminates one sram bit counted earlier */ + /* + sram_trans -= 1 * trans_sram_bit; + } + } + */ + /* Xifan TANG: new function starts */ + if (num_inputs <= 1) { + return 0; + } + /* Consider different structure */ + switch (target_switch.structure) { + case SPICE_MODEL_STRUCTURE_TREE: + sram_trans = trans_sram_bit * determine_tree_mux_level(num_inputs); + pass_trans = (num_inputs - 1)* 2 * pass_trans_area; + break; + case SPICE_MODEL_STRUCTURE_ONELEVEL: + sram_trans = trans_sram_bit * num_inputs; + pass_trans = (num_inputs * pass_trans_area); + break; + case SPICE_MODEL_STRUCTURE_MULTILEVEL: + assert(1 < target_switch.switch_num_level); + sram_trans = trans_sram_bit * target_switch.switch_num_level; + mux_basis = determine_num_input_basis_multilevel_mux(num_inputs, target_switch.switch_num_level); + num_second_stage_trans = (int)pow((double)mux_basis, (double)(target_switch.switch_num_level - 1)); + pass_trans = ((num_second_stage_trans - 1) * mux_basis/(mux_basis-1)) * pass_trans_area + + num_inputs * pass_trans_area; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid structure for switch(name=%s)!\n", + __FILE__, __LINE__, target_switch.name); + exit(1); + } + + ntrans = pass_trans + sram_trans; + return (ntrans); +} + +static float trans_per_R(float Rtrans, float R_minW_trans) { + + /* Returns the number of minimum width transistor area equivalents needed * + * to make a transistor with Rtrans, given that the resistance of a minimum * + * width transistor of this type is R_minW_trans. */ + + float trans_area; + + if (Rtrans <= 0.) /* Assume resistances are nonsense -- use min. width */ + return (1.); + + if (Rtrans >= R_minW_trans) + return (1.); + + /* Area = minimum width area (1) + 0.5 for each additional unit of width. * + * The 50% factor takes into account the "overlapping" that occurs in * + * horizontally-paralleled transistors, and the need for only one spacing, * + * not two (i.e. two min W transistors need two spaces; a 2W transistor * + * needs only 1). */ + + trans_area = 0.5 * R_minW_trans / Rtrans + 0.5; + return (trans_area); +} diff --git a/vpr7_rram/vpr/SRC/route/rr_graph_area.h b/vpr7_rram/vpr/SRC/route/rr_graph_area.h new file mode 100755 index 000000000..c933648ef --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/rr_graph_area.h @@ -0,0 +1,6 @@ + +float trans_per_buf(float Rbuf, float R_minW_nmos, float R_minW_pmos); + +void count_routing_transistors(enum e_directionality directionality, + int num_switch, t_segment_inf * segment_inf, float R_minW_nmos, + float R_minW_pmos, float sram_area); diff --git a/vpr7_rram/vpr/SRC/route/rr_graph_indexed_data.c b/vpr7_rram/vpr/SRC/route/rr_graph_indexed_data.c new file mode 100755 index 000000000..9a4f6e7a8 --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/rr_graph_indexed_data.c @@ -0,0 +1,338 @@ +#include /* Needed only for sqrt call (remove if sqrt removed) */ +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph_util.h" +#include "rr_graph2.h" +#include "rr_graph_indexed_data.h" +#include "read_xml_arch_file.h" + +/* mrFPGA: Xifan TANG */ +#include "mrfpga_globals.h" +/* end */ + +/******************* Subroutines local to this module ************************/ + +static void load_rr_indexed_data_base_costs(int nodes_per_chan, + t_ivec *** L_rr_node_indices, enum e_base_cost_type base_cost_type, + int wire_to_ipin_switch); + +static float get_delay_normalization_fac(int nodes_per_chan, + t_ivec *** L_rr_node_indices); + +static float get_average_opin_delay(t_ivec *** L_rr_node_indices, + int nodes_per_chan); + +static void load_rr_indexed_data_T_values(int index_start, + int num_indices_to_load, t_rr_type rr_type, int nodes_per_chan, + t_ivec *** L_rr_node_indices, t_segment_inf * segment_inf); + +/******************** Subroutine definitions *********************************/ + +/* Allocates the rr_indexed_data array and loads it with appropriate values. * + * It currently stores the segment type (or OPEN if the index doesn't * + * correspond to an CHANX or CHANY type), the base cost of nodes of that * + * type, and some info to allow rapid estimates of time to get to a target * + * to be computed by the router. * + * + * Right now all SOURCES have the same base cost; and similarly there's only * + * one base cost for each of SINKs, OPINs, and IPINs (four total). This can * + * be changed just by allocating more space in the array below and changing * + * the cost_index values for these rr_nodes, if you want to make some pins * + * etc. more expensive than others. I give each segment type in an * + * x-channel its own cost_index, and each segment type in a y-channel its * + * own cost_index. */ +void alloc_and_load_rr_indexed_data(INP t_segment_inf * segment_inf, + INP int num_segment, INP t_ivec *** L_rr_node_indices, + INP int nodes_per_chan, int wire_to_ipin_switch, + enum e_base_cost_type base_cost_type) { + + int iseg, length, i, index; + + num_rr_indexed_data = CHANX_COST_INDEX_START + (2 * num_segment); + rr_indexed_data = (t_rr_indexed_data *) my_malloc( + num_rr_indexed_data * sizeof(t_rr_indexed_data)); + + /* For rr_types that aren't CHANX or CHANY, base_cost is valid, but most * + * * other fields are invalid. For IPINs, the T_linear field is also valid; * + * * all other fields are invalid. For SOURCES, SINKs and OPINs, all fields * + * * other than base_cost are invalid. Mark invalid fields as OPEN for safety. */ + + for (i = SOURCE_COST_INDEX; i <= IPIN_COST_INDEX; i++) { + rr_indexed_data[i].ortho_cost_index = OPEN; + rr_indexed_data[i].seg_index = OPEN; + rr_indexed_data[i].inv_length = OPEN; + rr_indexed_data[i].T_linear = OPEN; + rr_indexed_data[i].T_quadratic = OPEN; + rr_indexed_data[i].C_load = OPEN; + } + + rr_indexed_data[IPIN_COST_INDEX].T_linear = + switch_inf[wire_to_ipin_switch].Tdel; + + /* X-directed segments. */ + + for (iseg = 0; iseg < num_segment; iseg++) { + index = CHANX_COST_INDEX_START + iseg; + + rr_indexed_data[index].ortho_cost_index = index + num_segment; + + if (segment_inf[iseg].longline) + length = nx; + else + length = std::min(segment_inf[iseg].length, nx); + + rr_indexed_data[index].inv_length = 1. / length; + rr_indexed_data[index].seg_index = iseg; + } + + load_rr_indexed_data_T_values(CHANX_COST_INDEX_START, num_segment, CHANX, + nodes_per_chan, L_rr_node_indices, segment_inf); + + /* Y-directed segments. */ + + for (iseg = 0; iseg < num_segment; iseg++) { + index = CHANX_COST_INDEX_START + num_segment + iseg; + + rr_indexed_data[index].ortho_cost_index = index - num_segment; + + if (segment_inf[iseg].longline) + length = ny; + else + length = std::min(segment_inf[iseg].length, ny); + + rr_indexed_data[index].inv_length = 1. / length; + rr_indexed_data[index].seg_index = iseg; + } + + load_rr_indexed_data_T_values((CHANX_COST_INDEX_START + num_segment), + num_segment, CHANY, nodes_per_chan, L_rr_node_indices, segment_inf); + + load_rr_indexed_data_base_costs(nodes_per_chan, L_rr_node_indices, + base_cost_type, wire_to_ipin_switch); + +} + +static void load_rr_indexed_data_base_costs(int nodes_per_chan, + t_ivec *** L_rr_node_indices, enum e_base_cost_type base_cost_type, + int wire_to_ipin_switch) { + + /* Loads the base_cost member of rr_indexed_data according to the specified * + * base_cost_type. */ + + float delay_normalization_fac; + int index; + + if (base_cost_type == DELAY_NORMALIZED) { + delay_normalization_fac = get_delay_normalization_fac(nodes_per_chan, + L_rr_node_indices); + } else { + delay_normalization_fac = 1.; + } + + if (base_cost_type == DEMAND_ONLY || base_cost_type == DELAY_NORMALIZED) { + rr_indexed_data[SOURCE_COST_INDEX].base_cost = delay_normalization_fac; + /* rr_indexed_data[SOURCE_COST_INDEX].base_cost = 0; Xifan TANG: TODO: Update routing cost to 1*/ + rr_indexed_data[SINK_COST_INDEX].base_cost = 0.; + rr_indexed_data[OPIN_COST_INDEX].base_cost = delay_normalization_fac; + /*rr_indexed_data[OPIN_COST_INDEX].base_cost = 0.95; Xifan TANG: TODO: Update routing cost to 1*/ + +#ifndef SPEC + rr_indexed_data[IPIN_COST_INDEX].base_cost = 0.95 + * delay_normalization_fac; +#else /* Avoid roundoff for SPEC */ + rr_indexed_data[IPIN_COST_INDEX].base_cost = + delay_normalization_fac; +#endif + } + + else if (base_cost_type == INTRINSIC_DELAY) { + rr_indexed_data[SOURCE_COST_INDEX].base_cost = 0.; + rr_indexed_data[SINK_COST_INDEX].base_cost = 0.; + rr_indexed_data[OPIN_COST_INDEX].base_cost = get_average_opin_delay( + L_rr_node_indices, nodes_per_chan); + rr_indexed_data[IPIN_COST_INDEX].base_cost = + switch_inf[wire_to_ipin_switch].Tdel; + } + + /* Load base costs for CHANX and CHANY segments */ + + for (index = CHANX_COST_INDEX_START; index < num_rr_indexed_data; index++) { + if (base_cost_type == INTRINSIC_DELAY) + rr_indexed_data[index].base_cost = rr_indexed_data[index].T_linear + + rr_indexed_data[index].T_quadratic; + else + /* rr_indexed_data[index].base_cost = delay_normalization_fac / + rr_indexed_data[index].inv_length; */ + + rr_indexed_data[index].base_cost = delay_normalization_fac; + /* rr_indexed_data[index].base_cost = delay_normalization_fac * + sqrt (1. / rr_indexed_data[index].inv_length); */ + /* rr_indexed_data[index].base_cost = delay_normalization_fac * + (1. + 1. / rr_indexed_data[index].inv_length); */ + } + + /* Save a copy of the base costs -- if dynamic costing is used by the * + * router, the base_cost values will get changed all the time and being * + * able to restore them from a saved version is useful. */ + + for (index = 0; index < num_rr_indexed_data; index++) { + rr_indexed_data[index].saved_base_cost = + rr_indexed_data[index].base_cost; + } +} + +static float get_delay_normalization_fac(int nodes_per_chan, + t_ivec *** L_rr_node_indices) { + + /* Returns the average delay to go 1 CLB distance along a wire. */ + + const int clb_dist = 3; /* Number of CLBs I think the average conn. goes. */ + + int inode, itrack, cost_index; + float Tdel, Tdel_sum, frac_num_seg; + + Tdel_sum = 0.; + + for (itrack = 0; itrack < nodes_per_chan; itrack++) { + inode = get_rr_node_index((nx + 1) / 2, (ny + 1) / 2, CHANX, itrack, + L_rr_node_indices); + cost_index = rr_node[inode].cost_index; + frac_num_seg = clb_dist * rr_indexed_data[cost_index].inv_length; + Tdel = frac_num_seg * rr_indexed_data[cost_index].T_linear + + frac_num_seg * frac_num_seg + * rr_indexed_data[cost_index].T_quadratic; + Tdel_sum += Tdel / (float) clb_dist; + } + + for (itrack = 0; itrack < nodes_per_chan; itrack++) { + inode = get_rr_node_index((nx + 1) / 2, (ny + 1) / 2, CHANY, itrack, + L_rr_node_indices); + cost_index = rr_node[inode].cost_index; + frac_num_seg = clb_dist * rr_indexed_data[cost_index].inv_length; + Tdel = frac_num_seg * rr_indexed_data[cost_index].T_linear + + frac_num_seg * frac_num_seg + * rr_indexed_data[cost_index].T_quadratic; + Tdel_sum += Tdel / (float) clb_dist; + } + + return (Tdel_sum / (2. * nodes_per_chan)); +} + +static float get_average_opin_delay(t_ivec *** L_rr_node_indices, + int nodes_per_chan) { + + /* Returns the average delay from an OPIN to a wire in an adjacent channel. */ + /* RESEARCH TODO: Got to think if this heuristic needs to change for hetero, right now, I'll calculate + * the average delay of non-IO blocks */ + int inode, ipin, iclass, iedge, itype, num_edges, to_switch, to_node, + num_conn; + float Cload, Tdel; + + Tdel = 0.; + num_conn = 0; + for (itype = 0; itype < num_types && &type_descriptors[itype] != IO_TYPE; + itype++) { + for (ipin = 0; ipin < type_descriptors[itype].num_pins; ipin++) { + iclass = type_descriptors[itype].pin_class[ipin]; + if (type_descriptors[itype].class_inf[iclass].type == DRIVER) { /* OPIN */ + inode = get_rr_node_index((nx + 1) / 2, (ny + 1) / 2, OPIN, + ipin, L_rr_node_indices); + num_edges = rr_node[inode].num_edges; + + for (iedge = 0; iedge < num_edges; iedge++) { + to_node = rr_node[inode].edges[iedge]; + to_switch = rr_node[inode].switches[iedge]; + Cload = rr_node[to_node].C; + Tdel += Cload * switch_inf[to_switch].R + + switch_inf[to_switch].Tdel; + num_conn++; + } + } + } + } + + Tdel /= (float) num_conn; + return (Tdel); +} + +static void load_rr_indexed_data_T_values(int index_start, + int num_indices_to_load, t_rr_type rr_type, int nodes_per_chan, + t_ivec *** L_rr_node_indices, t_segment_inf * segment_inf) { + + /* Loads the average propagation times through segments of each index type * + * for either all CHANX segment types or all CHANY segment types. It does * + * this by looking at all the segments in one channel in the middle of the * + * array and averaging the R and C values of all segments of the same type * + * and using them to compute average delay values for this type of segment. */ + + int itrack, iseg, inode, cost_index, iswitch; + float *C_total, *R_total; /* [0..num_rr_indexed_data - 1] */ + int *num_nodes_of_index; /* [0..num_rr_indexed_data - 1] */ + float Rnode, Cnode, Rsw, Tsw; + + num_nodes_of_index = (int *) my_calloc(num_rr_indexed_data, sizeof(int)); + C_total = (float *) my_calloc(num_rr_indexed_data, sizeof(float)); + R_total = (float *) my_calloc(num_rr_indexed_data, sizeof(float)); + + /* Get average C and R values for all the segments of this type in one * + * channel segment, near the middle of the array. */ + + for (itrack = 0; itrack < nodes_per_chan; itrack++) { + inode = get_rr_node_index((nx + 1) / 2, (ny + 1) / 2, rr_type, itrack, + L_rr_node_indices); + cost_index = rr_node[inode].cost_index; + num_nodes_of_index[cost_index]++; + C_total[cost_index] += rr_node[inode].C; + R_total[cost_index] += rr_node[inode].R; + } + + for (cost_index = index_start; + cost_index < index_start + num_indices_to_load; cost_index++) { + + if (num_nodes_of_index[cost_index] == 0) { /* Segments don't exist. */ + rr_indexed_data[cost_index].T_linear = OPEN; + rr_indexed_data[cost_index].T_quadratic = OPEN; + rr_indexed_data[cost_index].C_load = OPEN; + } else { + Rnode = R_total[cost_index] / num_nodes_of_index[cost_index]; + Cnode = C_total[cost_index] / num_nodes_of_index[cost_index]; + /* mrFPGA: Xifan TANG */ + if (is_isolation) { + Cnode += switch_inf[iswitch].Cin + switch_inf[iswitch].Cout; + } + /* end */ + iseg = rr_indexed_data[cost_index].seg_index; + iswitch = segment_inf[iseg].wire_switch; + Rsw = switch_inf[iswitch].R; + Tsw = switch_inf[iswitch].Tdel; + + if (switch_inf[iswitch].buffered) { + rr_indexed_data[cost_index].T_linear = Tsw + Rsw * Cnode + + 0.5 * Rnode * Cnode; + rr_indexed_data[cost_index].T_quadratic = 0.; + rr_indexed_data[cost_index].C_load = 0.; + } else { /* Pass transistor */ + rr_indexed_data[cost_index].C_load = Cnode; + + /* See Dec. 23, 1997 notes for deriviation of formulae. */ + + rr_indexed_data[cost_index].T_linear = Tsw + 0.5 * Rsw * Cnode; + rr_indexed_data[cost_index].T_quadratic = (Rsw + Rnode) * 0.5 + * Cnode; + /* mrFPGA: Xifan TANG */ + if (is_mrFPGA && is_wire_buffer) { + rr_indexed_data[cost_index].T_linear += wire_buffer_inf.R * Cnode + wire_buffer_inf.C * (Rnode + Rsw) + + sqrt(rr_indexed_data[cost_index].T_quadratic * (wire_buffer_inf.Tdel + + wire_buffer_inf.R * wire_buffer_inf.C)); + rr_indexed_data[cost_index].T_quadratic = 0.; + } + /* end */ + } + } + } + + free(num_nodes_of_index); + free(C_total); + free(R_total); +} diff --git a/vpr7_rram/vpr/SRC/route/rr_graph_indexed_data.h b/vpr7_rram/vpr/SRC/route/rr_graph_indexed_data.h new file mode 100755 index 000000000..1ec5ca8ab --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/rr_graph_indexed_data.h @@ -0,0 +1,3 @@ +void alloc_and_load_rr_indexed_data(t_segment_inf * segment_inf, + int num_segment, t_ivec *** L_rr_node_indices, int nodes_per_chan, + int wire_to_ipin_switch, enum e_base_cost_type base_cost_type); diff --git a/vpr7_rram/vpr/SRC/route/rr_graph_opincb.c b/vpr7_rram/vpr/SRC/route/rr_graph_opincb.c new file mode 100644 index 000000000..80169617d --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/rr_graph_opincb.c @@ -0,0 +1,626 @@ +#include +#include +#include +#include +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph_util.h" +#include "rr_graph.h" +#include "rr_graph2.h" +#include "rr_graph_sbox.h" +#include "check_rr_graph.h" +#include "rr_graph_timing_params.h" +#include "rr_graph_indexed_data.h" +#include "vpr_utils.h" +#include "read_xml_arch_file.h" +#include "ReadOptions.h" +#include "rr_graph_opincb.h" + +/* Subroutines */ +static +int add_rr_graph_one_grid_fast_edge_opin_to_cb(int grid_x, + int grid_y, + t_ivec*** LL_rr_node_indices); + +static +void get_grid_side_pins(int grid_x, int grid_y, + int side, enum e_pin_type pin_type, + t_ivec*** LL_rr_node_indices, + int *num_pins, t_rr_node** *pin_list); + +static +int add_opin_list_ipin_list_fast_edge(int num_opins, t_rr_node** opin_list, + int num_ipins, t_rr_node** ipin_list); + +static +int add_opin_fast_edge_to_ipin(t_rr_node* opin, + t_rr_node* ipin); + +static +int get_ipin_switch_index(t_rr_node* ipin); + +static +void find_rr_nodes_ipin_driver_switch(); + +static +void recover_rr_nodes_ipin_driver_switch(); + +/* Xifan TANG: Create Fast Interconnection between LB OPIN and CB INPUT*/ +/* TOP function */ +int add_rr_graph_fast_edge_opin_to_cb(t_ivec*** LL_rr_node_indices) { + int ix, iy; + int add_edge_counter = 0; + int run_opintocb = 0; + + /* Decide if we run this part */ + + /* For each grid, include I/O*/ + for (ix = 1; ix < (nx+1); ix++) { + for (iy = 1; iy < (ny+1); iy++) { + if ((EMPTY_TYPE != grid[ix][iy].type)&&(TRUE == grid[ix][iy].type->opin_to_cb)) { + run_opintocb = 1; + break; + } + } + if (1 == run_opintocb) { + break; + } + } + + if (0 == run_opintocb) { + return add_edge_counter; + } + + find_rr_nodes_ipin_driver_switch(); + + /* For each grid, include I/O*/ + for (ix = 1; ix < (nx+1); ix++) { + for (iy = 1; iy < (ny+1); iy++) { + add_edge_counter += add_rr_graph_one_grid_fast_edge_opin_to_cb(ix, iy, LL_rr_node_indices); + } + } + + recover_rr_nodes_ipin_driver_switch(); + + return add_edge_counter; +} + +/* For one grid, add fast edge from a LB OPIN to CB*/ +static +int add_rr_graph_one_grid_fast_edge_opin_to_cb(int grid_x, + int grid_y, + t_ivec*** LL_rr_node_indices) { + int opin_side, ipin_side; + boolean early_stop = FALSE; + int num_opins = 0; + t_rr_node** opin_list = NULL; + int num_ipins = 0; + t_rr_node** ipin_list = NULL; + int add_edge_counter = 0; + t_type_ptr type_descriptor = NULL; + + /* Make sure this is a valid grid*/ + assert((-1 < grid_x) && (grid_x < (nx+1))); + assert((-1 < grid_y) && (grid_y < (ny+1))); + + /* Get the type_descriptor and determine if this grid should add edges */ + type_descriptor = grid[grid_x][grid_y].type; + if (NULL == type_descriptor) { + return add_edge_counter; + } else if (FALSE == type_descriptor->opin_to_cb) { + return add_edge_counter; + } + + /* Check each side of this grid, + * determine how many adjacent LB should be taken into account. + */ + for (opin_side = 0; opin_side < 4; opin_side++) { + early_stop = FALSE; + switch(opin_side) { + case TOP: + /* Only I/O on the bottom side of FPGA allows to continue */ + if ((0 == grid_x)||(ny + 1 == grid_y)||(nx + 1 == grid_x)) { + early_stop = TRUE; + } + break; + case RIGHT: + /* Only I/O on the left side of FPGA allows to continue */ + if ((0 == grid_y)||(ny + 1 == grid_y)||(nx + 1 == grid_x)) { + early_stop = TRUE; + } + break; + case BOTTOM: + /* Only I/O on the top side of FPGA allows to continue */ + if ((0 == grid_x)||(0 == grid_y)||(nx + 1 == grid_x)) { + early_stop = TRUE; + } + break; + case LEFT: + /* Only I/O on the right side of FPGA allows to continue */ + if ((0 == grid_x)||(ny + 1 == grid_y)||(0 == grid_y)) { + early_stop = TRUE; + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File: %s, [LINE%d]) Invalid opin_side(%d)!\n", + __FILE__, __LINE__, opin_side); + exit(1); + } + /* Decide if we should do something or not */ + if (TRUE == early_stop) { + continue; + } + + /* Find the opins on the opin_side of current grid */ + get_grid_side_pins(grid_x, grid_y, opin_side, DRIVER, LL_rr_node_indices, &num_opins, &opin_list); + if (0 == num_opins) { /* Do nothing if there is no OPIN available */ + continue; + } + + switch(opin_side) { + case TOP: + /* Create fast connection to the grid above*/ + for (ipin_side = 0; ipin_side < 4; ipin_side++) { + /* For the grid on the boundary, we only create connections to the bottom side */ + if (((grid_y + 1) == (ny + 1))&&(BOTTOM != ipin_side)) { + continue; + } + /* We also skip the top side because we believe a IPIN at the top side + * can be swapped to others by using logic equivalence. Which is faster. + */ + if (TOP == ipin_side) { + continue; + } + get_grid_side_pins(grid_x, grid_y+1, ipin_side, RECEIVER, LL_rr_node_indices, &num_ipins, &ipin_list); + /* Create fast edge from the OPINs to IPINs*/ + add_edge_counter += add_opin_list_ipin_list_fast_edge(num_opins, opin_list, num_ipins, ipin_list); + /* Free ipin_list */ + num_ipins = 0; + free(ipin_list); + } + /* If this is already the bottom side of FPGA, we skip */ + if (0 == grid_y) { + break; + } + /* Create fast connection to the grid below */ + for (ipin_side = 0; ipin_side < 4; ipin_side++) { + /* For the grid on the boundary, we only create connections to the top side */ + if (((grid_y - 1) == 0)&&(TOP != ipin_side)) { + continue; + } + /* We also skip the bottom side because we believe a IPIN at the bottom side + * can be swapped to others by using logic equivalence. Which is faster. + */ + if (BOTTOM == ipin_side) { + continue; + } + get_grid_side_pins(grid_x, grid_y-1, ipin_side, RECEIVER, LL_rr_node_indices, &num_ipins, &ipin_list); + /* Create fast edge from the OPINs to IPINs*/ + add_edge_counter += add_opin_list_ipin_list_fast_edge(num_opins, opin_list, num_ipins, ipin_list); + /* Free ipin_list */ + num_ipins = 0; + free(ipin_list); + } + break; + case RIGHT: + /* Create fast connection to the grid on the right side */ + for (ipin_side = 0; ipin_side < 4; ipin_side++) { + /* For the grid on the boundary, we only create connections to the left side */ + if (((grid_x + 1) == (nx + 1))&&(LEFT != ipin_side)) { + continue; + } + /* We also skip the top side because we believe a IPIN at the top side + * can be swapped to others by using logic equivalence. Which is faster. + */ + if (RIGHT == ipin_side) { + continue; + } + get_grid_side_pins(grid_x+1, grid_y, ipin_side, RECEIVER, LL_rr_node_indices, &num_ipins, &ipin_list); + /* Create fast edge from the OPINs to IPINs*/ + add_edge_counter += add_opin_list_ipin_list_fast_edge(num_opins, opin_list, num_ipins, ipin_list); + /* Free ipin_list */ + num_ipins = 0; + free(ipin_list); + } + /* If this is already the left side of FPGA, we skip */ + if (0 == grid_x) { + break; + } + /* Create fast connection to the grid on the left side */ + for (ipin_side = 0; ipin_side < 4; ipin_side++) { + /* For the grid on the boundary, we only create connections to the rigth side */ + if (((grid_x - 1) == 0)&&(RIGHT != ipin_side)) { + continue; + } + /* We also skip the bottom side because we believe a IPIN at the bottom side + * can be swapped to others by using logic equivalence. Which is faster. + */ + if (LEFT == ipin_side) { + continue; + } + get_grid_side_pins(grid_x-1, grid_y, ipin_side, RECEIVER, LL_rr_node_indices, &num_ipins, &ipin_list); + /* Create fast edge from the OPINs to IPINs*/ + add_edge_counter += add_opin_list_ipin_list_fast_edge(num_opins, opin_list, num_ipins, ipin_list); + /* Free ipin_list */ + num_ipins = 0; + free(ipin_list); + } + break; + case BOTTOM: + /* Create fast connection to the grid on the bottom side */ + for (ipin_side = 0; ipin_side < 4; ipin_side++) { + /* For the grid on the boundary, we only create connections to the left side */ + if (((grid_y - 1) == 0)&&(TOP != ipin_side)) { + continue; + } + /* We also skip the top side because we believe a IPIN at the bottom side + * can be swapped to others by using logic equivalence. Which is faster. + */ + if (BOTTOM == ipin_side) { + continue; + } + get_grid_side_pins(grid_x, grid_y-1, ipin_side, RECEIVER, LL_rr_node_indices, &num_ipins, &ipin_list); + /* Create fast edge from the OPINs to IPINs*/ + add_edge_counter += add_opin_list_ipin_list_fast_edge(num_opins, opin_list, num_ipins, ipin_list); + /* Free ipin_list */ + num_ipins = 0; + free(ipin_list); + } + /* If this is already the left side of FPGA, we skip */ + if ((ny + 1) == grid_y) { + break; + } + /* Create fast connection to the grid on the top side */ + for (ipin_side = 0; ipin_side < 4; ipin_side++) { + /* For the grid on the boundary, we only create connections to the rigth side */ + if (((grid_y + 1) == (ny + 1))&&(BOTTOM != ipin_side)) { + continue; + } + /* We also skip the bottom side because we believe a IPIN at the bottom side + * can be swapped to others by using logic equivalence. Which is faster. + */ + if (TOP == ipin_side) { + continue; + } + if (grid_y + 1 == ny + 1) { + assert(BOTTOM == ipin_side); + } + get_grid_side_pins(grid_x, grid_y+1, ipin_side, RECEIVER, LL_rr_node_indices, &num_ipins, &ipin_list); + /* Create fast edge from the OPINs to IPINs*/ + add_edge_counter += add_opin_list_ipin_list_fast_edge(num_opins, opin_list, num_ipins, ipin_list); + /* Free ipin_list */ + num_ipins = 0; + free(ipin_list); + } + break; + case LEFT: + /* Create fast connection to the grid on the left side */ + for (ipin_side = 0; ipin_side < 4; ipin_side++) { + /* For the grid on the boundary, we only create connections to the left side */ + if (((grid_x - 1) == 0)&&(RIGHT != ipin_side)) { + continue; + } + /* We also skip the top side because we believe a IPIN at the top side + * can be swapped to others by using logic equivalence. Which is faster. + */ + if (LEFT == ipin_side) { + continue; + } + get_grid_side_pins(grid_x-1, grid_y, ipin_side, RECEIVER, LL_rr_node_indices, &num_ipins, &ipin_list); + /* Create fast edge from the OPINs to IPINs*/ + add_edge_counter += add_opin_list_ipin_list_fast_edge(num_opins, opin_list, num_ipins, ipin_list); + /* Free ipin_list */ + num_ipins = 0; + free(ipin_list); + } + /* If this is already the right side of FPGA, we skip */ + if ((nx + 1) == grid_x) { + break; + } + /* Create fast connection to the grid on the right side */ + for (ipin_side = 0; ipin_side < 4; ipin_side++) { + /* For the grid on the boundary, we only create connections to the right side */ + if (((grid_x + 1) == (nx + 1))&&(LEFT != ipin_side)) { + continue; + } + /* We also skip the bottom side because we believe a IPIN at the bottom side + * can be swapped to others by using logic equivalence. Which is faster. + */ + if (RIGHT == ipin_side) { + continue; + } + get_grid_side_pins(grid_x+1, grid_y, ipin_side, RECEIVER, LL_rr_node_indices, &num_ipins, &ipin_list); + /* Create fast edge from the OPINs to IPINs*/ + add_edge_counter += add_opin_list_ipin_list_fast_edge(num_opins, opin_list, num_ipins, ipin_list); + /* Free ipin_list */ + num_ipins = 0; + free(ipin_list); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File: %s, [LINE%d]) Invalid opin_side(%d)!\n", + __FILE__, __LINE__, opin_side); + exit(1); + } + /* Free opin_list */ + num_opins = 0; + free(opin_list); + } + + return add_edge_counter; +} + +/* Find all the OPINs at a side of one grid. + * Return num_opins, and opin_list + */ +static +void get_grid_side_pins(int grid_x, int grid_y, + int side, enum e_pin_type pin_type, + t_ivec*** LL_rr_node_indices, + int *num_pins, t_rr_node** *pin_list) { + int ipin, iheight, class_idx, cur_pin, inode; + t_type_ptr type_descriptor = NULL; + t_rr_type pin_rr_type; + + switch (pin_type) { + case DRIVER: + pin_rr_type = OPIN; + break; + case RECEIVER: + pin_rr_type = IPIN; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File: %s, [LINE%d]) Invalid pin_type(%d)!\n", + __FILE__, __LINE__, pin_type); + exit(1); + } + + /* Initialization */ + (*num_pins) = 0; + (*pin_list) = NULL; + /* (*pin_class_list) = NULL; */ + + /* Make sure this is a valid grid*/ + assert((-1 < grid_x) && (grid_x < (nx+2))); + assert((-1 < grid_y) && (grid_y < (ny+2))); + + assert((-1 < side) && (side < 4)); + + type_descriptor = grid[grid_x][grid_y].type; + + /* Kick out corner cases */ + switch(side) { + case TOP: + /* If this is the most top grid, return*/ + if ((ny+1 == grid_y)||(0 == grid_x)||(nx + 1 == grid_x)) { + return; + } + break; + case RIGHT: + /* If this is the most right grid, return*/ + if ((nx + 1 == grid_x)||(ny + 1 == grid_y)||(0 == grid_y)) { + return; + } + break; + case BOTTOM: + /* If this is the most bottom grid, return*/ + if ((0 == grid_y)||(0 == grid_x)||(nx + 1 == grid_x)) { + return; + } + break; + case LEFT: + /* If this is the most left grid, return*/ + if ((0 == grid_x)||(0 == grid_y)||(ny + 1 == grid_y)) { + return; + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File: %s, [LINE%d]) Invalid side(%d)!\n", + __FILE__, __LINE__, side); + exit(1); + } + + /* Count num_opins */ + for (iheight = 0; iheight < type_descriptor->height; iheight++) { + for (ipin = 0; ipin < type_descriptor->num_pins; ipin++) { + /* Check if this is an OPIN at the side we want*/ + class_idx = type_descriptor->pin_class[ipin]; + assert((-1 < class_idx) && (class_idx < type_descriptor->num_class)); + if ((1 == type_descriptor->pinloc[iheight][side][ipin]) + &&(pin_type == type_descriptor->class_inf[class_idx].type) + &&(TRUE == type_descriptor->opin_to_cb)) { + (*num_pins)++; + } + } + } + + /* Alloc array */ + cur_pin = 0; + (*pin_list) = (t_rr_node**)my_malloc((*num_pins)*sizeof(t_rr_node*)); + /* (*pin_class_list) = (int*)my_malloc((*num_pins)*sizeof(int)); */ + + /* Fill array */ + for (iheight = 0; iheight < type_descriptor->height; iheight++) { + for (ipin = 0; ipin < type_descriptor->num_pins; ipin++) { + /* Check if this is an OPIN at the side we want*/ + class_idx = type_descriptor->pin_class[ipin]; + assert((-1 < class_idx) && (class_idx < type_descriptor->num_class)); + if ((1 == type_descriptor->pinloc[iheight][side][ipin]) + &&(pin_type == type_descriptor->class_inf[class_idx].type) + &&(TRUE == type_descriptor->opin_to_cb)) { + inode = get_rr_node_index(grid_x, grid_y, pin_rr_type, ipin, LL_rr_node_indices); + (*pin_list)[cur_pin] = &rr_node[inode]; + /* (*pin_class_list)[cur_pin] = class_idx; */ + cur_pin++; + } + } + } + assert(cur_pin == (*num_pins)); + + return; +} + +/* We have one list of OPIN, and one list of IPIN, + * decide which two rr_nodes should have a fast edge + */ +static +int add_opin_list_ipin_list_fast_edge(int num_opins, t_rr_node** opin_list, + int num_ipins, t_rr_node** ipin_list) { + int ipin, iedge, to_node, jpin; + int num_ipin_sink = 0; + t_linked_int* ipin_sink_head = NULL; + t_linked_int* ipin_sink_list_node; + int* ipin_sink_index = (int*)my_malloc(sizeof(int)*num_ipins); + int add_edge_counter = 0; + + if (0 == num_opins) { + assert(NULL == opin_list); + return add_edge_counter; + } + + if (0 == num_ipins) { + assert(NULL == ipin_list); + return add_edge_counter; + } + + /* Count the number of common source of these ipin */ + for (ipin = 0; ipin < num_ipins; ipin++) { + ipin_sink_index[ipin] = OPEN; + assert(IPIN == ipin_list[ipin]->type); + for (iedge = 0; iedge < ipin_list[ipin]->num_edges; iedge++) { + to_node = ipin_list[ipin]->edges[iedge]; + if (SINK == rr_node[to_node].type) { + /* Search if the source exists in the list */ + if (NULL == search_in_int_list(ipin_sink_head, to_node)) { + /* Do not exist, add one */ + ipin_sink_head = insert_node_to_int_list(ipin_sink_head, to_node); + /* Update counter */ + num_ipin_sink++; + /* Update the index list */ + ipin_sink_index[ipin] = to_node; + } + } + } + } + + /* For each OPIN node, create a edge to each ipin whose ipin_src is different */ + for (ipin = 0; ipin < num_opins; ipin++) { + for (jpin = 0; jpin < num_ipins; jpin++) { + //if (OPEN != ipin_sink_index[jpin]) { + /* Find its ipin source node*/ + //ipin_sink_list_node = search_in_int_list(ipin_sink_head, ipin_sink_index[jpin]); + //if (NULL != ipin_sink_list_node) { + /* Add a fast edge */ + add_edge_counter += add_opin_fast_edge_to_ipin(opin_list[ipin], ipin_list[jpin]); + /* Make the sink list node invalid */ + // ipin_sink_list_node->data = OPEN; + // } + //} + } + } + + /* Free */ + free_int_list(&ipin_sink_head); + + return add_edge_counter; +} + +/* Add an edge from opin to ipin, use the switch of ipin*/ +static +int add_opin_fast_edge_to_ipin(t_rr_node* opin, + t_rr_node* ipin) { + int ipin_switch_index = OPEN; + int iedge, to_node; + + /* Make sure we have an OPIN and an IPIN*/ + assert(OPIN == opin->type); + assert(IPIN == ipin->type); + + /* Get the switch index of ipin, and check it is valid */ + ipin_switch_index = get_ipin_switch_index(ipin); + if (OPEN == ipin_switch_index) { + return 0; + } + + /* Check if OPIN has a fan-out to IPIN already*/ + for (iedge = 0; iedge < opin->num_edges; iedge++) { + to_node = opin->edges[iedge]; + if ((IPIN == rr_node[to_node].type)&&(ipin == &rr_node[to_node])) { + vpr_printf(TIO_MESSAGE_WARNING, "(File:%s,[LINE%d])OPIN rr_node[%d] has an fan-out to IPIN rr_node[%d]. Fast edge will not be created.\n", __FILE__, __LINE__, opin-rr_node, ipin-rr_node); + return 0; + } + } + + /* create a fast edge */ + /* 1. re-alloc a edge list switch list */ + opin->num_edges++; + opin->edges = (int*)my_realloc(opin->edges, opin->num_edges*sizeof(int)); + opin->switches = (short*)my_realloc(opin->switches, opin->num_edges*sizeof(short)); + /* 2. Update edge and switch info */ + opin->edges[opin->num_edges-1] = ipin - rr_node; + opin->switches[opin->num_edges-1] = ipin_switch_index; + /* 3. Increase the fan-in of IPIN */ + ipin->fan_in++; + /* Finish*/ + + return 1; +} + +/* This is not efficent, should be improved by using LL_rr_node_indices*/ +static +int get_ipin_switch_index(t_rr_node* ipin) { + return ipin->driver_switch; +} + +static +void find_rr_nodes_ipin_driver_switch() { + int inode, jnode, iedge, to_node, fan_in_counter; + int ipin_switch_index = OPEN; + + vpr_printf(TIO_MESSAGE_INFO, "Building rr_node driver switches...\n"); + + for (inode = 0; inode < num_rr_nodes; inode++) { + if (IPIN != rr_node[inode].type) { + continue; + } + /* Create a counter, check the correctness*/ + fan_in_counter = 0; + ipin_switch_index = OPEN; + for (jnode = 0; jnode < num_rr_nodes; jnode++) { + for (iedge = 0; iedge < rr_node[jnode].num_edges; iedge++) { + to_node = rr_node[jnode].edges[iedge]; + if (inode == to_node) { + fan_in_counter++; + if (OPEN == ipin_switch_index) { + ipin_switch_index = rr_node[jnode].switches[iedge]; + } else { + assert(ipin_switch_index == rr_node[jnode].switches[iedge]); + } + } + } + } + assert(fan_in_counter == rr_node[inode].fan_in); + if (0 != fan_in_counter) { + assert(OPEN != ipin_switch_index); + } + rr_node[inode].driver_switch = ipin_switch_index; + } + + return; +} + +static +void recover_rr_nodes_ipin_driver_switch() { + int inode; + + vpr_printf(TIO_MESSAGE_INFO, "Recovering rr_node driver switches...\n"); + + for (inode = 0; inode < num_rr_nodes; inode++) { + if (IPIN == rr_node[inode].type) { + rr_node[inode].driver_switch = OPEN; + } + } + return; +} + diff --git a/vpr7_rram/vpr/SRC/route/rr_graph_opincb.h b/vpr7_rram/vpr/SRC/route/rr_graph_opincb.h new file mode 100644 index 000000000..df0dec4d6 --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/rr_graph_opincb.h @@ -0,0 +1,2 @@ +/* Top function */ +int add_rr_graph_fast_edge_opin_to_cb(t_ivec*** LL_rr_node_indices); diff --git a/vpr7_rram/vpr/SRC/route/rr_graph_sbox.c b/vpr7_rram/vpr/SRC/route/rr_graph_sbox.c new file mode 100755 index 000000000..0b962a2d5 --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/rr_graph_sbox.c @@ -0,0 +1,228 @@ +#include +#include "util.h" +#include "vpr_types.h" +#include "rr_graph_sbox.h" +#include "rr_graph_util.h" +#include "ReadOptions.h" + +/* Switch box: * + * TOP (CHANY) * + * | | | | | | * + * +-----------+ * + * --| |-- * + * --| |-- * + * LEFT --| |-- RIGHT * + * (CHANX)--| |--(CHANX) * + * --| |-- * + * --| |-- * + * +-----------+ * + * | | | | | | * + * BOTTOM (CHANY) */ + +/* [0..3][0..3][0..nodes_per_chan-1]. Structure below is indexed as: * + * [from_side][to_side][from_track]. That yields an integer vector (ivec) * + * of the tracks to which from_track connects in the proper to_location. * + * For simple switch boxes this is overkill, but it will allow complicated * + * switch boxes with Fs > 3, etc. without trouble. */ + +int get_simple_switch_block_track(INP enum e_side from_side, + INP enum e_side to_side, INP int from_track, + INP enum e_switch_block_type switch_block_type, INP int nodes_per_chan); + +/* Allocates and loads the switch_block_conn data structure. This structure * + * lists which tracks connect to which at each switch block. This is for + * bidir. */ +struct s_ivec *** +alloc_and_load_switch_block_conn(INP int nodes_per_chan, + INP enum e_switch_block_type switch_block_type, INP int Fs) { + enum e_side from_side, to_side; + int from_track; + struct s_ivec ***switch_block_conn = NULL; + + /* Currently Fs must be 3 since each track maps once to each other side */ + assert(3 == Fs); + + switch_block_conn = (struct s_ivec ***) alloc_matrix3(0, 3, 0, 3, 0, + (nodes_per_chan - 1), sizeof(struct s_ivec)); + + for (from_side = (enum e_side)0; from_side < 4; from_side = (enum e_side)(from_side + 1)) { + for (to_side = (enum e_side)0; to_side < 4; to_side = (enum e_side)(to_side + 1)) { + for (from_track = 0; from_track < nodes_per_chan; from_track++) { + if (from_side != to_side) { + switch_block_conn[from_side][to_side][from_track].nelem = 1; + switch_block_conn[from_side][to_side][from_track].list = + (int *) my_malloc(sizeof(int)); + + switch_block_conn[from_side][to_side][from_track].list[0] = + get_simple_switch_block_track(from_side, to_side, + from_track, switch_block_type, + nodes_per_chan); + } else { /* from_side == to_side -> no connection. */ + switch_block_conn[from_side][to_side][from_track].nelem = 0; + switch_block_conn[from_side][to_side][from_track].list = + NULL; + } + } + } + } + + if (getEchoEnabled()) { + int i, j, k, l; + FILE *out; + + out = my_fopen("switch_block_conn.echo", "w", 0); + for (l = 0; l < 4; ++l) { + for (k = 0; k < 4; ++k) { + fprintf(out, "Side %d to %d\n", l, k); + for (j = 0; j < nodes_per_chan; ++j) { + fprintf(out, "%d: ", j); + for (i = 0; i < switch_block_conn[l][k][j].nelem; ++i) { + fprintf(out, "%d ", switch_block_conn[l][k][j].list[i]); + } + fprintf(out, "\n"); + } + fprintf(out, "\n"); + } + } + fclose(out); + } + return switch_block_conn; +} + +void free_switch_block_conn(struct s_ivec ***switch_block_conn, + int nodes_per_chan) { + /* Frees the switch_block_conn data structure. */ + + free_ivec_matrix3(switch_block_conn, 0, 3, 0, 3, 0, nodes_per_chan - 1); +} + +#define SBOX_ERROR -1 + +/* This routine permutes the track number to connect for topologies + * SUBSET, UNIVERSAL, and WILTON. I added FULL (for fully flexible topology) + * but the returned value is simply a dummy, since we don't need to permute + * what connections to make for FULL (connect to EVERYTHING) */ +int get_simple_switch_block_track(INP enum e_side from_side, + INP enum e_side to_side, INP int from_track, + INP enum e_switch_block_type switch_block_type, INP int nodes_per_chan) { + + /* This routine returns the track number to which the from_track should * + * connect. It supports three simple, Fs = 3, switch blocks. */ + + int to_track; + + to_track = SBOX_ERROR; /* Can check to see if it's not set later. */ + + if (switch_block_type == SUBSET) { /* NB: Global routing uses SUBSET too */ + to_track = from_track; + } + + /* See S. Wilton Phd thesis, U of T, 1996 p. 103 for details on following. */ + + else if (switch_block_type == WILTON) { + + if (from_side == LEFT) { + + if (to_side == RIGHT) { /* CHANX to CHANX */ + to_track = from_track; + } else if (to_side == TOP) { /* from CHANX to CHANY */ + to_track = (nodes_per_chan - from_track) % nodes_per_chan; + } else if (to_side == BOTTOM) { + to_track = (nodes_per_chan + from_track - 1) % nodes_per_chan; + } + } + + else if (from_side == RIGHT) { + if (to_side == LEFT) { /* CHANX to CHANX */ + to_track = from_track; + } else if (to_side == TOP) { /* from CHANX to CHANY */ + to_track = (nodes_per_chan + from_track - 1) % nodes_per_chan; + } else if (to_side == BOTTOM) { + to_track = (2 * nodes_per_chan - 2 - from_track) + % nodes_per_chan; + } + } + + else if (from_side == BOTTOM) { + if (to_side == TOP) { /* CHANY to CHANY */ + to_track = from_track; + } else if (to_side == LEFT) { /* from CHANY to CHANX */ + to_track = (from_track + 1) % nodes_per_chan; + } else if (to_side == RIGHT) { + to_track = (2 * nodes_per_chan - 2 - from_track) + % nodes_per_chan; + } + } + + else if (from_side == TOP) { + if (to_side == BOTTOM) { /* CHANY to CHANY */ + to_track = from_track; + } else if (to_side == LEFT) { /* from CHANY to CHANX */ + to_track = (nodes_per_chan - from_track) % nodes_per_chan; + } else if (to_side == RIGHT) { + to_track = (from_track + 1) % nodes_per_chan; + } + } + + } + /* End switch_block_type == WILTON case. */ + else if (switch_block_type == UNIVERSAL) { + + if (from_side == LEFT) { + + if (to_side == RIGHT) { /* CHANX to CHANX */ + to_track = from_track; + } else if (to_side == TOP) { /* from CHANX to CHANY */ + to_track = nodes_per_chan - 1 - from_track; + } else if (to_side == BOTTOM) { + to_track = from_track; + } + } + + else if (from_side == RIGHT) { + if (to_side == LEFT) { /* CHANX to CHANX */ + to_track = from_track; + } else if (to_side == TOP) { /* from CHANX to CHANY */ + to_track = from_track; + } else if (to_side == BOTTOM) { + to_track = nodes_per_chan - 1 - from_track; + } + } + + else if (from_side == BOTTOM) { + if (to_side == TOP) { /* CHANY to CHANY */ + to_track = from_track; + } else if (to_side == LEFT) { /* from CHANY to CHANX */ + to_track = from_track; + } else if (to_side == RIGHT) { + to_track = nodes_per_chan - 1 - from_track; + } + } + + else if (from_side == TOP) { + if (to_side == BOTTOM) { /* CHANY to CHANY */ + to_track = from_track; + } else if (to_side == LEFT) { /* from CHANY to CHANX */ + to_track = nodes_per_chan - 1 - from_track; + } else if (to_side == RIGHT) { + to_track = from_track; + } + } + } + + /* End switch_block_type == UNIVERSAL case. */ + /* UDSD Modification by WMF Begin */ + if (switch_block_type == FULL) { /* Just a placeholder. No meaning in reality */ + to_track = from_track; + } + /* UDSD Modification by WMF End */ + + if (to_track == SBOX_ERROR) { + vpr_printf(TIO_MESSAGE_ERROR, "in get_simple_switch_block_track.\n"); + vpr_printf(TIO_MESSAGE_ERROR, "\tUnexpected connection from_side: %d to_side: %d switch_block_type: %d.\n", + from_side, to_side, switch_block_type); + exit(1); + } + + return (to_track); +} diff --git a/vpr7_rram/vpr/SRC/route/rr_graph_sbox.h b/vpr7_rram/vpr/SRC/route/rr_graph_sbox.h new file mode 100755 index 000000000..23b8d5964 --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/rr_graph_sbox.h @@ -0,0 +1,24 @@ +#ifndef RR_GRAPH_SBOX_H +#define RR_GRAPH_SBOX_H + +struct s_ivec get_switch_box_tracks(INP int from_i, + INP int from_j, + INP int from_track, + INP t_rr_type from_type, + INP int to_i, + INP int to_j, + INP t_rr_type to_type, + INP struct s_ivec ***switch_block_conn); + +void free_switch_block_conn(struct s_ivec ***switch_block_conn, + int nodes_per_chan); + +struct s_ivec ***alloc_and_load_switch_block_conn(int nodes_per_chan, + enum e_switch_block_type switch_block_type, int Fs); + +int get_simple_switch_block_track(enum e_side from_side, enum e_side to_side, + int from_track, enum e_switch_block_type switch_block_type, + int nodes_per_chan); + +#endif + diff --git a/vpr7_rram/vpr/SRC/route/rr_graph_swseg.c b/vpr7_rram/vpr/SRC/route/rr_graph_swseg.c new file mode 100644 index 000000000..d923aa14b --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/rr_graph_swseg.c @@ -0,0 +1,704 @@ +#include +#include +#include +#include +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph_util.h" +#include "rr_graph.h" +#include "rr_graph2.h" +#include "rr_graph_sbox.h" +#include "check_rr_graph.h" +#include "rr_graph_timing_params.h" +#include "rr_graph_indexed_data.h" +#include "vpr_utils.h" +#include "read_xml_arch_file.h" +#include "ReadOptions.h" +#include "rr_graph_swseg.h" + +/* Switch Segment Pattern Support + * Xifan TANG, + * EPFL-IC-ISIM-LSI + * July 2014 + */ +enum ret_track_swseg_pattern { + RET_SWSEG_TRACK_DIR_UNMATCH, + RET_SWSEG_TRACK_NON_SEG_LEN_PATTERN, + RET_SWSEG_TRACK_APPLIED +}; + +/** Basic idea: + * Add unbuffered multiplexers(switches) to the length-n segments + * For example: + * clb clb clb clb + * sb ------sb-------sb--------sb--------sb + * BUF BUF BUF BUF BUF + * The above is a length-1 wire. All the multiplexers in thes segments are buffered. + * In this work, we adapt the segments to the following story: + * clb clb clb clb + * sb ------sb-------sb--------sb--------sb + * BUF UNBUF BUF UNBUF BUF + * + * This is called a pattern. The length of the pattern is 2. + * Of cource, we can generalize it to length-n wire and define a pattern + * Pattern: 0 1 1 1 0, Segment length: 1, Pattern length 5 + * The results are as follows: + * clb clb clb clb + * sb ------sb-------sb--------sb--------sb + * BUF UNBUF UNBUF UNBUF BUF + */ + +/** We check the routing tracks one by one to apply the pattern. + * Start from the source of coordinate systems + */ + + +/* The numbering relation between the channels and clbs is: * + * * + * | IO | chan_ | CLB | chan_ | CLB | * + * |grid[0][2] | y[0][2] |grid[1][2] | y[1][2] | grid[2][2]| * + * +-----------+ +-----------+ +-----------+ * + * } capacity in * + * No channel chan_x[1][1] chan_x[2][1] } chan_width * + * } _x[1] * + * +-----------+ +-----------+ +-----------+ * + * | | chan_ | | chan_ | | * + * | IO | y[0][1] | CLB | y[1][1] | CLB | * + * |grid[0][1] | |grid[1][1] | |grid[2][1] | * + * | | | | | | * + * +-----------+ +-----------+ +-----------+ * + * } capacity in * + * chan_x[1][0] chan_x[2][0] } chan_width * + * } _x[0] * + * +-----------+ +-----------+ * + * No | | No | | * + * Channel | IO | Channel | IO | * + * |grid[1][0] | |grid[2][0] | * + * | | | | * + * +-----------+ +-----------+ * + * * + * {=======} {=======} * + * Capacity in Capacity in * + * chan_width_y[0] chan_width_y[1] * + * */ + +/**************************************************************************** + * =========chan_x [ix][iy]========= * + * || *---------------* || * + * || | | || * + * || | | || * + * chan_y | CLB | chan_y * + * [ix-1][iy] | [ix][iy] | [ix][iy] * + * || | | || * + * || | | || * + * || *---------------* || * + * ========chan_x [ix][iy-1]======== * + **************************************************************************** + * Directionality * + * /|\ * + * | INC * + * | * + * <--------- ----------> * + * DEC | INC * + * | * + * | DEC * + * \|/ * + **************************************************************************** + */ +/* We spot a routing track in channel (inx,iny). And start check its segment + * length. When we got the segment length, then apply the pattern to this routing track. + * And move on to the next. + * So, we would check the channels from [0][0] to [0][ny], [nx][0], [nx][ny] + */ + +/*****Subroutine Declaration*****/ +static +int init_chan_seg_detail_params(INP char* chan_type, + INP int curx, + INP int cury, + INP int nx, // Width of FPGA + INP int ny, // Height of FPGA + INP t_seg_details* seg_details_x, + INP t_seg_details* seg_details_y, + OUTP int* seg_num, + OUTP int* chan_num, + //OUTP short* direction, + OUTP t_seg_details* seg_details, + OUTP int* max_len); + +static t_swseg_pattern_inf* +search_swseg_pattern_seg_len(INP int num_swseg_pattern, + INP t_swseg_pattern_inf* swseg_patterns, + INP int seg_len); + +static enum ret_track_swseg_pattern + apply_swseg_pattern_chanx_track(INP int track_id, + INP int chanx_y, + INP int start_x, + INP int end_x, + INP int max_x, + INP int max_y, + INP short direction, + INP int num_swseg_pattern, + INP t_swseg_pattern_inf* swseg_patterns, + INP t_ivec*** L_rr_node_indices, + INP t_seg_details* seg_details_x, + INP t_seg_details* seg_details_y, + INP int* num_changed_chanx); + +static enum ret_track_swseg_pattern + apply_swseg_pattern_chany_track(INP int track_id, + INP int chany_x, + INP int start_y, + INP int end_y, + INP int max_x, + INP int max_y, + INP short direction, + INP int num_swseg_pattern, + INP t_swseg_pattern_inf* swseg_patterns, + INP t_ivec*** L_rr_node_indices, + INP t_seg_details* seg_details_x, + INP t_seg_details* seg_details_y, + INP int* num_changed_chany); + +static int swseg_pattern_change_switch_type(int inode, + t_rr_type chan_type, + t_swseg_pattern_inf swseg_pattern, + int* num_unbuf_mux); + +/*Update the driver_switch of all rr_nodes*/ +void update_rr_nodes_driver_switch(enum e_directionality directionality); + +static boolean* rotate_shift_swseg_pattern(int pattern_length, + boolean* pattern, + int rotate_shift_length); + +/*Start : The top function*/ +int add_rr_graph_switch_segment_pattern(enum e_directionality directionality, + INP int nodes_per_chan, + INP int num_swseg_pattern, + INP t_swseg_pattern_inf* swseg_patterns, + INP t_ivec*** L_rr_node_indices, + INP t_seg_details* seg_details_x, + INP t_seg_details* seg_details_y) { + int ix, iy, itrack; + int num_changed_chanx, num_changed_chany; + t_seg_details* seg_details; + + /*Initialization*/ + seg_details = NULL; + num_changed_chanx = 0; + num_changed_chany = 0; + + // Initialization + update_rr_nodes_driver_switch(directionality); + /* CHAN_X segments + * We start from chan_x [1...nx-1][0] to chan_x [1...nx-1][ny-1]. + * They are the start points of routing tracks in CHANX + */ + /* Ensure we have channel width > 0*/ + assert(nodes_per_chan > 0); + seg_details = seg_details_x; + for (iy = 0; iy < (ny + 1); iy++) { + /* Check each routing track in a channel*/ + for (itrack = 0; itrack < nodes_per_chan; itrack++) { + if (INC_DIRECTION == seg_details[itrack].direction) { + apply_swseg_pattern_chanx_track(itrack, iy, 0, nx, nx, ny, INC_DIRECTION, + num_swseg_pattern, swseg_patterns, L_rr_node_indices, seg_details_x, seg_details_y, + &num_changed_chanx); + } else if (DEC_DIRECTION == seg_details[itrack].direction) { + apply_swseg_pattern_chanx_track(itrack, iy, nx, 0, nx, ny, DEC_DIRECTION, + num_swseg_pattern, swseg_patterns, L_rr_node_indices, seg_details_x, seg_details_y, + &num_changed_chanx); + } + } // Time to change another channelยง + } + /* CHAN_Y segments + * We start from chan_y [0][1...ny-1] to chan_y [nx-1][1...ny-1]. + * They are the start points of routing tracks in CHANX + */ + seg_details = seg_details_y; + for (ix = 0; ix < (nx + 1); ix++) { + /* Check each routing track in a channel*/ + for (itrack = 0; itrack < nodes_per_chan; itrack++) { + if (INC_DIRECTION == seg_details[itrack].direction) { + apply_swseg_pattern_chany_track(itrack, ix, 0, ny, nx, ny, INC_DIRECTION, + num_swseg_pattern, swseg_patterns, L_rr_node_indices, seg_details_x, seg_details_y, + &num_changed_chany); + } else if (DEC_DIRECTION == seg_details[itrack].direction) { + apply_swseg_pattern_chany_track(itrack, ix, ny, 0, nx, ny, DEC_DIRECTION, + num_swseg_pattern, swseg_patterns, L_rr_node_indices, seg_details_x, seg_details_y, + &num_changed_chany); + } + } // Time to change another channelยง + } + + // Show Statistics + vpr_printf(TIO_MESSAGE_INFO,"Switch Segment Pattern applied to %d Channel X.\n",num_changed_chanx); + vpr_printf(TIO_MESSAGE_INFO,"Switch Segment Pattern applied to %d Channel Y.\n",num_changed_chany); + + return 1; // Success +} + +// This part copied from function: view_mux_size_distribution +/* Determine seg_num, chan_num, direction, seg_details, max_len + * according to the side of FPGA + */ +static int init_chan_seg_detail_params(INP char* chan_type, + INP int curx, + INP int cury, + INP int max_x, // Width of FPGA + INP int max_y, // Height of FPGA + INP t_seg_details* seg_details_x, + INP t_seg_details* seg_details_y, + OUTP int* seg_num, + OUTP int* chan_num, + //OUTP short* direction, + OUTP t_seg_details* seg_details, + OUTP int* max_len) { + /*Initialization*/ + (*seg_num) = 0; + (*chan_num) = 0; + //(*direction) = 0; + seg_details = NULL; + (*max_len) = 0; + + if (0 == strcmp(chan_type,"chanx_inc")) { + (*seg_num) = curx; + (*chan_num) = cury; + //(*direction) = INC_DIRECTION; + seg_details = seg_details_x; + (*max_len) = max_x; + } else if (0 == strcmp(chan_type,"chanx_dec")) { + (*seg_num) = curx; + (*chan_num) = cury; + //(*direction) = DEC_DIRECTION; + seg_details = seg_details_x; + (*max_len) = max_x; + } else if (0 == strcmp(chan_type,"chany_inc")) { + (*seg_num) = cury; + (*chan_num) = curx; + //(*direction) = INC_DIRECTION; + seg_details = seg_details_y; + (*max_len) = max_y; + } else if (0 == strcmp(chan_type,"chany_dec")) { + (*seg_num) = cury; + (*chan_num) = curx; + //(*direction) = DEC_DIRECTION; + seg_details = seg_details_y; + (*max_len) = max_y; + } else { + vpr_printf(TIO_MESSAGE_ERROR, "Input channel type: %s. Expect [chanx_inc|chanx_dec|chany_inc|chany_dec].\n",chan_type); + exit(1); + } + return 1; +} + +/** Select a pattern according to the segment length. + * Return NULL if nothing found + */ +static +t_swseg_pattern_inf* search_swseg_pattern_seg_len(INP int num_swseg_pattern, + INP t_swseg_pattern_inf* swseg_patterns, + INP int seg_len) { + int ipattern; + t_swseg_pattern_inf* ret = NULL; + + for (ipattern = 0; ipattern < num_swseg_pattern; ipattern++) { + if (seg_len == swseg_patterns[ipattern].seg_length) { + ret = &swseg_patterns[ipattern]; + } + } + return ret; +} + +/** Apply patterns to all the segments of a track in a chanx + */ +static enum ret_track_swseg_pattern + apply_swseg_pattern_chanx_track(INP int track_id, + INP int chanx_y, + INP int start_x, + INP int end_x, + INP int max_x, + INP int max_y, + INP short direction, + INP int num_swseg_pattern, + INP t_swseg_pattern_inf* swseg_patterns, + INP t_ivec*** L_rr_node_indices, + INP t_seg_details* seg_details_x, + INP t_seg_details* seg_details_y, + INP int* num_changed_chanx) { + int ix, start, end, seg_len; + int seg_num, chan_num, max_len, inode; + t_seg_details* seg_details; + t_swseg_pattern_inf* select_swseg_pattern; + int swseg_offset; + boolean* rotated_pattern; + + /*Initialization*/ + seg_len = 0; + seg_details = seg_details_x; + seg_num = 0; + chan_num = 0; + max_len = 0; + select_swseg_pattern = NULL; + swseg_offset = 0; + rotated_pattern = NULL; + + /* Check directions and ranges*/ + assert((INC_DIRECTION == direction)||(DEC_DIRECTION == direction)); + if (INC_DIRECTION == direction) { + assert((!(start_x < 0))&&(!(end_x > max_x))&&(start_x < end_x)); + } else { + assert((!(end_x < 0))&&(!(start_x > max_x))&&(start_x > end_x)&&(DEC_DIRECTION == direction)); + } + + // Check if the track direction matches + if (direction != seg_details[track_id].direction) { + return RET_SWSEG_TRACK_DIR_UNMATCH; // Direction does not match. Ignore the track + } + // Direction match, try to apply the Switch Segment Pattern + if (INC_DIRECTION == direction) { + for (ix = start_x; ix < (end_x + 1); ix++) { + init_chan_seg_detail_params("chanx_inc", ix, chanx_y, max_x, max_y, seg_details_x, seg_details_y, /* INPUT list */ + &seg_num, &chan_num, seg_details, &max_len); /* OUTPUT list */ + /* Get the start point and end point of the segment*/ + start = get_seg_start(seg_details, track_id, chan_num, seg_num); + end = get_seg_end(seg_details, track_id, start, chan_num, max_len); + assert((start > 0)||(0 == start)); + assert((end > 0)||(0 == end)); + /* Get the segment length*/ + seg_len = end - start + 1; + /* Search a pattern*/ + select_swseg_pattern = search_swseg_pattern_seg_len(num_swseg_pattern, swseg_patterns, seg_len); + /* Nothing found, continue to the next track*/ + if (NULL == select_swseg_pattern) { + return RET_SWSEG_TRACK_NON_SEG_LEN_PATTERN; // Do not need to apply any pattern + } + /* Rotate it*/ + rotated_pattern = rotate_shift_swseg_pattern(select_swseg_pattern->pattern_length,select_swseg_pattern->patterns,chanx_y); + /* Check it the segment starts here*/ + if ((start == seg_num)&&(direction == INC_DIRECTION)) { + /* Get the corresponding rr_node index of CHANX MUX*/ + inode = get_rr_node_index(seg_num, chan_num, CHANX, track_id, L_rr_node_indices); + /* Check if we need to change the switch to a unbuffered one*/ + if (TRUE == rotated_pattern[swseg_offset]) { + swseg_pattern_change_switch_type(inode,CHANX,(*select_swseg_pattern), num_changed_chanx); + } + /* Update the swseg_offset*/ + swseg_offset++; + if ((swseg_offset > select_swseg_pattern->pattern_length) + ||(swseg_offset == select_swseg_pattern->pattern_length)) { + swseg_offset = 0; + } + } + if ((rotated_pattern != NULL)&&(rotated_pattern != select_swseg_pattern->patterns)) { + free(rotated_pattern); + } + } + } else if (DEC_DIRECTION == direction) { + for (ix = start_x; ix > (end_x - 1); ix--) { + init_chan_seg_detail_params("chanx_dec", ix, chanx_y, max_x, max_y, seg_details_x, seg_details_y, /* INPUT list */ + &seg_num, &chan_num, seg_details, &max_len); /* OUTPUT list */ + /* Get the start point and end point of the segment*/ + start = get_seg_start(seg_details, track_id, chan_num, seg_num); + end = get_seg_end(seg_details, track_id, start, chan_num, max_len); + assert((start > 0)||(0 == start)); + assert((end > 0)||(0 == end)); + /* Get the segment length*/ + seg_len = end - start + 1; + /* Search a pattern*/ + select_swseg_pattern = search_swseg_pattern_seg_len(num_swseg_pattern, swseg_patterns, seg_len); + /* Nothing found, continue to the next track*/ + if (NULL == select_swseg_pattern) { + return RET_SWSEG_TRACK_NON_SEG_LEN_PATTERN; // Do not need to apply any pattern + } + /* Rotate it*/ + rotated_pattern = rotate_shift_swseg_pattern(select_swseg_pattern->pattern_length,select_swseg_pattern->patterns,chanx_y); + /* Check it the segment starts here*/ + if ((end == seg_num)&&(direction == DEC_DIRECTION)) { + /* Get the corresponding rr_node index of CHANX MUX*/ + inode = get_rr_node_index(seg_num, chan_num, CHANX, track_id, L_rr_node_indices); + /* Check if we need to change the switch to a unbuffered one*/ + if (TRUE == rotated_pattern[swseg_offset]) { + swseg_pattern_change_switch_type(inode,CHANX,(*select_swseg_pattern), num_changed_chanx); + } + /* Update the swseg_offset*/ + swseg_offset++; + if ((swseg_offset > select_swseg_pattern->pattern_length) + ||(swseg_offset == select_swseg_pattern->pattern_length)) { + swseg_offset = 0; + } + } + if ((rotated_pattern != NULL)&&(rotated_pattern != select_swseg_pattern->patterns)) { + free(rotated_pattern); + } + } + } + + return RET_SWSEG_TRACK_APPLIED; +} + +/** Apply patterns to all the segments of a track in a chany + */ +static enum ret_track_swseg_pattern + apply_swseg_pattern_chany_track(INP int track_id, + INP int chany_x, + INP int start_y, + INP int end_y, + INP int max_x, + INP int max_y, + INP short direction, + INP int num_swseg_pattern, + INP t_swseg_pattern_inf* swseg_patterns, + INP t_ivec*** L_rr_node_indices, + INP t_seg_details* seg_details_x, + INP t_seg_details* seg_details_y, + INP int* num_changed_chany) { + int iy, start, end, seg_len; + int seg_num, chan_num, max_len, inode; + t_seg_details* seg_details; + t_swseg_pattern_inf* select_swseg_pattern; + int swseg_offset; + boolean* rotated_pattern= NULL; + + /*Initialization*/ + seg_len = 0; + seg_details = seg_details_y; + seg_num = 0; + chan_num = 0; + max_len = 0; + select_swseg_pattern = NULL; + swseg_offset = 0; + + /* Check directions and ranges*/ + assert((INC_DIRECTION == direction)||(DEC_DIRECTION == direction)); + if (INC_DIRECTION == direction) { + assert((!(start_y < 0))&&(!(end_y > max_y))&&(start_y < end_y)); + } else { + assert((!(end_y < 0))&&(!(start_y > max_y))&&(start_y > end_y)&&(DEC_DIRECTION == direction)); + } + + // Check if the track direction matches + if (direction != seg_details[track_id].direction) { + return RET_SWSEG_TRACK_DIR_UNMATCH; // Direction does not match. Ignore the track + } + // Direction match, try to apply the Switch Segment Pattern + if (INC_DIRECTION == direction) { + for (iy = start_y; iy < (end_y + 1); iy++) { + init_chan_seg_detail_params("chany_inc", chany_x, iy, max_x, max_y, seg_details_x, seg_details_y, /* INPUT list */ + &seg_num, &chan_num, seg_details, &max_len); /* OUTPUT list */ + /* Get the start point and end point of the segment*/ + start = get_seg_start(seg_details, track_id, chan_num, seg_num); + end = get_seg_end(seg_details, track_id, start, chan_num, max_len); + assert((start > 0)||(0 == start)); + assert((end > 0)||(0 == end)); + /* Get the segment length*/ + seg_len = end - start + 1; + /* Search a pattern*/ + select_swseg_pattern = search_swseg_pattern_seg_len(num_swseg_pattern, swseg_patterns, seg_len); + /* Nothing found, continue to the next track*/ + if (NULL == select_swseg_pattern) { + return RET_SWSEG_TRACK_NON_SEG_LEN_PATTERN; // Do not need to apply any pattern + } + /* Rotate it*/ + rotated_pattern = rotate_shift_swseg_pattern(select_swseg_pattern->pattern_length,select_swseg_pattern->patterns,chany_x); + /* Check it the segment starts here*/ + if ((start == seg_num)&&(direction == INC_DIRECTION)) { + /* Get the corresponding rr_node index of CHANX MUX*/ + inode = get_rr_node_index(chan_num, seg_num, CHANY, track_id, L_rr_node_indices); + /* Check if we need to change the switch to a unbuffered one*/ + if (TRUE == rotated_pattern[swseg_offset]) { + swseg_pattern_change_switch_type(inode,CHANY,(*select_swseg_pattern), num_changed_chany); + } + /* Update the swseg_offset*/ + swseg_offset++; + if ((swseg_offset > select_swseg_pattern->pattern_length) + ||(swseg_offset == select_swseg_pattern->pattern_length)) { + swseg_offset = 0; + } + } + if ((rotated_pattern != NULL)&&(rotated_pattern != select_swseg_pattern->patterns)) { + free(rotated_pattern); + } + } + } else if (DEC_DIRECTION == direction) { + for (iy = start_y; iy > (end_y - 1); iy--) { + init_chan_seg_detail_params("chany_dec", chany_x, iy, max_x, max_y, seg_details_x, seg_details_y, /* INPUT list */ + &seg_num, &chan_num, seg_details, &max_len); /* OUTPUT list */ + /* Get the start point and end point of the segment*/ + start = get_seg_start(seg_details, track_id, chan_num, seg_num); + end = get_seg_end(seg_details, track_id, start, chan_num, max_len); + assert((start > 0)||(0 == start)); + assert((end > 0)||(0 == end)); + /* Get the segment length*/ + seg_len = end - start + 1; + /* Search a pattern*/ + select_swseg_pattern = search_swseg_pattern_seg_len(num_swseg_pattern, swseg_patterns, seg_len); + /* Nothing found, continue to the next track*/ + if (NULL == select_swseg_pattern) { + return RET_SWSEG_TRACK_NON_SEG_LEN_PATTERN; // Do not need to apply any pattern + } + /* Rotate it*/ + rotated_pattern = rotate_shift_swseg_pattern(select_swseg_pattern->pattern_length,select_swseg_pattern->patterns,chany_x); + /* Check it the segment starts here*/ + if ((end == seg_num)&&(direction == DEC_DIRECTION)) { + /* Get the corresponding rr_node index of CHANX MUX*/ + inode = get_rr_node_index(chan_num, seg_num, CHANY, track_id, L_rr_node_indices); + /* Check if we need to change the switch to a unbuffered one*/ + if (TRUE == rotated_pattern[swseg_offset]) { + swseg_pattern_change_switch_type(inode,CHANY,(*select_swseg_pattern), num_changed_chany); + } + /* Update the swseg_offset*/ + swseg_offset++; + if ((swseg_offset > select_swseg_pattern->pattern_length) + ||(swseg_offset == select_swseg_pattern->pattern_length)) { + swseg_offset = 0; + } + } + if ((rotated_pattern != NULL)&&(rotated_pattern != select_swseg_pattern->patterns)) { + free(rotated_pattern); + } + } + } + + return RET_SWSEG_TRACK_APPLIED; +} + + +/* Change the type of switch to a unbuffered one*/ +static +int swseg_pattern_change_switch_type(int cur_node, + t_rr_type chan_type, + t_swseg_pattern_inf swseg_pattern, + int* num_unbuf_mux) { + int iedge, jedge; + int inode, to_node; + + assert((CHANX == chan_type)||(CHANY == chan_type)); + /*Find the rr_node*/ + assert(rr_node+cur_node); + + for (iedge = 0; iedge < rr_node[cur_node].num_edges; iedge++) { + to_node = rr_node[cur_node].edges[iedge]; + if (chan_type == rr_node[to_node].type) { // Only apply to the matched type + rr_node[cur_node].switches[iedge] = swseg_pattern.unbuf_switch; + // Define the driver switch for routing stats + rr_node[to_node].unbuf_switched = 1; + rr_node[to_node].driver_switch = rr_node[cur_node].switches[iedge]; + (*num_unbuf_mux)++; + /* We should change the switches for other rr_nodes that drives this rr_node*/ + for(inode = 0; inode < num_rr_nodes; inode++) { + for (jedge = 0; jedge < rr_node[inode].num_edges; jedge++) { + if (to_node == rr_node[inode].edges[jedge]) { + rr_node[inode].switches[jedge] = rr_node[to_node].driver_switch; + } + } + } + } + } + + return 1; +} + +void update_rr_nodes_driver_switch(enum e_directionality directionality) { + int inode, iedge; + t_rr_type inode_rr_type; + int to_node; + + if (UNI_DIRECTIONAL != directionality) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d])Update_rr_nodes_driver_switch is only valid for uni-directional routing architecture.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Initial all the driver_switch to -1*/ + for (inode = 0; inode < num_rr_nodes; inode++) { + rr_node[inode].driver_switch = -1; + } + + for (inode = 0; inode < num_rr_nodes; inode++) { + inode_rr_type = rr_node[inode].type; + switch (inode_rr_type) { + // We care only switch boxes + case CHANX: + case CHANY: + for (iedge = 0; iedge < rr_node[inode].num_edges; iedge++) { + to_node = rr_node[inode].edges[iedge]; + /* if to_node is a Channel, this is a switch box, + * if to_node is a IPIN, this is a connection box + */ + if ((CHANX == rr_node[to_node].type) + ||(CHANY == rr_node[to_node].type) + ||(IPIN == rr_node[to_node].type)) { + /* We should consider if driver_switch is the same or not*/ + if (-1 == rr_node[to_node].driver_switch) { + rr_node[to_node].driver_switch = rr_node[inode].switches[iedge]; + } else { + assert(rr_node[to_node].driver_switch == rr_node[inode].switches[iedge]); + } + } + } + break; + case OPIN: + for (iedge = 0; iedge < rr_node[inode].num_edges; iedge++) { + to_node = rr_node[inode].edges[iedge]; + /* We care only to_node is a Channel + * Actually, in single driver routing, the switch is a delayless + * However, we have to update all switches + */ + if ((CHANX == rr_node[to_node].type) + ||(CHANY == rr_node[to_node].type)) { + /* We should consider if driver_switch is the same or not*/ + if (-1 == rr_node[to_node].driver_switch) { + rr_node[to_node].driver_switch = rr_node[inode].switches[iedge]; + } else { + assert(rr_node[to_node].driver_switch == rr_node[inode].switches[iedge]); + } + } + } + break; + case IPIN: + /* This is a sink... There is no to_node*/ + default: + break; + } + } +} + +/* Rotate the switch segmentpattern + * Original: 1 0 0 , rotated_shift = 2, return: 0 0 1 + */ +static +boolean* rotate_shift_swseg_pattern(int pattern_length, + boolean* pattern, + int rotate_shift_length) { + boolean* ret = NULL; + int shift_length; + + /* There is no need to do anything if input is NULL*/ + if ((pattern_length == 0)||(pattern_length < 0)) { + return NULL; + } + /* if rotate_shift_length exceeds the pattern lenght, we use mod */ + shift_length = rotate_shift_length % pattern_length; + /* Direct return the pattern */ + if (0 == shift_length) { + return pattern; + } + + /*Alloc*/ + ret = (boolean*)my_malloc(pattern_length*sizeof(boolean)); + /* Initialization*/ + memset(ret, 0, pattern_length*sizeof(boolean)); + + /*Rotate, rotated pattern: shifted part, orignal part*/ + /* Step 1: fill the shifted part*/ + memcpy(ret, pattern+pattern_length-shift_length, sizeof(boolean)*shift_length); + /* Step 2 : fill the rest*/ + memcpy(ret+shift_length, pattern, sizeof(boolean)*(pattern_length-shift_length)); + + /* Return*/ + return ret; +} diff --git a/vpr7_rram/vpr/SRC/route/rr_graph_swseg.h b/vpr7_rram/vpr/SRC/route/rr_graph_swseg.h new file mode 100644 index 000000000..0dea8a590 --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/rr_graph_swseg.h @@ -0,0 +1,12 @@ +/*Declaration*/ +/*The top function*/ +int add_rr_graph_switch_segment_pattern(enum e_directionality directionality, + INP int nodes_per_chan, + INP int num_swseg_pattern, + INP t_swseg_pattern_inf* swseg_patterns, + INP t_ivec*** L_rr_node_indices, + INP t_seg_details* seg_details_x, + INP t_seg_details* seg_details_y); + +void update_rr_nodes_driver_switch(enum e_directionality directionality); + diff --git a/vpr7_rram/vpr/SRC/route/rr_graph_timing_params.c b/vpr7_rram/vpr/SRC/route/rr_graph_timing_params.c new file mode 100755 index 000000000..c6f7ccc42 --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/rr_graph_timing_params.c @@ -0,0 +1,237 @@ +#include +#include +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph.h" +#include "rr_graph_util.h" +#include "rr_graph2.h" +#include "rr_graph_timing_params.h" + +/*mrFPGA: Xifan TANG*/ +#include "mrfpga_globals.h" +/*end */ + +/****************** Subroutine definitions *********************************/ + +void add_rr_graph_C_from_switches(float C_ipin_cblock) { + + /* This routine finishes loading the C elements of the rr_graph. It assumes * + * that when you call it the CHANX and CHANY nodes have had their C set to * + * their metal capacitance, and everything else has C set to 0. The graph * + * connectivity (edges, switch types etc.) must all be loaded too. This * + * routine will add in the capacitance on the CHANX and CHANY nodes due to: * + * * + * 1) The output capacitance of the switches coming from OPINs; * + * 2) The input and output capacitance of the switches between the various * + * wiring (CHANX and CHANY) segments; and * + * 3) The input capacitance of the buffers separating routing tracks from * + * the connection block inputs. */ + + int inode, iedge, switch_index, to_node, maxlen; + int icblock, isblock, iseg_low, iseg_high; + float Cin, Cout; + t_rr_type from_rr_type, to_rr_type; + boolean * cblock_counted; /* [0..max(nx,ny)] -- 0th element unused. */ + float *buffer_Cin; /* [0..max(nx,ny)] */ + boolean buffered; + float *Couts_to_add; /* UDSD */ + + maxlen = std::max(nx, ny) + 1; + cblock_counted = (boolean *) my_calloc(maxlen, sizeof(boolean)); + buffer_Cin = (float *) my_calloc(maxlen, sizeof(float)); + + for (inode = 0; inode < num_rr_nodes; inode++) { + + from_rr_type = rr_node[inode].type; + + if (from_rr_type == CHANX || from_rr_type == CHANY) { + + for (iedge = 0; iedge < rr_node[inode].num_edges; iedge++) { + + to_node = rr_node[inode].edges[iedge]; + to_rr_type = rr_node[to_node].type; + + if (to_rr_type == CHANX || to_rr_type == CHANY) { + + switch_index = rr_node[inode].switches[iedge]; + Cin = switch_inf[switch_index].Cin; + Cout = switch_inf[switch_index].Cout; + buffered = switch_inf[switch_index].buffered; + + /* If both the switch from inode to to_node and the switch from * + * to_node back to inode use bidirectional switches (i.e. pass * + * transistors), there will only be one physical switch for * + * both edges. Hence, I only want to count the capacitance of * + * that switch for one of the two edges. (Note: if there is * + * a pass transistor edge from x to y, I always build the graph * + * so that there is a corresponding edge using the same switch * + * type from y to x.) So, I arbitrarily choose to add in the * + * capacitance in that case of a pass transistor only when * + * processing the the lower inode number. * + * If an edge uses a buffer I always have to add in the output * + * capacitance. I assume that buffers are shared at the same * + * (i,j) location, so only one input capacitance needs to be * + * added for all the buffered switches at that location. If * + * the buffers at that location have different sizes, I use the * + * input capacitance of the largest one. */ + /* mrFPGA : Xifan TANG */ + if (is_junction) { + rr_node[inode].C += 2.0 * memristor_inf.C; + } + if (!is_isolation) { + /* end */ + /* Original VPR*/ + if (!buffered && inode < to_node) { /* Pass transistor. */ + rr_node[inode].C += Cin; + rr_node[to_node].C += Cout; + } + + else if (buffered) { + /* Prevent double counting of capacitance for UDSD */ + if (rr_node[to_node].drivers != SINGLE) { + /* For multiple-driver architectures the output capacitance can + * be added now since each edge is actually a driver */ + rr_node[to_node].C += Cout; + } + isblock = seg_index_of_sblock(inode, to_node); + buffer_Cin[isblock] = std::max(buffer_Cin[isblock], Cin); + } + /* end */ + } + + } + /* End edge to CHANX or CHANY node. */ + else if (to_rr_type == IPIN) { + + /* Code below implements sharing of the track to connection * + * box buffer. I assume there is one such buffer at every * + * segment of the wire at which at least one logic block input * + * connects. */ + + /* mrFPGA : Xifan TANG */ + if (is_junction) { + rr_node[inode].C += memristor_inf.C; + } + if (!is_isolation) { + /* end */ + /* Original VPR*/ + icblock = seg_index_of_cblock(from_rr_type, to_node); + if (cblock_counted[icblock] == FALSE) { + rr_node[inode].C += C_ipin_cblock; + cblock_counted[icblock] = TRUE; + } + } + /* end */ + } + } /* End loop over all edges of a node. */ + + /* Reset the cblock_counted and buffer_Cin arrays, and add buf Cin. */ + + /* Method below would be faster for very unpopulated segments, but I * + * think it would be slower overall for most FPGAs, so commented out. */ + + /* for (iedge=0;iedgeedge = edge; + linked_edge->iswitch = iswitch; + linked_edge->next = head; + + return linked_edge; +} + +#if 0 +void +free_linked_edge_soft(INOUT t_linked_edge * edge_ptr, + INOUT t_linked_edge ** free_list_head_ptr) +{ + + /* This routine does a soft free of the structure pointed to by edge_ptr by * + * adding it to the free list. You have to pass in the address of the * + * head of the free list. */ + + edge_ptr->next = *free_list_head_ptr; + *free_list_head_ptr = edge_ptr; +} +#endif + +int seg_index_of_cblock(t_rr_type from_rr_type, int to_node) { + + /* Returns the segment number (distance along the channel) of the connection * + * box from from_rr_type (CHANX or CHANY) to to_node (IPIN). */ + + if (from_rr_type == CHANX) + return (rr_node[to_node].xlow); + else + /* CHANY */ + return (rr_node[to_node].ylow); +} + +int seg_index_of_sblock(int from_node, int to_node) { + + /* Returns the segment number (distance along the channel) of the switch box * + * box from from_node (CHANX or CHANY) to to_node (CHANX or CHANY). The * + * switch box on the left side of a CHANX segment at (i,j) has seg_index = * + * i-1, while the switch box on the right side of that segment has seg_index * + * = i. CHANY stuff works similarly. Hence the range of values returned is * + * 0 to nx (if from_node is a CHANX) or 0 to ny (if from_node is a CHANY). */ + + t_rr_type from_rr_type, to_rr_type; + + from_rr_type = rr_node[from_node].type; + to_rr_type = rr_node[to_node].type; + + if (from_rr_type == CHANX) { + if (to_rr_type == CHANY) { + return (rr_node[to_node].xlow); + } else if (to_rr_type == CHANX) { + if (rr_node[to_node].xlow > rr_node[from_node].xlow) { /* Going right */ + return (rr_node[from_node].xhigh); + } else { /* Going left */ + return (rr_node[to_node].xhigh); + } + } else { + vpr_printf(TIO_MESSAGE_ERROR, "in seg_index_of_sblock: to_node %d is of type %d.\n", + to_node, to_rr_type); + exit(1); + } + } + /* End from_rr_type is CHANX */ + else if (from_rr_type == CHANY) { + if (to_rr_type == CHANX) { + return (rr_node[to_node].ylow); + } else if (to_rr_type == CHANY) { + if (rr_node[to_node].ylow > rr_node[from_node].ylow) { /* Going up */ + return (rr_node[from_node].yhigh); + } else { /* Going down */ + return (rr_node[to_node].yhigh); + } + } else { + vpr_printf(TIO_MESSAGE_ERROR, "in seg_index_of_sblock: to_node %d is of type %d.\n", + to_node, to_rr_type); + exit(1); + } + } + /* End from_rr_type is CHANY */ + else { + vpr_printf(TIO_MESSAGE_ERROR, "in seg_index_of_sblock: from_node %d is of type %d.\n", + from_node, from_rr_type); + exit(1); + } +} diff --git a/vpr7_rram/vpr/SRC/route/rr_graph_util.h b/vpr7_rram/vpr/SRC/route/rr_graph_util.h new file mode 100755 index 000000000..6db080324 --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/rr_graph_util.h @@ -0,0 +1,16 @@ +struct s_linked_edge { + int edge; + short iswitch; + struct s_linked_edge *next; +}; +typedef struct s_linked_edge t_linked_edge; + +t_linked_edge *insert_in_edge_list(t_linked_edge * head, int edge, + short iswitch); + +void free_linked_edge_soft(t_linked_edge * edge_ptr, + t_linked_edge ** free_list_head_ptr); + +int seg_index_of_cblock(t_rr_type from_rr_type, int to_node); + +int seg_index_of_sblock(int from_node, int to_node); diff --git a/vpr7_rram/vpr/SRC/route/segment_stats.c b/vpr7_rram/vpr/SRC/route/segment_stats.c new file mode 100755 index 000000000..9c5895389 --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/segment_stats.c @@ -0,0 +1,93 @@ +#include +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "segment_stats.h" + +/*************** Variables and defines local to this module ****************/ + +#define LONGLINE 0 + +/******************* Subroutine definitions ********************************/ + +void get_segment_usage_stats(int num_segment, t_segment_inf * segment_inf) { + + /* Computes statistics on the fractional utilization of segments by type * + * (index) and by length. This routine needs a valid rr_graph, and a * + * completed routing. Note that segments cut off by the end of the array * + * are counted as full-length segments (e.g. length 4 even if the last 2 * + * units of wire were chopped off by the chip edge). */ + + int inode, length, seg_type, max_segment_length, cost_index; + int *seg_occ_by_length, *seg_cap_by_length; /* [0..max_segment_length] */ + int *seg_occ_by_type, *seg_cap_by_type; /* [0..num_segment-1] */ + float utilization; + + max_segment_length = 0; + for (seg_type = 0; seg_type < num_segment; seg_type++) { + if (segment_inf[seg_type].longline == FALSE) + max_segment_length = std::max(max_segment_length, + segment_inf[seg_type].length); + } + + seg_occ_by_length = (int *) my_calloc((max_segment_length + 1), + sizeof(int)); + seg_cap_by_length = (int *) my_calloc((max_segment_length + 1), + sizeof(int)); + + seg_occ_by_type = (int *) my_calloc(num_segment, sizeof(int)); + seg_cap_by_type = (int *) my_calloc(num_segment, sizeof(int)); + + for (inode = 0; inode < num_rr_nodes; inode++) { + if (rr_node[inode].type == CHANX || rr_node[inode].type == CHANY) { + cost_index = rr_node[inode].cost_index; + seg_type = rr_indexed_data[cost_index].seg_index; + + if (!segment_inf[seg_type].longline) + length = segment_inf[seg_type].length; + else + length = LONGLINE; + + seg_occ_by_length[length] += rr_node[inode].occ; + seg_cap_by_length[length] += rr_node[inode].capacity; + seg_occ_by_type[seg_type] += rr_node[inode].occ; + seg_cap_by_type[seg_type] += rr_node[inode].capacity; + + } + } + + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "Segment usage by type (index):\n"); + vpr_printf(TIO_MESSAGE_INFO, "Segment type Fractional utilization\n"); + vpr_printf(TIO_MESSAGE_INFO, "------------ ----------------------\n"); + + for (seg_type = 0; seg_type < num_segment; seg_type++) { + if (seg_cap_by_type[seg_type] != 0) { + utilization = (float) seg_occ_by_type[seg_type] / (float) seg_cap_by_type[seg_type]; + vpr_printf(TIO_MESSAGE_INFO, "%8d %5.3g\n", seg_type, utilization); + } + } + + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "Segment usage by length:\n"); + vpr_printf(TIO_MESSAGE_INFO, "Segment length Fractional utilization\n"); + vpr_printf(TIO_MESSAGE_INFO, "-------------- ----------------------\n"); + + for (length = 1; length <= max_segment_length; length++) { + if (seg_cap_by_length[length] != 0) { + utilization = (float) seg_occ_by_length[length] / (float) seg_cap_by_length[length]; + vpr_printf(TIO_MESSAGE_INFO, "%9d %5.3g\n", length, utilization); + } + } + vpr_printf(TIO_MESSAGE_INFO, "\n"); + + if (seg_cap_by_length[LONGLINE] != 0) { + utilization = (float) seg_occ_by_length[LONGLINE] / (float) seg_cap_by_length[LONGLINE]; + vpr_printf(TIO_MESSAGE_INFO, " longline %5.3g\n", utilization); + } + + free(seg_occ_by_length); + free(seg_cap_by_length); + free(seg_occ_by_type); + free(seg_cap_by_type); +} diff --git a/vpr7_rram/vpr/SRC/route/segment_stats.h b/vpr7_rram/vpr/SRC/route/segment_stats.h new file mode 100755 index 000000000..16f1c04f5 --- /dev/null +++ b/vpr7_rram/vpr/SRC/route/segment_stats.h @@ -0,0 +1 @@ +void get_segment_usage_stats(int num_segment, t_segment_inf * segment_inf); diff --git a/vpr7_rram/vpr/SRC/spice/spice_api.c b/vpr7_rram/vpr/SRC/spice/spice_api.c new file mode 100644 index 000000000..3667278fb --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_api.c @@ -0,0 +1,393 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph.h" +#include "vpr_utils.h" +#include "path_delay.h" +#include "stats.h" + +/* Include spice support headers*/ +#include "read_xml_spice_util.h" +#include "linkedlist.h" +#include "fpga_spice_utils.h" +#include "fpga_spice_backannotate_utils.h" +#include "fpga_spice_globals.h" +#include "fpga_spice_bitstream.h" + + +/* Include SPICE generator headers */ +#include "spice_globals.h" +#include "spice_subckt.h" +#include "spice_pbtypes.h" +#include "spice_heads.h" +#include "spice_lut.h" +#include "spice_top_netlist.h" +#include "spice_mux_testbench.h" +#include "spice_grid_testbench.h" +#include "spice_lut_testbench.h" +#include "spice_routing_testbench.h" +#include "spice_hardlogic_testbench.h" +#include "spice_run_scripts.h" + +/* For mrFPGA */ +#ifdef MRFPGA_H +#include "mrfpga_globals.h" +#endif + +/* RUN HSPICE Shell Script Name */ +static char* default_spice_dir_path = "spice_netlists/"; +static char* spice_top_tb_dir_name = "top_tb/"; +static char* spice_grid_tb_dir_name = "grid_tb/"; +static char* spice_pb_mux_tb_dir_name = "pb_mux_tb/"; +static char* spice_cb_mux_tb_dir_name = "cb_mux_tb/"; +static char* spice_sb_mux_tb_dir_name = "sb_mux_tb/"; +static char* spice_cb_tb_dir_name = "cb_tb/"; +static char* spice_sb_tb_dir_name = "sb_tb/"; +static char* spice_lut_tb_dir_name = "lut_tb/"; +static char* spice_hardlogic_tb_dir_name = "hardlogic_tb/"; + +/***** Subroutines Declarations *****/ +static +void init_list_include_netlists(t_spice* spice); + +static +void free_spice_tb_llist(); + +/***** Subroutines *****/ + +static +void init_list_include_netlists(t_spice* spice) { + int i, j, cur; + int to_include = 0; + int num_to_include = 0; + + /* Initialize */ + for (i = 0; i < spice->num_include_netlist; i++) { + FreeSpiceModelNetlist(&(spice->include_netlists[i])); + } + my_free(spice->include_netlists); + spice->include_netlists = NULL; + spice->num_include_netlist = 0; + + /* Generate include netlist list */ + vpr_printf(TIO_MESSAGE_INFO, "Listing SPICE Netlist Names to be included...\n"); + for (i = 0; i < spice->num_spice_model; i++) { + if (NULL != spice->spice_models[i].model_netlist) { + /* Check if this netlist name has already existed in the list */ + to_include = 1; + for (j = 0; j < i; j++) { + if (NULL == spice->spice_models[j].model_netlist) { + continue; + } + if (0 == strcmp(spice->spice_models[j].model_netlist, spice->spice_models[i].model_netlist)) { + to_include = 0; + break; + } + } + /* Increamental */ + if (1 == to_include) { + num_to_include++; + } + } + } + + /* realloc */ + spice->include_netlists = (t_spice_model_netlist*)my_realloc(spice->include_netlists, + sizeof(t_spice_model_netlist)*(num_to_include + spice->num_include_netlist)); + + /* Fill the new included netlists */ + cur = spice->num_include_netlist; + for (i = 0; i < spice->num_spice_model; i++) { + if (NULL != spice->spice_models[i].model_netlist) { + /* Check if this netlist name has already existed in the list */ + to_include = 1; + for (j = 0; j < i; j++) { + if (NULL == spice->spice_models[j].model_netlist) { + continue; + } + if (0 == strcmp(spice->spice_models[j].model_netlist, spice->spice_models[i].model_netlist)) { + to_include = 0; + break; + } + } + /* Increamental */ + if (1 == to_include) { + spice->include_netlists[cur].path = my_strdup(spice->spice_models[i].model_netlist); + spice->include_netlists[cur].included = 0; + vpr_printf(TIO_MESSAGE_INFO, "[%d] %s\n", cur+1, spice->include_netlists[cur].path); + cur++; + } + } + } + /* Check */ + assert(cur == (num_to_include + spice->num_include_netlist)); + /* Update */ + spice->num_include_netlist += num_to_include; + + return; +} + + +static +void free_spice_tb_llist() { + t_llist* temp = tb_head; + + while (temp) { + my_free(((t_spicetb_info*)(temp->dptr))->tb_name); + my_free(temp->dptr); + temp->dptr = NULL; + temp = temp->next; + } + free_llist(tb_head); + + return; +} + +/***** Main Function *****/ +void vpr_print_spice_netlists(t_vpr_setup vpr_setup, + t_arch Arch, + char* circuit_name) { + clock_t t_start; + clock_t t_end; + float run_time_sec; + + int num_clocks = Arch.spice->spice_params.stimulate_params.num_clocks; + int vpr_crit_path_delay = Arch.spice->spice_params.stimulate_params.vpr_crit_path_delay; + + char* spice_dir_formatted = NULL; + char* include_dir_path = NULL; + char* subckt_dir_path = NULL; + char* top_netlist_path = NULL; + char* include_dir_name = vpr_setup.FPGA_SPICE_Opts.SpiceOpts.include_dir; + char* subckt_dir_name = vpr_setup.FPGA_SPICE_Opts.SpiceOpts.subckt_dir; + char* chomped_circuit_name = NULL; + char* chomped_spice_dir = NULL; + char* top_testbench_dir_path = NULL; + char* pb_mux_testbench_dir_path = NULL; + char* cb_mux_testbench_dir_path = NULL; + char* sb_mux_testbench_dir_path = NULL; + char* cb_testbench_dir_path = NULL; + char* sb_testbench_dir_path = NULL; + char* grid_testbench_dir_path = NULL; + char* lut_testbench_dir_path = NULL; + char* hardlogic_testbench_dir_path = NULL; + char* top_testbench_file = NULL; + char* bitstream_file_name = NULL; + char* bitstream_file_path = NULL; + + /* Check if the routing architecture we support*/ + if (UNI_DIRECTIONAL != vpr_setup.RoutingArch.directionality) { + vpr_printf(TIO_MESSAGE_ERROR, "FPGA SPICE netlists only support uni-directional routing architecture!\n"); + exit(1); + } + + /* We don't support mrFPGA */ +#ifdef MRFPGA_H + if (is_mrFPGA) { + vpr_printf(TIO_MESSAGE_ERROR, "FPGA SPICE netlists do not support mrFPGA!\n"); + exit(1); + } +#endif + + /* assign the global variable of SRAM model */ + assert(NULL != Arch.sram_inf.spice_sram_inf_orgz); /* Check !*/ + sram_spice_model = Arch.sram_inf.spice_sram_inf_orgz->spice_model; + sram_spice_orgz_type = Arch.sram_inf.spice_sram_inf_orgz->type; + /* initialize the SRAM organization information struct */ + sram_spice_orgz_info = alloc_one_sram_orgz_info(); + init_sram_orgz_info(sram_spice_orgz_info, sram_spice_orgz_type, sram_spice_model, nx + 2, ny + 2); + /* Report error: SPICE part only support standalone SRAMs */ + if (SPICE_SRAM_STANDALONE != sram_spice_orgz_info->type) { + vpr_printf(TIO_MESSAGE_ERROR, "Currently FPGA SPICE netlist only support standalone SRAM organization!\n"); + exit(1); + } + /* Check all the SRAM port is using the correct SRAM SPICE MODEL */ + config_spice_models_sram_port_spice_model(Arch.spice->num_spice_model, + Arch.spice->spice_models, + Arch.sram_inf.spice_sram_inf_orgz->spice_model); + + /* Assign global variables of input and output pads */ + iopad_spice_model = find_iopad_spice_model(Arch.spice->num_spice_model, Arch.spice->spice_models); + assert(NULL != iopad_spice_model); + + /* Initial Arch SPICE MODELS*/ + /* zero the counter of each spice_model */ + zero_spice_models_cnt(Arch.spice->num_spice_model, Arch.spice->spice_models); + + /* Move to the top-level function: vpr_fpga_spice_tool_suits */ + /* init_check_arch_spice_models(&Arch, &vpr_setup.RoutingArch); */ + init_list_include_netlists(Arch.spice); + + /* Initialize the number of configuration bits of all the grids */ + init_grids_num_conf_bits(sram_spice_orgz_info); + init_grids_num_iopads(); + + /* Add keyword checking */ + /* Move to the top-level function: vpr_fpga_spice_tool_suits */ + /* check_keywords_conflict(Arch); */ + + /*Process the circuit name*/ + split_path_prog_name(circuit_name,'/',&chomped_spice_dir ,&chomped_circuit_name); + + /* Update the global variable : + * the number of mutli-thread used in SPICE simulator */ + spice_sim_multi_thread_num = vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_sim_multi_thread_num; + + /* FPGA-SPICE formally starts*/ + vpr_printf(TIO_MESSAGE_INFO, "\nFPGA-SPICE starts...\n"); + + /* Start Clocking*/ + t_start = clock(); + + /* Format the directory path */ + if (NULL != vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_dir) { + spice_dir_formatted = format_dir_path(vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_dir); + } else { + spice_dir_formatted = format_dir_path(my_strcat(format_dir_path(chomped_spice_dir), + default_spice_dir_path)); + } + + /*Initial directory organization*/ + /* Process include directory */ + (include_dir_path) = my_strcat(spice_dir_formatted,include_dir_name); + /* Process subckt directory */ + (subckt_dir_path) = my_strcat(spice_dir_formatted,subckt_dir_name); + + /* Check the spice folders exists if not we create it.*/ + create_dir_path(spice_dir_formatted); + create_dir_path(include_dir_path); + create_dir_path(subckt_dir_path); + + /* Generate Header files */ + spice_print_headers(include_dir_path, vpr_crit_path_delay, num_clocks, *(Arch.spice)); + + /* Generate sub circuits: Inverter, Buffer, Transmission Gate, LUT, DFF, SRAM, MUX*/ + generate_spice_subckts(subckt_dir_path, &Arch ,&vpr_setup.RoutingArch); + + /* Print MUX testbench if needed */ + if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_print_pb_mux_testbench) { + pb_mux_testbench_dir_path = my_strcat(spice_dir_formatted, spice_pb_mux_tb_dir_name); + create_dir_path(pb_mux_testbench_dir_path); + spice_print_mux_testbench(pb_mux_testbench_dir_path, chomped_circuit_name, + include_dir_path, subckt_dir_path, + rr_node_indices, num_clocks, Arch, + SPICE_PB_MUX_TB, + vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only); + } + + if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_print_cb_mux_testbench) { + cb_mux_testbench_dir_path = my_strcat(spice_dir_formatted, spice_cb_mux_tb_dir_name); + create_dir_path(cb_mux_testbench_dir_path); + spice_print_mux_testbench(cb_mux_testbench_dir_path, chomped_circuit_name, + include_dir_path, subckt_dir_path, + rr_node_indices, num_clocks, Arch, SPICE_CB_MUX_TB, + vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only); + } + + if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_print_sb_mux_testbench) { + sb_mux_testbench_dir_path = my_strcat(spice_dir_formatted, spice_sb_mux_tb_dir_name); + create_dir_path(sb_mux_testbench_dir_path); + spice_print_mux_testbench(sb_mux_testbench_dir_path, chomped_circuit_name, + include_dir_path, subckt_dir_path, + rr_node_indices, num_clocks, Arch, SPICE_SB_MUX_TB, + vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only); + } + + if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_print_cb_testbench) { + cb_testbench_dir_path = my_strcat(spice_dir_formatted, spice_cb_tb_dir_name); + create_dir_path(cb_testbench_dir_path); + spice_print_cb_testbench(cb_testbench_dir_path, chomped_circuit_name, + include_dir_path, subckt_dir_path, + rr_node_indices, num_clocks, Arch, + vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only); + } + + if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_print_sb_testbench) { + sb_testbench_dir_path = my_strcat(spice_dir_formatted, spice_sb_tb_dir_name); + create_dir_path(sb_testbench_dir_path); + spice_print_sb_testbench(sb_testbench_dir_path, chomped_circuit_name, + include_dir_path, subckt_dir_path, + rr_node_indices, num_clocks, Arch, + vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only); + } + + if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_print_lut_testbench) { + lut_testbench_dir_path = my_strcat(spice_dir_formatted, spice_lut_tb_dir_name); + create_dir_path(lut_testbench_dir_path); + spice_print_lut_testbench(lut_testbench_dir_path, chomped_circuit_name, include_dir_path, subckt_dir_path, + rr_node_indices, num_clocks, Arch, vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only); + } + + /* Print hardlogic testbench file if needed */ + if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_print_hardlogic_testbench) { + hardlogic_testbench_dir_path = my_strcat(spice_dir_formatted, spice_hardlogic_tb_dir_name); + create_dir_path(hardlogic_testbench_dir_path); + spice_print_hardlogic_testbench(hardlogic_testbench_dir_path, chomped_circuit_name, include_dir_path, subckt_dir_path, + rr_node_indices, num_clocks, Arch, vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only); + } + + /* Print Grid testbench if needed */ + if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_print_grid_testbench) { + grid_testbench_dir_path = my_strcat(spice_dir_formatted, spice_grid_tb_dir_name); + create_dir_path(grid_testbench_dir_path); + spice_print_grid_testbench(grid_testbench_dir_path, chomped_circuit_name, + include_dir_path, subckt_dir_path, + rr_node_indices, num_clocks, Arch, + vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only); + } + + /* Print Netlists of the given FPGA*/ + if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_print_top_testbench) { + top_testbench_file = my_strcat(chomped_circuit_name, spice_top_testbench_postfix); + bitstream_file_name = my_strcat(chomped_circuit_name, bitstream_spice_file_postfix); + bitstream_file_path = my_strcat(spice_dir_formatted, bitstream_file_name); + /* Process top_netlist_path */ + top_testbench_dir_path = my_strcat(spice_dir_formatted, spice_top_tb_dir_name); + create_dir_path(top_testbench_dir_path); + top_netlist_path = my_strcat(top_testbench_dir_path, top_testbench_file); + spice_print_top_netlist(chomped_circuit_name, top_netlist_path, + include_dir_path, subckt_dir_path, + num_rr_nodes, rr_node, rr_node_indices, num_clocks, *(Arch.spice), + vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only); + /* Dump bitstream file */ + dump_fpga_spice_bitstream(bitstream_file_path, chomped_circuit_name, sram_spice_orgz_info); + } + + + /* Generate a shell script for running HSPICE simulations */ + fprint_run_hspice_shell_script(*(Arch.spice), spice_dir_formatted, subckt_dir_path); + + /* END Clocking*/ + t_end = clock(); + + run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, "SPICE netlists dumping took %g seconds\n", run_time_sec); + + /* Free sram_orgz_info */ + free_sram_orgz_info(sram_spice_orgz_info, + sram_spice_orgz_info->type, + nx + 2, ny + 2); + /* Free tb_llist */ + free_spice_tb_llist(); + /* Free */ + my_free(spice_dir_formatted); + my_free(include_dir_path); + my_free(subckt_dir_path); + + return; +} diff --git a/vpr7_rram/vpr/SRC/spice/spice_api.h b/vpr7_rram/vpr/SRC/spice/spice_api.h new file mode 100644 index 000000000..066a0b296 --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_api.h @@ -0,0 +1,3 @@ +void vpr_print_spice_netlists(t_vpr_setup vpr_setup, + t_arch Arch, + char* circuit_name); diff --git a/vpr7_rram/vpr/SRC/spice/spice_globals.c b/vpr7_rram/vpr/SRC/spice/spice_globals.c new file mode 100644 index 000000000..79ec6cfab --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_globals.c @@ -0,0 +1,109 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +/* Include SPICE support headers*/ +#include +#include "spice_types.h" +#include "linkedlist.h" +#include "fpga_spice_globals.h" +#include "spice_globals.h" + +/* Threshold of max transistor width for each transistor */ +float max_width_per_trans = 5.; + +char* nmos_subckt_name = "vpr_nmos"; +char* pmos_subckt_name = "vpr_pmos"; +char* io_nmos_subckt_name = "vpr_io_nmos"; +char* io_pmos_subckt_name = "vpr_io_pmos"; +char* cpt_subckt_name = "cpt"; +char* mux_basis_posfix = "_basis"; +char* mux_special_basis_posfix = "_special_basis"; +char* nmos_pmos_spice_file_name = "nmos_pmos.sp"; +char* basics_spice_file_name = "inv_buf_trans_gate.sp"; +char* muxes_spice_file_name = "muxes.sp"; +char* rram_veriloga_file_name = "rram_behavior.va"; +char* wires_spice_file_name = "wires.sp"; +char* logic_block_spice_file_name = "logic_blocks.sp"; +char* luts_spice_file_name = "luts.sp"; +char* routing_spice_file_name = "routing.sp"; +char* meas_header_file_name = "meas_params.sp"; +char* stimu_header_file_name = "stimulate_params.sp"; +char* design_param_header_file_name = "design_params.sp"; + +/* Postfix for circuit design parameters */ +char* design_param_postfix_input_buf_size = "_input_buf_size"; +char* design_param_postfix_output_buf_size = "_output_buf_size"; +char* design_param_postfix_pass_gate_logic_pmos_size = "_pgl_pmos_size"; +char* design_param_postfix_pass_gate_logic_nmos_size = "_pgl_nmos_size"; +char* design_param_postfix_wire_param_res_val = "_wire_param_res_val"; +char* design_param_postfix_wire_param_cap_val = "_wire_param_cap_val"; +char* design_param_postfix_rram_ron = "_rram_ron"; +char* design_param_postfix_rram_roff = "_rram_roff"; +char* design_param_postfix_rram_wprog_set_pmos = "_rram_wprog_set_pmos"; +char* design_param_postfix_rram_wprog_set_nmos = "_rram_wprog_set_nmos"; +char* design_param_postfix_rram_wprog_reset_pmos = "_rram_wprog_reset_pmos"; +char* design_param_postfix_rram_wprog_reset_nmos = "_rram_wprog_reset_nmos"; + +/* Testbench names */ +char* spice_top_testbench_postfix = "_top.sp"; +char* spice_grid_testbench_postfix = "_grid_testbench.sp"; +char* spice_pb_mux_testbench_postfix = "_pbmux_testbench.sp"; +char* spice_cb_mux_testbench_postfix = "_cbmux_testbench.sp"; +char* spice_sb_mux_testbench_postfix = "_sbmux_testbench.sp"; +char* spice_cb_testbench_postfix = "_cb_testbench.sp"; +char* spice_sb_testbench_postfix = "_sb_testbench.sp"; +char* spice_lut_testbench_postfix = "_lut_testbench.sp"; +char* spice_dff_testbench_postfix = "_dff_testbench.sp"; +char* spice_hardlogic_testbench_postfix = "_hardlogic_testbench.sp"; +char* spice_io_testbench_postfix = "_io_testbench.sp"; +char* bitstream_spice_file_postfix = ".bitstream"; + +/* SRAM SPICE MODEL should be set as global*/ +t_spice_model* sram_spice_model = NULL; +enum e_sram_orgz sram_spice_orgz_type = SPICE_SRAM_STANDALONE; +t_sram_orgz_info* sram_spice_orgz_info = NULL; + +/* Input and Output Pad spice model. should be set as global */ +t_spice_model* iopad_spice_model = NULL; + +/* Global counters */ +int rram_design_tech = 0; +int num_used_grid_mux_tb = 0; +int num_used_grid_tb = 0; +int num_used_cb_tb = 0; +int num_used_sb_tb = 0; +int num_used_cb_mux_tb = 0; +int num_used_sb_mux_tb = 0; +int num_used_lut_tb = 0; +int num_used_dff_tb = 0; +int num_used_hardlogic_tb = 0; +int num_used_io_tb = 0; + +/* linked-list for all the testbenches */ +t_llist* tb_head = NULL; +/* linked-list for heads of scan-chain */ +t_llist* scan_chain_heads = NULL; + +/* Name of global ports used in all netlists */ +char* spice_tb_global_vdd_port_name = "gvdd"; +char* spice_tb_global_gnd_port_name = "ggnd"; +char* spice_tb_global_config_done_port_name = "gconfig_done"; +char* spice_tb_global_set_port_name = "gset"; +char* spice_tb_global_reset_port_name = "greset"; +char* spice_tb_global_vdd_localrouting_port_name = "gvdd_local_interc"; +char* spice_tb_global_vdd_io_port_name = "gvdd_io"; +char* spice_tb_global_vdd_hardlogic_port_name = "gvdd_hardlogic"; +char* spice_tb_global_vdd_sram_port_name = "gvdd_sram"; +char* spice_tb_global_vdd_lut_sram_port_name = "gvdd_sram_luts"; +char* spice_tb_global_vdd_localrouting_sram_port_name = "gvdd_sram_local_routing"; +char* spice_tb_global_vdd_io_sram_port_name = "gvdd_sram_io"; +char* spice_tb_global_vdd_hardlogic_sram_port_name = "gvdd_sram_hardlogic"; +char* spice_tb_global_vdd_cb_sram_port_name = "gvdd_sram_cbs"; +char* spice_tb_global_vdd_sb_sram_port_name = "gvdd_sram_sbs"; +char* spice_tb_global_clock_port_name = "gclock"; +char* spice_tb_global_vdd_load_port_name = "gvdd_load"; +char* spice_tb_global_port_inv_postfix = "_inv"; + +int spice_sim_multi_thread_num = 8; + diff --git a/vpr7_rram/vpr/SRC/spice/spice_globals.h b/vpr7_rram/vpr/SRC/spice/spice_globals.h new file mode 100644 index 000000000..4f1e0c74c --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_globals.h @@ -0,0 +1,105 @@ +/* global parameters for SPICE support*/ +extern float max_width_per_trans; + +extern char* nmos_subckt_name; +extern char* pmos_subckt_name; +extern char* io_nmos_subckt_name; +extern char* io_pmos_subckt_name; +extern char* cpt_subckt_name; +extern char* rram_veriloga_file_name; +extern char* mux_basis_posfix; +extern char* mux_special_basis_posfix; +extern char* nmos_pmos_spice_file_name; +extern char* basics_spice_file_name; +extern char* muxes_spice_file_name; +extern char* wires_spice_file_name; +extern char* logic_block_spice_file_name; +extern char* luts_spice_file_name; +extern char* routing_spice_file_name; +extern char* meas_header_file_name; +extern char* stimu_header_file_name; +extern char* design_param_header_file_name; + +/* Postfix for circuit design parameters */ +extern char* design_param_postfix_input_buf_size; +extern char* design_param_postfix_output_buf_size; +extern char* design_param_postfix_pass_gate_logic_pmos_size; +extern char* design_param_postfix_pass_gate_logic_nmos_size; +extern char* design_param_postfix_wire_param_res_val; +extern char* design_param_postfix_wire_param_cap_val; +extern char* design_param_postfix_rram_ron; +extern char* design_param_postfix_rram_roff; +extern char* design_param_postfix_rram_wprog_set_pmos; +extern char* design_param_postfix_rram_wprog_set_nmos; +extern char* design_param_postfix_rram_wprog_reset_pmos; +extern char* design_param_postfix_rram_wprog_reset_nmos; + +/* Testbench names */ +extern char* spice_top_testbench_postfix; +extern char* spice_grid_testbench_postfix; +extern char* spice_pb_mux_testbench_postfix; +extern char* spice_cb_mux_testbench_postfix; +extern char* spice_sb_mux_testbench_postfix; +extern char* spice_cb_testbench_postfix; +extern char* spice_sb_testbench_postfix; +extern char* spice_lut_testbench_postfix; +extern char* spice_dff_testbench_postfix; +extern char* spice_hardlogic_testbench_postfix; +extern char* spice_io_testbench_postfix; +extern char* bitstream_spice_file_postfix; +/* RUN HSPICE Shell Script Name */ +/* +extern char* run_hspice_shell_script_name; +extern char* default_spice_dir_path; +extern char* sim_results_dir_name; +extern char* spice_top_tb_dir_name; +extern char* spice_grid_tb_dir_name; +extern char* spice_pb_mux_tb_dir_name; +extern char* spice_cb_mux_tb_dir_name; +extern char* spice_sb_mux_tb_dir_name; +extern char* spice_lut_tb_dir_name; +extern char* spice_dff_tb_dir_name; +*/ + +extern t_spice_model* sram_spice_model; +extern enum e_sram_orgz sram_spice_orgz_type; +extern t_sram_orgz_info* sram_spice_orgz_info; + +extern t_spice_model* iopad_spice_model; + +extern int rram_design_tech; +extern int num_used_grid_mux_tb; +extern int num_used_cb_mux_tb; +extern int num_used_sb_mux_tb; +extern int num_used_grid_tb; +extern int num_used_cb_tb; +extern int num_used_sb_tb; +extern int num_used_lut_tb; +extern int num_used_dff_tb; +extern int num_used_hardlogic_tb; +extern int num_used_io_tb; +extern t_llist* tb_head; +/* Heads of scan-chain */ +extern t_llist* scan_chain_heads; + +/* Name of global ports used in all netlists */ +extern char* spice_tb_global_vdd_port_name; +extern char* spice_tb_global_gnd_port_name; +extern char* spice_tb_global_config_done_port_name; +extern char* spice_tb_global_set_port_name; +extern char* spice_tb_global_reset_port_name; +extern char* spice_tb_global_vdd_localrouting_port_name; +extern char* spice_tb_global_vdd_io_port_name; +extern char* spice_tb_global_vdd_hardlogic_port_name; +extern char* spice_tb_global_vdd_sram_port_name; +extern char* spice_tb_global_vdd_lut_sram_port_name; +extern char* spice_tb_global_vdd_localrouting_sram_port_name; +extern char* spice_tb_global_vdd_io_sram_port_name; +extern char* spice_tb_global_vdd_hardlogic_sram_port_name; +extern char* spice_tb_global_vdd_cb_sram_port_name; +extern char* spice_tb_global_vdd_sb_sram_port_name; +extern char* spice_tb_global_clock_port_name; +extern char* spice_tb_global_vdd_load_port_name; +extern char* spice_tb_global_port_inv_postfix; + +extern int spice_sim_multi_thread_num; diff --git a/vpr7_rram/vpr/SRC/spice/spice_grid_testbench.c b/vpr7_rram/vpr/SRC/spice/spice_grid_testbench.c new file mode 100644 index 000000000..a0ab8b80a --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_grid_testbench.c @@ -0,0 +1,543 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph_util.h" +#include "rr_graph.h" +#include "rr_graph2.h" +#include "vpr_utils.h" + +/* Include spice support headers*/ +#include "linkedlist.h" +#include "fpga_spice_globals.h" +#include "spice_globals.h" +#include "fpga_spice_utils.h" +#include "spice_utils.h" +#include "spice_pbtypes.h" +#include "spice_subckt.h" +#include "spice_grid_testbench.h" + +/* Global variable inside this C-source file*/ +/* +static int num_inv_load = 0; +static int num_noninv_load = 0; +static int num_grid_load = 0; +*/ +static int testbench_load_cnt = 0; +static int tb_num_grid = 0; +static int max_sim_num_clock_cycles = 2; +static int upbound_sim_num_clock_cycles = 2; +static int auto_select_max_sim_num_clock_cycles = TRUE; + +/* Local subroutines only accessible in this C-source file */ +static +void init_spice_grid_testbench_globals(t_spice spice) { + testbench_load_cnt = 0; + tb_num_grid = 0; + auto_select_max_sim_num_clock_cycles = spice.spice_params.meas_params.auto_select_sim_num_clk_cycle; + upbound_sim_num_clock_cycles = spice.spice_params.meas_params.sim_num_clock_cycle + 1; + if (FALSE == auto_select_max_sim_num_clock_cycles) { + max_sim_num_clock_cycles = spice.spice_params.meas_params.sim_num_clock_cycle + 1; + } else { + max_sim_num_clock_cycles = 2; + } +} + +/* Subroutines in this source file*/ +static +void fprint_spice_grid_testbench_global_ports(FILE* fp, int x, int y, + int num_clock, + t_spice spice) { + /* A valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); + exit(1); + } + + /* Print generic global ports*/ + fprint_spice_generic_testbench_global_ports(fp, + sram_spice_orgz_info, + global_ports_head); + + fprintf(fp, ".global %s %s %s\n", + spice_tb_global_vdd_localrouting_port_name, + spice_tb_global_vdd_io_port_name, + spice_tb_global_vdd_hardlogic_port_name); + + /* Print the VDD ports of SRAM belonging to other SPICE module */ + fprintf(fp, ".global %s\n", + spice_tb_global_vdd_localrouting_sram_port_name); + fprintf(fp, ".global %s\n", + spice_tb_global_vdd_lut_sram_port_name); + fprintf(fp, ".global %s\n", + spice_tb_global_vdd_io_sram_port_name); + + /*Global Vdds for LUTs*/ + fprint_grid_global_vdds_spice_model(fp, x, y, SPICE_MODEL_LUT, spice); + + /*Global Vdds for FFs*/ + fprint_grid_global_vdds_spice_model(fp, x, y, SPICE_MODEL_FF, spice); + + /*Global Vdds for IOPADs*/ + fprint_grid_global_vdds_spice_model(fp, x, y, SPICE_MODEL_IOPAD, spice); + + /*Global Vdds for Hardlogics*/ + fprint_grid_global_vdds_spice_model(fp, x, y, SPICE_MODEL_HARDLOGIC, spice); + + return; +} + +void fprint_spice_grid_testbench_call_defined_core_grids(FILE* fp) { + int ix, iy; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* Normal Grids */ + for (ix = 1; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + assert(IO_TYPE != grid[ix][iy].type); + fprintf(fp, "Xgrid[%d][%d] ", ix, iy); + fprint_grid_pins(fp, ix, iy, 1); + fprintf(fp, "gvdd 0 grid[%d][%d]\n", ix, iy); /* Call the name of subckt */ + } + } + + return; +} + +void fprint_spice_grid_testbench_call_one_defined_grid(FILE* fp, int ix, int iy) { + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* if ((NULL == grid[ix][iy].type)||(0 != grid[ix][iy].offset)||(0 == grid[ix][iy].usage)) { */ + if ((NULL == grid[ix][iy].type)||(0 != grid[ix][iy].offset)) { + return; + } + + if (IO_TYPE == grid[ix][iy].type) { + fprintf(fp, "Xgrid[%d][%d] \n", ix, iy); + fprint_io_grid_pins(fp, ix, iy, 1); + fprintf(fp, "+ gvdd 0 grid[%d][%d]\n", ix, iy); /* Call the name of subckt */ + tb_num_grid++; + } else { + fprintf(fp, "Xgrid[%d][%d] \n", ix, iy); + fprint_grid_pins(fp, ix, iy, 1); + fprintf(fp, "+ gvdd 0 grid[%d][%d]\n", ix, iy); /* Call the name of subckt */ + tb_num_grid++; + } + + return; +} + +int get_grid_testbench_one_grid_num_sim_clock_cycles(FILE* fp, + t_spice spice, + t_ivec*** LL_rr_node_indices, + int x, int y) { + int ipin, class_id, side, iheight; + t_type_ptr type = NULL; + int ipin_rr_node_index; + float ipin_density = 0.; + float average_density = 0.; + int avg_density_cnt = 0; + int num_sim_clock_cycles = 0; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + type = grid[x][y].type; + assert(NULL != type); + + average_density = 0.; + avg_density_cnt = 0; + /* For each input pin, we give a stimulate*/ + for (side = 0; side < 4; side++) { + for (iheight = 0; iheight < type->height; iheight++) { + for (ipin = 0; ipin < type->num_pins; ipin++) { + if (1 == type->pinloc[iheight][side][ipin]) { + class_id = type->pin_class[ipin]; + if (RECEIVER == type->class_inf[class_id].type) { + /* Print a voltage source according to density and probability */ + ipin_rr_node_index = get_rr_node_index(x, y, IPIN, ipin, LL_rr_node_indices); + /* Get density and probability */ + ipin_density = get_rr_node_net_density(rr_node[ipin_rr_node_index]); + if (0. < ipin_density) { + average_density += ipin_density; + avg_density_cnt++; + } + } + } + } + } + } + + /* Calculate the num_sim_clock_cycle for this MUX, update global max_sim_clock_cycle in this testbench */ + if (0 < avg_density_cnt) { + average_density = average_density/avg_density_cnt; + } else { + assert(0 == avg_density_cnt); + average_density = 0.; + } + if (TRUE == auto_select_max_sim_num_clock_cycles) { + if (0. == average_density) { + num_sim_clock_cycles = 2; + } else { + assert(0. < average_density); + num_sim_clock_cycles = (int)(1/average_density) + 1; + } + /* for idle blocks, 2 clock cycle is well enough... */ + if (2 < num_sim_clock_cycles) { + num_sim_clock_cycles = upbound_sim_num_clock_cycles; + } else { + num_sim_clock_cycles = 2; + } + if (max_sim_num_clock_cycles < num_sim_clock_cycles) { + max_sim_num_clock_cycles = num_sim_clock_cycles; + } + } else { + num_sim_clock_cycles = max_sim_num_clock_cycles; + } + + return num_sim_clock_cycles; +} + + +void fprint_grid_testbench_one_grid_stimulation(FILE* fp, + t_spice spice, + t_ivec*** LL_rr_node_indices, + int x, int y) { + int ipin, class_id, side, iheight; + t_type_ptr type = NULL; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + type = grid[x][y].type; + assert(NULL != type); + + /* For each input pin, we give a stimulate*/ + for (side = 0; side < 4; side++) { + for (iheight = 0; iheight < type->height; iheight++) { + for (ipin = 0; ipin < type->num_pins; ipin++) { + if (1 == type->pinloc[iheight][side][ipin]) { + class_id = type->pin_class[ipin]; + if (RECEIVER == type->class_inf[class_id].type) { + fprint_spice_testbench_one_grid_pin_stimulation(fp, x, y, iheight, side, ipin, LL_rr_node_indices); + } else if (DRIVER == type->class_inf[class_id].type) { + if (TRUE == run_testbench_load_extraction) { /* Additional switch, default on! */ + fprint_spice_testbench_one_grid_pin_loads(fp, x, y, iheight, side, ipin, &testbench_load_cnt, LL_rr_node_indices); + } + } else { + fprint_stimulate_dangling_one_grid_pin(fp, x, y, iheight, side, ipin, LL_rr_node_indices); + } + } + } + } + } + + return; +} + +static +void fprint_spice_grid_testbench_stimulations(FILE* fp, + int num_clock, + t_spice spice, + int grid_x, int grid_y, + t_ivec*** LL_rr_node_indices) { + /* int ix, iy; */ + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Print generic stimuli */ + fprint_spice_testbench_generic_global_ports_stimuli(fp, num_clock); + + /* Generate global ports stimuli */ + fprint_spice_testbench_global_ports_stimuli(fp, global_ports_head); + + /* SRAM ports */ + /* Every SRAM inputs should have a voltage source */ + fprintf(fp, "***** Global Inputs for SRAMs *****\n"); + fprint_spice_testbench_global_sram_inport_stimuli(fp, sram_spice_orgz_info); + + fprintf(fp, "***** Global VDD for SRAMs *****\n"); + fprint_spice_testbench_global_vdd_port_stimuli(fp, + spice_tb_global_vdd_sram_port_name, + "vsp"); + + /* Global routing Vdds */ + fprint_spice_testbench_global_vdd_port_stimuli(fp, + spice_tb_global_vdd_localrouting_port_name, + "vsp"); + + /* Global Vdds for SRAMs */ + fprint_spice_testbench_global_vdd_port_stimuli(fp, + spice_tb_global_vdd_lut_sram_port_name, + "vsp"); + + fprint_spice_testbench_global_vdd_port_stimuli(fp, + spice_tb_global_vdd_localrouting_sram_port_name, + "vsp"); + + fprint_spice_testbench_global_vdd_port_stimuli(fp, + spice_tb_global_vdd_io_sram_port_name, + "vsp"); + + fprintf(fp, "***** Global VDD for load inverters *****\n"); + fprint_spice_testbench_global_vdd_port_stimuli(fp, + spice_tb_global_vdd_load_port_name, + "vsp"); + + /* Every Hardlogic use an independent Voltage source */ + fprintf(fp, "***** Global VDD for Hard Logics *****\n"); + fprint_grid_splited_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_HARDLOGIC, spice); + + /* Every LUT use an independent Voltage source */ + fprintf(fp, "***** Global VDD for Look-Up Tables (LUTs) *****\n"); + fprint_grid_splited_vdds_spice_model(fp, grid_x, grid_y,SPICE_MODEL_LUT, spice); + + /* Every FF use an independent Voltage source */ + fprintf(fp, "***** Global VDD for Flip-flops (FFs) *****\n"); + fprint_grid_splited_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_FF, spice); + + /* For each grid input port, we generate the voltage pulses */ + fprint_grid_testbench_one_grid_stimulation(fp, spice, LL_rr_node_indices, + grid_x, grid_y); + + return; +} + +static +void fprint_spice_grid_testbench_measurements(FILE* fp, int grid_x, int grid_y, + t_spice spice, + boolean leakage_only) { + /* First cycle reserved for measuring leakage */ + int num_clock_cycle = max_sim_num_clock_cycles; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + fprint_spice_netlist_transient_setting(fp, spice, num_clock_cycle, leakage_only); + fprint_spice_netlist_generic_measurements(fp, spice.spice_params.mc_params, spice.num_spice_model, spice.spice_models); + + /* TODO: Measure the delay of each mapped net and logical block */ + + /* Measure the power */ + /* Leakage ( the first cycle is reserved for leakage measurement) */ + if (TRUE == leakage_only) { + /* Leakage power of SRAMs */ + fprintf(fp, ".measure tran leakage_power_sram_local_routing find p(Vgvdd_sram_local_routing) at=0\n"); + fprintf(fp, ".measure tran leakage_power_sram_luts find p(Vgvdd_sram_luts) at=0\n"); + /* Global power of Local Interconnections*/ + fprintf(fp, ".measure tran leakage_power_local_routing find p(Vgvdd_local_interc) at=0\n"); + } else { + /* Leakage power of SRAMs */ + fprintf(fp, ".measure tran leakage_power_sram_local_routing avg p(Vgvdd_sram_local_routing) from=0 to='clock_period'\n"); + fprintf(fp, ".measure tran leakage_power_sram_luts avg p(Vgvdd_sram_luts) from=0 to='clock_period'\n"); + /* Global power of Local Interconnections*/ + fprintf(fp, ".measure tran leakage_power_local_routing avg p(Vgvdd_local_interc) from=0 to='clock_period'\n"); + } + /* Leakge power of Hard logic */ + fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_HARDLOGIC, SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, spice, leakage_only); + /* Leakage power of LUTs*/ + fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_LUT, SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, spice, leakage_only); + /* Leakage power of FFs*/ + fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_FF, SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, spice, leakage_only); + + if (TRUE == leakage_only) { + return; + } + + /* Dynamic power */ + /* Dynamic power of SRAMs */ + fprintf(fp, ".measure tran dynamic_power_sram_local_routing avg p(Vgvdd_sram_local_routing) from='clock_period' to='%d*clock_period'\n", num_clock_cycle); + fprintf(fp, ".measure tran total_energy_per_cycle_sram_local_routing param='dynamic_power_sram_local_routing*clock_period'\n"); + fprintf(fp, ".measure tran dynamic_power_sram_luts avg p(Vgvdd_sram_luts) from='clock_period' to='%d*clock_period'\n", num_clock_cycle); + fprintf(fp, ".measure tran total_energy_per_cycle_sram_luts param='dynamic_power_sram_luts*clock_period'\n"); + /* Dynamic power of Local Interconnections */ + fprintf(fp, ".measure tran dynamic_power_local_interc avg p(Vgvdd_local_interc) from='clock_period' to='%d*clock_period'\n", num_clock_cycle); + fprintf(fp, ".measure tran total_energy_per_cycle_local_routing param='dynamic_power_local_interc*clock_period'\n"); + /* Dynamic power of Hard Logic */ + fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_HARDLOGIC, SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, spice, leakage_only); + /* Dynamic power of LUTs */ + fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_LUT, SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, spice, leakage_only); + /* Dynamic power of FFs */ + fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_FF, SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, spice, leakage_only); + + return; +} + +/* Top-level function in this source file */ +int fprint_spice_one_grid_testbench(char* formatted_spice_dir, + char* circuit_name, + char* grid_test_bench_name, + char* include_dir_path, + char* subckt_dir_path, + t_ivec*** LL_rr_node_indices, + int num_clock, + t_arch arch, + int grid_x, int grid_y, + boolean leakage_only) { + FILE* fp = NULL; + char* formatted_subckt_dir_path = format_dir_path(subckt_dir_path); + char* temp_include_file_path = NULL; + char* title = my_strcat("FPGA Grid Testbench for Design: ", circuit_name); + char* grid_testbench_file_path = my_strcat(formatted_spice_dir, grid_test_bench_name); + t_llist* temp = NULL; + int used = 0; + + /* Check if the path exists*/ + fp = fopen(grid_testbench_file_path,"w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create Grid Testbench SPICE netlist %s!",__FILE__, __LINE__, grid_testbench_file_path); + exit(1); + } + + + /* Print the title */ + fprint_spice_head(fp, title); + my_free(title); + + /* print technology library and design parameters*/ + /* fprint_tech_lib(fp, arch.spice->tech_lib); */ + + /* Include parameter header files */ + fprint_spice_include_param_headers(fp, include_dir_path); + + /* Include Key subckts */ + fprint_spice_include_key_subckts(fp, subckt_dir_path); + + /* Include user-defined sub-circuit netlist */ + init_include_user_defined_netlists(*(arch.spice)); + fprint_include_user_defined_netlists(fp, *(arch.spice)); + + /* Special subckts for Top-level SPICE netlist */ + fprintf(fp, "****** Include subckt netlists: Look-Up Tables (LUTs) *****\n"); + temp_include_file_path = my_strcat(formatted_subckt_dir_path, luts_spice_file_name); + fprintf(fp, ".include \'%s\'\n", temp_include_file_path); + my_free(temp_include_file_path); + + fprintf(fp, "****** Include subckt netlists: Logic Blocks *****\n"); + temp_include_file_path = my_strcat(formatted_subckt_dir_path, logic_block_spice_file_name); + fprintf(fp, ".include \'%s\'\n", temp_include_file_path); + my_free(temp_include_file_path); + + /* Print simulation temperature and other options for SPICE */ + fprint_spice_options(fp, arch.spice->spice_params); + + /* Global nodes: Vdd for SRAMs, Logic Blocks(Include IO), Switch Boxes, Connection Boxes */ + fprint_spice_grid_testbench_global_ports(fp, grid_x, grid_y, num_clock, (*arch.spice)); + + /* Quote defined Logic blocks subckts (Grids) */ + init_spice_grid_testbench_globals(*(arch.spice)); + + fprint_spice_grid_testbench_call_one_defined_grid(fp, grid_x, grid_y); + + /* Back-anotate activity information to each routing resource node + * (We should have activity of each Grid port) + */ + + /* Add stimulations */ + max_sim_num_clock_cycles = get_grid_testbench_one_grid_num_sim_clock_cycles(fp, (*arch.spice), LL_rr_node_indices, grid_x, grid_y); + fprint_spice_grid_testbench_stimulations(fp, num_clock, (*arch.spice), grid_x, grid_y, LL_rr_node_indices); + + /* Add measurements */ + fprint_spice_grid_testbench_measurements(fp, grid_x, grid_y, (*arch.spice), leakage_only); + + /* SPICE ends*/ + fprintf(fp, ".end\n"); + + /* Close the file*/ + fclose(fp); + + if (0 < tb_num_grid) { + vpr_printf(TIO_MESSAGE_INFO, "Writing Grid[%d][%d] Testbench for %s...\n", grid_x, grid_y, circuit_name); + /* Push the testbench to the linked list */ + tb_head = add_one_spice_tb_info_to_llist(tb_head, grid_testbench_file_path, + max_sim_num_clock_cycles); + used = 1; + } else { + my_remove_file(grid_testbench_file_path); + used = 0; + } + + return used; +} + + +/* Top-level function in this source file */ +void spice_print_grid_testbench(char* formatted_spice_dir, + char* circuit_name, + char* include_dir_path, + char* subckt_dir_path, + t_ivec*** LL_rr_node_indices, + int num_clock, + t_arch arch, + boolean leakage_only) { + char* grid_testbench_name = NULL; + int ix, iy; + int cnt = 0; + int used; + + for (ix = 1; ix < (nx+1); ix++) { + for (iy = 1; iy < (ny+1); iy++) { + grid_testbench_name = (char*)my_malloc(sizeof(char)*( strlen(circuit_name) + + 6 + strlen(my_itoa(ix)) + 1 + + strlen(my_itoa(iy)) + 1 + + strlen(spice_grid_testbench_postfix) + 1 )); + sprintf(grid_testbench_name, "%s_grid%d_%d%s", + circuit_name, ix, iy, spice_grid_testbench_postfix); + used = fprint_spice_one_grid_testbench(formatted_spice_dir, circuit_name, grid_testbench_name, + include_dir_path, subckt_dir_path, LL_rr_node_indices, + num_clock, arch, ix, iy, + leakage_only); + if (1 == used) { + cnt += used; + } + /* free */ + my_free(grid_testbench_name); + } + } + /* Update the global counter */ + num_used_grid_tb = cnt; + vpr_printf(TIO_MESSAGE_INFO,"No. of generated grid testbench = %d\n", num_used_grid_tb); + + return; +} diff --git a/vpr7_rram/vpr/SRC/spice/spice_grid_testbench.h b/vpr7_rram/vpr/SRC/spice/spice_grid_testbench.h new file mode 100644 index 000000000..e3702e564 --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_grid_testbench.h @@ -0,0 +1,9 @@ + +void spice_print_grid_testbench(char* formatted_spice_dir, + char* circuit_name, + char* include_dir_path, + char* subckt_dir_path, + t_ivec*** LL_rr_node_indices, + int num_clock, + t_arch arch, + boolean leakage_only); diff --git a/vpr7_rram/vpr/SRC/spice/spice_hardlogic_testbench.c b/vpr7_rram/vpr/SRC/spice/spice_hardlogic_testbench.c new file mode 100644 index 000000000..e67dbdfa1 --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_hardlogic_testbench.c @@ -0,0 +1,857 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph_util.h" +#include "rr_graph.h" +#include "rr_graph2.h" +#include "vpr_utils.h" + +/* Include spice support headers*/ +#include "linkedlist.h" +#include "fpga_spice_globals.h" +#include "spice_globals.h" +#include "fpga_spice_utils.h" +#include "spice_utils.h" +#include "spice_mux.h" +#include "spice_pbtypes.h" +#include "spice_subckt.h" + +/* local global variables */ +static int tb_num_hardlogic = 0; +static int testbench_load_cnt = 0; +static int upbound_sim_num_clock_cycles = 2; +static int max_sim_num_clock_cycles = 2; +static int auto_select_max_sim_num_clock_cycles = TRUE; + +/* Subroutines in this source file*/ +/* Initialize the global parameters in this source file */ +static +void init_spice_hardlogic_testbench_globals(t_spice spice) { + tb_num_hardlogic = 0; + auto_select_max_sim_num_clock_cycles = spice.spice_params.meas_params.auto_select_sim_num_clk_cycle; + upbound_sim_num_clock_cycles = spice.spice_params.meas_params.sim_num_clock_cycle + 1; + if (FALSE == auto_select_max_sim_num_clock_cycles) { + max_sim_num_clock_cycles = spice.spice_params.meas_params.sim_num_clock_cycle + 1; + } else { + max_sim_num_clock_cycles = 2; + } +} + +/* Print Common global ports in the testbench */ +static +void fprint_spice_hardlogic_testbench_global_ports(FILE* fp, int grid_x, int grid_y, + int num_clock, + t_spice spice) { + /* int i; */ + /* A valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); + exit(1); + } + + + /* Global nodes: Vdd for SRAMs, Logic Blocks(Include IO), Switch Boxes, Connection Boxes */ + /* Print generic global ports*/ + fprint_spice_generic_testbench_global_ports(fp, + sram_spice_orgz_info, + global_ports_head); + /* VDD Load port name */ + fprintf(fp, ".global %s\n", + spice_tb_global_vdd_load_port_name); + + /*Global Vdds for FFs: TODO: TO BE REMOVED */ + fprint_grid_global_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_FF, spice); + + /*Global Vdds for hardlogic */ + fprint_grid_global_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_HARDLOGIC, spice); + + /*Global Vdds for IOPADs (TODO: TO BE MOVED TO IO_TB SOURCE FILE */ + fprint_grid_global_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_IOPAD, spice); + + /* Global VDDs for SRAMs of IOPADs */ + fprintf(fp, ".global %s\n", + spice_tb_global_vdd_io_sram_port_name); + + return; +} + +/* Dump the subckt of a hardlogic and also the input stimuli */ +void fprint_spice_hardlogic_testbench_one_hardlogic(FILE* fp, + char* subckt_name, + t_spice_model* hardlogic_spice_model) { + int iport, ipin; + int num_input_port = 0; + t_spice_model_port** input_ports = NULL; + + int num_output_port = 0; + t_spice_model_port** output_ports = NULL; + + int num_inout_port = 0; + t_spice_model_port** inout_ports = NULL; + + int num_clk_port = 0; + t_spice_model_port** clk_ports = NULL; + + /* A valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert(NULL != hardlogic_spice_model); + + /* identify the type of spice model */ + /* Call defined subckt */ + fprintf(fp, "Xhardlogic_%s[%d] \n", + hardlogic_spice_model->prefix, + hardlogic_spice_model->tb_cnt); + + /* Sequence in dumping ports: + * 1. Global ports + * 2. Input ports + * 3. Output ports + * 4. Inout ports + * 5. Configuration ports + * 6. VDD and GND ports + */ + + /* 1. Global ports */ + if (0 < rec_fprint_spice_model_global_ports(fp, hardlogic_spice_model, FALSE)) { + fprintf(fp, "+ "); + } + + /* 2. Input ports (TODO: check the number of inputs matches the spice model definition) */ + /* Find pb_type input ports */ + input_ports = find_spice_model_ports(hardlogic_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + for (iport = 0; iport < num_input_port; iport++) { + for (ipin = 0; ipin < input_ports[iport]->size; ipin++) { + fprintf(fp, "hardlogic_%s[%d]->%s[%d] ", + hardlogic_spice_model->prefix, + hardlogic_spice_model->tb_cnt, + input_ports[iport]->prefix, ipin); + } + } + if (NULL != input_ports) { + fprintf(fp, "\n"); + fprintf(fp, "+ "); + } + + /* 3. Output ports */ + /* Find pb_type output ports */ + output_ports = find_spice_model_ports(hardlogic_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + for (iport = 0; iport < num_output_port; iport++) { + for (ipin = 0; ipin < output_ports[iport]->size; ipin++) { + fprintf(fp, "hardlogic_%s[%d]->%s[%d] ", + hardlogic_spice_model->prefix, + hardlogic_spice_model->tb_cnt, + output_ports[iport]->prefix, ipin); + } + } + if (NULL != output_ports) { + fprintf(fp, "\n"); + fprintf(fp, "+ "); + } + + /* 4. Inout ports */ + /* INOUT ports */ + /* Find pb_type inout ports */ + inout_ports = find_spice_model_ports(hardlogic_spice_model, SPICE_MODEL_PORT_INOUT, &num_inout_port, TRUE); + for (iport = 0; iport < num_inout_port; iport++) { + for (ipin = 0; ipin < inout_ports[iport]->size; ipin++) { + fprintf(fp, "hardlogic_%s[%d]->%s[%d] ", + hardlogic_spice_model->prefix, + hardlogic_spice_model->tb_cnt, + inout_ports[iport]->prefix, ipin); + } + } + if (NULL != inout_ports) { + fprintf(fp, "\n"); + fprintf(fp, "+ "); + } + + /* Clocks */ + /* Identify if the clock port is a global signal */ + /* Find pb_type clock ports */ + clk_ports = find_spice_model_ports(hardlogic_spice_model, SPICE_MODEL_PORT_CLOCK, &num_clk_port, TRUE); + for (iport = 0; iport < num_clk_port; iport++) { + for (ipin = 0; ipin < clk_ports[iport]->size; ipin++) { + fprintf(fp, "hardlogic_%s[%d]->%s[%d] ", + hardlogic_spice_model->prefix, + hardlogic_spice_model->tb_cnt, + clk_ports[iport]->prefix, ipin); + } + } + if (NULL != clk_ports) { + fprintf(fp, "\n"); + fprintf(fp, "+ "); + } + + /* 5. Configuration ports */ + /* Generate SRAMs? */ + + /* 6. VDD and GND ports */ + fprintf(fp, "%s_%s[%d] %s ", + spice_tb_global_vdd_port_name, hardlogic_spice_model->prefix, hardlogic_spice_model->tb_cnt, + spice_tb_global_gnd_port_name); + fprintf(fp, "\n"); + fprintf(fp, "+ "); + + /* Call the name of subckt */ + fprintf(fp, "%s\n", hardlogic_spice_model->name); + + /* Free */ + my_free(input_ports); + my_free(output_ports); + my_free(inout_ports); + my_free(clk_ports); + + return; +} + +void fprint_spice_hardlogic_testbench_one_pb_graph_node_hardlogic(FILE* fp, + t_pb_graph_node* cur_pb_graph_node, + char* prefix, + int x, int y, + t_ivec*** LL_rr_node_indices) { + int logical_block_index = OPEN; + t_spice_model* pb_spice_model = NULL; + t_pb_type* cur_pb_type = NULL; + int iport, ipin; + + /* For pb_spice_model */ + int num_input_port; + t_spice_model_port** input_ports; + int num_output_port; + t_spice_model_port** output_ports; + + /* Two-dimension arrays, corresponding to the port map [port_id][pin_id] */ + float** input_density = NULL; + float** input_probability = NULL; + int** input_init_value = NULL; + int** input_net_num = NULL; + + char* outport_name = NULL; + t_rr_node* local_rr_graph = NULL; + float average_density = 0.; + int avg_density_cnt = 0; + int num_sim_clock_cycles = 0; + + assert(NULL != cur_pb_graph_node); + assert(NULL != prefix); + + cur_pb_type = cur_pb_graph_node->pb_type; + assert(NULL != cur_pb_type); + pb_spice_model = cur_pb_type->spice_model; + + /* Just a double check*/ + if ((SPICE_MODEL_HARDLOGIC != pb_spice_model->type) + &&(SPICE_MODEL_FF != pb_spice_model->type)) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Type of SPICE models should be either Flip-Flop or Hard Logic!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Try to find the mapped logic block index */ + logical_block_index = find_grid_mapped_logical_block(x, y, + pb_spice_model, prefix); + + /* UNCOMMENT THIS, IF YOU DO NOT WANT SIMULATE THE IDLE ELEMENTS + if (OPEN == logical_block_index) { + return; + } + */ + + /* Call the subckt and give stimulates, measurements */ + if (OPEN != logical_block_index) { + fprintf(fp,"***** Hardlogic[%d]: logical_block_index[%d], gvdd_index[%d]*****\n", + pb_spice_model->cnt, logical_block_index, logical_block[logical_block_index].mapped_spice_model_index); + } else { + fprintf(fp,"***** Hardlogic[%d]: logical_block_index[%d], gvdd_index[%d]*****\n", + pb_spice_model->cnt, -1, -1); + } + + /* Now, we print the SPICE subckt of a hard logic */ + fprint_spice_hardlogic_testbench_one_hardlogic(fp, prefix, pb_spice_model); + + /* Malloc */ + /* First dimension */ + input_density = (float**)my_malloc(sizeof(float*) * cur_pb_graph_node->num_input_ports); + input_probability = (float**)my_malloc(sizeof(float*) * cur_pb_graph_node->num_input_ports); + input_init_value = (int**)my_malloc(sizeof(int*) * cur_pb_graph_node->num_input_ports); + input_net_num = (int**)my_malloc(sizeof(int*) * cur_pb_graph_node->num_input_ports); + /* Second dimension */ + for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { + input_density[iport] = (float*)my_malloc(sizeof(float) * cur_pb_graph_node->num_input_pins[iport]); + input_probability[iport] = (float*)my_malloc(sizeof(float) * cur_pb_graph_node->num_input_pins[iport]); + input_init_value[iport] = (int*)my_malloc(sizeof(int) * cur_pb_graph_node->num_input_pins[iport]); + input_net_num[iport] = (int*)my_malloc(sizeof(int) * cur_pb_graph_node->num_input_pins[iport]); + } + + /* Get activity information */ + for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { + for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) { + /* if we find a mapped logic block */ + if (OPEN != logical_block_index) { + local_rr_graph = logical_block[logical_block_index].pb->parent_pb->rr_graph; + } else { + local_rr_graph = NULL; + } + input_net_num[iport][ipin] = pb_pin_net_num(local_rr_graph, &(cur_pb_graph_node->input_pins[iport][ipin])); + input_density[iport][ipin] = pb_pin_density(local_rr_graph, &(cur_pb_graph_node->input_pins[iport][ipin])); + input_probability[iport][ipin] = pb_pin_probability(local_rr_graph, &(cur_pb_graph_node->input_pins[iport][ipin])); + input_init_value[iport][ipin] = pb_pin_init_value(local_rr_graph, &(cur_pb_graph_node->input_pins[iport][ipin])); + } + } + + /* Add Input stimulates */ + /* Get the input port list of spice model */ + input_ports = find_spice_model_ports(pb_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + /* Check if the port map of current pb_graph_node matches that of the spice model !!!*/ + assert(num_input_port == cur_pb_graph_node->num_input_ports); + for (iport = 0; iport < num_input_port; iport++) { + assert(input_ports[iport]->size == cur_pb_graph_node->num_input_pins[iport]); + for (ipin = 0; ipin < input_ports[iport]->size; ipin++) { + /* Check the port size should match!*/ + fprintf(fp, "Vhardlogic_%s[%d]->%s[%d] hardlogic_%s[%d]->%s[%d] 0 \n", + pb_spice_model->prefix, + pb_spice_model->tb_cnt, + cur_pb_graph_node->input_pins[iport]->port->name, + ipin, + pb_spice_model->prefix, + pb_spice_model->tb_cnt, + input_ports[iport]->prefix, + ipin); + fprint_voltage_pulse_params(fp, input_init_value[iport][ipin], input_density[iport][ipin], input_probability[iport][ipin]); + } + } + + /* Add loads: Recursively */ + /* Get the output port list of spice model */ + output_ports = find_spice_model_ports(pb_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + for (iport = 0; iport < num_output_port; iport++) { + for (ipin = 0; ipin < output_ports[iport]->size; ipin++) { + outport_name = (char*)my_malloc(sizeof(char)*( 10 + + + strlen(pb_spice_model->prefix) + 1 + + strlen(my_itoa(pb_spice_model->tb_cnt)) + + 3 + strlen(output_ports[iport]->prefix) + 1 + + strlen(my_itoa(ipin)) + 2 )); + sprintf(outport_name, "hardlogic_%s[%d]->%s[%d]", + pb_spice_model->prefix, + pb_spice_model->tb_cnt, + output_ports[iport]->prefix, + ipin); + if (TRUE == run_testbench_load_extraction) { /* Additional switch, default on! */ + if (OPEN != logical_block_index) { + fprint_spice_testbench_pb_graph_pin_inv_loads_rec(fp, &testbench_load_cnt, + x, y, + &(cur_pb_graph_node->output_pins[0][0]), + logical_block[logical_block_index].pb, + outport_name, + FALSE, + LL_rr_node_indices); + } else { + fprint_spice_testbench_pb_graph_pin_inv_loads_rec(fp, &testbench_load_cnt, + x, y, + &(cur_pb_graph_node->output_pins[0][0]), + NULL, + outport_name, + FALSE, + LL_rr_node_indices); + } + } + /* Free outport_name in each iteration */ + my_free(outport_name); + } + } + + /* Calculate average density of this hardlogic */ + average_density = 0.; + avg_density_cnt = 0; + for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { + for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) { + assert(!(0 > input_density[iport][ipin])); + if (0. < input_density[iport][ipin]) { + average_density += input_density[iport][ipin]; + avg_density_cnt++; + } + } + } + /* Calculate the num_sim_clock_cycle for this MUX, update global max_sim_clock_cycle in this testbench */ + if (0 < avg_density_cnt) { + average_density = average_density/avg_density_cnt; + } else { + assert(0 == avg_density_cnt); + average_density = 0.; + } + if (0. == average_density) { + num_sim_clock_cycles = 2; + } else { + assert(0. < average_density); + num_sim_clock_cycles = (int)(1/average_density) + 1; + } + if (TRUE == auto_select_max_sim_num_clock_cycles) { + /* for idle blocks, 2 clock cycle is well enough... */ + if (2 < num_sim_clock_cycles) { + num_sim_clock_cycles = upbound_sim_num_clock_cycles; + } else { + num_sim_clock_cycles = 2; + } + if (max_sim_num_clock_cycles < num_sim_clock_cycles) { + max_sim_num_clock_cycles = num_sim_clock_cycles; + } + } else { + num_sim_clock_cycles = max_sim_num_clock_cycles; + } + + /* Mark temporary used */ + if (OPEN != logical_block_index) { + logical_block[logical_block_index].temp_used = 1; + } + + /* Increment the counter of the hardlogic spice model */ + pb_spice_model->tb_cnt++; + tb_num_hardlogic++; + + /* Free */ + for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { + my_free(input_net_num[iport]); + my_free(input_init_value[iport]); + my_free(input_density[iport]); + my_free(input_probability[iport]); + } + my_free(input_net_num); + my_free(input_init_value); + my_free(input_density); + my_free(input_probability); + my_free(input_ports); + my_free(output_ports); + + return; +} + +void fprint_spice_hardlogic_testbench_rec_pb_graph_node_hardlogics(FILE* fp, + t_pb_graph_node* cur_pb_graph_node, + char* prefix, + int x, int y, + t_ivec*** LL_rr_node_indices) { + char* formatted_prefix = format_spice_node_prefix(prefix); + int ipb, jpb, mode_index; + t_pb_type* cur_pb_type = NULL; + char* rec_prefix = NULL; + + assert(NULL != cur_pb_graph_node); + cur_pb_type = cur_pb_graph_node->pb_type; + assert(NULL != cur_pb_type); + /* Until we reach a FF */ + if (NULL != cur_pb_type->spice_model) { + if (SPICE_MODEL_FF != cur_pb_type->spice_model->type) { + return; + } + /* Generate rec_prefix */ + rec_prefix = (char*)my_malloc(sizeof(char) * (strlen(formatted_prefix) + + strlen(cur_pb_type->name) + 1 + + strlen(my_itoa(cur_pb_graph_node->placement_index)) + + 1 + 1)); + sprintf(rec_prefix, "%s%s[%d]", + formatted_prefix, cur_pb_type->name, cur_pb_graph_node->placement_index); + /* Print a hardlogic tb: call spice_model, stimulates */ + fprint_spice_hardlogic_testbench_one_pb_graph_node_hardlogic(fp, cur_pb_graph_node, rec_prefix, x, y, LL_rr_node_indices); + my_free(rec_prefix); + return; + } + + /* Go recursively ... */ + mode_index = find_pb_type_idle_mode_index(*(cur_pb_type)); + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Generate rec_prefix */ + rec_prefix = (char*)my_malloc(sizeof(char) * (strlen(formatted_prefix) + + strlen(cur_pb_type->name) + 1 + + strlen(my_itoa(cur_pb_graph_node->placement_index)) + 7 + + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1)); + sprintf(rec_prefix, "%s%s[%d]_mode[%s]", + formatted_prefix, cur_pb_type->name, cur_pb_graph_node->placement_index, + cur_pb_type->modes[mode_index].name); + /* Go recursively */ + fprint_spice_hardlogic_testbench_rec_pb_graph_node_hardlogics(fp, &(cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), + rec_prefix, x, y, LL_rr_node_indices); + my_free(rec_prefix); + } + } + + return; +} + +void fprint_spice_hardlogic_testbench_rec_pb_hardlogics(FILE* fp, + t_pb* cur_pb, char* prefix, + int x, int y, + t_ivec*** LL_rr_node_indices) { + char* formatted_prefix = format_spice_node_prefix(prefix); + int ipb, jpb; + int mode_index; + char* rec_prefix = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert(NULL != cur_pb); + + /* If we touch the leaf, there is no need print interc*/ + if (NULL != cur_pb->pb_graph_node->pb_type->spice_model) { + if ((SPICE_MODEL_HARDLOGIC != cur_pb->pb_graph_node->pb_type->spice_model->type) + &&(SPICE_MODEL_FF != cur_pb->pb_graph_node->pb_type->spice_model->type)) { + return; + } + /* Generate rec_prefix */ + rec_prefix = (char*)my_malloc(sizeof(char) * (strlen(formatted_prefix) + + strlen(cur_pb->pb_graph_node->pb_type->name) + 1 + + strlen(my_itoa(cur_pb->pb_graph_node->placement_index)) + + 1 + 1)); + sprintf(rec_prefix, "%s%s[%d]", + formatted_prefix, cur_pb->pb_graph_node->pb_type->name, cur_pb->pb_graph_node->placement_index); + /* Print a lut tb: call spice_model, stimulates */ + fprint_spice_hardlogic_testbench_one_pb_graph_node_hardlogic(fp, cur_pb->pb_graph_node, rec_prefix, x, y, LL_rr_node_indices); + my_free(rec_prefix); + return; + } + + /* Go recursively ... */ + mode_index = cur_pb->mode; + if (!(0 < cur_pb->pb_graph_node->pb_type->num_modes)) { + return; + } + for (ipb = 0; ipb < cur_pb->pb_graph_node->pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb->pb_graph_node->pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Generate rec_prefix */ + rec_prefix = (char*)my_malloc(sizeof(char) * (strlen(formatted_prefix) + + strlen(cur_pb->pb_graph_node->pb_type->name) + 1 + + strlen(my_itoa(cur_pb->pb_graph_node->placement_index)) + 7 + + strlen(cur_pb->pb_graph_node->pb_type->modes[mode_index].name) + 1 + 1)); + sprintf(rec_prefix, "%s%s[%d]_mode[%s]", + formatted_prefix, cur_pb->pb_graph_node->pb_type->name, + cur_pb->pb_graph_node->placement_index, + cur_pb->pb_graph_node->pb_type->modes[mode_index].name); + /* Refer to pack/output_clustering.c [LINE 392] */ + if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { + fprint_spice_hardlogic_testbench_rec_pb_hardlogics(fp, &(cur_pb->child_pbs[ipb][jpb]), rec_prefix, x, y, LL_rr_node_indices); + } else { + /* Then we go on */ + fprint_spice_hardlogic_testbench_rec_pb_graph_node_hardlogics(fp, cur_pb->child_pbs[ipb][jpb].pb_graph_node, + rec_prefix, x, y, LL_rr_node_indices); + } + } + } + + return; +} + +void fprint_spice_hardlogic_testbench_call_one_grid_defined_hardlogics(FILE* fp, + int ix, int iy, + t_ivec*** LL_rr_node_indices) { + int iblk; + char* prefix = NULL; + + if (NULL == grid[ix][iy].type) { + return; + } + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + for (iblk = 0; iblk < grid[ix][iy].usage; iblk++) { + prefix = (char*)my_malloc(sizeof(char)* (5 + + strlen(my_itoa(block[grid[ix][iy].blocks[iblk]].x)) + + 2 + strlen(my_itoa(block[grid[ix][iy].blocks[iblk]].y)) + + 3 )); + sprintf(prefix, "grid[%d][%d]_", + block[grid[ix][iy].blocks[iblk]].x, + block[grid[ix][iy].blocks[iblk]].y); + /* Only for mapped block */ + assert(NULL != block[grid[ix][iy].blocks[iblk]].pb); + /* Mark the temporary net_num for the type pins*/ + mark_one_pb_parasitic_nets(block[grid[ix][iy].blocks[iblk]].pb); + /* Go into the hierachy and dump hardlogics */ + fprint_spice_hardlogic_testbench_rec_pb_hardlogics(fp, block[grid[ix][iy].blocks[iblk]].pb, prefix, ix, iy, LL_rr_node_indices); + /* Free */ + my_free(prefix); + } + /* Bypass unused blocks */ + for (iblk = grid[ix][iy].usage; iblk < grid[ix][iy].type->capacity; iblk++) { + prefix = (char*)my_malloc(sizeof(char)* (5 + strlen(my_itoa(ix)) + + 2 + strlen(my_itoa(iy)) + 3 )); + sprintf(prefix, "grid[%d][%d]_", ix, iy); + assert(NULL != grid[ix][iy].type->pb_graph_head); + /* Mark the temporary net_num for the type pins*/ + mark_grid_type_pb_graph_node_pins_temp_net_num(ix, iy); + /* Go into the hierachy and dump hardlogics */ + fprint_spice_hardlogic_testbench_rec_pb_graph_node_hardlogics(fp, grid[ix][iy].type->pb_graph_head, prefix, ix, iy, LL_rr_node_indices); + /* Free */ + my_free(prefix); + } + + return; +} + +void fprint_spice_hardlogic_testbench_call_defined_hardlogics(FILE* fp, + t_ivec*** LL_rr_node_indices) { + int ix, iy; + + for (ix = 1; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + fprint_spice_hardlogic_testbench_call_one_grid_defined_hardlogics(fp, ix, iy, LL_rr_node_indices); + } + } + + return; +} + +static +void fprint_spice_hardlogic_testbench_stimulations(FILE* fp, int grid_x, int grid_y, + int num_clocks, + t_spice spice, + t_ivec*** LL_rr_node_indices) { + /* Print generic stimuli */ + fprint_spice_testbench_generic_global_ports_stimuli(fp, num_clocks); + + /* Generate global ports stimuli */ + fprint_spice_testbench_global_ports_stimuli(fp, global_ports_head); + + /* SRAM ports */ + fprintf(fp, "***** Global Inputs for SRAMs *****\n"); + fprint_spice_testbench_global_sram_inport_stimuli(fp, sram_spice_orgz_info); + + fprintf(fp, "***** Global VDD for SRAMs *****\n"); + fprint_spice_testbench_global_vdd_port_stimuli(fp, + spice_tb_global_vdd_sram_port_name, + "vsp"); + + fprintf(fp, "***** Global VDD for load inverters *****\n"); + fprint_spice_testbench_global_vdd_port_stimuli(fp, + spice_tb_global_vdd_load_port_name, + "vsp"); + /* + fprintf(fp, "***** Global VDD for IOPADs *****\n"); + fprint_spice_testbench_global_vdd_port_stimuli(fp, + spice_tb_global_vdd_io_port_name, + "vsp"); + + fprintf(fp, "***** Global VDD for IOPAD SRAMs *****\n"); + fprint_spice_testbench_global_vdd_port_stimuli(fp, + spice_tb_global_vdd_io_sram_port_name, + "vsp"); + */ + + /* Every LUT use an independent Voltage source */ + fprintf(fp, "***** Global VDD for FFs *****\n"); + fprint_grid_splited_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_FF, spice); + fprintf(fp, "***** Global VDD for Hardlogics *****\n"); + fprint_grid_splited_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_HARDLOGIC, spice); + + return; +} + +void fprint_spice_hardlogic_testbench_measurements(FILE* fp, int grid_x, int grid_y, + t_spice spice, + boolean leakage_only) { + + /* int i; */ + /* First cycle reserved for measuring leakage */ + int num_clock_cycle = max_sim_num_clock_cycles; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + fprint_spice_netlist_transient_setting(fp, spice, num_clock_cycle, leakage_only); + fprint_spice_netlist_generic_measurements(fp, spice.spice_params.mc_params, spice.num_spice_model, spice.spice_models); + + /* TODO: Measure the delay of each mapped net and logical block */ + + /* Measure the power */ + /* Leakage ( the first cycle is reserved for leakage measurement) */ + /* Leakage power of FFs*/ + fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_FF, SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, spice, leakage_only); + /* Leakage power of Hardlogic */ + fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_HARDLOGIC, SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, spice, leakage_only); + + if (TRUE == leakage_only) { + return; + } + + /* Dynamic power */ + /* Dynamic power of FFs */ + fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_FF, SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, spice, leakage_only); + + /* Dynamic power of Hardlogics */ + fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_HARDLOGIC, SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, spice, leakage_only); + + return; +} + +/* Top-level function in this source file */ +int fprint_spice_one_hardlogic_testbench(char* formatted_spice_dir, + char* circuit_name, + char* hardlogic_testbench_name, + char* include_dir_path, + char* subckt_dir_path, + t_ivec*** LL_rr_node_indices, + int num_clock, + t_arch arch, + int grid_x, int grid_y, + boolean leakage_only) { + FILE* fp = NULL; + char* formatted_subckt_dir_path = format_dir_path(subckt_dir_path); + char* temp_include_file_path = NULL; + char* title = my_strcat("FPGA Hard Logic Testbench for Design: ", circuit_name); + char* hardlogic_testbench_file_path = my_strcat(formatted_spice_dir, hardlogic_testbench_name); + int used; + + /* Check if the path exists*/ + fp = fopen(hardlogic_testbench_file_path,"w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create DFF Testbench SPICE netlist %s!",__FILE__, __LINE__, + hardlogic_testbench_file_path); + exit(1); + } + + /* Reset tb_cnt for all the spice models */ + init_spice_models_grid_tb_cnt(arch.spice->num_spice_model, arch.spice->spice_models, grid_x, grid_y); + + /* vpr_printf(TIO_MESSAGE_INFO, "Writing DFF Testbench for %s...\n", circuit_name); */ + testbench_load_cnt = 0; + + /* Print the title */ + fprint_spice_head(fp, title); + my_free(title); + + /* print technology library and design parameters*/ + /* fprint_tech_lib(fp, arch.spice->tech_lib);*/ + + /* Include parameter header files */ + fprint_spice_include_param_headers(fp, include_dir_path); + + /* Include Key subckts */ + fprint_spice_include_key_subckts(fp, subckt_dir_path); + + /* Include user-defined sub-circuit netlist */ + init_include_user_defined_netlists(*(arch.spice)); + fprint_include_user_defined_netlists(fp, *(arch.spice)); + + /* Print simulation temperature and other options for SPICE */ + fprint_spice_options(fp, arch.spice->spice_params); + + /* Global nodes: Vdd for SRAMs, Logic Blocks(Include IO), Switch Boxes, Connection Boxes */ + fprint_spice_hardlogic_testbench_global_ports(fp, grid_x, grid_y, num_clock, (*arch.spice)); + + /* Quote defined Logic blocks subckts (Grids) */ + init_spice_hardlogic_testbench_globals(*(arch.spice)); + init_logical_block_spice_model_type_temp_used(arch.spice->num_spice_model, arch.spice->spice_models, SPICE_MODEL_FF); + init_logical_block_spice_model_type_temp_used(arch.spice->num_spice_model, arch.spice->spice_models, SPICE_MODEL_HARDLOGIC); + + /* Now start our job formally: dump hard logic circuit one by one */ + fprint_spice_hardlogic_testbench_call_one_grid_defined_hardlogics(fp, grid_x, grid_y, LL_rr_node_indices); + + /* Back-anotate activity information to each routing resource node + * (We should have activity of each Grid port) + */ + + /* Check if the all hardlogic located in this grid have been printed */ + check_spice_models_grid_tb_cnt(arch.spice->num_spice_model, arch.spice->spice_models, grid_x, grid_y, SPICE_MODEL_FF); + check_spice_models_grid_tb_cnt(arch.spice->num_spice_model, arch.spice->spice_models, grid_x, grid_y, SPICE_MODEL_HARDLOGIC); + + /* Add stimulations */ + fprint_spice_hardlogic_testbench_stimulations(fp, grid_x, grid_y, num_clock, (*arch.spice), LL_rr_node_indices); + + /* Add measurements */ + fprint_spice_hardlogic_testbench_measurements(fp, grid_x, grid_y, (*arch.spice), leakage_only); + + /* SPICE ends*/ + fprintf(fp, ".end\n"); + + /* Close the file*/ + fclose(fp); + + if (0 < tb_num_hardlogic) { + vpr_printf(TIO_MESSAGE_INFO, "Writing Grid[%d][%d] SPICE Hard Logic Testbench for %s...\n", + grid_x, grid_y, circuit_name); + /* Push the testbench to the linked list */ + tb_head = add_one_spice_tb_info_to_llist(tb_head, hardlogic_testbench_file_path, + max_sim_num_clock_cycles); + used = 1; + } else { + /* Remove the file generated */ + my_remove_file(hardlogic_testbench_file_path); + used = 0; + } + + return used; +} + +/* Top-level function in this source file */ +void spice_print_hardlogic_testbench(char* formatted_spice_dir, + char* circuit_name, + char* include_dir_path, + char* subckt_dir_path, + t_ivec*** LL_rr_node_indices, + int num_clock, + t_arch arch, + boolean leakage_only) { + char* hardlogic_testbench_name = NULL; + int ix, iy; + int cnt = 0; + int used = 0; + + for (ix = 1; ix < (nx+1); ix++) { + for (iy = 1; iy < (ny+1); iy++) { + /* Name the testbench */ + hardlogic_testbench_name = (char*)my_malloc(sizeof(char)*( strlen(circuit_name) + + 6 + strlen(my_itoa(ix)) + 1 + + strlen(my_itoa(iy)) + 1 + + strlen(spice_hardlogic_testbench_postfix) + 1 )); + sprintf(hardlogic_testbench_name, "%s_grid%d_%d%s", + circuit_name, ix, iy, spice_hardlogic_testbench_postfix); + /* Start building one testbench */ + used = fprint_spice_one_hardlogic_testbench(formatted_spice_dir, circuit_name, hardlogic_testbench_name, + include_dir_path, subckt_dir_path, LL_rr_node_indices, + num_clock, arch, ix, iy, + leakage_only); + if (1 == used) { + cnt += used; + } + /* free */ + my_free(hardlogic_testbench_name); + } + } + /* Update the global counter */ + num_used_hardlogic_tb = cnt; + vpr_printf(TIO_MESSAGE_INFO,"No. of generated hard logic testbench = %d\n", num_used_hardlogic_tb); + + return; +} + diff --git a/vpr7_rram/vpr/SRC/spice/spice_hardlogic_testbench.h b/vpr7_rram/vpr/SRC/spice/spice_hardlogic_testbench.h new file mode 100644 index 000000000..318ffa62f --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_hardlogic_testbench.h @@ -0,0 +1,9 @@ + +void spice_print_hardlogic_testbench(char* formatted_spice_dir, + char* circuit_name, + char* include_dir_path, + char* subckt_dir_path, + t_ivec*** LL_rr_node_indices, + int num_clock, + t_arch arch, + boolean leakage_only); diff --git a/vpr7_rram/vpr/SRC/spice/spice_heads.c b/vpr7_rram/vpr/SRC/spice/spice_heads.c new file mode 100644 index 000000000..ec242f978 --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_heads.c @@ -0,0 +1,270 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph.h" +#include "vpr_utils.h" + +/* Include spice support headers*/ +#include "linkedlist.h" +#include "fpga_spice_globals.h" +#include "spice_globals.h" +#include "fpga_spice_utils.h" +#include "spice_utils.h" +#include "spice_mux.h" +#include "spice_pbtypes.h" +#include "spice_subckt.h" + +/* For mrFPGA */ +#ifdef MRFPGA_H +#include "mrfpga_globals.h" +#endif + +/***** Subroutines Declarations *****/ +static +void fprint_spice_meas_header(char* meas_file_name, + t_spice_meas_params spice_meas_params); + +static +void fprint_spice_stimulate_header(char* stimulate_file_name, + t_spice_stimulate_params spice_stimulate_params, + float vpr_clock_period, + int num_clock); + +/***** Subroutines *****/ +/* Print SPICE Netlists header*/ +/* Print parameters for measurements */ +static +void fprint_spice_meas_header(char* meas_file_name, + t_spice_meas_params spice_meas_params) { + FILE* fp = NULL; + + /* Check */ + assert(NULL != meas_file_name); + + /* Create File */ + fp = fopen(meas_file_name, "w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Failure in create measure header file %s!\n", + __FILE__, __LINE__, meas_file_name); + exit(1); + } + + /* Print parameters */ + fprint_spice_head(fp, "Parameters for measurement"); + fprintf(fp, "***** Parameters For Slew Measurement *****\n"); + fprintf(fp, "***** Rising Edge *****\n"); + fprintf(fp, ".param slew_upper_thres_pct_rise=%g\n", spice_meas_params.slew_upper_thres_pct_rise); + fprintf(fp, ".param slew_lower_thres_pct_rise=%g\n", spice_meas_params.slew_lower_thres_pct_rise); + fprintf(fp, "***** Falling Edge *****\n"); + fprintf(fp, ".param slew_upper_thres_pct_fall=%g\n", spice_meas_params.slew_upper_thres_pct_fall); + fprintf(fp, ".param slew_lower_thres_pct_fall=%g\n", spice_meas_params.slew_lower_thres_pct_fall); + + fprintf(fp, "***** Parameters For Delay Measurement *****\n"); + fprintf(fp, "***** Rising Edge *****\n"); + fprintf(fp, ".param input_thres_pct_rise=%g\n", spice_meas_params.input_thres_pct_rise); + fprintf(fp, ".param output_thres_pct_rise=%g\n", spice_meas_params.output_thres_pct_rise); + fprintf(fp, "***** Falling Edge *****\n"); + fprintf(fp, ".param input_thres_pct_fall=%g\n", spice_meas_params.input_thres_pct_fall); + fprintf(fp, ".param output_thres_pct_fall=%g\n", spice_meas_params.output_thres_pct_fall); + + /* Close File */ + fclose(fp); + + return; +} + +/* Print parameters for measurements */ +static +void fprint_spice_stimulate_header(char* stimulate_file_name, + t_spice_stimulate_params spice_stimulate_params, + float vpr_clock_period, + int num_clock) { + FILE* fp = NULL; + float sim_clock_freq = 0.; + float sim_clock_period = 0.; + + /* Check */ + assert(NULL != stimulate_file_name); + + /* Create File */ + fp = fopen(stimulate_file_name, "w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Failure in create stimulate header file %s!\n", + __FILE__, __LINE__, stimulate_file_name); + exit(1); + } + + fprint_spice_head(fp, "Parameters for Stimulations"); + + /* if estimated clock frequency from VPR is 0. + * this is a combinational circuit, clock frequency will never be used + */ + /* if the clock frequency is not specified in architecture file, + * We define the clock frequency with estimated value and slack + */ + fprintf(fp, "***** Frequency *****\n"); + sim_clock_freq = spice_stimulate_params.op_clock_freq; + /* Simulate clock frequency should be larger than 0 !*/ + assert(0. < sim_clock_freq); /*TODO: check this earlier!!! */ + /* vpr_printf(TIO_MESSAGE_INFO, "Use Clock freqency %.2f [MHz] in SPICE simulation.\n", sim_clock_freq/1e6); */ + fprintf(fp, ".param clock_period=%g\n", 1. / sim_clock_freq); + sim_clock_period = 1./sim_clock_freq; + + /* Print parameters */ + fprintf(fp, "***** Parameters For Input Stimulations *****\n"); + switch (spice_stimulate_params.input_slew_rise_type) { + case SPICE_ABS: + if (sim_clock_period < (spice_stimulate_params.input_slew_rise_time + + spice_stimulate_params.input_slew_fall_time)) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid input_slew_rise_time(%.2g), should be smaller than clock period(%.2g)!\n", + __FILE__, __LINE__, spice_stimulate_params.input_slew_rise_time, sim_clock_period); + exit(1); + } + fprintf(fp, ".param input_slew_pct_rise='%g/clock_period'\n", spice_stimulate_params.input_slew_rise_time); + break; + case SPICE_FRAC: + fprintf(fp, ".param input_slew_pct_rise='%g'\n", spice_stimulate_params.input_slew_rise_time); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid input_slew_rise_type!\n", + __FILE__, __LINE__); + exit(1); + } + + switch (spice_stimulate_params.input_slew_fall_type) { + case SPICE_ABS: + if (sim_clock_period < (spice_stimulate_params.input_slew_rise_time + + spice_stimulate_params.input_slew_fall_time)) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid input_slew_fall_time(%.2g), should be smaller than clock period(%.2g)!\n", + __FILE__, __LINE__, spice_stimulate_params.input_slew_fall_time, sim_clock_period); + exit(1); + } + fprintf(fp, ".param input_slew_pct_fall='%g/clock_period'\n", spice_stimulate_params.input_slew_fall_time); + break; + case SPICE_FRAC: + fprintf(fp, ".param input_slew_pct_fall='%g'\n", spice_stimulate_params.input_slew_fall_time); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid input_slew_fall_type!\n", + __FILE__, __LINE__); + exit(1); + } + + fprintf(fp, "***** Parameters For Clock Stimulations *****\n"); + fprintf(fp, "***** Slew *****\n"); + + switch (spice_stimulate_params.clock_slew_rise_type) { + case SPICE_ABS: + if (sim_clock_period < (spice_stimulate_params.clock_slew_rise_time + + spice_stimulate_params.clock_slew_fall_time)) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid clock_slew_rise_time(%.2g)+clock_slew_fall_time(%.2g), should be smaller than clock period(%.2g)!\n", + __FILE__, __LINE__, spice_stimulate_params.clock_slew_rise_time,spice_stimulate_params.clock_slew_fall_time, sim_clock_period); + exit(1); + } + fprintf(fp, ".param clock_slew_pct_rise='%g/clock_period'\n", spice_stimulate_params.clock_slew_rise_time); + break; + case SPICE_FRAC: + fprintf(fp, ".param clock_slew_pct_rise='%g'\n", spice_stimulate_params.clock_slew_rise_time); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid clock_slew_rise_type!\n", + __FILE__, __LINE__); + exit(1); + } + + switch (spice_stimulate_params.clock_slew_fall_type) { + case SPICE_ABS: + if (sim_clock_period < (spice_stimulate_params.clock_slew_rise_time + + spice_stimulate_params.clock_slew_fall_time)) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid clock_slew_rise_time(%.2g)+clock_slew_fall_time(%.2g), should be smaller than clock period(%.2g)!\n", + __FILE__, __LINE__, spice_stimulate_params.clock_slew_rise_time,spice_stimulate_params.clock_slew_fall_time, sim_clock_period); + exit(1); + } + fprintf(fp, ".param clock_slew_pct_fall='%g/clock_period'\n", spice_stimulate_params.clock_slew_fall_time); + break; + case SPICE_FRAC: + fprintf(fp, ".param clock_slew_pct_fall='%g'\n", spice_stimulate_params.clock_slew_fall_time); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid input_slew_fall_type!\n", + __FILE__, __LINE__); + exit(1); + } + + fclose(fp); + + return; +} + +/* Print parameters for circuit designs */ +static +void fprint_spice_design_param_header(char* design_param_file_name, + t_spice spice) { + FILE* fp = NULL; + + /* Check */ + assert(NULL != design_param_file_name); + + /* Create File */ + fp = fopen(design_param_file_name, "w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Failure in create design parameter header file %s!\n", + __FILE__, __LINE__, design_param_file_name); + exit(1); + } + + fprint_spice_head(fp, "Parameters for Circuit Designs"); + + fprint_tech_lib(fp, + spice.spice_params.mc_params.cmos_variation, + spice.tech_lib); + + /* For transistors */ + fprint_spice_circuit_param(fp, + spice.spice_params.mc_params, + spice.num_spice_model, + spice.spice_models); + + fclose(fp); + + return; +} + + +void spice_print_headers(char* include_dir_path, + float vpr_clock_period, + int num_clock, + t_spice spice) { + char* formatted_include_dir_path = format_dir_path(include_dir_path); + char* meas_header_file_path = NULL; + char* stimu_header_file_path = NULL; + char* design_param_header_file_path = NULL; + + /* measurement header file */ + meas_header_file_path = my_strcat(formatted_include_dir_path, meas_header_file_name); + fprint_spice_meas_header(meas_header_file_path, spice.spice_params.meas_params); + + /* stimulate header file */ + stimu_header_file_path = my_strcat(formatted_include_dir_path, stimu_header_file_name); + fprint_spice_stimulate_header(stimu_header_file_path, spice.spice_params.stimulate_params, vpr_clock_period, num_clock); + + /* design parameter header file */ + design_param_header_file_path = my_strcat(formatted_include_dir_path, design_param_header_file_name); + fprint_spice_design_param_header(design_param_header_file_path, spice); + + return; +} diff --git a/vpr7_rram/vpr/SRC/spice/spice_heads.h b/vpr7_rram/vpr/SRC/spice/spice_heads.h new file mode 100644 index 000000000..30b4b83cf --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_heads.h @@ -0,0 +1,5 @@ + +void spice_print_headers(char* include_dir_path, + float vpr_clock_period, + int num_clock, + t_spice spice); diff --git a/vpr7_rram/vpr/SRC/spice/spice_lut.c b/vpr7_rram/vpr/SRC/spice/spice_lut.c new file mode 100644 index 000000000..d32d634b7 --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_lut.c @@ -0,0 +1,342 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph.h" +#include "rr_graph_swseg.h" +#include "vpr_utils.h" + +/* Include spice support headers*/ +#include "linkedlist.h" +#include "fpga_spice_globals.h" +#include "spice_globals.h" +#include "fpga_spice_utils.h" +#include "spice_utils.h" +#include "spice_mux.h" +#include "spice_pbtypes.h" +#include "spice_lut.h" + + +/***** Subroutines *****/ + +void fprint_spice_lut_subckt(FILE* fp, + t_spice_model spice_model) { + int i; + int num_input_port = 0; + t_spice_model_port** input_ports = NULL; + int num_output_port = 0; + t_spice_model_port** output_ports = NULL; + int num_sram_port = 0; + t_spice_model_port** sram_ports = NULL; + float total_width; + int width_cnt; + + /* Ensure a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler!\n", + __FILE__, __LINE__); + } + + /* Find input ports, output ports and sram ports*/ + input_ports = find_spice_model_ports(&spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + output_ports = find_spice_model_ports(&spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + sram_ports = find_spice_model_ports(&spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); + + /* Check */ + assert(1 == num_input_port); + assert(1 == num_output_port); + assert(1 == num_sram_port); + + fprintf(fp, "***** Auto-generated LUT info: spice_model_name = %s, size = %d *****\n", + spice_model.name, input_ports[0]->size); + /* Define the subckt*/ + fprintf(fp, ".subckt %s ", spice_model.name); /* Subckt name*/ + /* Input ports*/ + for (i = 0; i < input_ports[0]->size; i++) { + fprintf(fp, "%s%d ", input_ports[0]->prefix, i); + } + /* output ports*/ + assert(1 == output_ports[0]->size); + fprintf(fp, "%s ", output_ports[0]->prefix); + /* sram ports */ + for (i = 0; i < sram_ports[0]->size; i++) { + fprintf(fp, "%s%d ", sram_ports[0]->prefix, i); + } + /* local vdd and gnd*/ + fprintf(fp, "svdd sgnd\n"); + + /* Input buffers */ + for (i = 0; i < input_ports[0]->size; i++) { + /* For negative input of LUT MUX*/ + /* Output inverter with maximum size allowed + * until the rest of width is smaller than threshold */ + total_width = spice_model.lut_input_buffer->size * spice_model.lut_input_buffer->f_per_stage; + width_cnt = 0; + while (total_width > max_width_per_trans) { + fprintf(fp, "Xinv0_in%d_no%d %s%d lut_mux_in%d_inv svdd sgnd inv size=\'%g\'", + i, width_cnt, + input_ports[0]->prefix, i, + i, max_width_per_trans); + fprintf(fp, "\n"); + /* Update */ + total_width = total_width - max_width_per_trans; + width_cnt++; + } + /* Print if we still have to */ + if (total_width > 0) { + fprintf(fp, "Xinv0_in%d_no%d %s%d lut_mux_in%d_inv svdd sgnd inv size=\'%g\'", + i, width_cnt, + input_ports[0]->prefix, i, + i, total_width); + fprintf(fp, "\n"); + } + /* For postive input of LUT MUX, we use the tapered_buffer subckt directly */ + assert(1 == spice_model.lut_input_buffer->tapered_buf); + fprintf(fp, "X%s_in%d %s%d lut_mux_in%d svdd sgnd tapbuf_level%d_f%d\n", + spice_model.lut_input_buffer->spice_model->prefix, i, + input_ports[0]->prefix, i, i, + spice_model.lut_input_buffer->tap_buf_level, + spice_model.lut_input_buffer->f_per_stage); + fprintf(fp, "\n"); + } + + /* Output buffers already included in LUT MUX */ + /* LUT MUX*/ + assert(sram_ports[0]->size == (int)pow(2.,(double)(input_ports[0]->size))); + fprintf(fp, "Xlut_mux "); + /* SRAM ports of LUT, they are inputs of lut_muxes*/ + for (i = 0; i < sram_ports[0]->size; i++) { + fprintf(fp, "%s%d ", sram_ports[0]->prefix, i); + } + /* Output port, LUT output is LUT MUX output*/ + fprintf(fp, "%s ", output_ports[0]->prefix); + /* input port, LUT input is LUT MUX sram*/ + for (i = 0; i < input_ports[0]->size; i++) { + fprintf(fp, "lut_mux_in%d lut_mux_in%d_inv ", i, i); + } + /* Local vdd and gnd*/ + fprintf(fp, "svdd sgnd %s_mux_size%d\n", spice_model.name, sram_ports[0]->size); + + /* End of LUT subckt*/ + fprintf(fp, ".eom\n"); + + /* Free */ + free(input_ports); + free(output_ports); + free(sram_ports); + + return; +} + +/* Print LUT subckts into a SPICE file*/ +void generate_spice_luts(char* subckt_dir, + int num_spice_model, + t_spice_model* spice_models) { + FILE* fp = NULL; + char* sp_name = my_strcat(subckt_dir, luts_spice_file_name); + int imodel = 0; + + /* Create FILE*/ + fp = fopen(sp_name, "w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create SPICE netlist %s",__FILE__, __LINE__, wires_spice_file_name); + exit(1); + } + fprint_spice_head(fp,"LUTs"); + + for (imodel = 0; imodel < num_spice_model; imodel++) { + if ((SPICE_MODEL_LUT == spice_models[imodel].type) + &&(NULL == spice_models[imodel].model_netlist)) { + fprint_spice_lut_subckt(fp, spice_models[imodel]); + } + } + + /* Close*/ + fclose(fp); + + return; +} + +void fprint_pb_primitive_lut(FILE* fp, + char* subckt_prefix, + t_logical_block* mapped_logical_block, + t_pb_graph_node* cur_pb_graph_node, + int index, + t_spice_model* spice_model) { + int i; + int num_sram = 0; + int* sram_bits = NULL; /* decoded SRAM bits */ + int truth_table_length = 0; + char** truth_table = NULL; + int lut_size = 0; + int num_input_port = 0; + t_spice_model_port** input_ports = NULL; + int num_output_port = 0; + t_spice_model_port** output_ports = NULL; + int num_sram_port = 0; + t_spice_model_port** sram_ports = NULL; + + char* formatted_subckt_prefix = format_spice_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/ + t_pb_type* cur_pb_type = NULL; + char* port_prefix = NULL; + int cur_num_sram = 0; + char* sram_vdd_port_name = NULL; + + /* Ensure a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Ensure a valid pb_graph_node */ + if (NULL == cur_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb_graph_node!\n", + __FILE__, __LINE__); + exit(1); + } + /* Asserts */ + assert(SPICE_MODEL_LUT == spice_model->type); + + /* Check if this is an idle logical block mapped*/ + if (NULL != mapped_logical_block) { + truth_table = assign_lut_truth_table(mapped_logical_block, &truth_table_length); + /* Back-annotate to logical block */ + mapped_logical_block->mapped_spice_model = spice_model; + mapped_logical_block->mapped_spice_model_index = spice_model->cnt; + } + /* Determine size of LUT*/ + input_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + output_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + sram_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); + assert(1 == num_input_port); + assert(1 == num_output_port); + assert(1 == num_sram_port); + lut_size = input_ports[0]->size; + num_sram = (int)pow(2.,(double)(lut_size)); + assert(num_sram == sram_ports[0]->size); + assert(1 == output_ports[0]->size); + + /* Get current counter of mem_bits, bl and wl */ + cur_num_sram = get_sram_orgz_info_num_mem_bit(sram_spice_orgz_info); + + /* Generate sram bits, use the default value of SRAM port */ + sram_bits = generate_lut_sram_bits(truth_table_length, truth_table, + lut_size, sram_ports[0]->default_val); + + /* Print the subckts*/ + cur_pb_type = cur_pb_graph_node->pb_type; + + if (NULL != mapped_logical_block) { + fprintf(fp, "***** Logical block mapped to this LUT: %s *****\n", + mapped_logical_block->name); + } + + /* Subckt definition*/ + fprintf(fp, ".subckt %s%s[%d] ", formatted_subckt_prefix, cur_pb_type->name, index); + /* Print inputs, outputs, inouts, clocks, NO SRAMs*/ + /* + port_prefix = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(cur_pb_type->name) + 1 + + strlen(my_itoa(index)) + 1 + 1)); + sprintf(port_prefix, "%s%s[%d]", formatted_subckt_prefix, cur_pb_type->name, index); + */ + /* Simplify the prefix, make the SPICE netlist readable*/ + port_prefix = (char*)my_malloc(sizeof(char)* + (strlen(cur_pb_type->name) + 1 + + strlen(my_itoa(index)) + 1 + 1)); + sprintf(port_prefix, "%s[%d]", cur_pb_type->name, index); + + /* Only dump the global ports belonging to a spice_model + * Do not go recursive, we can freely define global ports anywhere in SPICE netlist + */ + rec_fprint_spice_model_global_ports(fp, spice_model, FALSE); + + fprint_pb_type_ports(fp, port_prefix, 0, cur_pb_type); + /* SRAM bits are fixed in this subckt, no need to define them here*/ + /* Local Vdd and gnd*/ + fprintf(fp, "svdd sgnd\n"); + /* Definition ends*/ + + /* Print the encoding in SPICE netlist for debugging */ + fprintf(fp, "***** Truth Table for LUT[%d], size=%d. *****\n", + spice_model->cnt, lut_size); + for (i = 0; i < truth_table_length; i++) { + fprintf(fp,"* %s *\n", truth_table[i]); + } + + fprintf(fp, "***** SRAM bits for LUT[%d], size=%d, num_sram=%d. *****\n", + spice_model->cnt, lut_size, num_sram); + fprintf(fp, "*****"); + for (i = 0; i < num_sram; i++) { + fprintf(fp, "%d", sram_bits[i]); + } + fprintf(fp, "*****\n"); + + /* Call SRAM subckts*/ + /* Give the VDD port name for SRAMs */ + sram_vdd_port_name = (char*)my_malloc(sizeof(char)* + (strlen(spice_tb_global_vdd_lut_sram_port_name) + + 1 )); + sprintf(sram_vdd_port_name, "%s", + spice_tb_global_vdd_lut_sram_port_name); + /* Now Print SRAMs one by one */ + for (i = 0; i < num_sram; i++) { + fprint_spice_one_sram_subckt(fp, sram_spice_orgz_info, spice_model, sram_vdd_port_name); + } + + /* Call LUT subckt*/ + fprintf(fp, "X%s[%d] ", spice_model->prefix, spice_model->cnt); + /* Connect inputs*/ + /* Connect outputs*/ + fprint_pb_type_ports(fp, port_prefix, 0, cur_pb_type); + /* Connect srams*/ + for (i = 0; i < num_sram; i++) { + assert( (0 == sram_bits[i]) || (1 == sram_bits[i]) ); + fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, cur_num_sram + i, sram_bits[i]); + } + + /* vdd should be connected to special global wire gvdd_lut and gnd, + * Every LUT has a special VDD for statistics + */ + fprintf(fp, "gvdd_%s[%d] sgnd %s\n", spice_model->prefix, spice_model->cnt, spice_model->name); + /* TODO: Add a nodeset for convergence */ + + /* End of subckt*/ + fprintf(fp, ".eom\n"); + + /* Store the configuraion bit to linked-list */ + add_sram_conf_bits_to_llist(sram_spice_orgz_info, cur_num_sram, + num_sram, sram_bits); + + spice_model->cnt++; + + /*Free*/ + for (i = 0; i < truth_table_length; i++) { + free(truth_table[i]); + } + free(truth_table); + my_free(formatted_subckt_prefix); + my_free(input_ports); + my_free(output_ports); + my_free(sram_ports); + my_free(sram_bits); + my_free(port_prefix); + my_free(sram_vdd_port_name); + + return; +} diff --git a/vpr7_rram/vpr/SRC/spice/spice_lut.h b/vpr7_rram/vpr/SRC/spice/spice_lut.h new file mode 100644 index 000000000..83da005a6 --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_lut.h @@ -0,0 +1,17 @@ + + + +void fprint_spice_lut_subckt(FILE* fp, + t_spice_model spice_model); + +void generate_spice_luts(char* subckt_dir, + int num_spice_model, + t_spice_model* spice_models); + + +void fprint_pb_primitive_lut(FILE* fp, + char* subckt_prefix, + t_logical_block* mapped_logical_block, + t_pb_graph_node* cur_pb_graph_node, + int index, + t_spice_model* spice_model); diff --git a/vpr7_rram/vpr/SRC/spice/spice_lut_testbench.c b/vpr7_rram/vpr/SRC/spice/spice_lut_testbench.c new file mode 100644 index 000000000..57aa0b335 --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_lut_testbench.c @@ -0,0 +1,743 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph_util.h" +#include "rr_graph.h" +#include "rr_graph2.h" +#include "vpr_utils.h" + +/* Include spice support headers*/ +#include "linkedlist.h" +#include "fpga_spice_globals.h" +#include "spice_globals.h" +#include "fpga_spice_utils.h" +#include "spice_utils.h" +#include "spice_subckt.h" +#include "spice_mux_testbench.h" + +/* local global variables */ +static int tb_num_luts = 0; +static int testbench_load_cnt = 0; +static int upbound_sim_num_clock_cycles = 2; +static int max_sim_num_clock_cycles = 2; +static int auto_select_max_sim_num_clock_cycles = TRUE; + +/* Subroutines in this source file*/ +static +void init_spice_lut_testbench_globals(t_spice spice) { + tb_num_luts = 0; + auto_select_max_sim_num_clock_cycles = spice.spice_params.meas_params.auto_select_sim_num_clk_cycle; + upbound_sim_num_clock_cycles = spice.spice_params.meas_params.sim_num_clock_cycle + 1; + if (FALSE == auto_select_max_sim_num_clock_cycles) { + max_sim_num_clock_cycles = spice.spice_params.meas_params.sim_num_clock_cycle + 1; + } else { + max_sim_num_clock_cycles = 2; + } +} + +static +void fprint_spice_lut_testbench_global_ports(FILE* fp, int grid_x, int grid_y, + int num_clock, + t_spice spice) { + /* int i; */ + /* A valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); + exit(1); + } + /* Print generic global ports*/ + fprint_spice_generic_testbench_global_ports(fp, + sram_spice_orgz_info, + global_ports_head); + + fprintf(fp, ".global gvdd_sram_luts\n"); + fprintf(fp, ".global gvdd_load\n"); + + /*Global Vdds for LUTs*/ + fprint_grid_global_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_LUT, spice); + /* + for (i = 0; i < spice.num_spice_model; i++) { + if (SPICE_MODEL_LUT == spice.spice_models[i].type) { + fprint_global_vdds_logical_block_spice_model(fp, &(spice.spice_models[i])); + } + } + */ + + + return; +} + +void fprint_spice_lut_testbench_one_lut(FILE* fp, + char* subckt_name, + int num_inputs, int num_outputs, + int* input_init_value, + float* input_density, + float* input_probability) { + int ipin; + /* A valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); + exit(1); + } + /* Call defined subckt */ + fprintf(fp, "Xlut[%d] ", tb_num_luts); + for (ipin = 0; ipin < num_inputs; ipin++) { + fprintf(fp, "lut[%d]->in[%d] ", tb_num_luts, ipin); + } + fprintf(fp, "lut[%d]->out gvdd 0 %s\n", tb_num_luts, subckt_name); + /* Stimulates */ + for (ipin = 0; ipin < num_inputs; ipin++) { + fprintf(fp, "Vlut[%d]->in[%d] lut[%d]->in[%d] 0 \n", + tb_num_luts, ipin, tb_num_luts, ipin); + fprint_voltage_pulse_params(fp, input_init_value[ipin], input_density[ipin], input_probability[ipin]); + } + return; +} + +void fprint_spice_lut_testbench_one_pb_graph_node_lut(FILE* fp, + t_pb_graph_node* cur_pb_graph_node, + char* prefix, + int x, int y, + t_ivec*** LL_rr_node_indices) { + int logical_block_index = OPEN; + t_spice_model* pb_spice_model = NULL; + t_pb_type* cur_pb_type = NULL; + float* input_density = NULL; + float* input_probability = NULL; + int* input_init_value = NULL; + int* input_net_num = NULL; + int iport, ipin, cur_pin; + int num_inputs, num_outputs, num_clock_pins; + char* outport_name = NULL; + t_rr_node* local_rr_graph = NULL; + float average_density = 0.; + int avg_density_cnt = 0; + int num_sim_clock_cycles = 0; + + assert(NULL != cur_pb_graph_node); + assert(NULL != prefix); + + cur_pb_type = cur_pb_graph_node->pb_type; + assert(NULL != cur_pb_type); + pb_spice_model = cur_pb_type->spice_model; + + /* Try to find the mapped logic block index */ + logical_block_index = find_grid_mapped_logical_block(x, y, + pb_spice_model, prefix); + + /* Bypass unmapped luts */ + /* + if (OPEN == logical_block_index) { + return; + } + */ + + /* Allocate input_density and probability */ + stats_pb_graph_node_port_pin_numbers(cur_pb_graph_node,&num_inputs,&num_outputs, &num_clock_pins); + assert(0 == num_clock_pins); + assert(1 == num_outputs); + assert(0 < num_inputs); + + input_density = (float*)my_malloc(sizeof(float)*num_inputs); + input_probability = (float*)my_malloc(sizeof(float)*num_inputs); + input_init_value = (int*)my_malloc(sizeof(int)*num_inputs); + input_net_num = (int*)my_malloc(sizeof(int)*num_inputs); + + /* Get activity information */ + assert(1 == cur_pb_graph_node->num_input_ports); + cur_pin = 0; + for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { + for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) { + /* if we find a mapped logic block */ + if (OPEN != logical_block_index) { + local_rr_graph = logical_block[logical_block_index].pb->parent_pb->rr_graph; + } else { + local_rr_graph = NULL; + } + input_net_num[cur_pin] = pb_pin_net_num(local_rr_graph, &(cur_pb_graph_node->input_pins[iport][ipin])); + input_density[cur_pin] = pb_pin_density(local_rr_graph, &(cur_pb_graph_node->input_pins[iport][ipin])); + input_probability[cur_pin] = pb_pin_probability(local_rr_graph, &(cur_pb_graph_node->input_pins[iport][ipin])); + input_init_value[cur_pin] = pb_pin_init_value(local_rr_graph, &(cur_pb_graph_node->input_pins[iport][ipin])); + cur_pin++; + } + assert(cur_pin == num_inputs); + } + /* Check lut pin net num consistency */ + if (OPEN != logical_block_index) { + if (0 == check_consistency_logical_block_net_num(&(logical_block[logical_block_index]), num_inputs, input_net_num)) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])LUT(name:%s) consistency check fail!\n", + __FILE__, __LINE__, logical_block[logical_block_index].name); + exit(1); + } + } + + /* Call the subckt and give stimulates, measurements */ + if (OPEN != logical_block_index) { + fprintf(fp,"***** LUT[%d]: logical_block_index[%d], gvdd_index[%d]*****\n", + tb_num_luts, logical_block_index, logical_block[logical_block_index].mapped_spice_model_index); + } else { + fprintf(fp,"***** LUT[%d]: logical_block_index[%d], gvdd_index[%d]*****\n", + tb_num_luts, -1, -1); + } + fprint_spice_lut_testbench_one_lut(fp, prefix, num_inputs, num_outputs, + input_init_value, input_density, input_probability); + /* Add loads: two inverters */ + /* Recursive add all the loads */ + outport_name = (char*)my_malloc(sizeof(char)*( 4 + strlen(my_itoa(tb_num_luts)) + + 6 + 1 )); + sprintf(outport_name, "lut[%d]->out", + tb_num_luts); + if (TRUE == run_testbench_load_extraction) { /* Additional switch, default on! */ + if (OPEN != logical_block_index) { + fprint_spice_testbench_pb_graph_pin_inv_loads_rec(fp, &testbench_load_cnt, + x, y, + &(cur_pb_graph_node->output_pins[0][0]), + logical_block[logical_block_index].pb, + outport_name, + FALSE, + LL_rr_node_indices); + } else { + fprint_spice_testbench_pb_graph_pin_inv_loads_rec(fp, &testbench_load_cnt, + x, y, + &(cur_pb_graph_node->output_pins[0][0]), + NULL, + outport_name, + FALSE, + LL_rr_node_indices); + } + } + + /* Calculate average density of this MUX */ + average_density = 0.; + avg_density_cnt = 0; + for (ipin = 0; ipin < num_inputs; ipin++) { + assert(!(0 > input_density[ipin])); + if (0. < input_density[ipin]) { + average_density += input_density[ipin]; + avg_density_cnt++; + } + } + /* Calculate the num_sim_clock_cycle for this MUX, update global max_sim_clock_cycle in this testbench */ + if (0 < avg_density_cnt) { + average_density = average_density/avg_density_cnt; + } else { + assert(0 == avg_density_cnt); + average_density = 0.; + } + if (0. == average_density) { + num_sim_clock_cycles = 2; + } else { + assert(0. < average_density); + num_sim_clock_cycles = (int)(1/average_density) + 1; + } + if (TRUE == auto_select_max_sim_num_clock_cycles) { + /* for idle blocks, 2 clock cycle is well enough... */ + if (2 < num_sim_clock_cycles) { + num_sim_clock_cycles = upbound_sim_num_clock_cycles; + } else { + num_sim_clock_cycles = 2; + } + if (max_sim_num_clock_cycles < num_sim_clock_cycles) { + max_sim_num_clock_cycles = num_sim_clock_cycles; + } + } else { + num_sim_clock_cycles = max_sim_num_clock_cycles; + } + + /* Mark temporary used */ + if (OPEN != logical_block_index) { + logical_block[logical_block_index].temp_used = 1; + } + tb_num_luts++; + + /* Free */ + my_free(input_net_num); + my_free(input_init_value); + my_free(input_density); + my_free(input_probability); + + return; +} + +void fprint_spice_lut_testbench_rec_pb_graph_node_luts(FILE* fp, + t_pb_graph_node* cur_pb_graph_node, + char* prefix, + int x, int y, + t_ivec*** LL_rr_node_indices) { + char* formatted_prefix = format_spice_node_prefix(prefix); + int ipb, jpb, mode_index; + t_pb_type* cur_pb_type = NULL; + char* rec_prefix = NULL; + + assert(NULL != cur_pb_graph_node); + cur_pb_type = cur_pb_graph_node->pb_type; + assert(NULL != cur_pb_type); + /* Until we reach a LUT */ + if (NULL != cur_pb_type->spice_model) { + if (SPICE_MODEL_LUT != cur_pb_type->spice_model->type) { + return; + } + /* Generate rec_prefix */ + rec_prefix = (char*)my_malloc(sizeof(char) * (strlen(formatted_prefix) + + strlen(cur_pb_type->name) + 1 + + strlen(my_itoa(cur_pb_graph_node->placement_index)) + + 1 + 1)); + sprintf(rec_prefix, "%s%s[%d]", + formatted_prefix, cur_pb_type->name, cur_pb_graph_node->placement_index); + /* Print a lut tb: call spice_model, stimulates */ + fprint_spice_lut_testbench_one_pb_graph_node_lut(fp, cur_pb_graph_node, rec_prefix, x, y, LL_rr_node_indices); + my_free(rec_prefix); + return; + } + + /* Go recursively ... */ + mode_index = find_pb_type_idle_mode_index(*(cur_pb_type)); + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Generate rec_prefix */ + rec_prefix = (char*)my_malloc(sizeof(char) * (strlen(formatted_prefix) + + strlen(cur_pb_type->name) + 1 + + strlen(my_itoa(cur_pb_graph_node->placement_index)) + 7 + + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1)); + sprintf(rec_prefix, "%s%s[%d]_mode[%s]", + formatted_prefix, cur_pb_type->name, cur_pb_graph_node->placement_index, + cur_pb_type->modes[mode_index].name); + /* Go recursively */ + fprint_spice_lut_testbench_rec_pb_graph_node_luts(fp, &(cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), + rec_prefix, x, y, LL_rr_node_indices); + my_free(rec_prefix); + } + } + + return; +} + +void fprint_spice_lut_testbench_rec_pb_luts(FILE* fp, + t_pb* cur_pb, char* prefix, + int x, int y, + t_ivec*** LL_rr_node_indices) { + char* formatted_prefix = format_spice_node_prefix(prefix); + int ipb, jpb; + int mode_index; + char* rec_prefix = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert(NULL != cur_pb); + + /* If we touch the leaf, there is no need print interc*/ + if (NULL != cur_pb->pb_graph_node->pb_type->spice_model) { + if (SPICE_MODEL_LUT != cur_pb->pb_graph_node->pb_type->spice_model->type) { + return; + } + /* Generate rec_prefix */ + rec_prefix = (char*)my_malloc(sizeof(char) * (strlen(formatted_prefix) + + strlen(cur_pb->pb_graph_node->pb_type->name) + 1 + + strlen(my_itoa(cur_pb->pb_graph_node->placement_index)) + + 1 + 1)); + sprintf(rec_prefix, "%s%s[%d]", + formatted_prefix, cur_pb->pb_graph_node->pb_type->name, cur_pb->pb_graph_node->placement_index); + /* Print a lut tb: call spice_model, stimulates */ + fprint_spice_lut_testbench_one_pb_graph_node_lut(fp, cur_pb->pb_graph_node, rec_prefix, x, y, LL_rr_node_indices); + my_free(rec_prefix); + return; + } + + /* Go recursively ... */ + mode_index = cur_pb->mode; + for (ipb = 0; ipb < cur_pb->pb_graph_node->pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb->pb_graph_node->pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Generate rec_prefix */ + rec_prefix = (char*)my_malloc(sizeof(char) * (strlen(formatted_prefix) + + strlen(cur_pb->pb_graph_node->pb_type->name) + 1 + + strlen(my_itoa(cur_pb->pb_graph_node->placement_index)) + 7 + + strlen(cur_pb->pb_graph_node->pb_type->modes[mode_index].name) + 1 + 1)); + sprintf(rec_prefix, "%s%s[%d]_mode[%s]", + formatted_prefix, cur_pb->pb_graph_node->pb_type->name, + cur_pb->pb_graph_node->placement_index, + cur_pb->pb_graph_node->pb_type->modes[mode_index].name); + /* Refer to pack/output_clustering.c [LINE 392] */ + if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { + fprint_spice_lut_testbench_rec_pb_luts(fp, &(cur_pb->child_pbs[ipb][jpb]), rec_prefix, x, y, LL_rr_node_indices); + } else { + /* Print idle graph_node muxes */ + /* Then we go on */ + fprint_spice_lut_testbench_rec_pb_graph_node_luts(fp, cur_pb->child_pbs[ipb][jpb].pb_graph_node, + rec_prefix, x, y, LL_rr_node_indices); + } + my_free(rec_prefix); + } + } + + return; +} + +void fprint_spice_lut_testbench_call_one_grid_defined_luts(FILE* fp, int ix, int iy, + t_ivec*** LL_rr_node_indices) { + int iblk; + char* prefix = NULL; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + if (NULL == grid[ix][iy].type) { + return; + } + + for (iblk = 0; iblk < grid[ix][iy].usage; iblk++) { + prefix = (char*)my_malloc(sizeof(char)* (5 + + strlen(my_itoa(block[grid[ix][iy].blocks[iblk]].x)) + + 2 + strlen(my_itoa(block[grid[ix][iy].blocks[iblk]].y)) + + 3 )); + sprintf(prefix, "grid[%d][%d]_", + block[grid[ix][iy].blocks[iblk]].x, + block[grid[ix][iy].blocks[iblk]].y); + /* Only for mapped block */ + assert(NULL != block[grid[ix][iy].blocks[iblk]].pb); + /* Mark the temporary net_num for the type pins*/ + mark_one_pb_parasitic_nets(block[grid[ix][iy].blocks[iblk]].pb); + fprint_spice_lut_testbench_rec_pb_luts(fp, block[grid[ix][iy].blocks[iblk]].pb, prefix, ix, iy, LL_rr_node_indices); + my_free(prefix); + } + /* By pass unused blocks */ + for (iblk = grid[ix][iy].usage; iblk < grid[ix][iy].type->capacity; iblk++) { + prefix = (char*)my_malloc(sizeof(char)* (5 + strlen(my_itoa(ix)) + + 2 + strlen(my_itoa(iy)) + 3 )); + sprintf(prefix, "grid[%d][%d]_", ix, iy); + assert(NULL != grid[ix][iy].type->pb_graph_head); + /* Mark the temporary net_num for the type pins*/ + mark_grid_type_pb_graph_node_pins_temp_net_num(ix, iy); + fprint_spice_lut_testbench_rec_pb_graph_node_luts(fp, grid[ix][iy].type->pb_graph_head, prefix, ix, iy, LL_rr_node_indices); + my_free(prefix); + } + + return; +} + +void fprint_spice_lut_testbench_call_defined_luts(FILE* fp, t_ivec*** LL_rr_node_indices) { + int ix, iy; + + for (ix = 1; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + fprint_spice_lut_testbench_call_one_grid_defined_luts(fp, ix, iy, LL_rr_node_indices); + } + } + + return; +} + +void fprint_spice_lut_testbench_conkt_lut_scan_chains(FILE* fp, int grid_x, int grid_y, + t_spice spice) { + int imodel, isc; + t_spice_model* lut_spice_model = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + for (imodel = 0; imodel < spice.num_spice_model; imodel++) { + if (SPICE_MODEL_LUT == spice.spice_models[imodel].type) { + lut_spice_model = &(spice.spice_models[imodel]); + /* Bypass LUT SPICE models that are contained by this grid */ + assert(-1 < (lut_spice_model->grid_index_high[grid_x][grid_y] - lut_spice_model->grid_index_low[grid_x][grid_y])); + if (0 == (lut_spice_model->grid_index_high[grid_x][grid_y] - lut_spice_model->grid_index_low[grid_x][grid_y])) { + continue; + } + fprintf(fp, "***** Connecting Scan-chains of %s in this grid[%d][%d] *****\n", + lut_spice_model->name, grid_x, grid_y); + for (isc = lut_spice_model->grid_index_low[grid_x][grid_y]; + isc < lut_spice_model->grid_index_high[grid_x][grid_y]; + isc++) { + fprintf(fp, "R%s[%d]_sc_short %s[%d]_sc_tail %s[%d]_sc_head\n", + lut_spice_model->prefix, isc, + lut_spice_model->prefix, isc, + lut_spice_model->prefix, isc + 1); + } + fprintf(fp, "***** END *****\n"); + fprintf(fp, "***** Scan-Chain Head of %s in grid[%d][%d]\n", + lut_spice_model->name, grid_x, grid_y); + fprintf(fp, "V%s[%d]_sc_head %s[%d]_sc_head 0 0\n", + lut_spice_model->prefix, lut_spice_model->grid_index_low[grid_x][grid_y], + lut_spice_model->prefix, lut_spice_model->grid_index_low[grid_x][grid_y]); + fprintf(fp, ".nodeset V(%s[%d]_sc_head) 0\n", + lut_spice_model->prefix, lut_spice_model->grid_index_low[grid_x][grid_y]); + } + } + + return; +} + +void fprint_spice_lut_testbench_stimulations(FILE* fp, int grid_x, int grid_y, + int num_clock, + t_spice spice, + t_ivec*** LL_rr_node_indices) { + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Print generic stimuli */ + fprint_spice_testbench_generic_global_ports_stimuli(fp, num_clock); + + /* Generate global ports stimuli */ + fprint_spice_testbench_global_ports_stimuli(fp, global_ports_head); + + /* SRAM ports */ + /* Every SRAM inputs should have a voltage source */ + fprintf(fp, "***** Global Inputs for SRAMs *****\n"); + fprint_spice_testbench_global_sram_inport_stimuli(fp, sram_spice_orgz_info); + + fprintf(fp, "***** Global VDD for LUTs SRAMs *****\n"); + fprint_spice_testbench_global_vdd_port_stimuli(fp, + spice_tb_global_vdd_lut_sram_port_name, + "vsp"); + + fprintf(fp, "***** Global VDD for SRAMs *****\n"); + fprint_spice_testbench_global_vdd_port_stimuli(fp, + spice_tb_global_vdd_sram_port_name, + "vsp"); + + fprintf(fp, "***** Global VDD for load inverters *****\n"); + fprint_spice_testbench_global_vdd_port_stimuli(fp, + spice_tb_global_vdd_load_port_name, + "vsp"); + + /* Global Vdd ports */ + /* Every LUT use an independent Voltage source */ + fprintf(fp, "***** Global VDD for Look-Up Tables (LUTs) *****\n"); + fprint_grid_splited_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_LUT, spice); + + return; +} + +void fprint_spice_lut_testbench_measurements(FILE* fp, int grid_x, int grid_y, + t_spice spice, + boolean leakage_only) { + /* int i; */ + /* First cycle reserved for measuring leakage */ + int num_clock_cycle = max_sim_num_clock_cycles; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + fprint_spice_netlist_transient_setting(fp, spice, num_clock_cycle, leakage_only); + fprint_spice_netlist_generic_measurements(fp, spice.spice_params.mc_params, spice.num_spice_model, spice.spice_models); + + /* TODO: Measure the delay of each mapped net and logical block */ + + /* Measure the power */ + /* Leakage ( the first cycle is reserved for leakage measurement) */ + if (TRUE == leakage_only) { + /* Leakage power of SRAMs */ + fprintf(fp, ".measure tran leakage_power_sram_luts find p(Vgvdd_sram_luts) at=0\n"); + } else { + /* Leakage power of SRAMs */ + fprintf(fp, ".measure tran leakage_power_sram_luts avg p(Vgvdd_sram_luts) from=0 to='clock_period'\n"); + } + /* Leakage power of LUTs*/ + fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_LUT, SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, spice, leakage_only); + /* + for (i = 0; i < spice.num_spice_model; i++) { + if (SPICE_MODEL_LUT == spice.spice_models[i].type) { + fprint_measure_vdds_logical_block_spice_model(fp, &(spice.spice_models[i]), SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, leakage_only); + } + } + */ + + if (TRUE == leakage_only) { + return; + } + + /* Dynamic power */ + /* Dynamic power of SRAMs */ + fprintf(fp, ".measure tran dynamic_power_sram_luts avg p(Vgvdd_sram_luts) from='clock_period' to='%d*clock_period'\n", num_clock_cycle); + fprintf(fp, ".measure tran energy_per_cycle_sram_luts param='dynamic_power_sram_luts*clock_period'\n"); + /* Dynamic power of LUTs */ + fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_LUT, SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, spice, leakage_only); + /* + for (i = 0; i < spice.num_spice_model; i++) { + if (SPICE_MODEL_LUT == spice.spice_models[i].type) { + fprint_measure_vdds_logical_block_spice_model(fp, &(spice.spice_models[i]), SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, leakage_only); + } + } + */ + + return; +} + +/* Top-level function in this source file */ +int fprint_spice_one_lut_testbench(char* formatted_spice_dir, + char* circuit_name, + char* lut_testbench_name, + char* include_dir_path, + char* subckt_dir_path, + t_ivec*** LL_rr_node_indices, + int num_clock, + t_arch arch, + int grid_x, int grid_y, + boolean leakage_only) { + FILE* fp = NULL; + char* formatted_subckt_dir_path = format_dir_path(subckt_dir_path); + char* temp_include_file_path = NULL; + char* title = my_strcat("FPGA LUT Testbench for Design: ", circuit_name); + char* lut_testbench_file_path = my_strcat(formatted_spice_dir, lut_testbench_name); + int used; + + /* Check if the path exists*/ + fp = fopen(lut_testbench_file_path,"w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create LUT Testbench SPICE netlist %s!",__FILE__, __LINE__, lut_testbench_file_path); + exit(1); + } + + /* Reset tb_cnt for all the spice models */ + init_spice_models_tb_cnt(arch.spice->num_spice_model, arch.spice->spice_models); + + /*vpr_printf(TIO_MESSAGE_INFO, "Writing LUT Testbench for %s...\n", circuit_name);*/ + testbench_load_cnt = 0; + + /* Print the title */ + fprint_spice_head(fp, title); + my_free(title); + + /* print technology library and design parameters*/ + + /* Include parameter header files */ + fprint_spice_include_param_headers(fp, include_dir_path); + + /* Include Key subckts */ + fprint_spice_include_key_subckts(fp, subckt_dir_path); + + /* Include user-defined sub-circuit netlist */ + init_include_user_defined_netlists(*(arch.spice)); + fprint_include_user_defined_netlists(fp, *(arch.spice)); + + /* Special subckts for Top-level SPICE netlist */ + fprintf(fp, "****** Include subckt netlists: Look-Up Tables (LUTs) *****\n"); + temp_include_file_path = my_strcat(formatted_subckt_dir_path, luts_spice_file_name); + fprintf(fp, ".include \'%s\'\n", temp_include_file_path); + my_free(temp_include_file_path); + + fprintf(fp, "****** Include subckt netlists: Logic Blocks *****\n"); + temp_include_file_path = my_strcat(formatted_subckt_dir_path, logic_block_spice_file_name); + fprintf(fp, ".include \'%s\'\n", temp_include_file_path); + my_free(temp_include_file_path); + + /* Print simulation temperature and other options for SPICE */ + fprint_spice_options(fp, arch.spice->spice_params); + + /* Global nodes: Vdd for SRAMs, Logic Blocks(Include IO), Switch Boxes, Connection Boxes */ + fprint_spice_lut_testbench_global_ports(fp, grid_x, grid_y, num_clock, (*arch.spice)); + + /* Quote defined Logic blocks subckts (Grids) */ + init_spice_lut_testbench_globals(*(arch.spice)); + init_logical_block_spice_model_type_temp_used(arch.spice->num_spice_model, arch.spice->spice_models, SPICE_MODEL_LUT); + fprint_spice_lut_testbench_call_one_grid_defined_luts(fp, grid_x, grid_y, LL_rr_node_indices); + + /* Back-anotate activity information to each routing resource node + * (We should have activity of each Grid port) + */ + + /* Check if the all hardlogic located in this grid have been printed */ + check_spice_models_grid_tb_cnt(arch.spice->num_spice_model, arch.spice->spice_models, grid_x, grid_y, SPICE_MODEL_LUT); + + /* Add stimulations */ + fprint_spice_lut_testbench_stimulations(fp, grid_x, grid_y, num_clock, (*arch.spice), LL_rr_node_indices); + + /* Add measurements */ + fprint_spice_lut_testbench_measurements(fp, grid_x, grid_y, (*arch.spice), leakage_only); + + /* SPICE ends*/ + fprintf(fp, ".end\n"); + + /* Close the file*/ + fclose(fp); + + if (0 < tb_num_luts) { + vpr_printf(TIO_MESSAGE_INFO, "Writing Grid[%d][%d] SPICE LUT Testbench for %s...\n", + grid_x, grid_y, circuit_name); + /* Push the testbench to the linked list */ + tb_head = add_one_spice_tb_info_to_llist(tb_head, lut_testbench_file_path, + max_sim_num_clock_cycles); + used = 1; + } else { + /* Remove the file generated */ + my_remove_file(lut_testbench_file_path); + used = 0; + } + + return used; +} + + +/* Top-level function in this source file */ +void spice_print_lut_testbench(char* formatted_spice_dir, + char* circuit_name, + char* include_dir_path, + char* subckt_dir_path, + t_ivec*** LL_rr_node_indices, + int num_clock, + t_arch arch, + boolean leakage_only) { + char* lut_testbench_name = NULL; + int ix, iy; + int cnt = 0; + int used; + + for (ix = 1; ix < (nx+1); ix++) { + for (iy = 1; iy < (ny+1); iy++) { + lut_testbench_name = (char*)my_malloc(sizeof(char)*( strlen(circuit_name) + + 6 + strlen(my_itoa(ix)) + 1 + + strlen(my_itoa(iy)) + 1 + + strlen(spice_lut_testbench_postfix) + 1 )); + sprintf(lut_testbench_name, "%s_grid%d_%d%s", + circuit_name, ix, iy, spice_lut_testbench_postfix); + used = fprint_spice_one_lut_testbench(formatted_spice_dir, circuit_name, lut_testbench_name, + include_dir_path, subckt_dir_path, LL_rr_node_indices, + num_clock, arch, ix, iy, + leakage_only); + if (1 == used) { + cnt += used; + } + /* free */ + my_free(lut_testbench_name); + } + } + /* Update the global counter */ + num_used_lut_tb = cnt; + vpr_printf(TIO_MESSAGE_INFO,"No. of generated LUT testbench = %d\n", num_used_lut_tb); + + return; +} diff --git a/vpr7_rram/vpr/SRC/spice/spice_lut_testbench.h b/vpr7_rram/vpr/SRC/spice/spice_lut_testbench.h new file mode 100644 index 000000000..8ec0fef2a --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_lut_testbench.h @@ -0,0 +1,10 @@ + + +void spice_print_lut_testbench(char* formatted_spice_dir, + char* circuit_name, + char* include_dir_path, + char* subckt_dir_path, + t_ivec*** LL_rr_node_indices, + int num_clock, + t_arch arch, + boolean leakage_only); diff --git a/vpr7_rram/vpr/SRC/spice/spice_mux.c b/vpr7_rram/vpr/SRC/spice/spice_mux.c new file mode 100644 index 000000000..76edce0d0 --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_mux.c @@ -0,0 +1,1305 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph.h" +#include "rr_graph_swseg.h" +#include "vpr_utils.h" + +/* Include spice support headers*/ +#include "linkedlist.h" +#include "fpga_spice_globals.h" +#include "spice_globals.h" +#include "fpga_spice_utils.h" +#include "spice_utils.h" +#include "spice_lut.h" +#include "spice_pbtypes.h" +#include "spice_mux.h" + +/***** Subroutines *****/ + +static +void fprint_spice_mux_model_basis_cmos_subckt(FILE* fp, char* subckt_name, + int num_input_per_level, + t_spice_model spice_model, + int mux_size, + boolean special_basis) { + char* pgl_name = NULL; + int num_sram_bits = 0; + int i; + + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert(1 < num_input_per_level); + + /* Ensure we have a CMOS MUX*/ + /* Exception: LUT require an auto-generation of netlist can run as well*/ + assert((SPICE_MODEL_MUX == spice_model.type)||(SPICE_MODEL_LUT == spice_model.type)); + assert(SPICE_MODEL_DESIGN_CMOS == spice_model.design_tech); + assert(NULL != spice_model.pass_gate_logic); + + /* Print the subckt */ + fprintf(fp, ".subckt %s ", subckt_name); + for (i = 0; i < num_input_per_level; i++) { + fprintf(fp, "in%d ", i); + } + fprintf(fp, "out "); + + /* General cases */ + num_sram_bits = determine_num_sram_bits_mux_basis_subckt(&spice_model, mux_size, + num_input_per_level, special_basis); + + for (i = 0; i < num_sram_bits; i++) { + fprintf(fp, "sel%d sel_inv%d ", i, i); + } + fprintf(fp, "svdd sgnd\n"); + /* Identify the pass-gate logic*/ + switch (spice_model.pass_gate_logic->type) { + case SPICE_MODEL_PASS_GATE_TRANSMISSION: + pgl_name = cpt_subckt_name; + /* We do not need to know the structure of multiplexer, just follow the number of input + * Identify a special case: input_size = 2 + */ + if (1 == num_sram_bits) { + fprintf(fp,"X%s_0 in0 out sel0 sel_inv0 svdd sgnd %s nmos_size=\'%s%s\' pmos_size=\'%s%s\'\n", + pgl_name, pgl_name, + spice_model.name, design_param_postfix_pass_gate_logic_nmos_size, + spice_model.name, design_param_postfix_pass_gate_logic_pmos_size); + fprintf(fp,"X%s_1 in1 out sel_inv0 sel0 svdd sgnd %s nmos_size=\'%s%s\' pmos_size=\'%s%s\'\n", + pgl_name, pgl_name, + spice_model.name, design_param_postfix_pass_gate_logic_nmos_size, + spice_model.name, design_param_postfix_pass_gate_logic_pmos_size); + } else { + for (i = 0; i < num_input_per_level; i++) { + fprintf(fp,"X%s_%d in%d out sel%d sel_inv%d svdd sgnd %s nmos_size=\'%s%s\' pmos_size=\'%s%s\'\n", + pgl_name, i, i, i, i, pgl_name, + spice_model.name, design_param_postfix_pass_gate_logic_nmos_size, + spice_model.name, design_param_postfix_pass_gate_logic_pmos_size); + } + } + break; + case SPICE_MODEL_PASS_GATE_TRANSISTOR: + pgl_name = nmos_subckt_name; + /* We do not need to know the structure of multiplexer, just follow the number of input + * Identify a special case: input_size = 2 + */ + if (1 == num_sram_bits) { + fprintf(fp,"X%s_0 in0 sel0 out sgnd %s W=\'%s%s*wn\'\n", + pgl_name, pgl_name, + spice_model.name, design_param_postfix_pass_gate_logic_nmos_size); + fprintf(fp,"X%s_1 in1 sel_inv0 out sgnd %s W=\'%s%s*wn\'\n", + pgl_name, pgl_name, + spice_model.name, design_param_postfix_pass_gate_logic_nmos_size); + } else { + for (i = 0; i < num_input_per_level; i++) { + fprintf(fp,"X%s_%d in%d sel%d out sgnd %s W=\'%s%s*wn\'\n", + pgl_name, i, i, i, + pgl_name, + spice_model.name, design_param_postfix_pass_gate_logic_nmos_size); + } + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File: %s,[LINE%d])Invalid pass gate logic for spice model(name:%s)!\n", + __FILE__, __LINE__, spice_model.name); + exit(1); + } + + fprintf(fp,".eom\n"); + fprintf(fp,"\n"); + + return; +} + +static +void fprint_spice_mux_model_basis_rram_subckt(FILE* fp, char* subckt_name, + int mux_size, + int num_input_per_level, + t_spice_model spice_model, + boolean special_basis) { + int i, num_sram_bits; + char* prog_pmos_subckt_name = NULL; + char* prog_nmos_subckt_name = NULL; + char* prog_wp = NULL; + char* prog_wn = NULL; + + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + + /* assert(SPICE_MODEL_PASS_GATE_TRANSMISSION == spice_model.pass_gate_logic->type); */ + assert(0. < spice_model.design_tech_info.wprog_set_pmos); + assert(0. < spice_model.design_tech_info.wprog_reset_pmos); + assert(0. < spice_model.design_tech_info.wprog_set_nmos); + assert(0. < spice_model.design_tech_info.wprog_reset_nmos); + + /* Ensure we have a CMOS MUX*/ + /* Exception: LUT require an auto-generation of netlist can run as well*/ + assert((SPICE_MODEL_MUX == spice_model.type)||(SPICE_MODEL_LUT == spice_model.type)); + assert(SPICE_MODEL_DESIGN_RRAM == spice_model.design_tech); + + /* Check */ + assert(1 < num_input_per_level); + + /* Determine the number of memory bit + * The function considers a special case : + * 2-input basis in tree-like MUX only requires 1 memory bit */ + num_sram_bits = determine_num_sram_bits_mux_basis_subckt(&spice_model, mux_size, num_input_per_level, special_basis); + + /* Consider advanced RRAM multiplexer design + * Advanced design employ normal logic transistors + * Basic design employ IO transistors + */ + if (TRUE == spice_model.design_tech_info.advanced_rram_design) { + prog_pmos_subckt_name = pmos_subckt_name; + prog_nmos_subckt_name = nmos_subckt_name; + prog_wp = "wp"; + prog_wn = "wn"; + } else { + prog_pmos_subckt_name = io_pmos_subckt_name; + prog_nmos_subckt_name = io_nmos_subckt_name; + prog_wp = "io_wp"; + prog_wn = "io_wn"; + } + + fprintf(fp, ".subckt %s ", subckt_name); + for (i = 0; i < num_input_per_level; i++) { + fprintf(fp, "in%d ", i); + } + fprintf(fp, "out "); + for (i = 0; i < num_sram_bits; i++) { + fprintf(fp, "sel%d sel_inv%d ", i, i); + } + fprintf(fp, "svdd sgnd "); + fprintf(fp, "ron=\'%s%s\' roff=\'%s%s\' ", + spice_model.name, design_param_postfix_rram_ron, + spice_model.name, design_param_postfix_rram_roff); + fprintf(fp, "wprog_set_nmos=\'%s%s*%s\' wprog_reset_nmos=\'%s%s*%s\' ", + spice_model.name, design_param_postfix_rram_wprog_set_nmos, + prog_wn, + spice_model.name, design_param_postfix_rram_wprog_reset_nmos, + prog_wn); + fprintf(fp, "wprog_set_pmos=\'%s%s*%s\' wprog_reset_pmos=\'%s%s*%s\' \n", + spice_model.name, design_param_postfix_rram_wprog_set_pmos, + prog_wp, + spice_model.name, design_param_postfix_rram_wprog_reset_pmos, + prog_wp); + /* Print the new 2T1R structure */ + /* Switch case: + * when there is only 1 SRAM bit */ + if (1 == num_sram_bits) { + /* RRAMs */ + fprintf(fp, "Xrram_0 in0 out sel0 sel_inv0 rram_behavior switch_thres=vsp ron=ron roff=roff\n"); + /* Programming transistor pairs */ + fprintf(fp, "Xnmos_prog_pair0 in0 sgnd sgnd sgnd %s W=\'wprog_reset_nmos\' \n", + prog_nmos_subckt_name); + fprintf(fp, "Xpmos_prog_pair0 in0 svdd svdd svdd %s W=\'wprog_set_pmos\' \n", + prog_pmos_subckt_name); + /* RRAMs */ + fprintf(fp, "Xrram_1 in1 out sel_inv0 sel0 rram_behavior switch_thres=vsp ron=ron roff=roff\n"); + /* Programming transistor pairs */ + fprintf(fp, "Xnmos_prog_pair_in1 in1 sgnd sgnd sgnd %s W=\'wprog_reset_nmos\' \n", + prog_nmos_subckt_name); + fprintf(fp, "Xpmos_prog_pair_in1 in1 svdd svdd svdd %s W=\'wprog_set_pmos\' \n", + prog_pmos_subckt_name); + } else { + for (i = 0; i < num_input_per_level; i++) { + /* RRAMs */ + fprintf(fp, "Xrram_%d in%d out sel%d sel_inv%d rram_behavior switch_thres=vsp ron=ron roff=roff\n", + i, i, i, i); + /* Programming transistor pairs */ + fprintf(fp, "Xnmos_prog_pair_in%d in%d sgnd sgnd sgnd %s W=\'wprog_reset_nmos\' \n", + i, i, prog_nmos_subckt_name); + fprintf(fp, "Xpmos_prog_pair_in%d in%d svdd svdd svdd %s W=\'wprog_set_pmos\' \n", + i, i, prog_pmos_subckt_name); + } + } + /* Programming transistor pairs shared at the output */ + fprintf(fp, "Xnmos_prog_pair_out out sgnd sgnd sgnd %s W=\'wprog_set_nmos\' \n", + prog_nmos_subckt_name); + fprintf(fp, "Xpmos_prog_pair_out out svdd svdd svdd %s W=\'wprog_reset_pmos\' \n", + prog_pmos_subckt_name); + fprintf(fp,".eom\n"); + fprintf(fp,"\n"); + + return; +} + +/* Print the SPICE model of a 2:1 MUX which is the basis */ +static +void fprint_spice_mux_model_basis_subckt(FILE* fp, + t_spice_mux_model* spice_mux_model) { + char* mux_basis_subckt_name = NULL; + char* mux_special_basis_subckt_name = NULL; + int num_input_basis_subckt = 0; + int num_input_special_basis_subckt = 0; + + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + + /* Try to find a mux in cmos technology, + * if we have, then build CMOS 2:1 MUX, and given cmos_mux2to1_subckt_name + */ + /* Exception: LUT require an auto-generation of netlist can run as well*/ + assert((SPICE_MODEL_MUX == spice_mux_model->spice_model->type) + ||(SPICE_MODEL_LUT == spice_mux_model->spice_model->type)); + + /* Generate the spice_mux_arch */ + spice_mux_model->spice_mux_arch = (t_spice_mux_arch*)my_malloc(sizeof(t_spice_mux_arch)); + init_spice_mux_arch(spice_mux_model->spice_model, spice_mux_model->spice_mux_arch, spice_mux_model->size); + + /* Corner case: Error out MUX_SIZE = 2, automatcially give a one-level structure */ + /* + if ((2 == spice_mux_model->size)&&(SPICE_MODEL_STRUCTURE_ONELEVEL != spice_mux_model->spice_model->design_tech_info.structure)) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Structure of SPICE model (%s) should be one-level because it is linked to a 2:1 MUX!\n", + __FILE__, __LINE__, spice_mux_model->spice_model->name); + exit(1); + } + */ + + /* Prepare the basis subckt name */ + mux_basis_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_mux_model->spice_model->name) + 5 + + strlen(my_itoa(spice_mux_model->size)) + + strlen(mux_basis_posfix) + 1)); + sprintf(mux_basis_subckt_name, "%s_size%d%s", + spice_mux_model->spice_model->name, spice_mux_model->size, mux_basis_posfix); + + /* deteremine the number of inputs of basis subckt */ + num_input_basis_subckt = spice_mux_model->spice_mux_arch->num_input_basis; + + /* Determine the input size of the spcial basis */ + num_input_special_basis_subckt = find_spice_mux_arch_special_basis_size(*(spice_mux_model->spice_mux_arch)); + + /* Name the special basis subckt */ + mux_special_basis_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_mux_model->spice_model->name) + 5 + + strlen(my_itoa(spice_mux_model->size)) + + strlen(mux_special_basis_posfix) + 1)); + sprintf(mux_special_basis_subckt_name, "%s_size%d%s", + spice_mux_model->spice_model->name, spice_mux_model->size, mux_special_basis_posfix); + + /* Print the basis subckt*/ + switch (spice_mux_model->spice_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + /* Give the subckt name*/ + fprint_spice_mux_model_basis_cmos_subckt(fp, mux_basis_subckt_name, + num_input_basis_subckt, + *(spice_mux_model->spice_model), + spice_mux_model->size, + FALSE); + /* Dump subckt of special basis if required */ + if (0 < num_input_special_basis_subckt) { + fprint_spice_mux_model_basis_cmos_subckt(fp, mux_special_basis_subckt_name, + num_input_special_basis_subckt, + (*spice_mux_model->spice_model), + spice_mux_model->size, + TRUE); + } + break; + case SPICE_MODEL_DESIGN_RRAM: + /* RRAM LUT are not yet supported ! */ + if (SPICE_MODEL_LUT == spice_mux_model->spice_model->type) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])RRAM LUT is not supported!\n", + __FILE__, __LINE__); + exit(1); + } + fprint_spice_mux_model_basis_rram_subckt(fp, mux_basis_subckt_name, + spice_mux_model->size, + num_input_basis_subckt, + *(spice_mux_model->spice_model), + FALSE); + /* Dump subckt of special basis if required */ + if (0 < num_input_special_basis_subckt) { + fprint_spice_mux_model_basis_rram_subckt(fp, mux_special_basis_subckt_name, + spice_mux_model->size, + num_input_special_basis_subckt, + (*spice_mux_model->spice_model), + TRUE); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of MUX(name: %s)\n", + __FILE__, __LINE__, spice_mux_model->spice_model->name); + exit(1); + } + + /* Free */ + my_free(mux_basis_subckt_name); + my_free(mux_special_basis_subckt_name); + + return; +} + +void fprint_spice_cmos_mux_tree_structure(FILE* fp, char* mux_basis_subckt_name, + t_spice_model spice_model, + t_spice_mux_arch spice_mux_arch, + int num_sram_port, t_spice_model_port** sram_port) { + int i, j, level, nextlevel; + int nextj, out_idx; + int mux_basis_cnt = 0; + + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + + mux_basis_cnt = 0; + for (i = 0; i < spice_mux_arch.num_level; i++) { + level = spice_mux_arch.num_level - i; + nextlevel = spice_mux_arch.num_level - i - 1; + /* Check */ + assert(nextlevel > -1); + /* Print basis mux2to1 for each level*/ + for (j = 0; j < spice_mux_arch.num_input_per_level[nextlevel]; j++) { + nextj = j + 1; + out_idx = j/2; + /* Each basis mux2to1: svdd sgnd */ + fprintf(fp, "Xmux_basis_no%d ", mux_basis_cnt); /* given_name */ + fprintf(fp, "mux2_l%d_in%d mux2_l%d_in%d ", level, j, level, nextj); /* input0 input1 */ + fprintf(fp, "mux2_l%d_in%d ", nextlevel, out_idx); /* output */ + /* fprintf(fp, "%s%d %s_inv%d ", sram_port[0]->prefix, nextlevel, sram_port[0]->prefix, nextlevel);*/ /* sram sram_inv */ + fprintf(fp, "%s%d %s_inv%d ", sram_port[0]->prefix, i, sram_port[0]->prefix, i); /* sram sram_inv */ + fprintf(fp, "svdd sgnd %s\n", mux_basis_subckt_name); /* subckt_name */ + /* Update the counter */ + j = nextj; + mux_basis_cnt++; + } + } + /* Assert */ + assert(0 == nextlevel); + assert(0 == out_idx); + assert(mux_basis_cnt == spice_mux_arch.num_input - 1); + + return; +} + +void fprint_spice_cmos_mux_multilevel_structure(FILE* fp, + char* mux_basis_subckt_name, + char* mux_special_basis_subckt_name, + t_spice_model spice_model, + t_spice_mux_arch spice_mux_arch, + int num_sram_port, t_spice_model_port** sram_port) { + int i, j, k, level, nextlevel, sram_idx; + int out_idx; + int mux_basis_cnt = 0; + int mux_special_basis_cnt = 0; + int cur_num_input_basis = 0; + + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + + mux_basis_cnt = 0; + assert((2 == spice_mux_arch.num_input_basis)||(2 < spice_mux_arch.num_input_basis)); + for (i = 0; i < spice_mux_arch.num_level; i++) { + level = spice_mux_arch.num_level - i; + nextlevel = spice_mux_arch.num_level - i - 1; + sram_idx = nextlevel * spice_mux_arch.num_input_basis; + /* Check */ + assert(nextlevel > -1); + /* Print basis muxQto1 for each level*/ + for (j = 0; j < spice_mux_arch.num_input_per_level[nextlevel]; j = j+cur_num_input_basis) { + /* output index */ + out_idx = j/spice_mux_arch.num_input_basis; + /* Determine the number of input of this basis */ + cur_num_input_basis = spice_mux_arch.num_input_basis; + /* See if we need a special basis */ + if ((j + cur_num_input_basis) > spice_mux_arch.num_input_per_level[nextlevel]) { + cur_num_input_basis = spice_mux_arch.num_input_per_level[nextlevel] - j; + /* Print the special basis subckt */ + /* Each basis muxQto1: svdd sgnd */ + fprintf(fp, "Xmux_special_basis_no%d ", mux_special_basis_cnt); /* given_name */ + for (k = 0; k < cur_num_input_basis; k++) { + fprintf(fp, "mux2_l%d_in%d ", level, j + k); /* input0 input1 */ + } + fprintf(fp, "mux2_l%d_in%d ", nextlevel, out_idx); /* output */ + /* Print number of sram bits for this basis */ + for (k = sram_idx; k < (sram_idx + cur_num_input_basis); k++) { + fprintf(fp, "%s%d %s_inv%d ", sram_port[0]->prefix, k, sram_port[0]->prefix, k); /* sram sram_inv */ + } + fprintf(fp, "svdd sgnd %s\n", mux_special_basis_subckt_name); /* subckt_name */ + /* update counter */ + mux_special_basis_cnt++; + continue; + } + /* Reach here, it means we need a normal basis subckt */ + /* Each basis muxQto1: svdd sgnd */ + fprintf(fp, "Xmux_basis_no%d ", mux_basis_cnt); /* given_name */ + for (k = 0; k < cur_num_input_basis; k++) { + fprintf(fp, "mux2_l%d_in%d ", level, j + k); /* input0 input1 */ + } + fprintf(fp, "mux2_l%d_in%d ", nextlevel, out_idx); /* output */ + /* Print number of sram bits for this basis */ + for (k = sram_idx; k < (sram_idx + cur_num_input_basis); k++) { + fprintf(fp, "%s%d %s_inv%d ", sram_port[0]->prefix, k, sram_port[0]->prefix, k); /* sram sram_inv */ + } + fprintf(fp, "svdd sgnd %s\n", mux_basis_subckt_name); /* subckt_name */ + /* Update the counter */ + mux_basis_cnt++; + } + } + /* Assert */ + assert(0 == nextlevel); + assert(0 == out_idx); + assert((1 == mux_special_basis_cnt)||(0 == mux_special_basis_cnt)); + /* + assert((mux_basis_cnt + mux_special_basis_cnt) + == (int)((spice_mux_arch.num_input - 1)/(spice_mux_arch.num_input_basis - 1)) + 1); + */ + + return; +} + +void fprint_spice_cmos_mux_onelevel_structure(FILE* fp, char* mux_basis_subckt_name, + t_spice_model spice_model, + t_spice_mux_arch spice_mux_arch, + int num_sram_port, t_spice_model_port** sram_port) { + int k, mux_basis_cnt; + int level, nextlevel, out_idx; + int num_sram_bits = 0; + + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + + assert(SPICE_MODEL_DESIGN_CMOS == spice_model.design_tech); + + /* Initialize */ + mux_basis_cnt = 0; + level = 1; + nextlevel = 0; + out_idx = 0; + + /* Each basis muxQto1: svdd sgnd */ + fprintf(fp, "Xmux_basis_no%d ", mux_basis_cnt); /* given_name */ + for (k = 0; k < spice_mux_arch.num_input; k++) { + fprintf(fp, "mux2_l%d_in%d ", level, k); /* input0 input1 */ + } + fprintf(fp, "mux2_l%d_in%d ", nextlevel, out_idx); /* output */ + /* Print number of sram bits for this basis */ + num_sram_bits = count_num_sram_bits_one_spice_model(&spice_model, + spice_mux_arch.num_input); + for (k = 0; k < num_sram_bits; k++) { + fprintf(fp, "%s%d %s_inv%d ", sram_port[0]->prefix, k, sram_port[0]->prefix, k); /* sram sram_inv */ + } + fprintf(fp, "svdd sgnd %s\n", mux_basis_subckt_name); /* subckt_name */ + /* Update the counter */ + mux_basis_cnt++; + + /* Check */ + return; +} + +/** This is an old tree-like RRAM MUX, which is not manufacturable + */ +void fprint_spice_rram_mux_tree_structure(FILE* fp, char* mux_basis_subckt_name, + t_spice_model spice_model, + t_spice_mux_arch spice_mux_arch, + int num_sram_port, t_spice_model_port** sram_port) { + int i, j, level, nextlevel; + int nextj, out_idx; + int mux_basis_cnt = 0; + + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + + mux_basis_cnt = 0; + for (i = 0; i < spice_mux_arch.num_level; i++) { + level = spice_mux_arch.num_level - i; + nextlevel = spice_mux_arch.num_level - i - 1; + /* Check */ + assert(nextlevel > -1); + /* Print basis mux2to1 for each level*/ + for (j = 0; j < spice_mux_arch.num_input_per_level[nextlevel]; j++) { + nextj = j + 1; + out_idx = j/2; + /* Each basis mux2to1: svdd sgnd */ + fprintf(fp, "Xmux_basis_no%d ", mux_basis_cnt); /* given_name */ + fprintf(fp, "mux2_l%d_in%d mux2_l%d_in%d ", level, j, level, nextj); /* input0 input1 */ + fprintf(fp, "mux2_l%d_in%d ", nextlevel, out_idx); /* output */ + fprintf(fp, "%s%d %s_inv%d ", sram_port[0]->prefix, i, sram_port[0]->prefix, i); /* sram sram_inv */ + fprintf(fp, "svdd sgnd %s\n", mux_basis_subckt_name); /* subckt_name */ + /* Update the counter */ + j = nextj; + mux_basis_cnt++; + } + } + /* Assert */ + assert(0 == nextlevel); + assert(0 == out_idx); + assert(mux_basis_cnt == spice_mux_arch.num_input - 1); + + return; +} + +/** This is supposed to be a multi-level 4T1R RRAM MUX + */ +void fprint_spice_rram_mux_multilevel_structure(FILE* fp, char* mux_basis_subckt_name, + char* mux_special_basis_subckt_name, + t_spice_model spice_model, + t_spice_mux_arch spice_mux_arch, + int num_sram_port, t_spice_model_port** sram_port) { + int i, j, k, level, nextlevel, sram_idx; + int out_idx; + int mux_basis_cnt = 0; + int mux_special_basis_cnt = 0; + int cur_num_input_basis = 0; + + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + + mux_basis_cnt = 0; + assert((2 == spice_mux_arch.num_input_basis)||(2 < spice_mux_arch.num_input_basis)); + for (i = 0; i < spice_mux_arch.num_level; i++) { + level = spice_mux_arch.num_level - i; + nextlevel = spice_mux_arch.num_level - i - 1; + sram_idx = nextlevel * spice_mux_arch.num_input_basis; + /* Check */ + assert(nextlevel > -1); + /* Print basis muxQto1 for each level*/ + for (j = 0; j < spice_mux_arch.num_input_per_level[nextlevel]; j = j+cur_num_input_basis) { + /* output index */ + out_idx = j/spice_mux_arch.num_input_basis; + /* Determine the number of input of this basis */ + cur_num_input_basis = spice_mux_arch.num_input_basis; + /* See if we need a special basis */ + if ((j + cur_num_input_basis) > spice_mux_arch.num_input_per_level[nextlevel]) { + cur_num_input_basis = spice_mux_arch.num_input_per_level[nextlevel] - j; + /* Print the special basis subckt */ + /* Each basis muxQto1: svdd sgnd */ + fprintf(fp, "Xmux_special_basis_no%d ", mux_special_basis_cnt); /* given_name */ + for (k = 0; k < cur_num_input_basis; k++) { + fprintf(fp, "mux2_l%d_in%d ", level, j + k); /* input0 input1 */ + } + fprintf(fp, "mux2_l%d_in%d ", nextlevel, out_idx); /* output */ + /* Print number of sram bits for this basis */ + for (k = sram_idx; k < (sram_idx + cur_num_input_basis); k++) { + fprintf(fp, "%s%d %s_inv%d ", sram_port[0]->prefix, k, sram_port[0]->prefix, k); /* sram sram_inv */ + } + fprintf(fp, "svdd sgnd %s\n", mux_special_basis_subckt_name); /* subckt_name */ + /* update counter */ + mux_special_basis_cnt++; + continue; + } + /* Reach here, it means we need a normal basis subckt */ + /* Each basis muxQto1: svdd sgnd */ + fprintf(fp, "Xmux_basis_no%d ", mux_basis_cnt); /* given_name */ + for (k = 0; k < cur_num_input_basis; k++) { + fprintf(fp, "mux2_l%d_in%d ", level, j + k); /* input0 input1 */ + } + fprintf(fp, "mux2_l%d_in%d ", nextlevel, out_idx); /* output */ + /* Print number of sram bits for this basis */ + for (k = sram_idx; k < (sram_idx + cur_num_input_basis); k++) { + fprintf(fp, "%s%d %s_inv%d ", sram_port[0]->prefix, k, sram_port[0]->prefix, k); /* sram sram_inv */ + } + fprintf(fp, "svdd sgnd %s\n", mux_basis_subckt_name); /* subckt_name */ + /* Update the counter */ + mux_basis_cnt++; + } + } + /* Assert */ + assert(0 == nextlevel); + assert(0 == out_idx); + assert((1 == mux_special_basis_cnt)||(0 == mux_special_basis_cnt)); + assert((mux_basis_cnt + mux_special_basis_cnt) + == (int)((spice_mux_arch.num_input - 1)/(spice_mux_arch.num_input_basis - 1)) + 1); + + return; +} + +/** Generate the structure of 4T1R-based RRAM MUX structure + * 4T1R-based RRAM MUX is optimal in area, delay and power only when it is built with one-level structure + */ +void fprint_spice_rram_mux_onelevel_structure(FILE* fp, + char* mux_basis_subckt_name, + t_spice_model spice_model, + t_spice_mux_arch spice_mux_arch, + int num_sram_port, t_spice_model_port** sram_port) { + int k, mux_basis_cnt; + int level, nextlevel, out_idx, num_sram_bits; + + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + + assert(SPICE_MODEL_DESIGN_RRAM == spice_model.design_tech); + + /* Initialize */ + mux_basis_cnt = 0; + level = 1; + nextlevel = 0; + out_idx = 0; + + /* Each basis muxQto1: svdd sgnd */ + fprintf(fp, "Xmux_basis_no%d ", mux_basis_cnt); /* given_name */ + for (k = 0; k < spice_mux_arch.num_input; k++) { + fprintf(fp, "mux2_l%d_in%d ", level, k); /* input0 input1 */ + } + fprintf(fp, "mux2_l%d_in%d ", nextlevel, out_idx); /* output */ + + /* Print number of sram bits for this basis */ + num_sram_bits = determine_num_sram_bits_mux_basis_subckt(&spice_model, spice_mux_arch.num_input, + spice_mux_arch.num_input, + FALSE); + + for (k = 0; k < num_sram_bits; k++) { + fprintf(fp, "%s%d %s_inv%d ", sram_port[0]->prefix, k, sram_port[0]->prefix, k); /* sram sram_inv */ + } + fprintf(fp, "svdd sgnd %s\n", mux_basis_subckt_name); /* subckt_name */ + /* Update the counter */ + mux_basis_cnt++; + + return; +} + +void fprint_spice_mux_model_cmos_subckt(FILE* fp, + int mux_size, + t_spice_model spice_model, + t_spice_mux_arch spice_mux_arch) { + int i; + int num_input_port = 0; + int num_output_port = 0; + int num_sram_port = 0; + t_spice_model_port** input_port = NULL; + t_spice_model_port** output_port = NULL; + t_spice_model_port** sram_port = NULL; + int num_sram_bits = 0; + + enum e_spice_model_structure cur_mux_structure; + + /* Find the basis subckt*/ + char* mux_basis_subckt_name = NULL; + char* mux_special_basis_subckt_name = NULL; + + /* Basis is always needed */ + mux_basis_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model.name) + 5 + + strlen(my_itoa(mux_size)) + + strlen(mux_basis_posfix) + 1)); + sprintf(mux_basis_subckt_name, "%s_size%d%s", + spice_model.name, mux_size, mux_basis_posfix); + /* Special basis is on request, but anyway we prepare to call it.*/ + mux_special_basis_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model.name) + 5 + + strlen(my_itoa(mux_size)) + + strlen(mux_special_basis_posfix) + 1)); + sprintf(mux_special_basis_subckt_name, "%s_size%d%s", + spice_model.name, mux_size, mux_special_basis_posfix); + + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + + /* Ensure we have a CMOS MUX, + * ATTENTION: support LUT as well + */ + assert((SPICE_MODEL_MUX == spice_model.type)||(SPICE_MODEL_LUT == spice_model.type)); + assert(SPICE_MODEL_DESIGN_CMOS == spice_model.design_tech); + + /* Find the input port, output port, and sram port*/ + input_port = find_spice_model_ports(&spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + output_port = find_spice_model_ports(&spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + sram_port = find_spice_model_ports(&spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); + + /* Asserts*/ + assert(1 == num_input_port); + assert(1 == num_output_port); + assert(1 == num_sram_port); + assert(1 == output_port[0]->size); + + /* We have two types of naming rules in terms of the usage of MUXes: + * 1. MUXes, the naming rule is __size + * 2. LUTs, the naming rule is _mux_size + */ + num_sram_bits = count_num_sram_bits_one_spice_model(&spice_model, + /* sram_verilog_orgz_info->type, */ + mux_size); + + if (SPICE_MODEL_LUT == spice_model.type) { + /* Special for LUT MUX*/ + fprintf(fp, "***** CMOS MUX info: spice_model_name= %s_MUX, size=%d *****\n", spice_model.name, mux_size); + fprintf(fp, ".subckt %s_mux_size%d ", spice_model.name, mux_size); + /* Global ports */ + if (0 < rec_fprint_spice_model_global_ports(fp, &spice_model, FALSE)) { + fprintf(fp, "+ "); + } + /* Print input ports*/ + assert(mux_size == num_sram_bits); + for (i = 0; i < num_sram_bits; i++) { + fprintf(fp, "%s%d ", input_port[0]->prefix, i); + } + /* Print output ports*/ + fprintf(fp, "%s ", output_port[0]->prefix); + /* Print sram ports*/ + for (i = 0; i < input_port[0]->size; i++) { + fprintf(fp, "%s%d ", sram_port[0]->prefix, i); + fprintf(fp, "%s_inv%d ", sram_port[0]->prefix, i); + } + } else { + fprintf(fp, "***** CMOS MUX info: spice_model_name=%s, size=%d, structure: %s *****\n", + spice_model.name, mux_size, gen_str_spice_model_structure(spice_model.design_tech_info.structure)); + fprintf(fp, ".subckt %s_size%d ", spice_model.name, mux_size); + /* Global ports */ + if (0 < rec_fprint_spice_model_global_ports(fp, &spice_model, FALSE)) { + fprintf(fp, "+ "); + } + /* Print input ports*/ + for (i = 0; i < mux_size; i++) { + fprintf(fp, "%s%d ", input_port[0]->prefix, i); + } + /* Print output ports*/ + fprintf(fp, "%s ", output_port[0]->prefix); + /* Print sram ports*/ + for (i = 0; i < num_sram_bits; i++) { + fprintf(fp, "%s%d ", sram_port[0]->prefix, i); + fprintf(fp, "%s_inv%d ", sram_port[0]->prefix, i); + } + } + /* Print local vdd and gnd*/ + fprintf(fp, "svdd sgnd"); + fprintf(fp, "\n"); + + /* Handle the corner case: input size = 2 */ + if (2 == mux_size) { + cur_mux_structure = SPICE_MODEL_STRUCTURE_ONELEVEL; + } else { + cur_mux_structure = spice_model.design_tech_info.structure; + } + + /* Print internal architecture*/ + switch (cur_mux_structure) { + case SPICE_MODEL_STRUCTURE_TREE: + fprint_spice_cmos_mux_tree_structure(fp, mux_basis_subckt_name, + spice_model, spice_mux_arch, num_sram_port, sram_port); + break; + case SPICE_MODEL_STRUCTURE_ONELEVEL: + fprint_spice_cmos_mux_onelevel_structure(fp, mux_basis_subckt_name, + spice_model, spice_mux_arch, num_sram_port, sram_port); + break; + case SPICE_MODEL_STRUCTURE_MULTILEVEL: + fprint_spice_cmos_mux_multilevel_structure(fp, mux_basis_subckt_name, mux_special_basis_subckt_name, + spice_model, spice_mux_arch, num_sram_port, sram_port); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n", + __FILE__, __LINE__, spice_model.name); + exit(1); + } + + /* To connect the input ports*/ + for (i = 0; i < mux_size; i++) { + if (1 == spice_model.input_buffer->exist) { + switch (spice_model.input_buffer->type) { + case SPICE_MODEL_BUF_INV: + /* Each inv: svdd sgnd size=param*/ + fprintf(fp, "Xinv%d ", i); /* Given name*/ + fprintf(fp, "%s%d ", input_port[0]->prefix, i); /* input port */ + fprintf(fp, "mux2_l%d_in%d ", spice_mux_arch.input_level[i], spice_mux_arch.input_offset[i]); /* output port*/ + fprintf(fp, "svdd sgnd inv size=\'%s%s\'", spice_model.name, design_param_postfix_input_buf_size); /* subckt name */ + fprintf(fp, "\n"); + break; + case SPICE_MODEL_BUF_BUF: + /* TODO: what about tapered buffer, can we support? */ + /* Each buf: svdd sgnd size=param*/ + fprintf(fp, "Xbuf%d ", i); /* Given name*/ + fprintf(fp, "%s%d ", input_port[0]->prefix, i); /* input port */ + fprintf(fp, "mux2_l%d_in%d ", spice_mux_arch.input_level[i], spice_mux_arch.input_offset[i]); /* output port*/ + fprintf(fp, "svdd sgnd buf size=\'%s%s\'", spice_model.name, design_param_postfix_input_buf_size); /* subckt name */ + fprintf(fp, "\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type for spice_model_buffer.\n", + __FILE__, __LINE__); + exit(1); + } + } else { + /* There is no buffer, I create a zero resisitance between*/ + /* Resistance R 0*/ + fprintf(fp, "Rin%d %s%d mux2_l%d_in%d 0\n", + i, input_port[0]->prefix, i, spice_mux_arch.input_level[i], + spice_mux_arch.input_offset[i]); + } + } + + /* Output buffer*/ + if (1 == spice_model.output_buffer->exist) { + switch (spice_model.output_buffer->type) { + case SPICE_MODEL_BUF_INV: + if (TRUE == spice_model.output_buffer->tapered_buf) { + break; + } + /* Each inv: svdd sgnd size=param*/ + fprintf(fp, "Xinv_out "); /* Given name*/ + fprintf(fp, "mux2_l%d_in%d ", 0, 0); /* input port */ + fprintf(fp, "%s ", output_port[0]->prefix); /* Output port*/ + fprintf(fp, "svdd sgnd inv size=\'%s%s\'", spice_model.name, design_param_postfix_output_buf_size); /* subckt name */ + fprintf(fp, "\n"); + break; + case SPICE_MODEL_BUF_BUF: + if (TRUE == spice_model.output_buffer->tapered_buf) { + break; + } + /* Each buf: svdd sgnd size=param*/ + fprintf(fp, "Xbuf_out "); /* Given name*/ + fprintf(fp, "mux2_l%d_in%d ", 0, 0); /* input port */ + fprintf(fp, "%s ", output_port[0]->prefix); /* Output port*/ + fprintf(fp, "svdd sgnd buf size=\'%s%s\'", spice_model.name, design_param_postfix_output_buf_size); /* subckt name */ + fprintf(fp, "\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type for spice_model_buffer.\n", + __FILE__, __LINE__); + exit(1); + } + /* Tapered buffer support */ + if (TRUE == spice_model.output_buffer->tapered_buf) { + /* Each buf: svdd sgnd size=param*/ + fprintf(fp, "Xbuf_out "); /* Given name*/ + fprintf(fp, "mux2_l%d_in%d ", 0, 0); /* input port */ + fprintf(fp, "%s ", output_port[0]->prefix); /* Output port*/ + fprintf(fp, "svdd sgnd tapbuf_level%d_f%d", + spice_model.output_buffer->tap_buf_level, spice_model.output_buffer->f_per_stage); /* subckt name */ + fprintf(fp, "\n"); + } + } else { + /* There is no buffer, I create a zero resisitance between*/ + /* Resistance R 0*/ + fprintf(fp, "Rout mux2_l0_in0 %s 0\n",output_port[0]->prefix); + } + + fprintf(fp, ".eom\n"); + fprintf(fp, "***** END CMOS MUX info: spice_model_name=%s, size=%d *****\n", spice_model.name, mux_size); + fprintf(fp, "\n"); + + /* Free */ + my_free(mux_basis_subckt_name); + my_free(mux_special_basis_subckt_name); + my_free(input_port); + my_free(output_port); + my_free(sram_port); + + return; +} + +/* Print the RRAM MUX SPICE model. + * The internal structures of CMOS and RRAM MUXes are similar. + * This one can be merged to CMOS function. + * However I use another function, because in future the internal structure may change. + * We will suffer less software problems. + */ +void fprint_spice_mux_model_rram_subckt(FILE* fp, + int mux_size, + t_spice_model spice_model, + t_spice_mux_arch spice_mux_arch) { + int i; + int num_input_port = 0; + int num_output_port = 0; + int num_sram_port = 0; + t_spice_model_port** input_port = NULL; + t_spice_model_port** output_port = NULL; + t_spice_model_port** sram_port = NULL; + int num_sram_bits = 0; + + enum e_spice_model_structure cur_mux_structure; + + /* Find the basis subckt*/ + char* mux_basis_subckt_name = NULL; + char* mux_special_basis_subckt_name = NULL; + /* Basis is always needed */ + mux_basis_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model.name) + 5 + + strlen(my_itoa(mux_size)) + + strlen(mux_basis_posfix) + 1)); + sprintf(mux_basis_subckt_name, "%s_size%d%s", + spice_model.name, mux_size, mux_basis_posfix); + /* Special basis is on request, but anyway we prepare to call it.*/ + mux_special_basis_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model.name) + 5 + + strlen(my_itoa(mux_size)) + + strlen(mux_special_basis_posfix) + 1)); + sprintf(mux_basis_subckt_name, "%s_size%d%s", + spice_model.name, mux_size, mux_basis_posfix); + + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + + /* Ensure we have a RRAM MUX*/ + assert((SPICE_MODEL_MUX == spice_model.type)||(SPICE_MODEL_LUT == spice_model.type)); + assert(SPICE_MODEL_DESIGN_RRAM == spice_model.design_tech); + + /* Find the input port, output port, and sram port*/ + input_port = find_spice_model_ports(&spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + output_port = find_spice_model_ports(&spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + sram_port = find_spice_model_ports(&spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); + + /* Asserts*/ + assert(1 == num_input_port); + assert(1 == num_output_port); + assert(1 == num_sram_port); + assert(1 == output_port[0]->size); + + /* We have two types of naming rules in terms of the usage of MUXes: + * 1. MUXes, the naming rule is __size + * 2. LUTs, the naming rule is _mux_size + */ + num_sram_bits = count_num_conf_bits_one_spice_model(&spice_model, + sram_spice_orgz_info->type, + mux_size); + + /* Print the definition of subckt*/ + if (SPICE_MODEL_LUT == spice_model.type) { + /* RRAM LUT is not supported now... */ + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])RRAM LUT is not supported!\n", + __FILE__, __LINE__); + exit(1); + /* Special for LUT MUX*/ + /* + fprintf(fp, "***** RRAM MUX info: spice_model_name= %s_MUX, size=%d *****\n", spice_model.name, mux_size); + fprintf(fp, ".subckt %s_mux_size%d ", spice_model.name, mux_size); + */ + } else { + fprintf(fp, "***** RRAM MUX info: spice_model_name=%s, size=%d, structure: %s *****\n", + spice_model.name, mux_size, gen_str_spice_model_structure(spice_model.design_tech_info.structure)); + fprintf(fp, ".subckt %s_size%d ", spice_model.name, mux_size); + } + + /* Global ports */ + if (0 < rec_fprint_spice_model_global_ports(fp, &spice_model, FALSE)) { + fprintf(fp, "+ "); + } + + /* Print input ports*/ + for (i = 0; i < mux_size; i++) { + fprintf(fp, "%s%d ", input_port[0]->prefix, i); + } + /* Print output ports*/ + fprintf(fp, "%s ", output_port[0]->prefix); + /* Print sram ports*/ + for (i = 0; i < num_sram_bits; i++) { + fprintf(fp, "%s%d ", sram_port[0]->prefix, i); + fprintf(fp, "%s_inv%d ", sram_port[0]->prefix, i); + } + /* Print local vdd and gnd*/ + fprintf(fp, "svdd sgnd "); + fprintf(fp, "ron=\'%s%s\' roff=\'%s%s\' ", + spice_model.name, design_param_postfix_rram_ron, + spice_model.name, design_param_postfix_rram_roff); + fprintf(fp, "\n"); + + /* Print internal architecture*/ + /* Handle the corner case: input size = 2 */ + if (2 == mux_size) { + cur_mux_structure = SPICE_MODEL_STRUCTURE_ONELEVEL; + } else { + cur_mux_structure = spice_model.design_tech_info.structure; + } + /* RRAM MUX is optimal in terms of area, delay and power for one-level structure. + * Hence, we do not support the multi-level or tree-like RRAM MUX. + */ + switch (cur_mux_structure) { + case SPICE_MODEL_STRUCTURE_TREE: + fprint_spice_rram_mux_tree_structure(fp, mux_basis_subckt_name, + spice_model, spice_mux_arch, num_sram_port, sram_port); + break; + case SPICE_MODEL_STRUCTURE_MULTILEVEL: + fprint_spice_rram_mux_multilevel_structure(fp, mux_basis_subckt_name, mux_special_basis_subckt_name, + spice_model, spice_mux_arch, num_sram_port, sram_port); + break; + case SPICE_MODEL_STRUCTURE_ONELEVEL: + fprint_spice_rram_mux_onelevel_structure(fp, mux_basis_subckt_name, + spice_model, spice_mux_arch, num_sram_port, sram_port); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n", + __FILE__, __LINE__, spice_model.name); + exit(1); + } + + /* To connect the input ports*/ + for (i = 0; i < mux_size; i++) { + if (1 == spice_model.input_buffer->exist) { + switch (spice_model.input_buffer->type) { + case SPICE_MODEL_BUF_INV: + /* Each inv: svdd sgnd size=param*/ + fprintf(fp, "Xinv%d ", i); /* Given name*/ + fprintf(fp, "%s%d ", input_port[0]->prefix, i); /* input port */ + fprintf(fp, "mux2_l%d_in%d ", spice_mux_arch.input_level[i], spice_mux_arch.input_offset[i]); /* output port*/ + fprintf(fp, "svdd sgnd inv size=\'%s%s\'", spice_model.name, design_param_postfix_input_buf_size); /* subckt name */ + fprintf(fp, "\n"); + break; + case SPICE_MODEL_BUF_BUF: + /* TODO: what about tapered buffer, can we support? */ + /* Each buf: svdd sgnd size=param*/ + fprintf(fp, "Xbuf%d ", i); /* Given name*/ + fprintf(fp, "%s%d ", input_port[0]->prefix, i); /* input port */ + fprintf(fp, "mux2_l%d_in%d ", spice_mux_arch.input_level[i], spice_mux_arch.input_offset[i]); /* output port*/ + fprintf(fp, "svdd sgnd buf size=\'%s%s\'", spice_model.name, design_param_postfix_input_buf_size); /* subckt name */ + fprintf(fp, "\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type for spice_model_buffer.\n", + __FILE__, __LINE__); + exit(1); + } + } else { + /* There is no buffer, I create a zero resisitance between*/ + /* Resistance R 0*/ + fprintf(fp, "Rin%d %s%d mux2_l%d_in%d 0\n", + i, input_port[0]->prefix, i, spice_mux_arch.input_level[i], + spice_mux_arch.input_offset[i]); + } + } + + /* Output buffer*/ + if (1 == spice_model.output_buffer->exist) { + switch (spice_model.output_buffer->type) { + case SPICE_MODEL_BUF_INV: + if (TRUE == spice_model.output_buffer->tapered_buf) { + break; + } + /* Each inv: svdd sgnd size=param*/ + fprintf(fp, "Xinv_out "); /* Given name*/ + fprintf(fp, "mux2_l%d_in%d ", 0, 0); /* input port */ + fprintf(fp, "%s ", output_port[0]->prefix); /* Output port*/ + fprintf(fp, "svdd sgnd inv size=\'%s%s\'", spice_model.name, design_param_postfix_output_buf_size); /* subckt name */ + fprintf(fp, "\n"); + break; + case SPICE_MODEL_BUF_BUF: + if (TRUE == spice_model.output_buffer->tapered_buf) { + break; + } + /* Each buf: svdd sgnd size=param*/ + fprintf(fp, "Xbuf_out "); /* Given name*/ + fprintf(fp, "mux2_l%d_in%d ", 0, 0); /* input port */ + fprintf(fp, "%s ", output_port[0]->prefix); /* Output port*/ + fprintf(fp, "svdd sgnd buf size=\'%s%s\'", spice_model.name, design_param_postfix_output_buf_size); /* subckt name */ + fprintf(fp, "\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type for spice_model_buffer.\n", + __FILE__, __LINE__); + exit(1); + } + /* Tapered buffer support */ + if (TRUE == spice_model.output_buffer->tapered_buf) { + /* Each buf: svdd sgnd size=param*/ + fprintf(fp, "Xbuf_out "); /* Given name*/ + fprintf(fp, "mux2_l%d_in%d ", 0 , 0); /* input port */ + fprintf(fp, "%s ", output_port[0]->prefix); /* Output port*/ + fprintf(fp, "svdd sgnd tapbuf_level%d_f%d", + spice_model.output_buffer->tap_buf_level, spice_model.output_buffer->f_per_stage); /* subckt name */ + fprintf(fp, "\n"); + } + } else { + /* There is no buffer, I create a zero resisitance between*/ + /* Resistance R 0*/ + fprintf(fp, "Rout mux2_l0_in0 %s 0\n",output_port[0]->prefix); + } + + fprintf(fp, ".eom\n"); + fprintf(fp, "***** END RRAM MUX info: spice_model_name=%s, size=%d *****\n", spice_model.name, mux_size); + fprintf(fp, "\n"); + + /* Free */ + my_free(mux_basis_subckt_name); + my_free(input_port); + my_free(output_port); + my_free(sram_port); + + return; +} + +/* Print the SPICE model of a multiplexer subckt with given info */ +static +void fprint_spice_mux_model_subckt(FILE* fp, + t_spice_mux_model* spice_mux_model) { + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + /* Make sure we have a valid spice_model*/ + if (NULL == spice_mux_model) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid spice_mux_model!\n",__FILE__, __LINE__); + exit(1); + } + /* Make sure we have a valid spice_model*/ + if (NULL == spice_mux_model->spice_model) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid spice_model!\n",__FILE__, __LINE__); + exit(1); + } + + /* Check the mux size*/ + if (spice_mux_model->size < 2) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid MUX size(=%d)! Should be at least 2.\n", + __FILE__, __LINE__, spice_mux_model->size); + exit(1); + } + + /* Corner case: Error out MUX_SIZE = 2, automatcially give a one-level structure */ + /* + if ((2 == spice_mux_model->size)&&(SPICE_MODEL_STRUCTURE_ONELEVEL != spice_mux_model->spice_model->design_tech_info.structure)) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Structure of SPICE model (%s) should be one-level because it is linked to a 2:1 MUX!\n", + __FILE__, __LINE__, spice_mux_model->spice_model->name); + exit(1); + } + */ + + /* Print the definition of subckt*/ + + /* Check the design technology*/ + switch (spice_mux_model->spice_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + fprint_spice_mux_model_cmos_subckt(fp, spice_mux_model->size, + *(spice_mux_model->spice_model), *(spice_mux_model->spice_mux_arch)); + break; + case SPICE_MODEL_DESIGN_RRAM: + fprint_spice_mux_model_rram_subckt(fp, spice_mux_model->size, + *(spice_mux_model->spice_model), *(spice_mux_model->spice_mux_arch)); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of MUX(name: %s)\n", + __FILE__, __LINE__, spice_mux_model->spice_model->name); + exit(1); + } + return; +} + + +/* We should count how many multiplexers with different sizes are needed */ +void generate_spice_muxes(char* subckt_dir, + int num_switch, + t_switch_inf* switches, + t_spice* spice, + t_det_routing_arch* routing_arch) { + /* We have linked list whichs stores spice model information of multiplexer*/ + t_llist* muxes_head = NULL; + t_llist* temp = NULL; + int mux_cnt = 0; + int max_mux_size = -1; + int min_mux_size = -1; + FILE* fp = NULL; + char* sp_name = my_strcat(subckt_dir,muxes_spice_file_name); + int num_input_ports = 0; + t_spice_model_port** input_ports = NULL; + int num_sram_ports = 0; + t_spice_model_port** sram_ports = NULL; + + int num_input_basis = 0; + t_spice_mux_model* cur_spice_mux_model = NULL; + + /* Alloc the muxes*/ + muxes_head = stats_spice_muxes(num_switch, switches, spice, routing_arch); + + /* Print the muxes netlist*/ + fp = fopen(sp_name, "w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create subckt SPICE netlist %s",__FILE__, __LINE__, sp_name); + exit(1); + } + /* Generate the descriptions*/ + fprint_spice_head(fp,"MUXes used in FPGA"); + + /* Print mux netlist one by one*/ + temp = muxes_head; + while(temp) { + assert(NULL != temp->dptr); + cur_spice_mux_model = (t_spice_mux_model*)(temp->dptr); + /* Bypass the spice models who has a user-defined subckt */ + if (NULL != cur_spice_mux_model->spice_model->model_netlist) { + input_ports = find_spice_model_ports(cur_spice_mux_model->spice_model, SPICE_MODEL_PORT_INPUT, &num_input_ports, TRUE); + sram_ports = find_spice_model_ports(cur_spice_mux_model->spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_ports, TRUE); + assert(0 != num_input_ports); + assert(0 != num_sram_ports); + /* Check the Input port size */ + if (cur_spice_mux_model->size != input_ports[0]->size) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])User-defined MUX SPICE MODEL(%s) size(%d) unmatch with the architecture needs(%d)!\n", + __FILE__, __LINE__, cur_spice_mux_model->spice_model->name, input_ports[0]->size,cur_spice_mux_model->size); + exit(1); + } + /* Check the SRAM port size */ + num_input_basis = determine_num_input_basis_multilevel_mux(cur_spice_mux_model->size, + cur_spice_mux_model->spice_model->design_tech_info.mux_num_level); + if ((num_input_basis * cur_spice_mux_model->spice_model->design_tech_info.mux_num_level) != sram_ports[0]->size) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])User-defined MUX SPICE MODEL(%s) SRAM size(%d) unmatch with the num of level(%d)!\n", + __FILE__, __LINE__, cur_spice_mux_model->spice_model->name, sram_ports[0]->size, cur_spice_mux_model->spice_model->design_tech_info.mux_num_level*num_input_basis); + exit(1); + } + /* Move on to the next*/ + temp = temp->next; + continue; + } + /* Let's have a N:1 MUX as basis*/ + fprint_spice_mux_model_basis_subckt(fp, cur_spice_mux_model); + /* Print the mux subckt */ + fprint_spice_mux_model_subckt(fp, cur_spice_mux_model); + /* Update the statistics*/ + mux_cnt++; + if ((-1 == max_mux_size)||(max_mux_size < cur_spice_mux_model->size)) { + max_mux_size = cur_spice_mux_model->size; + } + if ((-1 == min_mux_size)||(min_mux_size > cur_spice_mux_model->size)) { + min_mux_size = cur_spice_mux_model->size; + } + /* Move on to the next*/ + temp = temp->next; + } + + vpr_printf(TIO_MESSAGE_INFO,"Generated %d Multiplexer subckts.\n", + mux_cnt); + vpr_printf(TIO_MESSAGE_INFO,"Max. MUX size = %d.\t", + max_mux_size); + vpr_printf(TIO_MESSAGE_INFO,"Min. MUX size = %d.\n", + min_mux_size); + + + /* remember to free the linked list*/ + free_muxes_llist(muxes_head); + /* Free strings */ + free(sp_name); + + /* Close the file*/ + fclose(fp); + + return; +} + diff --git a/vpr7_rram/vpr/SRC/spice/spice_mux.h b/vpr7_rram/vpr/SRC/spice/spice_mux.h new file mode 100644 index 000000000..8e104ae1f --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_mux.h @@ -0,0 +1,19 @@ + + + +void generate_spice_muxes(char* subckt_dir, + int num_switch, + t_switch_inf* switches, + t_spice* spice, + t_det_routing_arch* routing_arch); + +t_llist* search_mux_linked_list(t_llist* mux_head, + int mux_size, + t_spice_model* spice_model); + +void check_and_add_mux_to_linked_list(t_llist** muxes_head, + int mux_size, + t_spice_model* spice_model); + +void free_muxes_llist(t_llist* muxes_head); + diff --git a/vpr7_rram/vpr/SRC/spice/spice_mux_testbench.c b/vpr7_rram/vpr/SRC/spice/spice_mux_testbench.c new file mode 100644 index 000000000..e0a388744 --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_mux_testbench.c @@ -0,0 +1,2010 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph_util.h" +#include "rr_graph.h" +#include "rr_graph2.h" +#include "vpr_utils.h" + +/* Include spice support headers*/ +#include "linkedlist.h" +#include "fpga_spice_globals.h" +#include "spice_globals.h" +#include "fpga_spice_utils.h" +#include "spice_utils.h" +#include "spice_routing.h" +#include "spice_subckt.h" +#include "spice_mux_testbench.h" + +/** In this test bench. + * All the multiplexers (Local routing, Switch Boxes, Connection Blocks) in the FPGA are examined + * All the multiplexers are hanged with equivalent capactive loads in their context. + */ + +/* Global variables in this C-source file */ +static int testbench_mux_cnt = 0; +static int testbench_sram_cnt = 0; +static int testbench_load_cnt = 0; +static int testbench_pb_mux_cnt = 0; +static int testbench_cb_mux_cnt = 0; +static int testbench_sb_mux_cnt = 0; +static int num_segments; +static t_segment_inf* segments; +static t_llist* testbench_muxes_head = NULL; +static int upbound_sim_num_clock_cycles = 2; +static int max_sim_num_clock_cycles = 2; +static int auto_select_max_sim_num_clock_cycles = TRUE; + +static float total_pb_mux_input_density = 0.; +static float total_cb_mux_input_density = 0.; +static float total_sb_mux_input_density = 0.; + +/***** Local Subroutines Declaration *****/ + +/***** Local Subroutines *****/ +static void init_spice_mux_testbench_globals(t_spice spice) { + testbench_mux_cnt = 0; + testbench_sram_cnt = 0; + testbench_load_cnt = 0; + testbench_muxes_head = NULL; + testbench_pb_mux_cnt = 0; + testbench_cb_mux_cnt = 0; + testbench_sb_mux_cnt = 0; + auto_select_max_sim_num_clock_cycles = spice.spice_params.meas_params.auto_select_sim_num_clk_cycle; + upbound_sim_num_clock_cycles = spice.spice_params.meas_params.sim_num_clock_cycle + 1; + if (FALSE == auto_select_max_sim_num_clock_cycles) { + max_sim_num_clock_cycles = spice.spice_params.meas_params.sim_num_clock_cycle + 1; + } else { + max_sim_num_clock_cycles = 2; + } +} + +static +void fprint_spice_mux_testbench_global_ports(FILE* fp, + t_spice spice) { + /* A valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); + exit(1); + } + + /* Print generic global ports*/ + fprint_spice_generic_testbench_global_ports(fp, + sram_spice_orgz_info, + global_ports_head); + + return; +} + +static +void fprint_spice_mux_testbench_pb_mux_meas(FILE* fp, + char* meas_tag) { + /* A valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); + exit(1); + } + + if (0 == testbench_pb_mux_cnt) { + fprintf(fp, ".meas tran sum_leakage_power_pb_mux[0to%d] \n", testbench_pb_mux_cnt); + fprintf(fp, "+ param=\'leakage_%s\'\n", meas_tag); + fprintf(fp, ".meas tran sum_energy_per_cycle_pb_mux[0to%d] \n", testbench_pb_mux_cnt); + fprintf(fp, "+ param=\'energy_per_cycle_%s\'\n", meas_tag); + } else { + fprintf(fp, ".meas tran sum_leakage_power_pb_mux[0to%d] \n", testbench_pb_mux_cnt); + fprintf(fp, "+ param=\'sum_leakage_power_pb_mux[0to%d]+leakage_%s\'\n", testbench_pb_mux_cnt-1, meas_tag); + fprintf(fp, ".meas tran sum_energy_per_cycle_pb_mux[0to%d] \n", testbench_pb_mux_cnt); + fprintf(fp, "+ param=\'sum_energy_per_cycle_pb_mux[0to%d]+energy_per_cycle_%s\'\n", testbench_pb_mux_cnt-1, meas_tag); + } + + /* Update the counter */ + testbench_pb_mux_cnt++; + + return; +} + +static +void fprint_spice_mux_testbench_cb_mux_meas(FILE* fp, + char* meas_tag) { + /* A valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); + exit(1); + } + + if (0 == testbench_cb_mux_cnt) { + fprintf(fp, ".meas tran sum_leakage_power_cb_mux[0to%d] \n", testbench_cb_mux_cnt); + fprintf(fp, "+ param=\'leakage_%s\'\n", meas_tag); + fprintf(fp, ".meas tran sum_energy_per_cycle_cb_mux[0to%d] \n", testbench_cb_mux_cnt); + fprintf(fp, "+ param=\'energy_per_cycle_%s\'\n", meas_tag); + } else { + fprintf(fp, ".meas tran sum_leakage_power_cb_mux[0to%d] \n", testbench_cb_mux_cnt); + fprintf(fp, "+ param=\'sum_leakage_power_cb_mux[0to%d]+leakage_%s\'\n", testbench_cb_mux_cnt-1, meas_tag); + fprintf(fp, ".meas tran sum_energy_per_cycle_cb_mux[0to%d] \n", testbench_cb_mux_cnt); + fprintf(fp, "+ param=\'sum_energy_per_cycle_cb_mux[0to%d]+energy_per_cycle_%s\'\n", testbench_cb_mux_cnt-1, meas_tag); + } + + /* Update the counter */ + testbench_cb_mux_cnt++; + + return; +} + +static +void fprint_spice_mux_testbench_sb_mux_meas(FILE* fp, + char* meas_tag) { + /* A valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); + exit(1); + } + + if (0 == testbench_sb_mux_cnt) { + fprintf(fp, ".meas tran sum_leakage_power_sb_mux[0to%d] \n", testbench_sb_mux_cnt); + fprintf(fp, "+ param=\'leakage_%s\'\n", meas_tag); + fprintf(fp, ".meas tran sum_energy_per_cycle_sb_mux[0to%d] \n", testbench_sb_mux_cnt); + fprintf(fp, "+ param=\'energy_per_cycle_%s\'\n", meas_tag); + } else { + fprintf(fp, ".meas tran sum_leakage_power_sb_mux[0to%d] \n", testbench_sb_mux_cnt); + fprintf(fp, "+ param=\'sum_leakage_power_sb_mux[0to%d]+leakage_%s\'\n", testbench_sb_mux_cnt-1, meas_tag); + fprintf(fp, ".meas tran sum_energy_per_cycle_sb_mux[0to%d] \n", testbench_sb_mux_cnt); + fprintf(fp, "+ param=\'sum_energy_per_cycle_sb_mux[0to%d]+energy_per_cycle_%s\'\n", testbench_sb_mux_cnt-1, meas_tag); + } + + /* Update the counter */ + testbench_sb_mux_cnt++; + + return; +} + + +static +void fprint_spice_mux_testbench_one_mux(FILE* fp, + char* meas_tag, + t_spice_model* mux_spice_model, + int mux_size, + int* input_init_value, + float* input_density, + float* input_probability, + int path_id) { + int inode, mux_level, ilevel, cur_num_sram; + int num_mux_sram_bits = 0; + int* mux_sram_bits = NULL; + t_llist* found_mux_node = NULL; + t_spice_mux_model* cur_mux = NULL; + int num_sim_clock_cycles = 0; + float average_density = 0.; + int avg_density_cnt = 0; + char* sram_vdd_port_name = NULL; + + /* A valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert(NULL != mux_spice_model); + assert((2 < mux_size)||(2 == mux_size)); + assert(NULL != input_density); + assert(NULL != input_probability); + + /* Add to linked list */ + check_and_add_mux_to_linked_list(&(testbench_muxes_head), mux_size, mux_spice_model); + found_mux_node = search_mux_linked_list(testbench_muxes_head, mux_size, mux_spice_model); + /* Check */ + assert(NULL != found_mux_node); + cur_mux = (t_spice_mux_model*)(found_mux_node->dptr); + assert(mux_spice_model == cur_mux->spice_model); + + /* Call the subckt that has already been defined before */ + fprintf(fp, "X%s_size%d[%d] ", mux_spice_model->prefix, mux_size, testbench_mux_cnt); + /* Global ports */ + if (0 < rec_fprint_spice_model_global_ports(fp, mux_spice_model, FALSE)) { + fprintf(fp, "+ "); + } + /* input port*/ + for (inode = 0; inode < mux_size; inode++) { + fprintf(fp, "%s_size%d[%d]->in[%d] ", + mux_spice_model->prefix, mux_size, testbench_mux_cnt, inode); + } + /* Output port */ + fprintf(fp, "%s_size%d[%d]->out ", + mux_spice_model->prefix, mux_size, testbench_mux_cnt); + + /* SRAMs */ + /* Print SRAM configurations, + * we should have a global SRAM vdd, AND it should be connected to a real sram subckt !!! + */ + /* Configuration bits for MUX*/ + assert((-1 != path_id)&&(path_id < mux_size)); + + /* 1. Get the mux level*/ + switch (mux_spice_model->design_tech_info.structure) { + case SPICE_MODEL_STRUCTURE_TREE: + mux_level = determine_tree_mux_level(mux_size); + num_mux_sram_bits = mux_level; + mux_sram_bits = decode_tree_mux_sram_bits(mux_size, mux_level, path_id); + break; + case SPICE_MODEL_STRUCTURE_ONELEVEL: + mux_level = 1; + /* Special for 2-input MUX */ + if (2 == mux_size) { + num_mux_sram_bits = 1; + mux_sram_bits = decode_tree_mux_sram_bits(mux_size, mux_level, path_id); + } else { + num_mux_sram_bits = mux_size; + mux_sram_bits = decode_onelevel_mux_sram_bits(mux_size, mux_level, path_id); + } + break; + case SPICE_MODEL_STRUCTURE_MULTILEVEL: + /* Special for 2-input MUX */ + if (2 == mux_size) { + mux_level = 1; + num_mux_sram_bits = 1; + mux_sram_bits = decode_tree_mux_sram_bits(mux_size, 1, path_id); + } else { + mux_level = mux_spice_model->design_tech_info.mux_num_level; + num_mux_sram_bits = determine_num_input_basis_multilevel_mux(mux_size, mux_level) * mux_level; + mux_sram_bits = decode_multilevel_mux_sram_bits(mux_size, mux_level, path_id); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n", + __FILE__, __LINE__, mux_spice_model->name); + exit(1); + } + + /* Print SRAMs that configure this MUX */ + /* Get current counter of mem_bits, bl and wl */ + cur_num_sram = testbench_sram_cnt; + for (ilevel = 0; ilevel < num_mux_sram_bits; ilevel++) { + assert( (0 == mux_sram_bits[ilevel]) || (1 == mux_sram_bits[ilevel]) ); + fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, + cur_num_sram + ilevel, mux_sram_bits[ilevel]); + fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, + cur_num_sram + ilevel, 1 - mux_sram_bits[ilevel]); + } + + /* End with svdd and sgnd, subckt name*/ + /* Local vdd and gnd, we should have an independent VDD for all local interconnections*/ + fprintf(fp, "gvdd_%s_size%d[%d] 0 ", mux_spice_model->prefix, mux_size, testbench_mux_cnt); + /* End with spice_model name */ + fprintf(fp, "%s_size%d\n", mux_spice_model->name, mux_size); + + + /* Print the encoding in SPICE netlist for debugging */ + fprintf(fp, "***** SRAM bits for MUX[%d], level=%d, select_path_id=%d. *****\n", + testbench_mux_cnt, mux_level, path_id); + fprintf(fp, "*****"); + for (ilevel = 0; ilevel < num_mux_sram_bits; ilevel++) { + fprintf(fp, "%d", mux_sram_bits[ilevel]); + } + fprintf(fp, "*****\n"); + + /* Force SRAM bits */ + /* cur_num_sram = testbench_sram_cnt; */ + /* + for (ilevel = 0; ilevel < mux_level; ilevel++) { + fprintf(fp,"V%s[%d]->in %s[%d]->in 0 ", + sram_spice_model->prefix, cur_num_sram, sram_spice_model->prefix, cur_num_sram); + fprintf(fp, "0\n"); + cur_num_sram++; + } + */ + + /* Call SRAM subckts*/ + /* Give the VDD port name for SRAMs */ + sram_vdd_port_name = (char*)my_malloc(sizeof(char)* + (strlen(spice_tb_global_vdd_sram_port_name) + + 1 )); + sprintf(sram_vdd_port_name, "%s", + spice_tb_global_vdd_sram_port_name); + /* Now Print SRAMs one by one */ + for (ilevel = 0; ilevel < num_mux_sram_bits; ilevel++) { + fprint_spice_one_specific_sram_subckt(fp, sram_spice_orgz_info, mux_spice_model, + sram_vdd_port_name, testbench_sram_cnt); + testbench_sram_cnt++; + } + + /* Test bench : Add voltage sources */ + for (inode = 0; inode < mux_size; inode++) { + /* Print voltage source */ + fprintf(fp, "***** Signal %s_size%d[%d]->in[%d] density = %g, probability=%g.*****\n", + mux_spice_model->prefix, mux_size, testbench_mux_cnt, inode, input_density[inode], input_probability[inode]); + fprintf(fp, "V%s_size%d[%d]->in[%d] %s_size%d[%d]->in[%d] 0 \n", + mux_spice_model->prefix, mux_size, testbench_mux_cnt, inode, + mux_spice_model->prefix, mux_size, testbench_mux_cnt, inode); + fprint_voltage_pulse_params(fp, input_init_value[inode], input_density[inode], input_probability[inode]); + /* fprint_voltage_pulse_params(fp, input_init_value[inode], 1, 0.5); */ + } + /* global voltage supply */ + fprintf(fp, "Vgvdd_%s_size%d[%d] gvdd_%s_size%d[%d] 0 vsp\n", + mux_spice_model->prefix, mux_size, testbench_mux_cnt, + mux_spice_model->prefix, mux_size, testbench_mux_cnt); + + /* Calculate average density of this MUX */ + average_density = 0.; + avg_density_cnt = 0; + for (inode = 0; inode < mux_size; inode++) { + assert(!(0 > input_density[inode])); + if (0. < input_density[inode]) { + average_density += input_density[inode]; + avg_density_cnt++; + } + } + /* Calculate the num_sim_clock_cycle for this MUX, update global max_sim_clock_cycle in this testbench */ + if (0 < avg_density_cnt) { + average_density = average_density/avg_density_cnt; + num_sim_clock_cycles = (int)(1/average_density) + 1; + } else { + assert(0 == avg_density_cnt); + average_density = 0.; + num_sim_clock_cycles = 2; + } + if (TRUE == auto_select_max_sim_num_clock_cycles) { + /* for idle blocks, 2 clock cycle is well enough... */ + if (2 < num_sim_clock_cycles) { + num_sim_clock_cycles = upbound_sim_num_clock_cycles; + } else { + num_sim_clock_cycles = 2; + } + if (max_sim_num_clock_cycles < num_sim_clock_cycles) { + max_sim_num_clock_cycles = num_sim_clock_cycles; + } + } else { + num_sim_clock_cycles = max_sim_num_clock_cycles; + } + + /* Measurements */ + /* Measure the delay of MUX */ + fprintf(fp, "***** Measurements *****\n"); + /* Rise delay */ + fprintf(fp, "***** Rise delay *****\n"); + fprintf(fp, ".meas tran delay_rise_%s trig v(%s_size%d[%d]->in[%d]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'\n", meas_tag, mux_spice_model->prefix, mux_size, testbench_mux_cnt, path_id); + fprintf(fp, "+ targ v(%s_size%d[%d]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'\n", + mux_spice_model->prefix, mux_size, testbench_mux_cnt); + /* Fall delay */ + fprintf(fp, "***** Fall delay *****\n"); + fprintf(fp, ".meas tran delay_fall_%s trig v(%s_size%d[%d]->in[%d]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'\n", meas_tag, mux_spice_model->prefix, mux_size, testbench_mux_cnt, path_id); + fprintf(fp, "+ targ v(%s_size%d[%d]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'\n", + mux_spice_model->prefix, mux_size, testbench_mux_cnt); + /* Measure timing period of MUX switching */ + /* Rise */ + fprintf(fp, "***** Rise timing period *****\n"); + fprintf(fp, ".meas start_rise_%s when v(%s_size%d[%d]->in[%d])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'\n", + meas_tag, mux_spice_model->prefix, mux_size, testbench_mux_cnt, path_id); + fprintf(fp, ".meas tran switch_rise_%s trig v(%s_size%d[%d]->in[%d]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'\n", meas_tag, mux_spice_model->prefix, mux_size, testbench_mux_cnt, path_id); + fprintf(fp, "+ targ v(%s_size%d[%d]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'\n", + mux_spice_model->prefix, mux_size, testbench_mux_cnt); + /* Fall */ + fprintf(fp, "***** Fall timing period *****\n"); + fprintf(fp, ".meas start_fall_%s when v(%s_size%d[%d]->in[%d])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'\n", + meas_tag, mux_spice_model->prefix, mux_size, testbench_mux_cnt, path_id); + fprintf(fp, ".meas tran switch_fall_%s trig v(%s_size%d[%d]->in[%d]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'\n", meas_tag, mux_spice_model->prefix, mux_size, testbench_mux_cnt, path_id); + fprintf(fp, "+ targ v(%s_size%d[%d]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'\n", + mux_spice_model->prefix, mux_size, testbench_mux_cnt); + /* Measure the leakage power of MUX */ + fprintf(fp, "***** Leakage Power Measurement *****\n"); + fprintf(fp, ".meas tran %s_size%d[%d]_leakage_power avg p(Vgvdd_%s_size%d[%d]) from=0 to='clock_period'\n", + mux_spice_model->prefix, mux_size, testbench_mux_cnt, + mux_spice_model->prefix, mux_size, testbench_mux_cnt); + fprintf(fp, ".meas tran leakage_%s param='%s_size%d[%d]_leakage_power'\n", + meas_tag, mux_spice_model->prefix, mux_size, testbench_mux_cnt); + /* Measure the dynamic power of MUX */ + fprintf(fp, "***** Dynamic Power Measurement *****\n"); + fprintf(fp, ".meas tran %s_size%d[%d]_dynamic_power avg p(Vgvdd_%s_size%d[%d]) from='clock_period' to='%d*clock_period'\n", + mux_spice_model->prefix, mux_size, testbench_mux_cnt, + mux_spice_model->prefix, mux_size, testbench_mux_cnt, num_sim_clock_cycles); + fprintf(fp, ".meas tran %s_size%d[%d]_energy_per_cycle param='%s_size%d[%d]_dynamic_power*clock_period'\n", + mux_spice_model->prefix, mux_size, testbench_mux_cnt, + mux_spice_model->prefix, mux_size, testbench_mux_cnt); + /* Important: to give dynamic power measurement per toggle !!!! + * it is not fair to compare dynamic power when clock_period is different from designs to designs !!! + */ + fprintf(fp, ".meas tran dynamic_power_%s param='%s_size%d[%d]_dynamic_power'\n", + meas_tag, mux_spice_model->prefix, mux_size, testbench_mux_cnt); + fprintf(fp, ".meas tran energy_per_cycle_%s param='dynamic_power_%s*clock_period'\n", + meas_tag, meas_tag); + fprintf(fp, ".meas tran dynamic_rise_%s avg p(Vgvdd_%s_size%d[%d]) from='start_rise_%s' to='start_rise_%s+switch_rise_%s'\n", + meas_tag, mux_spice_model->prefix, mux_size, testbench_mux_cnt, meas_tag, meas_tag, meas_tag); + fprintf(fp, ".meas tran dynamic_fall_%s avg p(Vgvdd_%s_size%d[%d]) from='start_fall_%s' to='start_fall_%s+switch_fall_%s'\n", + meas_tag, mux_spice_model->prefix, mux_size, testbench_mux_cnt, meas_tag, meas_tag, meas_tag); + /* + fprintf(fp, ".meas tran %s_size%d[%d]_dynamic_power param='(dynamic_rise_%s)*(%g*%d)'\n", + mux_spice_model->prefix, mux_size, testbench_mux_cnt, + meas_tag, input_density[path_id], sim_num_clock_cycle-1); + fprintf(fp, ".meas tran dynamic_%s param='(dynamic_rise_%s)*(%g*%d)'\n", + meas_tag, meas_tag, input_density[path_id], sim_num_clock_cycle-1); + */ + if (0 == testbench_mux_cnt) { + fprintf(fp, ".meas tran sum_leakage_power_mux[0to%d] \n", testbench_mux_cnt); + fprintf(fp, "+ param=\'leakage_%s\'\n", meas_tag); + fprintf(fp, ".meas tran sum_energy_per_cycle_mux[0to%d] \n", testbench_mux_cnt); + fprintf(fp, "+ param=\'energy_per_cycle_%s\'\n", meas_tag); + } else { + fprintf(fp, ".meas tran sum_leakage_power_mux[0to%d] \n", testbench_mux_cnt); + fprintf(fp, "+ param=\'sum_leakage_power_mux[0to%d]+leakage_%s\'\n", testbench_mux_cnt-1, meas_tag); + fprintf(fp, ".meas tran sum_energy_per_cycle_mux[0to%d] \n", testbench_mux_cnt); + fprintf(fp, "+ param=\'sum_energy_per_cycle_mux[0to%d]+energy_per_cycle_%s\'\n", testbench_mux_cnt-1, meas_tag); + } + + /* Free */ + my_free(mux_sram_bits); + my_free(sram_vdd_port_name); + + return; +} + +/** Print a mulitplexer testbench of a given pb pin + * --|---| + * --| M | + * ..| U |--- des_pb_graph_in + * --| X | + * --|---| + */ +static +void fprint_spice_mux_testbench_pb_graph_node_pin_mux(FILE* fp, + t_mode* cur_mode, + t_pb_graph_pin* des_pb_graph_pin, + t_interconnect* cur_interc, + int fan_in, + int select_edge, + int grid_x, int grid_y, + t_ivec*** LL_rr_node_indices) { + int cur_input = 0; + float* input_density = NULL; + float* input_probability = NULL; + int* input_init_value = NULL; + int iedge; + int* sram_bits = NULL; + char* meas_tag = NULL; + char* outport_name = NULL; + + float average_pb_mux_input_density = 0.; + + /* A valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); + exit(1); + } + /* Check : + * MUX should have at least 2 fan_in + */ + assert((2 == fan_in)||(2 < fan_in)); + /* 2. spice_model is a wire */ + assert(NULL != cur_interc->spice_model); + assert(SPICE_MODEL_MUX == cur_interc->spice_model->type); + + /* Test bench : Add voltage sources */ + cur_input = 0; + input_density = (float*)my_malloc(sizeof(float)*fan_in); + input_probability = (float*)my_malloc(sizeof(float)*fan_in); + input_init_value = (int*)my_malloc(sizeof(int)*fan_in); + for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { + if (cur_mode != des_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode) { + continue; + } + check_pb_graph_edge(*(des_pb_graph_pin->input_edges[iedge])); + /* Find activity information */ + input_density[cur_input] = pb_pin_density(NULL, des_pb_graph_pin->input_edges[iedge]->input_pins[0]); + input_probability[cur_input] = pb_pin_probability(NULL, des_pb_graph_pin->input_edges[iedge]->input_pins[0]); + input_init_value[cur_input] = pb_pin_init_value(NULL, des_pb_graph_pin->input_edges[iedge]->input_pins[0]); + average_pb_mux_input_density += input_density[cur_input]; + cur_input++; + } + average_pb_mux_input_density = average_pb_mux_input_density/fan_in; + total_pb_mux_input_density += average_pb_mux_input_density; + /* Check fan-in number is correct */ + assert(fan_in == cur_input); + + /* Build a measurement tag: _[pin_index]_ */ + meas_tag = (char*)my_malloc(sizeof(char)* (10 + strlen(my_itoa(fan_in)) + strlen(my_itoa(testbench_mux_cnt)) + 2 + + strlen(des_pb_graph_pin->port->name) + 1 + + strlen(my_itoa(des_pb_graph_pin->pin_number)) + 2 + + strlen(cur_interc->name) + 1)); /* Add '0'*/ + sprintf(meas_tag, "idle_mux%d[%d]_%s[%d]_%s", + fan_in, testbench_mux_cnt, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number, cur_interc->name); + /* Print the main part of a single MUX testbench */ + fprint_spice_mux_testbench_one_mux(fp, meas_tag, cur_interc->spice_model, + fan_in, input_init_value, input_density, input_probability, select_edge); + + /* Test bench : Capactive load */ + /* TODO: Search all the fan-outs of des_pb_graph_pin */ + outport_name = (char*)my_malloc(sizeof(char)*( strlen(cur_interc->spice_model->prefix) + 5 + + strlen(my_itoa(fan_in)) + 1 + strlen(my_itoa(testbench_mux_cnt)) + + 7 )); + sprintf(outport_name, "%s_size%d[%d]->out", + cur_interc->spice_model->prefix, fan_in, testbench_mux_cnt); + + if (TRUE == run_testbench_load_extraction) { /* Additional switch, default on! */ + fprint_spice_testbench_pb_graph_pin_inv_loads_rec(fp, &testbench_load_cnt, + grid_x, grid_y, + des_pb_graph_pin, NULL, + outport_name, TRUE, + LL_rr_node_indices); + } + + fprint_spice_mux_testbench_pb_mux_meas(fp, meas_tag); + /* Update the counter */ + testbench_mux_cnt++; + + /* Free */ + my_free(sram_bits); + my_free(input_init_value); + my_free(input_density); + my_free(input_probability); + my_free(outport_name); + + return; +} + + +/** Print a mulitplexer testbench of a given pb pin + * --|---| + * --| M | + * ..| U |--- des_pb_graph_in + * --| X | + * --|---| + */ +static +void fprint_spice_mux_testbench_pb_pin_mux(FILE* fp, + t_rr_node* pb_rr_graph, + t_pb* des_pb, + t_mode* cur_mode, + t_pb_graph_pin* des_pb_graph_pin, + t_interconnect* cur_interc, + int fan_in, + int select_edge, + int grid_x, int grid_y, + t_ivec*** LL_rr_node_indices) { + int cur_input = 0; + float* input_density = NULL; + float* input_probability = NULL; + int* input_init_value = NULL; + int iedge; + int* sram_bits = NULL; + char* meas_tag = NULL; + char* outport_name = NULL; + float average_pb_mux_input_density = 0.; + + /* A valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); + exit(1); + } + /* Check : + * MUX should have at least 2 fan_in + */ + assert((2 == fan_in)||(2 < fan_in)); + /* 2. spice_model is a wire */ + assert(NULL != cur_interc->spice_model); + assert(SPICE_MODEL_MUX == cur_interc->spice_model->type); + + /* Test bench : Add voltage sources */ + cur_input = 0; + input_density = (float*)my_malloc(sizeof(float)*fan_in); + input_probability = (float*)my_malloc(sizeof(float)*fan_in); + input_init_value = (int*)my_malloc(sizeof(int)*fan_in); + for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { + if (cur_mode != des_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode) { + continue; + } + check_pb_graph_edge(*(des_pb_graph_pin->input_edges[iedge])); + /* Find activity information */ + input_density[cur_input] = pb_pin_density(pb_rr_graph, des_pb_graph_pin->input_edges[iedge]->input_pins[0]); + input_probability[cur_input] = pb_pin_probability(pb_rr_graph, des_pb_graph_pin->input_edges[iedge]->input_pins[0]); + input_init_value[cur_input] = pb_pin_init_value(pb_rr_graph, des_pb_graph_pin->input_edges[iedge]->input_pins[0]); + average_pb_mux_input_density += input_density[cur_input]; + cur_input++; + } + average_pb_mux_input_density = average_pb_mux_input_density/fan_in; + total_pb_mux_input_density += average_pb_mux_input_density; + /* Check fan-in number is correct */ + assert(fan_in == cur_input); + + /* Build a measurement tag: _[pin_index]_ */ + meas_tag = (char*)my_malloc(sizeof(char)* (strlen(des_pb->spice_name_tag) + 1 + + strlen(des_pb_graph_pin->port->name) + 1 + + strlen(my_itoa(des_pb_graph_pin->pin_number)) + 2 + + strlen(cur_interc->name) + 1)); /* Add '0'*/ + sprintf(meas_tag, "%s_%s[%d]_%s", + des_pb->spice_name_tag, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number, cur_interc->name); + /* Print the main part of a single MUX testbench */ + fprint_spice_mux_testbench_one_mux(fp, meas_tag, cur_interc->spice_model, + fan_in, input_init_value, input_density, input_probability, select_edge); + + /* Test bench : Capactive load */ + /* Search all the fan-outs of des_pb_graph_pin */ + outport_name = (char*)my_malloc(sizeof(char)*( strlen(cur_interc->spice_model->prefix) + 5 + + strlen(my_itoa(fan_in)) + 1 + strlen(my_itoa(testbench_mux_cnt)) + + 7 )); + sprintf(outport_name, "%s_size%d[%d]->out", + cur_interc->spice_model->prefix, fan_in, testbench_mux_cnt); + + if (TRUE == run_testbench_load_extraction) { /* Additional switch, default on! */ + fprint_spice_testbench_pb_graph_pin_inv_loads_rec(fp, &testbench_load_cnt, + grid_x, grid_y, + des_pb_graph_pin, des_pb, + outport_name, TRUE, + LL_rr_node_indices); + } + + fprint_spice_mux_testbench_pb_mux_meas(fp, meas_tag); + + /* Update the counter */ + testbench_mux_cnt++; + + /* Free */ + my_free(sram_bits); + my_free(input_init_value); + my_free(input_density); + my_free(input_probability); + my_free(outport_name); + + return; +} + +static +void fprint_spice_mux_testbench_pb_graph_node_pin_interc(FILE* fp, + enum e_pin2pin_interc_type pin2pin_interc_type, + t_pb_graph_pin* des_pb_graph_pin, + t_mode* cur_mode, + int select_path_id, + int grid_x, int grid_y, + t_ivec*** LL_rr_node_indices) { + int fan_in; + int iedge; + t_interconnect* cur_interc = NULL; + enum e_interconnect spice_interc_type; + + /* A valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); + exit(1); + } + + /* 1. identify pin interconnection type, + * 2. Identify the number of fan-in (Consider interconnection edges of only selected mode) + * 3. Select and print the SPICE netlist + */ + fan_in = 0; + cur_interc = NULL; + /* Search the input edges only, stats on the size of MUX we may need (fan-in) */ + for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { + /* 1. First, we should make sure this interconnect is in the selected mode!!!*/ + if (cur_mode == des_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode) { + /* Check this edge*/ + check_pb_graph_edge(*(des_pb_graph_pin->input_edges[iedge])); + /* Record the interconnection*/ + if (NULL == cur_interc) { + cur_interc = des_pb_graph_pin->input_edges[iedge]->interconnect; + } else { /* Make sure the interconnections for this pin is the same!*/ + assert(cur_interc == des_pb_graph_pin->input_edges[iedge]->interconnect); + } + /* Search the input_pins of input_edges only*/ + fan_in += des_pb_graph_pin->input_edges[iedge]->num_input_pins; + } + } + if (NULL == cur_interc) { + /* No interconnection matched */ + return; + } + /* Initialize the interconnection type that will be implemented in SPICE netlist*/ + switch (cur_interc->type) { + case DIRECT_INTERC: + assert(1 == fan_in); + spice_interc_type = DIRECT_INTERC; + break; + case COMPLETE_INTERC: + if (1 == fan_in) { + spice_interc_type = DIRECT_INTERC; + } else { + assert((2 == fan_in)||(2 < fan_in)); + spice_interc_type = MUX_INTERC; + } + break; + case MUX_INTERC: + assert((2 == fan_in)||(2 < fan_in)); + spice_interc_type = MUX_INTERC; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid interconnection type for %s (Arch[LINE%d])!\n", + __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); + exit(1); + } + + /* Print all the multiplexers at current level */ + switch (spice_interc_type) { + case DIRECT_INTERC: + break; + case MUX_INTERC: + assert(SPICE_MODEL_MUX == cur_interc->spice_model->type); + fprint_spice_mux_testbench_pb_graph_node_pin_mux(fp, cur_mode, des_pb_graph_pin, + cur_interc, fan_in, + select_path_id, + grid_x, grid_y, + LL_rr_node_indices); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid interconnection type!\n", + __FILE__, __LINE__); + exit(1); + } + + return; +} + + +static +void fprint_spice_mux_testbench_pb_pin_interc(FILE* fp, + t_rr_node* pb_rr_graph, + t_pb* des_pb, + enum e_pin2pin_interc_type pin2pin_interc_type, + t_pb_graph_pin* des_pb_graph_pin, + t_mode* cur_mode, + int select_path_id, + int grid_x, int grid_y, + t_ivec*** LL_rr_node_indices) { + int fan_in; + int iedge; + t_interconnect* cur_interc = NULL; + enum e_interconnect spice_interc_type; + + /* A valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); + exit(1); + } + + /* 1. identify pin interconnection type, + * 2. Identify the number of fan-in (Consider interconnection edges of only selected mode) + * 3. Select and print the SPICE netlist + */ + fan_in = 0; + cur_interc = NULL; + /* Search the input edges only, stats on the size of MUX we may need (fan-in) */ + for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { + /* 1. First, we should make sure this interconnect is in the selected mode!!!*/ + if (cur_mode == des_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode) { + /* Check this edge*/ + check_pb_graph_edge(*(des_pb_graph_pin->input_edges[iedge])); + /* Record the interconnection*/ + if (NULL == cur_interc) { + cur_interc = des_pb_graph_pin->input_edges[iedge]->interconnect; + } else { /* Make sure the interconnections for this pin is the same!*/ + assert(cur_interc == des_pb_graph_pin->input_edges[iedge]->interconnect); + } + /* Search the input_pins of input_edges only*/ + fan_in += des_pb_graph_pin->input_edges[iedge]->num_input_pins; + } + } + if (NULL == cur_interc) { + /* No interconnection matched */ + return; + } + /* Initialize the interconnection type that will be implemented in SPICE netlist*/ + switch (cur_interc->type) { + case DIRECT_INTERC: + assert(1 == fan_in); + spice_interc_type = DIRECT_INTERC; + break; + case COMPLETE_INTERC: + if (1 == fan_in) { + spice_interc_type = DIRECT_INTERC; + } else { + assert((2 == fan_in)||(2 < fan_in)); + spice_interc_type = MUX_INTERC; + } + break; + case MUX_INTERC: + assert((2 == fan_in)||(2 < fan_in)); + spice_interc_type = MUX_INTERC; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid interconnection type for %s (Arch[LINE%d])!\n", + __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); + exit(1); + } + + /* Print all the multiplexers at current level */ + switch (spice_interc_type) { + case DIRECT_INTERC: + break; + case MUX_INTERC: + assert(SPICE_MODEL_MUX == cur_interc->spice_model->type); + fprint_spice_mux_testbench_pb_pin_mux(fp, + pb_rr_graph, des_pb, + cur_mode, des_pb_graph_pin, + cur_interc, fan_in, select_path_id, + grid_x, grid_y, + LL_rr_node_indices); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid interconnection type!\n", + __FILE__, __LINE__); + exit(1); + } + + return; +} + +/* For each pb, we search the input pins and output pins for local interconnections */ +static +void fprint_spice_mux_testbench_pb_graph_node_interc(FILE* fp, + t_pb_graph_node* cur_pb_graph_node, + int grid_x, int grid_y, + t_ivec*** LL_rr_node_indices) { + int iport, ipin; + int ipb, jpb; + t_pb_type* cur_pb_type = NULL; + t_mode* cur_mode = NULL; + t_pb_graph_node* child_pb_graph_node = NULL; + int select_mode_index = -1; + + int path_id = -1; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + assert(NULL != cur_pb_graph_node); + cur_pb_type = cur_pb_graph_node->pb_type; + assert(NULL != cur_pb_type); + select_mode_index = find_pb_type_idle_mode_index(*(cur_pb_type)); + cur_mode = &(cur_pb_type->modes[select_mode_index]); + assert(NULL != cur_mode); + + /* We check output_pins of cur_pb_graph_node and its the input_edges + * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node + * child_pb_graph_node.output_pins -----------------> cur_pb_graph_node.outpins + * /|\ + * | + * input_pins, edges, output_pins + */ + for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) { + for (ipin = 0; ipin < cur_pb_graph_node->num_output_pins[iport]; ipin++) { + path_id = 0; + fprint_spice_mux_testbench_pb_graph_node_pin_interc(fp, + OUTPUT2OUTPUT_INTERC, + &(cur_pb_graph_node->output_pins[iport][ipin]), + cur_mode, + path_id, + grid_x, grid_y, + LL_rr_node_indices); + } + } + + /* We check input_pins of child_pb_graph_node and its the input_edges + * Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node + * cur_pb_graph_node.input_pins -----------------> child_pb_graph_node.input_pins + * /|\ + * | + * input_pins, edges, output_pins + */ + for (ipb = 0; ipb < cur_pb_type->modes[select_mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb_type->modes[select_mode_index].pb_type_children[ipb].num_pb; jpb++) { + child_pb_graph_node = &(cur_pb_graph_node->child_pb_graph_nodes[select_mode_index][ipb][jpb]); + /* For each child_pb_graph_node input pins*/ + for (iport = 0; iport < child_pb_graph_node->num_input_ports; iport++) { + for (ipin = 0; ipin < child_pb_graph_node->num_input_pins[iport]; ipin++) { + path_id = 0; + /* Write the interconnection*/ + fprint_spice_mux_testbench_pb_graph_node_pin_interc(fp, + INPUT2INPUT_INTERC, + &(child_pb_graph_node->input_pins[iport][ipin]), + cur_mode, + path_id, + grid_x, grid_y, + LL_rr_node_indices); + } + } + /* TODO: for clock pins, we should do the same work */ + for (iport = 0; iport < child_pb_graph_node->num_clock_ports; iport++) { + for (ipin = 0; ipin < child_pb_graph_node->num_clock_pins[iport]; ipin++) { + path_id = 0; + /* Write the interconnection*/ + fprint_spice_mux_testbench_pb_graph_node_pin_interc(fp, + INPUT2INPUT_INTERC, + &(child_pb_graph_node->clock_pins[iport][ipin]), + cur_mode, + path_id, + grid_x, grid_y, + LL_rr_node_indices); + } + } + } + } + + return; +} + +void fprint_spice_mux_testbench_idle_pb_graph_node_muxes_rec(FILE* fp, + t_pb_graph_node* cur_pb_graph_node, + int grid_x, int grid_y, + t_ivec*** LL_rr_node_indices) { + int ipb, jpb; + int mode_index; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert(NULL != cur_pb_graph_node); + + /* If we touch the leaf, there is no need print interc*/ + if (NULL == cur_pb_graph_node->pb_type->spice_model) { + /* Print MUX interc at current-level pb*/ + fprint_spice_mux_testbench_pb_graph_node_interc(fp, cur_pb_graph_node, + grid_x, grid_y, + LL_rr_node_indices); + } else { + return; + } + + /* Go recursively ... */ + mode_index = find_pb_type_idle_mode_index(*(cur_pb_graph_node->pb_type)); + for (ipb = 0; ipb < cur_pb_graph_node->pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb_graph_node->pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Print idle muxes */ + fprint_spice_mux_testbench_idle_pb_graph_node_muxes_rec(fp, + &(cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), + grid_x, grid_y, + LL_rr_node_indices); + } + } + + return; +} + +/* For each pb, we search the input pins and output pins for local interconnections */ +static +void fprint_spice_mux_testbench_pb_interc(FILE* fp, + t_pb* cur_pb, + int grid_x, int grid_y, + t_ivec*** LL_rr_node_indices) { + int iport, ipin; + int ipb, jpb; + t_pb_graph_node* cur_pb_graph_node = NULL; + t_pb_type* cur_pb_type = NULL; + t_mode* cur_mode = NULL; + t_pb_graph_node* child_pb_graph_node = NULL; + t_pb* child_pb = NULL; + int select_mode_index = -1; + + int node_index = -1; + int prev_node = -1; + int prev_edge = -1; + int path_id = -1; + t_rr_node* pb_rr_nodes = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + assert(NULL != cur_pb); + cur_pb_graph_node = cur_pb->pb_graph_node; + assert(NULL != cur_pb_graph_node); + cur_pb_type = cur_pb_graph_node->pb_type; + assert(NULL != cur_pb_type); + select_mode_index = cur_pb->mode; + cur_mode = &(cur_pb_type->modes[select_mode_index]); + assert(NULL != cur_mode); + + /* We check output_pins of cur_pb_graph_node and its the input_edges + * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node + * child_pb_graph_node.output_pins -----------------> cur_pb_graph_node.outpins + * /|\ + * | + * input_pins, edges, output_pins + */ + for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) { + for (ipin = 0; ipin < cur_pb_graph_node->num_output_pins[iport]; ipin++) { + /* Get the selected edge of current pin*/ + assert(NULL != cur_pb); + pb_rr_nodes = cur_pb->rr_graph; + node_index = cur_pb_graph_node->output_pins[iport][ipin].pin_count_in_cluster; + /* Bypass unmapped interc */ + /* + if (OPEN == pb_rr_nodes[node_index].net_num) { + continue; + } + */ + prev_node = pb_rr_nodes[node_index].prev_node; + /* prev_edge is the index of edge of prev_node !!! */ + prev_edge = pb_rr_nodes[node_index].prev_edge; + /* Make sure this pb_rr_node is not OPEN and is not a primitive output*/ + if (OPEN == prev_node) { + path_id = 0; + /* Determine the child_pb */ + } else { + /* Find the path_id */ + path_id = find_path_id_between_pb_rr_nodes(pb_rr_nodes, prev_node, node_index); + assert(-1 != path_id); + } + fprint_spice_mux_testbench_pb_pin_interc(fp, pb_rr_nodes ,cur_pb, /* TODO: find out the child_pb*/ + OUTPUT2OUTPUT_INTERC, + &(cur_pb_graph_node->output_pins[iport][ipin]), + cur_mode, + path_id, + grid_x, grid_y, + LL_rr_node_indices); + } + } + + /* We check input_pins of child_pb_graph_node and its the input_edges + * Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node + * cur_pb_graph_node.input_pins -----------------> child_pb_graph_node.input_pins + * /|\ + * | + * input_pins, edges, output_pins + */ + for (ipb = 0; ipb < cur_pb_type->modes[select_mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb_type->modes[select_mode_index].pb_type_children[ipb].num_pb; jpb++) { + child_pb_graph_node = &(cur_pb_graph_node->child_pb_graph_nodes[select_mode_index][ipb][jpb]); + child_pb = &(cur_pb->child_pbs[ipb][jpb]); + /* Check if child_pb is empty */ + if (NULL == child_pb->name) { + //continue; /* by pass*/ + /* For each child_pb_graph_node input pins*/ + for (iport = 0; iport < child_pb_graph_node->num_input_ports; iport++) { + for (ipin = 0; ipin < child_pb_graph_node->num_input_pins[iport]; ipin++) { + path_id = 0; + /* Write the interconnection*/ + fprint_spice_mux_testbench_pb_graph_node_pin_interc(fp, + INPUT2INPUT_INTERC, + &(child_pb_graph_node->input_pins[iport][ipin]), + cur_mode, + path_id, + grid_x, grid_y, + LL_rr_node_indices); + } + } + /* TODO: for clock pins, we should do the same work */ + for (iport = 0; iport < child_pb_graph_node->num_clock_ports; iport++) { + for (ipin = 0; ipin < child_pb_graph_node->num_clock_pins[iport]; ipin++) { + path_id = 0; + /* Write the interconnection*/ + fprint_spice_mux_testbench_pb_graph_node_pin_interc(fp, + INPUT2INPUT_INTERC, + &(child_pb_graph_node->clock_pins[iport][ipin]), + cur_mode, + path_id, + grid_x, grid_y, + LL_rr_node_indices); + } + } + continue; + } + /* Get pb_rr_graph of current pb*/ + pb_rr_nodes = child_pb->rr_graph; + /* For each child_pb_graph_node input pins*/ + for (iport = 0; iport < child_pb_graph_node->num_input_ports; iport++) { + for (ipin = 0; ipin < child_pb_graph_node->num_input_pins[iport]; ipin++) { + /* Get the index of the edge that are selected to pass signal*/ + node_index = child_pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster; + prev_node = pb_rr_nodes[node_index].prev_node; + prev_edge = pb_rr_nodes[node_index].prev_edge; + /* Bypass unmapped interc */ + /* + if (OPEN == pb_rr_nodes[node_index].net_num) { + continue; + } + */ + /* Make sure this pb_rr_node is not OPEN and is not a primitive output*/ + if (OPEN == prev_node) { + path_id = 0; + //break; /* TODO: if there exist parasitic input waveforms, we should print the interc */ + } else { + /* Find the path_id */ + path_id = find_path_id_between_pb_rr_nodes(pb_rr_nodes, prev_node, node_index); + assert(-1 != path_id); + } + /* Write the interconnection*/ + fprint_spice_mux_testbench_pb_pin_interc(fp, pb_rr_nodes, child_pb, + INPUT2INPUT_INTERC, + &(child_pb_graph_node->input_pins[iport][ipin]), + cur_mode, + path_id, + grid_x, grid_y, + LL_rr_node_indices); + } + } + /* TODO: for clock pins, we should do the same work */ + for (iport = 0; iport < child_pb_graph_node->num_clock_ports; iport++) { + for (ipin = 0; ipin < child_pb_graph_node->num_clock_pins[iport]; ipin++) { + /* Get the index of the edge that are selected to pass signal*/ + node_index = child_pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster; + prev_node = pb_rr_nodes[node_index].prev_node; + prev_edge = pb_rr_nodes[node_index].prev_edge; + /* Bypass unmapped interc */ + /* + if (OPEN == pb_rr_nodes[node_index].net_num) { + continue; + } + */ + /* Make sure this pb_rr_node is not OPEN and is not a primitive output*/ + if (OPEN == prev_node) { + path_id = 0; + //break; /* TODO: if there exist parasitic input waveforms, we should print the interc */ + } else { + /* Find the path_id */ + path_id = find_path_id_between_pb_rr_nodes(pb_rr_nodes, prev_node, node_index); + assert(-1 != path_id); + } + /* Write the interconnection*/ + fprint_spice_mux_testbench_pb_pin_interc(fp, pb_rr_nodes, child_pb, + INPUT2INPUT_INTERC, + &(child_pb_graph_node->clock_pins[iport][ipin]), + cur_mode, + path_id, + grid_x, grid_y, + LL_rr_node_indices); + } + } + } + } + + return; +} + +static +void fprint_spice_mux_testbench_pb_muxes_rec(FILE* fp, + t_pb* cur_pb, + int grid_x, int grid_y, + t_ivec*** LL_rr_node_indices) { + int ipb, jpb; + int mode_index; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert(NULL != cur_pb); + + /* If we touch the leaf, there is no need print interc*/ + if (OPEN == cur_pb->logical_block) { + /* Print MUX interc at current-level pb*/ + fprint_spice_mux_testbench_pb_interc(fp, cur_pb, + grid_x, grid_y, + LL_rr_node_indices); + } else { + return; + } + + /* Go recursively ... */ + mode_index = cur_pb->mode; + for (ipb = 0; ipb < cur_pb->pb_graph_node->pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb->pb_graph_node->pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Refer to pack/output_clustering.c [LINE 392] */ + if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { + fprint_spice_mux_testbench_pb_muxes_rec(fp, &(cur_pb->child_pbs[ipb][jpb]), grid_x, grid_y, LL_rr_node_indices); + } else { + /* Print idle muxes */ + fprint_spice_mux_testbench_idle_pb_graph_node_muxes_rec(fp, + cur_pb->child_pbs[ipb][jpb].pb_graph_node, + grid_x, grid_y, + LL_rr_node_indices); + } + } + } + + return; +} + + +static +void fprint_spice_mux_testbench_cb_one_mux(FILE* fp, + t_cb cur_cb_info, + t_rr_node* src_rr_node, + t_ivec*** LL_rr_node_indices) { + int mux_size, cb_x, cb_y; + int inode, path_id, switch_index; + t_rr_node** drive_rr_nodes = NULL; + t_spice_model* mux_spice_model = NULL; + int* mux_sram_bits = NULL; + float* input_density = NULL; + float* input_probability = NULL; + int* input_init_value = NULL; + char* meas_tag = NULL; + char* outport_name = NULL; + float average_cb_mux_input_density = 0.; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert((!(0 > cur_cb_info.x))&&(!(cur_cb_info.x > (nx + 1)))); + assert((!(0 > cur_cb_info.y))&&(!(cur_cb_info.y > (ny + 1)))); + + cb_x = cur_cb_info.x; + cb_y = cur_cb_info.y; + + assert(IPIN == src_rr_node->type); + + /* Find drive_rr_nodes*/ + mux_size = src_rr_node->num_drive_rr_nodes; + assert(mux_size == src_rr_node->fan_in); + drive_rr_nodes = src_rr_node->drive_rr_nodes; + + /* Find path_id */ + path_id = -1; + for (inode = 0; inode < mux_size; inode++) { + if (drive_rr_nodes[inode] == &(rr_node[src_rr_node->prev_node])) { + path_id = inode; + break; + } + } + assert((-1 != path_id)&&(path_id < mux_size)); + + switch_index = src_rr_node->drive_switches[path_id]; + + mux_spice_model = switch_inf[switch_index].spice_model; + + /* Check : + * MUX should have at least 2 fan_in + */ + assert((2 == mux_size)||(2 < mux_size)); + /* 2. spice_model is a wire */ + assert(SPICE_MODEL_MUX == mux_spice_model->type); + + input_density = (float*)my_malloc(sizeof(float)*mux_size); + input_probability = (float*)my_malloc(sizeof(float)*mux_size); + input_init_value = (int*)my_malloc(sizeof(int)*mux_size); + for (inode = 0; inode < mux_size; inode++) { + /* Find activity information */ + input_density[inode] = get_rr_node_net_density(*(drive_rr_nodes[inode])); + input_probability[inode] = get_rr_node_net_probability(*(drive_rr_nodes[inode])); + input_init_value[inode] = get_rr_node_net_init_value(*(drive_rr_nodes[inode])); + average_cb_mux_input_density += input_density[inode]; + } + average_cb_mux_input_density = average_cb_mux_input_density/mux_size; + total_cb_mux_input_density += average_cb_mux_input_density; + + /* Build meas_tag: cb_mux[cb_x][cb_y]_rrnode[node]*/ + meas_tag = (char*)my_malloc(sizeof(char)*(7 + strlen(my_itoa(cb_x)) + 2 + + strlen(my_itoa(cb_y)) + 9 + + strlen(my_itoa(src_rr_node-rr_node)) + 2)); /* Add '0'*/ + sprintf(meas_tag, "cb_mux[%d][%d]_rrnode[%ld]", cb_x, cb_y, src_rr_node-rr_node); + /* Print the main part of a single MUX testbench */ + fprint_spice_mux_testbench_one_mux(fp, meas_tag, + mux_spice_model, src_rr_node->fan_in, + input_init_value, input_density, + input_probability, path_id); + + /* Generate loads */ + outport_name = (char*)my_malloc(sizeof(char)*( strlen(mux_spice_model->prefix) + 5 + + strlen(my_itoa(mux_size)) + 1 + strlen(my_itoa(testbench_mux_cnt)) + + 7 )); + sprintf(outport_name, "%s_size%d[%d]->out", + mux_spice_model->prefix, + mux_size, + testbench_mux_cnt); + + if (TRUE == run_testbench_load_extraction) { /* Additional switch, default on! */ + fprint_spice_testbench_one_cb_mux_loads(fp, &testbench_load_cnt, src_rr_node, + outport_name, LL_rr_node_indices); + } + + fprint_spice_mux_testbench_cb_mux_meas(fp, meas_tag); + /* Update the counter */ + testbench_mux_cnt++; + + /* Free */ + my_free(mux_sram_bits); + my_free(input_init_value); + my_free(input_density); + my_free(input_probability); + + return; +} + +void fprint_spice_mux_testbench_cb_interc(FILE* fp, + t_cb cur_cb_info, + t_rr_node* src_rr_node, + t_ivec*** LL_rr_node_indices) { + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > cur_cb_info.x))&&(!(cur_cb_info.x > (nx + 1)))); + assert((!(0 > cur_cb_info.y))&&(!(cur_cb_info.y > (ny + 1)))); + + assert(NULL != src_rr_node); + + /* Skip non-mapped CB MUX */ + if (OPEN == src_rr_node->net_num) { + //return; + } + + assert((0 < src_rr_node->fan_in)||(0 == src_rr_node->fan_in)); + if (1 == src_rr_node->fan_in) { + /* By-pass a direct connection*/ + return; + } else if ((2 < src_rr_node->fan_in)||(2 == src_rr_node->fan_in)) { + /* Print a MUX */ + fprint_spice_mux_testbench_cb_one_mux(fp, + cur_cb_info, + src_rr_node, + LL_rr_node_indices); + } + + return; +} + + +/* Assume each connection box has a regional power-on/off switch */ +static +int fprint_spice_mux_testbench_call_one_grid_cb_muxes(FILE* fp, + t_cb cur_cb_info, + t_ivec*** LL_rr_node_indices) { + int inode, side; + int side_cnt = 0; + int used = 0; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert((!(0 > cur_cb_info.x))&&(!(cur_cb_info.x > (nx + 1)))); + assert((!(0 > cur_cb_info.y))&&(!(cur_cb_info.y > (ny + 1)))); + + side_cnt = 0; + used = 0; + /* Print the ports of grids*/ + /* only check ipin_rr_nodes of cur_cb_info */ + for (side = 0; side < cur_cb_info.num_sides; side++) { + /* Bypass side with zero IPINs*/ + if (0 == cur_cb_info.num_ipin_rr_nodes[side]) { + continue; + } + side_cnt++; + assert(0 < cur_cb_info.num_ipin_rr_nodes[side]); + assert(NULL != cur_cb_info.ipin_rr_node[side]); + for (inode = 0; inode < cur_cb_info.num_ipin_rr_nodes[side]; inode++) { + /* Print multiplexers */ + /* Check if there is at least one rr_node with a net_name*/ + if (OPEN != cur_cb_info.ipin_rr_node[side][inode]->net_num) { + used = 1; + } + fprint_spice_mux_testbench_cb_interc(fp, cur_cb_info, + cur_cb_info.ipin_rr_node[side][inode], + LL_rr_node_indices); + } + } + /* Make sure only 2 sides of IPINs are printed */ + assert((1 == side_cnt)||(2 == side_cnt)); + + /* Free */ + + return used; +} + +static +int fprint_spice_mux_testbench_sb_one_mux(FILE* fp, + int switch_box_x, int switch_box_y, + int chan_side, + t_rr_node* src_rr_node) { + int inode, switch_index, mux_size; + t_spice_model* mux_spice_model = NULL; + float* input_density = NULL; + float* input_probability = NULL; + int* input_init_value = NULL; + int path_id = -1; + char* meas_tag = NULL; + int num_drive_rr_nodes = 0; + t_rr_node** drive_rr_nodes = NULL; + char* outport_name = NULL; + char* rr_node_outport_name = NULL; + int used = 0; + + float average_sb_mux_input_density = 0.; + + /* Check */ + assert((!(0 > switch_box_x))&&(!(switch_box_x > (nx + 1)))); + assert((!(0 > switch_box_y))&&(!(switch_box_y > (ny + 1)))); + + if (NULL == src_rr_node) { + return 0; + } + + /* ignore idle sb mux + if (OPEN == src_rr_node->net_num) { + return used; + } + */ + + /* Determine if the interc lies inside a channel wire, that is interc between segments */ + if (1 == is_sb_interc_between_segments(switch_box_x, switch_box_y, src_rr_node, chan_side)) { + num_drive_rr_nodes = 0; + drive_rr_nodes = NULL; + } else { + num_drive_rr_nodes = src_rr_node->num_drive_rr_nodes; + drive_rr_nodes = src_rr_node->drive_rr_nodes; + switch_index = src_rr_node->drive_switches[0]; + } + + /* Print MUX only when fan-in >= 2 */ + if (2 > num_drive_rr_nodes) { + return used; + } + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Find mux_spice_model, mux_size */ + mux_size = num_drive_rr_nodes; + + mux_spice_model = switch_inf[switch_index].spice_model; + assert(NULL != mux_spice_model); + assert(SPICE_MODEL_MUX == mux_spice_model->type); + + /* input_density, input_probability */ + input_density = (float*)my_malloc(sizeof(float)*mux_size); + input_probability = (float*)my_malloc(sizeof(float)*mux_size); + input_init_value = (int*)my_malloc(sizeof(int)*mux_size); + for (inode = 0; inode < mux_size; inode++) { + input_density[inode] = get_rr_node_net_density(*(drive_rr_nodes[inode])); + input_probability[inode] = get_rr_node_net_probability(*(drive_rr_nodes[inode])); + input_init_value[inode] = get_rr_node_net_init_value(*(drive_rr_nodes[inode])); + average_sb_mux_input_density += input_density[inode]; + } + average_sb_mux_input_density = average_sb_mux_input_density/mux_size; + total_sb_mux_input_density += average_sb_mux_input_density; + + /* Find path_id */ + path_id = -1; + for (inode = 0; inode < mux_size; inode++) { + if (drive_rr_nodes[inode] == &(rr_node[src_rr_node->prev_node])) { + path_id = inode; + break; + } + } + assert((-1 != path_id)&&(path_id < mux_size)); + + /* Build meas_tag: sb_mux[sb_x][sb_y]_rrnode[node]*/ + meas_tag = (char*)my_malloc(sizeof(char)*(7 + strlen(my_itoa(switch_box_x)) + 2 + + strlen(my_itoa(switch_box_y)) + 9 + + strlen(my_itoa(src_rr_node-rr_node)) + 2)); /* Add '0'*/ + sprintf(meas_tag, "sb_mux[%d][%d]_rrnode[%ld]", switch_box_x, switch_box_y, src_rr_node-rr_node); + /* Print MUX */ + fprint_spice_mux_testbench_one_mux(fp, meas_tag, + mux_spice_model, mux_size, + input_init_value, input_density, + input_probability, path_id); + + /* Print a channel wire !*/ + outport_name = (char*)my_malloc(sizeof(char)*( strlen(mux_spice_model->prefix) + + 5 + strlen(my_itoa(mux_size)) + 1 + + strlen(my_itoa(testbench_mux_cnt)) + + 6 + 1 )); + sprintf(outport_name, "%s_size%d[%d]->out", mux_spice_model->prefix, mux_size, testbench_mux_cnt); + + if (TRUE == run_testbench_load_extraction) { /* Additional switch, default on! */ + fprintf(fp, "***** Load for rr_node[%d] *****\n", src_rr_node - rr_node); + rr_node_outport_name = fprint_spice_testbench_rr_node_load_version(fp, + &testbench_load_cnt, + num_segments, + segments, + 0, /* load size */ + (*src_rr_node), + outport_name); + } + + fprint_spice_mux_testbench_sb_mux_meas(fp, meas_tag); + + /* Update the counter */ + testbench_mux_cnt++; + + /* Free */ + my_free(input_init_value); + my_free(input_density); + my_free(input_probability); + + return 1; +} + + +static +int fprint_spice_mux_testbench_call_one_grid_sb_muxes(FILE* fp, + t_sb cur_sb_info, + t_ivec*** LL_rr_node_indices) { + int itrack, inode, side; + int used = 0; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert((!(0 > cur_sb_info.x))&&(!(cur_sb_info.x > (nx + 1)))); + assert((!(0 > cur_sb_info.y))&&(!(cur_sb_info.y > (ny + 1)))); + + + /* print all the rr_nodes in the switch boxes if there is at least one rr_node with a net_num */ + used = 0; + for (side = 0; side < cur_sb_info.num_sides; side++) { + for (itrack = 0; itrack < cur_sb_info.chan_width[side]; itrack++) { + switch (cur_sb_info.chan_rr_node_direction[side][itrack]) { + case OUT_PORT: + fprint_spice_mux_testbench_sb_one_mux(fp, + cur_sb_info.x, + cur_sb_info.y, + side, + cur_sb_info.chan_rr_node[side][itrack]); + used++; + break; + case IN_PORT: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of port sb[%d][%d] Channel node[%d] track[%d]!\n", + __FILE__, __LINE__, cur_sb_info.x, cur_sb_info.y, side, itrack); + exit(1); + } + } + } + + /* Free */ + if (0 < used) { + used = 1; + } + + return used; +} + +static +int fprint_spice_mux_testbench_call_one_grid_pb_muxes(FILE* fp, int ix, int iy, + t_ivec*** LL_rr_node_indices) { + int iblk; + int used = 0; + + /* A valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); + exit(1); + } + /* Print all the grid */ + if ((NULL == grid[ix][iy].type)||(0 != grid[ix][iy].offset)) { + return used; + } + /* Used blocks */ + for (iblk = 0; iblk < grid[ix][iy].usage; iblk++) { + /* Only for mapped block */ + assert(NULL != block[grid[ix][iy].blocks[iblk]].pb); + /* Mark the temporary net_num for the type pins*/ + mark_one_pb_parasitic_nets(block[grid[ix][iy].blocks[iblk]].pb); + fprint_spice_mux_testbench_pb_muxes_rec(fp, + block[grid[ix][iy].blocks[iblk]].pb, + ix, iy, + LL_rr_node_indices); + used = 1; + } + /* By pass Unused blocks */ + for (iblk = grid[ix][iy].usage; iblk < grid[ix][iy].type->capacity; iblk++) { + /* Mark the temporary net_num for the type pins*/ + mark_grid_type_pb_graph_node_pins_temp_net_num(ix, iy); + fprint_spice_mux_testbench_idle_pb_graph_node_muxes_rec(fp, + grid[ix][iy].type->pb_graph_head, + ix, iy, + LL_rr_node_indices); + } + + return used; +} + +static +void fprint_spice_mux_testbench_stimulations(FILE* fp, + int num_clocks) { + /* Voltage sources of Multiplexers are already generated during printing the netlist + * We just need global stimulations Here. + */ + + /* Give global vdd, gnd, voltage sources*/ + /* A valid file handler */ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* Print generic stimuli */ + fprint_spice_testbench_generic_global_ports_stimuli(fp, num_clocks); + + /* Generate global ports stimuli */ + fprint_spice_testbench_global_ports_stimuli(fp, global_ports_head); + + /* SRAM ports */ + fprintf(fp, "***** Global Inputs for SRAMs *****\n"); + fprint_spice_testbench_global_sram_inport_stimuli(fp, sram_spice_orgz_info); + + fprintf(fp, "***** Global VDD for SRAMs *****\n"); + fprint_spice_testbench_global_vdd_port_stimuli(fp, + spice_tb_global_vdd_sram_port_name, + "vsp"); + + fprintf(fp, "***** Global VDD for load inverters *****\n"); + fprint_spice_testbench_global_vdd_port_stimuli(fp, + spice_tb_global_vdd_load_port_name, + "vsp"); + + return; +} + +static +void fprint_spice_mux_testbench_measurements(FILE* fp, + enum e_spice_mux_tb_type mux_tb_type, + t_spice spice) { + int num_clock_cycle = max_sim_num_clock_cycles; + + /* + int i; + t_llist* head = NULL; + t_spice_mux_model* spice_mux_model = NULL; + */ + + /* Give global vdd, gnd, voltage sources*/ + /* A valid file handler */ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + fprint_spice_netlist_transient_setting(fp, spice, num_clock_cycle, FALSE); + fprint_spice_netlist_generic_measurements(fp, spice.spice_params.mc_params, spice.num_spice_model, spice.spice_models); + + /* Measure the leakage and dynamic power of SRAMs*/ + fprintf(fp, ".meas tran total_leakage_srams avg p(Vgvdd_sram) from=0 to=\'clock_period\'\n"); + fprintf(fp, ".meas tran total_dynamic_srams avg p(Vgvdd_sram) from=\'clock_period\' to=\'%d*clock_period\'\n", num_clock_cycle); + fprintf(fp, ".meas tran total_energy_per_cycle_srams param=\'total_dynamic_srams*clock_period\'\n"); + + /* Measure the total leakage and dynamic power */ + fprintf(fp, ".meas tran total_leakage_power_mux[0to%d] \n", testbench_mux_cnt - 1); + fprintf(fp, "+ param=\'sum_leakage_power_mux[0to%d]\'\n", testbench_mux_cnt-1); + fprintf(fp, ".meas tran total_energy_per_cycle_mux[0to%d] \n", testbench_mux_cnt - 1); + fprintf(fp, "+ param=\'sum_energy_per_cycle_mux[0to%d]\'\n", testbench_mux_cnt-1); + + switch (mux_tb_type) { + case SPICE_PB_MUX_TB: + /* pb_muxes */ + fprintf(fp, ".meas tran total_leakage_power_pb_mux \n"); + fprintf(fp, "+ param=\'sum_leakage_power_pb_mux[0to%d]\'\n", testbench_pb_mux_cnt-1); + fprintf(fp, ".meas tran total_energy_per_cycle_pb_mux \n"); + fprintf(fp, "+ param=\'sum_energy_per_cycle_pb_mux[0to%d]\'\n", testbench_pb_mux_cnt-1); + break; + case SPICE_CB_MUX_TB: + /* cb_muxes */ + fprintf(fp, ".meas tran total_leakage_power_cb_mux \n"); + fprintf(fp, "+ param=\'sum_leakage_power_cb_mux[0to%d]\'\n", testbench_cb_mux_cnt-1); + fprintf(fp, ".meas tran total_energy_per_cycle_cb_mux \n"); + fprintf(fp, "+ param=\'sum_energy_per_cycle_cb_mux[0to%d]\'\n", testbench_cb_mux_cnt-1); + break; + case SPICE_SB_MUX_TB: + /* sb_muxes */ + fprintf(fp, ".meas tran total_leakage_power_sb_mux \n"); + fprintf(fp, "+ param=\'sum_leakage_power_sb_mux[0to%d]\'\n", testbench_sb_mux_cnt-1); + fprintf(fp, ".meas tran total_energy_per_cycle_sb_mux \n"); + fprintf(fp, "+ param=\'sum_energy_per_cycle_sb_mux[0to%d]\'\n", testbench_sb_mux_cnt-1); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d]) Invalid mux_tb_type!\n", __FILE__, __LINE__); + exit(1); + } + + return; +} + +/* Top-level function in this source file */ +int fprint_spice_one_mux_testbench(char* formatted_spice_dir, + char* circuit_name, + char* mux_testbench_name, + char* include_dir_path, + char* subckt_dir_path, + t_ivec*** LL_rr_node_indices, + int num_clocks, + t_arch arch, + int grid_x, int grid_y, t_rr_type cb_type, + enum e_spice_mux_tb_type mux_tb_type, + boolean leakage_only) { + FILE* fp = NULL; + char* formatted_subckt_dir_path = format_dir_path(subckt_dir_path); + char* title = my_strcat("FPGA SPICE Routing MUX Test Bench for Design: ", circuit_name); + char* mux_testbench_file_path = my_strcat(formatted_spice_dir, mux_testbench_name); + char* mux_tb_name = NULL; + int used = 0; + + switch (mux_tb_type) { + case SPICE_PB_MUX_TB: + mux_tb_name = "CLB MUX"; + break; + case SPICE_CB_MUX_TB: + mux_tb_name = "Connection Box MUX"; + break; + case SPICE_SB_MUX_TB: + mux_tb_name = "Switch Block MUX"; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d]) Invalid mux_tb_type!\n", __FILE__, __LINE__); + exit(1); + } + + /* Check if the path exists*/ + fp = fopen(mux_testbench_file_path,"w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create SPICE %s Test bench netlist %s!\n", + __FILE__, __LINE__, mux_tb_name, mux_testbench_file_path); + exit(1); + } + + /* + vpr_printf(TIO_MESSAGE_INFO, "Writing Grid[%d][%d] SPICE %s MUX Test Bench for %s...\n", + grid_x, grid_y, mux_tb_name, circuit_name); + */ + + /* Load global vars in this source file */ + num_segments = arch.num_segments; + segments = arch.Segments; + + /* Print the title */ + fprint_spice_head(fp, title); + my_free(title); + + /* print technology library and design parameters*/ + /*fprint_tech_lib(fp, arch.spice->tech_lib);*/ + + /* Include parameter header files */ + fprint_spice_include_param_headers(fp, include_dir_path); + + /* Include Key subckts */ + fprint_spice_include_key_subckts(fp, formatted_subckt_dir_path); + + /* Include user-defined sub-circuit netlist */ + init_include_user_defined_netlists(*(arch.spice)); + fprint_include_user_defined_netlists(fp, *(arch.spice)); + + /* Special subckts for Top-level SPICE netlist */ + /* + fprintf(fp, "****** Include subckt netlists: Look-Up Tables (LUTs) *****\n"); + temp_include_file_path = my_strcat(formatted_subckt_dir_path, luts_spice_file_name); + fprintf(fp, ".include %s\n", temp_include_file_path); + my_free(temp_include_file_path); + */ + + /* Print simulation temperature and other options for SPICE */ + fprint_spice_options(fp, arch.spice->spice_params); + + /* Global nodes: Vdd for SRAMs, Logic Blocks(Include IO), Switch Boxes, Connection Boxes */ + fprint_spice_mux_testbench_global_ports(fp, *(arch.spice)); + + /* Quote defined Logic blocks subckts (Grids) */ + init_spice_mux_testbench_globals(*(arch.spice)); + + switch (mux_tb_type) { + case SPICE_PB_MUX_TB: + total_pb_mux_input_density = 0.; + used = fprint_spice_mux_testbench_call_one_grid_pb_muxes(fp, grid_x, grid_y, LL_rr_node_indices); + total_pb_mux_input_density = total_pb_mux_input_density/testbench_pb_mux_cnt; + vpr_printf(TIO_MESSAGE_INFO,"Average density of PB MUX inputs is %.2g.\n", total_pb_mux_input_density); + /* Add stimulations */ + fprint_spice_mux_testbench_stimulations(fp, num_clocks); + /* Add measurements */ + fprint_spice_mux_testbench_measurements(fp, mux_tb_type, *(arch.spice)); + break; + case SPICE_CB_MUX_TB: + /* one cbx, one cby*/ + total_cb_mux_input_density = 0.; + switch (cb_type) { + case CHANX: + used = fprint_spice_mux_testbench_call_one_grid_cb_muxes(fp, cbx_info[grid_x][grid_y], LL_rr_node_indices); + break; + case CHANY: + used = fprint_spice_mux_testbench_call_one_grid_cb_muxes(fp, cby_info[grid_x][grid_y], LL_rr_node_indices); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d]) Invalid connection_box_type!\n", __FILE__, __LINE__); + exit(1); + } + total_cb_mux_input_density = total_cb_mux_input_density/testbench_cb_mux_cnt; + vpr_printf(TIO_MESSAGE_INFO,"Average density of CB MUX inputs is %.2g.\n", total_cb_mux_input_density); + /* Add stimulations */ + fprint_spice_mux_testbench_stimulations(fp, num_clocks); + /* Add measurements */ + fprint_spice_mux_testbench_measurements(fp, mux_tb_type, *(arch.spice)); + break; + case SPICE_SB_MUX_TB: + total_sb_mux_input_density = 0.; + used = fprint_spice_mux_testbench_call_one_grid_sb_muxes(fp, sb_info[grid_x][grid_y], LL_rr_node_indices); + total_sb_mux_input_density = total_sb_mux_input_density/testbench_sb_mux_cnt; + vpr_printf(TIO_MESSAGE_INFO,"Average density of SB MUX inputs is %.2g.\n", total_sb_mux_input_density); + /* Add stimulations */ + fprint_spice_mux_testbench_stimulations(fp, num_clocks); + /* Add measurements */ + fprint_spice_mux_testbench_measurements(fp, mux_tb_type, *(arch.spice)); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d]) Invalid mux_tb_type!\n", __FILE__, __LINE__); + exit(1); + } + + /* SPICE ends*/ + fprintf(fp, ".end\n"); + + /* Close the file*/ + fclose(fp); + + /* Free */ + //my_free(formatted_subckt_dir_path); + //my_free(mux_testbench_file_path); + //my_free(title); + free_muxes_llist(testbench_muxes_head); + + if (0 < testbench_mux_cnt) { + vpr_printf(TIO_MESSAGE_INFO, "Writing Grid[%d][%d] SPICE %s Test Bench for %s...\n", + grid_x, grid_y, mux_tb_name, circuit_name); + /* Push the testbench to the linked list */ + tb_head = add_one_spice_tb_info_to_llist(tb_head, mux_testbench_file_path, max_sim_num_clock_cycles); + used = 1; + } else { + /* Remove the file generated */ + my_remove_file(mux_testbench_file_path); + used = 0; + } + + return used; +} + +void spice_print_mux_testbench(char* formatted_spice_dir, + char* circuit_name, + char* include_dir_path, + char* subckt_dir_path, + t_ivec*** LL_rr_node_indices, + int num_clocks, + t_arch arch, + enum e_spice_mux_tb_type mux_tb_type, + boolean leakage_only) { + char* mux_testbench_name = NULL; + int ix, iy; + int cnt = 0; + int used = 0; + + /* Depend on the type of testbench, we generate the a list of testbenches */ + switch (mux_tb_type) { + case SPICE_PB_MUX_TB: + cnt = 0; + for (ix = 1; ix < (nx+1); ix++) { + for (iy = 1; iy < (ny+1); iy++) { + mux_testbench_name = (char*)my_malloc(sizeof(char)*( strlen(circuit_name) + + 5 + strlen(my_itoa(ix)) + 1 + + strlen(my_itoa(iy)) + 1 + + strlen(spice_pb_mux_testbench_postfix) + 1 )); + sprintf(mux_testbench_name, "%s_grid%d_%d%s", + circuit_name, ix, iy, spice_pb_mux_testbench_postfix); + used = fprint_spice_one_mux_testbench(formatted_spice_dir, circuit_name, mux_testbench_name, + include_dir_path, subckt_dir_path, LL_rr_node_indices, + num_clocks, arch, ix, iy, NUM_RR_TYPES, SPICE_PB_MUX_TB, + leakage_only); + if (1 == used) { + cnt += used; + } + /* free */ + my_free(mux_testbench_name); + } + } + /* Update the global counter */ + num_used_grid_mux_tb = cnt; + vpr_printf(TIO_MESSAGE_INFO,"No. of generated PB_MUX testbench = %d\n", num_used_grid_tb); + break; + case SPICE_CB_MUX_TB: + cnt = 0; + for (iy = 0; iy < (ny+1); iy++) { + for (ix = 1; ix < (nx+1); ix++) { + mux_testbench_name = (char*)my_malloc(sizeof(char)*( strlen(circuit_name) + + 4 + strlen(my_itoa(ix)) + 2 + strlen(my_itoa(iy)) + 1 + + strlen(spice_cb_mux_testbench_postfix) + 1 )); + sprintf(mux_testbench_name, "%s_cbx%d_%d%s", + circuit_name, ix, iy, spice_cb_mux_testbench_postfix); + used = fprint_spice_one_mux_testbench(formatted_spice_dir, circuit_name, mux_testbench_name, + include_dir_path, subckt_dir_path, LL_rr_node_indices, + num_clocks, arch, ix, iy, CHANX, SPICE_CB_MUX_TB, + leakage_only); + if (1 == used) { + cnt += used; + } + /* free */ + my_free(mux_testbench_name); + } + } + for (ix = 0; ix < (nx+1); ix++) { + for (iy = 1; iy < (ny+1); iy++) { + mux_testbench_name = (char*)my_malloc(sizeof(char)*( strlen(circuit_name) + + 4 + strlen(my_itoa(ix)) + 2 + strlen(my_itoa(iy)) + 1 + + strlen(spice_cb_mux_testbench_postfix) + 1 )); + sprintf(mux_testbench_name, "%s_cby%d_%d%s", + circuit_name, ix, iy, spice_cb_mux_testbench_postfix); + used = fprint_spice_one_mux_testbench(formatted_spice_dir, circuit_name, mux_testbench_name, + include_dir_path, subckt_dir_path, LL_rr_node_indices, + num_clocks, arch, ix, iy, CHANY, SPICE_CB_MUX_TB, + leakage_only); + if (1 == used) { + cnt += used; + } + /* free */ + my_free(mux_testbench_name); + } + } + /* Update the global counter */ + num_used_cb_mux_tb = cnt; + vpr_printf(TIO_MESSAGE_INFO,"No. of generated CB_MUX testbench = %d\n", num_used_cb_mux_tb); + break; + case SPICE_SB_MUX_TB: + cnt = 0; + for (ix = 0; ix < (nx+1); ix++) { + for (iy = 0; iy < (ny+1); iy++) { + mux_testbench_name = (char*)my_malloc(sizeof(char)*( strlen(circuit_name) + + 4 + strlen(my_itoa(ix)) + 2 + strlen(my_itoa(iy)) + 1 + + strlen(spice_sb_mux_testbench_postfix) + 1 )); + sprintf(mux_testbench_name, "%s_sb%d_%d%s", + circuit_name, ix, iy, spice_sb_mux_testbench_postfix); + used = fprint_spice_one_mux_testbench(formatted_spice_dir, circuit_name, mux_testbench_name, + include_dir_path, subckt_dir_path, LL_rr_node_indices, + num_clocks, arch, ix, iy, NUM_RR_TYPES, SPICE_SB_MUX_TB, + leakage_only); + if (1 == used) { + cnt += used; + } + /* free */ + my_free(mux_testbench_name); + } + } + /* Update the global counter */ + num_used_sb_mux_tb = cnt; + vpr_printf(TIO_MESSAGE_INFO,"No. of generated SB_MUX testbench = %d\n", num_used_sb_mux_tb); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d]) Invalid mux_tb_type!\n", __FILE__, __LINE__); + exit(1); + } + + return; +} diff --git a/vpr7_rram/vpr/SRC/spice/spice_mux_testbench.h b/vpr7_rram/vpr/SRC/spice/spice_mux_testbench.h new file mode 100644 index 000000000..4e6740ae8 --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_mux_testbench.h @@ -0,0 +1,24 @@ + +enum e_spice_mux_tb_type { + SPICE_CB_MUX_TB, SPICE_SB_MUX_TB, SPICE_PB_MUX_TB +}; + +void spice_print_mux_testbench(char* formatted_spice_dir, + char* circuit_name, + char* include_dir_path, + char* subckt_dir_path, + t_ivec*** LL_rr_node_indices, + int num_clock, + t_arch arch, + enum e_spice_mux_tb_type mux_tb_type, + boolean leakage_only); + +/* useful subroutines */ +void fprint_spice_mux_testbench_pb_graph_pin_inv_loads_rec(FILE* fp, + int grid_x, int grid_y, + t_pb_graph_pin* src_pb_graph_pin, + t_pb* src_pb, + char* outport_name, + boolean consider_parent_node, + t_ivec*** LL_rr_node_indices); + diff --git a/vpr7_rram/vpr/SRC/spice/spice_pbtypes.c b/vpr7_rram/vpr/SRC/spice/spice_pbtypes.c new file mode 100644 index 000000000..cd1bbb953 --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_pbtypes.c @@ -0,0 +1,2414 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph.h" +#include "vpr_utils.h" + +/* Include SPICE support headers*/ +#include "linkedlist.h" +#include "fpga_spice_globals.h" +#include "spice_globals.h" +#include "fpga_spice_utils.h" +#include "spice_utils.h" +#include "spice_mux.h" +#include "spice_lut.h" +#include "spice_primitives.h" +#include "spice_pbtypes.h" + +/***** Subroutines *****/ + +/* Print ports of pb_types, + * SRAM ports are not printed here!!! + */ +void fprint_pb_type_ports(FILE* fp, + char* port_prefix, + int use_global_clock, + t_pb_type* cur_pb_type) { + int iport, ipin; + int num_pb_type_input_port = 0; + t_port** pb_type_input_ports = NULL; + + int num_pb_type_output_port = 0; + t_port** pb_type_output_ports = NULL; + + int num_pb_type_inout_port = 0; + t_port** pb_type_inout_ports = NULL; + + int num_pb_type_clk_port = 0; + t_port** pb_type_clk_ports = NULL; + + char* formatted_port_prefix = chomp_spice_node_prefix(port_prefix); + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + } + + /* Inputs */ + /* Find pb_type input ports */ + pb_type_input_ports = find_pb_type_ports_match_spice_model_port_type(cur_pb_type, SPICE_MODEL_PORT_INPUT, &num_pb_type_input_port); + for (iport = 0; iport < num_pb_type_input_port; iport++) { + for (ipin = 0; ipin < pb_type_input_ports[iport]->num_pins; ipin++) { + fprintf(fp, "%s->%s[%d] ", formatted_port_prefix, pb_type_input_ports[iport]->name, ipin); + } + } + /* Outputs */ + /* Find pb_type output ports */ + pb_type_output_ports = find_pb_type_ports_match_spice_model_port_type(cur_pb_type, SPICE_MODEL_PORT_OUTPUT, &num_pb_type_output_port); + for (iport = 0; iport < num_pb_type_output_port; iport++) { + for (ipin = 0; ipin < pb_type_output_ports[iport]->num_pins; ipin++) { + fprintf(fp, "%s->%s[%d] ", formatted_port_prefix, pb_type_output_ports[iport]->name, ipin); + } + } + /* INOUT ports */ + /* Find pb_type inout ports */ + pb_type_inout_ports = find_pb_type_ports_match_spice_model_port_type(cur_pb_type, SPICE_MODEL_PORT_INOUT, &num_pb_type_inout_port); + for (iport = 0; iport < num_pb_type_inout_port; iport++) { + for (ipin = 0; ipin < pb_type_inout_ports[iport]->num_pins; ipin++) { + fprintf(fp, "%s->%s[%d] ", formatted_port_prefix, pb_type_inout_ports[iport]->name, ipin); + } + } + /* Clocks */ + /* Identify if the clock port is a global signal */ + /* Find pb_type clock ports */ + pb_type_clk_ports = find_pb_type_ports_match_spice_model_port_type(cur_pb_type, SPICE_MODEL_PORT_CLOCK, &num_pb_type_clk_port); + for (iport = 0; iport < num_pb_type_clk_port; iport++) { + /* only search mapped ports for primitive node */ + if (NULL != cur_pb_type->spice_model) { + /* We need to bypass global ports */ + assert(NULL != pb_type_clk_ports[iport]->spice_model_port); + if (TRUE == pb_type_clk_ports[iport]->spice_model_port->is_global) { + continue; + } + } + for (ipin = 0; ipin < pb_type_clk_ports[iport]->num_pins; ipin++) { + fprintf(fp, "%s->%s[%d] ", formatted_port_prefix, pb_type_clk_ports[iport]->name, ipin); + } + } + + /* Free */ + my_free(formatted_port_prefix); + my_free(pb_type_input_ports); + my_free(pb_type_output_ports); + my_free(pb_type_inout_ports); + my_free(pb_type_clk_ports); + + return; +} + +/* This is a truncated version of generate_spice_src_des_pb_graph_pin_prefix + * Only used to generate prefix for those dangling pin in PB Types + */ +void fprint_spice_dangling_des_pb_graph_pin_interc(FILE* fp, + t_pb_graph_pin* des_pb_graph_pin, + t_mode* cur_mode, + enum e_pin2pin_interc_type pin2pin_interc_type, + char* parent_pin_prefix) { + t_pb_graph_node* des_pb_graph_node = NULL; + t_pb_type* des_pb_type = NULL; + int des_pb_type_index = -1; + int fan_in = 0; + t_interconnect* cur_interc = NULL; + char* des_pin_prefix = NULL; + + /* char* formatted_parent_pin_prefix = format_spice_node_prefix(parent_pin_prefix);*/ /* Complete a "_" at the end if needed*/ + //char* chomped_parent_pin_prefix = chomp_spice_node_prefix(parent_pin_prefix); /* Remove a "_" at the end if needed*/ + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check the pb_graph_nodes*/ + if (NULL == des_pb_graph_pin) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid pointer: des_pb_graph_pin.\n", + __FILE__, __LINE__); + exit(1); + } + + find_interc_fan_in_des_pb_graph_pin(des_pb_graph_pin, cur_mode, &cur_interc, &fan_in); + if ((NULL != cur_interc)&&(0 != fan_in)) { + return; + /* + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Cur_interc not NULL & fan_in not zero!\n", + __FILE__, __LINE__); + exit(1); + */ + } + + /* Initialize */ + des_pb_graph_node = des_pb_graph_pin->parent_node; + des_pb_type = des_pb_graph_node->pb_type; + des_pb_type_index = des_pb_graph_node->placement_index; + + /* generate the pin prefix for src_pb_graph_node and des_pb_graph_node */ + switch (pin2pin_interc_type) { + case INPUT2INPUT_INTERC: + /* src_pb_graph_node.input_pins -----------------> des_pb_graph_node.input_pins + * des_pb_graph_node is a child of src_pb_graph_node + * parent_pin_prefix is the prefix from parent pb_graph_node, in this case, src_pb_graph_node + * src_pin_prefix: we need to handle the feedbacks, they comes from the same-level pb_graph_node + * src_pin_prefix = + * OR + * src_pin_prefix = _[] + * des_pin_prefix = mode[]_[]_ + */ + /* + des_pin_prefix = (char*)my_malloc(sizeof(char)* + (strlen(formatted_parent_pin_prefix) + 5 + strlen(cur_mode->name) + + 2 + strlen(des_pb_type->name) + 1 + strlen(my_itoa(des_pb_type_index)) + 1 + 1)); + sprintf(des_pin_prefix, "%smode[%s]_%s[%d]", + formatted_parent_pin_prefix, cur_mode->name, des_pb_type->name, des_pb_type_index); + */ + /*Simplify the prefix, make the SPICE netlist readable*/ + des_pin_prefix = (char*)my_malloc(sizeof(char)* + (strlen(des_pb_type->name) + 1 + strlen(my_itoa(des_pb_type_index)) + 1 + 1)); + sprintf(des_pin_prefix, "%s[%d]", + des_pb_type->name, des_pb_type_index); + /* This is a start point, we connect it to gnd*/ + fprintf(fp, "Vdangling_%s->%s[%d] %s->%s[%d] 0 0\n", + des_pin_prefix, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number, + des_pin_prefix, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number); + fprintf(fp, ".nodeset V(%s->%s[%d]) 0\n", + des_pin_prefix, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number); + break; + case OUTPUT2OUTPUT_INTERC: + /* src_pb_graph_node.output_pins -----------------> des_pb_graph_node.output_pins + * src_pb_graph_node is a child of des_pb_graph_node + * parent_pin_prefix is the prefix from parent pb_graph_node, in this case, des_pb_graph_node + * src_pin_prefix = mode[]_[]_ + * des_pin_prefix = + */ + /* + des_pin_prefix = (char*)my_malloc(sizeof(char)* + (strlen(formatted_parent_pin_prefix) + 5 + strlen(cur_mode->name) + + 2 + strlen(des_pb_type->name) + 1 + strlen(my_itoa(des_pb_type_index)) + 1 + 1)); + sprintf(des_pin_prefix, "%smode[%s]_%s[%d]", + formatted_parent_pin_prefix, cur_mode->name, des_pb_type->name, des_pb_type_index); + */ + if (des_pb_type == cur_mode->parent_pb_type) { /* Interconnection from parent pb_type*/ + des_pin_prefix = (char*)my_malloc(sizeof(char)* + (5 + strlen(cur_mode->name) + 2 )); + sprintf(des_pin_prefix, "mode[%s]", cur_mode->name); + } else { + des_pin_prefix = (char*)my_malloc(sizeof(char)* + (strlen(des_pb_type->name) + 1 + strlen(my_itoa(des_pb_type_index)) + 1 + 1)); + sprintf(des_pin_prefix, "%s[%d]", + des_pb_type->name, des_pb_type_index); + } + /*Simplify the prefix, make the SPICE netlist readable*/ + /* This is a start point, we connect it to gnd*/ + fprintf(fp, "Vdangling_%s->%s[%d] %s->%s[%d] 0 0\n", + des_pin_prefix, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number, + des_pin_prefix, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number); + fprintf(fp, ".nodeset V(%s->%s[%d]) 0\n", + des_pin_prefix, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s [LINE%d])Invalid pin to pin interconnection type!\n", + __FILE__, __LINE__); + exit(1); + } + + my_free(des_pin_prefix); + + return; +} + +void generate_spice_src_des_pb_graph_pin_prefix(t_pb_graph_node* src_pb_graph_node, + t_pb_graph_node* des_pb_graph_node, + enum e_pin2pin_interc_type pin2pin_interc_type, + t_interconnect* pin2pin_interc, + char* parent_pin_prefix, + char** src_pin_prefix, + char** des_pin_prefix) { + t_pb_type* src_pb_type = NULL; + int src_pb_type_index = -1; + + t_pb_type* des_pb_type = NULL; + int des_pb_type_index = -1; + + //char* formatted_parent_pin_prefix = format_spice_node_prefix(parent_pin_prefix); /* Complete a "_" at the end if needed*/ + //char* chomped_parent_pin_prefix = chomp_spice_node_prefix(parent_pin_prefix); /* Remove a "_" at the end if needed*/ + + t_mode* pin2pin_interc_parent_mode = NULL; + + /* Check the pb_graph_nodes*/ + if (NULL == src_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid pointer: src_pb_graph_node.\n", + __FILE__, __LINE__); + exit(1); + } + if (NULL == des_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid pointer: des_pb_graph_node.\n", + __FILE__, __LINE__); + exit(1); + } + if (NULL == pin2pin_interc) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid pointer: pin2pin_interc.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Initialize */ + src_pb_type = src_pb_graph_node->pb_type; + src_pb_type_index = src_pb_graph_node->placement_index; + des_pb_type = des_pb_graph_node->pb_type; + des_pb_type_index = des_pb_graph_node->placement_index; + + pin2pin_interc_parent_mode = pin2pin_interc->parent_mode; + + assert(NULL == (*src_pin_prefix)); + assert(NULL == (*des_pin_prefix)); + /* generate the pin prefix for src_pb_graph_node and des_pb_graph_node */ + switch (pin2pin_interc_type) { + case INPUT2INPUT_INTERC: + /* src_pb_graph_node.input_pins -----------------> des_pb_graph_node.input_pins + * des_pb_graph_node is a child of src_pb_graph_node + * parent_pin_prefix is the prefix from parent pb_graph_node, in this case, src_pb_graph_node + * src_pin_prefix: we need to handle the feedbacks, they comes from the same-level pb_graph_node + * src_pin_prefix = + * OR + * src_pin_prefix = _[] + * des_pin_prefix = mode[]_[]_ + */ + if (src_pb_type == des_pb_type->parent_mode->parent_pb_type) { /* Interconnection from parent pb_type*/ + /* + (*src_pin_prefix) = my_strdup(chomped_parent_pin_prefix); + */ + /*Simplify the prefix, make the SPICE netlist readable*/ + (*src_pin_prefix) = (char*)my_malloc(sizeof(char)* + (5 + strlen(des_pb_type->parent_mode->name) + 2)); + sprintf((*src_pin_prefix), "mode[%s]", des_pb_type->parent_mode->name); + } else { + /* + (*src_pin_prefix) = (char*)my_malloc(sizeof(char)* + (strlen(formatted_parent_pin_prefix) + 5 + strlen(pin2pin_interc_parent_mode->name) + + 2 + strlen(src_pb_type->name) + 1 + strlen(my_itoa(src_pb_type_index)) + 1 + 1)); + sprintf((*src_pin_prefix), "%smode[%s]_%s[%d]", + formatted_parent_pin_prefix, pin2pin_interc_parent_mode->name, src_pb_type->name, src_pb_type_index); + */ + /*Simplify the prefix, make the SPICE netlist readable*/ + (*src_pin_prefix) = (char*)my_malloc(sizeof(char)* + (strlen(src_pb_type->name) + 1 + strlen(my_itoa(src_pb_type_index)) + 1 + 1)); + sprintf((*src_pin_prefix), "%s[%d]", + src_pb_type->name, src_pb_type_index); + } + /* + (*des_pin_prefix) = (char*)my_malloc(sizeof(char)* + (strlen(formatted_parent_pin_prefix) + 5 + strlen(pin2pin_interc_parent_mode->name) + + 2 + strlen(des_pb_type->name) + 1 + strlen(my_itoa(des_pb_type_index)) + 1 + 1)); + sprintf((*des_pin_prefix), "%smode[%s]_%s[%d]", + formatted_parent_pin_prefix, pin2pin_interc_parent_mode->name, des_pb_type->name, des_pb_type_index); + */ + /*Simplify the prefix, make the SPICE netlist readable*/ + (*des_pin_prefix) = (char*)my_malloc(sizeof(char)* + (strlen(des_pb_type->name) + 1 + strlen(my_itoa(des_pb_type_index)) + 1 + 1)); + sprintf((*des_pin_prefix), "%s[%d]", + des_pb_type->name, des_pb_type_index); + break; + case OUTPUT2OUTPUT_INTERC: + /* src_pb_graph_node.output_pins -----------------> des_pb_graph_node.output_pins + * src_pb_graph_node is a child of des_pb_graph_node + * parent_pin_prefix is the prefix from parent pb_graph_node, in this case, des_pb_graph_node + * src_pin_prefix = mode[]_[]_ + * des_pin_prefix = + */ + /* + (*src_pin_prefix) = (char*)my_malloc(sizeof(char)* + (strlen(formatted_parent_pin_prefix) + 5 + strlen(pin2pin_interc_parent_mode->name) + + 2 + strlen(src_pb_type->name) + 1 + strlen(my_itoa(src_pb_type_index)) + 1 + 1)); + sprintf((*src_pin_prefix), "%smode[%s]_%s[%d]", + formatted_parent_pin_prefix, pin2pin_interc_parent_mode->name, src_pb_type->name, src_pb_type_index); + */ + /*Simplify the prefix, make the SPICE netlist readable*/ + (*src_pin_prefix) = (char*)my_malloc(sizeof(char)* + (strlen(src_pb_type->name) + 1 + strlen(my_itoa(src_pb_type_index)) + 1 + 1)); + sprintf((*src_pin_prefix), "%s[%d]", + src_pb_type->name, src_pb_type_index); + if (des_pb_type == src_pb_type->parent_mode->parent_pb_type) { /* Interconnection from parent pb_type*/ + /* + (*des_pin_prefix) = my_strdup(chomped_parent_pin_prefix); + */ + /*Simplify the prefix, make the SPICE netlist readable*/ + (*des_pin_prefix) = (char*)my_malloc(sizeof(char)* + (5 + strlen(src_pb_type->parent_mode->name) + 2)); + sprintf((*des_pin_prefix), "mode[%s]", src_pb_type->parent_mode->name); + } else { + /* + (*des_pin_prefix) = (char*)my_malloc(sizeof(char)* + (strlen(formatted_parent_pin_prefix) + 5 + strlen(pin2pin_interc_parent_mode->name) + + 2 + strlen(des_pb_type->name) + 1 + strlen(my_itoa(des_pb_type_index)) + 1 + 1)); + sprintf((*des_pin_prefix), "%smode[%s]_%s[%d]", + formatted_parent_pin_prefix, pin2pin_interc_parent_mode->name, des_pb_type->name, des_pb_type_index); + */ + /*Simplify the prefix, make the SPICE netlist readable*/ + (*des_pin_prefix) = (char*)my_malloc(sizeof(char)* + (strlen(des_pb_type->name) + 1 + strlen(my_itoa(des_pb_type_index)) + 1 + 1)); + sprintf((*des_pin_prefix), "%s[%d]", + des_pb_type->name, des_pb_type_index); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s [LINE%d])Invalid pin to pin interconnection type!\n", + __FILE__, __LINE__); + exit(1); + } + return; +} + +void find_interc_fan_in_des_pb_graph_pin(t_pb_graph_pin* des_pb_graph_pin, + t_mode* cur_mode, + t_interconnect** cur_interc, + int* fan_in) { + int iedge; + + (*cur_interc) = NULL; + (*fan_in) = 0; + + /* Search the input edges only, stats on the size of MUX we may need (fan-in) */ + for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { + /* 1. First, we should make sure this interconnect is in the selected mode!!!*/ + if (cur_mode == des_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode) { + /* Check this edge*/ + check_pb_graph_edge(*(des_pb_graph_pin->input_edges[iedge])); + /* Record the interconnection*/ + if (NULL == (*cur_interc)) { + (*cur_interc) = des_pb_graph_pin->input_edges[iedge]->interconnect; + } else { /* Make sure the interconnections for this pin is the same!*/ + assert((*cur_interc) == des_pb_graph_pin->input_edges[iedge]->interconnect); + } + /* Search the input_pins of input_edges only*/ + (*fan_in) += des_pb_graph_pin->input_edges[iedge]->num_input_pins; + } + } + + return; +} + +/* We check output_pins of cur_pb_graph_node and its the input_edges + * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node + * src_pb_graph_node.[in|out]_pins -----------------> des_pb_graph_node.[in|out]pins + * /|\ + * | + * input_pins, edges, output_pins + */ +void fprintf_spice_pb_graph_pin_interc(FILE* fp, + char* parent_pin_prefix, + enum e_pin2pin_interc_type pin2pin_interc_type, + t_pb_graph_pin* des_pb_graph_pin, + t_mode* cur_mode, + int select_edge) { + int iedge, ilevel; + int fan_in = 0; + t_interconnect* cur_interc = NULL; + enum e_interconnect spice_interc_type = DIRECT_INTERC; + + t_pb_graph_pin* src_pb_graph_pin = NULL; + t_pb_graph_node* src_pb_graph_node = NULL; + t_pb_type* src_pb_type = NULL; + int src_pb_type_index = -1; + + t_pb_graph_node* des_pb_graph_node = NULL; + t_pb_type* des_pb_type = NULL; + int des_pb_type_index = -1; + + char* formatted_parent_pin_prefix = chomp_spice_node_prefix(parent_pin_prefix); /* Complete a "_" at the end if needed*/ + char* src_pin_prefix = NULL; + char* des_pin_prefix = NULL; + char* sram_vdd_port_name = NULL; + + int num_sram_bits = 0; + int* sram_bits = NULL; + int num_sram = 0; + int cur_sram = 0; + int mux_level = 0; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* 1. identify pin interconnection type, + * 2. Identify the number of fan-in (Consider interconnection edges of only selected mode) + * 3. Select and print the SPICE netlist + */ + fan_in = 0; + cur_interc = NULL; + find_interc_fan_in_des_pb_graph_pin(des_pb_graph_pin, cur_mode, &cur_interc, &fan_in); + if ((NULL == cur_interc)||(0 == fan_in)) { + /* No interconnection matched */ + /* Connect this pin to GND for better convergence */ + /* TODO: find the correct pin name!!!*/ + fprint_spice_dangling_des_pb_graph_pin_interc(fp, des_pb_graph_pin, cur_mode, pin2pin_interc_type, + formatted_parent_pin_prefix); + return; + } + /* Initialize the interconnection type that will be implemented in SPICE netlist*/ + switch (cur_interc->type) { + case DIRECT_INTERC: + assert(1 == fan_in); + spice_interc_type = DIRECT_INTERC; + break; + case COMPLETE_INTERC: + if (1 == fan_in) { + spice_interc_type = DIRECT_INTERC; + } else { + assert((2 == fan_in)||(2 < fan_in)); + spice_interc_type = MUX_INTERC; + } + break; + case MUX_INTERC: + assert((2 == fan_in)||(2 < fan_in)); + spice_interc_type = MUX_INTERC; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid interconnection type for %s (Arch[LINE%d])!\n", + __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); + exit(1); + } + /* This time, (2nd round), we print the subckt, according to interc type*/ + switch (spice_interc_type) { + case DIRECT_INTERC: + /* Check : + * 1. Direct interc has only one fan-in! + */ + assert(1 == fan_in); + //assert(1 == des_pb_graph_pin->num_input_edges); + /* For more than one mode defined, the direct interc has more than one input_edge , + * We need to find which edge is connected the pin we want + */ + for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { + if (cur_interc == des_pb_graph_pin->input_edges[iedge]->interconnect) { + break; + } + } + assert(iedge < des_pb_graph_pin->num_input_edges); + /* 2. spice_model is a wire */ + assert(NULL != cur_interc->spice_model); + assert(SPICE_MODEL_WIRE == cur_interc->spice_model->type); + assert(NULL != cur_interc->spice_model->wire_param); + /* Initialize*/ + /* Source pin, node, pb_type*/ + src_pb_graph_pin = des_pb_graph_pin->input_edges[iedge]->input_pins[0]; + src_pb_graph_node = src_pb_graph_pin->parent_node; + src_pb_type = src_pb_graph_node->pb_type; + src_pb_type_index = src_pb_graph_node->placement_index; + /* Des pin, node, pb_type */ + des_pb_graph_node = des_pb_graph_pin->parent_node; + des_pb_type = des_pb_graph_node->pb_type; + des_pb_type_index = des_pb_graph_node->placement_index; + /* Generate the pin_prefix for src_pb_graph_node and des_pb_graph_node*/ + generate_spice_src_des_pb_graph_pin_prefix(src_pb_graph_node, des_pb_graph_node, pin2pin_interc_type, + cur_interc, formatted_parent_pin_prefix, &src_pin_prefix, &des_pin_prefix); + /* Call the subckt that has already been defined before */ + fprintf(fp, "X%s[%d] ", cur_interc->spice_model->prefix, cur_interc->spice_model->cnt); + cur_interc->spice_model->cnt++; /* Stats the number of spice_model used*/ + /* Print the pin names! Input and output + * Input: port_prefix_->[pin_index] + * Output: port_prefix_[pin_index] + */ + /* Input */ + /* Make sure correctness*/ + assert(src_pb_type == des_pb_graph_pin->input_edges[iedge]->input_pins[0]->port->parent_pb_type); + /* Print */ + fprintf(fp, "%s->%s[%d] ", + src_pin_prefix, src_pb_graph_pin->port->name, src_pb_graph_pin->pin_number); + /* Output */ + fprintf(fp, "%s->%s[%d] ", + des_pin_prefix, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number); + /* Middle output for wires in logic blocks: TODO: Abolish to save simulation time */ + /* fprintf(fp, "gidle_mid_out "); */ + /* Local vdd and gnd, TODO: we should have an independent VDD for all local interconnections*/ + fprintf(fp, "gvdd_local_interc sgnd "); + /* End with spice_model name */ + fprintf(fp, "%s\n", cur_interc->spice_model->name); + /* Free */ + my_free(src_pin_prefix); + my_free(des_pin_prefix); + src_pin_prefix = NULL; + des_pin_prefix = NULL; + break; + case COMPLETE_INTERC: + case MUX_INTERC: + /* Check : + * MUX should have at least 2 fan_in + */ + assert((2 == fan_in)||(2 < fan_in)); + /* 2. spice_model is a wire */ + assert(NULL != cur_interc->spice_model); + assert(SPICE_MODEL_MUX == cur_interc->spice_model->type); + /* Call the subckt that has already been defined before */ + fprintf(fp, "X%s_size%d[%d] ", cur_interc->spice_model->prefix, fan_in, cur_interc->spice_model->cnt); + /* Global ports */ + if (0 < rec_fprint_spice_model_global_ports(fp, cur_interc->spice_model, FALSE)) { + fprintf(fp, "+ "); + } + /* Inputs */ + for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { + if (cur_mode != des_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode) { + continue; + } + check_pb_graph_edge(*(des_pb_graph_pin->input_edges[iedge])); + /* Initialize*/ + /* Source pin, node, pb_type*/ + src_pb_graph_pin = des_pb_graph_pin->input_edges[iedge]->input_pins[0]; + src_pb_graph_node = src_pb_graph_pin->parent_node; + src_pb_type = src_pb_graph_node->pb_type; + src_pb_type_index = src_pb_graph_node->placement_index; + /* Des pin, node, pb_type */ + des_pb_graph_node = des_pb_graph_pin->parent_node; + des_pb_type = des_pb_graph_node->pb_type; + des_pb_type_index = des_pb_graph_node->placement_index; + /* Generate the pin_prefix for src_pb_graph_node and des_pb_graph_node*/ + generate_spice_src_des_pb_graph_pin_prefix(src_pb_graph_node, des_pb_graph_node, pin2pin_interc_type, + cur_interc, formatted_parent_pin_prefix, &src_pin_prefix, &des_pin_prefix); + /* We need to find out if the des_pb_graph_pin is in the mode we want !*/ + /* Print */ + fprintf(fp, "%s->%s[%d] ", + src_pin_prefix, src_pb_graph_pin->port->name, src_pb_graph_pin->pin_number); + /* Free */ + my_free(src_pin_prefix); + my_free(des_pin_prefix); + src_pin_prefix = NULL; + des_pin_prefix = NULL; + } + /* Generate the pin_prefix for src_pb_graph_node and des_pb_graph_node*/ + generate_spice_src_des_pb_graph_pin_prefix(src_pb_graph_node, des_pb_graph_node, pin2pin_interc_type, + cur_interc, formatted_parent_pin_prefix, &src_pin_prefix, &des_pin_prefix); + /* Outputs */ + fprintf(fp, "%s->%s[%d] ", + des_pin_prefix, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number); + + assert(select_edge < fan_in); + /* SRAMs */ + switch (cur_interc->spice_model->design_tech_info.structure) { + case SPICE_MODEL_STRUCTURE_TREE: + /* 1. Get the mux level*/ + mux_level = determine_tree_mux_level(fan_in); + /* Get the SRAM configurations*/ + /* Decode the selected_edge_index */ + num_sram_bits = mux_level; + sram_bits = decode_tree_mux_sram_bits(fan_in, mux_level, select_edge); + /* Print SRAM configurations, + * we should have a global SRAM vdd, AND it should be connected to a real sram subckt !!! + */ + break; + case SPICE_MODEL_STRUCTURE_ONELEVEL: + mux_level = 1; + /* Special for 2-input MUX */ + if (2 == fan_in) { + num_sram_bits = 1; + sram_bits = decode_tree_mux_sram_bits(fan_in, mux_level, select_edge); + } else { + num_sram_bits = fan_in; + sram_bits = decode_onelevel_mux_sram_bits(fan_in, mux_level, select_edge); + } + break; + case SPICE_MODEL_STRUCTURE_MULTILEVEL: + mux_level = cur_interc->spice_model->design_tech_info.mux_num_level; + num_sram_bits = determine_num_input_basis_multilevel_mux(fan_in, mux_level) *mux_level; + sram_bits = decode_multilevel_mux_sram_bits(fan_in, mux_level, select_edge); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n", + __FILE__, __LINE__, cur_interc->spice_model->name); + exit(1); + } + cur_sram = get_sram_orgz_info_num_mem_bit(sram_spice_orgz_info); + /* Create wires to sram outputs*/ + for (ilevel = 0; ilevel < num_sram_bits; ilevel++) { + assert( (0 == sram_bits[ilevel]) || (1 == sram_bits[ilevel]) ); + fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, cur_sram + ilevel, sram_bits[ilevel]); + fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, cur_sram + ilevel, 1 - sram_bits[ilevel]); + } + /* Local vdd and gnd, TODO: we should have an independent VDD for all local interconnections*/ + fprintf(fp, "gvdd_local_interc sgnd "); + /* End with spice_model name */ + fprintf(fp, "%s_size%d\n", cur_interc->spice_model->name, fan_in); + /* Print the encoding in SPICE netlist for debugging */ + fprintf(fp, "***** SRAM bits for MUX[%d], level=%d, select_path_id=%d. *****\n", + cur_interc->spice_model->cnt, mux_level, select_edge); + fprintf(fp, "*****"); + for (ilevel = 0; ilevel < num_sram_bits; ilevel++) { + fprintf(fp, "%d", sram_bits[ilevel]); + } + fprintf(fp, "*****\n"); + /* Print all the srams*/ + cur_sram = get_sram_orgz_info_num_mem_bit(sram_spice_orgz_info); + /* Give the VDD port name for SRAMs */ + sram_vdd_port_name = (char*)my_malloc(sizeof(char)* + (strlen(spice_tb_global_vdd_localrouting_sram_port_name) + + 1 )); + sprintf(sram_vdd_port_name, "%s", + spice_tb_global_vdd_localrouting_sram_port_name); + /* Now Print SRAMs one by one */ + for (ilevel = 0; ilevel < num_sram_bits; ilevel++) { + fprint_spice_one_sram_subckt(fp, sram_spice_orgz_info, + cur_interc->spice_model, + sram_vdd_port_name); + } + /* Store the configuraion bit to linked-list */ + add_sram_conf_bits_to_llist(sram_spice_orgz_info, cur_sram, + num_sram_bits, sram_bits); + /* Update spice_model counter */ + cur_interc->spice_model->cnt++; + /* Free */ + my_free(sram_bits); + my_free(src_pin_prefix); + my_free(des_pin_prefix); + my_free(sram_vdd_port_name); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid interconnection type for %s (Arch[LINE%d])!\n", + __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); + exit(1); + } + return; +} + + +/* Print the SPICE interconnections according to pb_graph */ +void fprint_spice_pb_graph_interc(FILE* fp, + char* pin_prefix, + t_pb_graph_node* cur_pb_graph_node, + t_pb* cur_pb, + int select_mode_index, + int is_idle) { + int iport, ipin; + int ipb, jpb; + t_mode* cur_mode = NULL; + t_pb_type* cur_pb_type = cur_pb_graph_node->pb_type; + t_pb_graph_node* child_pb_graph_node = NULL; + t_pb* child_pb = NULL; + int is_child_pb_idle = 0; + + char* formatted_pin_prefix = format_spice_node_prefix(pin_prefix); /* Complete a "_" at the end if needed*/ + + int node_index = -1; + int prev_node = -1; + int prev_edge = -1; + int path_id = -1; + t_rr_node* pb_rr_nodes = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check cur_pb_type*/ + if (NULL == cur_pb_type) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb_type.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Assign current mode */ + cur_mode = &(cur_pb_graph_node->pb_type->modes[select_mode_index]); + + /* We check output_pins of cur_pb_graph_node and its the input_edges + * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node + * child_pb_graph_node.output_pins -----------------> cur_pb_graph_node.outpins + * /|\ + * | + * input_pins, edges, output_pins + */ + for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) { + for (ipin = 0; ipin < cur_pb_graph_node->num_output_pins[iport]; ipin++) { + /* If this is a idle block, we set 0 to the selected edge*/ + if (is_idle) { + assert(NULL == cur_pb); + fprintf_spice_pb_graph_pin_interc(fp, + formatted_pin_prefix, /* parent_pin_prefix */ + OUTPUT2OUTPUT_INTERC, + &(cur_pb_graph_node->output_pins[iport][ipin]), + cur_mode, + 0); + } else { + /* Get the selected edge of current pin*/ + assert(NULL != cur_pb); + pb_rr_nodes = cur_pb->rr_graph; + node_index = cur_pb_graph_node->output_pins[iport][ipin].pin_count_in_cluster; + prev_node = pb_rr_nodes[node_index].prev_node; + prev_edge = pb_rr_nodes[node_index].prev_edge; + /* Make sure this pb_rr_node is not OPEN and is not a primitive output*/ + if (OPEN == prev_node) { + path_id = 0; // + } else { + /* Find the path_id */ + path_id = find_path_id_between_pb_rr_nodes(pb_rr_nodes, prev_node, node_index); + assert(-1 != path_id); + } + fprintf_spice_pb_graph_pin_interc(fp, + formatted_pin_prefix, /* parent_pin_prefix */ + OUTPUT2OUTPUT_INTERC, + &(cur_pb_graph_node->output_pins[iport][ipin]), + cur_mode, + path_id); + } + } + } + + /* We check input_pins of child_pb_graph_node and its the input_edges + * Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node + * cur_pb_graph_node.input_pins -----------------> child_pb_graph_node.input_pins + * /|\ + * | + * input_pins, edges, output_pins + */ + for (ipb = 0; ipb < cur_pb_type->modes[select_mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb_type->modes[select_mode_index].pb_type_children[ipb].num_pb; jpb++) { + child_pb_graph_node = &(cur_pb_graph_node->child_pb_graph_nodes[select_mode_index][ipb][jpb]); + /* If this is a idle block, we set 0 to the selected edge*/ + if (is_idle) { + assert(NULL == cur_pb); + /* For each child_pb_graph_node input pins*/ + for (iport = 0; iport < child_pb_graph_node->num_input_ports; iport++) { + for (ipin = 0; ipin < child_pb_graph_node->num_input_pins[iport]; ipin++) { + fprintf_spice_pb_graph_pin_interc(fp, + formatted_pin_prefix, /* parent_pin_prefix */ + INPUT2INPUT_INTERC, + &(child_pb_graph_node->input_pins[iport][ipin]), + cur_mode, + 0); + } + } + /* TODO: for clock pins, we should do the same work */ + for (iport = 0; iport < child_pb_graph_node->num_clock_ports; iport++) { + for (ipin = 0; ipin < child_pb_graph_node->num_clock_pins[iport]; ipin++) { + fprintf_spice_pb_graph_pin_interc(fp, + formatted_pin_prefix, /* parent_pin_prefix */ + INPUT2INPUT_INTERC, + &(child_pb_graph_node->clock_pins[iport][ipin]), + cur_mode, + 0); + } + } + continue; + } + assert(NULL != cur_pb); + child_pb = &(cur_pb->child_pbs[ipb][jpb]); + /* Check if child_pb is empty */ + if (NULL != child_pb->name) { + is_child_pb_idle = 0; + } else { + is_child_pb_idle = 1; + } + /* Get pb_rr_graph of current pb*/ + pb_rr_nodes = child_pb->rr_graph; + /* For each child_pb_graph_node input pins*/ + for (iport = 0; iport < child_pb_graph_node->num_input_ports; iport++) { + for (ipin = 0; ipin < child_pb_graph_node->num_input_pins[iport]; ipin++) { + if (is_child_pb_idle) { + prev_edge = 0; + } else { + /* Get the index of the edge that are selected to pass signal*/ + node_index = child_pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster; + prev_node = pb_rr_nodes[node_index].prev_node; + prev_edge = pb_rr_nodes[node_index].prev_edge; + /* Make sure this pb_rr_node is not OPEN and is not a primitive output*/ + if (OPEN == prev_node) { + path_id = 0; // + } else { + /* Find the path_id */ + path_id = find_path_id_between_pb_rr_nodes(pb_rr_nodes, prev_node, node_index); + assert(-1 != path_id); + } + } + /* Write the interconnection*/ + fprintf_spice_pb_graph_pin_interc(fp, + formatted_pin_prefix, /* parent_pin_prefix */ + INPUT2INPUT_INTERC, + &(child_pb_graph_node->input_pins[iport][ipin]), + cur_mode, + path_id); + } + } + /* TODO: for clock pins, we should do the same work */ + for (iport = 0; iport < child_pb_graph_node->num_clock_ports; iport++) { + for (ipin = 0; ipin < child_pb_graph_node->num_clock_pins[iport]; ipin++) { + if (is_child_pb_idle) { + prev_edge = 0; + } else { + /* Get the index of the edge that are selected to pass signal*/ + node_index = child_pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster; + prev_node = pb_rr_nodes[node_index].prev_node; + prev_edge = pb_rr_nodes[node_index].prev_edge; + /* Make sure this pb_rr_node is not OPEN and is not a primitive output*/ + if (OPEN == prev_node) { + path_id = 0; // + } else { + /* Find the path_id */ + path_id = find_path_id_between_pb_rr_nodes(pb_rr_nodes, prev_node, node_index); + assert(-1 != path_id); + } + } + /* Write the interconnection*/ + fprintf_spice_pb_graph_pin_interc(fp, + formatted_pin_prefix, /* parent_pin_prefix */ + INPUT2INPUT_INTERC, + &(child_pb_graph_node->clock_pins[iport][ipin]), + cur_mode, + path_id); + } + } + } + } + + return; +} + +/* Print the netlist for primitive pb_types*/ +void fprint_spice_pb_graph_primitive_node(FILE* fp, + char* subckt_prefix, + t_pb* cur_pb, + t_pb_graph_node* cur_pb_graph_node, + int pb_type_index) { + int iport, ipin; + t_pb_type* cur_pb_type = NULL; + char* formatted_subckt_prefix = format_spice_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/ + t_spice_model* spice_model = NULL; + char* subckt_name = NULL; + char* subckt_port_name = NULL; + + int num_spice_model_sram_port = 0; + t_spice_model_port** spice_model_sram_ports = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check cur_pb_graph_node*/ + if (NULL == cur_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb_graph_node.\n", + __FILE__, __LINE__); + exit(1); + } + + spice_model = cur_pb_type->spice_model; + /* If we define a SPICE model for the pb_type, + * We should print the subckt of it. + * 1. If the SPICE model defines an included netlist, we quote the netlist subckt + * 2. If not defined an included netlist, we built one only if this is a LUT + */ + /* Example: []*/ + subckt_name = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + + strlen(cur_pb_type->name) + 1 + + strlen(my_itoa(pb_type_index)) + 1 + 1)); /* Plus the '0' at the end of string*/ + sprintf(subckt_name, "%s%s[%d]", formatted_subckt_prefix, cur_pb_type->name, pb_type_index); + /* Check if defines an included netlist*/ + if (NULL == spice_model->model_netlist) { + if (LUT_CLASS == cur_pb_type->class_type) { + /* For LUT, we have a built-in netlist, See "spice_lut.c", So we don't do anything here */ + } else { + /* We report an error */ + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Require an included netlist in Pb_type(%s) SPICE_model(%s)!\n", + __FILE__, __LINE__, cur_pb_type->name, spice_model->name); + exit(1); + } + } + /* Print the definition line + * IMPORTANT: NO SRAMs ports are created here, they are fixed when quoting spice_models + */ + fprintf(fp, ".subckt %s ", subckt_name); + subckt_port_name = format_spice_node_prefix(subckt_name); + /* Inputs, outputs, inouts, clocks */ + fprint_pb_type_ports(fp, subckt_port_name, 0, cur_pb_type); + /* Finish with local vdd and gnd */ + fprintf(fp, "svdd sgnd\n"); + /* Include the spice_model*/ + fprintf(fp, "X%s[%d] ", spice_model->prefix, spice_model->cnt); + spice_model->cnt++; /* Stats the number of spice_model used*/ + /* Make input, output, inout, clocks connected*/ + /* IMPORTANT: (sequence of these ports should be changed!) */ + fprint_pb_type_ports(fp, subckt_name, 0, cur_pb_type); + /* Connected to SRAMs */ + /* Configure the SRAMs to be idle*/ + spice_model_sram_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_SRAM, &num_spice_model_sram_port, TRUE); + for (iport = 0; iport < num_spice_model_sram_port; iport++) { + for(ipin = 0; ipin < spice_model_sram_ports[iport]->size; ipin++) { + fprintf(fp, "sgnd "); + } + } + /* Print the spice_model name defined */ + fprintf(fp, "%s\n", spice_model->name); + /* Print end of subckt*/ + fprintf(fp, ".eom\n"); + /* Free */ + my_free(subckt_name); + + return; +} + +/* Print the subckt of a primitive pb */ +void fprint_pb_primitive_spice_model(FILE* fp, + char* subckt_prefix, + t_pb* prim_pb, + t_pb_graph_node* prim_pb_graph_node, + int pb_index, + t_spice_model* spice_model, + int is_idle) { + t_pb_type* prim_pb_type = NULL; + t_logical_block* mapped_logical_block = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check cur_pb_graph_node*/ + if (NULL == prim_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb_graph_node.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Initialize */ + prim_pb_type = prim_pb_graph_node->pb_type; + if (is_idle) { + mapped_logical_block = NULL; + } else { + mapped_logical_block = &logical_block[prim_pb->logical_block]; + } + + /* Asserts*/ + assert(pb_index == prim_pb_graph_node->placement_index); + assert(0 == strcmp(spice_model->name, prim_pb_type->spice_model->name)); + + if (is_idle) { + assert(NULL == prim_pb); + } else { + if (NULL == prim_pb) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid prim_pb.\n", + __FILE__, __LINE__); + exit(1); + } + } + + /* According to different type, we print netlist*/ + switch (spice_model->type) { + case SPICE_MODEL_LUT: + /* If this is a idle block we should set sram_bits to zero*/ + fprint_pb_primitive_lut(fp, subckt_prefix, mapped_logical_block, prim_pb_graph_node, + pb_index, spice_model); + break; + case SPICE_MODEL_FF: + assert(NULL != spice_model->model_netlist); + /* TODO : We should learn trigger type and initial value!!! and how to apply them!!! */ + fprint_pb_primitive_ff(fp, subckt_prefix, mapped_logical_block, prim_pb_graph_node, + pb_index, spice_model); + break; + case SPICE_MODEL_IOPAD: + assert(NULL != spice_model->model_netlist); + fprint_pb_primitive_io(fp, subckt_prefix, mapped_logical_block, prim_pb_graph_node, + pb_index, spice_model); + break; + case SPICE_MODEL_HARDLOGIC: + assert(NULL != spice_model->model_netlist); + fprint_pb_primitive_hardlogic(fp, subckt_prefix, mapped_logical_block, prim_pb_graph_node, + pb_index, spice_model); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of spice_model(%s), should be [LUT|FF|HARD_LOGIC|IO]!\n", + __FILE__, __LINE__, spice_model->name); + exit(1); + break; + } + + return; +} + +/* Print idle pb_types recursively + * search the idle_mode until we reach the leaf node + */ +void fprint_spice_idle_pb_graph_node_rec(FILE* fp, + char* subckt_prefix, + t_pb_graph_node* cur_pb_graph_node, + int pb_type_index) { + int mode_index, ipb, jpb, child_mode_index; + t_pb_type* cur_pb_type = NULL; + char* subckt_name = NULL; + char* formatted_subckt_prefix = format_spice_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/ + char* pass_on_prefix = NULL; + char* child_pb_type_prefix = NULL; + char* subckt_port_prefix = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check cur_pb_graph_node*/ + if (NULL == cur_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb_graph_node.\n", + __FILE__, __LINE__); + exit(1); + } + cur_pb_type = cur_pb_graph_node->pb_type; + + /* Recursively finish all the child pb_types*/ + if (NULL == cur_pb_type->spice_model) { + /* Find the mode that define_idle_mode*/ + mode_index = find_pb_type_idle_mode_index((*cur_pb_type)); + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Pass the SPICE mode prefix on, + * mode[]_ + */ + pass_on_prefix = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(cur_pb_type->name) + 1 + + strlen(my_itoa(pb_type_index)) + 7 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1 + 1)); + sprintf(pass_on_prefix, "%s%s[%d]_mode[%s]_", + formatted_subckt_prefix, cur_pb_type->name, pb_type_index, cur_pb_type->modes[mode_index].name); + /* Recursive*/ + fprint_spice_idle_pb_graph_node_rec(fp, pass_on_prefix, + &(cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), jpb); + /* Free */ + my_free(pass_on_prefix); + } + } + } + + /* Check if this has defined a spice_model*/ + if (NULL != cur_pb_type->spice_model) { + fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix, + NULL, cur_pb_graph_node, + pb_type_index, cur_pb_type->spice_model, 1); + /* Finish the primitive node, we return */ + return; + } + + /* Find the mode that define_idle_mode*/ + mode_index = find_pb_type_idle_mode_index((*cur_pb_type)); + /* Create a new subckt */ + /* mode[] + */ + subckt_name = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(cur_pb_type->name) + 1 + + strlen(my_itoa(pb_type_index)) + 7 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1)); + /* Definition*/ + sprintf(subckt_name, "%s%s[%d]_mode[%s]", + formatted_subckt_prefix, cur_pb_type->name, pb_type_index, cur_pb_type->modes[mode_index].name); + fprintf(fp, ".subckt %s ", subckt_name); + /* Inputs, outputs, inouts, clocks */ + subckt_port_prefix = (char*)my_malloc(sizeof(char)* + (5 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1)); + sprintf(subckt_port_prefix, "mode[%s]", cur_pb_type->modes[mode_index].name); + /* + fprint_pb_type_ports(fp, subckt_name, 0, cur_pb_type); + */ + /* Simplify the port prefix, make SPICE netlist readable */ + fprint_pb_type_ports(fp, subckt_port_prefix, 0, cur_pb_type); + /* Finish with local vdd and gnd */ + fprintf(fp, "svdd sgnd\n"); + /* Definition ends*/ + + /* Specify the head of scan-chain */ + if (SPICE_SRAM_SCAN_CHAIN == sram_spice_orgz_type) { + fprintf(fp, "***** Head of scan-chain *****\n"); + fprintf(fp, "R%s_sc_head %s_sc_head %s[%d]->in 0\n", + subckt_name, subckt_name, sram_spice_model->prefix, sram_spice_model->cnt); + } + + /* Quote all child pb_types */ + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + /* Each child may exist multiple times in the hierarchy*/ + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* we should make sure this placement index == child_pb_type[jpb]*/ + assert(jpb == cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb].placement_index); + /* mode[]_[] + */ + fprintf(fp, "X%s[%d] ", cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); + /* Pass the SPICE mode prefix on, + * mode[]_[] + * [] + */ + /* + child_pb_type_prefix = (char*)my_malloc(sizeof(char)* + (strlen(subckt_name) + 1 + + strlen(cur_pb_type->modes[imode].pb_type_children[ipb].name) + 1 + + strlen(my_itoa(jpb)) + 1 + 1)); + sprintf(child_pb_type_prefix, "%s_%s[%d]", subckt_name, + cur_pb_type->modes[imode].pb_type_children[ipb].name, jpb); + */ + /* Simplify the prefix! */ + child_pb_type_prefix = (char*)my_malloc(sizeof(char)* + (strlen(cur_pb_type->modes[mode_index].pb_type_children[ipb].name) + 1 + + strlen(my_itoa(jpb)) + 1 + 1)); + sprintf(child_pb_type_prefix, "%s[%d]", + cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); + /* Print inputs, outputs, inouts, clocks + * NO SRAMs !!! They have already been fixed in the bottom level + */ + fprint_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb])); + fprintf(fp, "svdd sgnd "); /* Local vdd and gnd*/ + + /* Find the pb_type_children mode */ + if (NULL == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model) { /* Find the idle_mode_index, if this is not a leaf node */ + child_mode_index = find_pb_type_idle_mode_index(cur_pb_type->modes[mode_index].pb_type_children[ipb]); + } + /* If the pb_type_children is a leaf node, we don't use the mode to name it, + * else we can use the mode to name it + */ + if (NULL == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model) { /* Not a leaf node*/ + fprintf(fp, "%s_%s[%d]_mode[%s]\n", + subckt_name, cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb, + cur_pb_type->modes[mode_index].pb_type_children[ipb].modes[child_mode_index].name); + } else { /* Have a spice model definition, this is a leaf node*/ + fprintf(fp, "%s_%s[%d]\n", + subckt_name, cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); + } + my_free(child_pb_type_prefix); + } + } + /* Print interconnections, set is_idle as TRUE*/ + fprint_spice_pb_graph_interc(fp, subckt_name, cur_pb_graph_node, NULL, mode_index, 1); + /* Check each pins of pb_graph_node */ + + /* Specify the Tail of scan-chain */ + if (SPICE_SRAM_SCAN_CHAIN == sram_spice_orgz_type) { + fprintf(fp, "***** Tail of scan-chain *****\n"); + fprintf(fp, "R%s_sc_tail %s_sc_tail %s[%d]->in 0\n", + subckt_name, subckt_name, sram_spice_model->prefix, sram_spice_model->cnt); + } + + /* End the subckt */ + fprintf(fp, ".eom\n"); + /* Free subckt name*/ + my_free(subckt_name); + + return; +} + +/* Print SPICE netlist for each pb and corresponding pb_graph_node*/ +void fprint_spice_pb_graph_node_rec(FILE* fp, + char* subckt_prefix, + t_pb* cur_pb, + t_pb_graph_node* cur_pb_graph_node, + int pb_type_index) { + int mode_index, ipb, jpb, child_mode_index; + t_pb_type* cur_pb_type = NULL; + char* subckt_name = NULL; + char* formatted_subckt_prefix = format_spice_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/ + char* pass_on_prefix = NULL; + char* child_pb_type_prefix = NULL; + + char* subckt_port_prefix = NULL; + t_pb* child_pb = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check cur_pb_graph_node*/ + if (NULL == cur_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb_graph_node.\n", + __FILE__, __LINE__); + exit(1); + } + cur_pb_type = cur_pb_graph_node->pb_type; + mode_index = cur_pb->mode; + + /* Recursively finish all the child pb_types*/ + if (NULL == cur_pb_type->spice_model) { + /* recursive for the child_pbs*/ + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Pass the SPICE mode prefix on, + * []_mode[]_ + */ + pass_on_prefix = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(cur_pb_type->name) + 1 + + strlen(my_itoa(pb_type_index)) + 7 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1 + 1)); + sprintf(pass_on_prefix, "%s%s[%d]_mode[%s]_", + formatted_subckt_prefix, cur_pb_type->name, pb_type_index, cur_pb_type->modes[mode_index].name); + /* Recursive*/ + /* Refer to pack/output_clustering.c [LINE 392] */ + if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { + fprint_spice_pb_graph_node_rec(fp, pass_on_prefix, &(cur_pb->child_pbs[ipb][jpb]), + cur_pb->child_pbs[ipb][jpb].pb_graph_node, jpb); + } else { + /* Check if this pb has no children, no children mean idle*/ + fprint_spice_idle_pb_graph_node_rec(fp, pass_on_prefix, + cur_pb->child_pbs[ipb][jpb].pb_graph_node, jpb); + } + /* Free */ + my_free(pass_on_prefix); + } + } + } + + /* Check if this has defined a spice_model*/ + if (NULL != cur_pb_type->spice_model) { + switch (cur_pb_type->class_type) { + case LUT_CLASS: + /* Special care for LUT !!! + * Mapped logical block information is stored in child_pbs + */ + child_pb = get_lut_child_pb(cur_pb, mode_index); + fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix, + child_pb, cur_pb_graph_node, + pb_type_index, cur_pb_type->spice_model, 0); + break; + case LATCH_CLASS: + assert(0 == cur_pb_type->num_modes); + /* Consider the num_pb, create all the subckts*/ + fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix, + cur_pb, cur_pb_graph_node, + pb_type_index, cur_pb_type->spice_model, 0); + break; + case UNKNOWN_CLASS: + case MEMORY_CLASS: + /* Consider the num_pb, create all the subckts*/ + fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix, + cur_pb, cur_pb_graph_node, + pb_type_index, cur_pb_type->spice_model, 0); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Unknown class type of pb_type(%s)!\n", + __FILE__, __LINE__, cur_pb_type->name); + exit(1); + } + /* Finish for primitive node, return */ + return; + } + + /* Create a new subckt */ + /* mode[] + */ + subckt_name = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(cur_pb_type->name) + 1 + + strlen(my_itoa(pb_type_index)) + 7 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1)); + /* Definition*/ + sprintf(subckt_name, "%s%s[%d]_mode[%s]", + formatted_subckt_prefix, cur_pb_type->name, pb_type_index, cur_pb_type->modes[mode_index].name); + fprintf(fp, ".subckt %s ", subckt_name); + /* Inputs, outputs, inouts, clocks */ + subckt_port_prefix = (char*)my_malloc(sizeof(char)* + (5 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1)); + sprintf(subckt_port_prefix, "mode[%s]", cur_pb_type->modes[mode_index].name); + /* + fprint_pb_type_ports(fp, subckt_name, 0, cur_pb_type); + */ + /* Simplify the prefix! Make the SPICE netlist readable*/ + fprint_pb_type_ports(fp, subckt_port_prefix, 0, cur_pb_type); + /* Finish with local vdd and gnd */ + fprintf(fp, "svdd sgnd\n"); + /* Definition ends*/ + /* Quote all child pb_types */ + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + /* Each child may exist multiple times in the hierarchy*/ + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* we should make sure this placement index == child_pb_type[jpb]*/ + assert(jpb == cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb].placement_index); + /* mode[]_[] + */ + fprintf(fp, "X%s[%d] ", cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); + /* Pass the SPICE mode prefix on, + * mode[]_[] + */ + /* + child_pb_type_prefix = (char*)my_malloc(sizeof(char)* + (strlen(subckt_name) + 1 + + strlen(cur_pb_type->modes[mode_index].pb_type_children[ipb].name) + 1 + + strlen(my_itoa(jpb)) + 1 + 1)); + sprintf(child_pb_type_prefix, "%s_%s[%d]", subckt_name, + cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); + */ + /* Simplify the prefix! Make the SPICE netlist readable*/ + child_pb_type_prefix = (char*)my_malloc(sizeof(char)* + (strlen(cur_pb_type->modes[mode_index].pb_type_children[ipb].name) + 1 + + strlen(my_itoa(jpb)) + 1 + 1)); + sprintf(child_pb_type_prefix, "%s[%d]", + cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); + /* Print inputs, outputs, inouts, clocks + * NO SRAMs !!! They have already been fixed in the bottom level + */ + fprint_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb])); + fprintf(fp, "svdd sgnd "); /* Local vdd and gnd*/ + /* Find the pb_type_children mode */ + if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { + child_mode_index = cur_pb->child_pbs[ipb][jpb].mode; + } else if (NULL == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model) { /* Find the idle_mode_index, if this is not a leaf node */ + child_mode_index = find_pb_type_idle_mode_index(cur_pb_type->modes[mode_index].pb_type_children[ipb]); + } + /* If the pb_type_children is a leaf node, we don't use the mode to name it, + * else we can use the mode to name it + */ + if (NULL == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model) { /* Not a leaf node*/ + fprintf(fp, "%s_%s[%d]_mode[%s]\n", + subckt_name, cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb, + cur_pb_type->modes[mode_index].pb_type_children[ipb].modes[child_mode_index].name); + } else { /* Have a spice model definition, this is a leaf node*/ + fprintf(fp, "%s_%s[%d]\n", + subckt_name, cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); + } + my_free(child_pb_type_prefix); + } + } + /* Print interconnections, set is_idle as TRUE*/ + fprint_spice_pb_graph_interc(fp, subckt_name, cur_pb_graph_node, cur_pb, mode_index, 0); + /* Check each pins of pb_graph_node */ + /* End the subckt */ + fprintf(fp, ".eom\n"); + /* Free subckt name*/ + my_free(subckt_name); + + return; +} + +/* Print SPICE netlist for each pb and corresponding pb_graph_node + * at physical-level implementation */ +void fprint_spice_phy_pb_graph_node_rec(FILE* fp, + char* subckt_prefix, + t_pb* cur_pb, + t_pb_graph_node* cur_pb_graph_node, + int pb_type_index) { + int mode_index, ipb, jpb, child_mode_index, is_idle; + t_pb_type* cur_pb_type = NULL; + char* subckt_name = NULL; + char* formatted_subckt_prefix = format_spice_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/ + char* pass_on_prefix = NULL; + char* child_pb_type_prefix = NULL; + + char* subckt_port_prefix = NULL; + t_pb* child_pb = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check cur_pb_graph_node*/ + if (NULL == cur_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb_graph_node.\n", + __FILE__, __LINE__); + exit(1); + } + cur_pb_type = cur_pb_graph_node->pb_type; + + is_idle = 1; + if (NULL != cur_pb) { + is_idle = 0; + } + + /* Recursively finish all the child pb_types*/ + if (NULL == cur_pb_type->spice_model) { + /* Find the mode that define_idle_mode*/ + mode_index = find_pb_type_physical_mode_index((*cur_pb_type)); + /* recursive for the child_pbs*/ + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Pass the SPICE mode prefix on, + * []_mode[]_ + */ + pass_on_prefix = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(cur_pb_type->name) + 1 + + strlen(my_itoa(pb_type_index)) + 7 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1 + 1)); + sprintf(pass_on_prefix, "%s%s[%d]_mode[%s]_", + formatted_subckt_prefix, cur_pb_type->name, pb_type_index, cur_pb_type->modes[mode_index].name); + /* Recursive*/ + /* Refer to pack/output_clustering.c [LINE 392] */ + /* Find the child pb that is mapped, and the mapping info is not stored in the physical mode ! */ + child_pb = get_child_pb_for_phy_pb_graph_node(cur_pb, ipb, jpb); + fprint_spice_phy_pb_graph_node_rec(fp, pass_on_prefix, child_pb, + &(cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), jpb); + /* Free */ + my_free(pass_on_prefix); + } + } + } + + /* Check if this has defined a spice_model*/ + if (NULL != cur_pb_type->spice_model) { + switch (cur_pb_type->class_type) { + case LUT_CLASS: + if (1 == is_idle) { + fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix, + NULL, cur_pb_graph_node, + pb_type_index, cur_pb_type->spice_model, is_idle); + } else { + child_pb = get_lut_child_pb(cur_pb, mode_index); + /* Special care for LUT !!! + * Mapped logical block information is stored in child_pbs + */ + fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix, + child_pb, cur_pb_graph_node, + pb_type_index, cur_pb_type->spice_model, is_idle); + } + break; + case LATCH_CLASS: + assert(0 == cur_pb_type->num_modes); + /* Consider the num_pb, create all the subckts*/ + fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix, + cur_pb, cur_pb_graph_node, + pb_type_index, cur_pb_type->spice_model, is_idle); + break; + case UNKNOWN_CLASS: + case MEMORY_CLASS: + /* Consider the num_pb, create all the subckts*/ + fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix, + cur_pb, cur_pb_graph_node, + pb_type_index, cur_pb_type->spice_model, is_idle); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Unknown class type of pb_type(%s)!\n", + __FILE__, __LINE__, cur_pb_type->name); + exit(1); + } + /* Finish for primitive node, return */ + return; + } + + /* Find the mode that define_idle_mode*/ + mode_index = find_pb_type_physical_mode_index((*cur_pb_type)); + /* Create a new subckt */ + /* mode[] + */ + subckt_name = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(cur_pb_type->name) + 1 + + strlen(my_itoa(pb_type_index)) + 7 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1)); + /* Definition*/ + sprintf(subckt_name, "%s%s[%d]_mode[%s]", + formatted_subckt_prefix, cur_pb_type->name, pb_type_index, cur_pb_type->modes[mode_index].name); + fprintf(fp, ".subckt %s ", subckt_name); + /* Inputs, outputs, inouts, clocks */ + subckt_port_prefix = (char*)my_malloc(sizeof(char)* + (5 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1)); + sprintf(subckt_port_prefix, "mode[%s]", cur_pb_type->modes[mode_index].name); + /* + fprint_pb_type_ports(fp, subckt_name, 0, cur_pb_type); + */ + /* Simplify the prefix! Make the SPICE netlist readable*/ + fprint_pb_type_ports(fp, subckt_port_prefix, 0, cur_pb_type); + /* Finish with local vdd and gnd */ + fprintf(fp, "svdd sgnd\n"); + /* Definition ends*/ + /* Quote all child pb_types */ + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + /* Each child may exist multiple times in the hierarchy*/ + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* we should make sure this placement index == child_pb_type[jpb]*/ + assert(jpb == cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb].placement_index); + /* If the pb_type_children is a leaf node, we don't use the mode to name it, + * else we can use the mode to name it + */ + fprintf(fp, "X%s[%d] ", cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); + /* Simplify the prefix! Make the SPICE netlist readable*/ + child_pb_type_prefix = (char*)my_malloc(sizeof(char)* + (strlen(cur_pb_type->modes[mode_index].pb_type_children[ipb].name) + 1 + + strlen(my_itoa(jpb)) + 1 + 1)); + sprintf(child_pb_type_prefix, "%s[%d]", + cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); + /* Print inputs, outputs, inouts, clocks + * NO SRAMs !!! They have already been fixed in the bottom level + */ + fprint_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb])); + fprintf(fp, "svdd sgnd "); /* Local vdd and gnd*/ + /* Find the pb_type_children mode */ + /* If the pb_type_children is a leaf node, we don't use the mode to name it, + * else we can use the mode to name it + */ + if (NULL == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model) { /* Not a leaf node*/ + child_mode_index = find_pb_type_idle_mode_index(cur_pb_type->modes[mode_index].pb_type_children[ipb]); + fprintf(fp, "%s_%s[%d]_mode[%s]\n", + subckt_name, cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb, + cur_pb_type->modes[mode_index].pb_type_children[ipb].modes[child_mode_index].name); + } else { /* Have a spice model definition, this is a leaf node*/ + fprintf(fp, "%s_%s[%d]\n", + subckt_name, cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); + } + my_free(child_pb_type_prefix); + } + } + /* Print interconnections, set is_idle as TRUE*/ + fprint_spice_pb_graph_interc(fp, subckt_name, cur_pb_graph_node, cur_pb, mode_index, is_idle); + /* Check each pins of pb_graph_node */ + /* End the subckt */ + fprintf(fp, ".eom\n"); + /* Free subckt name*/ + my_free(subckt_name); + + return; +} + + +/* Print the SPICE netlist of a block that has been mapped */ +void fprint_spice_block(FILE* fp, + char* subckt_name, + int x, + int y, + int z, + t_type_ptr type_descriptor, + t_block* mapped_block) { + t_pb* top_pb = NULL; + t_pb_graph_node* top_pb_graph_node = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* check */ + assert(x == mapped_block->x); + assert(y == mapped_block->y); + assert(type_descriptor == mapped_block->type); + assert(NULL != type_descriptor); + + /* Print SPICE netlist according to the hierachy of type descriptor recursively*/ + /* Go for the pb_types*/ + top_pb_graph_node = type_descriptor->pb_graph_head; + assert(NULL != top_pb_graph_node); + top_pb = mapped_block->pb; + assert(NULL != top_pb); + + /* Recursively find all mode and print netlist*/ + /* IMPORTANT: type_descriptor just say we have a block that in global view, how it connects to global routing arch. + * Inside the type_descripor, there is a top_pb_graph_node(pb_graph_head), describe the top pb_type defined. + * The index of such top pb_type is always 0. + */ + fprint_spice_pb_graph_node_rec(fp, subckt_name, top_pb, top_pb_graph_node, z); + + return; +} + + +/* Print an idle logic block + * Find the idle_mode in arch files, + * And print the spice netlist into file + */ +void fprint_spice_idle_block(FILE* fp, + char* subckt_name, + int x, + int y, + int z, + t_type_ptr type_descriptor) { + t_pb_graph_node* top_pb_graph_node = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Ensure we have a valid type_descriptor*/ + assert(NULL != type_descriptor); + + /* Go for the pb_types*/ + top_pb_graph_node = type_descriptor->pb_graph_head; + assert(NULL != top_pb_graph_node); + + /* Recursively find all idle mode and print netlist*/ + fprint_spice_idle_pb_graph_node_rec(fp, subckt_name, top_pb_graph_node, z); + + return; +} + +/* Print the SPICE netlist of a block that has been mapped */ +void fprint_spice_physical_block(FILE* fp, + char* subckt_name, + int x, + int y, + int z, + t_type_ptr type_descriptor) { + t_pb* top_pb = NULL; + t_pb_graph_node* top_pb_graph_node = NULL; + t_block* mapped_block = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* check */ + assert(NULL != type_descriptor); + top_pb_graph_node = type_descriptor->pb_graph_head; + assert(NULL != top_pb_graph_node); + + /* Print SPICE netlist according to the hierachy of type descriptor recursively*/ + + mapped_block = search_mapped_block(x, y, z); + /* Go for the pb_types*/ + if (NULL != mapped_block) { + top_pb = mapped_block->pb; + assert(NULL != top_pb); + } + + /* Recursively find all mode and print netlist*/ + /* IMPORTANT: type_descriptor just say we have a block that in global view, how it connects to global routing arch. + * Inside the type_descripor, there is a top_pb_graph_node(pb_graph_head), describe the top pb_type defined. + * The index of such top pb_type is always 0. + */ + fprint_spice_phy_pb_graph_node_rec(fp, subckt_name, top_pb, top_pb_graph_node, z); + + return; +} + +/* We print all the pins of a type descriptor in the following sequence + * TOP, RIGHT, BOTTOM, LEFT + */ +void fprint_grid_pins(FILE* fp, + int x, + int y, + int top_level) { + int iheight, side, ipin; + int side_pin_index; + t_type_ptr type_descriptor = grid[x][y].type; + int capacity = grid[x][y].type->capacity; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + assert(NULL != type_descriptor); + assert(0 < capacity); + + for (side = 0; side < 4; side++) { + /* Count the number of pins */ + side_pin_index = 0; + //for (iz = 0; iz < capacity; iz++) { + for (iheight = 0; iheight < type_descriptor->height; iheight++) { + for (ipin = 0; ipin < type_descriptor->num_pins; ipin++) { + if (1 == type_descriptor->pinloc[iheight][side][ipin]) { + /* This pin appear at this side! */ + if (1 == top_level) { + fprintf(fp, "+ grid[%d][%d]_pin[%d][%d][%d] \n", x, y, + iheight, side, ipin); + } else { + fprintf(fp, "+ %s_height[%d]_pin[%d] \n", + convert_side_index_to_string(side), iheight, ipin); + } + side_pin_index++; + } + } + } + //} + } + + return; +} + +/* Special for I/O grid, we need only part of the ports + * i.e., grid[0][0..ny] only need the right side ports. + */ +/* We print all the pins of a type descriptor in the following sequence + * TOP, RIGHT, BOTTOM, LEFT + */ +void fprint_io_grid_pins(FILE* fp, + int x, + int y, + int top_level) { + int iheight, side, ipin; + int side_pin_index; + t_type_ptr type_descriptor = grid[x][y].type; + int capacity = grid[x][y].type->capacity; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + assert(NULL != type_descriptor); + assert(0 < capacity); + /* Make sure this is IO */ + assert(IO_TYPE == type_descriptor); + + /* identify the location of IO grid and + * decide which side of ports we need + */ + side = determine_io_grid_side(x,y); + + /* Count the number of pins */ + side_pin_index = 0; + //for (iz = 0; iz < capacity; iz++) { + for (iheight = 0; iheight < type_descriptor->height; iheight++) { + for (ipin = 0; ipin < type_descriptor->num_pins; ipin++) { + if (1 == type_descriptor->pinloc[iheight][side][ipin]) { + /* This pin appear at this side! */ + if (1 == top_level) { + fprintf(fp, "+ grid[%d][%d]_pin[%d][%d][%d] \n", x, y, + iheight, side, ipin); + } else { + fprintf(fp, "+ %s_height[%d]_pin[%d] \n", + convert_side_index_to_string(side), iheight, ipin); + } + side_pin_index++; + } + } + } + //} + + return; +} + +char* get_grid_block_subckt_name(int x, + int y, + int z, + char* subckt_prefix, + t_block* mapped_block) { + char* ret = NULL; + int imode; + t_type_ptr type_descriptor = NULL; + char* formatted_subckt_prefix = format_spice_node_prefix(subckt_prefix); + int num_idle_mode = 0; + + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + + type_descriptor = grid[x][y].type; + assert(NULL != type_descriptor); + + if (NULL == mapped_block) { + /* This a NULL logic block... Find the idle mode*/ + for (imode = 0; imode < type_descriptor->pb_type->num_modes; imode++) { + if (1 == type_descriptor->pb_type->modes[imode].define_idle_mode) { + num_idle_mode++; + } + } + assert(1 == num_idle_mode); + for (imode = 0; imode < type_descriptor->pb_type->num_modes; imode++) { + if (1 == type_descriptor->pb_type->modes[imode].define_idle_mode) { + ret = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(type_descriptor->name) + 1 + + strlen(my_itoa(z)) + 7 + strlen(type_descriptor->pb_type->modes[imode].name) + 1 + 1)); + sprintf(ret, "%s%s[%d]_mode[%s]", formatted_subckt_prefix, + type_descriptor->name, z, type_descriptor->pb_type->modes[imode].name); + break; + } + } + } else { + /* This is a logic block with specific configurations*/ + assert(NULL != mapped_block->pb); + imode = mapped_block->pb->mode; + ret = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(type_descriptor->name) + 1 + + strlen(my_itoa(z)) + 7 + strlen(type_descriptor->pb_type->modes[imode].name) + 1 + 1)); + sprintf(ret, "%s%s[%d]_mode[%s]", formatted_subckt_prefix, + type_descriptor->name, z, type_descriptor->pb_type->modes[imode].name); + } + + return ret; +} + +/* Physical mode subckt name */ +char* get_grid_phy_block_subckt_name(int x, int y, int z, + char* subckt_prefix, + t_block* mapped_block) { + char* ret = NULL; + int imode; + t_type_ptr type_descriptor = NULL; + char* formatted_subckt_prefix = format_spice_node_prefix(subckt_prefix); + int num_physical_mode = 0; + + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + + type_descriptor = grid[x][y].type; + assert(NULL != type_descriptor); + + if (NULL == mapped_block) { + /* This a NULL logic block... Find the idle mode*/ + for (imode = 0; imode < type_descriptor->pb_type->num_modes; imode++) { + if (1 == type_descriptor->pb_type->modes[imode].define_physical_mode) { + num_physical_mode++; + } + } + assert(1 == num_physical_mode); + for (imode = 0; imode < type_descriptor->pb_type->num_modes; imode++) { + if (1 == type_descriptor->pb_type->modes[imode].define_physical_mode) { + ret = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(type_descriptor->name) + 1 + + strlen(my_itoa(z)) + 7 + strlen(type_descriptor->pb_type->modes[imode].name) + 1 + 1)); + sprintf(ret, "%s%s[%d]_mode[%s]", formatted_subckt_prefix, + type_descriptor->name, z, type_descriptor->pb_type->modes[imode].name); + break; + } + } + } else { + /* This is a logic block with specific configurations*/ + assert(NULL != mapped_block->pb); + imode = mapped_block->pb->mode; + ret = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(type_descriptor->name) + 1 + + strlen(my_itoa(z)) + 7 + strlen(type_descriptor->pb_type->modes[imode].name) + 1 + 1)); + sprintf(ret, "%s%s[%d]_mode[%s]", formatted_subckt_prefix, + type_descriptor->name, z, type_descriptor->pb_type->modes[imode].name); + } + + return ret; +} + + +/* Print the pins of grid subblocks */ +void fprint_grid_block_subckt_pins(FILE* fp, + int z, + t_type_ptr type_descriptor) { + int iport, ipin, side; + int grid_pin_index, pin_height, side_pin_index; + t_pb_graph_node* top_pb_graph_node = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert(NULL != type_descriptor); + top_pb_graph_node = type_descriptor->pb_graph_head; + assert(NULL != top_pb_graph_node); + + for (iport = 0; iport < top_pb_graph_node->num_input_ports; iport++) { + for (ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport]; ipin++) { + grid_pin_index = top_pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster + + z * type_descriptor->num_pins / type_descriptor->capacity; + /* num_pins/capacity = the number of pins that each type_descriptor has. + * Capacity defines the number of type_descriptors in each grid + * so the pin index at grid level = pin_index_in_type_descriptor + * + type_descriptor_index_in_capacity * num_pins_per_type_descriptor + */ + pin_height = type_descriptor->pin_height[grid_pin_index]; + for (side = 0; side < 4; side++) { + if (1 == type_descriptor->pinloc[pin_height][side][grid_pin_index]) { + /* This pin appear at this side! */ + fprintf(fp, "+ %s_height[%d]_pin[%d] \n", + convert_side_index_to_string(side), pin_height, grid_pin_index); + side_pin_index++; + } + } + } + } + + for (iport = 0; iport < top_pb_graph_node->num_output_ports; iport++) { + for (ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport]; ipin++) { + grid_pin_index = top_pb_graph_node->output_pins[iport][ipin].pin_count_in_cluster + + z * type_descriptor->num_pins / type_descriptor->capacity; + /* num_pins/capacity = the number of pins that each type_descriptor has. + * Capacity defines the number of type_descriptors in each grid + * so the pin index at grid level = pin_index_in_type_descriptor + * + type_descriptor_index_in_capacity * num_pins_per_type_descriptor + */ + pin_height = type_descriptor->pin_height[grid_pin_index]; + for (side = 0; side < 4; side++) { + if (1 == type_descriptor->pinloc[pin_height][side][grid_pin_index]) { + /* This pin appear at this side! */ + fprintf(fp, "+ %s_height[%d]_pin[%d] \n", + convert_side_index_to_string(side), pin_height, grid_pin_index); + side_pin_index++; + } + } + } + } + + for (iport = 0; iport < top_pb_graph_node->num_clock_ports; iport++) { + for (ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport]; ipin++) { + grid_pin_index = top_pb_graph_node->clock_pins[iport][ipin].pin_count_in_cluster + + z * type_descriptor->num_pins / type_descriptor->capacity; + /* num_pins/capacity = the number of pins that each type_descriptor has. + * Capacity defines the number of type_descriptors in each grid + * so the pin index at grid level = pin_index_in_type_descriptor + * + type_descriptor_index_in_capacity * num_pins_per_type_descriptor + */ + pin_height = type_descriptor->pin_height[grid_pin_index]; + for (side = 0; side < 4; side++) { + if (1 == type_descriptor->pinloc[pin_height][side][grid_pin_index]) { + /* This pin appear at this side! */ + fprintf(fp, "+ %s_height[%d]_pin[%d] \n", + convert_side_index_to_string(side), pin_height, grid_pin_index); + side_pin_index++; + } + } + } + } + + return; +} + + +/* Print the pins of grid subblocks */ +void fprint_io_grid_block_subckt_pins(FILE* fp, + int x, + int y, + int z, + t_type_ptr type_descriptor) { + int iport, ipin, side; + int grid_pin_index, pin_height, side_pin_index; + t_pb_graph_node* top_pb_graph_node = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert(NULL != type_descriptor); + top_pb_graph_node = type_descriptor->pb_graph_head; + assert(NULL != top_pb_graph_node); + + /* Make sure this is IO */ + assert(IO_TYPE == type_descriptor); + + /* identify the location of IO grid and + * decide which side of ports we need + */ + if (0 == x) { + /* Left side */ + assert((0 < y)&&(y < (ny + 1))); + /* Print Right side ports*/ + side = RIGHT; + } else if ((nx + 1) == x) { + /* Right side */ + assert((0 < y)&&(y < (ny + 1))); + /* Print Left side ports*/ + side = LEFT; + } else if (0 == y) { + /* Bottom Side */ + assert((0 < x)&&(x < (nx + 1))); + /* Print TOP side ports */ + side = TOP; + } else if ((ny + 1) == y) { + /* TOP Side */ + assert((0 < x)&&(x < (nx + 1))); + /* Print BOTTOM side ports */ + side = BOTTOM; + } else { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid co-ordinators(x=%d, y=%d) for I/O grid!\n", + __FILE__, __LINE__, x, y); + exit(1); + } + + for (iport = 0; iport < top_pb_graph_node->num_input_ports; iport++) { + for (ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport]; ipin++) { + grid_pin_index = top_pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster + + z * type_descriptor->num_pins / type_descriptor->capacity; + /* num_pins/capacity = the number of pins that each type_descriptor has. + * Capacity defines the number of type_descriptors in each grid + * so the pin index at grid level = pin_index_in_type_descriptor + * + type_descriptor_index_in_capacity * num_pins_per_type_descriptor + */ + pin_height = type_descriptor->pin_height[grid_pin_index]; + if (1 == type_descriptor->pinloc[pin_height][side][grid_pin_index]) { + /* This pin appear at this side! */ + fprintf(fp, "+ %s_height[%d]_pin[%d] \n", + convert_side_index_to_string(side), pin_height, grid_pin_index); + side_pin_index++; + } + } + } + + for (iport = 0; iport < top_pb_graph_node->num_output_ports; iport++) { + for (ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport]; ipin++) { + grid_pin_index = top_pb_graph_node->output_pins[iport][ipin].pin_count_in_cluster + + z * type_descriptor->num_pins / type_descriptor->capacity; + /* num_pins/capacity = the number of pins that each type_descriptor has. + * Capacity defines the number of type_descriptors in each grid + * so the pin index at grid level = pin_index_in_type_descriptor + * + type_descriptor_index_in_capacity * num_pins_per_type_descriptor + */ + pin_height = type_descriptor->pin_height[grid_pin_index]; + if (1 == type_descriptor->pinloc[pin_height][side][grid_pin_index]) { + /* This pin appear at this side! */ + fprintf(fp, "+ %s_height[%d]_pin[%d] \n", + convert_side_index_to_string(side), pin_height, grid_pin_index); + side_pin_index++; + } + } + } + + for (iport = 0; iport < top_pb_graph_node->num_clock_ports; iport++) { + for (ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport]; ipin++) { + grid_pin_index = top_pb_graph_node->clock_pins[iport][ipin].pin_count_in_cluster + + z * type_descriptor->num_pins / type_descriptor->capacity; + /* num_pins/capacity = the number of pins that each type_descriptor has. + * Capacity defines the number of type_descriptors in each grid + * so the pin index at grid level = pin_index_in_type_descriptor + * + type_descriptor_index_in_capacity * num_pins_per_type_descriptor + */ + pin_height = type_descriptor->pin_height[grid_pin_index]; + if (1 == type_descriptor->pinloc[pin_height][side][grid_pin_index]) { + /* This pin appear at this side! */ + fprintf(fp, "+ %s_height[%d]_pin[%d] \n", + convert_side_index_to_string(side), pin_height, grid_pin_index); + side_pin_index++; + } + } + } + + return; +} + +/* Print the SPICE netlist for a physical grid blocks */ +void fprint_grid_physical_blocks(FILE* fp, + int ix, + int iy, + t_arch* arch) { + int subckt_name_str_len = 0; + char* subckt_name = NULL; + t_block* mapped_block = NULL; + int iz; + int cur_block_index = 0; + int capacity; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert((!(0 > ix))&&(!(ix > (nx + 1)))); + assert((!(0 > iy))&&(!(iy > (ny + 1)))); + + /* Update the grid_index_low for each spice_model */ + update_spice_models_grid_index_low(ix, iy, arch->spice->num_spice_model, arch->spice->spice_models); + + /* generate_grid_subckt, type_descriptor of each grid defines the capacity, + * for example, each grid may contains more than one top-level pb_types, such as I/O + */ + if ((NULL == grid[ix][iy].type)||(0 != grid[ix][iy].offset)) { + /* Update the grid_index_high for each spice_model */ + update_spice_models_grid_index_high(ix, iy, arch->spice->num_spice_model, arch->spice->spice_models); + return; + } + capacity= grid[ix][iy].type->capacity; + assert(0 < capacity); + + /* Make the sub-circuit name*/ + /* Name format: grid[][]_*/ + subckt_name_str_len = 4 + 1 + strlen(my_itoa(ix)) + 2 + + strlen(my_itoa(iy)) + 1 + 1 + 1; /* Plus '0' at the end of string*/ + subckt_name = (char*)my_malloc(sizeof(char)*subckt_name_str_len); + sprintf(subckt_name, "grid[%d][%d]_", ix, iy); + + /* Specify the head of scan-chain */ + if (SPICE_SRAM_SCAN_CHAIN == sram_spice_orgz_type) { + fprintf(fp, "***** Head of scan-chain *****\n"); + fprintf(fp, "Rgrid[%d][%d]_sc_head grid[%d][%d]_sc_head %s[%d]->in 0\n", + ix, iy, ix, iy, sram_spice_model->prefix, sram_spice_model->cnt); + fprintf(fp, ".global grid[%d][%d]_sc_head \n", + ix, iy); + } + + cur_block_index = 0; + /* check capacity and if this has been mapped */ + for (iz = 0; iz < capacity; iz++) { + /* Comments: Grid [x][y]*/ + fprintf(fp, "***** Grid[%d][%d] type_descriptor: %s[%d] *****\n", ix, iy, grid[ix][iy].type->name, iz); + /* Print a physical logic block with specific configurations*/ + fprint_spice_physical_block(fp, subckt_name, ix, iy, iz, grid[ix][iy].type); + fprintf(fp, "***** END *****\n\n"); + } + + /* Specify the tail of scan-chain */ + if (SPICE_SRAM_SCAN_CHAIN == sram_spice_orgz_type) { + fprintf(fp, "***** Tail of scan-chain *****\n"); + fprintf(fp, "Rgrid[%d][%d]_sc_tail grid[%d][%d]_sc_tail %s[%d]->in 0\n", + ix, iy, ix, iy, sram_spice_model->prefix, sram_spice_model->cnt); + fprintf(fp, ".global grid[%d][%d]_sc_tail \n", + ix, iy); + } + + /* Update the grid_index_high for each spice_model */ + update_spice_models_grid_index_high(ix, iy, arch->spice->num_spice_model, arch->spice->spice_models); + + fprintf(fp, "***** Grid[%d][%d], Capactity: %d *****\n", ix, iy, capacity); + fprintf(fp, "***** Top Protocol *****\n"); + /* Definition */ + fprintf(fp, ".subckt grid[%d][%d] \n", ix, iy); + /* Pins */ + /* Special Care for I/O grid */ + if (IO_TYPE == grid[ix][iy].type) { + fprint_io_grid_pins(fp, ix, iy, 0); + } else { + fprint_grid_pins(fp, ix, iy, 0); + } + /* Local Vdd and GND */ + fprintf(fp, "+ svdd sgnd\n"); + + /* Quote all the sub blocks*/ + for (iz = 0; iz < capacity; iz++) { + fprintf(fp, "Xgrid[%d][%d][%d] \n", ix, iy, iz); + /* Print all the pins */ + /* Special Care for I/O grid */ + if (IO_TYPE == grid[ix][iy].type) { + fprint_io_grid_block_subckt_pins(fp, ix, iy, iz, grid[ix][iy].type); + } else { + fprint_grid_block_subckt_pins(fp, iz, grid[ix][iy].type); + } + /* Check in all the blocks(clustered logic block), there is a match x,y,z*/ + mapped_block = search_mapped_block(ix, iy, iz); + /* Local Vdd and Gnd, subckt name*/ + fprintf(fp, "+ svdd sgnd %s\n", get_grid_phy_block_subckt_name(ix, iy, iz, subckt_name, NULL)); + } + + fprintf(fp, ".eom\n"); + + /* Free */ + my_free(subckt_name); + + return; +} + + + +/* Print the SPICE netlist for a grid blocks */ +void fprint_grid_blocks(FILE* fp, + int ix, + int iy, + t_arch* arch) { + int subckt_name_str_len = 0; + char* subckt_name = NULL; + t_block* mapped_block = NULL; + int iz; + int cur_block_index = 0; + int capacity; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert((!(0 > ix))&&(!(ix > (nx + 1)))); + assert((!(0 > iy))&&(!(iy > (ny + 1)))); + + /* Update the grid_index_low for each spice_model */ + update_spice_models_grid_index_low(ix, iy, arch->spice->num_spice_model, arch->spice->spice_models); + + /* generate_grid_subckt, type_descriptor of each grid defines the capacity, + * for example, each grid may contains more than one top-level pb_types, such as I/O + */ + if ((NULL == grid[ix][iy].type)||(0 != grid[ix][iy].offset)) { + /* Update the grid_index_high for each spice_model */ + update_spice_models_grid_index_high(ix, iy, arch->spice->num_spice_model, arch->spice->spice_models); + return; + } + capacity= grid[ix][iy].type->capacity; + assert(0 < capacity); + + /* Make the sub-circuit name*/ + /* Name format: grid[][]_*/ + subckt_name_str_len = 4 + 1 + strlen(my_itoa(ix)) + 2 + + strlen(my_itoa(iy)) + 1 + 1 + 1; /* Plus '0' at the end of string*/ + subckt_name = (char*)my_malloc(sizeof(char)*subckt_name_str_len); + sprintf(subckt_name, "grid[%d][%d]_", ix, iy); + + /* Specify the head of scan-chain */ + if (SPICE_SRAM_SCAN_CHAIN == sram_spice_orgz_type) { + fprintf(fp, "***** Head of scan-chain *****\n"); + fprintf(fp, "Rgrid[%d][%d]_sc_head grid[%d][%d]_sc_head %s[%d]->in 0\n", + ix, iy, ix, iy, sram_spice_model->prefix, sram_spice_model->cnt); + fprintf(fp, ".global grid[%d][%d]_sc_head \n", + ix, iy); + } + + cur_block_index = 0; + /* check capacity and if this has been mapped */ + for (iz = 0; iz < capacity; iz++) { + /* Check in all the blocks(clustered logic block), there is a match x,y,z*/ + mapped_block = search_mapped_block(ix, iy, iz); + /* Comments: Grid [x][y]*/ + fprintf(fp, "***** Grid[%d][%d] type_descriptor: %s[%d] *****\n", ix, iy, grid[ix][iy].type->name, iz); + if (NULL == mapped_block) { + /* Print a NULL logic block...*/ + fprint_spice_idle_block(fp, subckt_name, ix, iy, iz, grid[ix][iy].type); + } else { + if (iz == mapped_block->z) { + // assert(mapped_block == &(block[grid[ix][iy].blocks[cur_block_index]])); + cur_block_index++; + } + /* Print a logic block with specific configurations*/ + fprint_spice_block(fp, subckt_name, ix, iy, iz, grid[ix][iy].type, mapped_block); + } + fprintf(fp, "***** END *****\n\n"); + } + + /* Specify the tail of scan-chain */ + if (SPICE_SRAM_SCAN_CHAIN == sram_spice_orgz_type) { + fprintf(fp, "***** Tail of scan-chain *****\n"); + fprintf(fp, "Rgrid[%d][%d]_sc_tail grid[%d][%d]_sc_tail %s[%d]->in 0\n", + ix, iy, ix, iy, sram_spice_model->prefix, sram_spice_model->cnt); + fprintf(fp, ".global grid[%d][%d]_sc_tail \n", + ix, iy); + } + + assert(cur_block_index == grid[ix][iy].usage); + + /* Update the grid_index_high for each spice_model */ + update_spice_models_grid_index_high(ix, iy, arch->spice->num_spice_model, arch->spice->spice_models); + + fprintf(fp, "***** Grid[%d][%d], Capactity: %d *****\n", ix, iy, capacity); + fprintf(fp, "***** Top Protocol *****\n"); + /* Definition */ + fprintf(fp, ".subckt grid[%d][%d] \n", ix, iy); + /* Pins */ + /* Special Care for I/O grid */ + if (IO_TYPE == grid[ix][iy].type) { + fprint_io_grid_pins(fp, ix, iy, 0); + } else { + fprint_grid_pins(fp, ix, iy, 0); + } + /* Local Vdd and GND */ + fprintf(fp, "+ svdd sgnd\n"); + + /* Quote all the sub blocks*/ + for (iz = 0; iz < capacity; iz++) { + fprintf(fp, "Xgrid[%d][%d][%d] \n", ix, iy, iz); + /* Print all the pins */ + /* Special Care for I/O grid */ + if (IO_TYPE == grid[ix][iy].type) { + fprint_io_grid_block_subckt_pins(fp, ix, iy, iz, grid[ix][iy].type); + } else { + fprint_grid_block_subckt_pins(fp, iz, grid[ix][iy].type); + } + /* Check in all the blocks(clustered logic block), there is a match x,y,z*/ + mapped_block = search_mapped_block(ix, iy, iz); + /* Local Vdd and Gnd, subckt name*/ + fprintf(fp, "+ svdd sgnd %s\n", get_grid_block_subckt_name(ix, iy, iz, subckt_name, mapped_block)); + } + + fprintf(fp, ".eom\n"); + + /* Free */ + my_free(subckt_name); + + return; +} + + +/* Print all logic blocks SPICE models + * Each logic blocks in the grid that allocated for the FPGA + * will be printed. May have an additional option that only + * output the used logic blocks + */ +void generate_spice_logic_blocks(char* subckt_dir, + t_arch* arch) { + /* Create file names */ + char* sp_name = my_strcat(subckt_dir, logic_block_spice_file_name); + FILE* fp = NULL; + int ix, iy; + + /* Check the grid*/ + if ((0 == nx)||(0 == ny)) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid grid size (nx=%d, ny=%d)!\n", __FILE__, __LINE__, nx, ny); + return; + } + vpr_printf(TIO_MESSAGE_INFO,"Grid size of FPGA: nx=%d ny=%d\n", nx + 1, ny + 1); + assert(NULL != grid); + + /* Create a file*/ + fp = fopen(sp_name, "w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create subckt SPICE netlist %s",__FILE__, __LINE__, sp_name); + exit(1); + } + /* Generate the descriptions*/ + fprint_spice_head(fp,"Logic Blocks in FPGA"); + + /* Print the core logic block one by one + * Note ix=0 and ix = nx + 1 are IO pads. They surround the core logic blocks + */ + vpr_printf(TIO_MESSAGE_INFO,"Generating core grids...\n"); + for (ix = 1; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + /* Ensure this is not a io */ + assert(IO_TYPE != grid[ix][iy].type); + /* Ensure a valid usage */ + assert((0 == grid[ix][iy].usage)||(0 < grid[ix][iy].usage)); + fprint_grid_blocks(fp, ix, iy, arch); + } + } + + vpr_printf(TIO_MESSAGE_INFO,"Generating IO grids...\n"); + /* Print the IO pads */ + /* Left side: x = 0, y = 1 .. ny*/ + ix = 0; + for (iy = 1; iy < (ny + 1); iy++) { + /* Ensure this is a io */ + assert(IO_TYPE == grid[ix][iy].type); + /* TODO: replace with physical block generator */ + fprint_grid_physical_blocks(fp, ix, iy, arch); + } + /* Right side : x = nx + 1, y = 1 .. ny*/ + ix = nx + 1; + for (iy = 1; iy < (ny + 1); iy++) { + /* Ensure this is a io */ + assert(IO_TYPE == grid[ix][iy].type); + /* TODO: replace with physical block generator */ + fprint_grid_physical_blocks(fp, ix, iy, arch); + } + /* Bottom side : x = 1 .. nx + 1, y = 0 */ + iy = 0; + for (ix = 1; ix < (nx + 1); ix++) { + /* Ensure this is a io */ + assert(IO_TYPE == grid[ix][iy].type); + /* TODO: replace with physical block generator */ + fprint_grid_physical_blocks(fp, ix, iy, arch); + } + /* Top side : x = 1 .. nx + 1, y = nx + 1 */ + iy = ny + 1; + for (ix = 1; ix < (nx + 1); ix++) { + /* Ensure this is a io */ + assert(IO_TYPE == grid[ix][iy].type); + /* TODO: replace with physical block generator */ + fprint_grid_physical_blocks(fp, ix, iy, arch); + } + + + /* Close the file */ + fclose(fp); + + /* Free */ + my_free(sp_name); + + return; +} diff --git a/vpr7_rram/vpr/SRC/spice/spice_pbtypes.h b/vpr7_rram/vpr/SRC/spice/spice_pbtypes.h new file mode 100644 index 000000000..0e8737eb8 --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_pbtypes.h @@ -0,0 +1,110 @@ + +void fprint_pb_type_ports(FILE* fp, + char* port_prefix, + int use_global_clock, + t_pb_type* cur_pb_type); + +void fprint_spice_dangling_des_pb_graph_pin_interc(FILE* fp, + t_pb_graph_pin* des_pb_graph_pin, + t_mode* cur_mode, + enum e_pin2pin_interc_type pin2pin_interc_type, + char* parent_pin_prefix); + +void generate_spice_src_des_pb_graph_pin_prefix(t_pb_graph_node* src_pb_graph_node, + t_pb_graph_node* des_pb_graph_node, + enum e_pin2pin_interc_type pin2pin_interc_type, + t_interconnect* pin2pin_interc, + char* parent_pin_prefix, + char** src_pin_prefix, + char** des_pin_prefix); + +void find_interc_fan_in_des_pb_graph_pin(t_pb_graph_pin* des_pb_graph_pin, + t_mode* cur_mode, + t_interconnect** cur_interc, + int* fan_in); + +void fprintf_spice_pb_graph_pin_interc(FILE* fp, + char* parent_pin_prefix, + enum e_pin2pin_interc_type pin2pin_interc_type, + t_pb_graph_pin* des_pb_graph_pin, + t_mode* cur_mode, + int is_idle); + +void fprint_spice_pb_graph_interc(FILE* fp, + char* pin_prefix, + t_pb_graph_node* cur_pb_graph_node, + int select_mode_index, + int is_idle); + +void fprint_spice_pb_graph_primitive_node(FILE* fp, + char* subckt_prefix, + t_pb* cur_pb, + t_pb_graph_node* cur_pb_graph_node, + int pb_type_index); + +void fprint_pb_primitive_spice_model(FILE* fp, + char* subckt_prefix, + t_pb* prim_pb, + t_pb_graph_node* prim_pb_graph_node, + int pb_index, + t_spice_model* spice_model, + int is_idle); + +void fprint_spice_idle_pb_graph_node_rec(FILE* fp, + char* subckt_prefix, + t_pb_graph_node* cur_pb_graph_node, + int pb_type_index); + +void fprint_spice_pb_graph_node_rec(FILE* fp, + char* subckt_prefix, + t_pb* cur_pb, + t_pb_graph_node* cur_pb_graph_node, + int pb_type_index); + + +void fprint_spice_block(FILE* fp, + char* subckt_name, + int x, + int y, + int z, + t_type_ptr type_descriptor, + t_block* mapped_block); + +void fprint_grid_pins(FILE* fp, + int x, + int y, + int top_level); + +void fprint_io_grid_pins(FILE* fp, + int x, + int y, + int top_level); + +char* get_grid_block_subckt_name(int x, + int y, + int z, + char* subckt_prefix, + t_block* mapped_block); + +void fprint_grid_block_subckt_pins(FILE* fp, + int z, + t_type_ptr type_descriptor); + +void fprint_io_grid_block_subckt_pins(FILE* fp, + int x, + int y, + int z, + t_type_ptr type_descriptor); + +void fprint_grid_blocks(FILE* fp, + int ix, + int iy); + +void fprint_spice_idle_block(FILE* fp, + char* subckt_name, + int x, + int y, + int z, + t_type_ptr type_descriptor); + +void generate_spice_logic_blocks(char* subckt_dir, t_arch* arch); diff --git a/vpr7_rram/vpr/SRC/spice/spice_primitives.c b/vpr7_rram/vpr/SRC/spice/spice_primitives.c new file mode 100644 index 000000000..7128e8931 --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_primitives.c @@ -0,0 +1,469 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph.h" +#include "rr_graph_swseg.h" +#include "vpr_utils.h" + +/* Include spice support headers*/ +#include "linkedlist.h" +#include "fpga_spice_globals.h" +#include "spice_globals.h" +#include "fpga_spice_utils.h" +#include "spice_utils.h" +#include "spice_pbtypes.h" +#include "spice_primitives.h" + +enum e_ff_trigger_type { + FF_RE, FF_FE +}; + +/* Subroutines */ +void fprint_pb_primitive_ff(FILE* fp, + char* subckt_prefix, + t_logical_block* mapped_logical_block, + t_pb_graph_node* prim_pb_graph_node, + int index, + t_spice_model* spice_model) { + int i; + /* Default FF settings, applied when this FF is idle*/ + enum e_ff_trigger_type trigger_type = FF_RE; + int init_val = 0; + + int num_input_port = 0; + t_spice_model_port** input_ports = NULL; + int num_output_port = 0; + t_spice_model_port** output_ports = NULL; + int num_clock_port = 0; + t_spice_model_port** clock_ports = NULL; + + int iport, ipin; + int num_pb_type_output_port = 0; + t_port** pb_type_output_ports = NULL; + + char* formatted_subckt_prefix = format_spice_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/ + t_pb_type* prim_pb_type = NULL; + char* port_prefix = NULL; + + /* Ensure a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Ensure a valid pb_graph_node */ + if (NULL == prim_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid prim_pb_graph_node!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Find ports*/ + input_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, FALSE); + output_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + clock_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_CLOCK, &num_clock_port, FALSE); + + /* Asserts */ + assert(3 == num_input_port); /* D, Set and Reset*/ + for (i = 0; i < num_input_port; i++) { + assert(1 == input_ports[i]->size); + } + assert(1 == num_output_port); + assert(1 == output_ports[0]->size); + assert(1 == num_clock_port); + assert(1 == clock_ports[0]->size); + + assert(SPICE_MODEL_FF == spice_model->type); + + /* Initialize */ + prim_pb_type = prim_pb_graph_node->pb_type; + + if (NULL != mapped_logical_block) { + fprintf(fp, "***** Logical block mapped to this FF: %s *****\n", + mapped_logical_block->name); + } + + /* Generate Subckt for pb_type*/ + /* + port_prefix = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(prim_pb_type->name) + 1 + + strlen(my_itoa(index)) + 1 + 1)); + sprintf(port_prefix, "%s%s[%d]", formatted_subckt_prefix, prim_pb_type->name, index); + */ + /* Simplify the port prefix, make SPICE netlist readable */ + port_prefix = (char*)my_malloc(sizeof(char)* + (strlen(prim_pb_type->name) + 1 + + strlen(my_itoa(index)) + 1 + 1)); + sprintf(port_prefix, "%s[%d]", prim_pb_type->name, index); + /* Definition line */ + fprintf(fp, ".subckt %s%s ", formatted_subckt_prefix, port_prefix); + /* print ports*/ + fprint_pb_type_ports(fp, port_prefix, 0, prim_pb_type); + /* Local vdd and gnd*/ + fprintf(fp, "svdd sgnd\n"); + /* Definition ends*/ + + /* Call the dff subckt*/ + fprintf(fp, "X%s[%d] ", spice_model->prefix, spice_model->cnt); + /* Global ports */ + if (0 < rec_fprint_spice_model_global_ports(fp, spice_model, FALSE)) { + fprintf(fp, "+ "); + } + /* print ports*/ + fprint_pb_type_ports(fp, port_prefix, 0, prim_pb_type); /* Use global clock for each DFF...*/ + /* Local vdd and gnd, spice_model name + * global vdd for ff + */ + fprintf(fp, "%s_%s[%d] sgnd %s\n", + spice_tb_global_vdd_port_name, + spice_model->prefix, + spice_model->cnt, + spice_model->name); + + /* Apply rising edge, and init value to the ff*/ + if (NULL != mapped_logical_block) { + /* Consider the rising edge|falling edge */ + if (0 == strcmp("re", mapped_logical_block->trigger_type)) { + trigger_type = FF_RE; + } else if (0 == strcmp("fe", mapped_logical_block->trigger_type)) { + trigger_type = FF_FE; + } else { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid ff trigger type! Should be [re|fe].\n", + __FILE__, __LINE__); + exit(1); + } + /* Assign initial value */ + if (1 == mapped_logical_block->init_val) { + init_val = 1; + } else { + init_val = 0; + } + + /* Back-annotate to logical block */ + mapped_logical_block->mapped_spice_model = spice_model; + mapped_logical_block->mapped_spice_model_index = spice_model->cnt; + } else { + trigger_type = FF_RE; + init_val = 0; + } + /* TODO: apply falling edge, initial value to FF!!!*/ + /*fprintf(fp, "\n");*/ + + /* Add nodeset */ + pb_type_output_ports = find_pb_type_ports_match_spice_model_port_type(prim_pb_type, SPICE_MODEL_PORT_OUTPUT, &num_pb_type_output_port); + for (iport = 0; iport < num_pb_type_output_port; iport++) { + for (ipin = 0; ipin < pb_type_output_ports[iport]->num_pins; ipin++) { + fprintf(fp, ".nodeset V(%s->%s[%d]) ", port_prefix, pb_type_output_ports[iport]->name, ipin); + if (0 == init_val) { + fprintf(fp, "0\n"); + } else { + assert(1 == init_val); + fprintf(fp, "vsp\n"); + } + } + } + + /* End */ + fprintf(fp, ".eom\n"); + + spice_model->cnt++; + + /*Free*/ + my_free(formatted_subckt_prefix); + my_free(port_prefix); + + return; +} + +/* Print hardlogic SPICE subckt*/ +void fprint_pb_primitive_hardlogic(FILE* fp, + char* subckt_prefix, + t_logical_block* mapped_logical_block, + t_pb_graph_node* prim_pb_graph_node, + int index, + t_spice_model* spice_model) { + int num_input_port = 0; + t_spice_model_port** input_ports = NULL; + int num_output_port = 0; + t_spice_model_port** output_ports = NULL; + int num_clock_port = 0; + t_spice_model_port** clock_ports = NULL; + + char* formatted_subckt_prefix = format_spice_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/ + t_pb_type* prim_pb_type = NULL; + char* port_prefix = NULL; + + /* Ensure a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Ensure a valid pb_graph_node */ + if (NULL == prim_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid prim_pb_graph_node!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Find ports*/ + input_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + output_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + clock_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_CLOCK, &num_clock_port, TRUE); + + /* Asserts */ + assert(SPICE_MODEL_HARDLOGIC == spice_model->type); + + /* Initialize */ + prim_pb_type = prim_pb_graph_node->pb_type; + + if (NULL != mapped_logical_block) { + fprintf(fp, "***** Logical block mapped to this hardlogic: %s *****\n", + mapped_logical_block->name); + } + + + /* Generate Subckt for pb_type*/ + /* + port_prefix = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(prim_pb_type->name) + 1 + + strlen(my_itoa(index)) + 1 + 1)); + sprintf(port_prefix, "%s%s[%d]", formatted_subckt_prefix, prim_pb_type->name, index); + */ + /* Simplify the port prefix, make SPICE netlist readable */ + port_prefix = (char*)my_malloc(sizeof(char)* + (strlen(prim_pb_type->name) + 1 + + strlen(my_itoa(index)) + 1 + 1)); + sprintf(port_prefix, "%s[%d]", prim_pb_type->name, index); + /* Definition line */ + fprintf(fp, ".subckt %s%s ", formatted_subckt_prefix, port_prefix); + /* print ports*/ + fprint_pb_type_ports(fp, port_prefix, 0, prim_pb_type); + /* Local vdd and gnd*/ + fprintf(fp, "svdd sgnd\n"); + /* Definition ends*/ + + /* Back-annotate to logical block */ + if (NULL != mapped_logical_block) { + mapped_logical_block->mapped_spice_model = spice_model; + mapped_logical_block->mapped_spice_model_index = spice_model->cnt; + } + + /* Call the dff subckt*/ + fprintf(fp, "X%s[%d] ", spice_model->prefix, spice_model->cnt); + /* print ports*/ + fprint_pb_type_ports(fp, port_prefix, 0, prim_pb_type); + /* Local vdd and gnd, spice_model name, + * Global vdd for hardlogic to split + */ + fprintf(fp, "gvdd_%s[%d] sgnd %s\n", spice_model->prefix, spice_model->cnt, spice_model->name); + + /* End */ + fprintf(fp, ".eom\n"); + + spice_model->cnt++; + + /*Free*/ + free(formatted_subckt_prefix); + free(port_prefix); + + return; +} + +void fprint_pb_primitive_io(FILE* fp, + char* subckt_prefix, + t_logical_block* mapped_logical_block, + t_pb_graph_node* prim_pb_graph_node, + int index, + t_spice_model* spice_model) { + int num_pad_port = 0; /* INOUT port */ + t_spice_model_port** pad_ports = NULL; + int num_input_port = 0; + t_spice_model_port** input_ports = NULL; + int num_output_port = 0; + t_spice_model_port** output_ports = NULL; + int num_clock_port = 0; + t_spice_model_port** clock_ports = NULL; + int num_sram_port = 0; + t_spice_model_port** sram_ports = NULL; + + int i; + int num_sram = 0; + int expected_num_sram = 0; + int* sram_bits = NULL; + int cur_num_sram = 0; + t_spice_model* mem_model = NULL; + + char* formatted_subckt_prefix = format_spice_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/ + t_pb_type* prim_pb_type = NULL; + char* port_prefix = NULL; + char* sram_vdd_port_name = NULL; + + /* Ensure a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Ensure a valid pb_graph_node */ + if (NULL == prim_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid prim_pb_graph_node!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Find ports*/ + pad_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_INOUT, &num_pad_port, TRUE); + input_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + output_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + clock_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_CLOCK, &num_clock_port, TRUE); + sram_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); + + /* Asserts */ + assert(SPICE_MODEL_IOPAD == spice_model->type); + + /* Initialize */ + + prim_pb_type = prim_pb_graph_node->pb_type; + + if (NULL != mapped_logical_block) { + fprintf(fp, "***** Logical block mapped to this IO: %s *****\n", + mapped_logical_block->name); + } + + /* Generate Subckt for pb_type*/ + /* + port_prefix = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(prim_pb_type->name) + 1 + + strlen(my_itoa(index)) + 1 + 1)); + sprintf(port_prefix, "%s%s[%d]", formatted_subckt_prefix, prim_pb_type->name, index); + */ + /* Simplify the port prefix, make SPICE netlist readable */ + port_prefix = (char*)my_malloc(sizeof(char)* + (strlen(prim_pb_type->name) + 1 + + strlen(my_itoa(index)) + 1 + 1)); + sprintf(port_prefix, "%s[%d]", prim_pb_type->name, index); + + /* Decode SRAM bits */ + assert((1 == num_sram_port)&&(NULL != sram_ports)&&(1 == sram_ports[0]->size)); + num_sram = count_num_sram_bits_one_spice_model(spice_model, -1); + /* what is the SRAM bit of a mode? */ + /* If logical block is not NULL, we need to decode the sram bit */ + if (NULL != mapped_logical_block) { + assert(NULL != mapped_logical_block->pb->pb_graph_node->pb_type->mode_bits); + sram_bits = decode_mode_bits(mapped_logical_block->pb->pb_graph_node->pb_type->mode_bits, &expected_num_sram); + assert(expected_num_sram == num_sram); + } else { + /* Initialize */ + sram_bits = (int*)my_calloc(num_sram, sizeof(int)); + for (i = 0; i < num_sram; i++) { + sram_bits[i] = sram_ports[0]->default_val; + } + } + + /* Get current counter of mem_bits, bl and wl */ + cur_num_sram = get_sram_orgz_info_num_mem_bit(sram_spice_orgz_info); + + /* Definition line */ + fprintf(fp, ".subckt %s%s ", formatted_subckt_prefix, port_prefix); + /* print ports*/ + fprint_pb_type_ports(fp, port_prefix, 0, prim_pb_type); + /* Local vdd and gnd*/ + fprintf(fp, "svdd sgnd\n"); + /* Definition ends*/ + + /* Call the iopad subckt*/ + fprintf(fp, "X%s[%d] ", spice_model->prefix, spice_model->cnt); + /* Only dump the global ports belonging to a spice_model + * Do not go recursive, we can freely define global ports anywhere in SPICE netlist + */ + if (0 < rec_fprint_spice_model_global_ports(fp, spice_model, FALSE)) { + fprintf(fp, "+ "); + } + /* print regular ports*/ + fprint_pb_type_ports(fp, port_prefix, 0, prim_pb_type); + /* Print inout port */ + fprintf(fp, " %s%s[%d] ", + gio_inout_prefix, + spice_model->prefix, + spice_model->cnt); + /* Print SRAM ports */ + for (i = 0; i < num_sram; i++) { + fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, cur_num_sram + i, sram_bits[i]); + /* We need the invertered signal for better convergency */ + fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, cur_num_sram + i, 1 - sram_bits[i]); + } + + /* Local vdd and gnd, spice_model name, + * TODO: Global vdd for i/o pad to split? + */ + fprintf(fp, "%s_%s[%d] sgnd %s\n", + spice_tb_global_vdd_port_name, + spice_model->prefix, + spice_model->cnt, + spice_model->name); + + /* Print the encoding in SPICE netlist for debugging */ + fprintf(fp, "***** SRAM bits for IOPAD[%d] *****\n", + spice_model->cnt); + fprintf(fp, "*****"); + for (i = 0; i < num_sram; i++) { + fprintf(fp, "%d", sram_bits[i]); + } + fprintf(fp, "*****\n"); + + /* Call SRAM subckts*/ + /* Give the VDD port name for SRAMs */ + sram_vdd_port_name = (char*)my_malloc(sizeof(char)* + (strlen(spice_tb_global_vdd_io_sram_port_name) + + 1 )); + sprintf(sram_vdd_port_name, "%s", + spice_tb_global_vdd_io_sram_port_name); + /* Now Print SRAMs one by one */ + for (i = 0; i < num_sram; i++) { + fprint_spice_one_sram_subckt(fp, sram_spice_orgz_info, spice_model, sram_vdd_port_name); + } + + /* Store the configuraion bit to linked-list */ + add_sram_conf_bits_to_llist(sram_spice_orgz_info, cur_num_sram, + num_sram, sram_bits); + + /* End */ + fprintf(fp, ".eom\n"); + + /* Back-annotate to logical block */ + if (NULL != mapped_logical_block) { + mapped_logical_block->mapped_spice_model = spice_model; + mapped_logical_block->mapped_spice_model_index = spice_model->cnt; + } + + /* Update the spice_model counter */ + spice_model->cnt++; + + /*Free*/ + my_free(formatted_subckt_prefix); + my_free(port_prefix); + my_free(sram_vdd_port_name); + + return; +} + + diff --git a/vpr7_rram/vpr/SRC/spice/spice_primitives.h b/vpr7_rram/vpr/SRC/spice/spice_primitives.h new file mode 100644 index 000000000..e923fe18b --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_primitives.h @@ -0,0 +1,22 @@ + +void fprint_pb_primitive_ff(FILE* fp, + char* subckt_prefix, + t_logical_block* mapped_logical_block, + t_pb_graph_node* prim_pb_graph_node, + int index, + t_spice_model* spice_model); + + +void fprint_pb_primitive_hardlogic(FILE* fp, + char* subckt_prefix, + t_logical_block* mapped_logical_block, + t_pb_graph_node* prim_pb_graph_node, + int index, + t_spice_model* spice_model); + +void fprint_pb_primitive_io(FILE* fp, + char* subckt_prefix, + t_logical_block* mapped_logical_block, + t_pb_graph_node* prim_pb_graph_node, + int index, + t_spice_model* spice_model); diff --git a/vpr7_rram/vpr/SRC/spice/spice_routing.c b/vpr7_rram/vpr/SRC/spice/spice_routing.c new file mode 100644 index 000000000..40b4080f4 --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_routing.c @@ -0,0 +1,1260 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph_util.h" +#include "rr_graph.h" +#include "rr_graph2.h" +#include "vpr_utils.h" + +/* Include SPICE support headers*/ +#include "linkedlist.h" +#include "fpga_spice_globals.h" +#include "spice_globals.h" +#include "fpga_spice_utils.h" +#include "spice_utils.h" +#include "spice_mux.h" +#include "spice_lut.h" +#include "spice_primitives.h" +#include "fpga_spice_backannotate_utils.h" +#include "spice_routing.h" + + +void fprint_routing_chan_subckt(FILE* fp, + int x, int y, t_rr_type chan_type, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices, + int num_segment, t_segment_inf* segments) { + int itrack, iseg, cost_index; + char* chan_prefix = NULL; + int chan_width = 0; + t_rr_node** chan_rr_nodes = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + assert((CHANX == chan_type)||(CHANY == chan_type)); + + /* Initial chan_prefix*/ + switch (chan_type) { + case CHANX: + chan_prefix = "chanx"; + fprintf(fp, "***** Subckt for Channel X [%d][%d] *****\n", x, y); + break; + case CHANY: + chan_prefix = "chany"; + fprintf(fp, "***** Subckt for Channel Y [%d][%d] *****\n", x, y); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid Channel type! Should be CHANX or CHANY.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Collect rr_nodes for Tracks for chanx[ix][iy] */ + chan_rr_nodes = get_chan_rr_nodes(&chan_width, chan_type, x, y, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + + /* Chan subckt definition */ + fprintf(fp, ".subckt %s[%d][%d] \n", chan_prefix, x, y); + /* Inputs and outputs, + * Rules for CHANX: + * print left-hand ports(in) first, then right-hand ports(out) + * Rules for CHANX: + * print bottom ports(in) first, then top ports(out) + */ + fprintf(fp, "+ "); + /* LEFT/BOTTOM side port of CHANX/CHANY */ + for (itrack = 0; itrack < chan_width; itrack++) { + switch (chan_rr_nodes[itrack]->direction) { + case INC_DIRECTION: + fprintf(fp, "in%d ", itrack); /* INC_DIRECTION: input on the left/bottom side */ + break; + case DEC_DIRECTION: + fprintf(fp, "out%d ", itrack); /* DEC_DIRECTION: output on the left/bottom side*/ + break; + case BI_DIRECTION: + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of %s[%d][%d]_track[%d]!\n", + __FILE__, __LINE__, chan_prefix, x, y, itrack); + exit(1); + } + } + fprintf(fp, "\n"); + fprintf(fp, "+ "); + /* RIGHT/TOP side port of CHANX/CHANY */ + for (itrack = 0; itrack < chan_width; itrack++) { + switch (chan_rr_nodes[itrack]->direction) { + case INC_DIRECTION: + fprintf(fp, "out%d ", itrack); /* INC_DIRECTION: output on the right/top side*/ + break; + case DEC_DIRECTION: + fprintf(fp, "in%d ", itrack); /* DEC_DIRECTION: input on the right/top side */ + break; + case BI_DIRECTION: + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of rr_node %s[%d][%d]_track[%d]!\n", + __FILE__, __LINE__, chan_prefix, x, y, itrack); + exit(1); + } + } + fprintf(fp, "\n"); + fprintf(fp, "+ "); + /* Middle point output for connection box inputs */ + for (itrack = 0; itrack < chan_width; itrack++) { + fprintf(fp, "mid_out%d ", itrack); + } + fprintf(fp, "\n"); + /* End with svdd and sgnd */ + fprintf(fp, "+ svdd sgnd\n"); + + /* Print segments models*/ + for (itrack = 0; itrack < chan_width; itrack++) { + cost_index = chan_rr_nodes[itrack]->cost_index; + iseg = rr_indexed_data[cost_index].seg_index; + /* Check */ + assert((!(iseg < 0))&&(iseg < num_segment)); + assert(NULL != segments[iseg].spice_model); + assert(SPICE_MODEL_CHAN_WIRE == segments[iseg].spice_model->type); + fprintf(fp, "X%s[%d] ", segments[iseg].spice_model->prefix, segments[iseg].spice_model->cnt); /*Call subckt*/ + /* Update counter of SPICE model*/ + segments[iseg].spice_model->cnt++; + /* Inputs and ouputs*/ + fprintf(fp, "in%d out%d mid_out%d ", itrack, itrack, itrack); + /* End with svdd, sgnd and Subckt name*/ + fprintf(fp, "svdd sgnd %s_seg%d\n", segments[iseg].spice_model->name, iseg); + } + + fprintf(fp, ".eom\n"); + + /* Free */ + my_free(chan_rr_nodes); + + return; +} + +void fprint_grid_side_pin_with_given_index(FILE* fp, + int pin_index, int side, + int x, int y) { + int height, class_id; + t_type_ptr type = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + type = grid[x][y].type; + assert(NULL != type); + + assert((!(0 > pin_index))&&(pin_index < type->num_pins)); + assert((!(0 > side))&&(!(side > 3))); + + /* Output the pins on the side*/ + height = grid[x][y].offset; + class_id = type->pin_class[pin_index]; + if ((1 == type->pinloc[height][side][pin_index])) { + /* Not sure if we need to plus a height */ + /* fprintf(fp, "grid[%d][%d]_pin[%d][%d][%d] ", x, y, height, side, pin_index); */ + fprintf(fp, "grid[%d][%d]_pin[%d][%d][%d] ", x, y + height, height, side, pin_index); + } else { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Fail to print a grid pin (x=%d, y=%d, height=%d, side=%d, index=%d)", + __FILE__, __LINE__, x, y, height, side, pin_index); + exit(1); + } + + return; +} + +void fprint_grid_side_pins(FILE* fp, + t_rr_type pin_type, + int x, + int y, + int side) { + int height, ipin, class_id; + t_type_ptr type = NULL; + enum e_pin_type pin_class_type; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + type = grid[x][y].type; + assert(NULL != type); + + /* Assign the type of PIN*/ + switch (pin_type) { + case IPIN: + /* case SINK: */ + pin_class_type = RECEIVER; /* This is the end of a route path*/ + break; + /* case SOURCE: */ + case OPIN: + pin_class_type = DRIVER; /* This is the start of a route path */ + break; + /* SINK and SOURCE are hypothesis nodes */ + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid pin_type!\n", __FILE__, __LINE__); + exit(1); + } + + /* Output the pins on the side*/ + height = grid[x][y].offset; + for (ipin = 0; ipin < type->num_pins; ipin++) { + class_id = type->pin_class[ipin]; + if ((1 == type->pinloc[height][side][ipin])&&(pin_class_type == type->class_inf[class_id].type)) { + /* Not sure if we need to plus a height */ + fprintf(fp, "grid[%d][%d]_pin[%d][%d][%d] ", x, y + height, height, side, ipin); + } + } + + return; +} + +void fprint_switch_box_chan_port(FILE* fp, + t_sb cur_sb_info, + int chan_side, + t_rr_node* cur_rr_node, + enum PORTS cur_rr_node_direction) { + int index = -1; + t_rr_type chan_rr_node_type; + int chan_rr_node_x, chan_rr_node_y; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Get the index in sb_info of cur_rr_node */ + index = get_rr_node_index_in_sb_info(cur_rr_node, cur_sb_info, chan_side, cur_rr_node_direction); + /* Make sure this node is included in this sb_info */ + assert((-1 != index)&&(-1 != chan_side)); + + get_chan_rr_node_coorindate_in_sb_info(cur_sb_info, chan_side, + &chan_rr_node_type, &chan_rr_node_x, &chan_rr_node_y); + + assert(cur_rr_node->type == chan_rr_node_type); + + fprintf(fp, "%s[%d][%d]_%s[%d] ", + convert_chan_type_to_string(chan_rr_node_type), + chan_rr_node_x, chan_rr_node_y, + convert_chan_rr_node_direction_to_string(cur_sb_info.chan_rr_node_direction[chan_side][index]), + cur_rr_node->ptc_num); + + return; +} + +/* Print a short interconneciton in switch box + * There are two cases should be noticed. + * 1. The actual fan-in of cur_rr_node is 0. In this case, + the cur_rr_node need to be short connected to itself which is on the opposite side of this switch + * 2. The actual fan-in of cur_rr_node is 0. In this case, + * The cur_rr_node need to connected to the drive_rr_node + */ +void fprint_switch_box_short_interc(FILE* fp, + t_sb cur_sb_info, + int chan_side, + t_rr_node* cur_rr_node, + int actual_fan_in, + t_rr_node* drive_rr_node) { + int side, index; + int grid_x, grid_y, height; + char* chan_name = NULL; + char* des_chan_port_name = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > cur_sb_info.x))&&(!(cur_sb_info.x > (nx + 1)))); + assert((!(0 > cur_sb_info.y))&&(!(cur_sb_info.y > (ny + 1)))); + assert((0 == actual_fan_in)||(1 == actual_fan_in)); + + chan_name = convert_chan_type_to_string(cur_rr_node->type); + + /* Get the index in sb_info of cur_rr_node */ + index = get_rr_node_index_in_sb_info(cur_rr_node, cur_sb_info, chan_side, OUT_PORT); + des_chan_port_name = "out"; + + fprintf(fp, "R%s[%d][%d]_%s[%d] ", + chan_name, cur_sb_info.x, cur_sb_info.y, des_chan_port_name, cur_rr_node->ptc_num); + + /* Check the driver*/ + if (0 == actual_fan_in) { + assert(drive_rr_node == cur_rr_node); + } else { + /* drive_rr_node = &(rr_node[cur_rr_node->prev_node]); */ + assert(1 == rr_node_drive_switch_box(drive_rr_node, cur_rr_node, cur_sb_info.x, cur_sb_info.y, chan_side)); + } + switch (drive_rr_node->type) { + /* case SOURCE: */ + case OPIN: + /* Indicate a CLB Outpin*/ + /* Search all the sides of a SB, see this drive_rr_node is an INPUT of this SB */ + get_rr_node_side_and_index_in_sb_info(drive_rr_node, cur_sb_info, IN_PORT, &side, &index); + /* We need to be sure that drive_rr_node is part of the SB */ + assert((-1 != index)&&(-1 != side)); + /* Find grid_x and grid_y */ + grid_x = drive_rr_node->xlow; + grid_y = drive_rr_node->ylow; /*Plus the offset in function fprint_grid_side_pin_with_given_index */ + height = grid[grid_x][grid_y].offset; + /* Print a grid pin */ + fprint_grid_side_pin_with_given_index(fp, drive_rr_node->ptc_num, + cur_sb_info.opin_rr_node_grid_side[side][index], + grid_x, grid_y); + break; + case CHANX: + case CHANY: + /* Should be an input */ + get_rr_node_side_and_index_in_sb_info(drive_rr_node, cur_sb_info, IN_PORT, &side, &index); + /* We need to be sure that drive_rr_node is part of the SB */ + assert((-1 != index)&&(-1 != side)); + fprint_switch_box_chan_port(fp, cur_sb_info, side, drive_rr_node, IN_PORT); + break; + default: /* IPIN, SINK are invalid*/ + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", + __FILE__, __LINE__); + exit(1); + } + + /* Output port */ + /* fprint_switch_box_chan_port(fp, switch_box_x, switch_box_y, chan_side, cur_rr_node); */ + fprint_switch_box_chan_port(fp, cur_sb_info, chan_side, cur_rr_node, OUT_PORT); + + /* END */ + fprintf(fp, "0\n"); + + return; +} + +/* Print the SPICE netlist of multiplexer that drive this rr_node */ +void fprint_switch_box_mux(FILE* fp, + t_sb cur_sb_info, + int chan_side, + t_rr_node* cur_rr_node, + int mux_size, + t_rr_node** drive_rr_nodes, + int switch_index) { + int inode, side, index; + int grid_x, grid_y, height; + t_spice_model* spice_model = NULL; + int mux_level, path_id, cur_num_sram, ilevel; + int num_mux_sram_bits = 0; + int* mux_sram_bits = NULL; + char* sram_vdd_port_name = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > cur_sb_info.x))&&(!(cur_sb_info.x > (nx + 1)))); + assert((!(0 > cur_sb_info.y))&&(!(cur_sb_info.y > (ny + 1)))); + + /* Check current rr_node is CHANX or CHANY*/ + assert((CHANX == cur_rr_node->type)||(CHANY == cur_rr_node->type)); + + /* Allocate drive_rr_nodes according to the fan-in*/ + assert((2 == mux_size)||(2 < mux_size)); + + /* Get spice model*/ + spice_model = switch_inf[switch_index].spice_model; + /* Now it is the time print the SPICE netlist of MUX*/ + fprintf(fp, "X%s_size%d[%d] ", spice_model->prefix, mux_size, spice_model->cnt); + /* Global ports */ + if (0 < rec_fprint_spice_model_global_ports(fp, spice_model, FALSE)) { + fprintf(fp, "+ "); + } + /* Input ports*/ + for (inode = 0; inode < mux_size; inode++) { + switch (drive_rr_nodes[inode]->type) { + /* case SOURCE: */ + case OPIN: + /* Indicate a CLB Outpin*/ + /* Search all the sides of a SB, see this drive_rr_node is an INPUT of this SB */ + get_rr_node_side_and_index_in_sb_info(drive_rr_nodes[inode], cur_sb_info, IN_PORT, &side, &index); + /* We need to be sure that drive_rr_node is part of the SB */ + assert((-1 != index)&&(-1 != side)); + /* Find grid_x and grid_y */ + grid_x = drive_rr_nodes[inode]->xlow; + grid_y = drive_rr_nodes[inode]->ylow; /*Plus the offset in function fprint_grid_side_pin_with_given_index */ + height = grid[grid_x][grid_y].offset; + /* Print a grid pin */ + fprint_grid_side_pin_with_given_index(fp, drive_rr_nodes[inode]->ptc_num, + cur_sb_info.opin_rr_node_grid_side[side][index], + grid_x, grid_y); + break; + case CHANX: + case CHANY: + /* Should be an input ! */ + get_rr_node_side_and_index_in_sb_info(drive_rr_nodes[inode], cur_sb_info, IN_PORT, &side, &index); + /* We need to be sure that drive_rr_node is part of the SB */ + assert((-1 != index)&&(-1 != side)); + fprint_switch_box_chan_port(fp, cur_sb_info, side, drive_rr_nodes[inode], IN_PORT); + break; + default: /* IPIN, SINK are invalid*/ + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", + __FILE__, __LINE__); + exit(1); + } + } + + /* Output port */ + fprint_switch_box_chan_port(fp, cur_sb_info, chan_side, cur_rr_node, OUT_PORT); + + /* Configuration bits for this MUX*/ + path_id = -1; + for (inode = 0; inode < mux_size; inode++) { + if (drive_rr_nodes[inode] == &(rr_node[cur_rr_node->prev_node])) { + path_id = inode; + break; + } + } + + if (!((-1 != path_id)&&(path_id < mux_size))) { + assert((-1 != path_id)&&(path_id < mux_size)); + } + + switch (spice_model->design_tech_info.structure) { + case SPICE_MODEL_STRUCTURE_TREE: + mux_level = determine_tree_mux_level(mux_size); + num_mux_sram_bits = mux_level; + mux_sram_bits = decode_tree_mux_sram_bits(mux_size, mux_level, path_id); + break; + case SPICE_MODEL_STRUCTURE_ONELEVEL: + mux_level = 1; + /* Special for 2-input MUX */ + if (2 == mux_size) { + num_mux_sram_bits = 1; + mux_sram_bits = decode_tree_mux_sram_bits(mux_size, mux_level, path_id); + } else { + num_mux_sram_bits = mux_size; + mux_sram_bits = decode_onelevel_mux_sram_bits(mux_size, mux_level, path_id); + } + break; + case SPICE_MODEL_STRUCTURE_MULTILEVEL: + /* Take care of corner case: MUX size = 2 */ + if (2 == mux_size) { + mux_level = 1; + num_mux_sram_bits = 1; + mux_sram_bits = decode_tree_mux_sram_bits(mux_size, 1, path_id); + } else { + mux_level = spice_model->design_tech_info.mux_num_level; + num_mux_sram_bits = determine_num_input_basis_multilevel_mux(mux_size, mux_level) * mux_level; + mux_sram_bits = decode_multilevel_mux_sram_bits(mux_size, mux_level, path_id); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n", + __FILE__, __LINE__, spice_model->name); + exit(1); + } + /* Print SRAMs that configure this MUX */ + /* Get current counter of mem_bits, bl and wl */ + cur_num_sram = get_sram_orgz_info_num_mem_bit(sram_spice_orgz_info); + for (ilevel = 0; ilevel < num_mux_sram_bits; ilevel++) { + assert( (0 == mux_sram_bits[ilevel]) || (1 == mux_sram_bits[ilevel]) ); + fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, + cur_num_sram + ilevel, mux_sram_bits[ilevel]); + fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, + cur_num_sram + ilevel, 1 - mux_sram_bits[ilevel]); + } + + /* End with svdd and sgnd, subckt name*/ + fprintf(fp, "svdd sgnd %s_size%d\n", spice_model->name, mux_size); + + /* Print the encoding in SPICE netlist for debugging */ + fprintf(fp, "***** SRAM bits for MUX[%d], level=%d, select_path_id=%d. *****\n", + spice_model->cnt, mux_level, path_id); + fprintf(fp, "*****"); + for (ilevel = 0; ilevel < num_mux_sram_bits; ilevel++) { + fprintf(fp, "%d", mux_sram_bits[ilevel]); + } + fprintf(fp, "*****\n"); + + /* Call SRAM subckts*/ + /* Give the VDD port name for SRAMs */ + sram_vdd_port_name = (char*)my_malloc(sizeof(char)* + (strlen(spice_tb_global_vdd_sb_sram_port_name) + + 1 )); + sprintf(sram_vdd_port_name, "%s", + spice_tb_global_vdd_sb_sram_port_name); + /* Now Print SRAMs one by one */ + for (ilevel = 0; ilevel < num_mux_sram_bits; ilevel++) { + fprint_spice_one_sram_subckt(fp, sram_spice_orgz_info, + spice_model, sram_vdd_port_name); + } + + /* Store the configuraion bit to linked-list */ + add_sram_conf_bits_to_llist(sram_spice_orgz_info, cur_num_sram, + num_mux_sram_bits, mux_sram_bits); + + /* Update spice_model counter */ + spice_model->cnt++; + + /* Free */ + my_free(mux_sram_bits); + my_free(sram_vdd_port_name); + + return; +} + +void fprint_switch_box_interc(FILE* fp, + t_sb cur_sb_info, + int chan_side, + t_rr_node* cur_rr_node) { + int sb_x, sb_y; + int num_drive_rr_nodes = 0; + t_rr_node** drive_rr_nodes = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + sb_x = cur_sb_info.x; + sb_y = cur_sb_info.y; + + /* Check */ + assert((!(0 > sb_x))&&(!(sb_x > (nx + 1)))); + assert((!(0 > sb_y))&&(!(sb_y > (ny + 1)))); + /* + find_drive_rr_nodes_switch_box(switch_box_x, switch_box_y, cur_rr_node, chan_side, 0, + &num_drive_rr_nodes, &drive_rr_nodes, &switch_index); + */ + + /* Determine if the interc lies inside a channel wire, that is interc between segments */ + if (1 == is_sb_interc_between_segments(sb_x, sb_y, cur_rr_node, chan_side)) { + num_drive_rr_nodes = 0; + drive_rr_nodes = NULL; + } else { + num_drive_rr_nodes = cur_rr_node->num_drive_rr_nodes; + drive_rr_nodes = cur_rr_node->drive_rr_nodes; + } + + if (0 == num_drive_rr_nodes) { + /* Print a special direct connection*/ + fprint_switch_box_short_interc(fp, cur_sb_info, chan_side, cur_rr_node, + num_drive_rr_nodes, cur_rr_node); + } else if (1 == num_drive_rr_nodes) { + /* Print a direct connection*/ + fprint_switch_box_short_interc(fp, cur_sb_info, chan_side, cur_rr_node, + num_drive_rr_nodes, drive_rr_nodes[0]); + } else if (1 < num_drive_rr_nodes) { + /* Print the multiplexer, fan_in >= 2 */ + fprint_switch_box_mux(fp, cur_sb_info, chan_side, cur_rr_node, + num_drive_rr_nodes, drive_rr_nodes, + cur_rr_node->drive_switches[0]); + } /*Nothing should be done else*/ + + /* Free */ + + return; +} + +/* Task: Print the subckt of a Switch Box. + * A Switch Box subckt consists of following ports: + * 1. Channel Y [x][y] inputs + * 2. Channel X [x+1][y] inputs + * 3. Channel Y [x][y-1] outputs + * 4. Channel X [x][y] outputs + * 5. Grid[x][y+1] Right side outputs pins + * 6. Grid[x+1][y+1] Left side output pins + * 7. Grid[x+1][y+1] Bottom side output pins + * 8. Grid[x+1][y] Top side output pins + * 9. Grid[x+1][y] Left side output pins + * 10. Grid[x][y] Right side output pins + * 11. Grid[x][y] Top side output pins + * 12. Grid[x][y+1] Bottom side output pins + * + * -------------- -------------- + * | | | | + * | Grid | ChanY | Grid | + * | [x][y+1] | [x][y+1] | [x+1][y+1] | + * | | | | + * -------------- -------------- + * ---------- + * ChanX | Switch | ChanX + * [x][y] | Box | [x+1][y] + * | [x][y] | + * ---------- + * -------------- -------------- + * | | | | + * | Grid | ChanY | Grid | + * | [x][y] | [x][y] | [x+1][y] | + * | | | | + * -------------- -------------- + * For channels chanY with INC_DIRECTION on the top side, they should be marked as outputs + * For channels chanY with DEC_DIRECTION on the top side, they should be marked as inputs + * For channels chanY with INC_DIRECTION on the bottom side, they should be marked as inputs + * For channels chanY with DEC_DIRECTION on the bottom side, they should be marked as outputs + * For channels chanX with INC_DIRECTION on the left side, they should be marked as inputs + * For channels chanX with DEC_DIRECTION on the left side, they should be marked as outputs + * For channels chanX with INC_DIRECTION on the right side, they should be marked as outputs + * For channels chanX with DEC_DIRECTION on the right side, they should be marked as inputs + */ +void fprint_routing_switch_box_subckt(FILE* fp, t_sb cur_sb_info, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices) { + int itrack, inode, side, ix, iy, x, y; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > cur_sb_info.x))&&(!(cur_sb_info.x > (nx + 1)))); + assert((!(0 > cur_sb_info.y))&&(!(cur_sb_info.y > (ny + 1)))); + + x = cur_sb_info.x; + y = cur_sb_info.y; + + /* Print the definition of subckt*/ + fprintf(fp, "***** Switch Box[%d][%d] Sub-Circuit *****\n", cur_sb_info.x, cur_sb_info.y); + fprintf(fp, ".subckt sb[%d][%d] ", cur_sb_info.x, cur_sb_info.y); + fprintf(fp, "\n"); + for (side = 0; side < cur_sb_info.num_sides; side++) { + fprintf(fp, "***** Inputs/outputs of %s side *****\n",convert_side_index_to_string(side)); + determine_sb_port_coordinator(cur_sb_info, side, &ix, &iy); + fprintf(fp, "+ "); + + for (itrack = 0; itrack < cur_sb_info.chan_width[side]; itrack++) { + switch (cur_sb_info.chan_rr_node_direction[side][itrack]) { + case OUT_PORT: + fprintf(fp, "%s[%d][%d]_out[%d] ", + convert_chan_type_to_string(cur_sb_info.chan_rr_node[side][itrack]->type), + ix, iy, itrack); + break; + case IN_PORT: + fprintf(fp, "%s[%d][%d]_in[%d] ", + convert_chan_type_to_string(cur_sb_info.chan_rr_node[side][itrack]->type), + ix, iy, itrack); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of port sb[%d][%d] Channel node[%d] track[%d]!\n", + __FILE__, __LINE__, cur_sb_info.x, cur_sb_info.y, side, itrack); + exit(1); + } + } + fprintf(fp, "\n"); + fprintf(fp, "+ "); + /* Dump OPINs of adjacent CLBs */ + for (inode = 0; inode < cur_sb_info.num_opin_rr_nodes[side]; inode++) { + fprint_grid_side_pin_with_given_index(fp, cur_sb_info.opin_rr_node[side][inode]->ptc_num, + cur_sb_info.opin_rr_node_grid_side[side][inode], + cur_sb_info.opin_rr_node[side][inode]->xlow, + cur_sb_info.opin_rr_node[side][inode]->ylow); + } + fprintf(fp, "\n"); + fprintf(fp, "+ "); + } + + /* Local Vdd and Gnd */ + fprintf(fp, "svdd sgnd\n"); + + /* Specify the head of scan-chain */ + if (SPICE_SRAM_SCAN_CHAIN == sram_spice_orgz_type) { + fprintf(fp, "***** Head of scan-chain *****\n"); + fprintf(fp, "Rsb[%d][%d]_sc_head sb[%d][%d]_sc_head %s[%d]->in 0\n", + x, y, x, y, sram_spice_model->prefix, sram_spice_model->cnt); + } + + /* Put down all the multiplexers */ + for (side = 0; side < cur_sb_info.num_sides; side++) { + fprintf(fp, "***** %s side Multiplexers *****\n", + convert_side_index_to_string(side)); + for (itrack = 0; itrack < cur_sb_info.chan_width[side]; itrack++) { + assert((CHANX == cur_sb_info.chan_rr_node[side][itrack]->type) + ||(CHANY == cur_sb_info.chan_rr_node[side][itrack]->type)); + /* We care INC_DIRECTION tracks at this side*/ + if (OUT_PORT == cur_sb_info.chan_rr_node_direction[side][itrack]) { + fprint_switch_box_interc(fp, cur_sb_info, side, cur_sb_info.chan_rr_node[side][itrack]); + } + } + } + + /* Specify the tail of scan-chain */ + if (SPICE_SRAM_SCAN_CHAIN == sram_spice_orgz_type) { + fprintf(fp, "***** Tail of scan-chain *****\n"); + fprintf(fp, "Rsb[%d][%d]_sc_tail sb[%d][%d]_sc_tail %s[%d]->in 0\n", + x, y, x, y, sram_spice_model->prefix, sram_spice_model->cnt); + } + + fprintf(fp, ".eom\n"); + + /* Free */ + + return; +} + +/* SRC rr_node is the IPIN of a grid.*/ +void fprint_connection_box_short_interc(FILE* fp, + t_cb cur_cb_info, + t_rr_node* src_rr_node) { + t_rr_node* drive_rr_node = NULL; + int iedge, check_flag; + int xlow, ylow, height, side, index; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > cur_cb_info.x))&&(!(cur_cb_info.x > (nx + 1)))); + assert((!(0 > cur_cb_info.y))&&(!(cur_cb_info.y > (ny + 1)))); + assert(1 == src_rr_node->fan_in); + + /* Check the driver*/ + drive_rr_node = &(rr_node[src_rr_node->prev_node]); + assert((CHANX == drive_rr_node->type)||(CHANY == drive_rr_node->type)); + check_flag = 0; + for (iedge = 0; iedge < drive_rr_node->num_edges; iedge++) { + if (src_rr_node == &(rr_node[drive_rr_node->edges[iedge]])) { + check_flag++; + } + } + assert(1 == check_flag); + + xlow = src_rr_node->xlow; + ylow = src_rr_node->ylow; + height = grid[xlow][ylow].offset; + + /* Call the zero-resistance model */ + switch(cur_cb_info.type) { + case CHANX: + fprintf(fp, "Rcbx[%d][%d]_grid[%d][%d]_pin[%d] ", + cur_cb_info.x, cur_cb_info.y, + xlow, ylow + height, src_rr_node->ptc_num); + break; + case CHANY: + fprintf(fp, "Rcby[%d][%d]_grid[%d][%d]_pin[%d] ", + cur_cb_info.x, cur_cb_info.y, + xlow, ylow + height, src_rr_node->ptc_num); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); + exit(1); + } + /* Input port*/ + assert(IPIN == src_rr_node->type); + /* Search all the sides of a SB, see this drive_rr_node is an INPUT of this SB */ + get_rr_node_side_and_index_in_cb_info(src_rr_node, cur_cb_info, OUT_PORT, &side, &index); + /* We need to be sure that drive_rr_node is part of the SB */ + assert((-1 != index)&&(-1 != side)); + fprint_grid_side_pin_with_given_index(fp, cur_cb_info.ipin_rr_node[side][index]->ptc_num, + cur_cb_info.ipin_rr_node_grid_side[side][index], + xlow, ylow); + + /* output port -- > connect to the output at middle point of a channel */ + fprintf(fp, "%s[%d][%d]_midout[%d] ", + convert_chan_type_to_string(drive_rr_node->type), + cur_cb_info.x, cur_cb_info.y, drive_rr_node->ptc_num); + + /* End */ + fprintf(fp, "0\n"); + + + return; +} + +void fprint_connection_box_mux(FILE* fp, + t_cb cur_cb_info, + t_rr_node* src_rr_node) { + int mux_size, cur_num_sram, ilevel; + t_rr_node** drive_rr_nodes = NULL; + int inode, mux_level, path_id, switch_index; + t_spice_model* mux_spice_model = NULL; + int num_mux_sram_bits = 0; + int* mux_sram_bits = NULL; + t_rr_type drive_rr_node_type = NUM_RR_TYPES; + int xlow, ylow, offset, side, index; + char* sram_vdd_port_name = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > cur_cb_info.x))&&(!(cur_cb_info.x > (nx + 1)))); + assert((!(0 > cur_cb_info.y))&&(!(cur_cb_info.y > (ny + 1)))); + + /* Find drive_rr_nodes*/ + mux_size = src_rr_node->num_drive_rr_nodes; + drive_rr_nodes = src_rr_node->drive_rr_nodes; + + /* Configuration bits for MUX*/ + path_id = -1; + for (inode = 0; inode < mux_size; inode++) { + if (drive_rr_nodes[inode] == &(rr_node[src_rr_node->prev_node])) { + path_id = inode; + break; + } + } + assert((-1 != path_id)&&(path_id < mux_size)); + + switch_index = src_rr_node->drive_switches[path_id]; + + mux_spice_model = switch_inf[switch_index].spice_model; + + /* Call the MUX SPICE model */ + fprintf(fp, "X%s_size%d[%d] ", mux_spice_model->prefix, mux_size, mux_spice_model->cnt); + + /* Global ports */ + if (0 < rec_fprint_spice_model_global_ports(fp, mux_spice_model, FALSE)) { + fprintf(fp, "+ "); + } + + /* Check drive_rr_nodes type, should be the same*/ + for (inode = 0; inode < mux_size; inode++) { + if (NUM_RR_TYPES == drive_rr_node_type) { + drive_rr_node_type = drive_rr_nodes[inode]->type; + } else { + assert(drive_rr_node_type == drive_rr_nodes[inode]->type); + assert((CHANX == drive_rr_nodes[inode]->type)||(CHANY == drive_rr_nodes[inode]->type)); + } + } + + /* input port*/ + for (inode = 0; inode < mux_size; inode++) { + fprintf(fp, "%s[%d][%d]_midout[%d] ", + convert_chan_type_to_string(drive_rr_nodes[inode]->type), + cur_cb_info.x, cur_cb_info.y, drive_rr_nodes[inode]->ptc_num); + } + /* output port*/ + xlow = src_rr_node->xlow; + ylow = src_rr_node->ylow; + offset = grid[xlow][ylow].offset; + + assert(IPIN == src_rr_node->type); + /* Search all the sides of a CB, see this drive_rr_node is an INPUT of this SB */ + get_rr_node_side_and_index_in_cb_info(src_rr_node, cur_cb_info, OUT_PORT, &side, &index); + /* We need to be sure that drive_rr_node is part of the CB */ + assert((-1 != index)&&(-1 != side)); + fprint_grid_side_pin_with_given_index(fp, cur_cb_info.ipin_rr_node[side][index]->ptc_num, + cur_cb_info.ipin_rr_node_grid_side[side][index], + xlow, ylow); + + switch (mux_spice_model->design_tech_info.structure) { + case SPICE_MODEL_STRUCTURE_TREE: + mux_level = determine_tree_mux_level(mux_size); + num_mux_sram_bits = mux_level; + mux_sram_bits = decode_tree_mux_sram_bits(mux_size, mux_level, path_id); + break; + case SPICE_MODEL_STRUCTURE_ONELEVEL: + mux_level = 1; + /* Special for 2-input MUX */ + if (2 == mux_size) { + num_mux_sram_bits = 1; + mux_sram_bits = decode_tree_mux_sram_bits(mux_size, mux_level, path_id); + } else { + num_mux_sram_bits = mux_size; + mux_sram_bits = decode_onelevel_mux_sram_bits(mux_size, mux_level, path_id); + } + break; + case SPICE_MODEL_STRUCTURE_MULTILEVEL: + /* Take care of corner case: MUX size = 2 */ + if (2 == mux_size) { + num_mux_sram_bits = 1; + mux_sram_bits = decode_tree_mux_sram_bits(mux_size, 1, path_id); + } else { + mux_level = mux_spice_model->design_tech_info.mux_num_level; + num_mux_sram_bits = determine_num_input_basis_multilevel_mux(mux_size, mux_level) * mux_level; + mux_sram_bits = decode_multilevel_mux_sram_bits(mux_size, mux_level, path_id); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n", + __FILE__, __LINE__, mux_spice_model->name); + exit(1); + } + + /* Print SRAMs that configure this MUX */ + /* Get current counter of mem_bits, bl and wl */ + cur_num_sram = get_sram_orgz_info_num_mem_bit(sram_spice_orgz_info); + for (ilevel = 0; ilevel < num_mux_sram_bits; ilevel++) { + assert( (0 == mux_sram_bits[ilevel]) || (1 == mux_sram_bits[ilevel]) ); + fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, + cur_num_sram + ilevel, mux_sram_bits[ilevel]); + fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, + cur_num_sram + ilevel, 1 - mux_sram_bits[ilevel]); + } + + /* End with svdd and sgnd, subckt name*/ + fprintf(fp, "svdd sgnd %s_size%d\n", mux_spice_model->name, mux_size); + + /* Print the encoding in SPICE netlist for debugging */ + fprintf(fp, "***** SRAM bits for MUX[%d], level=%d, select_path_id=%d. *****\n", + mux_spice_model->cnt, mux_level, path_id); + fprintf(fp, "*****"); + for (ilevel = 0; ilevel < num_mux_sram_bits; ilevel++) { + fprintf(fp, "%d", mux_sram_bits[ilevel]); + } + fprintf(fp, "*****\n"); + + /* Call SRAM subckts*/ + /* Give the VDD port name for SRAMs */ + sram_vdd_port_name = (char*)my_malloc(sizeof(char)* + (strlen(spice_tb_global_vdd_cb_sram_port_name) + + 1 )); + sprintf(sram_vdd_port_name, "%s", + spice_tb_global_vdd_cb_sram_port_name); + /* Now Print SRAMs one by one */ + for (ilevel = 0; ilevel < num_mux_sram_bits; ilevel++) { + fprint_spice_one_sram_subckt(fp, sram_spice_orgz_info, + mux_spice_model, sram_vdd_port_name); + } + + /* Store the configuraion bit to linked-list */ + add_sram_conf_bits_to_llist(sram_spice_orgz_info, cur_num_sram, + num_mux_sram_bits, mux_sram_bits); + + /* Update spice_model counter */ + mux_spice_model->cnt++; + + /* Free */ + my_free(mux_sram_bits); + my_free(sram_vdd_port_name); + + return; +} + +void fprint_connection_box_interc(FILE* fp, + t_cb cur_cb_info, + t_rr_node* src_rr_node) { + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > cur_cb_info.x))&&(!(cur_cb_info.x > (nx + 1)))); + assert((!(0 > cur_cb_info.y))&&(!(cur_cb_info.y > (ny + 1)))); + + if (1 == src_rr_node->fan_in) { + /* Print a direct connection*/ + fprint_connection_box_short_interc(fp, cur_cb_info, src_rr_node); + } else if (1 < src_rr_node->fan_in) { + /* Print the multiplexer, fan_in >= 2 */ + fprint_connection_box_mux(fp, cur_cb_info, src_rr_node); + } /*Nothing should be done else*/ + + return; +} + +/* Print connection boxes + * Print the sub-circuit of a connection Box (Type: [CHANX|CHANY]) + * Actually it is very similiar to switch box but + * the difference is connection boxes connect Grid INPUT Pins to channels + * TODO: merge direct connections into CB + * -------------- -------------- + * | | | | + * | Grid | ChanY | Grid | + * | [x][y+1] | [x][y] | [x+1][y+1] | + * | | Connection | | + * -------------- Box_Y[x][y] -------------- + * ---------- + * ChanX | Switch | ChanX + * [x][y] | Box | [x+1][y] + * Connection | [x][y] | Connection + * Box_X[x][y] ---------- Box_X[x+1][y] + * -------------- -------------- + * | | | | + * | Grid | ChanY | Grid | + * | [x][y] | [x][y-1] | [x+1][y] | + * | | Connection | | + * --------------Box_Y[x][y-1]-------------- + */ +void fprint_routing_connection_box_subckt(FILE* fp, t_cb cur_cb_info, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices) { + int itrack, inode, side, x, y; + int side_cnt = 0; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert((!(0 > cur_cb_info.x))&&(!(cur_cb_info.x > (nx + 1)))); + assert((!(0 > cur_cb_info.y))&&(!(cur_cb_info.y > (ny + 1)))); + + x = cur_cb_info.x; + y = cur_cb_info.y; + + /* Print the definition of subckt*/ + fprintf(fp, ".subckt "); + /* Identify the type of connection box */ + switch(cur_cb_info.type) { + case CHANX: + fprintf(fp, "cbx[%d][%d] ", cur_cb_info.x, cur_cb_info.y); + break; + case CHANY: + fprintf(fp, "cby[%d][%d] ", cur_cb_info.x, cur_cb_info.y); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of connection box!\n", + __FILE__, __LINE__); + exit(1); + } + fprintf(fp, "\n"); + + /* Print the ports of channels*/ + /*connect to the mid point of a track*/ + /* Get the chan_rr_nodes: Only one side of a cb_info has chan_rr_nodes*/ + side_cnt = 0; + for (side = 0; side < cur_cb_info.num_sides; side++) { + /* Bypass side with zero channel width */ + if (0 == cur_cb_info.chan_width[side]) { + continue; + } + assert (0 < cur_cb_info.chan_width[side]); + side_cnt++; + for (itrack = 0; itrack < cur_cb_info.chan_width[side]; itrack++) { + fprintf(fp, "+ "); + fprintf(fp, "%s[%d][%d]_midout[%d] ", + convert_chan_type_to_string(cur_cb_info.type), + cur_cb_info.x, cur_cb_info.y, itrack); + fprintf(fp, "\n"); + } + } + /*check side_cnt */ + assert(1 == side_cnt); + + side_cnt = 0; + /* Print the ports of grids*/ + /* only check ipin_rr_nodes of cur_cb_info */ + for (side = 0; side < cur_cb_info.num_sides; side++) { + /* Bypass side with zero IPINs*/ + if (0 == cur_cb_info.num_ipin_rr_nodes[side]) { + continue; + } + side_cnt++; + assert(0 < cur_cb_info.num_ipin_rr_nodes[side]); + assert(NULL != cur_cb_info.ipin_rr_node[side]); + for (inode = 0; inode < cur_cb_info.num_ipin_rr_nodes[side]; inode++) { + fprintf(fp, "+ "); + /* Print each INPUT Pins of a grid */ + fprint_grid_side_pin_with_given_index(fp, cur_cb_info.ipin_rr_node[side][inode]->ptc_num, + cur_cb_info.ipin_rr_node_grid_side[side][inode], + cur_cb_info.ipin_rr_node[side][inode]->xlow, + cur_cb_info.ipin_rr_node[side][inode]->ylow); + fprintf(fp, "\n"); + } + } + /* Make sure only 2 sides of IPINs are printed */ + assert((1 == side_cnt)||(2 == side_cnt)); + + /* subckt definition ends with svdd and sgnd*/ + fprintf(fp, "+ "); + fprintf(fp, "svdd sgnd\n"); + + /* Specify the head of scan-chain */ + if (SPICE_SRAM_SCAN_CHAIN == sram_spice_orgz_type) { + switch(cur_cb_info.type) { + case CHANX: + fprintf(fp, "***** Head of scan-chain *****\n"); + fprintf(fp, "Rcbx[%d][%d]_sc_head cbx[%d][%d]_sc_head %s[%d]->in 0\n", + x, y, x, y, sram_spice_model->prefix, sram_spice_model->cnt); + case CHANY: + fprintf(fp, "***** Head of scan-chain *****\n"); + fprintf(fp, "Rcby[%d][%d]_sc_head cby[%d][%d]_sc_head %s[%d]->in 0\n", + x, y, x, y, sram_spice_model->prefix, sram_spice_model->cnt); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); + exit(1); + } + } + + /* Print multiplexers or direct interconnect, + * According to the rr_node lists in cbx_info or cby_info + */ + side_cnt = 0; + for (side = 0; side < cur_cb_info.num_sides; side++) { + /* Bypass side with zero IPINs*/ + if (0 == cur_cb_info.num_ipin_rr_nodes[side]) { + continue; + } + side_cnt++; + assert(0 < cur_cb_info.num_ipin_rr_nodes[side]); + assert(NULL != cur_cb_info.ipin_rr_node[side]); + for (inode = 0; inode < cur_cb_info.num_ipin_rr_nodes[side]; inode++) { + fprint_connection_box_interc(fp, cur_cb_info, cur_cb_info.ipin_rr_node[side][inode]); + } + } + /* Make sure only 2 sides of IPINs are printed */ + assert((1 == side_cnt)||(2 == side_cnt)); + + /* Specify the tail of scan-chain */ + if (SPICE_SRAM_SCAN_CHAIN == sram_spice_orgz_type) { + switch(cur_cb_info.type) { + case CHANX: + fprintf(fp, "***** Tail of scan-chain *****\n"); + fprintf(fp, "Rcbx[%d][%d]_sc_tail cbx[%d][%d]_sc_tail %s[%d]->in 0\n", + x, y, x, y, sram_spice_model->prefix, sram_spice_model->cnt); + case CHANY: + fprintf(fp, "***** Tail of scan-chain *****\n"); + fprintf(fp, "Rcby[%d][%d]_sc_tail cby[%d][%d]_sc_tail %s[%d]->in 0\n", + x, y, x, y, sram_spice_model->prefix, sram_spice_model->cnt); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); + exit(1); + } + } + + fprintf(fp, ".eom\n"); + + return; +} + + +/* Top Function*/ +/* Build the routing resource SPICE sub-circuits*/ +void generate_spice_routing_resources(char* subckt_dir, + t_arch arch, + t_det_routing_arch* routing_arch, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices) { + FILE* fp = NULL; + char* sp_name = my_strcat(subckt_dir, routing_spice_file_name); + int ix, iy; + + assert(UNI_DIRECTIONAL == routing_arch->directionality); + + /* Create FILE */ + fp = fopen(sp_name, "w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create SPICE netlist %s",__FILE__, __LINE__, wires_spice_file_name); + exit(1); + } + fprint_spice_head(fp,"Routing Resources"); + + /* Two major tasks: + * 1. Generate sub-circuits for Routing Channels + * 2. Generate sub-circuits for Switch Boxes + */ + /* Now: First task: Routing channels + * Sub-circuits are named as chanx[ix][iy] or chany[ix][iy] for horizontal or vertical channels + * each channels consist of a number of routing tracks. (Actually they are metal wires) + * We only support single-driver routing architecture. + * The direction is defined as INC_DIRECTION ------> and DEC_DIRECTION <-------- for chanx + * The direction is defined as INC_DIRECTION /|\ and DEC_DIRECTION | for chany + * | | + * | | + * | \|/ + * For INC_DIRECTION chanx, the inputs are at the left of channels, the outputs are at the right of channels + * For DEC_DIRECTION chanx, the inputs are at the right of channels, the outputs are at the left of channels + * For INC_DIRECTION chany, the inputs are at the bottom of channels, the outputs are at the top of channels + * For DEC_DIRECTION chany, the inputs are at the top of channels, the outputs are at the bottom of channels + */ + /* X - channels [1...nx][0..ny]*/ + vpr_printf(TIO_MESSAGE_INFO, "Writing X-direction Channels...\n"); + for (iy = 0; iy < (ny + 1); iy++) { + for (ix = 1; ix < (nx + 1); ix++) { + fprint_routing_chan_subckt(fp, ix, iy, CHANX, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, + arch.num_segments, arch.Segments); + } + } + /* Y - channels [1...ny][0..nx]*/ + vpr_printf(TIO_MESSAGE_INFO, "Writing Y-direction Channels...\n"); + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + fprint_routing_chan_subckt(fp, ix, iy, CHANY, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, + arch.num_segments, arch.Segments); + } + } + + /* Switch Boxes*/ + vpr_printf(TIO_MESSAGE_INFO, "Writing Switch Boxes...\n"); + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 0; iy < (ny + 1); iy++) { + update_spice_models_routing_index_low(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models); + fprint_routing_switch_box_subckt(fp, sb_info[ix][iy], + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + update_spice_models_routing_index_high(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models); + } + } + + /* Connection Boxes */ + vpr_printf(TIO_MESSAGE_INFO, "Writing Connection Boxes...\n"); + /* X - channels [1...nx][0..ny]*/ + for (iy = 0; iy < (ny + 1); iy++) { + for (ix = 1; ix < (nx + 1); ix++) { + update_spice_models_routing_index_low(ix, iy, CHANX, arch.spice->num_spice_model, arch.spice->spice_models); + fprint_routing_connection_box_subckt(fp, cbx_info[ix][iy], + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + update_spice_models_routing_index_high(ix, iy, CHANX, arch.spice->num_spice_model, arch.spice->spice_models); + } + } + /* Y - channels [1...ny][0..nx]*/ + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + update_spice_models_routing_index_low(ix, iy, CHANY, arch.spice->num_spice_model, arch.spice->spice_models); + fprint_routing_connection_box_subckt(fp, cby_info[ix][iy], + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + update_spice_models_routing_index_high(ix, iy, CHANY, arch.spice->num_spice_model, arch.spice->spice_models); + } + } + + /* Close the file*/ + fclose(fp); + + return; +} + diff --git a/vpr7_rram/vpr/SRC/spice/spice_routing.h b/vpr7_rram/vpr/SRC/spice/spice_routing.h new file mode 100644 index 000000000..46e51c531 --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_routing.h @@ -0,0 +1,69 @@ + +void fprint_routing_chan_subckt(FILE* fp, + int x, int y, t_rr_type chan_type, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices, + int num_segment, t_segment_inf* segments); + +void fprint_grid_side_pin_with_given_index(FILE* fp, + int pin_index, int side, + int x, int y); + +void fprint_grid_side_pins(FILE* fp, + t_rr_type pin_type, + int x, + int y, + int side); + +void fprint_switch_box_chan_port(FILE* fp, + t_sb cur_sb_info, + int chan_side, + t_rr_node* cur_rr_node, + enum PORTS cur_rr_node_direction); + +void fprint_switch_box_short_interc(FILE* fp, + t_sb cur_sb_info, + int chan_side, + t_rr_node* cur_rr_node, + int actual_fan_in, + t_rr_node* drive_rr_node); + +void fprint_switch_box_mux(FILE* fp, + t_sb cur_sb_info, + int chan_side, + t_rr_node* cur_rr_node, + int mux_size, + t_rr_node** drive_rr_nodes, + int switch_index); + +void fprint_switch_box_interc(FILE* fp, + t_sb cur_sb_info, + int chan_side, + t_rr_node* cur_rr_node); + +void fprint_routing_switch_box_subckt(FILE* fp, t_sb cur_sb_info, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices); + +void fprint_connection_box_short_interc(FILE* fp, + t_cb cur_cb_info, + t_rr_node* src_rr_node); + +void fprint_connection_box_mux(FILE* fp, + t_cb cur_cb_info, + t_rr_node* src_rr_node); + +void fprint_connection_box_interc(FILE* fp, + t_cb cur_cb_info, + t_rr_node* src_rr_node); + +void fprint_routing_connection_box_subckt(FILE* fp, t_cb cur_cb_info, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices); + +void generate_spice_routing_resources(char* subckt_dir, + t_arch arch, + t_det_routing_arch* routing_arch, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices); + diff --git a/vpr7_rram/vpr/SRC/spice/spice_routing_testbench.c b/vpr7_rram/vpr/SRC/spice/spice_routing_testbench.c new file mode 100644 index 000000000..d4c3e7bc6 --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_routing_testbench.c @@ -0,0 +1,820 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph_util.h" +#include "rr_graph.h" +#include "rr_graph2.h" +#include "vpr_utils.h" + +/* Include spice support headers*/ +#include "linkedlist.h" +#include "fpga_spice_globals.h" +#include "spice_globals.h" +#include "fpga_spice_utils.h" +#include "spice_utils.h" +#include "spice_routing.h" +#include "spice_subckt.h" + +/* Global parameters */ +static int num_segments; +static t_segment_inf* segments; +static int testbench_load_cnt = 0; +static int upbound_sim_num_clock_cycles = 2; +static int max_sim_num_clock_cycles = 2; +static int auto_select_max_sim_num_clock_cycles = TRUE; + +static void init_spice_routing_testbench_globals(t_spice spice) { + auto_select_max_sim_num_clock_cycles = spice.spice_params.meas_params.auto_select_sim_num_clk_cycle; + upbound_sim_num_clock_cycles = spice.spice_params.meas_params.sim_num_clock_cycle + 1; + if (FALSE == auto_select_max_sim_num_clock_cycles) { + max_sim_num_clock_cycles = spice.spice_params.meas_params.sim_num_clock_cycle + 1; + } else { + max_sim_num_clock_cycles = 2; + } +} + +static +void fprint_spice_cb_testbench_global_ports(FILE* fp, + t_spice spice) { + /* Declare the global SRAM ports */ + fprintf(fp, ".global %s\n", + spice_tb_global_vdd_cb_sram_port_name); + + return; +} + +static +void fprint_spice_sb_testbench_global_ports(FILE* fp, + t_spice spice) { + /* Declare the global SRAM ports */ + fprintf(fp, ".global %s\n", + spice_tb_global_vdd_sb_sram_port_name); + + return; +} + + +static +void fprint_spice_routing_testbench_global_ports(FILE* fp, + t_spice spice) { + /* A valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); + exit(1); + } + + /* Print generic global ports*/ + fprint_spice_generic_testbench_global_ports(fp, + sram_spice_orgz_info, + global_ports_head); + + return; +} + +static +void fprintf_spice_routing_testbench_generic_stimuli(FILE* fp, + int num_clocks) { + + /* Give global vdd, gnd, voltage sources*/ + /* A valid file handler */ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* Print generic stimuli */ + fprint_spice_testbench_generic_global_ports_stimuli(fp, num_clocks); + + /* Generate global ports stimuli */ + fprint_spice_testbench_global_ports_stimuli(fp, global_ports_head); + + /* SRAM ports */ + fprintf(fp, "***** Global Inputs for SRAMs *****\n"); + fprint_spice_testbench_global_sram_inport_stimuli(fp, sram_spice_orgz_info); + + fprintf(fp, "***** Global VDD for SRAMs *****\n"); + fprint_spice_testbench_global_vdd_port_stimuli(fp, + spice_tb_global_vdd_sram_port_name, + "vsp"); + + fprintf(fp, "***** Global VDD for load inverters *****\n"); + fprint_spice_testbench_global_vdd_port_stimuli(fp, + spice_tb_global_vdd_load_port_name, + "vsp"); + + + return; +} + +/** In a testbench, we call the subckt of defined connection box (cbx[x][y] or cby[x][y]) + * For each input of connection box (channel track rr_nodes), + * we find their activities and generate input voltage pulses. + * For each output of connection box, we add all the non-inverter downstream components as load. + */ +static +int fprint_spice_routing_testbench_call_one_cb_tb(FILE* fp, + t_spice spice, + t_rr_type chan_type, + int x, int y, + t_ivec*** LL_rr_node_indices) { + int itrack, inode, side, ipin_height; + int side_cnt = 0; + int used = 0; + t_cb cur_cb_info; + + float input_density; + float input_probability; + int input_init_value; + float average_cb_input_density = 0.; + int avg_density_cnt = 0; + + int num_sim_clock_cycles = 0; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + + /* call the defined switch block sb[x][y]*/ + fprintf(fp, "***** Call defined Connection Box[%d][%d] *****\n", x, y); + switch(chan_type) { + case CHANX: + cur_cb_info = cbx_info[x][y]; + break; + case CHANY: + cur_cb_info = cby_info[x][y]; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); + exit(1); + } + fprint_call_defined_one_connection_box(fp, cur_cb_info); + + /* Print input voltage pulses */ + /* connect to the mid point of a track*/ + side_cnt = 0; + for (side = 0; side < cur_cb_info.num_sides; side++) { + /* Bypass side with zero channel width */ + if (0 == cur_cb_info.chan_width[side]) { + continue; + } + assert (0 < cur_cb_info.chan_width[side]); + side_cnt++; + for (itrack = 0; itrack < cur_cb_info.chan_width[side]; itrack++) { + /* Add input voltage pulses*/ + input_density = get_rr_node_net_density(*cur_cb_info.chan_rr_node[side][itrack]); + input_probability = get_rr_node_net_probability(*cur_cb_info.chan_rr_node[side][itrack]); + input_init_value = get_rr_node_net_init_value(*cur_cb_info.chan_rr_node[side][itrack]); + fprintf(fp, "***** Signal %s[%d][%d]_midout[%d] density = %g, probability=%g.*****\n", + convert_chan_type_to_string(cur_cb_info.type), + cur_cb_info.x, cur_cb_info.y, itrack, + input_density, input_probability); + fprintf(fp, "V%s[%d][%d]_midout[%d] %s[%d][%d]_midout[%d] 0 \n", + convert_chan_type_to_string(cur_cb_info.type), + cur_cb_info.x, cur_cb_info.y, itrack, + convert_chan_type_to_string(cur_cb_info.type), + cur_cb_info.x, cur_cb_info.y, itrack); + fprint_voltage_pulse_params(fp, input_init_value, input_density, input_probability); + /* Update statistics */ + average_cb_input_density += input_density; + if (0. < input_density) { + avg_density_cnt++; + } + } + } + /*check side_cnt */ + assert(1 == side_cnt); + + /* Add loads */ + side_cnt = 0; + /* Print the ports of grids*/ + /* only check ipin_rr_nodes of cur_cb_info */ + for (side = 0; side < cur_cb_info.num_sides; side++) { + /* Bypass side with zero IPINs*/ + if (0 == cur_cb_info.num_ipin_rr_nodes[side]) { + continue; + } + side_cnt++; + assert(0 < cur_cb_info.num_ipin_rr_nodes[side]); + assert(NULL != cur_cb_info.ipin_rr_node[side]); + for (inode = 0; inode < cur_cb_info.num_ipin_rr_nodes[side]; inode++) { + /* Print each INPUT Pins of a grid */ + ipin_height = get_grid_pin_height(cur_cb_info.ipin_rr_node[side][inode]->xlow, + cur_cb_info.ipin_rr_node[side][inode]->ylow, + cur_cb_info.ipin_rr_node[side][inode]->ptc_num); + + if (TRUE == run_testbench_load_extraction) { /* Additional switch, default on! */ + fprint_spice_testbench_one_grid_pin_loads(fp, + cur_cb_info.ipin_rr_node[side][inode]->xlow, + cur_cb_info.ipin_rr_node[side][inode]->ylow, + ipin_height, + cur_cb_info.ipin_rr_node_grid_side[side][inode], + cur_cb_info.ipin_rr_node[side][inode]->ptc_num, + &testbench_load_cnt, + LL_rr_node_indices); + } + fprintf(fp, "\n"); + /* Get signal activity */ + input_density = get_rr_node_net_density(*cur_cb_info.ipin_rr_node[side][inode]); + input_probability = get_rr_node_net_probability(*cur_cb_info.ipin_rr_node[side][inode]); + input_init_value = get_rr_node_net_init_value(*cur_cb_info.ipin_rr_node[side][inode]); + /* Update statistics */ + average_cb_input_density += input_density; + if (0. < input_density) { + avg_density_cnt++; + } + } + } + /* Make sure only 2 sides of IPINs are printed */ + assert((1== side_cnt)||(2 == side_cnt)); + + /* Voltage stilumli */ + /* Connect to VDD supply */ + fprintf(fp, "***** Voltage supplies *****\n"); + switch(chan_type) { + case CHANX: + /* Connect to VDD supply */ + fprintf(fp, "***** Voltage supplies *****\n"); + fprintf(fp, "Vgvdd_cb[%d][%d] gvdd_cbx[%d][%d] 0 vsp\n", x, y, x, y); + break; + case CHANY: + /* Connect to VDD supply */ + fprintf(fp, "***** Voltage supplies *****\n"); + fprintf(fp, "Vgvdd_cb[%d][%d] gvdd_cby[%d][%d] 0 vsp\n", x, y, x, y); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); + exit(1); + } + /* SRAM Voltage stimulit */ + fprintf(fp, "V%s %s 0 vsp\n", + spice_tb_global_vdd_cb_sram_port_name, + spice_tb_global_vdd_cb_sram_port_name); + + /* Calculate the num_sim_clock_cycle for this MUX, update global max_sim_clock_cycle in this testbench */ + if (0 < avg_density_cnt) { + average_cb_input_density = average_cb_input_density/avg_density_cnt; + num_sim_clock_cycles = (int)(1/average_cb_input_density) + 1; + used = 1; + } else { + assert(0 == avg_density_cnt); + average_cb_input_density = 0.; + num_sim_clock_cycles = 2; + used = 0; + } + if (TRUE == auto_select_max_sim_num_clock_cycles) { + /* for idle blocks, 2 clock cycle is well enough... */ + if (2 < num_sim_clock_cycles) { + num_sim_clock_cycles = upbound_sim_num_clock_cycles; + } else { + num_sim_clock_cycles = 2; + } + if (max_sim_num_clock_cycles < num_sim_clock_cycles) { + max_sim_num_clock_cycles = num_sim_clock_cycles; + } + } else { + num_sim_clock_cycles = max_sim_num_clock_cycles; + } + + /* Measurements */ + fprint_spice_netlist_transient_setting(fp, spice, num_sim_clock_cycles, FALSE); + fprint_spice_netlist_generic_measurements(fp, spice.spice_params.mc_params, spice.num_spice_model, spice.spice_models); + /* Measure the delay of MUX */ + fprintf(fp, "***** Measurements *****\n"); + /* Measure the leakage power of MUX */ + fprintf(fp, "***** Leakage Power Measurement *****\n"); + fprintf(fp, ".meas tran leakage_power_cb avg p(Vgvdd_cb[%d][%d]) from=0 to='clock_period'\n", + x, y); + /* Measure the leakage power of SRAMs */ + fprintf(fp, ".meas tran leakage_power_sram_cb avg p(V%s) from=0 to='clock_period'\n", + spice_tb_global_vdd_cb_sram_port_name); + /* Measure the dynamic power of MUX */ + fprintf(fp, "***** Dynamic Power Measurement *****\n"); + fprintf(fp, ".meas tran dynamic_power_cb avg p(Vgvdd_cb[%d][%d]) from='clock_period' to='%d*clock_period'\n", + x, y, num_sim_clock_cycles); + fprintf(fp, ".meas tran energy_per_cycle_cb param='dynamic_power_cb*clock_period'\n"); + /* Measure the dynamic power of SRAMs */ + fprintf(fp, ".meas tran dynamic_power_sram_cb avg p(V%s) from='clock_period' to='%d*clock_period'\n", + spice_tb_global_vdd_cb_sram_port_name, + num_sim_clock_cycles); + fprintf(fp, ".meas tran energy_per_cycle_sram_cb param='dynamic_power_sram_cb*clock_period'\n"); + + /* print average cb input density */ + switch(chan_type) { + case CHANX: + vpr_printf(TIO_MESSAGE_INFO,"Average density of CBX[%d][%d] inputs is %.2g.\n", x, y, average_cb_input_density); + break; + case CHANY: + vpr_printf(TIO_MESSAGE_INFO,"Average density of CBY[%d][%d] inputs is %.2g.\n", x, y, average_cb_input_density); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); + exit(1); + } + + return used; +} + +/** In a testbench, we call the subckt of a defined switch block (sb[x][y]) + * For each input of switch block, we find their activities and generate input voltage pulses. + * For each output of switch block, we add all the non-inverter downstream components as load. + */ +static +int fprint_spice_routing_testbench_call_one_sb_tb(FILE* fp, + t_spice spice, + int x, int y, + t_ivec*** LL_rr_node_indices) { + int itrack, inode, side, ipin_height, ix, iy; + int used = 0; + t_sb cur_sb_info; + + char* outport_name = NULL; + char* rr_node_outport_name = NULL; + + float input_density; + float input_probability; + int input_init_value; + float average_sb_input_density = 0.; + int avg_density_cnt = 0; + + int num_sim_clock_cycles = 0; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + + /* call the defined switch block sb[x][y]*/ + fprintf(fp, "***** Call defined Switch Box[%d][%d] *****\n", x, y); + fprint_call_defined_one_switch_box(fp, sb_info[x][y]); + + cur_sb_info = sb_info[x][y]; + + /* For each input of switch block, we generate a input voltage pulse + * For each output of switch block, we generate downstream loads + */ + /* Find all rr_nodes of channels */ + for (side = 0; side < cur_sb_info.num_sides; side++) { + determine_sb_port_coordinator(cur_sb_info, side, &ix, &iy); + + for (itrack = 0; itrack < cur_sb_info.chan_width[side]; itrack++) { + /* Print voltage stimuli and loads */ + switch (cur_sb_info.chan_rr_node_direction[side][itrack]) { + case OUT_PORT: + /* Output port requires loads*/ + /* We should not add any loads to those outputs that are driven simply by a wire in this switch box! + if (1 == is_sb_interc_between_segments(cur_sb_info.x, cur_sb_info.y, + cur_sb_info.chan_rr_node[side][itrack], side)) { + break; + } + */ + /* Only consider the outputs that are driven by a multiplexer */ + outport_name = (char*)my_malloc(sizeof(char)*( + strlen(convert_chan_type_to_string(cur_sb_info.chan_rr_node[side][itrack]->type)) + + 1 + strlen(my_itoa(cur_sb_info.x)) + 2 + strlen(my_itoa(cur_sb_info.y)) + + 6 + strlen(my_itoa(itrack)) + + 1 + 1)); + sprintf(outport_name, "%s[%d][%d]_out[%d]", + convert_chan_type_to_string(cur_sb_info.chan_rr_node[side][itrack]->type), + ix, iy, itrack); + if (TRUE == run_testbench_load_extraction) { /* Additional switch, default on! */ + fprintf(fp, "**** Load for rr_node[%ld] *****\n", cur_sb_info.chan_rr_node[side][itrack] - rr_node); + rr_node_outport_name = fprint_spice_testbench_rr_node_load_version(fp, &testbench_load_cnt, + num_segments, + segments, + 0, + *cur_sb_info.chan_rr_node[side][itrack], + outport_name); + } + /* Free */ + my_free(rr_node_outport_name); + break; + case IN_PORT: + /* Get signal activity */ + input_density = get_rr_node_net_density(*cur_sb_info.chan_rr_node[side][itrack]); + input_probability = get_rr_node_net_probability(*cur_sb_info.chan_rr_node[side][itrack]); + input_init_value = get_rr_node_net_init_value(*cur_sb_info.chan_rr_node[side][itrack]); + /* Update statistics */ + average_sb_input_density += input_density; + if (0. < input_density) { + avg_density_cnt++; + } + /* Input port requires a voltage stimuli */ + /* Add input voltage pulses*/ + fprintf(fp, "***** Signal %s[%d][%d]_in[%d] density = %g, probability=%g.*****\n", + convert_chan_type_to_string(cur_sb_info.chan_rr_node[side][itrack]->type), + ix, iy, itrack, + input_density, input_probability); + fprintf(fp, "V%s[%d][%d]_in[%d] %s[%d][%d]_in[%d] 0 \n", + convert_chan_type_to_string(cur_sb_info.chan_rr_node[side][itrack]->type), + ix, iy, itrack, + convert_chan_type_to_string(cur_sb_info.chan_rr_node[side][itrack]->type), + ix, iy, itrack); + fprint_voltage_pulse_params(fp, input_init_value, input_density, input_probability); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of sb[%d][%d] side[%d] track[%d]!\n", + __FILE__, __LINE__, cur_sb_info.x, cur_sb_info.y, side, itrack); + exit(1); + } + } + /* OPINs of adjacent CLBs are inputs and requires a voltage stimuli */ + /* Input port requires a voltage stimuli */ + for (inode = 0; inode < cur_sb_info.num_opin_rr_nodes[side]; inode++) { + /* Print voltage stimuli of each OPIN */ + ipin_height = get_grid_pin_height(cur_sb_info.opin_rr_node[side][inode]->xlow, + cur_sb_info.opin_rr_node[side][inode]->ylow, + cur_sb_info.opin_rr_node[side][inode]->ptc_num); + fprint_spice_testbench_one_grid_pin_stimulation(fp, + cur_sb_info.opin_rr_node[side][inode]->xlow, + cur_sb_info.opin_rr_node[side][inode]->ylow, + ipin_height, + cur_sb_info.opin_rr_node_grid_side[side][inode], + cur_sb_info.opin_rr_node[side][inode]->ptc_num, + LL_rr_node_indices); + /* Get signal activity */ + input_density = get_rr_node_net_density(*cur_sb_info.opin_rr_node[side][inode]); + input_probability = get_rr_node_net_probability(*cur_sb_info.opin_rr_node[side][inode]); + input_init_value = get_rr_node_net_init_value(*cur_sb_info.opin_rr_node[side][inode]); + /* Update statistics */ + average_sb_input_density += input_density; + if (0. < input_density) { + avg_density_cnt++; + } + } + fprintf(fp, "\n"); + } + + /* Connect to VDD supply */ + fprintf(fp, "***** Voltage supplies *****\n"); + fprintf(fp, "Vgvdd_sb[%d][%d] gvdd_sb[%d][%d] 0 vsp\n", x, y, x, y); + /* SRAM Voltage stimulit */ + fprintf(fp, "V%s %s 0 vsp\n", + spice_tb_global_vdd_sb_sram_port_name, + spice_tb_global_vdd_sb_sram_port_name); + + /* Calculate the num_sim_clock_cycle for this MUX, update global max_sim_clock_cycle in this testbench */ + if (0 < avg_density_cnt) { + average_sb_input_density = average_sb_input_density/avg_density_cnt; + num_sim_clock_cycles = (int)(1/average_sb_input_density) + 1; + used = 1; + } else { + assert(0 == avg_density_cnt); + average_sb_input_density = 0.; + num_sim_clock_cycles = 2; + used = 0; + } + if (TRUE == auto_select_max_sim_num_clock_cycles) { + /* for idle blocks, 2 clock cycle is well enough... */ + if (2 < num_sim_clock_cycles) { + num_sim_clock_cycles = upbound_sim_num_clock_cycles; + } else { + num_sim_clock_cycles = 2; + } + if (max_sim_num_clock_cycles < num_sim_clock_cycles) { + max_sim_num_clock_cycles = num_sim_clock_cycles; + } + } else { + num_sim_clock_cycles = max_sim_num_clock_cycles; + } + + /* Measurements */ + fprint_spice_netlist_transient_setting(fp, spice, num_sim_clock_cycles, FALSE); + fprint_spice_netlist_generic_measurements(fp, spice.spice_params.mc_params, spice.num_spice_model, spice.spice_models); + /* Measure the delay of MUX */ + fprintf(fp, "***** Measurements *****\n"); + /* Measure the leakage power of MUX */ + fprintf(fp, "***** Leakage Power Measurement *****\n"); + fprintf(fp, ".meas tran leakage_power_sb avg p(Vgvdd_sb[%d][%d]) from=0 to='clock_period'\n", + x, y); + /* Measure the leakage power of SRAMs */ + fprintf(fp, ".meas tran leakage_power_sram_sb avg p(V%s) from=0 to='clock_period'\n", + spice_tb_global_vdd_sb_sram_port_name); + /* Measure the dynamic power of MUX */ + fprintf(fp, "***** Dynamic Power Measurement *****\n"); + fprintf(fp, ".meas tran dynamic_power_sb avg p(Vgvdd_sb[%d][%d]) from='clock_period' to='%d*clock_period'\n", + x, y, num_sim_clock_cycles); + fprintf(fp, ".meas tran energy_per_cycle_sb param='dynamic_power_sb*clock_period'\n"); + /* Measure the dynamic power of SRAMs */ + fprintf(fp, ".meas tran dynamic_power_sram_sb avg p(V%s) from='clock_period' to='%d*clock_period'\n", + spice_tb_global_vdd_sb_sram_port_name, + num_sim_clock_cycles); + fprintf(fp, ".meas tran energy_per_cycle_sram_sb param='dynamic_power_sram_sb*clock_period'\n"); + + /* print average sb input density */ + vpr_printf(TIO_MESSAGE_INFO,"Average density of SB[%d][%d] inputs is %.2g.\n", x, y, average_sb_input_density); + + /* Free */ + + return used; +} + +int fprint_spice_one_cb_testbench(char* formatted_spice_dir, + char* circuit_name, + char* cb_testbench_name, + char* include_dir_path, + char* subckt_dir_path, + t_ivec*** LL_rr_node_indices, + int num_clocks, + t_arch arch, + int grid_x, int grid_y, t_rr_type cb_type, + boolean leakage_only) { + FILE* fp = NULL; + char* formatted_subckt_dir_path = format_dir_path(subckt_dir_path); + char* title = my_strcat("FPGA SPICE Connection Box Testbench Bench for Design: ", circuit_name); + char* cb_testbench_file_path = my_strcat(formatted_spice_dir, cb_testbench_name); + char* cb_tb_name = NULL; + int used = 0; + char* temp_include_file_path = NULL; + + /* one cbx, one cby*/ + switch (cb_type) { + case CHANX: + cb_tb_name = "Connection Box X-channel "; + break; + case CHANY: + cb_tb_name = "Connection Box Y-channel "; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d]) Invalid connection_box_type!\n", __FILE__, __LINE__); + exit(1); + } + + /* Check if the path exists*/ + fp = fopen(cb_testbench_file_path,"w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create SPICE %s Test bench netlist %s!\n", + __FILE__, __LINE__, cb_tb_name, cb_testbench_file_path); + exit(1); + } + + /* Load global vars in this source file */ + num_segments = arch.num_segments; + segments = arch.Segments; + testbench_load_cnt = 0; + + /* Print the title */ + fprint_spice_head(fp, title); + my_free(title); + + /* print technology library and design parameters*/ + /* fprint_tech_lib(fp, arch.spice->tech_lib); */ + + /* Include parameter header files */ + fprint_spice_include_param_headers(fp, include_dir_path); + + /* Include Key subckts */ + fprint_spice_include_key_subckts(fp, formatted_subckt_dir_path); + + /* Include user-defined sub-circuit netlist */ + init_include_user_defined_netlists(*(arch.spice)); + fprint_include_user_defined_netlists(fp, *(arch.spice)); + + /* Print simulation temperature and other options for SPICE */ + fprint_spice_options(fp, arch.spice->spice_params); + + /* Global nodes: Vdd for SRAMs, Logic Blocks(Include IO), Switch Boxes, Connection Boxes */ + fprint_spice_routing_testbench_global_ports(fp, *(arch.spice)); + fprint_spice_cb_testbench_global_ports(fp, *(arch.spice)); + + /* Quote defined Logic blocks subckts (Grids) */ + init_spice_routing_testbench_globals(*(arch.spice)); + + fprintf(fp, "****** Include subckt netlists: Routing structures (Switch Boxes, Channels, Connection Boxes) *****\n"); + temp_include_file_path = my_strcat(formatted_subckt_dir_path, routing_spice_file_name); + fprintf(fp, ".include \'%s\'\n", temp_include_file_path); + my_free(temp_include_file_path); + + /* one cbx, one cby*/ + switch (cb_type) { + case CHANX: + case CHANY: + used = fprint_spice_routing_testbench_call_one_cb_tb(fp, *(arch.spice), cb_type, grid_x, grid_y, LL_rr_node_indices); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d]) Invalid connection_box_type!\n", __FILE__, __LINE__); + exit(1); + } + + + /* Generate SPICE routing testbench generic stimuli*/ + fprintf_spice_routing_testbench_generic_stimuli(fp, num_clocks); + + /* SPICE ends*/ + fprintf(fp, ".end\n"); + + /* Close the file*/ + fclose(fp); + + /* Push the testbench to the linked list */ + tb_head = add_one_spice_tb_info_to_llist(tb_head, cb_testbench_file_path, + max_sim_num_clock_cycles); + used = 1; + + return used; +} + +int fprint_spice_one_sb_testbench(char* formatted_spice_dir, + char* circuit_name, + char* sb_testbench_name, + char* include_dir_path, + char* subckt_dir_path, + t_ivec*** LL_rr_node_indices, + int num_clocks, + t_arch arch, + int grid_x, int grid_y, + boolean leakage_only) { + FILE* fp = NULL; + char* formatted_subckt_dir_path = format_dir_path(subckt_dir_path); + char* title = my_strcat("FPGA SPICE Switch Block Testbench Bench for Design: ", circuit_name); + char* sb_testbench_file_path = my_strcat(formatted_spice_dir, sb_testbench_name); + char* sb_tb_name = NULL; + int used = 0; + char* temp_include_file_path = NULL; + + sb_tb_name = "Switch Block "; + + /* Check if the path exists*/ + fp = fopen(sb_testbench_file_path,"w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create SPICE %s Test bench netlist %s!\n", + __FILE__, __LINE__, sb_tb_name, sb_testbench_file_path); + exit(1); + } + + /* Load global vars in this source file */ + num_segments = arch.num_segments; + segments = arch.Segments; + testbench_load_cnt = 0; + + /* Print the title */ + fprint_spice_head(fp, title); + my_free(title); + + /* print technology library and design parameters*/ + + /* Include parameter header files */ + fprint_spice_include_param_headers(fp, include_dir_path); + + /* Include Key subckts */ + fprint_spice_include_key_subckts(fp, formatted_subckt_dir_path); + + /* Include user-defined sub-circuit netlist */ + init_include_user_defined_netlists(*(arch.spice)); + fprint_include_user_defined_netlists(fp, *(arch.spice)); + + /* Print simulation temperature and other options for SPICE */ + fprint_spice_options(fp, arch.spice->spice_params); + + /* Global nodes: Vdd for SRAMs, Logic Blocks(Include IO), Switch Boxes, Connection Boxes */ + fprint_spice_routing_testbench_global_ports(fp, *(arch.spice)); + fprint_spice_sb_testbench_global_ports(fp, *(arch.spice)); + + /* Quote defined Logic blocks subckts (Grids) */ + init_spice_routing_testbench_globals(*(arch.spice)); + + fprintf(fp, "****** Include subckt netlists: Routing structures (Switch Boxes, Channels, Connection Boxes) *****\n"); + temp_include_file_path = my_strcat(formatted_subckt_dir_path, routing_spice_file_name); + fprintf(fp, ".include \'%s\'\n", temp_include_file_path); + my_free(temp_include_file_path); + used = fprint_spice_routing_testbench_call_one_sb_tb(fp, *(arch.spice), grid_x, grid_y, LL_rr_node_indices); + + /* Generate SPICE routing testbench generic stimuli*/ + fprintf_spice_routing_testbench_generic_stimuli(fp, num_clocks); + + /* SPICE ends*/ + fprintf(fp, ".end\n"); + + /* Close the file*/ + fclose(fp); + + /* Push the testbench to the linked list */ + tb_head = add_one_spice_tb_info_to_llist(tb_head, sb_testbench_file_path, + max_sim_num_clock_cycles); + used = 1; + + return used; +} + +/* Top function: Generate testbenches for all Connection Boxes */ +void spice_print_cb_testbench(char* formatted_spice_dir, + char* circuit_name, + char* include_dir_path, + char* subckt_dir_path, + t_ivec*** LL_rr_node_indices, + int num_clocks, + t_arch arch, + boolean leakage_only) { + char* cb_testbench_name = NULL; + int ix, iy; + int cnt = 0; + int used = 0; + + for (iy = 0; iy < (ny+1); iy++) { + for (ix = 1; ix < (nx+1); ix++) { + cb_testbench_name = (char*)my_malloc(sizeof(char)*( strlen(circuit_name) + + 4 + strlen(my_itoa(ix)) + 2 + strlen(my_itoa(iy)) + 1 + + strlen(spice_cb_testbench_postfix) + 1 )); + sprintf(cb_testbench_name, "%s_cbx%d_%d%s", + circuit_name, ix, iy, spice_cb_testbench_postfix); + used = fprint_spice_one_cb_testbench(formatted_spice_dir, circuit_name, cb_testbench_name, + include_dir_path, subckt_dir_path, LL_rr_node_indices, + num_clocks, arch, ix, iy, CHANX, + leakage_only); + if (1 == used) { + cnt += used; + } + /* free */ + my_free(cb_testbench_name); + } + } + for (ix = 0; ix < (nx+1); ix++) { + for (iy = 1; iy < (ny+1); iy++) { + cb_testbench_name = (char*)my_malloc(sizeof(char)*( strlen(circuit_name) + + 4 + strlen(my_itoa(ix)) + 2 + strlen(my_itoa(iy)) + 1 + + strlen(spice_cb_testbench_postfix) + 1 )); + sprintf(cb_testbench_name, "%s_cby%d_%d%s", + circuit_name, ix, iy, spice_cb_testbench_postfix); + used = fprint_spice_one_cb_testbench(formatted_spice_dir, circuit_name, cb_testbench_name, + include_dir_path, subckt_dir_path, LL_rr_node_indices, + num_clocks, arch, ix, iy, CHANY, + leakage_only); + if (1 == used) { + cnt += used; + } + /* free */ + my_free(cb_testbench_name); + } + } + /* Update the global counter */ + num_used_cb_tb = cnt; + vpr_printf(TIO_MESSAGE_INFO,"No. of generated CB testbench = %d\n", num_used_cb_tb); + + + return; +} + +/* Top function: Generate testbenches for all Switch Blocks */ +void spice_print_sb_testbench(char* formatted_spice_dir, + char* circuit_name, + char* include_dir_path, + char* subckt_dir_path, + t_ivec*** LL_rr_node_indices, + int num_clocks, + t_arch arch, + boolean leakage_only) { + + char* sb_testbench_name = NULL; + int ix, iy; + int cnt = 0; + int used = 0; + + for (ix = 0; ix < (nx+1); ix++) { + for (iy = 0; iy < (ny+1); iy++) { + sb_testbench_name = (char*)my_malloc(sizeof(char)*( strlen(circuit_name) + + 4 + strlen(my_itoa(ix)) + 2 + strlen(my_itoa(iy)) + 1 + + strlen(spice_sb_testbench_postfix) + 1 )); + sprintf(sb_testbench_name, "%s_sb%d_%d%s", + circuit_name, ix, iy, spice_sb_testbench_postfix); + used = fprint_spice_one_sb_testbench(formatted_spice_dir, circuit_name, sb_testbench_name, + include_dir_path, subckt_dir_path, LL_rr_node_indices, + num_clocks, arch, ix, iy, + leakage_only); + if (1 == used) { + cnt += used; + } + /* free */ + my_free(sb_testbench_name); + } + } + /* Update the global counter */ + num_used_sb_tb = cnt; + vpr_printf(TIO_MESSAGE_INFO,"No. of generated SB testbench = %d\n", num_used_sb_tb); + + return; +} diff --git a/vpr7_rram/vpr/SRC/spice/spice_routing_testbench.h b/vpr7_rram/vpr/SRC/spice/spice_routing_testbench.h new file mode 100644 index 000000000..fddafd258 --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_routing_testbench.h @@ -0,0 +1,19 @@ + + +void spice_print_cb_testbench(char* formatted_spice_dir, + char* circuit_name, + char* include_dir_path, + char* subckt_dir_path, + t_ivec*** LL_rr_node_indices, + int num_clocks, + t_arch arch, + boolean leakage_only); + +void spice_print_sb_testbench(char* formatted_spice_dir, + char* circuit_name, + char* include_dir_path, + char* subckt_dir_path, + t_ivec*** LL_rr_node_indices, + int num_clocks, + t_arch arch, + boolean leakage_only); diff --git a/vpr7_rram/vpr/SRC/spice/spice_run_scripts.c b/vpr7_rram/vpr/SRC/spice/spice_run_scripts.c new file mode 100644 index 000000000..d39d37334 --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_run_scripts.c @@ -0,0 +1,128 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph.h" +#include "vpr_utils.h" +#include "path_delay.h" +#include "stats.h" + +/* Include spice support headers*/ +#include "read_xml_spice_util.h" +#include "linkedlist.h" +#include "fpga_spice_globals.h" +#include "spice_globals.h" +#include "fpga_spice_utils.h" +#include "spice_subckt.h" +#include "spice_pbtypes.h" +#include "spice_heads.h" +#include "spice_lut.h" +#include "spice_top_netlist.h" +#include "spice_mux_testbench.h" +#include "spice_grid_testbench.h" +#include "spice_lut_testbench.h" +#include "spice_hardlogic_testbench.h" +#include "spice_routing_testbench.h" + +static char* run_hspice_shell_script_name = "run_hspice_sim.sh"; +static char* sim_results_dir_name = "results/"; + +void fprint_run_hspice_shell_script(t_spice spice, + char* spice_dir_path, + char* subckt_dir_path) { + FILE* fp = NULL; + /* Format the directory path */ + char* spice_dir_formatted = format_dir_path(spice_dir_path); + char* shell_script_path = my_strcat(spice_dir_path, run_hspice_shell_script_name); + char* testbench_file = NULL; + char* chomped_testbench_file = NULL; + char* chomped_testbench_path = NULL; + char* chomped_testbench_name = NULL; + char* sim_results_dir_path = my_strcat(spice_dir_formatted, sim_results_dir_name); + t_llist* temp = tb_head; + int progress_cnt = 0; + int total_num_sim = 0; + int num_sim_clock_cycle = 0; + + create_dir_path(sim_results_dir_path); + + /* Check if the path exists*/ + fp = fopen(shell_script_path,"w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create Shell Script for running HSPICE %s!",__FILE__, __LINE__, shell_script_path); + exit(1); + } + + /* Go to the subckt dir for HSPICE VerilogA sim*/ + + /* For VerilogA initilization */ + if (1 == rram_design_tech) { + fprintf(fp, "cd %s\n", subckt_dir_path); + fprintf(fp, "source /uusoc/facility/cad_common/Synopsys/hspice_vM-2017.03/hspice/bin/cshrc.meta\n"); + } + + total_num_sim = 0; + temp = tb_head; + while(temp) { + total_num_sim++; + temp = temp->next; + } + + progress_cnt = 0; + temp = tb_head; + /* Run hspice lut testbench netlist */ + while(temp) { + testbench_file = ((t_spicetb_info*)(temp->dptr))->tb_name; + num_sim_clock_cycle = ((t_spicetb_info*)(temp->dptr))->num_sim_clock_cycles; + chomped_testbench_file = chomp_file_name_postfix(testbench_file); + split_path_prog_name(chomped_testbench_file,'/',&chomped_testbench_path ,&chomped_testbench_name); + fprintf(fp, "echo Number of clock cycles in simulation: %d\n", num_sim_clock_cycle); + fprintf(fp, "echo Simulation progress: %d Finish, %d to go, total %d\n", + progress_cnt, total_num_sim-progress_cnt, total_num_sim); + progress_cnt++; + + fprintf(fp, "hspice64 -mt %d -i %s -o %s%s.lis ", + spice_sim_multi_thread_num, + testbench_file, sim_results_dir_path, chomped_testbench_name); + temp = temp->next; + if (1 == rram_design_tech) { + fprintf(fp, "-hdlpath /uusoc/facility/cad_common/Synopsys/hspice_vM-2017.03/hspice/include\n"); + } else { + fprintf(fp, "\n"); + } + } + + fprintf(fp, "echo Simulation progress: %d Finish, %d to go, total %d\n", + progress_cnt, total_num_sim-progress_cnt, total_num_sim); + + if (1 == rram_design_tech) { + fprintf(fp, "cd %s\n", spice_dir_path); + } + + /* close fp */ + fclose(fp); + + vpr_printf(TIO_MESSAGE_INFO,"Shell Script for running HSPICE (%s) has been created successfully!\n", shell_script_path); + + /* Free */ + my_free(spice_dir_formatted); + my_free(shell_script_path); + my_free(chomped_testbench_file); + + return; +} + diff --git a/vpr7_rram/vpr/SRC/spice/spice_run_scripts.h b/vpr7_rram/vpr/SRC/spice/spice_run_scripts.h new file mode 100644 index 000000000..4b19ce9af --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_run_scripts.h @@ -0,0 +1,4 @@ + +void fprint_run_hspice_shell_script(t_spice spice, + char* spice_dir_path, + char* subckt_dir_path); diff --git a/vpr7_rram/vpr/SRC/spice/spice_subckt.c b/vpr7_rram/vpr/SRC/spice/spice_subckt.c new file mode 100644 index 000000000..1c9a4d929 --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_subckt.c @@ -0,0 +1,745 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph.h" +#include "vpr_utils.h" + +/* Include spice support headers*/ +#include "linkedlist.h" +#include "fpga_spice_globals.h" +#include "spice_globals.h" +#include "fpga_spice_utils.h" +#include "spice_utils.h" +#include "spice_mux.h" +#include "spice_lut.h" +#include "spice_pbtypes.h" +#include "spice_routing.h" +#include "spice_subckt.h" + +/***** Local Subroutines *****/ +static +int search_tapbuf_llist_same_settings(t_llist* head, + t_spice_model_buffer* output_buf); + +static +int generate_spice_basics(char* subckt_dir, t_spice spice); + +/* Generate the NMOS and PMOS */ +int generate_spice_nmos_pmos(char* subckt_dir, + t_spice_tech_lib tech_lib) { + FILE* fp = NULL; + char* sp_name = my_strcat(subckt_dir,nmos_pmos_spice_file_name); + /* Standard transistors */ + t_spice_transistor_type* nmos_trans = NULL; + t_spice_transistor_type* pmos_trans = NULL; + /* I/O transistors */ + t_spice_transistor_type* io_nmos_trans = NULL; + t_spice_transistor_type* io_pmos_trans = NULL; + + /* Spot NMOS*/ + nmos_trans = find_mosfet_tech_lib(tech_lib,SPICE_TRANS_NMOS); + if (NULL == nmos_trans) { + vpr_printf(TIO_MESSAGE_ERROR,"NMOS transistor is not defined in architecture XML!\n"); + exit(1); + } + + /* Spot PMOS*/ + pmos_trans = find_mosfet_tech_lib(tech_lib,SPICE_TRANS_PMOS); + if (NULL == pmos_trans) { + vpr_printf(TIO_MESSAGE_ERROR,"PMOS transistor is not defined in architecture XML!\n"); + exit(1); + } + + fp = fopen(sp_name, "w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in SPICE netlist for NMOS and PMOS subckt: %s \n", + __FILE__, __LINE__, nmos_pmos_spice_file_name); + exit(1); + } + fprint_spice_head(fp,"Standard and I/O NMOS and PMOS"); + + /* print sub circuit for PMOS*/ + fprintf(fp,"* Standard NMOS\n"); + fprintf(fp,".subckt %s drain gate source bulk L=nl W=wn\n", nmos_subckt_name); + fprintf(fp,"%s1 drain gate source bulk %s L=L W=W\n", tech_lib.model_ref, nmos_trans->model_name); + fprintf(fp,".eom %s\n", nmos_subckt_name); + + fprintf(fp,"\n"); + /* Print sub circuit for PMOS*/ + fprintf(fp,"* Standard PMOS\n"); + fprintf(fp,".subckt %s drain gate source bulk L=pl W=wp\n", pmos_subckt_name); + fprintf(fp,"%s1 drain gate source bulk %s L=L W=W\n", tech_lib.model_ref, pmos_trans->model_name); + fprintf(fp,".eom %s\n", pmos_subckt_name); + + /* Spot I/O NMOS*/ + io_nmos_trans = find_mosfet_tech_lib(tech_lib,SPICE_TRANS_IO_NMOS); + + if (NULL == io_nmos_trans) { + vpr_printf(TIO_MESSAGE_WARNING,"I/O NMOS transistor is not defined in architecture XML!\n"); + } else { + /* print sub circuit for NMOS*/ + fprintf(fp,"* I/O NMOS\n"); + fprintf(fp,".subckt %s drain gate source bulk L=io_nl W=io_wn\n", io_nmos_subckt_name); + fprintf(fp,"%s1 drain gate source bulk %s L=L W=W\n", tech_lib.model_ref, io_nmos_trans->model_name); + fprintf(fp,".eom %s\n", io_nmos_subckt_name); + } + + /* Spot I/O PMOS*/ + io_pmos_trans = find_mosfet_tech_lib(tech_lib,SPICE_TRANS_IO_PMOS); + + if (NULL == io_pmos_trans) { + vpr_printf(TIO_MESSAGE_WARNING,"I/O PMOS transistor is not defined in architecture XML!\n"); + } else { + /* print sub circuit for PMOS*/ + fprintf(fp,"* I/O PMOS\n"); + fprintf(fp,".subckt %s drain gate source bulk L=io_pl W=io_wp\n", io_pmos_subckt_name); + fprintf(fp,"%s1 drain gate source bulk %s L=L W=W\n", tech_lib.model_ref, io_pmos_trans->model_name); + fprintf(fp,".eom %s\n", io_pmos_subckt_name); + } + + fclose(fp); + + return 1; +} + +static +int search_tapbuf_llist_same_settings(t_llist* head, + t_spice_model_buffer* output_buf) { + t_llist* temp = head; + t_spice_model_buffer* cur_out_buf = NULL; + + /* check */ + if ((NULL == output_buf)||(NULL == head)) { + return 0; + } + assert(NULL != output_buf); + assert(TRUE == output_buf->tapered_buf); + + while(temp) { + cur_out_buf = (t_spice_model_buffer*)(temp->dptr); + assert(TRUE == cur_out_buf->tapered_buf); + if ((cur_out_buf->tap_buf_level == output_buf->tap_buf_level) + &&(cur_out_buf->f_per_stage == output_buf->f_per_stage)) { + return 1; + } + temp = temp->next; + } + return 0; +} + +/* Generate the subckt for a normal tapered buffer */ +void generate_spice_subckt_tapbuf(FILE* fp, + t_spice_model_buffer* output_buf) { + int istage, j; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create top SPICE netlist %s",__FILE__, __LINE__, basics_spice_file_name); + exit(1); + } + + assert(NULL != output_buf); + assert(TRUE == output_buf->tapered_buf); + assert(0 < output_buf->tap_buf_level); + assert(0 < output_buf->f_per_stage); + + /* Definition line */ + fprintf(fp, ".subckt tapbuf_level%d_f%d in out svdd sgnd\n", output_buf->tap_buf_level, output_buf->f_per_stage); + /* Main body of tapered buffer */ + fprintf(fp, "Rinv_in in in_lvl0 0\n"); + /* Print each stage */ + for (istage = 0; istage < output_buf->tap_buf_level; istage++) { + for (j = 0; j < output_buf->size * pow(output_buf->f_per_stage,istage); j++) { + fprintf(fp, "Xinv_lvl%d_no%d in_lvl%d in_lvl%d svdd sgnd inv\n", + istage, j, istage, istage + 1); + } + } + fprintf(fp, "Rinv_out in_lvl%d out 0\n", output_buf->tap_buf_level); + /* End of subckt*/ + fprintf(fp, ".eom\n\n"); + + return; +} + +/* Generate the subckt for a power-gated tapered buffer */ +void generate_spice_subckt_powergated_tapbuf(FILE* fp, + t_spice_model_buffer* output_buf) { + int istage, j; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create top SPICE netlist %s",__FILE__, __LINE__, basics_spice_file_name); + exit(1); + } + + assert(NULL != output_buf); + assert(TRUE == output_buf->exist); + assert(TRUE == output_buf->tapered_buf); + assert(0 < output_buf->tap_buf_level); + assert(0 < output_buf->f_per_stage); + + /* Definition line */ + fprintf(fp, ".subckt pg_tapbuf_level%d_f%d en enb in out svdd sgnd\n", output_buf->tap_buf_level, output_buf->f_per_stage); + /* Main body of tapered buffer */ + fprintf(fp, "Rinv_in in in_lvl0 0\n"); + /* Print each stage */ + for (istage = 0; istage < output_buf->tap_buf_level; istage++) { + for (j = 0; j < output_buf->size * pow(output_buf->f_per_stage,istage); j++) { + fprintf(fp, "Xinv_lvl%d_no%d en enb in_lvl%d in_lvl%d svdd sgnd pg_inv size=1 pg_size=1\n", + istage, j, istage, istage + 1); + } + } + fprintf(fp, "Rinv_out in_lvl%d out 0\n", output_buf->tap_buf_level); + /* End of subckt*/ + fprintf(fp, ".eom\n\n"); + + /* Generate a power-gated tap_buf */ + + return; +} + + +static +int generate_spice_basics(char* subckt_dir, t_spice spice) { + FILE* fp = NULL; + char* sp_name = my_strcat(subckt_dir, basics_spice_file_name); + int imodel = 0; + t_llist* tapered_bufs_head = NULL; + t_llist* temp = NULL; + + fp = fopen(sp_name, "w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create top SPICE netlist %s",__FILE__, __LINE__, basics_spice_file_name); + exit(1); + } + fprint_spice_head(fp,"Inverter, Buffer, Trans. Gate"); + + /* TODO: support power-gated inverter and buffer ! + * We have two options: + * 1. Add power-gate transistors to each inverter/buffer + * 2. Add huge power-gate transistors to the VDD and GND of inverters + */ + /* Inverter */ + fprintf(fp,"* Inverter\n"); + fprintf(fp,".subckt inv in out svdd sgnd size=1\n"); + fprintf(fp,"Xn0_inv out in sgnd sgnd %s L=nl W=\'size*wn\'\n",nmos_subckt_name); + fprintf(fp,"Xp0_inv out in svdd svdd %s L=pl W=\'size*beta*wp\'\n",pmos_subckt_name); + fprintf(fp,".eom inv\n"); + fprintf(fp,"\n"); + /* Power-gated Inverter */ + fprintf(fp,"* Powergated Inverter\n"); + fprintf(fp,".subckt pg_inv en enb in out svdd sgnd size=1 pg_size=1\n"); + fprintf(fp,"Xn0_inv out in sgnd_pg sgnd %s L=nl W=\'size*wn\'\n",nmos_subckt_name); + fprintf(fp,"Xp0_inv out in svdd_pg svdd %s L=pl W=\'size*beta*wp\'\n",pmos_subckt_name); + fprintf(fp,"Xn0_inv_pg sgnd_pg en sgnd sgnd %s L=nl W=\'pg_size*wn\'\n",nmos_subckt_name); + fprintf(fp,"Xp0_inv_pg svdd_pg enb svdd svdd %s L=pl W=\'pg_size*beta*wp\'\n",pmos_subckt_name); + fprintf(fp,".eom inv\n"); + fprintf(fp,"\n"); + + /* Buffer */ + fprintf(fp,"* Buffer\n"); + fprintf(fp,".subckt buf in out svdd sgnd size=2 base_size=1\n"); + fprintf(fp,"Xinv0 in mid svdd sgnd inv base_size='base_size'\n"); + fprintf(fp,"Xinv1 mid out svdd sgnd inv size='size*base_size'\n"); + fprintf(fp,".eom buf\n"); + fprintf(fp,"\n"); + + /* Power-gated Buffer */ + fprintf(fp,"* Power-gated Buffer\n"); + fprintf(fp,".subckt pg_buf en enb in out svdd sgnd size=2 pg_size=2\n"); + fprintf(fp,"Xinv0 en enb in mid svdd sgnd pg_inv size=1 pg_size=1\n"); + fprintf(fp,"Xinv1 en enb mid out svdd sgnd pg_inv size=size pg_size=size\n"); + fprintf(fp,".eom buf\n"); + fprintf(fp,"\n"); + + /* Transmission Gate*/ + fprintf(fp,"* Transmission Gate (Complementary Pass Transistor)\n"); + fprintf(fp,".subckt cpt in out sel sel_inv svdd sgnd nmos_size=1 pmos_size=1\n"); + fprintf(fp,"Xn0_cpt in sel out sgnd %s L=nl W=\'nmos_size*wn\'\n", nmos_subckt_name); + fprintf(fp,"Xp0_cpt in sel_inv out svdd %s L=pl W=\'pmos_size*wp\'\n", pmos_subckt_name); + fprintf(fp,".eom cpt\n"); + fprintf(fp,"\n"); + + /* Tapered buffered support */ + for (imodel = 0; imodel < spice.num_spice_model; imodel++) { + /* Bypass basic components */ + if (SPICE_MODEL_INVBUF != spice.spice_models[imodel].type) { + continue; + } + /* Bypass un tapered buffers */ + if (TRUE != spice.spice_models[imodel].design_tech_info.buffer_info->tapered_buf) { + continue; + } + if (NULL == tapered_bufs_head) { + tapered_bufs_head = create_llist(1); + tapered_bufs_head->dptr = (void*)spice.spice_models[imodel].design_tech_info.buffer_info; + } else if (FALSE == search_tapbuf_llist_same_settings(tapered_bufs_head, spice.spice_models[imodel].design_tech_info.buffer_info)) { + temp = insert_llist_node(tapered_bufs_head); + temp->dptr = (void*)spice.spice_models[imodel].design_tech_info.buffer_info; + } + } + /* Print all the tapered_buf */ + temp = tapered_bufs_head; + while(temp) { + generate_spice_subckt_tapbuf(fp, (t_spice_model_buffer*)(temp->dptr)); + temp = temp->next; + } + + fclose(fp); + + /* Free */ + temp = tapered_bufs_head; + while(temp) { + temp->dptr = NULL; + temp = temp->next; + } + free_llist(tapered_bufs_head); + + return 1; +} + +void generate_spice_rram_veriloga(char* subckt_dir, + t_spice spice) { + FILE* fp = NULL; + char* sp_name = NULL; + int imodel, write_model; + + /* Check if we need such a verilogA model */ + write_model = 0; + for (imodel = 0; imodel < spice.num_spice_model; imodel++) { + if (SPICE_MODEL_DESIGN_RRAM == spice.spice_models[imodel].design_tech) { + write_model = 1; + break; + } + } + if (0 == write_model) { + return; + } else { + rram_design_tech = 1; + } + + sp_name = my_strcat(subckt_dir, rram_veriloga_file_name); + /* Open a File */ + fp = fopen(sp_name, "w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create SPICE netlist %s",__FILE__, __LINE__, wires_spice_file_name); + exit(1); + } + fprintf(fp,"// RRAM Behavior VerilogA Mode\n"); + + /* Include the headers of VerilogA */ + fprintf(fp, "`include \"constants.vams\"\n"); + fprintf(fp, "`include \"disciplines.vams\"\n"); + + /* Model */ + fprintf(fp, "\n"); + fprintf(fp, "module rram_behavior(TE, BE, SRAM, SRAM_INV);\n"); + fprintf(fp, "input SRAM, SRAM_INV;\n"); + fprintf(fp, "inout TE, BE;\n"); + fprintf(fp, "electrical TE, BE, SRAM, SRAM_INV;\n"); + fprintf(fp, "// Design Parameters\n"); + fprintf(fp, "parameter integer initial_state = 0 from [0:1];\n"); + fprintf(fp, "parameter real switch_thres = 1.8 from (0:inf);\n"); + fprintf(fp, "parameter real ron = 1e3 from (0:inf);\n"); + fprintf(fp, "parameter real roff = 1e6 from (0:inf);\n"); + fprintf(fp, "// Local Parameters\n"); + fprintf(fp, "real res = roff;\n"); + fprintf(fp, "real voltage_tolerence = 0;\n"); + fprintf(fp, "integer state = 0;\n"); + fprintf(fp, "\n"); + fprintf(fp, "analog begin\n"); + fprintf(fp, " // Initial\n"); + fprintf(fp, " @(initial_step) begin\n"); + fprintf(fp, " state = initial_state;\n"); + fprintf(fp, " end\n"); + fprintf(fp, " // State\n"); + fprintf(fp, " if (V(SRAM,SRAM_INV) < voltage_tolerence*switch_thres) begin\n"); + fprintf(fp, " state = 0;\n"); + fprintf(fp, " end else begin\n"); + fprintf(fp, " state = 1;\n"); + fprintf(fp, " end\n"); + fprintf(fp, " //LRS\n"); + fprintf(fp, " if (1 == state) begin\n"); + fprintf(fp, " res = ron;\n"); + fprintf(fp, " //HRS\n"); + fprintf(fp, " end else begin\n"); + fprintf(fp, " res = roff;\n"); + fprintf(fp, " end\n"); + fprintf(fp, " // Correlated Resistance with TE and BE\n"); + fprintf(fp, " I(TE,BE) <+ V(TE,BE) / res;\n"); + fprintf(fp, "end\n"); + fprintf(fp, "endmodule\n"); + + /* Close File */ + fclose(fp); + + /* Free */ + my_free(sp_name); + + return; +} + +void fprint_spice_wire_model(FILE* fp, + char* wire_subckt_name, + t_spice_model spice_model, + float res_total, + float cap_total) { + float res_per_level = 0.; + float cap_per_level = 0.; + int i; + int num_input_port = 0; + int num_output_port = 0; + t_spice_model_port** input_port = NULL; + t_spice_model_port** output_port = NULL; + + /* Ensure a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check the wire model*/ + assert(NULL != spice_model.wire_param); + assert(0 < spice_model.wire_param->level); + /* Find the input port, output port*/ + input_port = find_spice_model_ports(&spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + output_port = find_spice_model_ports(&spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + + /* Asserts*/ + assert(1 == num_input_port); + assert(1 == num_output_port); + assert(1 == input_port[0]->size); + assert(1 == output_port[0]->size); + /* print the spice model*/ + fprintf(fp, "* Wire, spice_model_name=%s\n", spice_model.name); + switch (spice_model.type) { + case SPICE_MODEL_CHAN_WIRE: + /* Add an output at middle point for connecting CB inputs */ + fprintf(fp, ".subckt %s %s %s mid_out svdd sgnd\n", + wire_subckt_name, input_port[0]->prefix, output_port[0]->prefix); + break; + case SPICE_MODEL_WIRE: + /* Add an output at middle point for connecting CB inputs */ + fprintf(fp, ".subckt %s %s %s svdd sgnd\n", + wire_subckt_name, input_port[0]->prefix, output_port[0]->prefix); + /* Direct shortcut */ + if ((0. == cap_per_level)&&(0. == res_per_level) + &&(0 == spice_model.input_buffer->exist) + &&(0 == spice_model.output_buffer->exist)) { + fprintf(fp, "Rshortcut %s %s 0\n", input_port[0]->prefix, output_port[0]->prefix); + /* Finish*/ + fprintf(fp, ".eom\n"); + fprintf(fp, "\n"); + return; + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of spice_model! Expect [chan_wire|wire].\n", + __FILE__, __LINE__); + exit(1); + } + + + /* Determine which type of model to print*/ + switch (spice_model.wire_param->type) { + case WIRE_MODEL_PIE : + /* Determine the resistance and capacitance of each level*/ + res_per_level = res_total/((float)(2*spice_model.wire_param->level)); + cap_per_level = cap_total/((float)(spice_model.wire_param->level + 1)); + if ((0. == cap_per_level)&&(0. == res_per_level)) { + /* Special: if R and C are all zeros, we use a zero-voltage source instead */ + fprintf(fp, "Vshortcut pie_wire_in%d pie_wire_in%d 0\n", + 0, spice_model.wire_param->level); + if (SPICE_MODEL_CHAN_WIRE == spice_model.type) { + fprintf(fp, "* Connect the output of middle point\n"); + fprintf(fp, "Vmid_out_ckt pie_wire_in0 mid_out 0\n"); + } + i = spice_model.wire_param->level; + break; + } + if (0. != cap_per_level) { + fprintf(fp, "Clvin pie_wire_in0 sgnd \'%s%s/%d\'\n", + spice_model.name, + design_param_postfix_wire_param_cap_val, + spice_model.wire_param->level + 1); + } + for (i = 0; i < spice_model.wire_param->level; i++) { + fprintf(fp, "Rlv%d_idx0 pie_wire_in%d pie_wire_in%d_inter \'%s%s/%d\'\n", + i, i, i, + spice_model.name, + design_param_postfix_wire_param_res_val, + 2* spice_model.wire_param->level); + fprintf(fp, "Rlv%d_idx1 pie_wire_in%d_inter pie_wire_in%d \'%s%s/%d\'\n", + i, i, i + 1, + spice_model.name, + design_param_postfix_wire_param_res_val, + 2* spice_model.wire_param->level); + if (0. != cap_per_level) { + fprintf(fp, "Clv%d_idx1 pie_wire_in%d sgnd \'%s%s/%d\'\n", + i, i + 1, + spice_model.name, + design_param_postfix_wire_param_cap_val, + spice_model.wire_param->level + 1); + } + } + if (SPICE_MODEL_CHAN_WIRE == spice_model.type) { + /*Connect the middle point */ + fprintf(fp, "* Connect the output of middle point\n"); + if (0 == spice_model.wire_param->level%2) { + fprintf(fp, "Vmid_out_ckt pie_wire_in%d mid_out 0\n", spice_model.wire_param->level/2); + } else if (1 == spice_model.wire_param->level%2) { + fprintf(fp, "Vmid_out_ckt pie_wire_in%d_inter mid_out 0\n", spice_model.wire_param->level/2); + } + } + break; + case WIRE_MODEL_T : + /* Determine the resistance and capacitance of each level*/ + res_per_level = res_total/((float)(2*spice_model.wire_param->level)); + cap_per_level = cap_total/((float)(spice_model.wire_param->level)); + if ((0. == cap_per_level)&&(0. == res_per_level)) { + fprintf(fp, "Vshortcut pie_wire_in%d pie_wire_in%d 0\n", + 0, spice_model.wire_param->level); + if (SPICE_MODEL_CHAN_WIRE == spice_model.type) { + fprintf(fp, "* Connect the output of middle point\n"); + fprintf(fp, "Vmid_out_ckt pie_wire_in0 mid_out 0\n"); + } + i = spice_model.wire_param->level; + break; + } + for (i = 0; i < spice_model.wire_param->level; i++) { + fprintf(fp, "Rlv%d_idx0 pie_wire_in%d pie_wire_in%d_inter \'%s%s/%d\'\n", + i, i, i, + spice_model.name, + design_param_postfix_wire_param_res_val, + 2 * spice_model.wire_param->level); + if (0. != cap_per_level) { + fprintf(fp, "Clv%d_idx1 pie_wire_in%d_inter sgnd \'%s%s/%d\'\n", + i, i, + spice_model.name, + design_param_postfix_wire_param_cap_val, + spice_model.wire_param->level); + } + fprintf(fp, "Rlv%d_idx2 pie_wire_in%d_inter pie_wire_in%d \'%s%s/%d\'\n", + i, i, i + 1, + spice_model.name, + design_param_postfix_wire_param_res_val, + 2 * spice_model.wire_param->level); + } + if (SPICE_MODEL_CHAN_WIRE == spice_model.type) { + /*Connect the middle point */ + fprintf(fp, "* Connect the output of middle point\n"); + if (0 == spice_model.wire_param->level%2) { + fprintf(fp, "Vmid_out_ckt pie_wire_in%d mid_out 0\n", spice_model.wire_param->level/2); + } else if (1 == spice_model.wire_param->level%2) { + fprintf(fp, "Vmid_out_ckt pie_wire_in%d_inter mid_out 0\n", spice_model.wire_param->level/2); + } + } + break; + default: + vpr_printf(TIO_MESSAGE_INFO,"(File:%s,[LINE%d])Invalid SPICE Wire Model type of spice_model(%s).\n", + __FILE__, __LINE__, spice_model.name); + exit(1); + } + assert(i == spice_model.wire_param->level); + + /* Add input, output buffers*/ + assert(NULL != spice_model.input_buffer); + if (spice_model.input_buffer->exist) { + switch (spice_model.input_buffer->type) { + case SPICE_MODEL_BUF_INV: + /* Each inv: svdd sgnd size=param*/ + fprintf(fp, "Xinv_in "); /* Given name*/ + fprintf(fp, "%s ", input_port[0]->prefix); /* input port */ + fprintf(fp, "pie_wire_in0 "); /* output port*/ + fprintf(fp, "svdd sgnd inv size=\'%s%s\'", + spice_model.name, + design_param_postfix_input_buf_size); /* subckt name */ + fprintf(fp, "\n"); + break; + case SPICE_MODEL_BUF_BUF: + /* TODO: what about tapered buffer, can we support? */ + /* Each buf: svdd sgnd size=param*/ + fprintf(fp, "Xbuf_in "); /* Given name*/ + fprintf(fp, "%s ", input_port[0]->prefix); /* input port */ + fprintf(fp, "pie_wire_in0 "); /* output port*/ + fprintf(fp, "svdd sgnd buf size=\'%s%s\'", + spice_model.name, + design_param_postfix_output_buf_size); /* subckt name */ + fprintf(fp, "\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type for spice_model_buffer.\n", + __FILE__, __LINE__); + exit(1); + } + } else { + /* There is no buffer, I create a zero voltage source between*/ + /* V 0*/ + fprintf(fp, "Rin %s pie_wire_in0 0\n", + input_port[0]->prefix); + } + + assert(NULL != spice_model.output_buffer); + if (spice_model.output_buffer->exist) { + switch (spice_model.output_buffer->type) { + case SPICE_MODEL_BUF_INV: + /* Each inv: svdd sgnd size=param*/ + fprintf(fp, "Xinv_out "); /* Given name*/ + fprintf(fp, "pie_wire_in%d ", spice_model.wire_param->level); /* input port */ + fprintf(fp, "%s ", output_port[0]->prefix); /* output port*/ + fprintf(fp, "svdd sgnd inv size=\'%s%s\'", + spice_model.name, + design_param_postfix_output_buf_size); /* subckt name */ + fprintf(fp, "\n"); + break; + case SPICE_MODEL_BUF_BUF: + /* TODO: what about tapered buffer, can we support? */ + /* Each buf: svdd sgnd size=param*/ + fprintf(fp, "Xbuf_out "); /* Given name*/ + fprintf(fp, "pie_wire_in%d ", spice_model.wire_param->level); /* input port */ + fprintf(fp, "%s ", output_port[0]->prefix); /* output port*/ + fprintf(fp, "svdd sgnd buf size=\'%s%s\'", + spice_model.name, + design_param_postfix_output_buf_size); /* subckt name */ + fprintf(fp, "\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type for spice_model_buffer.\n", + __FILE__, __LINE__); + exit(1); + } + } else { + /* There is no buffer, I create a zero voltage source between*/ + /* V 0*/ + fprintf(fp, "Rout pie_wire_in%d %s 0\n", + spice_model.wire_param->level, output_port[0]->prefix); + } + + /* Finish*/ + fprintf(fp, ".eom\n"); + fprintf(fp, "\n"); + + return; +} + +void generate_spice_wires(char* subckt_dir, + int num_segments, + t_segment_inf* segments, + int num_spice_model, + t_spice_model* spice_models) { + FILE* fp = NULL; + char* sp_name = my_strcat(subckt_dir, wires_spice_file_name); + char* seg_wire_subckt_name = NULL; + char* seg_index_str = NULL; + int iseg, imodel, len_seg_subckt_name; + + fp = fopen(sp_name, "w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create SPICE netlist %s",__FILE__, __LINE__, wires_spice_file_name); + exit(1); + } + fprint_spice_head(fp,"Wires"); + /* Output wire models*/ + for (imodel = 0; imodel < num_spice_model; imodel++) { + if (SPICE_MODEL_WIRE == spice_models[imodel].type) { + assert(NULL != spice_models[imodel].wire_param); + fprint_spice_wire_model(fp, spice_models[imodel].name, + spice_models[imodel], + spice_models[imodel].wire_param->res_val, + spice_models[imodel].wire_param->cap_val); + } + } + + /* Create wire models for routing segments*/ + fprintf(fp,"* Wire models for segments in routing \n"); + for (iseg = 0; iseg < num_segments; iseg++) { + assert(NULL != segments[iseg].spice_model); + assert(SPICE_MODEL_CHAN_WIRE == segments[iseg].spice_model->type); + assert(NULL != segments[iseg].spice_model->wire_param); + /* Give a unique name for subckt of wire_model of segment, + * spice_model name is unique, and segment name is unique as well + */ + seg_index_str = my_itoa(iseg); + len_seg_subckt_name = strlen(segments[iseg].spice_model->name) + + 4 + strlen(seg_index_str) + 1; /* '\0'*/ + seg_wire_subckt_name = (char*)my_malloc(sizeof(char)*len_seg_subckt_name); + sprintf(seg_wire_subckt_name,"%s_seg%s", + segments[iseg].spice_model->name, seg_index_str); + fprint_spice_wire_model(fp, seg_wire_subckt_name, + *(segments[iseg].spice_model), + segments[iseg].Rmetal, + segments[iseg].Cmetal); + } + + /* Close the file handler */ + fclose(fp); + + /*Free*/ + my_free(seg_index_str); + my_free(seg_wire_subckt_name); + + return; +} + +/* Generate the sub circuits for FPGA SPICE Modeling + * Tasks: + * 1. NMOS and PMOS + * 2. Basics: Inverter and Buffers, transmission gates, rc_segements + * 3. Multiplexers + * 4. Look-Up Tables + * 5. Flip-flops + */ +void generate_spice_subckts(char* subckt_dir, + t_arch* arch, + t_det_routing_arch* routing_arch) { + /* 1.Generate NMOS, PMOS and transmission gate */ + vpr_printf(TIO_MESSAGE_INFO,"Writing SPICE NMOS and PMOS...\n"); + generate_spice_nmos_pmos(subckt_dir, arch->spice->tech_lib); + + /* 2. Generate Inverter, Buffer, and transmission gates*/ + vpr_printf(TIO_MESSAGE_INFO,"Writing SPICE Basic subckts...\n"); + generate_spice_basics(subckt_dir, *(arch->spice)); + + /* 2.5 Generate RRAM Verilog-A model*/ + vpr_printf(TIO_MESSAGE_INFO, "Writing RRAM Behavior Verilog-A model...\n"); + generate_spice_rram_veriloga(subckt_dir, (*(arch->spice))); + + /* 3. Generate Multiplexers */ + vpr_printf(TIO_MESSAGE_INFO,"Writing SPICE Multiplexers...\n"); + generate_spice_muxes(subckt_dir, routing_arch->num_switch, switch_inf, + arch->spice, routing_arch); + + /* 4. Generate Wires*/ + vpr_printf(TIO_MESSAGE_INFO,"Writing SPICE Wires...\n"); + generate_spice_wires(subckt_dir, arch->num_segments, arch->Segments, + arch->spice->num_spice_model, arch->spice->spice_models); + + /*5. Generate LUTs */ + vpr_printf(TIO_MESSAGE_INFO,"Writing SPICE LUTs...\n"); + generate_spice_luts(subckt_dir, arch->spice->num_spice_model, arch->spice->spice_models); + + /* 6. Generate Logic Blocks */ + vpr_printf(TIO_MESSAGE_INFO,"Writing Logic Blocks...\n"); + generate_spice_logic_blocks(subckt_dir, arch); + + /* 7. Generate Routing architecture*/ + vpr_printf(TIO_MESSAGE_INFO, "Writing Routing Resources....\n"); + generate_spice_routing_resources(subckt_dir, (*arch), routing_arch, + num_rr_nodes, rr_node, rr_node_indices); + + return; +} + diff --git a/vpr7_rram/vpr/SRC/spice/spice_subckt.h b/vpr7_rram/vpr/SRC/spice/spice_subckt.h new file mode 100644 index 000000000..d3eb8b9e2 --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_subckt.h @@ -0,0 +1,13 @@ + +int generate_spice_nmos_pmos(char* subckt_dir, + t_spice_tech_lib tech_lib); + +int generate_spice_basics(char* subckt_dir, + t_arch arch); + +void generate_spice_subckt_tapbuf(FILE* fp, + t_spice_model_buffer* output_buf); + +void generate_spice_subckts(char* subckt_dir, + t_arch* arch, + t_det_routing_arch* routing_arch); diff --git a/vpr7_rram/vpr/SRC/spice/spice_top_netlist.c b/vpr7_rram/vpr/SRC/spice/spice_top_netlist.c new file mode 100644 index 000000000..550e45be3 --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_top_netlist.c @@ -0,0 +1,737 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph.h" +#include "vpr_utils.h" + +/* Include spice support headers*/ +#include "linkedlist.h" +#include "fpga_spice_globals.h" +#include "spice_globals.h" +#include "fpga_spice_utils.h" +#include "spice_mux.h" +#include "spice_pbtypes.h" +#include "spice_routing.h" +#include "spice_subckt.h" +#include "spice_utils.h" +#include "spice_top_netlist.h" + +/* Global variables in this source file*/ + + +/******** Subroutines ***********/ +static +void fprint_top_netlist_global_ports(FILE* fp, + int num_clock, + t_spice spice) { + t_spice_model* mem_model = NULL; + int iblock, iopad_idx; + + /* A valid file handler */ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* Global nodes: Vdd for SRAMs, Logic Blocks(Include IO), Switch Boxes, Connection Boxes */ + /* Print generic global ports*/ + fprint_spice_generic_testbench_global_ports(fp, + sram_spice_orgz_info, + global_ports_head); + + fprintf(fp, ".global %s %s %s\n", + spice_tb_global_vdd_localrouting_port_name, + spice_tb_global_vdd_io_port_name, + spice_tb_global_vdd_hardlogic_port_name); + + /* Print the VDD ports of SRAM belonging to other SPICE module */ + fprintf(fp, ".global %s\n", + spice_tb_global_vdd_localrouting_sram_port_name); + fprintf(fp, ".global %s\n", + spice_tb_global_vdd_lut_sram_port_name); + fprintf(fp, ".global %s\n", + spice_tb_global_vdd_cb_sram_port_name); + fprintf(fp, ".global %s\n", + spice_tb_global_vdd_sb_sram_port_name); + fprintf(fp, ".global %s\n", + spice_tb_global_vdd_io_sram_port_name); + + /* Get memory spice model */ + get_sram_orgz_info_mem_model(sram_spice_orgz_info, &mem_model); + + /*Global Vdds for LUTs*/ + fprint_global_vdds_spice_model(fp, SPICE_MODEL_LUT, spice); + /*Global Vdds for FFs*/ + fprint_global_vdds_spice_model(fp, SPICE_MODEL_FF, spice); + /*Global Vdds for IOs*/ + fprint_global_vdds_spice_model(fp, SPICE_MODEL_IOPAD, spice); + /*Global Vdds for Hardlogics*/ + fprint_global_vdds_spice_model(fp, SPICE_MODEL_HARDLOGIC, spice); + /* Global Vdds for Switch Boxes */ + fprint_spice_global_vdd_switch_boxes(fp); + + /* Global Vdds for Connection Blocks */ + fprint_spice_global_vdd_connection_boxes(fp); + + /*Global ports for INPUTs of I/O PADS, SRAMs */ + fprint_global_pad_ports_spice_model(fp, spice); + + /* Add signals from blif benchmark and short-wire them to FPGA I/O PADs + * This brings convenience to checking functionality + */ + fprintf(fp, "***** Link Blif Benchmark inputs to FPGA IOPADs *****\n"); + for (iblock = 0; iblock < num_logical_blocks; iblock++) { + /* General INOUT*/ + if (iopad_spice_model == logical_block[iblock].mapped_spice_model) { + iopad_idx = logical_block[iblock].mapped_spice_model_index; + /* Make sure We find the correct logical block !*/ + assert((VPACK_INPAD == logical_block[iblock].type)||(VPACK_OUTPAD == logical_block[iblock].type)); + fprintf(fp, "***** Blif Benchmark inout %s is mapped to FPGA IOPAD %s[%d] *****\n", + logical_block[iblock].name, gio_inout_prefix, iopad_idx); + fprintf(fp, "R%s_%s[%d] %s_%s[%d] %s%s[%d] 0\n", + logical_block[iblock].name, gio_inout_prefix, iopad_idx, + logical_block[iblock].name, gio_inout_prefix, iopad_idx, + gio_inout_prefix, iopad_spice_model->prefix, iopad_idx); + } + } + + return; +} + +/* Print Stimulations for top-level netlist + * Task list: + * 1. For global ggnd: connect to 0(gnd) + * 2. For global vdd ports: connect to nominal voltage source + * 3. For clock signal, we should create voltage waveforms + * 4. For Set/Reset, TODO: should we reset the chip in the first cycle ??? + * 5. For input/output clb nets (mapped to I/O grids), we should create voltage waveforms + */ +static +void fprint_top_netlist_stimulations(FILE* fp, + int num_clock, + t_spice spice) { + int inet, iblock, iopad_idx; + int ix, iy; + int found_mapped_iopad = 0; + /* Find Input Pad Spice model */ + t_spice_net_info* cur_spice_net_info = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Print generic stimuli */ + fprint_spice_testbench_generic_global_ports_stimuli(fp, num_clock); + + /* Generate global ports stimuli */ + fprint_spice_testbench_global_ports_stimuli(fp, global_ports_head); + + /* SRAM ports */ + /* Every SRAM inputs should have a voltage source */ + fprintf(fp, "***** Global Inputs for SRAMs *****\n"); + fprint_spice_testbench_global_sram_inport_stimuli(fp, sram_spice_orgz_info); + + fprintf(fp, "***** Global VDD for SRAMs *****\n"); + fprint_spice_testbench_global_vdd_port_stimuli(fp, + spice_tb_global_vdd_sram_port_name, + "vsp"); + + /* Global Vdd ports */ + fprintf(fp, "***** Global VDD for I/O pads *****\n"); + fprint_spice_testbench_global_vdd_port_stimuli(fp, + spice_tb_global_vdd_io_port_name, + "vsp"); + + fprintf(fp, "***** Global VDD for I/O pads SRAMs *****\n"); + fprint_spice_testbench_global_vdd_port_stimuli(fp, + spice_tb_global_vdd_io_sram_port_name, + "vsp"); + + fprintf(fp, "***** Global VDD for Local Interconnection *****\n"); + fprint_spice_testbench_global_vdd_port_stimuli(fp, + spice_tb_global_vdd_localrouting_port_name, + "vsp"); + + fprintf(fp, "***** Global VDD for local routing SRAMs *****\n"); + fprint_spice_testbench_global_vdd_port_stimuli(fp, + spice_tb_global_vdd_localrouting_sram_port_name, + "vsp"); + + fprintf(fp, "***** Global VDD for LUTs SRAMs *****\n"); + fprint_spice_testbench_global_vdd_port_stimuli(fp, + spice_tb_global_vdd_lut_sram_port_name, + "vsp"); + + fprintf(fp, "***** Global VDD for Connection Boxes SRAMs *****\n"); + fprint_spice_testbench_global_vdd_port_stimuli(fp, + spice_tb_global_vdd_cb_sram_port_name, + "vsp"); + + fprintf(fp, "***** Global VDD for Switch Boxes SRAMs *****\n"); + fprint_spice_testbench_global_vdd_port_stimuli(fp, + spice_tb_global_vdd_sb_sram_port_name, + "vsp"); + + /* Every Hardlogic use an independent Voltage source */ + fprintf(fp, "***** Global VDD for Hard Logics *****\n"); + fprint_splited_vdds_spice_model(fp, SPICE_MODEL_HARDLOGIC, spice); + + /* Every LUT use an independent Voltage source */ + fprintf(fp, "***** Global VDD for Look-Up Tables (LUTs) *****\n"); + fprint_splited_vdds_spice_model(fp, SPICE_MODEL_LUT, spice); + + /* Every FF use an independent Voltage source */ + fprintf(fp, "***** Global VDD for Flip-flops (FFs) *****\n"); + fprint_splited_vdds_spice_model(fp, SPICE_MODEL_FF, spice); + + /* Every FF use an independent Voltage source */ + fprintf(fp, "***** Global VDD for Flip-flops (FFs) *****\n"); + fprint_splited_vdds_spice_model(fp, SPICE_MODEL_IOPAD, spice); + + /* Every Switch Box (SB) use an independent Voltage source */ + fprintf(fp, "***** Global VDD for Switch Boxes(SBs) *****\n"); + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 0; iy < (ny + 1); iy++) { + fprintf(fp, "Vgvdd_sb[%d][%d] gvdd_sb[%d][%d] 0 vsp\n", ix, iy, ix, iy); + } + } + + /* Every Connection Box (CB) use an independent Voltage source */ + fprintf(fp, "***** Global VDD for Connection Boxes(CBs) *****\n"); + /* cbx */ + /* X - channels [1...nx][0..ny]*/ + for (iy = 0; iy < (ny + 1); iy++) { + for (ix = 1; ix < (nx + 1); ix++) { + fprintf(fp, "Vgvdd_cbx[%d][%d] gvdd_cbx[%d][%d] 0 vsp\n", ix, iy, ix, iy); + } + } + + /* cby */ + /* Y - channels [1...ny][0..nx]*/ + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + fprintf(fp, "Vgvdd_cby[%d][%d] gvdd_cby[%d][%d] 0 vsp\n", ix, iy, ix, iy); + } + } + + + /* For each input_signal + * TODO: this part is low-efficent for run-time concern... Need improve + */ + assert(NULL != iopad_spice_model); + for (iopad_idx = 0; iopad_idx < iopad_spice_model->cnt; iopad_idx++) { + /* Find if this inpad is mapped to a logical block */ + found_mapped_iopad = 0; + for (iblock = 0; iblock < num_logical_blocks; iblock++) { + if ((iopad_spice_model == logical_block[iblock].mapped_spice_model) + &&(iopad_idx == logical_block[iblock].mapped_spice_model_index)) { + /* Make sure We find the correct logical block !*/ + if (VPACK_OUTPAD == logical_block[iblock].type) { + /* Bypass outputs */ + found_mapped_iopad++; + continue; + } + assert(VPACK_INPAD == logical_block[iblock].type); + cur_spice_net_info = NULL; + for (inet = 0; inet < num_nets; inet++) { + if (0 == strcmp(clb_net[inet].name, logical_block[iblock].name)) { + cur_spice_net_info = clb_net[inet].spice_net_info; + break; + } + } + if (NULL == cur_spice_net_info) { + assert(NULL != cur_spice_net_info); + } + assert(!(0 > cur_spice_net_info->density)); + /* assert(!(2 < cur_spice_net_info->density)); */ + assert(!(0 > cur_spice_net_info->probability)); + assert(!(1 < cur_spice_net_info->probability)); + /* Get the net information */ + /* First cycle reserved for measuring leakage */ + fprintf(fp, "V%s%s[%d] %s%s[%d] 0 \n", + gio_inout_prefix, + iopad_spice_model->prefix, iopad_idx, + gio_inout_prefix, + iopad_spice_model->prefix, iopad_idx); + fprint_voltage_pulse_params(fp, cur_spice_net_info->init_val, cur_spice_net_info->density, cur_spice_net_info->probability); + /* Short wire to a another node, it is easier to identify in testbench */ + found_mapped_iopad++; + } + } + assert((0 == found_mapped_iopad)||(1 == found_mapped_iopad)); + /* If we find one iopad already, we finished in this round here */ + if (1 == found_mapped_iopad) { + continue; + } + /* if we cannot find any mapped inpad from tech.-mapped netlist, give a default */ + fprintf(fp, "V%s%s[%d] %s%s[%d] 0 ", + gio_inout_prefix, + iopad_spice_model->prefix, iopad_idx, + gio_inout_prefix, + iopad_spice_model->prefix, iopad_idx); + switch (default_signal_init_value) { + case 0: + fprintf(fp, "0\n"); + break; + case 1: + fprintf(fp, "vsp\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid default_signal_init_value (=%d)!\n", + __FILE__, __LINE__, default_signal_init_value); + exit(1); + } + } + + /* Give the floating ports a GND */ + /* I found there is no difference in performance if we do not fix these floating ports */ + /* fprint_grid_float_port_stimulation(fp); */ + + return; +} + +static +void fprint_measure_vdds_cbs(FILE* fp, + enum e_measure_type meas_type, + int num_clock_cycle, + boolean leakage_only) { + int ix, iy, prev_ix, prev_iy; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + switch (meas_type) { + case SPICE_MEASURE_LEAKAGE_POWER: + /* Leakage power of CBs*/ + fprintf(fp, "***** Measure Leakage Power for Connection Boxes(CBs) *****\n"); + /* cbx */ + /* X - channels [1...nx][0..ny]*/ + for (iy = 0; iy < (ny + 1); iy++) { + for (ix = 1; ix < (nx + 1); ix++) { + if (TRUE == leakage_only) { + fprintf(fp, ".measure tran leakage_power_cbx[%d][%d] find p(Vgvdd_cbx[%d][%d]) at=0\n", + ix, iy, ix, iy); + } else { + fprintf(fp, ".measure tran leakage_power_cbx[%d][%d] avg p(Vgvdd_cbx[%d][%d]) from=0 to='clock_period'\n", + ix, iy, ix, iy); + } + } + } + /* cby */ + /* Y - channels [1...ny][0..nx]*/ + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + if (TRUE == leakage_only) { + fprintf(fp, ".measure tran leakage_power_cby[%d][%d] find p(Vgvdd_cby[%d][%d]) at=0\n", + ix, iy, ix, iy); + } else { + fprintf(fp, ".measure tran leakage_power_cby[%d][%d] avg p(Vgvdd_cby[%d][%d]) from=0 to='clock_period'\n", + ix, iy, ix, iy); + } + } + } + /* Measure Total Leakage Power of CBs */ + fprintf(fp, "***** Measure Total Leakage Power for Connection Boxes(CBs) *****\n"); + /* X - channels [1...nx][0..ny]*/ + for (iy = 0; iy < (ny + 1); iy++) { + for (ix = 1; ix < (nx + 1); ix++) { + fprintf(fp, ".measure tran leakage_power_cbx[1to%d][0to%d] \n", ix, iy); + if ((1 == ix)&&(0 == iy)) { + fprintf(fp, "+ param='leakage_power_cbx[%d][%d]'\n", ix, iy); + } else { + fprintf(fp, "+ param='leakage_power_cbx[%d][%d]+leakage_power_cbx[1to%d][0to%d]'\n", + ix, iy, prev_ix, prev_iy); + } + prev_ix = ix; + prev_iy = iy; + } + } + /* Y - channels [1...ny][0..nx]*/ + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + fprintf(fp, ".measure tran leakage_power_cby[0to%d][1to%d] \n", ix, iy); + if ((0 == ix)&&(1 == iy)) { + fprintf(fp, "+ param='leakage_power_cby[%d][%d]'\n", ix, iy); + } else { + fprintf(fp, "+ param='leakage_power_cby[%d][%d]+leakage_power_cby[0to%d][1to%d]'\n", + ix, iy, prev_ix, prev_iy); + } + prev_ix = ix; + prev_iy = iy; + } + } + /* Sum up the leakage power of cbx and cby*/ + fprintf(fp, ".measure tran leakage_power_cbs \n"); + fprintf(fp, "+ param='leakage_power_cbx[1to%d][0to%d]+leakage_power_cby[0to%d][1to%d]' \n", + nx, ny, nx, ny); + break; + case SPICE_MEASURE_DYNAMIC_POWER: + /* Dynamic power of CBs */ + fprintf(fp, "***** Measure Dynamic Power for Connection Boxes(CBs) *****\n"); + /* cbx */ + /* X - channels [1...nx][0..ny]*/ + for (iy = 0; iy < (ny + 1); iy++) { + for (ix = 1; ix < (nx + 1); ix++) { + fprintf(fp, ".measure tran dynamic_power_cbx[%d][%d] avg p(Vgvdd_cbx[%d][%d]) from='clock_period' to='%d*clock_period'\n", + ix, iy, ix, iy, num_clock_cycle); + } + } + /* cby */ + /* Y - channels [1...ny][0..nx]*/ + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + fprintf(fp, ".measure tran dynamic_power_cby[%d][%d] avg p(Vgvdd_cby[%d][%d]) from='clock_period' to='%d*clock_period'\n", + ix, iy, ix, iy, num_clock_cycle); + } + } + /* Measure Dynamic Power of CBs */ + fprintf(fp, "***** Measure Total Dynamic Power for Connection Boxes(CBs) *****\n"); + /* X - channels [1...nx][0..ny]*/ + for (iy = 0; iy < (ny + 1); iy++) { + for (ix = 1; ix < (nx + 1); ix++) { + fprintf(fp, ".measure tran dynamic_power_cbx[1to%d][0to%d] \n", ix, iy); + if ((1 == ix)&&(0 == iy)) { + fprintf(fp, "+ param='dynamic_power_cbx[%d][%d]'\n", ix, iy); + } else { + fprintf(fp, "+ param='dynamic_power_cbx[%d][%d]+dynamic_power_cbx[1to%d][0to%d]'\n", + ix, iy, prev_ix, prev_iy); + } + prev_ix = ix; + prev_iy = iy; + } + } + /* Y - channels [1...ny][0..nx]*/ + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + fprintf(fp, ".measure tran dynamic_power_cby[0to%d][1to%d] \n", ix, iy); + if ((0 == ix)&&(1 == iy)) { + fprintf(fp, "+ param='dynamic_power_cby[%d][%d]'\n", ix, iy); + } else { + fprintf(fp, "+ param='dynamic_power_cby[%d][%d]+dynamic_power_cby[0to%d][1to%d]'\n", + ix, iy, prev_ix, prev_iy); + } + prev_ix = ix; + prev_iy = iy; + } + } + /* Sum up the dynamic power of cbx and cby*/ + fprintf(fp, ".measure tran dynamic_power_cbs \n"); + fprintf(fp, "+ param='dynamic_power_cbx[1to%d][0to%d]+dynamic_power_cby[0to%d][1to%d]' \n", + nx, ny, nx, ny); + fprintf(fp, ".measure tran energy_per_cycle_cbs \n "); + fprintf(fp, "+ param='dynamic_power_cbs*clock_period'\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s,[LINE%d])Invalid Measure Type! Should be [SPICE_MEASURE_LEAKGE_POWER|SPICE_MEASURE_DYNAMIC_POWER]\n", + __FILE__, __LINE__); + exit(1); + } + + return; +} + +static +void fprint_measure_vdds_sbs(FILE* fp, + enum e_measure_type meas_type, + int num_clock_cycle, + boolean leakage_only) { + int ix, iy, prev_ix, prev_iy; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + switch (meas_type) { + case SPICE_MEASURE_LEAKAGE_POWER: + /* Leakage power of SBs*/ + fprintf(fp, "***** Measure Leakage Power for Switch Boxes(SBs) *****\n"); + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 0; iy < (ny + 1); iy++) { + if (TRUE == leakage_only) { + fprintf(fp, ".measure tran leakage_power_sb[%d][%d] find p(Vgvdd_sb[%d][%d]) at=0\n", + ix, iy, ix, iy); + } else { + fprintf(fp, ".measure tran leakage_power_sb[%d][%d] avg p(Vgvdd_sb[%d][%d]) from=0 to='clock_period'\n", + ix, iy, ix, iy); + } + } + } + /* Measure Total Leakage Power of SBs */ + fprintf(fp, "***** Measure Total Leakage Power for Switch Boxes(SBs) *****\n"); + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 0; iy < (ny + 1); iy++) { + fprintf(fp, ".measure tran leakage_power_sb[0to%d][0to%d] \n", ix, iy); + if ((0 == ix)&&(0 == iy)) { + fprintf(fp, "+ param='leakage_power_sb[%d][%d]'\n", ix, iy); + } else { + fprintf(fp, "+ param='leakage_power_sb[%d][%d]+leakage_power_sb[0to%d][0to%d]'\n", + ix, iy, prev_ix, prev_iy); + } + prev_ix = ix; + prev_iy = iy; + } + } + /* Sum up the leakage power of sbs*/ + fprintf(fp, ".measure tran leakage_power_sbs \n"); + fprintf(fp, "+ param='leakage_power_sb[0to%d][0to%d]' \n", + nx, ny); + break; + case SPICE_MEASURE_DYNAMIC_POWER: + /* Dynamic power of SBs */ + fprintf(fp, "***** Measure Dynamic Power for Switch Boxes(SBs) *****\n"); + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 0; iy < (ny + 1); iy++) { + fprintf(fp, ".measure tran dynamic_power_sb[%d][%d] avg p(Vgvdd_sb[%d][%d]) from='clock_period' to='%d*clock_period'\n", + ix, iy, ix, iy, num_clock_cycle); + } + } + /* Measure Total Dynamic Power of SBs */ + fprintf(fp, "***** Measure Total Dynamic Power for Switch Boxes(SBs) *****\n"); + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 0; iy < (ny + 1); iy++) { + fprintf(fp, ".measure tran dynamic_power_sb[0to%d][0to%d] \n", ix, iy); + if ((0 == ix)&&(0 == iy)) { + fprintf(fp, "+ param='dynamic_power_sb[%d][%d]'\n", ix, iy); + } else { + fprintf(fp, "+ param='dynamic_power_sb[%d][%d]+dynamic_power_sb[0to%d][0to%d]'\n", + ix, iy, prev_ix, prev_iy); + } + prev_ix = ix; + prev_iy = iy; + } + } + /* Sum up the dynamic power of sbs*/ + fprintf(fp, ".measure tran dynamic_power_sbs \n"); + fprintf(fp, "+ param='dynamic_power_sb[0to%d][0to%d]' \n", + nx, ny); + fprintf(fp, ".measure tran energy_per_cycle_sbs \n "); + fprintf(fp, "+ param='dynamic_power_sbs*clock_period'\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s,[LINE%d])Invalid Measure Type! Should be [SPICE_MEASURE_LEAKGE_POWER|SPICE_MEASURE_DYNAMIC_POWER]\n", + __FILE__, __LINE__); + exit(1); + } + + return; +} + +static +void fprint_top_netlist_measurements(FILE* fp, + t_spice spice, + boolean leakage_only) { + /* First cycle reserved for measuring leakage */ + int num_clock_cycle = spice.spice_params.meas_params.sim_num_clock_cycle + 1; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + fprint_spice_netlist_transient_setting(fp, spice, num_clock_cycle, leakage_only); + fprint_spice_netlist_generic_measurements(fp, spice.spice_params.mc_params, spice.num_spice_model, spice.spice_models); + + /* TODO: Measure the delay of each mapped net and logical block */ + + /* Measure the power */ + /* Leakage ( the first cycle is reserved for leakage measurement) */ + if (TRUE == leakage_only) { + /* Leakage power of SRAMs */ + fprintf(fp, ".measure tran leakage_power_sram_local_routing find p(Vgvdd_sram_local_routing) at=0\n"); + fprintf(fp, ".measure tran leakage_power_sram_luts find p(Vgvdd_sram_luts) at=0\n"); + fprintf(fp, ".measure tran leakage_power_sram_cbs find p(Vgvdd_sram_cbs) at=0\n"); + fprintf(fp, ".measure tran leakage_power_sram_sbs find p(Vgvdd_sram_sbs) at=0\n"); + /* Leakage power of I/O Pads */ + fprintf(fp, ".measure tran leakage_power_io find p(Vgvdd_io) at=0\n"); + /* Global power of Local Interconnections*/ + fprintf(fp, ".measure tran leakage_power_local_interc find p(Vgvdd_local_interc) at=0\n"); + } else { + /* Leakage power of SRAMs */ + fprintf(fp, ".measure tran leakage_power_sram_local_routing avg p(Vgvdd_sram_local_routing) from=0 to='clock_period'\n"); + fprintf(fp, ".measure tran leakage_power_sram_luts avg p(Vgvdd_sram_luts) from=0 to='clock_period'\n"); + fprintf(fp, ".measure tran leakage_power_sram_cbs avg p(Vgvdd_sram_cbs) from=0 to='clock_period'\n"); + fprintf(fp, ".measure tran leakage_power_sram_sbs avg p(Vgvdd_sram_sbs) from=0 to='clock_period'\n"); + /* Leakage power of I/O Pads */ + fprintf(fp, ".measure tran leakage_power_io avg p(Vgvdd_io) from=0 to='clock_period'\n"); + /* Global power of Local Interconnections*/ + fprintf(fp, ".measure tran leakage_power_local_interc avg p(Vgvdd_local_interc) from=0 to='clock_period'\n"); + } + /* Leakge power of Hard logic */ + fprint_measure_vdds_spice_model(fp, SPICE_MODEL_HARDLOGIC, SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, spice, leakage_only); + /* Leakage power of LUTs*/ + fprint_measure_vdds_spice_model(fp, SPICE_MODEL_LUT, SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, spice, leakage_only); + /* Leakage power of FFs*/ + fprint_measure_vdds_spice_model(fp, SPICE_MODEL_FF, SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, spice, leakage_only); + /* Leakage power of IOPADs */ + fprint_measure_vdds_spice_model(fp, SPICE_MODEL_IOPAD, SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, spice, leakage_only); + /* Leakage power of CBs */ + fprint_measure_vdds_cbs(fp, SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, leakage_only); + /* Leakage power of SBs */ + fprint_measure_vdds_sbs(fp, SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, leakage_only); + + if (TRUE == leakage_only) { + return; + } + + /* Dynamic power */ + /* Dynamic power of SRAMs */ + fprintf(fp, ".measure tran dynamic_power_sram_local_routing avg p(Vgvdd_sram_local_routing) from='clock_period' to='%d*clock_period'\n", num_clock_cycle); + fprintf(fp, ".measure tran energy_per_cycle_sram_local_routing \n "); + fprintf(fp, "+ param='dynamic_power_sram_local_routing*clock_period'\n"); + fprintf(fp, ".measure tran dynamic_power_sram_luts avg p(Vgvdd_sram_luts) from='clock_period' to='%d*clock_period'\n", num_clock_cycle); + fprintf(fp, ".measure tran energy_per_cycle_sram_luts \n "); + fprintf(fp, "+ param='dynamic_power_sram_luts*clock_period'\n"); + fprintf(fp, ".measure tran dynamic_power_sram_cbs avg p(Vgvdd_sram_cbs) from='clock_period' to='%d*clock_period'\n", num_clock_cycle); + fprintf(fp, ".measure tran energy_per_cycle_sram_cbs \n "); + fprintf(fp, "+ param='dynamic_power_sram_cbs*clock_period'\n"); + fprintf(fp, ".measure tran dynamic_power_sram_sbs avg p(Vgvdd_sram_sbs) from='clock_period' to='%d*clock_period'\n", num_clock_cycle); + fprintf(fp, ".measure tran energy_per_cycle_sram_sbs \n "); + fprintf(fp, "+ param='dynamic_power_sram_sbs*clock_period'\n"); + /* Dynamic power of I/O pads */ + fprint_measure_vdds_spice_model(fp, SPICE_MODEL_IOPAD, SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, spice, leakage_only); + /* Dynamic power of Local Interconnections */ + fprintf(fp, ".measure tran dynamic_power_local_interc avg p(Vgvdd_local_interc) from='clock_period' to='%d*clock_period'\n", num_clock_cycle); + fprintf(fp, ".measure tran energy_per_cycle_local_routing \n "); + fprintf(fp, "+ param='dynamic_power_local_interc*clock_period'\n"); + /* Dynamic power of Hard Logic */ + fprint_measure_vdds_spice_model(fp, SPICE_MODEL_HARDLOGIC, SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, spice, leakage_only); + /* Dynamic power of LUTs */ + fprint_measure_vdds_spice_model(fp, SPICE_MODEL_LUT, SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, spice, leakage_only); + /* Dynamic power of FFs */ + fprint_measure_vdds_spice_model(fp, SPICE_MODEL_FF, SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, spice, leakage_only); + /* Dynamic power of CBs */ + fprint_measure_vdds_cbs(fp, SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, leakage_only); + /* Dynamic power of SBs */ + fprint_measure_vdds_sbs(fp, SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, leakage_only); + + return; +} + +/***** Print Top-level SPICE netlist *****/ +void spice_print_top_netlist(char* circuit_name, + char* top_netlist_name, + char* include_dir_path, + char* subckt_dir_path, + int LL_num_rr_nodes, + t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices, + int num_clock, + t_spice spice, + boolean leakage_only) { + FILE* fp = NULL; + char* formatted_subckt_dir_path = format_dir_path(subckt_dir_path); + char* temp_include_file_path = NULL; + char* title = my_strcat("FPGA SPICE Netlist for Design: ", circuit_name); + + /* Check if the path exists*/ + fp = fopen(top_netlist_name,"w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create top SPICE netlist %s!",__FILE__, __LINE__, top_netlist_name); + exit(1); + } + + vpr_printf(TIO_MESSAGE_INFO, "Writing Top-level FPGA Netlist for %s...\n", circuit_name); + + /* Print the title */ + fprint_spice_head(fp, title); + my_free(title); + + /* print technology library and design parameters*/ + /* fprint_tech_lib(fp, spice.tech_lib); */ + + /* Include parameter header files */ + fprint_spice_include_param_headers(fp, include_dir_path); + + /* Include Key subckts */ + fprint_spice_include_key_subckts(fp, subckt_dir_path); + + /* Include user-defined sub-circuit netlist */ + init_include_user_defined_netlists(spice); + fprint_include_user_defined_netlists(fp, spice); + + /* Special subckts for Top-level SPICE netlist */ + fprintf(fp, "****** Include subckt netlists: Look-Up Tables (LUTs) *****\n"); + temp_include_file_path = my_strcat(formatted_subckt_dir_path, luts_spice_file_name); + fprintf(fp, ".include \'%s\'\n", temp_include_file_path); + my_free(temp_include_file_path); + + fprintf(fp, "****** Include subckt netlists: Logic Blocks *****\n"); + temp_include_file_path = my_strcat(formatted_subckt_dir_path, logic_block_spice_file_name); + fprintf(fp, ".include \'%s\'\n", temp_include_file_path); + my_free(temp_include_file_path); + + fprintf(fp, "****** Include subckt netlists: Routing structures (Switch Boxes, Channels, Connection Boxes) *****\n"); + temp_include_file_path = my_strcat(formatted_subckt_dir_path, routing_spice_file_name); + fprintf(fp, ".include \'%s\'\n", temp_include_file_path); + my_free(temp_include_file_path); + + /* Print all global wires*/ + fprint_top_netlist_global_ports(fp, num_clock, spice); + + /* Print simulation temperature and other options for SPICE */ + fprint_spice_options(fp, spice.spice_params); + + /* Quote defined Logic blocks subckts (Grids) */ + fprint_call_defined_grids(fp); + fprint_stimulate_dangling_grid_pins(fp); + + /* Quote Routing structures: Channels */ + fprint_call_defined_channels(fp, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + + /* Quote Routing structures: Conneciton Boxes */ + fprint_call_defined_connection_boxes(fp); + + /* Quote Routing structures: Switch Boxes */ + fprint_call_defined_switch_boxes(fp); + + /* Add stimulations */ + fprint_top_netlist_stimulations(fp, num_clock, spice); + + /* Add measurements */ + fprint_top_netlist_measurements(fp, spice, leakage_only); + + /* SPICE ends*/ + fprintf(fp, ".end\n"); + + /* Close the file*/ + fclose(fp); + + /* Push the testbench to the linked list */ + tb_head = add_one_spice_tb_info_to_llist(tb_head, top_netlist_name, + spice.spice_params.meas_params.sim_num_clock_cycle + 1); + + /* Free */ + //my_free(title); + //my_free(formatted_subckt_dir_path); + + return; +} + diff --git a/vpr7_rram/vpr/SRC/spice/spice_top_netlist.h b/vpr7_rram/vpr/SRC/spice/spice_top_netlist.h new file mode 100644 index 000000000..ed6357d2f --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_top_netlist.h @@ -0,0 +1,10 @@ +void spice_print_top_netlist(char* circuit_name, + char* top_netlist_name, + char* include_dir_path, + char* subckt_dir_path, + int LL_num_rr_nodes, + t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices, + int num_clock, + t_spice spice, + boolean leakage_only); diff --git a/vpr7_rram/vpr/SRC/spice/spice_utils.c b/vpr7_rram/vpr/SRC/spice/spice_utils.c new file mode 100644 index 000000000..9d694c151 --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_utils.c @@ -0,0 +1,3247 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph_util.h" +#include "rr_graph.h" +#include "rr_graph2.h" +#include "vpr_utils.h" + +/* Include spice support headers*/ +#include "linkedlist.h" +#include "fpga_spice_globals.h" +#include "spice_globals.h" +#include "fpga_spice_utils.h" +#include "spice_mux.h" +#include "spice_pbtypes.h" +#include "spice_routing.h" +#include "fpga_spice_backannotate_utils.h" +#include "spice_utils.h" + +/***** Subroutines *****/ +void fprint_spice_head(FILE* fp, + char* usage) { + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d]) FileHandle is NULL!\n",__FILE__,__LINE__); + exit(1); + } + fprintf(fp,"*****************************\n"); + fprintf(fp,"* FPGA SPICE Netlist *\n"); + fprintf(fp,"* Description: %s *\n",usage); + fprintf(fp,"* Author: Xifan TANG *\n"); + fprintf(fp,"* Organization: EPFL/IC/LSI *\n"); + fprintf(fp,"* Date: %s *\n",my_gettime()); + fprintf(fp,"*****************************\n"); + return; +} + + +/* Print all the global ports that are stored in the linked list + * Return the number of ports that have been dumped + */ +int rec_fprint_spice_model_global_ports(FILE* fp, + t_spice_model* cur_spice_model, + boolean recursive) { + int i, iport, dumped_port_cnt, rec_dumped_port_cnt; + + dumped_port_cnt = 0; + rec_dumped_port_cnt = 0; + + /* Check */ + assert(NULL != cur_spice_model); + if (0 < cur_spice_model->num_port) { + assert(NULL != cur_spice_model->ports); + } + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + } + + for (iport = 0; iport < cur_spice_model->num_port; iport++) { + /* if this spice model requires customized netlist to be included, we do not go recursively */ + if (TRUE == recursive) { + /* GO recursively first, and meanwhile count the number of global ports */ + /* For the port that requires another spice_model, i.e., SRAM + * We need include any global port in that spice model + */ + if (NULL != cur_spice_model->ports[iport].spice_model) { + /* Check if we need to dump a comma */ + rec_dumped_port_cnt += + rec_fprint_spice_model_global_ports(fp, cur_spice_model->ports[iport].spice_model, + recursive); + /* Update counter */ + dumped_port_cnt += rec_dumped_port_cnt; + continue; + } + } + /* By pass non-global ports*/ + if (FALSE == cur_spice_model->ports[iport].is_global) { + continue; + } + /* We have some port to dump ! + * Print a comment line + */ + if (0 == dumped_port_cnt) { + fprintf(fp, "\n"); + fprintf(fp, "***** BEGIN Global ports of SPICE_MODEL(%s) *****\n", + cur_spice_model->name); + fprintf(fp, "+ "); + } + /* Check if we need to dump a comma */ + for (i = 0; i < cur_spice_model->ports[iport].size; i++) { + fprintf(fp, " %s[%d] ", + cur_spice_model->ports[iport].prefix, + i); + } + /* Update counter */ + dumped_port_cnt++; + } + + /* We have dumped some port! + * Print another comment line + */ + if (0 < dumped_port_cnt) { + fprintf(fp, "\n"); + fprintf(fp, "***** END Global ports of SPICE_MODEL(%s) *****\n", + cur_spice_model->name); + } + + return dumped_port_cnt; +} + +/* Print all the global ports that are stored in the linked list */ +int fprint_spice_global_ports(FILE* fp, t_llist* head) { + t_llist* temp = head; + t_spice_model_port* cur_global_port = NULL; + int dumped_port_cnt = 0; + int i; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + } + + fprintf(fp, "\n"); + fprintf(fp, "***** BEGIN Global ports *****\n"); + fprintf(fp, "+ "); + while(NULL != temp) { + cur_global_port = (t_spice_model_port*)(temp->dptr); + for (i = 0; i < cur_global_port->size; i++) { + fprintf(fp, " %s[%d] ", + cur_global_port->prefix, + i); + } + /* Update counter */ + dumped_port_cnt++; + /* Go to the next */ + temp = temp->next; + } + fprintf(fp, "\n"); + fprintf(fp, "***** END Global ports *****\n"); + + return dumped_port_cnt; +} + +void fprint_spice_generic_testbench_global_ports(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info, + t_llist* head) { + t_spice_model* mem_model = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + } + + fprintf(fp, "***** Generic global ports ***** \n"); + fprintf(fp, "***** VDD, GND ***** \n"); + fprintf(fp, ".global %s\n", + spice_tb_global_vdd_port_name); + fprintf(fp, ".global %s\n", + spice_tb_global_gnd_port_name); + fprintf(fp, "***** Global set ports ***** \n"); + fprintf(fp, ".global %s %s%s \n", + spice_tb_global_set_port_name, + spice_tb_global_set_port_name, + spice_tb_global_port_inv_postfix); + fprintf(fp, "***** Global reset ports ***** \n"); + fprintf(fp, ".global %s %s%s\n", + spice_tb_global_reset_port_name, + spice_tb_global_reset_port_name, + spice_tb_global_port_inv_postfix); + fprintf(fp, "***** Configuration done ports ***** \n"); + fprintf(fp, ".global %s %s%s\n", + spice_tb_global_config_done_port_name, + spice_tb_global_config_done_port_name, + spice_tb_global_port_inv_postfix); + + /* Get memory spice model */ + get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); + fprintf(fp, "***** Global SRAM input ***** \n"); + fprintf(fp, ".global %s->in\n", mem_model->prefix); + + /* Print scan-chain global ports */ + if (SPICE_SRAM_SCAN_CHAIN == sram_spice_orgz_type) { + fprintf(fp, "***** Scan-chain FF: head of scan-chain *****\n"); + fprintf(fp, "*.global %s[0]->in\n", sram_spice_model->prefix); + } + + /* Define a global clock port if we need one*/ + fprintf(fp, "***** Global Clock Signals *****\n"); + fprintf(fp, ".global %s\n", + spice_tb_global_clock_port_name); + fprintf(fp, ".global %s%s\n", + spice_tb_global_clock_port_name, + spice_tb_global_port_inv_postfix); + + fprintf(fp, "***** User-defined global ports ****** \n"); + if (NULL != head) { + fprintf(fp, ".global \n"); + } + fprint_spice_global_ports(fp, head); + + return; +} + +/* Print a SRAM output port in SPICE format */ +void fprint_spice_sram_one_outport(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info, + int cur_sram, + int port_type_index) { + t_spice_model* mem_model = NULL; + char* port_name = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Get memory_model */ + get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); + + /* Keep the branch as it is, in case thing may become more complicated*/ + switch (cur_sram_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + if (0 == port_type_index) { + port_name = "out"; + } else { + assert(1 == port_type_index); + port_name = "outb"; + } + break; + case SPICE_SRAM_SCAN_CHAIN: + if (0 == port_type_index) { + port_name = "scff_out"; + } else { + assert(1 == port_type_index); + port_name = "scff_outb"; + } + break; + case SPICE_SRAM_MEMORY_BANK: + if (0 == port_type_index) { + port_name = "out"; + } else { + assert(1 == port_type_index); + port_name = "outb"; + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization !\n", + __FILE__, __LINE__); + exit(1); + } + + /*Malloc and generate the full name of port */ + fprintf(fp, "%s[%d]->%s ", + mem_model->prefix, cur_sram, port_name); /* Outputs */ + + /* Free */ + /* Local variables such as port1_name and port2 name are automatically freed */ + + return; +} + +/* Print a SRAM module in SPICE format */ +void fprint_spice_one_specific_sram_subckt(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info, + t_spice_model* parent_spice_model, + char* vdd_port_name, + int sram_index) { + t_spice_model* mem_model = NULL; + int cur_sram = 0; + + /* Get memory model */ + get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); + + /* Get current index of SRAM module */ + cur_sram = sram_index; + + /* Depend on the type of SRAM organization */ + switch (cur_sram_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + case SPICE_SRAM_MEMORY_BANK: + fprintf(fp, "X%s[%d] ", mem_model->prefix, cur_sram); /* SRAM subckts*/ + /* fprintf(fp, "%s[%d]->in ", sram_spice_model->prefix, cur_sram);*/ /* Input*/ + /* Global ports : + * Only dump the global ports belonging to a spice_model + * Do not go recursive, we can freely define global ports anywhere in SPICE netlist + */ + rec_fprint_spice_model_global_ports(fp, mem_model, FALSE); + /* Local ports */ + fprintf(fp, "%s->in ", mem_model->prefix); /* Input*/ + fprintf(fp, "%s[%d]->out %s[%d]->outb ", + mem_model->prefix, cur_sram, mem_model->prefix, cur_sram); /* Outputs */ + fprintf(fp, "%s sgnd ", + vdd_port_name); // + fprintf(fp, " %s\n", mem_model->name); // + /* Add nodeset to help convergence */ + fprintf(fp, ".nodeset V(%s[%d]->out) 0\n", mem_model->prefix, cur_sram); + fprintf(fp, ".nodeset V(%s[%d]->outb) vsp\n", mem_model->prefix, cur_sram); + break; + case SPICE_SRAM_SCAN_CHAIN: + fprintf(fp, "X%s[%d] ", mem_model->prefix, cur_sram); /* SRAM subckts*/ + /* Global ports : + * Only dump the global ports belonging to a spice_model + * Do not go recursive, we can freely define global ports anywhere in SPICE netlist + */ + rec_fprint_spice_model_global_ports(fp, mem_model, FALSE); + /* Local ports */ + fprintf(fp, "%s[%d]->in ", mem_model->prefix, cur_sram); /* Input*/ + fprintf(fp, "%s[%d]->out %s[%d]->outb ", + mem_model->prefix, cur_sram, mem_model->prefix, cur_sram); /* Outputs */ + fprintf(fp, "sc_clk sc_rst sc_set \n"); // + fprintf(fp, "%s sgnd ", + vdd_port_name); // + fprintf(fp, " %s\n", mem_model->name); // + /* Add nodeset to help convergence */ + fprintf(fp, ".nodeset V(%s[%d]->out) 0\n", mem_model->prefix, cur_sram); + fprintf(fp, ".nodeset V(%s[%d]->outb) vsp\n", mem_model->prefix, cur_sram); + /* Connect to the tail of previous Scan-chain FF*/ + fprintf(fp,"R%s[%d]_short %s[%d]->out %s[%d]->in 0\n", + mem_model->prefix, cur_sram, + mem_model->prefix, cur_sram, + sram_spice_model->prefix, cur_sram + 1); + /* Specify this is a global signal*/ + fprintf(fp, ".global %s[%d]->in\n", sram_spice_model->prefix, cur_sram); + /* Specify the head and tail of the scan-chain of this LUT */ + fprintf(fp,"R%s[%d]_sc_head %s[%d]_sc_head %s[%d]->in 0\n", + mem_model->prefix, mem_model->cnt, + mem_model->prefix, mem_model->cnt, + mem_model->prefix, mem_model->cnt); + fprintf(fp,"R%s[%d]_sc_tail %s[%d]_sc_tail %s[%d]->in 0\n", + mem_model->prefix, mem_model->cnt, + mem_model->prefix, mem_model->cnt, + mem_model->prefix, cur_sram); + fprintf(fp,".global %s[%d]_sc_head %s[%d]_sc_tail\n", + mem_model->prefix, mem_model->cnt, + mem_model->prefix, mem_model->cnt); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d]) Invalid SRAM organization type!\n", + __FILE__, __LINE__); + exit(1); + } + + return; +} + + +/* Print a SRAM module in SPICE format */ +void fprint_spice_one_sram_subckt(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info, + t_spice_model* parent_spice_model, + char* vdd_port_name) { + t_spice_model* mem_model = NULL; + int cur_num_sram = 0; + + /* Get memory model */ + get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); + + /* Get current index of SRAM module */ + cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); + + /* Call a subroutine: fprint_spice_one_specific_sram_subckt */ + fprint_spice_one_specific_sram_subckt(fp, cur_sram_orgz_info, + parent_spice_model, + vdd_port_name, cur_num_sram); + + /* Update the memory counter in sram_orgz_info */ + update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, + cur_num_sram + 1); + /* Update the memory counter */ + mem_model->cnt++; + + return; +} + +/* Include user defined SPICE netlists */ +void init_include_user_defined_netlists(t_spice spice) { + int i; + + /* Include user-defined sub-circuit netlist */ + for (i = 0; i < spice.num_include_netlist; i++) { + spice.include_netlists[i].included = 0; + } + + return; +} + +void fprint_include_user_defined_netlists(FILE* fp, + t_spice spice) { + int i; + + /* A valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* Include user-defined sub-circuit netlist */ + for (i = 0; i < spice.num_include_netlist; i++) { + if (0 == spice.include_netlists[i].included) { + assert(NULL != spice.include_netlists[i].path); + fprintf(fp, ".include \'%s\'\n", spice.include_netlists[i].path); + spice.include_netlists[i].included = 1; + } else { + assert(1 == spice.include_netlists[i].included); + } + } + + return; +} + +void fprint_splited_vdds_spice_model(FILE* fp, + enum e_spice_model_type spice_model_type, + t_spice spice) { + int imodel, i; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + for (imodel = 0; imodel < spice.num_spice_model; imodel++) { + if (spice_model_type == spice.spice_models[imodel].type) { + for (i = 0; i < spice.spice_models[imodel].cnt; i++) { + fprintf(fp, "V%s_%s[%d] %s_%s[%d] 0 vsp\n", + spice_tb_global_vdd_port_name, + spice.spice_models[imodel].prefix, i, + spice_tb_global_vdd_port_name, + spice.spice_models[imodel].prefix, i); + /* For some gvdd maybe floating, I add a huge resistance to make their leakage power trival + * which does no change to the delay result. + * The resistance value is co-related to the vsp, which produces a trival leakage current (1e-15). + */ + fprintf(fp, "Rgvdd_%s[%d]_huge gvdd_%s[%d] 0 'vsp/10e-15'\n", + spice.spice_models[imodel].prefix, i, spice.spice_models[imodel].prefix, i); + } + } + } + + return; +} + +void fprint_grid_splited_vdds_spice_model(FILE* fp, int grid_x, int grid_y, + enum e_spice_model_type spice_model_type, + t_spice spice) { + int imodel, i; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + for (imodel = 0; imodel < spice.num_spice_model; imodel++) { + if (spice_model_type == spice.spice_models[imodel].type) { + /* Bypass zero-usage spice_model in this grid*/ + if (spice.spice_models[imodel].grid_index_low[grid_x][grid_y] + == spice.spice_models[imodel].grid_index_high[grid_x][grid_y]) { + continue; + } + for (i = spice.spice_models[imodel].grid_index_low[grid_x][grid_y]; + i < spice.spice_models[imodel].grid_index_high[grid_x][grid_y]; + i++) { + fprintf(fp, "Vgvdd_%s[%d] gvdd_%s[%d] 0 vsp\n", + spice.spice_models[imodel].prefix, i, spice.spice_models[imodel].prefix, i); + /* For some gvdd maybe floating, I add a huge resistance to make their leakage power trival + * which does no change to the delay result. + * The resistance value is co-related to the vsp, which produces a trival leakage current (1e-15). + */ + fprintf(fp, "Rgvdd_%s[%d]_huge gvdd_%s[%d] 0 'vsp/10e-15'\n", + spice.spice_models[imodel].prefix, i, spice.spice_models[imodel].prefix, i); + } + } + } + + return; +} + +void fprint_global_vdds_spice_model(FILE* fp, + enum e_spice_model_type spice_model_type, + t_spice spice) { + int imodel, i; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + fprintf(fp, "***** Global VDD ports of %s *****\n", generate_string_spice_model_type(spice_model_type)); + fprintf(fp, ".global \n"); + + for (imodel = 0; imodel < spice.num_spice_model; imodel++) { + if (spice_model_type == spice.spice_models[imodel].type) { + for (i = 0; i < spice.spice_models[imodel].cnt; i++) { + fprintf(fp, "+ %s_%s[%d]\n", + spice_tb_global_vdd_port_name, + spice.spice_models[imodel].prefix, i); + } + } + } + + fprintf(fp, "\n"); + + return; +} + +void fprint_grid_global_vdds_spice_model(FILE* fp, int x, int y, + enum e_spice_model_type spice_model_type, + t_spice spice) { + int imodel, i; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + fprintf(fp, "***** Global VDD ports of %s *****\n", generate_string_spice_model_type(spice_model_type)); + + for (imodel = 0; imodel < spice.num_spice_model; imodel++) { + /* Bypass non-matched SPICE model */ + if (spice_model_type != spice.spice_models[imodel].type) { + continue; + } + /* Bypass zero-usage spice_model in this grid*/ + if (spice.spice_models[imodel].grid_index_low[x][y] + == spice.spice_models[imodel].grid_index_high[x][y]) { + continue; + } + fprintf(fp, ".global \n"); + for (i = spice.spice_models[imodel].grid_index_low[x][y]; + i < spice.spice_models[imodel].grid_index_high[x][y]; + i++) { + fprintf(fp, "+ gvdd_%s[%d]\n", + spice.spice_models[imodel].prefix, i); + } + } + + fprintf(fp, "\n"); + + return; +} + +void fprint_global_pad_ports_spice_model(FILE* fp, + t_spice spice) { + int imodel, i; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + fprintf(fp, "***** Global input/output ports of I/O Pads *****\n"); + fprintf(fp, ".global \n"); + + for (imodel = 0; imodel < spice.num_spice_model; imodel++) { + switch (spice.spice_models[imodel].type) { + /* Handle multiple INPAD/OUTPAD spice models*/ + case SPICE_MODEL_IOPAD: + for (i = 0; i < spice.spice_models[imodel].cnt; i++) { + fprintf(fp, "+ %s%s[%d]\n", gio_inout_prefix, spice.spice_models[imodel].prefix, i); + } + break; + /* SRAM inputs*/ + case SPICE_MODEL_SRAM: + /* + for (i = 0; i < spice.spice_models[imodel].cnt; i++) { + fprintf(fp, "+ %s[%d]->in\n", spice.spice_models[imodel].prefix, i); + } + fprintf(fp, "+ %s->in\n", spice.spice_models[imodel].prefix); + */ + break; + /* Other types we do not care*/ + case SPICE_MODEL_CHAN_WIRE: + case SPICE_MODEL_WIRE: + case SPICE_MODEL_MUX: + case SPICE_MODEL_LUT: + case SPICE_MODEL_FF: + case SPICE_MODEL_HARDLOGIC: + case SPICE_MODEL_SCFF: + case SPICE_MODEL_INVBUF: + case SPICE_MODEL_PASSGATE: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Unknown type for spice model!\n", + __FILE__, __LINE__); + exit(1); + } + } + + fprintf(fp, "\n"); + + return; +} + +void fprint_spice_global_vdd_switch_boxes(FILE* fp) { + int ix, iy; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + fprintf(fp, "***** Global Vdds for Switch Boxes *****\n"); + fprintf(fp, ".global "); + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 0; iy < (ny + 1); iy++) { + fprintf(fp, "gvdd_sb[%d][%d] ", ix, iy); + } + } + fprintf(fp, "\n"); + + return; +} + +/* Call the sub-circuits for connection boxes */ +void fprint_spice_global_vdd_connection_boxes(FILE* fp) { + int ix, iy; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + fprintf(fp, "***** Global Vdds for Connection Blocks - X channels *****\n"); + fprintf(fp, ".global "); + /* X - channels [1...nx][0..ny]*/ + for (iy = 0; iy < (ny + 1); iy++) { + for (ix = 1; ix < (nx + 1); ix++) { + fprintf(fp, "gvdd_cbx[%d][%d] ", ix, iy); + } + } + fprintf(fp, "\n"); + + fprintf(fp, "***** Global Vdds for Connection Blocks - Y channels *****\n"); + fprintf(fp, ".global "); + /* Y - channels [1...ny][0..nx]*/ + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + fprintf(fp, "gvdd_cby[%d][%d] ", ix, iy); + } + } + fprintf(fp, "\n"); + + return; +} + +void fprint_measure_vdds_spice_model(FILE* fp, + enum e_spice_model_type spice_model_type, + enum e_measure_type meas_type, + int num_cycle, + t_spice spice, + boolean leakage_only) { + int imodel, i; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + for (imodel = 0; imodel < spice.num_spice_model; imodel++) { + if (spice_model_type == spice.spice_models[imodel].type) { + for (i = 0; i < spice.spice_models[imodel].cnt; i++) { + switch (meas_type) { + case SPICE_MEASURE_LEAKAGE_POWER: + if (TRUE == leakage_only) { + fprintf(fp, ".measure tran leakage_power_%s[%d] find p(Vgvdd_%s[%d]) at=0\n", + spice.spice_models[imodel].prefix, i, spice.spice_models[imodel].prefix, i); + } else { + fprintf(fp, ".measure tran leakage_power_%s[%d] avg p(Vgvdd_%s[%d]) from=0 to='clock_period'\n", + spice.spice_models[imodel].prefix, i, spice.spice_models[imodel].prefix, i); + } + break; + case SPICE_MEASURE_DYNAMIC_POWER: + fprintf(fp, ".measure tran dynamic_power_%s[%d] avg p(Vgvdd_%s[%d]) from='clock_period' to='%d*clock_period'\n", + spice.spice_models[imodel].prefix, i, spice.spice_models[imodel].prefix, i, num_cycle); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid meas_type!\n", __FILE__, __LINE__); + exit(1); + } + } + } + } + + /* Measure the total power of this kind of spice model */ + for (imodel = 0; imodel < spice.num_spice_model; imodel++) { + if (spice_model_type == spice.spice_models[imodel].type) { + switch (meas_type) { + case SPICE_MEASURE_LEAKAGE_POWER: + for (i = 0; i < spice.spice_models[imodel].cnt; i++) { + fprintf(fp, ".measure tran leakage_power_%s[0to%d] \n", spice.spice_models[imodel].prefix, i); + if (0 == i) { + fprintf(fp, "+ param = 'leakage_power_%s[%d]'\n", spice.spice_models[imodel].prefix, i); + } else { + fprintf(fp, "+ param = 'leakage_power_%s[%d]+leakage_power_%s[0to%d]'\n", + spice.spice_models[imodel].prefix, i, spice.spice_models[imodel].prefix, i-1); + } + } + /* Spot the total leakage power of this spice model */ + fprintf(fp, ".measure tran total_leakage_power_%s \n", spice.spice_models[imodel].prefix); + fprintf(fp, "+ param = 'leakage_power_%s[0to%d]'\n", + spice.spice_models[imodel].prefix, spice.spice_models[imodel].cnt-1); + break; + case SPICE_MEASURE_DYNAMIC_POWER: + for (i = 0; i < spice.spice_models[imodel].cnt; i++) { + fprintf(fp, ".measure tran dynamic_power_%s[0to%d] \n", spice.spice_models[imodel].prefix, i); + if (0 == i) { + fprintf(fp, "+ param = 'dynamic_power_%s[%d]'\n", spice.spice_models[imodel].prefix, i); + } else { + fprintf(fp, "+ param = 'dynamic_power_%s[%d]+dynamic_power_%s[0to%d]'\n", + spice.spice_models[imodel].prefix, i, spice.spice_models[imodel].prefix, i-1); + } + } + /* Spot the total dynamic power of this spice model */ + fprintf(fp, ".measure tran total_dynamic_power_%s \n", spice.spice_models[imodel].prefix); + fprintf(fp, "+ param = 'dynamic_power_%s[0to%d]'\n", + spice.spice_models[imodel].prefix, spice.spice_models[imodel].cnt-1); + fprintf(fp, ".measure tran total_energy_per_cycle_%s \n", spice.spice_models[imodel].prefix); + fprintf(fp, "+ param = 'dynamic_power_%s[0to%d]*clock_period'\n", + spice.spice_models[imodel].prefix, spice.spice_models[imodel].cnt-1); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid meas_type!\n", __FILE__, __LINE__); + exit(1); + } + } + } + + + return; +} + +void fprint_measure_grid_vdds_spice_model(FILE* fp, int grid_x, int grid_y, + enum e_spice_model_type spice_model_type, + enum e_measure_type meas_type, + int num_cycle, + t_spice spice, + boolean leakage_only) { + int imodel, i; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + for (imodel = 0; imodel < spice.num_spice_model; imodel++) { + if (spice_model_type == spice.spice_models[imodel].type) { + /* Bypass zero-usage spice_model in this grid*/ + if (spice.spice_models[imodel].grid_index_low[grid_x][grid_y] + == spice.spice_models[imodel].grid_index_high[grid_x][grid_y]) { + continue; + } + for (i = spice.spice_models[imodel].grid_index_low[grid_x][grid_y]; + i < spice.spice_models[imodel].grid_index_high[grid_x][grid_y]; + i++) { + switch (meas_type) { + case SPICE_MEASURE_LEAKAGE_POWER: + if (TRUE == leakage_only) { + fprintf(fp, ".measure tran leakage_power_%s[%d] find p(Vgvdd_%s[%d]) at=0\n", + spice.spice_models[imodel].prefix, i, spice.spice_models[imodel].prefix, i); + } else { + fprintf(fp, ".measure tran leakage_power_%s[%d] avg p(Vgvdd_%s[%d]) from=0 to='clock_period'\n", + spice.spice_models[imodel].prefix, i, spice.spice_models[imodel].prefix, i); + } + break; + case SPICE_MEASURE_DYNAMIC_POWER: + fprintf(fp, ".measure tran dynamic_power_%s[%d] avg p(Vgvdd_%s[%d]) from='clock_period' to='%d*clock_period'\n", + spice.spice_models[imodel].prefix, i, spice.spice_models[imodel].prefix, i, num_cycle); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid meas_type!\n", __FILE__, __LINE__); + exit(1); + } + } + } + } + + /* Measure the total power of this kind of spice model */ + for (imodel = 0; imodel < spice.num_spice_model; imodel++) { + if (spice_model_type == spice.spice_models[imodel].type) { + switch (meas_type) { + case SPICE_MEASURE_LEAKAGE_POWER: + /* Bypass zero-usage spice_model in this grid*/ + if (spice.spice_models[imodel].grid_index_low[grid_x][grid_y] + == spice.spice_models[imodel].grid_index_high[grid_x][grid_y]) { + continue; + } + for (i = spice.spice_models[imodel].grid_index_low[grid_x][grid_y]; + i < spice.spice_models[imodel].grid_index_high[grid_x][grid_y]; + i++) { + fprintf(fp, ".measure tran leakage_power_%s[%dto%d] \n", + spice.spice_models[imodel].prefix, + spice.spice_models[imodel].grid_index_low[grid_x][grid_y], + i); + if (spice.spice_models[imodel].grid_index_low[grid_x][grid_y] == i) { + fprintf(fp, "+ param = 'leakage_power_%s[%d]'\n", spice.spice_models[imodel].prefix, i); + } else { + fprintf(fp, "+ param = 'leakage_power_%s[%d]+leakage_power_%s[%dto%d]'\n", + spice.spice_models[imodel].prefix, + i, spice.spice_models[imodel].prefix, + spice.spice_models[imodel].grid_index_low[grid_x][grid_y], + i-1); + } + } + /* Spot the total leakage power of this spice model */ + fprintf(fp, ".measure tran total_leakage_power_%s \n", spice.spice_models[imodel].prefix); + fprintf(fp, "+ param = 'leakage_power_%s[%dto%d]'\n", + spice.spice_models[imodel].prefix, + spice.spice_models[imodel].grid_index_low[grid_x][grid_y], + spice.spice_models[imodel].grid_index_high[grid_x][grid_y]-1); + break; + case SPICE_MEASURE_DYNAMIC_POWER: + /* Bypass zero-usage spice_model in this grid*/ + if (spice.spice_models[imodel].grid_index_low[grid_x][grid_y] + == spice.spice_models[imodel].grid_index_high[grid_x][grid_y]) { + continue; + } + for (i = spice.spice_models[imodel].grid_index_low[grid_x][grid_y]; + i < spice.spice_models[imodel].grid_index_high[grid_x][grid_y]; + i++) { + fprintf(fp, ".measure tran dynamic_power_%s[%dto%d] \n", + spice.spice_models[imodel].prefix, + spice.spice_models[imodel].grid_index_low[grid_x][grid_y], + i); + if (spice.spice_models[imodel].grid_index_low[grid_x][grid_y] == i) { + fprintf(fp, "+ param = 'dynamic_power_%s[%d]'\n", spice.spice_models[imodel].prefix, i); + } else { + fprintf(fp, "+ param = 'dynamic_power_%s[%d]+dynamic_power_%s[%dto%d]'\n", + spice.spice_models[imodel].prefix, i, + spice.spice_models[imodel].prefix, + spice.spice_models[imodel].grid_index_low[grid_x][grid_y], + i-1); + } + } + /* Spot the total dynamic power of this spice model */ + fprintf(fp, ".measure tran total_dynamic_power_%s \n", spice.spice_models[imodel].prefix); + fprintf(fp, "+ param = 'dynamic_power_%s[%dto%d]'\n", + spice.spice_models[imodel].prefix, + spice.spice_models[imodel].grid_index_low[grid_x][grid_y], + spice.spice_models[imodel].grid_index_high[grid_x][grid_y]-1); + fprintf(fp, ".measure tran total_energy_per_cycle_%s \n", spice.spice_models[imodel].prefix); + fprintf(fp, "+ param = 'dynamic_power_%s[%dto%d]*clock_period'\n", + spice.spice_models[imodel].prefix, + spice.spice_models[imodel].grid_index_low[grid_x][grid_y], + spice.spice_models[imodel].grid_index_high[grid_x][grid_y]-1); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid meas_type!\n", __FILE__, __LINE__); + exit(1); + } + } + } + + + return; +} + + +/***** Print (call) the defined grids *****/ +void fprint_call_defined_grids(FILE* fp) { + int ix, iy; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* Normal Grids */ + for (ix = 1; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + assert(IO_TYPE != grid[ix][iy].type); + fprintf(fp, "Xgrid[%d][%d] ", ix, iy); + fprintf(fp, "\n"); + fprint_grid_pins(fp, ix, iy, 1); + fprintf(fp, "+ "); + fprintf(fp, "gvdd 0 grid[%d][%d]\n", ix, iy); /* Call the name of subckt */ + } + } + + /* IO Grids */ + /* LEFT side */ + ix = 0; + for (iy = 1; iy < (ny + 1); iy++) { + assert(IO_TYPE == grid[ix][iy].type); + fprintf(fp, "Xgrid[%d][%d] ", ix, iy); + fprintf(fp, "\n"); + fprint_io_grid_pins(fp, ix, iy, 1); + fprintf(fp, "+ "); + /* Connect to a speical vdd port for statistics power */ + fprintf(fp, "gvdd_io 0 grid[%d][%d]\n", ix, iy); /* Call the name of subckt */ + } + + /* RIGHT side */ + ix = nx + 1; + for (iy = 1; iy < (ny + 1); iy++) { + assert(IO_TYPE == grid[ix][iy].type); + fprintf(fp, "Xgrid[%d][%d] ", ix, iy); + fprintf(fp, "\n"); + fprint_io_grid_pins(fp, ix, iy, 1); + fprintf(fp, "+ "); + /* Connect to a speical vdd port for statistics power */ + fprintf(fp, "gvdd_io 0 grid[%d][%d]\n", ix, iy); /* Call the name of subckt */ + } + + /* BOTTOM side */ + iy = 0; + for (ix = 1; ix < (nx + 1); ix++) { + assert(IO_TYPE == grid[ix][iy].type); + fprintf(fp, "Xgrid[%d][%d] ", ix, iy); + fprintf(fp, "\n"); + fprint_io_grid_pins(fp, ix, iy, 1); + fprintf(fp, "+ "); + /* Connect to a speical vdd port for statistics power */ + fprintf(fp, "gvdd_io 0 grid[%d][%d]\n", ix, iy); /* Call the name of subckt */ + } + + /* TOP side */ + iy = ny + 1; + for (ix = 1; ix < (nx + 1); ix++) { + assert(IO_TYPE == grid[ix][iy].type); + fprintf(fp, "Xgrid[%d][%d] ", ix, iy); + fprintf(fp, "\n"); + fprint_io_grid_pins(fp, ix, iy, 1); + fprintf(fp, "+ "); + /* Connect to a speical vdd port for statistics power */ + fprintf(fp, "gvdd_io 0 grid[%d][%d]\n", ix, iy); /* Call the name of subckt */ + } + + return; +} + +/* Call defined channels. + * Ensure the port name here is co-herent to other sub-circuits(SB,CB,grid)!!! + */ +void fprint_call_defined_one_channel(FILE* fp, + t_rr_type chan_type, + int x, int y, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices) { + int itrack; + int chan_width = 0; + t_rr_node** chan_rr_nodes = NULL; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((CHANX == chan_type)||(CHANY == chan_type)); + /* check x*/ + assert((!(0 > x))&&(x < (nx + 1))); + /* check y*/ + assert((!(0 > y))&&(y < (ny + 1))); + + /* Collect rr_nodes for Tracks for chanx[ix][iy] */ + chan_rr_nodes = get_chan_rr_nodes(&chan_width, chan_type, x, y, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + + /* Call the define sub-circuit */ + fprintf(fp, "X%s[%d][%d] ", + convert_chan_type_to_string(chan_type), + x, y); + fprintf(fp, "\n"); + /* LEFT/BOTTOM side port of CHANX/CHANY */ + /* We apply an opposite port naming rule than function: fprint_routing_chan_subckt + * In top-level netlists, we follow the same port name as switch blocks and connection blocks + * When a track is in INC_DIRECTION, the LEFT/BOTTOM port would be an output of a switch block + * When a track is in DEC_DIRECTION, the LEFT/BOTTOM port would be an input of a switch block + */ + for (itrack = 0; itrack < chan_width; itrack++) { + fprintf(fp, "+ "); + switch (chan_rr_nodes[itrack]->direction) { + case INC_DIRECTION: + fprintf(fp, "%s[%d][%d]_out[%d] ", + convert_chan_type_to_string(chan_type), + x, y, itrack); + fprintf(fp, "\n"); + break; + case DEC_DIRECTION: + fprintf(fp, "%s[%d][%d]_in[%d] ", + convert_chan_type_to_string(chan_type), + x, y, itrack); + fprintf(fp, "\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of %s[%d][%d]_track[%d]!\n", + __FILE__, __LINE__, + convert_chan_type_to_string(chan_type), + x, y, itrack); + exit(1); + } + } + /* RIGHT/TOP side port of CHANX/CHANY */ + /* We apply an opposite port naming rule than function: fprint_routing_chan_subckt + * In top-level netlists, we follow the same port name as switch blocks and connection blocks + * When a track is in INC_DIRECTION, the RIGHT/TOP port would be an input of a switch block + * When a track is in DEC_DIRECTION, the RIGHT/TOP port would be an output of a switch block + */ + for (itrack = 0; itrack < chan_width; itrack++) { + fprintf(fp, "+ "); + switch (chan_rr_nodes[itrack]->direction) { + case INC_DIRECTION: + fprintf(fp, "%s[%d][%d]_in[%d] ", + convert_chan_type_to_string(chan_type), + x, y, itrack); + fprintf(fp, "\n"); + break; + case DEC_DIRECTION: + fprintf(fp, "%s[%d][%d]_out[%d] ", + convert_chan_type_to_string(chan_type), + x, y, itrack); + fprintf(fp, "\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of %s[%d][%d]_track[%d]!\n", + __FILE__, __LINE__, + convert_chan_type_to_string(chan_type), + x, y, itrack); + exit(1); + } + } + /* output at middle point */ + for (itrack = 0; itrack < chan_width; itrack++) { + fprintf(fp, "+ "); + fprintf(fp, "%s[%d][%d]_midout[%d] ", + convert_chan_type_to_string(chan_type), + x, y, itrack); + fprintf(fp, "\n"); + } + fprintf(fp, "+ gvdd 0 %s[%d][%d]\n", + convert_chan_type_to_string(chan_type), + x, y); + + /* Free */ + my_free(chan_rr_nodes); + + return; +} + +/* Call the sub-circuits for channels : Channel X and Channel Y*/ +void fprint_call_defined_channels(FILE* fp, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices) { + int ix, iy; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* Channel X */ + for (iy = 0; iy < (ny + 1); iy++) { + for (ix = 1; ix < (nx + 1); ix++) { + fprint_call_defined_one_channel(fp, CHANX, ix, iy, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + } + } + + /* Channel Y */ + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + fprint_call_defined_one_channel(fp, CHANY, ix, iy, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + } + } + + return; +} + +/* Call the defined sub-circuit of connection box + * TODO: actually most of this function is copied from + * spice_routing.c : fprint_conneciton_box_interc + * Should be more clever to use the original function + */ +void fprint_call_defined_one_connection_box(FILE* fp, + t_cb cur_cb_info) { + int itrack, inode, side; + int side_cnt = 0; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > cur_cb_info.x))&&(!(cur_cb_info.x > (nx + 1)))); + assert((!(0 > cur_cb_info.y))&&(!(cur_cb_info.y > (ny + 1)))); + + /* Print the definition of subckt*/ + /* Identify the type of connection box */ + switch(cur_cb_info.type) { + case CHANX: + fprintf(fp, "Xcbx[%d][%d] ", cur_cb_info.x, cur_cb_info.y); + break; + case CHANY: + fprintf(fp, "Xcby[%d][%d] ", cur_cb_info.x, cur_cb_info.y); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); + exit(1); + } + + fprintf(fp, "\n"); + + /* Print the ports of channels*/ + /* connect to the mid point of a track*/ + side_cnt = 0; + for (side = 0; side < cur_cb_info.num_sides; side++) { + /* Bypass side with zero channel width */ + if (0 == cur_cb_info.chan_width[side]) { + continue; + } + assert (0 < cur_cb_info.chan_width[side]); + side_cnt++; + for (itrack = 0; itrack < cur_cb_info.chan_width[side]; itrack++) { + fprintf(fp, "+ "); + fprintf(fp, "%s[%d][%d]_midout[%d] ", + convert_chan_type_to_string(cur_cb_info.type), + cur_cb_info.x, cur_cb_info.y, itrack); + fprintf(fp, "\n"); + } + } + /*check side_cnt */ + assert(1 == side_cnt); + + side_cnt = 0; + /* Print the ports of grids*/ + /* only check ipin_rr_nodes of cur_cb_info */ + for (side = 0; side < cur_cb_info.num_sides; side++) { + /* Bypass side with zero IPINs*/ + if (0 == cur_cb_info.num_ipin_rr_nodes[side]) { + continue; + } + side_cnt++; + assert(0 < cur_cb_info.num_ipin_rr_nodes[side]); + assert(NULL != cur_cb_info.ipin_rr_node[side]); + for (inode = 0; inode < cur_cb_info.num_ipin_rr_nodes[side]; inode++) { + fprintf(fp, "+ "); + /* Print each INPUT Pins of a grid */ + fprint_grid_side_pin_with_given_index(fp, cur_cb_info.ipin_rr_node[side][inode]->ptc_num, + cur_cb_info.ipin_rr_node_grid_side[side][inode], + cur_cb_info.ipin_rr_node[side][inode]->xlow, + cur_cb_info.ipin_rr_node[side][inode]->ylow); + fprintf(fp, "\n"); + } + } + /* Make sure only 2 sides of IPINs are printed */ + assert((1 == side_cnt)||(2 == side_cnt)); + + fprintf(fp, "+ "); + /* Identify the type of connection box */ + switch(cur_cb_info.type) { + case CHANX: + /* Need split vdd port for each Connection Box */ + fprintf(fp, "gvdd_cbx[%d][%d] 0 ", cur_cb_info.x, cur_cb_info.y); + fprintf(fp, "cbx[%d][%d]\n", cur_cb_info.x, cur_cb_info.y); + break; + case CHANY: + /* Need split vdd port for each Connection Box */ + fprintf(fp, "gvdd_cby[%d][%d] 0 ", cur_cb_info.x, cur_cb_info.y); + fprintf(fp, "cby[%d][%d]\n", cur_cb_info.x, cur_cb_info.y); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); + exit(1); + } + + /* Free */ + + return; +} + +/* Call the sub-circuits for connection boxes */ +void fprint_call_defined_connection_boxes(FILE* fp) { + int ix, iy; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* X - channels [1...nx][0..ny]*/ + for (iy = 0; iy < (ny + 1); iy++) { + for (ix = 1; ix < (nx + 1); ix++) { + fprint_call_defined_one_connection_box(fp, cbx_info[ix][iy]); + } + } + /* Y - channels [1...ny][0..nx]*/ + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + fprint_call_defined_one_connection_box(fp, cby_info[ix][iy]); + } + } + + return; +} + +/* Call the defined switch box sub-circuit + * Critical difference between this function and + * spice_routing.c : fprint_routing_switch_box_subckt + * Whether a channel node of a Switch block should be input or output depends on it location: + * For example, a channel chanX INC_DIRECTION on the right side of a SB, it is marked as an input + * In fprint_routing_switch_box_subckt: it is marked as an output. + * For channels chanY with INC_DIRECTION on the top/bottom side, they should be marked as inputs + * For channels chanY with DEC_DIRECTION on the top/bottom side, they should be marked as outputs + * For channels chanX with INC_DIRECTION on the left/right side, they should be marked as inputs + * For channels chanX with DEC_DIRECTION on the left/right side, they should be marked as outputs + */ +void fprint_call_defined_one_switch_box(FILE* fp, + t_sb cur_sb_info) { + int ix, iy, side, itrack, inode; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > cur_sb_info.x))&&(!(cur_sb_info.x > (nx + 1)))); + assert((!(0 > cur_sb_info.y))&&(!(cur_sb_info.y > (ny + 1)))); + + fprintf(fp, "Xsb[%d][%d] ", cur_sb_info.x, cur_sb_info.y); + fprintf(fp, "\n"); + + for (side = 0; side < cur_sb_info.num_sides; side++) { + determine_sb_port_coordinator(cur_sb_info, side, &ix, &iy); + + fprintf(fp, "+ "); + for (itrack = 0; itrack < cur_sb_info.chan_width[side]; itrack++) { + switch (cur_sb_info.chan_rr_node_direction[side][itrack]) { + case OUT_PORT: + fprintf(fp, "%s[%d][%d]_out[%d] ", + convert_chan_type_to_string(cur_sb_info.chan_rr_node[side][itrack]->type), + ix, iy, itrack); + break; + case IN_PORT: + fprintf(fp, "%s[%d][%d]_in[%d] ", + convert_chan_type_to_string(cur_sb_info.chan_rr_node[side][itrack]->type), + ix, iy, itrack); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of sb[%d][%d] side[%d] track[%d]!\n", + __FILE__, __LINE__, cur_sb_info.x, cur_sb_info.y, side, itrack); + exit(1); + } + } + fprintf(fp, "\n"); + fprintf(fp, "+ "); + /* Dump OPINs of adjacent CLBs */ + for (inode = 0; inode < cur_sb_info.num_opin_rr_nodes[side]; inode++) { + fprint_grid_side_pin_with_given_index(fp, cur_sb_info.opin_rr_node[side][inode]->ptc_num, + cur_sb_info.opin_rr_node_grid_side[side][inode], + cur_sb_info.opin_rr_node[side][inode]->xlow, + cur_sb_info.opin_rr_node[side][inode]->ylow); + } + fprintf(fp, "\n"); + } + + + /* Connect to separate vdd port for each switch box??? */ + fprintf(fp, "+ "); + fprintf(fp, " gvdd_sb[%d][%d] 0 sb[%d][%d]\n", + cur_sb_info.x, cur_sb_info.y, cur_sb_info.x, cur_sb_info.y); + + /* Free */ + + return; +} + +void fprint_call_defined_switch_boxes(FILE* fp) { + int ix, iy; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 0; iy < (ny + 1); iy++) { + fprint_call_defined_one_switch_box(fp, sb_info[ix][iy]); + } + } + + return; +} + +/* Print stimulations for floating ports in Grid + * Some ports of CLB or I/O Pads is floating. + * There are two cases : + * 1. Their corresponding rr_node (SOURE or OPIN) has 0 fan-out. + * 2. Their corresponding rr_node (SINK or IPIN) has 0 fan-in. + * In these cases, we short connect them to global GND. + */ +void fprint_grid_float_port_stimulation(FILE* fp) { + int inode; + int num_float_port = 0; + int port_x, port_y, port_height; + int side, class_id, pin_index, pin_written_times; + t_type_ptr type = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Search all rr_nodes */ + for (inode = 0; inode < num_rr_nodes; inode++) { + switch (rr_node[inode].type) { + case SOURCE: + case OPIN: + /* Make sure 0 fan-in, 1 fan-in is connected to SOURCE */ + assert((0 == rr_node[inode].fan_in)||(1 == rr_node[inode].fan_in)); + if (1 == rr_node[inode].fan_in) { + assert(SOURCE == rr_node[rr_node[inode].prev_node].type); + } + /* Check if there is 0 fan-out */ + if (0 == rr_node[inode].num_edges) { + port_x = rr_node[inode].xlow; + port_y = rr_node[inode].ylow; + port_height = grid[port_x][port_y].offset; + port_y = port_y + port_height; + type = grid[port_x][port_y].type; + assert(NULL != type); + /* Get pin information */ + pin_index = rr_node[inode].ptc_num; + class_id = type->pin_class[pin_index]; + assert(DRIVER == type->class_inf[class_id].type); + pin_written_times = 0; + for (side = 0; side < 4; side++) { + /* Special Care for I/O pad */ + if (IO_TYPE == type) { + side = determine_io_grid_side(port_x, port_y); + } + if (1 == type->pinloc[port_height][side][pin_index]) { + fprintf(fp, "Vfloat_port_%d grid[%d][%d]_pin[%d][%d][%d] 0 0\n", + num_float_port, port_x, port_y, port_height, side, pin_index); + pin_written_times++; + num_float_port++; + } + /* Special Care for I/O pad */ + if (IO_TYPE == type) { + break; + } + } + assert(1 == pin_written_times); + } + break; + case SINK: + case IPIN: + /* Make sure 0 fan-out, 1 fan-out is connected to SINK */ + assert((0 == rr_node[inode].num_edges)||(1 == rr_node[inode].num_edges)); + if (1 == rr_node[inode].num_edges) { + assert(SINK == rr_node[rr_node[inode].edges[0]].type); + } + /* Check if there is 0 fan-out */ + if (0 == rr_node[inode].fan_in) { + port_x = rr_node[inode].xlow; + port_y = rr_node[inode].ylow; + port_height = grid[port_x][port_y].offset; + port_y = port_y + port_height; + type = grid[port_x][port_y + port_height].type; + assert(NULL != type); + /* Get pin information */ + pin_index = rr_node[inode].ptc_num; + class_id = type->pin_class[pin_index]; + assert(RECEIVER == type->class_inf[class_id].type); + pin_written_times = 0; + for (side = 0; side < 4; side++) { + /* Special Care for I/O pad */ + if (IO_TYPE == type) { + side = determine_io_grid_side(port_x, port_y); + } + if (1 == type->pinloc[port_height][side][pin_index]) { + fprintf(fp, "Vfloat_port_%d grid[%d][%d]_pin[%d][%d][%d] 0 0\n", + num_float_port, port_x, port_y, port_height, side, pin_index); + pin_written_times++; + num_float_port++; + } + /* Special Care for I/O pad */ + if (IO_TYPE == type) { + break; + } + } + assert(1 == pin_written_times); + } + break; + case CHANX: + case CHANY: + /*TODO: check 0 fan-in, fan-out channel*/ + case INTRA_CLUSTER_EDGE: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid rr_node type!\n", + __FILE__, __LINE__); + exit(1); + } + } + + vpr_printf(TIO_MESSAGE_INFO, "Connect %d floating grid pin to global gnd.\n", num_float_port); + + return; +} + +void fprint_one_design_param_w_wo_variation(FILE* fp, + char* param_name, + float avg_val, + t_spice_mc_variation_params variation_params) { + /* Check */ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d]) FileHandle is NULL!\n", + __FILE__,__LINE__); + exit(1); + } + + fprintf(fp,".param %s=", param_name); + if (FALSE == variation_params.variation_on) { + fprintf(fp, "%g", avg_val); + /* We do not allow any negative value exist in the variation, + * This could be too tight, could be removed + */ + } else if (TRUE == check_negative_variation(avg_val, variation_params)) { + fprintf(fp, "%g", avg_val); + } else { + fprintf(fp, "agauss(%g, '%g*%g', %d)", + avg_val, + variation_params.abs_variation, avg_val, + variation_params.num_sigma); + } + fprintf(fp, "\n"); + + return; +} + + +/* Print Technology Library and Design Parameters*/ +void fprint_tech_lib(FILE* fp, + t_spice_mc_variation_params cmos_variation_params, + t_spice_tech_lib tech_lib) { + /* Standard transistors*/ + t_spice_transistor_type* nmos_trans = NULL; + t_spice_transistor_type* pmos_trans = NULL; + + /* I/O transistors*/ + t_spice_transistor_type* io_nmos_trans = NULL; + t_spice_transistor_type* io_pmos_trans = NULL; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d]) FileHandle is NULL!\n", + __FILE__,__LINE__); + exit(1); + } + /* Include Technology Library*/ + fprintf(fp, "****** Include Technology Library ******\n"); + if (SPICE_LIB_INDUSTRY == tech_lib.type) { + fprintf(fp, ".lib \'%s\' %s\n", tech_lib.path, tech_lib.transistor_type); + } else { + fprintf(fp, ".include \'%s\'\n", tech_lib.path); + } + + /* Print Transistor parameters*/ + /* Define the basic transistor parameters: nl, pl, wn, wp, pn_ratio*/ + fprintf(fp, "****** Transistor Parameters ******\n"); + fprintf(fp,".param beta=%g\n",tech_lib.pn_ratio); + /* Make sure we have only 2 transistor*/ + assert((2 == tech_lib.num_transistor_type)||(4 == tech_lib.num_transistor_type)); + /* Find NMOS*/ + nmos_trans = find_mosfet_tech_lib(tech_lib,SPICE_TRANS_NMOS); + if (NULL == nmos_trans) { + vpr_printf(TIO_MESSAGE_ERROR,"NMOS transistor is not defined in architecture XML!\n"); + exit(1); + } + + fprint_one_design_param_w_wo_variation(fp, "nl", nmos_trans->chan_length, cmos_variation_params); + fprint_one_design_param_w_wo_variation(fp, "wn", nmos_trans->min_width, cmos_variation_params); + + /* Find PMOS*/ + pmos_trans = find_mosfet_tech_lib(tech_lib,SPICE_TRANS_PMOS); + if (NULL == pmos_trans) { + vpr_printf(TIO_MESSAGE_ERROR,"PMOS transistor is not defined in architecture XML!\n"); + exit(1); + } + + fprint_one_design_param_w_wo_variation(fp, "pl", pmos_trans->chan_length, cmos_variation_params); + fprint_one_design_param_w_wo_variation(fp, "wp", pmos_trans->min_width, cmos_variation_params); + + /* Print I/O NMOS and PMOS */ + io_nmos_trans = find_mosfet_tech_lib(tech_lib, SPICE_TRANS_IO_NMOS); + if ((NULL == io_nmos_trans) && (4 == tech_lib.num_transistor_type)) { + vpr_printf(TIO_MESSAGE_WARNING,"I/O NMOS transistor is not defined in architecture XML!\n"); + exit(1); + } + if (NULL != io_nmos_trans) { + fprint_one_design_param_w_wo_variation(fp, "io_nl", io_nmos_trans->chan_length, cmos_variation_params); + fprint_one_design_param_w_wo_variation(fp, "io_wn", io_nmos_trans->min_width, cmos_variation_params); + } + + io_pmos_trans = find_mosfet_tech_lib(tech_lib,SPICE_TRANS_IO_PMOS); + if ((NULL == io_pmos_trans) && (4 == tech_lib.num_transistor_type)) { + vpr_printf(TIO_MESSAGE_WARNING,"I/O PMOS transistor is not defined in architecture XML!\n"); + exit(1); + } + if (NULL != io_nmos_trans) { + fprint_one_design_param_w_wo_variation(fp, "io_pl", io_pmos_trans->chan_length, cmos_variation_params); + fprint_one_design_param_w_wo_variation(fp, "io_wp", io_pmos_trans->min_width, cmos_variation_params); + } + + /* Print nominal Vdd */ + fprintf(fp, ".param vsp=%g\n", tech_lib.nominal_vdd); + /* Print I/O VDD */ + fprintf(fp, ".param io_vsp=%g\n", tech_lib.io_vdd); + + return; +} + +/* Print all the circuit design parameters */ +void fprint_spice_circuit_param(FILE* fp, + t_spice_mc_params mc_params, + int num_spice_models, + t_spice_model* spice_model) { + int imodel; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!", + __FILE__, __LINE__); + exit(1); + } + + fprintf(fp, "***** Parameters for Circuits *****\n"); + for (imodel = 0; imodel < num_spice_models; imodel++) { + fprintf(fp, "***** Parameters for SPICE MODEL: %s *****\n", + spice_model[imodel].name); + /* Regular design parameters: input buf sizes, output buf sizes*/ + if ((NULL != spice_model[imodel].input_buffer) + &&(TRUE == spice_model[imodel].input_buffer->exist)) { + fprint_one_design_param_w_wo_variation(fp, + my_strcat(spice_model[imodel].name, design_param_postfix_input_buf_size), + spice_model[imodel].input_buffer->size, + mc_params.cmos_variation); + } + + if ((NULL != spice_model[imodel].output_buffer) + &&(TRUE == spice_model[imodel].output_buffer->exist)) { + fprint_one_design_param_w_wo_variation(fp, + my_strcat(spice_model[imodel].name, design_param_postfix_output_buf_size), + spice_model[imodel].output_buffer->size, + mc_params.cmos_variation); + } + + if (NULL != spice_model[imodel].pass_gate_logic) { + fprint_one_design_param_w_wo_variation(fp, + my_strcat(spice_model[imodel].name, design_param_postfix_pass_gate_logic_pmos_size), + spice_model[imodel].pass_gate_logic->pmos_size, + mc_params.cmos_variation); + fprint_one_design_param_w_wo_variation(fp, + my_strcat(spice_model[imodel].name, design_param_postfix_pass_gate_logic_nmos_size), + spice_model[imodel].pass_gate_logic->nmos_size, + mc_params.cmos_variation); + } + + /* Exclusive parameters WIREs */ + if ((SPICE_MODEL_CHAN_WIRE == spice_model[imodel].type) + ||(SPICE_MODEL_WIRE == spice_model[imodel].type)) { + fprint_one_design_param_w_wo_variation(fp, + my_strcat(spice_model[imodel].name, design_param_postfix_wire_param_res_val), + spice_model[imodel].wire_param->res_val, + mc_params.wire_variation); + fprint_one_design_param_w_wo_variation(fp, + my_strcat(spice_model[imodel].name, design_param_postfix_wire_param_cap_val), + spice_model[imodel].wire_param->cap_val, + mc_params.wire_variation); + } + + /* We care the spice models built with RRAMs */ + if (SPICE_MODEL_DESIGN_RRAM == spice_model[imodel].design_tech) { + /* Print Ron */ + fprint_one_design_param_w_wo_variation(fp, + my_strcat(spice_model[imodel].name, design_param_postfix_rram_ron), + spice_model[imodel].design_tech_info.ron, + mc_params.rram_variation); + /* Print Roff */ + fprint_one_design_param_w_wo_variation(fp, + my_strcat(spice_model[imodel].name, design_param_postfix_rram_roff), + spice_model[imodel].design_tech_info.roff, + mc_params.rram_variation); + /* Print Wprog_set_nmos */ + fprint_one_design_param_w_wo_variation(fp, + my_strcat(spice_model[imodel].name, design_param_postfix_rram_wprog_set_nmos), + spice_model[imodel].design_tech_info.wprog_set_nmos, + mc_params.cmos_variation); + /* Print Wprog_set_pmos */ + fprint_one_design_param_w_wo_variation(fp, + my_strcat(spice_model[imodel].name, design_param_postfix_rram_wprog_set_pmos), + spice_model[imodel].design_tech_info.wprog_set_pmos, + mc_params.cmos_variation); + /* Print Wprog_reset_nmos */ + fprint_one_design_param_w_wo_variation(fp, + my_strcat(spice_model[imodel].name, design_param_postfix_rram_wprog_reset_nmos), + spice_model[imodel].design_tech_info.wprog_reset_nmos, + mc_params.cmos_variation); + /* Print Wprog_reset_pmos */ + fprint_one_design_param_w_wo_variation(fp, + my_strcat(spice_model[imodel].name, design_param_postfix_rram_wprog_reset_pmos), + spice_model[imodel].design_tech_info.wprog_reset_pmos, + mc_params.cmos_variation); + } + } + + return; +} + +void fprint_spice_netlist_measurement_one_design_param(FILE* fp, + char* param_name) { + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!", + __FILE__, __LINE__); + exit(1); + } + + fprintf(fp, ".meas tran actual_%s param='%s'\n", + param_name, param_name); + + return; +} + +void fprint_spice_netlist_generic_measurements(FILE* fp, + t_spice_mc_params mc_params, + int num_spice_models, + t_spice_model* spice_model) { + + int imodel; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!", + __FILE__, __LINE__); + exit(1); + } + + fprintf(fp, "***** Generic Measurements for Circuit Parameters *****\n"); + + if ((FALSE == mc_params.cmos_variation.variation_on) + &&(FALSE == mc_params.rram_variation.variation_on)) { + return; + } + + for (imodel = 0; imodel < num_spice_models; imodel++) { + fprintf(fp, "***** Measurements for Parameters for SPICE MODEL: %s *****\n", + spice_model[imodel].name); + /* Regular design parameters: input buf sizes, output buf sizes*/ + if ((NULL != spice_model[imodel].input_buffer) + &&(TRUE == spice_model[imodel].input_buffer->exist)) { + fprint_spice_netlist_measurement_one_design_param(fp, + my_strcat(spice_model[imodel].name, design_param_postfix_input_buf_size)); + } + + if ((NULL != spice_model[imodel].output_buffer) + &&(TRUE == spice_model[imodel].output_buffer->exist)) { + fprint_spice_netlist_measurement_one_design_param(fp, + my_strcat(spice_model[imodel].name, design_param_postfix_output_buf_size)); + } + + if (NULL != spice_model[imodel].pass_gate_logic) { + fprint_spice_netlist_measurement_one_design_param(fp, + my_strcat(spice_model[imodel].name, design_param_postfix_pass_gate_logic_pmos_size)); + fprint_spice_netlist_measurement_one_design_param(fp, + my_strcat(spice_model[imodel].name, design_param_postfix_pass_gate_logic_nmos_size)); + } + + /* Exclusive parameters WIREs */ + if ((SPICE_MODEL_CHAN_WIRE == spice_model[imodel].type) + ||(SPICE_MODEL_WIRE == spice_model[imodel].type)) { + fprint_spice_netlist_measurement_one_design_param(fp, + my_strcat(spice_model[imodel].name, design_param_postfix_wire_param_res_val)); + fprint_spice_netlist_measurement_one_design_param(fp, + my_strcat(spice_model[imodel].name, design_param_postfix_wire_param_cap_val)); + } + + /* We care the spice models built with RRAMs */ + if (SPICE_MODEL_DESIGN_RRAM == spice_model[imodel].design_tech) { + /* Print Ron */ + fprint_spice_netlist_measurement_one_design_param(fp, + my_strcat(spice_model[imodel].name, design_param_postfix_rram_ron)); + /* Print Roff */ + fprint_spice_netlist_measurement_one_design_param(fp, + my_strcat(spice_model[imodel].name, design_param_postfix_rram_roff)); + /* Print Wprog_set_nmos */ + fprint_spice_netlist_measurement_one_design_param(fp, + my_strcat(spice_model[imodel].name, design_param_postfix_rram_wprog_set_nmos)); + /* Print Wprog_set_pmos */ + fprint_spice_netlist_measurement_one_design_param(fp, + my_strcat(spice_model[imodel].name, design_param_postfix_rram_wprog_set_pmos)); + /* Print Wprog_reset_nmos */ + fprint_spice_netlist_measurement_one_design_param(fp, + my_strcat(spice_model[imodel].name, design_param_postfix_rram_wprog_reset_nmos)); + /* Print Wprog_reset_pmos */ + fprint_spice_netlist_measurement_one_design_param(fp, + my_strcat(spice_model[imodel].name, design_param_postfix_rram_wprog_reset_pmos)); + } + } + + + return; +} + +/* This function may expand. + * It prints temperature, and options for a SPICE simulation + */ +void fprint_spice_options(FILE* fp, + t_spice_params spice_params) { + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!",__FILE__, __LINE__); + exit(1); + } + + /* Temperature */ + fprintf(fp, ".temp %d\n", spice_params.sim_temp); + + /* Options: print capacitances of all nodes */ + if (TRUE == spice_params.captab) { + fprintf(fp, ".option captab\n"); + } + /* Add post could make SPICE very slow for large benchmarks!!! Be careful*/ + if (TRUE == spice_params.post) { + fprintf(fp, ".option post\n"); + } + /* Use fast */ + if (TRUE == spice_params.fast) { + fprintf(fp, ".option fast\n"); + } + + return; +} + +/* This function may expand. + * It prints include paramters for SPICE netlists + */ +void fprint_spice_include_param_headers(FILE* fp, + char* include_dir_path) { + char* temp_include_file_path = NULL; + char* formatted_include_dir_path = format_dir_path(include_dir_path); + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!",__FILE__, __LINE__); + exit(1); + } + + /* Include headers for circuit designs, measurements and stimulates */ + + fprintf(fp, "****** Include Header file: circuit design parameters *****\n"); + temp_include_file_path = my_strcat(formatted_include_dir_path, design_param_header_file_name); + fprintf(fp, ".include \'%s\'\n", temp_include_file_path); + my_free(temp_include_file_path); + + fprintf(fp, "****** Include Header file: measurement parameters *****\n"); + temp_include_file_path = my_strcat(formatted_include_dir_path, meas_header_file_name); + fprintf(fp, ".include \'%s\'\n", temp_include_file_path); + my_free(temp_include_file_path); + + fprintf(fp, "****** Include Header file: stimulation parameters *****\n"); + temp_include_file_path = my_strcat(formatted_include_dir_path, stimu_header_file_name); + fprintf(fp, ".include \'%s\'\n", temp_include_file_path); + my_free(temp_include_file_path); + + return; +} + + +/* This function may expand. + * It prints include sub-circuit SPICE netlists + */ +void fprint_spice_include_key_subckts(FILE* fp, + char* subckt_dir_path) { + char* temp_include_file_path = NULL; + char* formatted_subckt_dir_path = format_dir_path(subckt_dir_path); + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!",__FILE__, __LINE__); + exit(1); + } + + /* Include necessary sub-circuits */ + fprintf(fp, "****** Include subckt netlists: NMOS and PMOS *****\n"); + temp_include_file_path = my_strcat(formatted_subckt_dir_path, nmos_pmos_spice_file_name); + fprintf(fp, ".include \'%s\'\n", temp_include_file_path); + my_free(temp_include_file_path); + + if (1 == rram_design_tech) { + fprintf(fp, "****** Include subckt netlists: RRAM behavior VerilogA model *****\n"); + /* This is a HSPICE Bug! When the verilogA file contain a dir_path, the sim results become weired! */ + /* + temp_include_file_path = my_strcat(formatted_subckt_dir_path, rram_veriloga_file_name); + fprintf(fp, ".hdl \'%s\'\n", temp_include_file_path); + my_free(temp_include_file_path); + */ + fprintf(fp, ".hdl \'%s\'\n", rram_veriloga_file_name); + } + + fprintf(fp, "****** Include subckt netlists: Inverters, Buffers *****\n"); + temp_include_file_path = my_strcat(formatted_subckt_dir_path, basics_spice_file_name); + fprintf(fp, ".include \'%s\'\n", temp_include_file_path); + my_free(temp_include_file_path); + + fprintf(fp, "****** Include subckt netlists: Multiplexers *****\n"); + temp_include_file_path = my_strcat(formatted_subckt_dir_path, muxes_spice_file_name); + fprintf(fp, ".include \'%s\'\n", temp_include_file_path); + my_free(temp_include_file_path); + + fprintf(fp, "****** Include subckt netlists: Wires *****\n"); + temp_include_file_path = my_strcat(formatted_subckt_dir_path, wires_spice_file_name); + fprintf(fp, ".include \'%s\'\n", temp_include_file_path); + my_free(temp_include_file_path); + + return; +} + +void fprint_voltage_pulse_params(FILE* fp, + int init_val, + float density, + float probability) { + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!",__FILE__, __LINE__); + exit(1); + } + + /* TODO: check codes for density and probability, init_val */ + /* If density = 0, this is a constant signal */ + if (0. == density) { + if (0. == probability) { + fprintf(fp, "+ 0\n"); + } else { + fprintf(fp, "+ vsp\n"); + } + return; + } + + if (0 == init_val) { + fprintf(fp, "+ pulse(0 vsp 'clock_period' \n"); + } else { + fprintf(fp, "+ pulse(vsp 0 'clock_period' \n"); + } + /* + fprintf(fp, "+ 'input_slew_pct_rise*%g*clock_period' 'input_slew_pct_fall*%g*clock_period'\n", + 2./density, 2./density); + */ + /* TODO: Think about a reasonable slew for signals with diverse density */ + fprintf(fp, "+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'\n"); + fprintf(fp, "+ '%g*%g*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '%g*clock_period')\n", + probability, 2./density, 2./density); + + return; +} + + +void fprint_spice_netlist_transient_setting(FILE* fp, + t_spice spice, + int num_sim_clock_cycles, + boolean leakage_only) { + int num_clock_cycle = spice.spice_params.meas_params.sim_num_clock_cycle + 1; + + /* Overwrite the sim if auto is turned on */ + if ((TRUE == spice.spice_params.meas_params.auto_select_sim_num_clk_cycle) + &&(num_sim_clock_cycles < num_clock_cycle)) { + num_clock_cycle = num_sim_clock_cycles; + } + /* + if (TRUE == spice.spice_params.meas_params.auto_select_sim_num_clk_cycle) { + assert(!(num_sim_clock_cycles > num_clock_cycle)); + } + */ + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!",__FILE__, __LINE__); + exit(1); + } + + /* Leakage power only, use a simplified tran sim*/ + if (TRUE == leakage_only) { + fprintf(fp, "***** Transient simulation only for leakage power *****\n"); + } else { + fprintf(fp, "***** %d Clock Simulation, accuracy=%g *****\n", + num_clock_cycle, spice.spice_params.meas_params.accuracy); + } + + /* Determine the transistion time to simulate */ + switch (spice.spice_params.meas_params.accuracy_type) { + case SPICE_ABS: + fprintf(fp, ".tran %g ", + spice.spice_params.meas_params.accuracy); + break; + case SPICE_FRAC: + fprintf(fp, ".tran '%d*clock_period/%d' ", + num_clock_cycle, (int)spice.spice_params.meas_params.accuracy); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid accuracy type!\n", + __FILE__, __LINE__); + exit(1); + } + + if (TRUE == leakage_only) { + fprintf(fp, " 'clock_period'"); + } else { + fprintf(fp, " '%d*clock_period'", + num_clock_cycle); + } + + if ((TRUE == spice.spice_params.mc_params.cmos_variation.variation_on) + ||(TRUE == spice.spice_params.mc_params.rram_variation.variation_on) + ||(TRUE == spice.spice_params.mc_params.mc_sim)) { + fprintf(fp, " sweep monte=%d ", + spice.spice_params.mc_params.num_mc_points); + } + + fprintf(fp, "\n"); + + return; +} + +void fprint_stimulate_dangling_one_grid_pin(FILE* fp, + int x, int y, + int height, int side, int pin_index, + t_ivec*** LL_rr_node_indices) { + t_type_ptr type_descriptor = grid[x][y].type; + int capacity = grid[x][y].type->capacity; + int class_id; + int rr_node_index; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + assert(NULL != type_descriptor); + assert(0 < capacity); + + class_id = type_descriptor->pin_class[pin_index]; + if (DRIVER == type_descriptor->class_inf[class_id].type) { + rr_node_index = get_rr_node_index(x, y, OPIN, pin_index, LL_rr_node_indices); + /* Zero fan-out OPIN */ + if (0 == rr_node[rr_node_index].num_edges) { + fprintf(fp, "Rdangling_grid[%d][%d]_pin[%d][%d][%d] grid[%d][%d]_pin[%d][%d][%d] 0 1e9\n", + x, y, height, side, pin_index, + x, y, height, side, pin_index); + fprintf(fp, "*.nodeset V(grid[%d][%d]_pin[%d][%d][%d]) 0 \n", + x, y, height, side, pin_index); + } + return; + } + if (RECEIVER == type_descriptor->class_inf[class_id].type) { + rr_node_index = get_rr_node_index(x, y, IPIN, pin_index, LL_rr_node_indices); + /* Zero fan-in IPIN */ + if (0 == rr_node[rr_node_index].fan_in) { + fprintf(fp, "Rdangling_grid[%d][%d]_pin[%d][%d][%d] grid[%d][%d]_pin[%d][%d][%d] 0 0\n", + x, y, height, side, pin_index, + x, y, height, side, pin_index); + fprintf(fp, ".nodeset V(grid[%d][%d]_pin[%d][%d][%d]) 0\n", + x, y, height, side, pin_index); + } + return; + } + + return; +} + +void fprint_stimulate_dangling_io_grid_pins(FILE* fp, + int x, int y) { + int iheight, side, ipin; + t_type_ptr type_descriptor = grid[x][y].type; + int capacity = grid[x][y].type->capacity; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + assert(NULL != type_descriptor); + assert(0 < capacity); + + /* identify the location of IO grid and + * decide which side of ports we need + */ + side = determine_io_grid_side(x,y); + + /* Count the number of pins */ + //for (iz = 0; iz < capacity; iz++) { + for (iheight = 0; iheight < type_descriptor->height; iheight++) { + for (ipin = 0; ipin < type_descriptor->num_pins; ipin++) { + if (1 == type_descriptor->pinloc[iheight][side][ipin]) { + fprint_stimulate_dangling_one_grid_pin(fp, x, y, iheight, side, ipin, rr_node_indices); + } + } + } + //} + + return; +} + +void fprint_stimulate_dangling_normal_grid_pins(FILE* fp, + int x, int y) { + int iheight, side, ipin; + t_type_ptr type_descriptor = grid[x][y].type; + int capacity = grid[x][y].type->capacity; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + assert(NULL != type_descriptor); + assert(0 < capacity); + + for (side = 0; side < 4; side++) { + /* Count the number of pins */ + for (iheight = 0; iheight < type_descriptor->height; iheight++) { + for (ipin = 0; ipin < type_descriptor->num_pins; ipin++) { + if (1 == type_descriptor->pinloc[iheight][side][ipin]) { + fprint_stimulate_dangling_one_grid_pin(fp, x, y, iheight, side, ipin, rr_node_indices); + } + } + } + } + + return; + +} + +void fprint_stimulate_dangling_grid_pins(FILE* fp) { + int ix, iy; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* Normal Grids */ + for (ix = 1; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + assert(IO_TYPE != grid[ix][iy].type); + /* zero-fan-in CLB IPIN*/ + fprint_stimulate_dangling_normal_grid_pins(fp, ix, iy); + } + } + + /* IO Grids */ + /* LEFT side */ + ix = 0; + for (iy = 1; iy < (ny + 1); iy++) { + assert(IO_TYPE == grid[ix][iy].type); + fprint_stimulate_dangling_io_grid_pins(fp, ix, iy); + } + + /* RIGHT side */ + ix = nx + 1; + for (iy = 1; iy < (ny + 1); iy++) { + assert(IO_TYPE == grid[ix][iy].type); + fprint_stimulate_dangling_io_grid_pins(fp, ix, iy); + } + + /* BOTTOM side */ + iy = 0; + for (ix = 1; ix < (nx + 1); ix++) { + assert(IO_TYPE == grid[ix][iy].type); + fprint_stimulate_dangling_io_grid_pins(fp, ix, iy); + } + + /* TOP side */ + iy = ny + 1; + for (ix = 1; ix < (nx + 1); ix++) { + assert(IO_TYPE == grid[ix][iy].type); + fprint_stimulate_dangling_io_grid_pins(fp, ix, iy); + } + + return; +} + +void init_logical_block_spice_model_temp_used(t_spice_model* spice_model) { + int i; + + /* For each logical block, we print a vdd */ + for (i = 0; i < num_logical_blocks; i++) { + if (logical_block[i].mapped_spice_model == spice_model) { + logical_block[i].temp_used = 0; + } + } + + return; +} + +void init_logical_block_spice_model_type_temp_used(int num_spice_models, t_spice_model* spice_model, + enum e_spice_model_type spice_model_type) { + int i; + + /* For each logical block, we print a vdd */ + for (i = 0; i < num_spice_models; i++) { + if (spice_model_type == spice_model[i].type) { + init_logical_block_spice_model_temp_used(&(spice_model[i])); + } + } + + return; +} + +void fprint_global_vdds_logical_block_spice_model(FILE* fp, + t_spice_model* spice_model) { + int i; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* For each logical block, we print a vdd */ + for (i = 0; i < num_logical_blocks; i++) { + if ((logical_block[i].mapped_spice_model == spice_model) + &&(1 == logical_block[i].temp_used)){ + fprintf(fp, ".global gvdd_%s[%d]\n", + spice_model->prefix, logical_block[i].mapped_spice_model_index); + } + } + + return; +} + +void fprint_splited_vdds_logical_block_spice_model(FILE* fp, + t_spice_model* spice_model) { + int i; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* For each logical block, we print a vdd */ + for (i = 0; i < num_logical_blocks; i++) { + if ((logical_block[i].mapped_spice_model == spice_model) + &&(1 == logical_block[i].temp_used)){ + fprintf(fp, "Vgvdd_%s[%d] gvdd_%s[%d] 0 vsp\n", + spice_model->prefix, logical_block[i].mapped_spice_model_index, + spice_model->prefix, logical_block[i].mapped_spice_model_index); + } + } + + return; +} + +void fprint_measure_vdds_logical_block_spice_model(FILE* fp, + t_spice_model* spice_model, + enum e_measure_type meas_type, + int num_clock_cycle, + boolean leakage_only) { + int i, iport, ipin, cur; + float average_output_density = 0.; + int output_cnt = 0; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* For each logical block, we print a vdd */ + for (i = 0; i < num_logical_blocks; i++) { + if ((logical_block[i].mapped_spice_model == spice_model) + &&(1 == logical_block[i].temp_used)) { + /* Get the average output density */ + output_cnt = 0; + for (iport = 0; iport < logical_block[i].pb->pb_graph_node->num_output_ports; iport++) { + for (ipin = 0; ipin < logical_block[i].pb->pb_graph_node->num_output_pins[iport]; ipin++) { + average_output_density += vpack_net[logical_block[i].output_nets[iport][ipin]].spice_net_info->density; + output_cnt++; + } + } + average_output_density = average_output_density/output_cnt; + switch (meas_type) { + case SPICE_MEASURE_LEAKAGE_POWER: + if (TRUE == leakage_only) { + fprintf(fp, ".measure tran leakage_power_%s[%d] find p(Vgvdd_%s[%d]) at=0\n", + spice_model->prefix, logical_block[i].mapped_spice_model_index, + spice_model->prefix, logical_block[i].mapped_spice_model_index); + } else { + fprintf(fp, ".measure tran leakage_power_%s[%d] avg p(Vgvdd_%s[%d]) from=0 to='clock_period'\n", + spice_model->prefix, logical_block[i].mapped_spice_model_index, + spice_model->prefix, logical_block[i].mapped_spice_model_index); + } + break; + case SPICE_MEASURE_DYNAMIC_POWER: + fprintf(fp, ".measure tran dynamic_power_%s[%d] avg p(Vgvdd_%s[%d]) from='clock_period' to='%d*clock_period'\n", + spice_model->prefix, logical_block[i].mapped_spice_model_index, + spice_model->prefix, logical_block[i].mapped_spice_model_index, + num_clock_cycle); + fprintf(fp, ".measure tran energy_per_cycle_%s[%d] param='dynamic_power_%s[%d]*clock_period'\n", + spice_model->prefix, logical_block[i].mapped_spice_model_index, + spice_model->prefix, logical_block[i].mapped_spice_model_index); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid meas_type!\n", __FILE__, __LINE__); + exit(1); + } + } + } + + /* Measure the total power of this kind of spice model */ + cur = 0; + switch (meas_type) { + case SPICE_MEASURE_LEAKAGE_POWER: + for (i = 0; i < num_logical_blocks; i++) { + if ((logical_block[i].mapped_spice_model == spice_model) + &&(1 == logical_block[i].temp_used)) { + fprintf(fp, ".measure tran leakage_power_%s[0to%d] \n", + spice_model->prefix, cur); + if (0 == cur) { + fprintf(fp, "+ param = 'leakage_power_%s[%d]'\n", + spice_model->prefix, logical_block[i].mapped_spice_model_index); + } else { + fprintf(fp, "+ param = 'leakage_power_%s[%d]+leakage_power_%s[0to%d]'\n", + spice_model->prefix, logical_block[i].mapped_spice_model_index, + spice_model->prefix, cur-1); + } + cur++; + } + } + if (0 == cur) { + break; + } + /* Spot the total leakage power of this spice model */ + fprintf(fp, ".measure tran total_leakage_power_%s \n", spice_model->prefix); + fprintf(fp, "+ param = 'leakage_power_%s[0to%d]'\n", + spice_model->prefix, cur-1); + break; + case SPICE_MEASURE_DYNAMIC_POWER: + for (i = 0; i < num_logical_blocks; i++) { + if ((logical_block[i].mapped_spice_model == spice_model) + &&(1 == logical_block[i].temp_used)) { + fprintf(fp, ".measure tran energy_per_cycle_%s[0to%d] \n", + spice_model->prefix, cur); + if (0 == cur) { + fprintf(fp, "+ param = 'energy_per_cycle_%s[%d]'\n", + spice_model->prefix, logical_block[i].mapped_spice_model_index); + } else { + fprintf(fp, "+ param = 'energy_per_cycle_%s[%d]+energy_per_cycle_%s[0to%d]'\n", + spice_model->prefix, logical_block[i].mapped_spice_model_index, + spice_model->prefix, cur-1); + } + cur++; + } + } + if (0 == cur) { + break; + } + /* Spot the total dynamic power of this spice model */ + fprintf(fp, ".measure tran total_energy_per_cycle_%s \n", spice_model->prefix); + fprintf(fp, "+ param = 'energy_per_cycle_%s[0to%d]'\n", + spice_model->prefix, cur-1); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid meas_type!\n", __FILE__, __LINE__); + exit(1); + } + + return; +} + +/* Give voltage stimuli of one global port */ +void fprint_spice_testbench_wire_one_global_port_stimuli(FILE* fp, + t_spice_model_port* cur_global_port, + char* voltage_stimuli_port_name) { + int ipin; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + assert(NULL != cur_global_port); + + for (ipin = 0; ipin < cur_global_port->size; ipin++) { + fprintf(fp, "Rshortwire%s[%d] %s[%d] ", + cur_global_port->prefix, ipin, + cur_global_port->prefix, ipin); + assert((0 == cur_global_port->default_val)||(1 == cur_global_port->default_val)); + fprintf(fp, "%s", + voltage_stimuli_port_name); + if (1 == cur_global_port->default_val) { + fprintf(fp, "%s ", + spice_tb_global_port_inv_postfix); + } + fprintf(fp, " 0\n"); + } + + return; + +} + +/* Give voltage stimuli of global ports */ +void fprint_spice_testbench_global_ports_stimuli(FILE* fp, + t_llist* head) { + t_llist* temp = head; + t_spice_model_port* cur_global_port = NULL; + int ipin; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + fprintf(fp, "***** Connecting Global ports *****\n"); + while(NULL != temp) { + cur_global_port = (t_spice_model_port*)(temp->dptr); + /* Make sure this is a global port */ + assert(TRUE == cur_global_port->is_global); + /* If this is a clock signal, connect to op_clock signal */ + if (SPICE_MODEL_PORT_CLOCK == cur_global_port->type) { + /* Special for programming clock */ + if (TRUE == cur_global_port->is_prog) { + /* We do need to program SRAMs/RRAM in spice netlist + * Just wire it to a constant GND/VDD + */ + fprint_spice_testbench_wire_one_global_port_stimuli(fp, cur_global_port, + spice_tb_global_config_done_port_name); + } else { + assert(FALSE == cur_global_port->is_prog); + fprint_spice_testbench_wire_one_global_port_stimuli(fp, cur_global_port, + spice_tb_global_clock_port_name); + } + /* If this is a config_enable signal, connect to config_done signal */ + } else if (TRUE == cur_global_port->is_config_enable) { + fprint_spice_testbench_wire_one_global_port_stimuli(fp, cur_global_port, + spice_tb_global_config_done_port_name); + /* If this is a set/reset signal, connect to global reset and set signals */ + } else if (TRUE == cur_global_port->is_reset) { + /* Special for programming reset */ + if (TRUE == cur_global_port->is_prog) { + fprint_spice_testbench_wire_one_global_port_stimuli(fp, cur_global_port, + spice_tb_global_reset_port_name); + } else { + assert(FALSE == cur_global_port->is_prog); + fprint_spice_testbench_wire_one_global_port_stimuli(fp, cur_global_port, + spice_tb_global_reset_port_name); + } + /* If this is a set/reset signal, connect to global reset and set signals */ + } else if (TRUE == cur_global_port->is_set) { + /* Special for programming reset */ + if (TRUE == cur_global_port->is_prog) { + fprint_spice_testbench_wire_one_global_port_stimuli(fp, cur_global_port, + spice_tb_global_set_port_name); + } else { + assert(FALSE == cur_global_port->is_prog); + fprint_spice_testbench_wire_one_global_port_stimuli(fp, cur_global_port, + spice_tb_global_set_port_name); + } + } else { + /* Other global signals stuck at the default values */ + for (ipin = 0; ipin < cur_global_port->size; ipin++) { + fprintf(fp, "R%s[%d] %s[%d] ", + cur_global_port->prefix, ipin, + cur_global_port->prefix, ipin); + assert( (0 == cur_global_port->default_val)||(1 == cur_global_port->default_val) ); + if ( 0 == cur_global_port->default_val ) { + /* Default value is 0: Connect to the global GND port */ + fprintf(fp, " %s", + spice_tb_global_gnd_port_name); + } else { + /* Default value is 1: Connect to the global VDD port */ + fprintf(fp, " %s", + spice_tb_global_vdd_port_name); + } + fprintf(fp, " 0\n"); + } + } + /* Go to the next */ + temp = temp->next; + } + fprintf(fp, "***** End Connecting Global ports *****\n"); + + return; +} + +void fprint_spice_testbench_global_vdd_port_stimuli(FILE* fp, + char* global_vdd_port_name, + char* voltage_level) { + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Print a Voltage Stimuli */ + fprintf(fp, "V%s %s 0 %s\n", + global_vdd_port_name, + global_vdd_port_name, + voltage_level); + return; +} + +void fprint_spice_testbench_global_sram_inport_stimuli(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info) { + t_spice_model* mem_model = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Get memory spice model */ + get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); + + /* Every SRAM inputs should have a voltage source */ + fprintf(fp, "***** Global Inputs for SRAMs *****\n"); + if (SPICE_SRAM_SCAN_CHAIN == cur_sram_orgz_info->type) { + fprintf(fp, "Vsc_clk sc_clk 0 0\n"); + fprintf(fp, "Vsc_rst sc_rst 0 0\n"); + fprintf(fp, "Vsc_set sc_set 0 0\n"); + fprintf(fp, "V%s[0]->in %s[0]->in 0 0\n", mem_model->prefix, mem_model->prefix); + fprintf(fp, ".nodeset V(%s[0]->in) 0\n", mem_model->prefix); + } else { + fprintf(fp, "V%s->in %s->in 0 0\n", + mem_model->prefix, mem_model->prefix); + fprintf(fp, ".nodeset V(%s->in) 0\n", mem_model->prefix); + } + + return; +} + +void fprint_spice_testbench_generic_global_ports_stimuli(FILE* fp, + int num_clock) { + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Global GND */ + fprintf(fp, "***** Global VDD port *****\n"); + fprintf(fp, "V%s %s 0 vsp\n", + spice_tb_global_vdd_port_name, + spice_tb_global_vdd_port_name); + fprintf(fp, "***** Global GND port *****\n"); + fprintf(fp, "V%s %s 0 0\n", + spice_tb_global_gnd_port_name, + spice_tb_global_gnd_port_name); + + /* Global set and reset */ + fprintf(fp, "***** Global Net for reset signal *****\n"); + fprintf(fp, "V%s %s 0 0\n", + spice_tb_global_reset_port_name, + spice_tb_global_reset_port_name); + fprintf(fp, "V%s%s %s%s 0 vsp\n", + spice_tb_global_reset_port_name, + spice_tb_global_port_inv_postfix, + spice_tb_global_reset_port_name, + spice_tb_global_port_inv_postfix); + fprintf(fp, "***** Global Net for set signal *****\n"); + fprintf(fp, "V%s %s 0 0\n", + spice_tb_global_set_port_name, + spice_tb_global_set_port_name); + fprintf(fp, "V%s%s %s%s 0 vsp\n", + spice_tb_global_set_port_name, + spice_tb_global_port_inv_postfix, + spice_tb_global_set_port_name, + spice_tb_global_port_inv_postfix); + + /* Global config done */ + fprintf(fp, "***** Global Net for configuration done signal *****\n"); + fprintf(fp, "V%s %s 0 0\n", + spice_tb_global_config_done_port_name, + spice_tb_global_config_done_port_name); + fprintf(fp, "V%s%s %s%s 0 vsp\n", + spice_tb_global_config_done_port_name, + spice_tb_global_port_inv_postfix, + spice_tb_global_config_done_port_name, + spice_tb_global_port_inv_postfix); + + /* Global clock if we need one */ + if (1 == num_clock) { + /* First cycle reserved for measuring leakage */ + fprintf(fp, "***** Global Clock signal *****\n"); + fprintf(fp, "***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****\n"); + fprintf(fp, "V%s %s 0 pulse(0 vsp 'clock_period'\n", + spice_tb_global_clock_port_name, + spice_tb_global_clock_port_name); + fprintf(fp, "+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'\n"); + fprintf(fp, "+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')\n"); + fprintf(fp, "\n"); + fprintf(fp, "***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****\n"); + fprintf(fp, "V%s%s %s%s 0 pulse(0 vsp 'clock_period'\n", + spice_tb_global_clock_port_name, + spice_tb_global_port_inv_postfix, + spice_tb_global_clock_port_name, + spice_tb_global_port_inv_postfix); + fprintf(fp, "+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'\n"); + fprintf(fp, "+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')\n"); + } else { + assert(0 == num_clock); + /* Give constant value */ + fprintf(fp, "V%s %s 0 0\n", + spice_tb_global_clock_port_name, + spice_tb_global_clock_port_name); + fprintf(fp, "V%s%s %s%s 0 vsp\n", + spice_tb_global_clock_port_name, + spice_tb_global_port_inv_postfix, + spice_tb_global_clock_port_name, + spice_tb_global_port_inv_postfix); + } + + return; +} + +/* Find the inverter size of a Programmable Logic Block Pin + * + */ +float find_spice_testbench_pb_pin_mux_load_inv_size(t_spice_model* fan_out_spice_model) { + float load_inv_size = 0; + + /* Check */ + assert(NULL != fan_out_spice_model); + assert(NULL != fan_out_spice_model->input_buffer); + + /* Special: this is a LUT, we should consider more inv size */ + if (SPICE_MODEL_LUT == fan_out_spice_model->type) { + assert(1 == fan_out_spice_model->lut_input_buffer->exist); + assert((SPICE_MODEL_BUF_INV == fan_out_spice_model->lut_input_buffer->type) + ||(SPICE_MODEL_BUF_BUF == fan_out_spice_model->lut_input_buffer->type)); + assert(TRUE == fan_out_spice_model->lut_input_buffer->tapered_buf); + assert(2 == fan_out_spice_model->lut_input_buffer->tap_buf_level); + load_inv_size = fan_out_spice_model->lut_input_buffer->size + + fan_out_spice_model->lut_input_buffer->f_per_stage; + return load_inv_size; + } + + /* depend on the input_buffer type */ + if (1 == fan_out_spice_model->input_buffer->exist) { + switch(fan_out_spice_model->input_buffer->type) { + case SPICE_MODEL_BUF_INV: + load_inv_size = fan_out_spice_model->input_buffer->size; + break; + case SPICE_MODEL_BUF_BUF: + load_inv_size = 1.; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid fanout spice_model input_buffer type!\n", + __FILE__, __LINE__); + exit(1); + } + } else { + /* TODO: If there is no inv/buffer at input, we should traversal until there is one + * However, now we just simply give a minimum sized inverter + */ + load_inv_size = 1.; + } + + return load_inv_size; +} + +float find_spice_testbench_rr_mux_load_inv_size(t_rr_node* load_rr_node, + int switch_index) { + float load_inv_size = 0; + t_spice_model* fan_out_spice_model = NULL; + + fan_out_spice_model = switch_inf[switch_index].spice_model; + + /* Check */ + assert(NULL != fan_out_spice_model); + assert(NULL != fan_out_spice_model->input_buffer); + + /* depend on the input_buffer type */ + if (1 == fan_out_spice_model->input_buffer->exist) { + switch(fan_out_spice_model->input_buffer->type) { + case SPICE_MODEL_BUF_INV: + load_inv_size = fan_out_spice_model->input_buffer->size; + break; + case SPICE_MODEL_BUF_BUF: + load_inv_size = fan_out_spice_model->input_buffer->size; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid fanout spice_model input_buffer type!\n", + __FILE__, __LINE__); + exit(1); + } + } else { + /* TODO: If there is no inv/buffer at input, we should traversal until there is one + * However, now we just simply give a minimum sized inverter + * fprint_spice_testbench_pb_graph_pin_inv_loads_rec(fp, &testbench_load_cnt, + x, y, + &(cur_pb_graph_node->output_pins[0][0]), + logical_block[logical_block_index].pb, + outport_name, + FALSE, + LL_rr_node_indices); + + */ + load_inv_size = 1; + } + + return load_inv_size; + +} + +void fprint_spice_testbench_pb_graph_pin_inv_loads_rec(FILE* fp, int* testbench_load_cnt, + int grid_x, int grid_y, + t_pb_graph_pin* src_pb_graph_pin, + t_pb* src_pb, + char* outport_name, + boolean consider_parent_node, + t_ivec*** LL_rr_node_indices) { + int iedge, mode_index, ipb, jpb; + t_interconnect* cur_interc = NULL; + char* rec_outport_name = NULL; + t_pb* des_pb = NULL; + int src_rr_node_index = -1; + float load_inv_size = 0.; + float total_width; + int width_cnt; + + /* A valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); + exit(1); + } + + assert(NULL != src_pb_graph_pin); + + if (TRUE == consider_parent_node) { + if (NULL != src_pb_graph_pin->parent_node->pb_type->spice_model) { + load_inv_size = find_spice_testbench_pb_pin_mux_load_inv_size(src_pb_graph_pin->parent_node->pb_type->spice_model); + /* Print inverters by considering maximum width */ + total_width = load_inv_size; + width_cnt = 0; + while (total_width > max_width_per_trans) { + fprintf(fp, "Xload_inv[%d]_no%d %s %s_out[0] gvdd_load 0 inv size=%g\n", + (*testbench_load_cnt), width_cnt, outport_name, outport_name, max_width_per_trans); + /* Update counter */ + total_width = total_width - max_width_per_trans; + width_cnt++; + } + if (total_width > 0) { + fprintf(fp, "Xload_inv[%d]_no%d %s %s_out[0] gvdd_load 0 inv size=%g\n", + (*testbench_load_cnt), width_cnt, outport_name, outport_name, total_width); + (*testbench_load_cnt)++; + } + return; + } + } + + /* Get the mode_index */ + if (NULL == src_pb) { + mode_index = find_pb_type_idle_mode_index(*(src_pb_graph_pin->parent_node->pb_type)); + } else { + mode_index = src_pb->mode; + } + + /* If this pb belongs to a pb_graph_head, + * the src_pb_graph_pin is a OPIN, we should find the rr_node */ + if ((OUT_PORT == src_pb_graph_pin->port->type) + &&(NULL == src_pb_graph_pin->parent_node->parent_pb_graph_node)) { + /* Find the corresponding rr_node */ + assert(grid[grid_x][grid_y].type->pb_graph_head == src_pb_graph_pin->parent_node); + src_rr_node_index = get_rr_node_index(grid_x, grid_y, OPIN, src_pb_graph_pin->pin_count_in_cluster, LL_rr_node_indices); + for (iedge = 0; iedge < rr_node[src_rr_node_index].num_edges; iedge++) { + /* Detect its input buffers */ + load_inv_size = find_spice_testbench_rr_mux_load_inv_size(&rr_node[rr_node[src_rr_node_index].edges[iedge]], + rr_node[src_rr_node_index].switches[iedge]); + /* Print inverters by considering maximum width */ + total_width = load_inv_size; + width_cnt = 0; + while (total_width > max_width_per_trans) { + fprintf(fp, "Xload_inv[%d]_no%d %s load_inv[%d]_out gvdd_load 0 inv size=%g\n", + (*testbench_load_cnt), width_cnt, outport_name, + (*testbench_load_cnt), max_width_per_trans); + /* Update counter */ + total_width = total_width - max_width_per_trans; + width_cnt++; + } + if (total_width > 0) { + fprintf(fp, "Xload_inv[%d]_no%d %s load_inv[%d]_out gvdd_load 0 inv size=%g\n", + (*testbench_load_cnt), width_cnt, outport_name, + (*testbench_load_cnt), total_width); + } + (*testbench_load_cnt)++; + } + return; + } + + /* Search output edges */ + for (iedge = 0; iedge < src_pb_graph_pin->num_output_edges; iedge++) { + check_pb_graph_edge(*(src_pb_graph_pin->output_edges[iedge])); + /* We care only the edges in selected mode */ + cur_interc = src_pb_graph_pin->output_edges[iedge]->interconnect; + assert(NULL != cur_interc); + if (mode_index == cur_interc->parent_mode_index) { + rec_outport_name = (char*)my_malloc(sizeof(char)* (strlen(outport_name) + 5 + strlen(my_itoa(iedge)) +2 )); + sprintf(rec_outport_name, "%s_out[%d]", outport_name, iedge); + /* check the interc has spice_model and if it is buffered */ + assert(NULL != cur_interc->spice_model); + if (TRUE == cur_interc->spice_model->input_buffer->exist) { + /* Print a inverter, and we stop this branch */ + load_inv_size = find_spice_testbench_pb_pin_mux_load_inv_size(cur_interc->spice_model); + /* Print inverters by considering maximum width */ + total_width = load_inv_size; + width_cnt = 0; + while (total_width > max_width_per_trans) { + fprintf(fp, "Xload_inv[%d]_no%d %s %s gvdd_load 0 inv size=%g\n", + (*testbench_load_cnt), width_cnt, outport_name, rec_outport_name, max_width_per_trans); + /* Update counter */ + total_width = total_width - max_width_per_trans; + width_cnt++; + } + if (total_width > 0) { + fprintf(fp, "Xload_inv[%d]_no%d %s %s gvdd_load 0 inv size=%g\n", + (*testbench_load_cnt), width_cnt, outport_name, rec_outport_name, total_width); + } + (*testbench_load_cnt)++; + } else { + /* + fprintf(fp, "R%s_to_%s %s %s 0\n", + outport_name, rec_outport_name, + outport_name, rec_outport_name); + */ + /* Go recursively */ + if (NULL == src_pb) { + des_pb = NULL; + } else { + if (IN_PORT == src_pb_graph_pin->port->type) { + ipb = src_pb_graph_pin->output_edges[iedge]->output_pins[0]->parent_node->pb_type + - src_pb_graph_pin->parent_node->pb_type->modes[mode_index].pb_type_children; + jpb = src_pb_graph_pin->output_edges[iedge]->output_pins[0]->parent_node->placement_index; + if ((NULL != src_pb->child_pbs[ipb])&&(NULL != src_pb->child_pbs[ipb][jpb].name)) { + des_pb = &(src_pb->child_pbs[ipb][jpb]); + } else { + des_pb = NULL; + } + } else if (OUT_PORT == src_pb_graph_pin->port->type) { + des_pb = src_pb->parent_pb; + } else if (INOUT_PORT == src_pb_graph_pin->port->type) { + des_pb = NULL; /* I don't know what to do...*/ + } + } + fprint_spice_testbench_pb_graph_pin_inv_loads_rec(fp, testbench_load_cnt, grid_x, grid_y, + src_pb_graph_pin->output_edges[iedge]->output_pins[0], + des_pb, outport_name, TRUE, LL_rr_node_indices); + + } + } + } + + return; +} + +char* fprint_spice_testbench_rr_node_load_version(FILE* fp, int* testbench_load_cnt, + int num_segments, + t_segment_inf* segments, + int load_level, + t_rr_node cur_rr_node, + char* outport_name) { + char* ret_outport_name = NULL; + char* mid_outport_name = NULL; + int cost_index; + int iseg, i, iedge, chan_wire_length, cur_x, cur_y; + t_rr_node to_node; + t_spice_model* wire_spice_model = NULL; + float load_inv_size = 0.; + float total_width; + int width_cnt; + + /* We only process CHANX or CHANY*/ + if (!((CHANX == cur_rr_node.type) + ||(CHANY == cur_rr_node.type))) { + ret_outport_name = my_strdup(outport_name); + return ret_outport_name; + } + + /* Important: + * As the cur_rr_node can only be channel wires + * and channel wires can only be driven at the starting point, + * in this function, + * the loads to be added will always starts from the starting point of a channel wire. + * We will consider the length of channel wires when adding the loads. + * For example, a length-4 wire will introduce 4 levels of channel segments to the loads. + * To handle the corner case, we will consider the border when adding channel segments + * If the length of wire exceeds the borderline of FPGA, + * we will adapt the number of channel segments. + */ + cost_index = cur_rr_node.cost_index; + iseg = rr_indexed_data[cost_index].seg_index; + assert((!(iseg < 0))&&(iseg < num_segments)); + wire_spice_model = segments[iseg].spice_model; + assert(SPICE_MODEL_CHAN_WIRE == wire_spice_model->type); + /* Check if the coordinate is correct */ + assert((0 == cur_rr_node.xhigh - cur_rr_node.xlow) + ||(0 == cur_rr_node.yhigh - cur_rr_node.ylow)); + chan_wire_length = cur_rr_node.xhigh - cur_rr_node.xlow + + cur_rr_node.yhigh - cur_rr_node.ylow; + + fprintf(fp, "**** Loads for rr_node: xlow=%d, ylow=%d, xhigh=%d, yhigh=%d, ptc_num=%d, type=%d *****\n", + cur_rr_node.xlow, cur_rr_node.ylow, + cur_rr_node.xhigh, cur_rr_node.yhigh, + cur_rr_node.ptc_num, cur_rr_node.type); + + for (i = 0; i < chan_wire_length + 1; i++) { + ret_outport_name = (char*)my_malloc(sizeof(char)*( strlen(outport_name) + + 9 + strlen(my_itoa(load_level + i)) + 6 + + 1 )); + sprintf(ret_outport_name,"%s_loadlvl[%d]_out", + outport_name, load_level + i); + mid_outport_name = (char*)my_malloc(sizeof(char)*( strlen(outport_name) + + 9 + strlen(my_itoa(load_level + i)) + 9 + + 1 )); + sprintf(mid_outport_name,"%s_loadlvl[%d]_midout", + outport_name, load_level + i); + if (0 == i) { + fprintf(fp, "Xchan_%s %s %s %s gvdd_load 0 %s_seg%d\n", + ret_outport_name, outport_name, ret_outport_name, mid_outport_name, + wire_spice_model->name, iseg); + } else { + fprintf(fp, "Xchan_%s %s_loadlvl[%d]_out %s %s gvdd_load 0 %s_seg%d\n", + ret_outport_name, outport_name, load_level + i -1, ret_outport_name, mid_outport_name, + wire_spice_model->name, iseg); + } + /* Print CB inv loads connected to the mid_out */ + switch (cur_rr_node.type) { + case CHANX: + /* Update the cur_x & cur_y */ + if (INC_DIRECTION == cur_rr_node.direction) { + cur_x = cur_rr_node.xlow + i; + cur_y = cur_rr_node.ylow; + } else { + assert(DEC_DIRECTION == cur_rr_node.direction); + cur_x = cur_rr_node.xhigh - i; + cur_y = cur_rr_node.ylow; + } + for (iedge = 0; iedge < cur_rr_node.num_edges; iedge++) { + /*Identify if the des node is a IPIN and fit the current(x,y)*/ + to_node = rr_node[cur_rr_node.edges[iedge]]; + switch (to_node.type) { + case IPIN: + assert(to_node.xhigh == to_node.xlow); + assert(to_node.yhigh == to_node.ylow); + if (((cur_x == to_node.xlow)&&(cur_y == to_node.ylow)) + ||((cur_x == to_node.xlow)&&((cur_y + 1) == to_node.ylow))) { + /* We find a CB! */ + /* Detect its input buffers */ + load_inv_size = find_spice_testbench_rr_mux_load_inv_size(&to_node, + cur_rr_node.switches[iedge]); + /* TODO: Need to find the downsteam inv_loads if it is not bufferred + fprint_spice_testbench_pb_graph_pin_inv_loads_rec(fp, &testbench_load_cnt, + x, y, + &(cur_pb_graph_node->output_pins[0][0]), + logical_block[logical_block_index].pb, + outport_name, + FALSE, + LL_rr_node_indices); + */ + assert(0. < load_inv_size); + /* Print an inverter */ + total_width = load_inv_size; + width_cnt = 0; + while (total_width > max_width_per_trans) { + fprintf(fp, "Xload_inv[%d]_no%d %s %s_out[%d] gvdd_load 0 inv size=%g\n", + (*testbench_load_cnt), width_cnt, mid_outport_name, mid_outport_name, iedge, + max_width_per_trans); + /* Update */ + total_width = total_width - max_width_per_trans; + width_cnt++; + } + if (total_width > 0) { + fprintf(fp, "Xload_inv[%d]_no%d %s %s_out[%d] gvdd_load 0 inv size=%g\n", + (*testbench_load_cnt), width_cnt, mid_outport_name, mid_outport_name, iedge, + total_width); + } + (*testbench_load_cnt)++; + } + break; + case CHANX: + case CHANY: + /* We find a SB! */ + /* Detect its input buffers */ + load_inv_size = find_spice_testbench_rr_mux_load_inv_size(&to_node, + cur_rr_node.switches[iedge]); + assert(0. < load_inv_size); + /* Print an inverter */ + total_width = load_inv_size; + width_cnt = 0; + while (total_width > max_width_per_trans) { + fprintf(fp, "Xload_inv[%d]_no%d %s %s_out[%d] gvdd_load 0 inv size=%g\n", + (*testbench_load_cnt), width_cnt, ret_outport_name, ret_outport_name, iedge, + max_width_per_trans); + /* Update */ + total_width = total_width - max_width_per_trans; + width_cnt++; + } + if (total_width > 0) { + fprintf(fp, "Xload_inv[%d]_no%d %s %s_out[%d] gvdd_load 0 inv size=%g\n", + (*testbench_load_cnt), width_cnt, ret_outport_name, ret_outport_name, iedge, + total_width); + } + (*testbench_load_cnt)++; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid src_rr_node_type!\n", + __FILE__, __LINE__); + exit(1); + } + } + break; + case CHANY: + /* Update the cur_x & cur_y */ + if (INC_DIRECTION == cur_rr_node.direction) { + cur_x = cur_rr_node.xlow; + cur_y = cur_rr_node.ylow + i; + } else { + assert(DEC_DIRECTION == cur_rr_node.direction); + cur_x = cur_rr_node.xlow; + cur_y = cur_rr_node.yhigh - i; + } + for (iedge = 0; iedge < cur_rr_node.num_edges; iedge++) { + /*Identify if the des node is a IPIN and fit the current(x,y)*/ + to_node = rr_node[cur_rr_node.edges[iedge]]; + switch (to_node.type) { + case IPIN: + assert(to_node.xhigh == to_node.xlow); + assert(to_node.yhigh == to_node.ylow); + if (((cur_y == to_node.ylow)&&(cur_x == to_node.xlow)) + ||((cur_y == to_node.xlow)&&((cur_x + 1) == to_node.xlow))) { + /* We find a CB! */ + /* Detect its input buffers */ + load_inv_size = find_spice_testbench_rr_mux_load_inv_size(&to_node, + cur_rr_node.switches[iedge]); + assert(0. < load_inv_size); + /* Print an inverter */ + total_width = load_inv_size; + width_cnt = 0; + while (total_width > max_width_per_trans) { + fprintf(fp, "Xload_inv[%d]_no%d %s %s_out[%d] gvdd_load 0 inv size=%g\n", + (*testbench_load_cnt), width_cnt, mid_outport_name, mid_outport_name, iedge, + max_width_per_trans); + /* Update */ + total_width = total_width - max_width_per_trans; + width_cnt++; + } + if (total_width > 0) { + fprintf(fp, "Xload_inv[%d]_no%d %s %s_out[%d] gvdd_load 0 inv size=%g\n", + (*testbench_load_cnt), width_cnt, mid_outport_name, mid_outport_name, iedge, + total_width); + } + (*testbench_load_cnt)++; + } + break; + case CHANX: + case CHANY: + /* We find a SB! */ + /* Detect its input buffers */ + load_inv_size = find_spice_testbench_rr_mux_load_inv_size(&to_node, + cur_rr_node.switches[iedge]); + assert(0. < load_inv_size); + /* Print an inverter */ + total_width = load_inv_size; + width_cnt = 0; + while (total_width > max_width_per_trans) { + fprintf(fp, "Xload_inv[%d]_no%d %s %s_out[%d] gvdd_load 0 inv size=%g\n", + (*testbench_load_cnt), width_cnt, ret_outport_name, ret_outport_name, iedge, + total_width); + /* Update */ + total_width = total_width - max_width_per_trans; + width_cnt++; + } + if (total_width > 0) { + fprintf(fp, "Xload_inv[%d]_no%d %s %s_out[%d] gvdd_load 0 inv size=%g\n", + (*testbench_load_cnt), width_cnt, ret_outport_name, ret_outport_name, iedge, + total_width); + } + (*testbench_load_cnt)++; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid src_rr_node_type!\n", + __FILE__, __LINE__); + exit(1); + } + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid src_rr_node_type!\n", + __FILE__, __LINE__); + exit(1); + } + } + + return ret_outport_name; +} + +void fprint_spice_testbench_one_cb_mux_loads(FILE* fp, int* testbench_load_cnt, + t_rr_node* src_rr_node, + char* outport_name, + t_ivec*** LL_rr_node_indices) { + t_type_ptr cb_out_grid_type = NULL; + t_pb_graph_pin* cb_out_pb_graph_pin = NULL; + t_pb* cb_out_pb = NULL; + + assert(IPIN == src_rr_node->type); + assert(src_rr_node->xlow == src_rr_node->xhigh); + assert(src_rr_node->ylow == src_rr_node->yhigh); + + cb_out_grid_type = grid[src_rr_node->xlow][src_rr_node->ylow].type; + assert(NULL != cb_out_grid_type); + + cb_out_pb_graph_pin = src_rr_node->pb_graph_pin; + assert(NULL != cb_out_pb_graph_pin); + + /* Get the pb ! Get the mode_index */ + cb_out_pb = src_rr_node->pb; + + if (IO_TYPE == cb_out_grid_type) { + fprintf(fp, "******* IO_TYPE loads *******\n"); + } else { + fprintf(fp, "******* Normal TYPE loads *******\n"); + } + + /* Recursively find all the inv load inside pb_graph_node */ + fprint_spice_testbench_pb_graph_pin_inv_loads_rec(fp, + testbench_load_cnt, + src_rr_node->xlow, + src_rr_node->ylow, + cb_out_pb_graph_pin, + cb_out_pb, + outport_name, + TRUE, + LL_rr_node_indices); + + + fprintf(fp, "******* END loads *******\n"); + return; +} + +void fprint_spice_testbench_one_grid_pin_stimulation(FILE* fp, int x, int y, + int height, int side, + int ipin, + t_ivec*** LL_rr_node_indices) { + int ipin_rr_node_index; + float ipin_density, ipin_probability; + int ipin_init_value; + int class_id; + t_rr_type grid_pin_rr_node_type; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + + /* Identify the type of rr_node */ + class_id = grid[x][y].type->pin_class[ipin]; + if (DRIVER == grid[x][y].type->class_inf[class_id].type) { + grid_pin_rr_node_type = OPIN; + } else if (RECEIVER == grid[x][y].type->class_inf[class_id].type) { + grid_pin_rr_node_type = IPIN; + } else { + /* Error */ + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Unknown pin type for grid(x=%d, y=%d, pin_index=%d)!\n", + __FILE__, __LINE__, + x, y, ipin); + exit(1); + } + + /* Print a voltage source according to density and probability */ + ipin_rr_node_index = get_rr_node_index(x, y, grid_pin_rr_node_type, ipin, LL_rr_node_indices); + /* Get density and probability */ + ipin_density = get_rr_node_net_density(rr_node[ipin_rr_node_index]); + ipin_probability = get_rr_node_net_probability(rr_node[ipin_rr_node_index]); + ipin_init_value = get_rr_node_net_init_value(rr_node[ipin_rr_node_index]); + /* Print voltage source */ + fprintf(fp, "Vgrid[%d][%d]_pin[%d][%d][%d] grid[%d][%d]_pin[%d][%d][%d] 0 \n", + x, y, height, side, ipin, x, y, height, side, ipin); + fprint_voltage_pulse_params(fp, ipin_init_value, ipin_density, ipin_probability); + + return; +} + +void fprint_spice_testbench_one_grid_pin_loads(FILE* fp, int x, int y, + int height, int side, + int ipin, + int* testbench_load_cnt, + t_ivec*** LL_rr_node_indices) { + + int ipin_rr_node_index; + int iedge, iswitch; + char* prefix = NULL; + t_spice_model* switch_spice_model = NULL; + int inv_cnt = 0; + int class_id; + t_rr_type grid_pin_rr_node_type; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + + /* Identify the type of rr_node */ + class_id = grid[x][y].type->pin_class[ipin]; + if (DRIVER == grid[x][y].type->class_inf[class_id].type) { + grid_pin_rr_node_type = OPIN; + } else if (RECEIVER == grid[x][y].type->class_inf[class_id].type) { + grid_pin_rr_node_type = IPIN; + } else { + /* Error */ + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Unknown pin type for grid(x=%d, y=%d, pin_index=%d)!\n", + __FILE__, __LINE__, + x, y, ipin); + exit(1); + } + + /* Print a voltage source according to density and probability */ + ipin_rr_node_index = get_rr_node_index(x, y, grid_pin_rr_node_type, ipin, LL_rr_node_indices); + /* Generate prefix */ + prefix = (char*)my_malloc(sizeof(char)*(5 + strlen(my_itoa(x)) + + 2 + strlen(my_itoa(y)) + 6 + strlen(my_itoa(height)) + + 2 + strlen(my_itoa(side)) + 2 + strlen(my_itoa(ipin)) + + 2 + 1)); + sprintf(prefix, "grid[%d][%d]_pin[%d][%d][%d]", + x, y, height, side, ipin); + + /* Depending on the type of this pin */ + /* For OPIN, we search the rr_node graph */ + if (OPIN == grid_pin_rr_node_type) { + /* Print all the inverter load now*/ + for (iedge = 0; iedge < rr_node[ipin_rr_node_index].num_edges; iedge++) { + /* Get the switch spice model */ + /* inode = rr_node[ipin_rr_node_index].edges[iedge]; */ + iswitch = rr_node[ipin_rr_node_index].switches[iedge]; + switch_spice_model = switch_inf[iswitch].spice_model; + if (NULL == switch_spice_model) { + continue; + } + /* Add inv/buf here */ + fprintf(fp, "X%s_inv[%d] %s %s_out[%d] gvdd_load 0 inv size=%g\n", + prefix, iedge, + prefix, prefix, iedge, + switch_spice_model->input_buffer->size); + inv_cnt++; + } + /* TODO: go recursively ? */ + /* For IPIN, we should search the internal rr_graph of the grid */ + } else if (IPIN == grid_pin_rr_node_type) { + fprint_spice_testbench_one_cb_mux_loads(fp, testbench_load_cnt, &rr_node[ipin_rr_node_index], + prefix, LL_rr_node_indices); + } else { + /* Error */ + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Unknown pin type for grid(x=%d, y=%d, pin_index=%d)!\n", + __FILE__, __LINE__, + x, y, ipin); + exit(1); + } + /* TODO: Generate loads recursively */ + /*fprint_rr_node_loads_rec(fp, rr_node[ipin_rr_node_index],prefix);*/ + + /*Free */ + my_free(prefix); + + return; +} + + +/* Add one SPICE TB information to linked list */ +t_llist* add_one_spice_tb_info_to_llist(t_llist* cur_head, + char* tb_file_path, + int num_sim_clock_cycles) { + t_llist* new_head = NULL; + + if (NULL == cur_head) { + new_head = create_llist(1); + new_head->dptr = my_malloc(sizeof(t_spicetb_info)); + ((t_spicetb_info*)(new_head->dptr))->tb_name = my_strdup(tb_file_path); + ((t_spicetb_info*)(new_head->dptr))->num_sim_clock_cycles = num_sim_clock_cycles; + } else { + new_head = insert_llist_node_before_head(cur_head); + new_head->dptr = my_malloc(sizeof(t_spicetb_info)); + ((t_spicetb_info*)(new_head->dptr))->tb_name = my_strdup(tb_file_path); + ((t_spicetb_info*)(new_head->dptr))->num_sim_clock_cycles = num_sim_clock_cycles; + } + + return new_head; +} + diff --git a/vpr7_rram/vpr/SRC/spice/spice_utils.h b/vpr7_rram/vpr/SRC/spice/spice_utils.h new file mode 100644 index 000000000..8b2c77b7b --- /dev/null +++ b/vpr7_rram/vpr/SRC/spice/spice_utils.h @@ -0,0 +1,230 @@ + +/* Enumeration for the types of measurements*/ +enum e_measure_type { + SPICE_MEASURE_LEAKAGE_POWER, SPICE_MEASURE_DYNAMIC_POWER +}; + +/* Subroutines declarations */ + +void fprint_spice_head(FILE* fp, + char* usage); + + +int rec_fprint_spice_model_global_ports(FILE* fp, + t_spice_model* cur_spice_model, + boolean recursive); + +int fprint_spice_global_ports(FILE* fp, t_llist* head); + +void fprint_spice_generic_testbench_global_ports(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info, + t_llist* head); + +void fprint_spice_sram_one_outport(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info, + int cur_sram, + int port_type_index); + +void fprint_spice_one_specific_sram_subckt(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info, + t_spice_model* parent_spice_model, + char* vdd_port_name, + int sram_index); + +void fprint_spice_one_sram_subckt(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info, + t_spice_model* parent_spice_model, + char* vdd_port_name); + +void fprint_voltage_pulse_params(FILE* fp, + int init_val, + float density, + float probability); + + +void init_include_user_defined_netlists(t_spice spice); + +void fprint_include_user_defined_netlists(FILE* fp, + t_spice spice); + +void fprint_splited_vdds_spice_model(FILE* fp, + enum e_spice_model_type spice_model_type, + t_spice spice); + +void fprint_grid_splited_vdds_spice_model(FILE* fp, int grid_x, int grid_y, + enum e_spice_model_type spice_model_type, + t_spice spice); + +void fprint_global_vdds_spice_model(FILE* fp, + enum e_spice_model_type spice_model_type, + t_spice spice); + +void fprint_grid_global_vdds_spice_model(FILE* fp, int x, int y, + enum e_spice_model_type spice_model_type, + t_spice spice); + +void fprint_global_pad_ports_spice_model(FILE* fp, + t_spice spice); + +void fprint_spice_global_vdd_switch_boxes(FILE* fp); + +void fprint_spice_global_vdd_connection_boxes(FILE* fp); + +void fprint_measure_vdds_spice_model(FILE* fp, + enum e_spice_model_type spice_model_type, + enum e_measure_type meas_type, + int num_cycle, + t_spice spice, + boolean leakage_only); + +void fprint_measure_grid_vdds_spice_model(FILE* fp, int grid_x, int grid_y, + enum e_spice_model_type spice_model_type, + enum e_measure_type meas_type, + int num_cycle, + t_spice spice, + boolean leakage_only); + +void fprint_call_defined_grids(FILE* fp); + +void fprint_call_defined_one_channel(FILE* fp, + t_rr_type chan_type, + int x, int y, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices); + +void fprint_call_defined_channels(FILE* fp, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices); + +void fprint_call_defined_one_connection_box(FILE* fp, + t_cb cur_cb_info); + +void fprint_call_defined_connection_boxes(FILE* fp); + +void fprint_call_defined_one_switch_box(FILE* fp, + t_sb cur_sb_info); + +void fprint_call_defined_switch_boxes(FILE* fp); + +void fprint_one_design_param_w_wo_variation(FILE* fp, + char* param_name, + float avg_val, + t_spice_mc_variation_params variation_params); + +void fprint_tech_lib(FILE* fp, + t_spice_mc_variation_params cmos_variation_params, + t_spice_tech_lib tech_lib); + +void fprint_spice_circuit_param(FILE* fp, + t_spice_mc_params mc_params, + int num_spice_models, + t_spice_model* spice_model); + +void fprint_spice_netlist_measurement_one_design_param(FILE* fp, + char* param_name); + +void fprint_spice_netlist_generic_measurements(FILE* fp, + t_spice_mc_params mc_params, + int num_spice_models, + t_spice_model* spice_model); + +void fprint_spice_options(FILE* fp, + t_spice_params spice_params); + +void fprint_spice_include_key_subckts(FILE* fp, + char* subckt_dir_path); + +void fprint_spice_include_param_headers(FILE* fp, + char* include_dir_path); + +void fprint_spice_netlist_transient_setting(FILE* fp, + t_spice spice, + int num_sim_clock_cycles, + boolean leakage_only); + +void fprint_stimulate_dangling_one_grid_pin(FILE* fp, + int x, int y, + int height, int side, int pin_index, + t_ivec*** LL_rr_node_indices); + +void fprint_stimulate_dangling_io_grid_pins(FILE* fp, + int x, int y); + +void fprint_stimulate_dangling_normal_grid_pins(FILE* fp, + int x, int y); + +void fprint_stimulate_dangling_grid_pins(FILE* fp); + +void init_logical_block_spice_model_temp_used(t_spice_model* spice_model); + +void init_logical_block_spice_model_type_temp_used(int num_spice_models, t_spice_model* spice_model, + enum e_spice_model_type spice_model_type); + +void fprint_global_vdds_logical_block_spice_model(FILE* fp, + t_spice_model* spice_model); + +void fprint_splited_vdds_logical_block_spice_model(FILE* fp, + t_spice_model* spice_model); + +void fprint_measure_vdds_logical_block_spice_model(FILE* fp, + t_spice_model* spice_model, + enum e_measure_type meas_type, + int num_clock_cycle, + boolean leakage_only); + +void fprint_spice_testbench_wire_one_global_port_stimuli(FILE* fp, + t_spice_model_port* cur_global_port, + char* voltage_stimuli_port_name); + +void fprint_spice_testbench_global_sram_inport_stimuli(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info); + +void fprint_spice_testbench_global_vdd_port_stimuli(FILE* fp, + char* global_vdd_port_name, + char* voltage_level); + +void fprint_spice_testbench_global_ports_stimuli(FILE* fp, + t_llist* head); + +void fprint_spice_testbench_generic_global_ports_stimuli(FILE* fp, + int num_clock); + +float find_spice_testbench_pb_pin_mux_load_inv_size(t_spice_model* fan_out_spice_model); + +float find_spice_testbench_rr_mux_load_inv_size(t_rr_node* load_rr_node, + int switch_index); + +void fprint_spice_testbench_pb_graph_pin_inv_loads_rec(FILE* fp, int* testbench_load_cnt, + int grid_x, int grid_y, + t_pb_graph_pin* src_pb_graph_pin, + t_pb* src_pb, + char* outport_name, + boolean consider_parent_node, + t_ivec*** LL_rr_node_indices); + +char* fprint_spice_testbench_rr_node_load_version(FILE* fp, int* testbench_load_cnt, + int num_segments, + t_segment_inf* segments, + int load_level, + t_rr_node cur_rr_node, + char* outport_name); + +void fprint_spice_testbench_one_cb_mux_loads(FILE* fp, int* testbench_load_cnt, + t_rr_node* src_rr_node, + char* outport_name, + t_ivec*** LL_rr_node_indices); + +void fprint_spice_testbench_one_grid_pin_stimulation(FILE* fp, int x, int y, + int height, int side, + int ipin, + t_ivec*** LL_rr_node_indices); + +void fprint_spice_testbench_one_grid_pin_loads(FILE* fp, int x, int y, + int height, int side, + int ipin, + int* testbench_load_cnt, + t_ivec*** LL_rr_node_indices); + +t_llist* add_one_spice_tb_info_to_llist(t_llist* cur_head, + char* tb_file_path, + int num_sim_clock_cycles); diff --git a/vpr7_rram/vpr/SRC/syn_verilog/syn_verilog_api.c b/vpr7_rram/vpr/SRC/syn_verilog/syn_verilog_api.c new file mode 100644 index 000000000..a1297774b --- /dev/null +++ b/vpr7_rram/vpr/SRC/syn_verilog/syn_verilog_api.c @@ -0,0 +1,279 @@ +/***********************************/ +/* Synthesizable Verilog Dumping */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph.h" +#include "vpr_utils.h" +#include "path_delay.h" +#include "stats.h" + +/* Include FPGA-SPICE utils */ +#include "read_xml_spice_util.h" +#include "linkedlist.h" +#include "fpga_spice_utils.h" +#include "fpga_spice_backannotate_utils.h" +#include "fpga_spice_globals.h" +#include "fpga_spice_bitstream.h" + +/* Include SynVerilog headers */ +#include "verilog_global.h" +#include "verilog_utils.h" +#include "verilog_submodules.h" +#include "verilog_decoder.h" +#include "verilog_pbtypes.h" +#include "verilog_routing.h" +#include "verilog_top_netlist.h" + +/* Global Variants available only in this source file */ +static char* default_verilog_dir_name = "syn_verilogs/"; +static char* default_lb_dir_name = "lb/"; +static char* default_rr_dir_name = "routing/"; +static char* default_submodule_dir_name = "sub_module/"; + +/***** Subroutines *****/ +/* Alloc array that records Configuration bits for : + * (1) Switch blocks + * (2) Connection boxes + * TODO: Can be improved in alloc strategy to be more memory efficient! + */ +static +void alloc_global_routing_conf_bits() { + int i; + + /* Alloc array for Switch blocks */ + num_conf_bits_sb = (int**)my_malloc((nx+1)*sizeof(int*)); + for (i = 0; i < (nx + 1); i++) { + num_conf_bits_sb[i] = (int*)my_calloc((ny+1), sizeof(int)); + } + + /* Alloc array for Connection blocks */ + num_conf_bits_cbx = (int**)my_malloc((nx+1)*sizeof(int*)); + for (i = 0; i < (nx + 1); i++) { + num_conf_bits_cbx[i] = (int*)my_calloc((ny+1), sizeof(int)); + } + + num_conf_bits_cby = (int**)my_malloc((nx+1)*sizeof(int*)); + for (i = 0; i < (nx + 1); i++) { + num_conf_bits_cby[i] = (int*)my_calloc((ny+1), sizeof(int)); + } + + return; +} + +static +void free_global_routing_conf_bits() { + int i; + + /* Free array for Switch blocks */ + for (i = 0; i < (nx + 1); i++) { + my_free(num_conf_bits_sb[i]); + } + my_free(num_conf_bits_sb); + + /* Free array for Connection box */ + for (i = 0; i < (nx + 1); i++) { + my_free(num_conf_bits_cbx[i]); + } + my_free(num_conf_bits_cbx); + + for (i = 0; i < (nx + 1); i++) { + my_free(num_conf_bits_cby[i]); + } + my_free(num_conf_bits_cby); + + return; +} + +/* Top-level function*/ +void vpr_dump_syn_verilog(t_vpr_setup vpr_setup, + t_arch Arch, + char* circuit_name) { + /* Timer */ + clock_t t_start; + clock_t t_end; + float run_time_sec; + + int num_clocks = Arch.spice->spice_params.stimulate_params.num_clocks; + /* int vpr_crit_path_delay = Arch.spice->spice_params.stimulate_params.vpr_crit_path_delay; */ + + /* Directory paths */ + char* verilog_dir_formatted = NULL; + char* submodule_dir_path= NULL; + char* lb_dir_path = NULL; + char* rr_dir_path = NULL; + char* top_netlist_file = NULL; + char* top_netlist_path = NULL; + char* bitstream_file_name = NULL; + char* bitstream_file_path = NULL; + char* top_testbench_file_name = NULL; + char* top_testbench_file_path = NULL; + char* blif_testbench_file_name = NULL; + char* blif_testbench_file_path = NULL; + + char* chomped_parent_dir = NULL; + char* chomped_circuit_name = NULL; + + /* Check if the routing architecture we support*/ + if (UNI_DIRECTIONAL != vpr_setup.RoutingArch.directionality) { + vpr_printf(TIO_MESSAGE_ERROR, "FPGA synthesizable Verilog dumping only support uni-directional routing architecture!\n"); + exit(1); + } + + /* We don't support mrFPGA */ +#ifdef MRFPGA_H + if (is_mrFPGA) { + vpr_printf(TIO_MESSAGE_ERROR, "FPGA synthesizable verilog dumping do not support mrFPGA!\n"); + exit(1); + } +#endif + + assert ( TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_syn_verilog); + + /* VerilogGenerator formally starts*/ + vpr_printf(TIO_MESSAGE_INFO, "\nFPGA synthesizable verilog generator starts...\n"); + + /* Start time count */ + t_start = clock(); + + /* Format the directory paths */ + split_path_prog_name(circuit_name, '/', &chomped_parent_dir, &chomped_circuit_name); + + if (NULL != vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.syn_verilog_dump_dir) { + verilog_dir_formatted = format_dir_path(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.syn_verilog_dump_dir); + } else { + verilog_dir_formatted = format_dir_path(my_strcat(format_dir_path(chomped_parent_dir),default_verilog_dir_name)); + } + /* lb directory */ + (lb_dir_path) = my_strcat(verilog_dir_formatted, default_lb_dir_name); + /* routing resources directory */ + (rr_dir_path) = my_strcat(verilog_dir_formatted, default_rr_dir_name); + /* submodule_dir_path */ + (submodule_dir_path) = my_strcat(verilog_dir_formatted, default_submodule_dir_name); + /* Top netlists dir_path */ + top_netlist_file = my_strcat(chomped_circuit_name, verilog_top_postfix); + top_netlist_path = my_strcat(verilog_dir_formatted, top_netlist_file); + bitstream_file_name = my_strcat(chomped_circuit_name, bitstream_verilog_file_postfix); + bitstream_file_path = my_strcat(verilog_dir_formatted, bitstream_file_name); + top_testbench_file_name = my_strcat(chomped_circuit_name, top_testbench_verilog_file_postfix); + top_testbench_file_path = my_strcat(verilog_dir_formatted, top_testbench_file_name); + blif_testbench_file_name = my_strcat(chomped_circuit_name, blif_testbench_verilog_file_postfix); + blif_testbench_file_path = my_strcat(verilog_dir_formatted, blif_testbench_file_name); + + /* Create directories */ + create_dir_path(verilog_dir_formatted); + create_dir_path(lb_dir_path); + create_dir_path(rr_dir_path); + create_dir_path(submodule_dir_path); + + /* assign the global variable of SRAM model */ + assert(NULL != Arch.sram_inf.verilog_sram_inf_orgz); /* Check !*/ + sram_verilog_model = Arch.sram_inf.verilog_sram_inf_orgz->spice_model; + sram_verilog_orgz_type = Arch.sram_inf.verilog_sram_inf_orgz->type; + /* initialize the SRAM organization information struct */ + sram_verilog_orgz_info = alloc_one_sram_orgz_info(); + init_sram_orgz_info(sram_verilog_orgz_info, sram_verilog_orgz_type, sram_verilog_model, nx + 2, ny + 2); + /* Check all the SRAM port is using the correct SRAM SPICE MODEL */ + config_spice_models_sram_port_spice_model(Arch.spice->num_spice_model, + Arch.spice->spice_models, + Arch.sram_inf.verilog_sram_inf_orgz->spice_model); + + /* Assign global variables of input and output pads */ + iopad_verilog_model = find_iopad_spice_model(Arch.spice->num_spice_model, Arch.spice->spice_models); + assert(NULL != iopad_verilog_model); + + /* zero the counter of each spice_model */ + zero_spice_models_cnt(Arch.spice->num_spice_model, Arch.spice->spice_models); + + /* Initialize the user-defined verilog netlists to be included */ + init_list_include_verilog_netlists(Arch.spice); + + /* Dump internal structures of submodules */ + dump_verilog_submodules(submodule_dir_path, Arch, &vpr_setup.RoutingArch); + + /* Initial global variables about configuration bits */ + alloc_global_routing_conf_bits(); + + /* Initialize the number of configuration bits of all the grids */ + vpr_printf(TIO_MESSAGE_INFO, "Count the number of configuration bits, IO pads in each logic block...\n"); + /* init_grids_num_conf_bits(sram_verilog_orgz_type); */ + init_grids_num_conf_bits(sram_verilog_orgz_info); + init_grids_num_iopads(); + /* init_grids_num_mode_bits(); */ + + /* Dump routing resources: switch blocks, connection blocks and channel tracks */ + dump_verilog_routing_resources(rr_dir_path, Arch, &vpr_setup.RoutingArch, + num_rr_nodes, rr_node, rr_node_indices); + + /* Dump logic blocks */ + dump_verilog_logic_blocks(lb_dir_path, &Arch); + + /* Dump decoder modules only when memory bank is required */ + switch(sram_verilog_orgz_type) { + case SPICE_SRAM_STANDALONE: + case SPICE_SRAM_SCAN_CHAIN: + break; + case SPICE_SRAM_MEMORY_BANK: + /* Dump verilog decoder */ + dump_verilog_decoder(submodule_dir_path); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization in Verilog Generator!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Dump top-level verilog */ + dump_verilog_top_netlist(chomped_circuit_name, top_netlist_path, lb_dir_path, rr_dir_path, + num_rr_nodes, rr_node, rr_node_indices, num_clocks, *(Arch.spice)); + + /* Dump SDC constraints */ + // dump_verilog_sdc_file(); + + /* dump verilog testbench only for top-level */ + dump_verilog_top_testbench(chomped_circuit_name, top_testbench_file_path, num_clocks, + vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, *(Arch.spice)); + + /* dump verilog testbench only for input blif */ + dump_verilog_input_blif_testbench(chomped_circuit_name, blif_testbench_file_path, num_clocks, + vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, *(Arch.spice)); + + /* Dump bitstream file */ + dump_fpga_spice_bitstream(bitstream_file_path, chomped_circuit_name, sram_verilog_orgz_info); + + /* End time count */ + t_end = clock(); + + run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, "Synthesizable verilog dumping took %g seconds\n", run_time_sec); + + /* Free global array */ + free_global_routing_conf_bits(); + + /* Free sram_orgz_info */ + free_sram_orgz_info(sram_verilog_orgz_info, + sram_verilog_orgz_info->type, + nx + 2, ny + 2); + /* Free */ + my_free(verilog_dir_formatted); + my_free(lb_dir_path); + my_free(rr_dir_path); + my_free(top_netlist_file); + my_free(top_netlist_path); + my_free(submodule_dir_path); + + return; +} diff --git a/vpr7_rram/vpr/SRC/syn_verilog/syn_verilog_api.h b/vpr7_rram/vpr/SRC/syn_verilog/syn_verilog_api.h new file mode 100644 index 000000000..8723d1038 --- /dev/null +++ b/vpr7_rram/vpr/SRC/syn_verilog/syn_verilog_api.h @@ -0,0 +1,4 @@ + +void vpr_dump_syn_verilog(t_vpr_setup vpr_setup, + t_arch Arch, + char* circuit_name); diff --git a/vpr7_rram/vpr/SRC/syn_verilog/verilog_decoder.c b/vpr7_rram/vpr/SRC/syn_verilog/verilog_decoder.c new file mode 100644 index 000000000..dee1882e0 --- /dev/null +++ b/vpr7_rram/vpr/SRC/syn_verilog/verilog_decoder.c @@ -0,0 +1,227 @@ +/***********************************/ +/* Synthesizable Verilog Dumping */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph.h" +#include "vpr_utils.h" +#include "path_delay.h" +#include "stats.h" + +/* Include FPGA-SPICE utils */ +#include "linkedlist.h" +#include "fpga_spice_utils.h" +#include "spice_mux.h" +#include "fpga_spice_globals.h" + +/* Include verilog utils */ +#include "verilog_global.h" +#include "verilog_utils.h" + +/***** Subroutines *****/ +void determine_verilog_blwl_decoder_size(INP t_sram_orgz_info* cur_sram_verilog_orgz_info, + OUTP int* num_array_bl, OUTP int* num_array_wl, + OUTP int* bl_decoder_size, OUTP int* wl_decoder_size) { + t_spice_model* mem_model = NULL; + int num_mem_bit; + int num_reserved_bl, num_reserved_wl; + + /* Check */ + assert(SPICE_SRAM_MEMORY_BANK == sram_verilog_orgz_info->type); + + num_mem_bit = get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info); + get_sram_orgz_info_num_blwl(sram_verilog_orgz_info, num_array_bl, num_array_wl); + get_sram_orgz_info_reserved_blwl(sram_verilog_orgz_info, &num_reserved_bl, &num_reserved_wl); + + /* Sizes of decodes depend on the Memory technology */ + get_sram_orgz_info_mem_model(sram_verilog_orgz_info, &mem_model); + switch (mem_model->design_tech) { + /* CMOS SRAM*/ + case SPICE_MODEL_DESIGN_CMOS: + /* SRAMs can efficiently share BLs and WLs, + * Actual number of BLs and WLs will be sqrt(num_bls) and sqrt(num_wls) + */ + assert(0 == num_reserved_bl); + assert(0 == num_reserved_wl); + (*num_array_bl) = ceil(sqrt(*num_array_bl)); + (*num_array_wl) = ceil(sqrt(*num_array_wl)); + (*bl_decoder_size) = determine_decoder_size(*num_array_bl); + (*wl_decoder_size) = determine_decoder_size(*num_array_wl); + break; + /* RRAM */ + case SPICE_MODEL_DESIGN_RRAM: + /* Currently we do not have more efficient way to share the BLs and WLs as CMOS SRAMs */ + (*bl_decoder_size) = determine_decoder_size(*num_array_bl); + (*wl_decoder_size) = determine_decoder_size(*num_array_wl); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology [CMOS|RRAM] for memory technology!\n", + __FILE__, __LINE__); + exit(1); + } + + return; +} + +void dump_verilog_decoder(char* submodule_dir) { + int num_array_bl, num_array_wl; + int bl_decoder_size, wl_decoder_size; + FILE* fp = NULL; + t_spice_model* mem_model = NULL; + boolean bl_inverted = FALSE; + boolean wl_inverted = FALSE; + + char* verilog_name = my_strcat(submodule_dir, decoders_verilog_file_name); + + /* Print the muxes netlist*/ + fp = fopen(verilog_name, "w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create decoder SPICE netlist %s",__FILE__, __LINE__, verilog_name); + exit(1); + } + + /* Check */ + assert(SPICE_SRAM_MEMORY_BANK == sram_verilog_orgz_info->type); + + /* Get number of BLs,WLs and decoder sizes */ + determine_verilog_blwl_decoder_size(sram_verilog_orgz_info, + &num_array_bl, &num_array_wl, + &bl_decoder_size, &wl_decoder_size); + + /* Generate file header*/ + vpr_printf(TIO_MESSAGE_INFO, "Writing Decoder verilog netlist...\n"); + + /* Generate the descriptions*/ + dump_verilog_file_header(fp, " Verilog Decoders"); + + /* Different design technology requires different BL decoder logic */ + get_sram_orgz_info_mem_model(sram_verilog_orgz_info, &mem_model); + /* Find if we need an inversion of the BL */ + check_mem_model_blwl_inverted(mem_model, SPICE_MODEL_PORT_BL, &bl_inverted); + check_mem_model_blwl_inverted(mem_model, SPICE_MODEL_PORT_WL, &wl_inverted); + + switch (mem_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: /* CMOS SRAM*/ + /* SRAM technology requires its BL decoder has an additional input called data_in + * only the selected BL will be set to the value of data_in, other BLs will be in high-resistance state + */ + /* Start the BL decoder module definition */ + fprintf(fp, "//----- BL Decoder convert %d bits to binary %d bits -----\n", + bl_decoder_size, num_array_bl); + fprintf(fp, "module bl_decoder%dto%d (\n", + bl_decoder_size, num_array_bl); + fprintf(fp, "input wire enable,\n"); + fprintf(fp, "input wire [%d:0] addr_in,\n", + bl_decoder_size - 1); + fprintf(fp, "input wire data_in,\n"); + fprintf(fp, "output reg [0:%d] addr_out\n", + num_array_bl - 1); + fprintf(fp, ");\n"); + + /* Wee need to know the default value of bl port and wl port */ + + /* Internal logics */ + + fprintf(fp, "always@(addr_out,addr_in,enable, data_in)\n"); + fprintf(fp, "begin\n"); + fprintf(fp, "\taddr_out = %d'bz;\n", num_array_bl); + fprintf(fp, "\tif (1'b1 == enable) begin\n"); + fprintf(fp, "\t\taddr_out[addr_in] = data_in;\n"); + fprintf(fp, "\tend\n"); + fprintf(fp, "end\n"); + + fprintf(fp, "endmodule\n"); + break; + case SPICE_MODEL_DESIGN_RRAM: /* RRAM */ + /* For RRAM technology, BL decoder should be same as the WL decoder */ + /* Start the BL decoder module definition */ + fprintf(fp, "//----- BL Decoder convert %d bits to binary %d bits -----\n", + bl_decoder_size, num_array_bl); + fprintf(fp, "module bl_decoder%dto%d (\n", + bl_decoder_size, num_array_bl); + fprintf(fp, "input wire enable,\n"); + fprintf(fp, "input wire [%d:0] addr_in,\n", + bl_decoder_size-1); + fprintf(fp, "output reg [0:%d] addr_out\n", + num_array_bl-1); + fprintf(fp, ");\n"); + + /* Internal logics */ + fprintf(fp, "always@(addr_out,addr_in,enable)\n"); + fprintf(fp, "begin\n"); + if (TRUE == bl_inverted) { + fprintf(fp, "\taddr_out = %d'b1;\n", num_array_bl); + } else { + assert (FALSE == bl_inverted); + fprintf(fp, "\taddr_out = %d'b0;\n", num_array_bl); + } + fprintf(fp, "\tif (1'b1 == enable) begin\n"); + if (TRUE == bl_inverted) { + fprintf(fp, "\t\taddr_out[addr_in] = 1'b0;\n"); + } else { + assert (FALSE == bl_inverted); + fprintf(fp, "\t\taddr_out[addr_in] = 1'b1;\n"); + } + fprintf(fp, "\tend\n"); + fprintf(fp, "end\n"); + + fprintf(fp, "endmodule\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology [CMOS|RRAM] for memory technology!\n", + __FILE__, __LINE__); + exit(1); + } + + /* WL decoder logic is the same whatever SRAM or RRAM technology is considered */ + /* Start the WL module definition */ + fprintf(fp, "//----- WL Decoder convert %d bits to binary %d bits -----\n", + wl_decoder_size, num_array_wl); + fprintf(fp, "module wl_decoder%dto%d (\n", + wl_decoder_size, num_array_wl); + fprintf(fp, "input wire enable,\n"); + fprintf(fp, "input wire [%d:0] addr_in,\n", + wl_decoder_size-1); + fprintf(fp, "output reg [0:%d] addr_out\n", + num_array_bl-1); + fprintf(fp, ");\n"); + + /* Internal logics */ + fprintf(fp, "always@(addr_out,addr_in,enable)\n"); + fprintf(fp, "begin\n"); + if (TRUE == wl_inverted) { + fprintf(fp, "\taddr_out = %d'b1;\n", num_array_wl); + } else { + assert (FALSE == wl_inverted); + fprintf(fp, "\taddr_out = %d'b0;\n", num_array_wl); + } + fprintf(fp, "\tif (1'b1 == enable) begin\n"); + if (TRUE == wl_inverted) { + fprintf(fp, "\t\taddr_out[addr_in] = 1'b0;\n"); + } else { + assert (FALSE == wl_inverted); + fprintf(fp, "\t\taddr_out[addr_in] = 1'b1;\n"); + } + fprintf(fp, "\tend\n"); + fprintf(fp, "end\n"); + + fprintf(fp, "endmodule\n"); + + /* Close the file*/ + fclose(fp); + + return; +} diff --git a/vpr7_rram/vpr/SRC/syn_verilog/verilog_decoder.h b/vpr7_rram/vpr/SRC/syn_verilog/verilog_decoder.h new file mode 100644 index 000000000..12c91fc91 --- /dev/null +++ b/vpr7_rram/vpr/SRC/syn_verilog/verilog_decoder.h @@ -0,0 +1,7 @@ + + +void determine_verilog_blwl_decoder_size(INP t_sram_orgz_info* cur_sram_verilog_orgz_info, + OUTP int* num_array_bl, OUTP int* num_array_wl, + OUTP int* bl_decoder_size, OUTP int* wl_decoder_size); + +void dump_verilog_decoder(char* submodule_dir); diff --git a/vpr7_rram/vpr/SRC/syn_verilog/verilog_global.c b/vpr7_rram/vpr/SRC/syn_verilog/verilog_global.c new file mode 100644 index 000000000..9e2c3b71a --- /dev/null +++ b/vpr7_rram/vpr/SRC/syn_verilog/verilog_global.c @@ -0,0 +1,37 @@ +/***********************************/ +/* Synthesizable Verilog Dumping */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include "spice_types.h" +#include "linkedlist.h" +#include "fpga_spice_globals.h" +#include "verilog_global.h" + +char* verilog_top_postfix = "_top.v"; +char* bitstream_verilog_file_postfix = ".bitstream"; +char* top_testbench_verilog_file_postfix = "_top_tb.v"; +char* blif_testbench_verilog_file_postfix = "_blif_tb.v"; +char* logic_block_verilog_file_name = "logic_blocks.v"; +char* luts_verilog_file_name = "luts.v"; +char* routing_verilog_file_name = "routing.v"; +char* muxes_verilog_file_name = "muxes.v"; +char* wires_verilog_file_name = "wires.v"; +char* essentials_verilog_file_name = "inv_buf_passgate.v"; +char* decoders_verilog_file_name = "decoders.v"; + +char* verilog_mux_basis_posfix = "_basis"; +char* verilog_mux_special_basis_posfix = "_special_basis"; + +/* SRAM SPICE MODEL should be set as global*/ +t_spice_model* sram_verilog_model = NULL; +enum e_sram_orgz sram_verilog_orgz_type = SPICE_SRAM_STANDALONE; +t_sram_orgz_info* sram_verilog_orgz_info = NULL; + +/* Input and Output Pad spice model. should be set as global */ +t_spice_model* iopad_verilog_model = NULL; + +/* Linked-list that stores all the configuration bits */ +t_llist* conf_bits_head = NULL; + +int verilog_default_signal_init_value = 0; diff --git a/vpr7_rram/vpr/SRC/syn_verilog/verilog_global.h b/vpr7_rram/vpr/SRC/syn_verilog/verilog_global.h new file mode 100644 index 000000000..f98c3355b --- /dev/null +++ b/vpr7_rram/vpr/SRC/syn_verilog/verilog_global.h @@ -0,0 +1,37 @@ +/* global parameters for dumping synthesizable verilog */ +extern char* verilog_top_postfix; +extern char* bitstream_verilog_file_postfix; +extern char* top_testbench_verilog_file_postfix; +extern char* blif_testbench_verilog_file_postfix; +extern char* logic_block_verilog_file_name; +extern char* luts_verilog_file_name; +extern char* routing_verilog_file_name; +extern char* muxes_verilog_file_name; +extern char* wires_verilog_file_name; +extern char* essentials_verilog_file_name; +extern char* decoders_verilog_file_name; +extern char* verilog_mux_basis_posfix; +extern char* verilog_mux_special_basis_posfix; + +extern t_spice_model* sram_verilog_model; +extern enum e_sram_orgz sram_verilog_orgz_type; +extern t_sram_orgz_info* sram_verilog_orgz_info; + +/* Input and Output Pad spice model. should be set as global */ +extern t_spice_model* inpad_verilog_model; +extern t_spice_model* outpad_verilog_model; +extern t_spice_model* iopad_verilog_model; + +/* Linked-list that stores all the configuration bits */ +extern t_llist* conf_bits_head; + +extern int verilog_default_signal_init_value; + +enum e_dump_verilog_port_type { +VERILOG_PORT_INPUT, +VERILOG_PORT_OUTPUT, +VERILOG_PORT_INOUT, +VERILOG_PORT_WIRE, +VERILOG_PORT_REG, +VERILOG_PORT_CONKT +}; diff --git a/vpr7_rram/vpr/SRC/syn_verilog/verilog_lut.c b/vpr7_rram/vpr/SRC/syn_verilog/verilog_lut.c new file mode 100644 index 000000000..56eb8221b --- /dev/null +++ b/vpr7_rram/vpr/SRC/syn_verilog/verilog_lut.c @@ -0,0 +1,358 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph.h" +#include "rr_graph_swseg.h" +#include "vpr_utils.h" + +/* Include spice support headers*/ +#include "linkedlist.h" +#include "fpga_spice_utils.h" +#include "fpga_spice_globals.h" + +/* Include verilog support headers*/ +#include "verilog_global.h" +#include "verilog_utils.h" +#include "verilog_pbtypes.h" +#include "verilog_lut.h" + + +/***** Subroutines *****/ +void dump_verilog_pb_primitive_lut(FILE* fp, + char* subckt_prefix, + t_logical_block* mapped_logical_block, + t_pb_graph_node* cur_pb_graph_node, + int index, + t_spice_model* verilog_model) { + int i; + int* sram_bits = NULL; /* decoded SRAM bits */ + int truth_table_length = 0; + char** truth_table = NULL; + int lut_size = 0; + int num_input_port = 0; + t_spice_model_port** input_ports = NULL; + int num_output_port = 0; + t_spice_model_port** output_ports = NULL; + int num_sram_port = 0; + t_spice_model_port** sram_ports = NULL; + + int num_pb_type_input_port = 0; + t_port** pb_type_input_ports = NULL; + + int num_pb_type_output_port = 0; + t_port** pb_type_output_ports = NULL; + + char* formatted_subckt_prefix = format_verilog_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/ + t_pb_type* cur_pb_type = NULL; + char* port_prefix = NULL; + int cur_num_sram = 0; + int num_sram = 0; + /* For each SRAM, we could have multiple BLs/WLs */ + int num_bl_ports = 0; + t_spice_model_port** bl_port = NULL; + int num_wl_ports = 0; + t_spice_model_port** wl_port = NULL; + int num_bl_per_sram = 0; + int num_wl_per_sram = 0; + int num_conf_bits = 0; + int num_reserved_conf_bits = 0; + int cur_bl, cur_wl; + t_spice_model* mem_model = NULL; + + /* Ensure a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Ensure a valid pb_graph_node */ + if (NULL == cur_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb_graph_node!\n", + __FILE__, __LINE__); + exit(1); + } + /* Asserts */ + assert(SPICE_MODEL_LUT == verilog_model->type); + + /* Check if this is an idle logical block mapped*/ + if (NULL != mapped_logical_block) { + truth_table = assign_lut_truth_table(mapped_logical_block, &truth_table_length); + /* Back-annotate to logical block */ + mapped_logical_block->mapped_spice_model = verilog_model; + mapped_logical_block->mapped_spice_model_index = verilog_model->cnt; + } + /* Determine size of LUT*/ + input_ports = find_spice_model_ports(verilog_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + output_ports = find_spice_model_ports(verilog_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + assert(1 == num_input_port); + assert(1 == num_output_port); + lut_size = input_ports[0]->size; + assert(1 == output_ports[0]->size); + /* Find SRAM ports */ + sram_ports = find_spice_model_ports(verilog_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); + assert(1 == num_sram_port); + /* Count the number of configuration bits */ + num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1); + /* Get memory model */ + get_sram_orgz_info_mem_model(sram_verilog_orgz_info, &mem_model); + + /* Find the number of BLs/WLs of each SRAM */ + switch (sram_verilog_orgz_type) { + case SPICE_SRAM_MEMORY_BANK: + /* Detect the SRAM SPICE model linked to this SRAM port */ + assert(NULL != sram_ports[0]->spice_model); + assert(SPICE_MODEL_SRAM == sram_ports[0]->spice_model->type); + find_bl_wl_ports_spice_model(sram_ports[0]->spice_model, + &num_bl_ports, &bl_port, &num_wl_ports, &wl_port); + assert(1 == num_bl_ports); + assert(1 == num_wl_ports); + num_bl_per_sram = bl_port[0]->size; + num_wl_per_sram = wl_port[0]->size; + /* Asserts */ + assert(num_bl_per_sram == num_wl_per_sram); + break; + case SPICE_SRAM_STANDALONE: + case SPICE_SRAM_SCAN_CHAIN: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid SRAM organization type!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Generate sram bits*/ + sram_bits = generate_lut_sram_bits(truth_table_length, truth_table, + lut_size, sram_ports[0]->default_val); + + /* Print the subckts*/ + cur_pb_type = cur_pb_graph_node->pb_type; + + /* Comment lines */ + fprintf(fp, "//----- LUT Verilog module: %s%s_%d_ -----\n", + formatted_subckt_prefix, cur_pb_type->name, index); + + /* Simplify the prefix, make the SPICE netlist readable*/ + port_prefix = (char*)my_malloc(sizeof(char)* + (strlen(cur_pb_type->name) + 1 + + strlen(my_itoa(index)) + 1 + 1)); + sprintf(port_prefix, "%s_%d_", cur_pb_type->name, index); + + /* Subckt definition*/ + fprintf(fp, "module %s%s_%d_ (", + formatted_subckt_prefix, cur_pb_type->name, index); + fprintf(fp, "\n"); + /* Only dump the global ports belonging to a spice_model */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE)) { + fprintf(fp, ",\n"); + } + /* Print inputs, outputs, inouts, clocks, NO SRAMs*/ + dump_verilog_pb_type_ports(fp, port_prefix, 0, cur_pb_type, TRUE, TRUE); + /* Print SRAM ports */ + cur_num_sram = get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info); + get_sram_orgz_info_num_blwl(sram_verilog_orgz_info, &cur_bl, &cur_wl); + /* connect to reserved BL/WLs ? */ + num_reserved_conf_bits = count_num_reserved_conf_bits_one_spice_model(verilog_model, sram_verilog_orgz_info->type, 0); + /* Get the number of configuration bits required by this MUX */ + num_conf_bits = count_num_conf_bits_one_spice_model(verilog_model, sram_verilog_orgz_info->type, 0); + /* Reserved sram ports */ + dump_verilog_reserved_sram_ports(fp, sram_verilog_orgz_info, + 0, num_reserved_conf_bits - 1, + VERILOG_PORT_INPUT); + if ( 0 < num_reserved_conf_bits) { + fprintf(fp, ",\n"); + } + /* Normal sram ports */ + dump_verilog_sram_ports(fp, sram_verilog_orgz_info, + cur_num_sram, cur_num_sram + num_conf_bits - 1, + VERILOG_PORT_INPUT); + /* Local Vdd and gnd*/ + fprintf(fp, ");\n"); + /* Definition ends*/ + + /* Specify inputs are wires */ + pb_type_input_ports = find_pb_type_ports_match_spice_model_port_type(cur_pb_type, SPICE_MODEL_PORT_INPUT, &num_pb_type_input_port); + assert(1 == num_pb_type_input_port); + fprintf(fp, "wire [0:%d] %s__%s;\n", + input_ports[0]->size - 1, port_prefix, pb_type_input_ports[0]->name); + for (i = 0; i < input_ports[0]->size; i++) { + fprintf(fp, "assign %s__%s[%d] = %s__%s_%d_;\n", + port_prefix, pb_type_input_ports[0]->name, i, + port_prefix, pb_type_input_ports[0]->name, i); + } + /* Specify outputs are wires */ + pb_type_output_ports = find_pb_type_ports_match_spice_model_port_type(cur_pb_type, SPICE_MODEL_PORT_OUTPUT, &num_pb_type_output_port); + assert(1 == num_pb_type_output_port); + fprintf(fp, "wire [0:%d] %s__%s;\n", + output_ports[0]->size - 1, port_prefix, pb_type_output_ports[0]->name); + for (i = 0; i < output_ports[0]->size; i++) { + fprintf(fp, "assign %s__%s_%d_ = %s__%s[%d];\n", + port_prefix, pb_type_output_ports[0]->name, i, + port_prefix, pb_type_output_ports[0]->name, i); + } + + /* Specify SRAM output are wires */ + cur_num_sram = get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info); + dump_verilog_sram_config_bus_internal_wires(fp, sram_verilog_orgz_info, cur_num_sram, cur_num_sram + num_sram - 1); + /* + fprintf(fp, "wire [%d:%d] %s_out;\n", + cur_num_sram, cur_num_sram + num_sram - 1, mem_model->prefix); + fprintf(fp, "wire [%d:%d] %s_outb;\n", + cur_num_sram, cur_num_sram + num_sram - 1, mem_model->prefix); + */ + + num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1); + cur_num_sram = get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info); + + /* Call LUT subckt*/ + fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + fprintf(fp, "\n"); + /* if we have to add global ports when dumping submodules of LUTs + * otherwise, the port map here does not match that of submodules + * Only dump the global ports belonging to a spice_model + * DISABLE recursive here ! + */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE)) { + fprintf(fp, ",\n"); + } + /* Connect inputs*/ + /* Connect outputs*/ + fprintf(fp, "//----- Input and output ports -----\n"); + dump_verilog_pb_type_bus_ports(fp, port_prefix, 0, cur_pb_type, FALSE, TRUE); + fprintf(fp, "//----- SRAM ports -----\n"); + /* Connect srams: TODO: to find the SRAM model used by this Verilog model */ + cur_num_sram = get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info); + /* TODO: switch depending on the type of configuration circuit */ + switch (sram_verilog_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + break; + case SPICE_SRAM_SCAN_CHAIN: + dump_verilog_sram_one_port(fp, sram_verilog_orgz_info, + cur_num_sram, cur_num_sram + num_sram - 1, + 1, VERILOG_PORT_CONKT); + fprintf(fp, ", "); + dump_verilog_sram_one_outport(fp, sram_verilog_orgz_info, + cur_num_sram, cur_num_sram + num_sram - 1, + 1, VERILOG_PORT_CONKT); + break; + case SPICE_SRAM_MEMORY_BANK: + dump_verilog_sram_one_outport(fp, sram_verilog_orgz_info, + cur_num_sram, cur_num_sram + num_sram - 1, + 0, VERILOG_PORT_CONKT); + fprintf(fp, ", "); + dump_verilog_sram_one_outport(fp, sram_verilog_orgz_info, + cur_num_sram, cur_num_sram + num_sram - 1, + 1, VERILOG_PORT_CONKT); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid SRAM organization type!\n", + __FILE__, __LINE__); + exit(1); + } + /* vdd should be connected to special global wire gvdd_lut and gnd, + * Every LUT has a special VDD for statistics + */ + fprintf(fp, ");\n"); + + /* Print the encoding in SPICE netlist for debugging */ + if (NULL != mapped_logical_block) { + fprintf(fp, "//----- Truth Table for LUT node (%s). -----\n", + mapped_logical_block->name); + } + fprintf(fp, "//----- Truth Table for LUT[%d], size=%d. -----\n", + verilog_model->cnt, lut_size); + for (i = 0; i < truth_table_length; i++) { + fprintf(fp,"// %s \n", truth_table[i]); + } + + fprintf(fp, "//----- SRAM bits for LUT[%d], size=%d, num_sram=%d. -----\n", + verilog_model->cnt, lut_size, num_sram); + fprintf(fp, "//-----"); + fprint_commented_sram_bits(fp, num_sram, sram_bits); + fprintf(fp, "-----\n"); + + /* Decode the SRAM bits to BL/WL bits. */ + switch (sram_verilog_orgz_type) { + case SPICE_SRAM_MEMORY_BANK: + cur_num_sram = get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info); + for (i = 0; i < num_sram; i++) { + /* TODO: should be more structural in coding !!! */ + /* Decode the SRAM bits to BL/WL bits. + * first half part is BL, the other half part is WL + */ + decode_and_add_verilog_sram_membank_conf_bit_to_llist(sram_verilog_orgz_info, cur_num_sram + i, + num_bl_per_sram, num_wl_per_sram, + sram_bits[i]); + } + /* NUM_SRAM is set to be consistent with number of BL/WLs + * TODO: NUM_SRAM should be the as they are. + * Should use another variable i.e., num_bl + */ + break; + case SPICE_SRAM_STANDALONE: + case SPICE_SRAM_SCAN_CHAIN: + /* Store the configuraion bit to linked-list */ + add_mux_conf_bits_to_llist(0, sram_verilog_orgz_info, + num_sram, sram_bits, + verilog_model); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid SRAM organization type!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Call SRAM subckts only + * when Configuration organization style is memory bank */ + /* No. of SRAMs is different from the number of configuration lines. + * Especially when SRAMs/RRAMs are configured with BL/WLs + */ + num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1); + for (i = 0; i < num_sram; i++) { + /* Dump the configuration port bus */ + /*TODO: to be more smart!!! num_reserved_conf_bits and num_conf_bits/num_sram should be determined by each mem_bit */ + cur_num_sram = get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info); + dump_verilog_mem_config_bus(fp, mem_model, sram_verilog_orgz_info, + cur_num_sram, num_reserved_conf_bits, num_conf_bits/num_sram); + /* This function should be called in the very end, + * because we update the counter of mem_model after each sram submodule is dumped !!! + */ + dump_verilog_sram_submodule(fp, sram_verilog_orgz_info, + mem_model); /* use the mem_model in sram_verilog_orgz_info */ + } + + /* End of subckt*/ + fprintf(fp, "endmodule\n"); + + /* Comment lines */ + fprintf(fp, "//----- END LUT Verilog module: %s%s_%d_ -----\n\n", + formatted_subckt_prefix, cur_pb_type->name, index); + + /* Update counter */ + verilog_model->cnt++; + + /*Free*/ + my_free(formatted_subckt_prefix); + my_free(input_ports); + my_free(output_ports); + my_free(sram_ports); + my_free(sram_bits); + my_free(port_prefix); + + return; +} diff --git a/vpr7_rram/vpr/SRC/syn_verilog/verilog_lut.h b/vpr7_rram/vpr/SRC/syn_verilog/verilog_lut.h new file mode 100644 index 000000000..70e755c5c --- /dev/null +++ b/vpr7_rram/vpr/SRC/syn_verilog/verilog_lut.h @@ -0,0 +1,7 @@ + +void dump_verilog_pb_primitive_lut(FILE* fp, + char* subckt_prefix, + t_logical_block* mapped_logical_block, + t_pb_graph_node* cur_pb_graph_node, + int index, + t_spice_model* spice_model); diff --git a/vpr7_rram/vpr/SRC/syn_verilog/verilog_pbtypes.c b/vpr7_rram/vpr/SRC/syn_verilog/verilog_pbtypes.c new file mode 100644 index 000000000..81a36e809 --- /dev/null +++ b/vpr7_rram/vpr/SRC/syn_verilog/verilog_pbtypes.c @@ -0,0 +1,3595 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph.h" +#include "vpr_utils.h" + +/* Include SPICE support headers*/ +#include "linkedlist.h" +#include "fpga_spice_utils.h" +#include "spice_mux.h" +#include "fpga_spice_globals.h" + +/* Include Synthesizable Verilog headers */ +#include "verilog_global.h" +#include "verilog_utils.h" +#include "verilog_lut.h" +#include "verilog_primitives.h" +#include "verilog_pbtypes.h" + +/***** Subroutines *****/ + +/* Find spice_model_name definition in pb_types + * Try to match the name with defined spice_models + */ +void match_pb_types_verilog_model_rec(t_pb_type* cur_pb_type, + int num_verilog_model, + t_spice_model* verilog_models) { + int imode, ipb, jinterc; + + if (NULL == cur_pb_type) { + vpr_printf(TIO_MESSAGE_WARNING,"(File:%s,LINE[%d])cur_pb_type is null pointor!\n",__FILE__,__LINE__); + return; + } + + /* If there is a spice_model_name, this is a leaf node!*/ + if (NULL != cur_pb_type->spice_model_name) { + /* What annoys me is VPR create a sub pb_type for each lut which suppose to be a leaf node + * This may bring software convience but ruins SPICE modeling + */ + /* Let's find a matched verilog model!*/ + printf("INFO: matching cur_pb_type=%s with spice_model_name=%s...\n",cur_pb_type->name, cur_pb_type->spice_model_name); + assert(NULL == cur_pb_type->spice_model); + cur_pb_type->spice_model = find_name_matched_spice_model(cur_pb_type->spice_model_name, num_verilog_model, verilog_models); + if (NULL == cur_pb_type->spice_model) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d]) Fail to find a defined SPICE model called %s, in pb_type(%s)!\n",__FILE__, __LINE__, cur_pb_type->spice_model_name, cur_pb_type->name); + exit(1); + } + return; + } + /* Traversal the hierarchy*/ + for (imode = 0; imode < cur_pb_type->num_modes; imode++) { + /* Task 1: Find the interconnections and match the spice_model */ + for (jinterc = 0; jinterc < cur_pb_type->modes[imode].num_interconnect; jinterc++) { + assert(NULL == cur_pb_type->modes[imode].interconnect[jinterc].spice_model); + /* If the spice_model_name is not defined, we use the default*/ + if (NULL == cur_pb_type->modes[imode].interconnect[jinterc].spice_model_name) { + switch (cur_pb_type->modes[imode].interconnect[jinterc].type) { + case DIRECT_INTERC: + cur_pb_type->modes[imode].interconnect[jinterc].spice_model = + get_default_spice_model(SPICE_MODEL_WIRE,num_verilog_model,verilog_models); + break; + case COMPLETE_INTERC: + /* Special for Completer Interconnection: + * 1. The input number is 1, this infers a direct interconnection. + * 2. The input number is larger than 1, this infers multplexers + * according to interconnect[j].num_mux identify the number of input at this level + */ + if (0 == cur_pb_type->modes[imode].interconnect[jinterc].num_mux) { + cur_pb_type->modes[imode].interconnect[jinterc].spice_model = + get_default_spice_model(SPICE_MODEL_WIRE,num_verilog_model,verilog_models); + } else { + cur_pb_type->modes[imode].interconnect[jinterc].spice_model = + get_default_spice_model(SPICE_MODEL_MUX,num_verilog_model,verilog_models); + } + break; + case MUX_INTERC: + cur_pb_type->modes[imode].interconnect[jinterc].spice_model = + get_default_spice_model(SPICE_MODEL_MUX,num_verilog_model,verilog_models); + break; + default: + break; + } + } else { + cur_pb_type->modes[imode].interconnect[jinterc].spice_model = + find_name_matched_spice_model(cur_pb_type->modes[imode].interconnect[jinterc].spice_model_name, num_verilog_model, verilog_models); + if (NULL == cur_pb_type->modes[imode].interconnect[jinterc].spice_model) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d]) Fail to find a defined SPICE model called %s, in pb_type(%s)!\n",__FILE__, __LINE__, cur_pb_type->modes[imode].interconnect[jinterc].spice_model_name, cur_pb_type->name); + exit(1); + } + switch (cur_pb_type->modes[imode].interconnect[jinterc].type) { + case DIRECT_INTERC: + if (SPICE_MODEL_WIRE != cur_pb_type->modes[imode].interconnect[jinterc].spice_model->type) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d]) Invalid type of matched SPICE model called %s, in pb_type(%s)! Sould be wire!\n",__FILE__, __LINE__, cur_pb_type->modes[imode].interconnect[jinterc].spice_model_name, cur_pb_type->name); + exit(1); + } + break; + case COMPLETE_INTERC: + if (0 == cur_pb_type->modes[imode].interconnect[jinterc].num_mux) { + if (SPICE_MODEL_WIRE != cur_pb_type->modes[imode].interconnect[jinterc].spice_model->type) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d]) Invalid type of matched SPICE model called %s, in pb_type(%s)! Sould be wire!\n",__FILE__, __LINE__, cur_pb_type->modes[imode].interconnect[jinterc].spice_model_name, cur_pb_type->name); + exit(1); + } + } else { + if (SPICE_MODEL_MUX != cur_pb_type->modes[imode].interconnect[jinterc].spice_model->type) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d]) Invalid type of matched SPICE model called %s, in pb_type(%s)! Sould be MUX!\n",__FILE__, __LINE__, cur_pb_type->modes[imode].interconnect[jinterc].spice_model_name, cur_pb_type->name); + exit(1); + } + } + break; + case MUX_INTERC: + if (SPICE_MODEL_MUX != cur_pb_type->modes[imode].interconnect[jinterc].spice_model->type) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d]) Invalid type of matched SPICE model called %s, in pb_type(%s)! Sould be MUX!\n",__FILE__, __LINE__, cur_pb_type->modes[imode].interconnect[jinterc].spice_model_name, cur_pb_type->name); + exit(1); + } + break; + default: + break; + } + } + } + /* Task 2: Find the child pb_type, do matching recursively */ + //if (1 == cur_pb_type->modes[imode].define_spice_model) { + for (ipb = 0; ipb < cur_pb_type->modes[imode].num_pb_type_children; ipb++) { + match_pb_types_verilog_model_rec(&cur_pb_type->modes[imode].pb_type_children[ipb], + num_verilog_model, + verilog_models); + } + //} + } + return; +} + +int verilog_find_path_id_between_pb_rr_nodes(t_rr_node* local_rr_graph, + int src_node, + int des_node) { + int path_id = -1; + int prev_edge = -1; + int path_count = 0; + int iedge; + t_interconnect* cur_interc = NULL; + + /* Check */ + assert(NULL != local_rr_graph); + assert((0 == src_node)||(0 < src_node)); + assert((0 == des_node)||(0 < des_node)); + + prev_edge = local_rr_graph[des_node].prev_edge; + check_pb_graph_edge(*(local_rr_graph[src_node].pb_graph_pin->output_edges[prev_edge])); + assert(local_rr_graph[src_node].pb_graph_pin->output_edges[prev_edge]->output_pins[0] == local_rr_graph[des_node].pb_graph_pin); + + cur_interc = local_rr_graph[src_node].pb_graph_pin->output_edges[prev_edge]->interconnect; + /* Search des_node input edges */ + for (iedge = 0; iedge < local_rr_graph[des_node].pb_graph_pin->num_input_edges; iedge++) { + if (local_rr_graph[des_node].pb_graph_pin->input_edges[iedge]->input_pins[0] + == local_rr_graph[src_node].pb_graph_pin) { + /* Strict check */ + assert(local_rr_graph[src_node].pb_graph_pin->output_edges[prev_edge] + == local_rr_graph[des_node].pb_graph_pin->input_edges[iedge]); + path_id = path_count; + break; + } + if (cur_interc == local_rr_graph[des_node].pb_graph_pin->input_edges[iedge]->interconnect) { + path_count++; + } + } + + return path_id; +} + +/* Find the interconnection type of pb_graph_pin edges*/ +enum e_interconnect verilog_find_pb_graph_pin_in_edges_interc_type(t_pb_graph_pin pb_graph_pin) { + enum e_interconnect interc_type; + int def_interc_type = 0; + int iedge; + + for (iedge = 0; iedge < pb_graph_pin.num_input_edges; iedge++) { + /* Make sure all edges are legal: 1 input_pin, 1 output_pin*/ + check_pb_graph_edge(*(pb_graph_pin.input_edges[iedge])); + /* Make sure all the edges interconnect type is the same*/ + if (0 == def_interc_type) { + interc_type = pb_graph_pin.input_edges[iedge]->interconnect->type; + } else if (interc_type != pb_graph_pin.input_edges[iedge]->interconnect->type) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d])Interconnection type are not same for port(%s),pin(%d).\n", + __FILE__, __LINE__, pb_graph_pin.port->name,pb_graph_pin.pin_number); + exit(1); + } + } + + return interc_type; +} + + +/* Find the interconnection type of pb_graph_pin edges*/ +t_spice_model* find_pb_graph_pin_in_edges_interc_verilog_model(t_pb_graph_pin pb_graph_pin) { + t_spice_model* interc_verilog_model; + int def_interc_model = 0; + int iedge; + + for (iedge = 0; iedge < pb_graph_pin.num_input_edges; iedge++) { + /* Make sure all edges are legal: 1 input_pin, 1 output_pin*/ + check_pb_graph_edge(*(pb_graph_pin.input_edges[iedge])); + /* Make sure all the edges interconnect type is the same*/ + if (0 == def_interc_model) { + interc_verilog_model= pb_graph_pin.input_edges[iedge]->interconnect->spice_model; + } else if (interc_verilog_model != pb_graph_pin.input_edges[iedge]->interconnect->spice_model) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d])Interconnection spice_model are not same for port(%s),pin(%d).\n", + __FILE__, __LINE__, pb_graph_pin.port->name,pb_graph_pin.pin_number); + exit(1); + } + } + + return interc_verilog_model; +} + +/* Recursively do statistics for the + * multiplexer verilog models inside pb_types + */ +void stats_mux_verilog_model_pb_type_rec(t_llist** muxes_head, + t_pb_type* cur_pb_type) { + + int imode, ichild, jinterc; + t_spice_model* interc_verilog_model = NULL; + + if (NULL == cur_pb_type) { + vpr_printf(TIO_MESSAGE_WARNING,"(File:%s,LINE[%d])cur_pb_type is null pointor!\n",__FILE__,__LINE__); + return; + } + + /* If there is spice_model_name, this is a leaf node!*/ + if (NULL != cur_pb_type->spice_model_name) { + /* What annoys me is VPR create a sub pb_type for each lut which suppose to be a leaf node + * This may bring software convience but ruins SPICE modeling + */ + assert(NULL != cur_pb_type->spice_model); + return; + } + /* Traversal the hierarchy*/ + for (imode = 0; imode < cur_pb_type->num_modes; imode++) { + /* Then we have to statisitic the interconnections*/ + for (jinterc = 0; jinterc < cur_pb_type->modes[imode].num_interconnect; jinterc++) { + /* Check the num_mux and fan_in*/ + assert((0 == cur_pb_type->modes[imode].interconnect[jinterc].num_mux) + ||(0 < cur_pb_type->modes[imode].interconnect[jinterc].num_mux)); + if (0 == cur_pb_type->modes[imode].interconnect[jinterc].num_mux) { + continue; + } + interc_verilog_model = cur_pb_type->modes[imode].interconnect[jinterc].spice_model; + assert(NULL != interc_verilog_model); + check_and_add_mux_to_linked_list(muxes_head, + cur_pb_type->modes[imode].interconnect[jinterc].fan_in, + interc_verilog_model); + } + for (ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ichild++) { + stats_mux_verilog_model_pb_type_rec(muxes_head, + &cur_pb_type->modes[imode].pb_type_children[ichild]); + } + } + return; +} + +/* Statistics the MUX SPICE MODEL with the help of pb_graph + * Not the most efficient function to finish the job + * Abandon it. But remains a good framework that could be re-used in connecting + * verilog components together + */ +void stats_mux_verilog_model_pb_node_rec(t_llist** muxes_head, + t_pb_graph_node* cur_pb_node) { + int imode, ipb, ichild, iport, ipin; + t_pb_type* cur_pb_type = cur_pb_node->pb_type; + t_spice_model* interc_verilog_model = NULL; + enum e_interconnect pin_interc_type; + + if (NULL == cur_pb_node) { + vpr_printf(TIO_MESSAGE_WARNING,"(File:%s,LINE[%d])cur_pb_node is null pointor!\n",__FILE__,__LINE__); + return; + } + + if (NULL == cur_pb_type) { + vpr_printf(TIO_MESSAGE_WARNING,"(File:%s,LINE[%d])cur_pb_type is null pointor!\n",__FILE__,__LINE__); + return; + } + + /* If there is 0 mode, this is a leaf node!*/ + if (NULL != cur_pb_type->blif_model) { + assert(0 == cur_pb_type->num_modes); + assert(NULL == cur_pb_type->modes); + /* Ensure there is blif_model, and spice_model*/ + assert(NULL != cur_pb_type->model); + assert(NULL != cur_pb_type->spice_model_name); + assert(NULL != cur_pb_type->spice_model); + return; + } + /* Traversal the hierarchy*/ + for (imode = 0; imode < cur_pb_type->num_modes; imode++) { + /* Then we have to statisitic the interconnections*/ + /* See the input ports*/ + for (iport = 0; iport < cur_pb_node->num_input_ports; iport++) { + for (ipin = 0; ipin < cur_pb_node->num_input_pins[iport]; ipin++) { + /* Ensure this is an input port */ + assert(IN_PORT == cur_pb_node->input_pins[iport][ipin].port->type); + /* See the edges, if the interconnetion type infer a MUX, we go next step*/ + pin_interc_type = verilog_find_pb_graph_pin_in_edges_interc_type(cur_pb_node->input_pins[iport][ipin]); + if ((COMPLETE_INTERC != pin_interc_type)&&(MUX_INTERC != pin_interc_type)) { + continue; + } + /* We shoule check the size of inputs, in some case of complete, the input_edge is one...*/ + if ((COMPLETE_INTERC == pin_interc_type)&&(1 == cur_pb_node->input_pins[iport][ipin].num_input_edges)) { + continue; + } + /* Note: i do care the input_edges only! They may infer multiplexers*/ + interc_verilog_model = find_pb_graph_pin_in_edges_interc_verilog_model(cur_pb_node->input_pins[iport][ipin]); + check_and_add_mux_to_linked_list(muxes_head, + cur_pb_node->input_pins[iport][ipin].num_input_edges, + interc_verilog_model); + } + } + /* See the output ports*/ + for (iport = 0; iport < cur_pb_node->num_output_ports; iport++) { + for (ipin = 0; ipin < cur_pb_node->num_output_pins[iport]; ipin++) { + /* Ensure this is an input port */ + assert(OUT_PORT == cur_pb_node->output_pins[iport][ipin].port->type); + /* See the edges, if the interconnetion type infer a MUX, we go next step*/ + pin_interc_type = verilog_find_pb_graph_pin_in_edges_interc_type(cur_pb_node->output_pins[iport][ipin]); + if ((COMPLETE_INTERC != pin_interc_type)&&(MUX_INTERC != pin_interc_type)) { + continue; + } + /* We shoule check the size of inputs, in some case of complete, the input_edge is one...*/ + if ((COMPLETE_INTERC == pin_interc_type)&&(1 == cur_pb_node->output_pins[iport][ipin].num_input_edges)) { + continue; + } + /* Note: i do care the input_edges only! They may infer multiplexers*/ + interc_verilog_model = find_pb_graph_pin_in_edges_interc_verilog_model(cur_pb_node->output_pins[iport][ipin]); + check_and_add_mux_to_linked_list(muxes_head, + cur_pb_node->output_pins[iport][ipin].num_input_edges, + interc_verilog_model); + } + } + /* See the clock ports*/ + for (iport = 0; iport < cur_pb_node->num_clock_ports; iport++) { + for (ipin = 0; ipin < cur_pb_node->num_clock_pins[iport]; ipin++) { + /* Ensure this is an input port */ + assert(IN_PORT == cur_pb_node->clock_pins[iport][ipin].port->type); + /* See the edges, if the interconnetion type infer a MUX, we go next step*/ + pin_interc_type = verilog_find_pb_graph_pin_in_edges_interc_type(cur_pb_node->clock_pins[iport][ipin]); + if ((COMPLETE_INTERC != pin_interc_type)&&(MUX_INTERC != pin_interc_type)) { + continue; + } + /* We shoule check the size of inputs, in some case of complete, the input_edge is one...*/ + if ((COMPLETE_INTERC == pin_interc_type)&&(1 == cur_pb_node->clock_pins[iport][ipin].num_input_edges)) { + continue; + } + /* Note: i do care the input_edges only! They may infer multiplexers*/ + interc_verilog_model = find_pb_graph_pin_in_edges_interc_verilog_model(cur_pb_node->clock_pins[iport][ipin]); + check_and_add_mux_to_linked_list(muxes_head, + cur_pb_node->clock_pins[iport][ipin].num_input_edges, + interc_verilog_model); + } + } + for (ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ichild++) { + /* num_pb is the number of such pb_type in a mode*/ + for (ipb = 0; ipb < cur_pb_type->modes[imode].pb_type_children[ichild].num_pb; ipb++) { + /* child_pb_grpah_nodes: [0..num_modes-1][0..num_pb_type_in_mode-1][0..num_pb_type-1]*/ + stats_mux_verilog_model_pb_node_rec(muxes_head, + &cur_pb_node->child_pb_graph_nodes[imode][ichild][ipb]); + } + } + } + return; +} + +/* Print ports of pb_types, + * SRAM ports are not printed here!!! + * Important feature: manage the comma between ports + * Make sure there is no redundant comma and there is no comma after the last element if specified + */ +void dump_verilog_pb_type_bus_ports(FILE* fp, + char* port_prefix, + int use_global_clock, + t_pb_type* cur_pb_type, + boolean dump_port_type, + boolean dump_last_comma) { + int iport; + int num_pb_type_input_port = 0; + t_port** pb_type_input_ports = NULL; + + int num_pb_type_output_port = 0; + t_port** pb_type_output_ports = NULL; + + int num_pb_type_inout_port = 0; + t_port** pb_type_inout_ports = NULL; + + int num_pb_type_clk_port = 0; + t_port** pb_type_clk_ports = NULL; + + char* formatted_port_prefix = chomp_verilog_node_prefix(port_prefix); + /* A counter to stats the number of dumped ports and pins */ + int num_dumped_port = 0; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + } + + /* INOUT ports */ + num_dumped_port = 0; + /* Find pb_type inout ports */ + pb_type_inout_ports = find_pb_type_ports_match_spice_model_port_type(cur_pb_type, SPICE_MODEL_PORT_INOUT, &num_pb_type_inout_port); + + /* Print all the inout ports */ + for (iport = 0; iport < num_pb_type_inout_port; iport++) { + if (0 < num_dumped_port) { + if (TRUE == dump_port_type) { + fprintf(fp, ",\n"); + } else { + fprintf(fp, ", "); + } + } + if (TRUE == dump_port_type) { + fprintf(fp, "inout "); + fprintf(fp, "[0:%d] %s__%s ", + pb_type_inout_ports[iport]->num_pins - 1, + formatted_port_prefix, pb_type_inout_ports[iport]->name); + } else { + fprintf(fp, "%s__%s[0:%d] ", + formatted_port_prefix, pb_type_inout_ports[iport]->name, + pb_type_inout_ports[iport]->num_pins - 1); + } + /* Update the counter */ + num_dumped_port++; + } + + /* Inputs */ + /* Find pb_type input ports */ + pb_type_input_ports = find_pb_type_ports_match_spice_model_port_type(cur_pb_type, SPICE_MODEL_PORT_INPUT, &num_pb_type_input_port); + /* Print all the input ports */ + for (iport = 0; iport < num_pb_type_input_port; iport++) { + if (0 < num_dumped_port) { + if (TRUE == dump_port_type) { + fprintf(fp, ",\n"); + } else { + fprintf(fp, ", "); + } + } + if (TRUE == dump_port_type) { + fprintf(fp, "input "); + fprintf(fp, " [0:%d] %s__%s ", + pb_type_input_ports[iport]->num_pins - 1, + formatted_port_prefix, pb_type_input_ports[iport]->name); + } else { + fprintf(fp, " %s__%s[0:%d] ", + formatted_port_prefix, pb_type_input_ports[iport]->name, + pb_type_input_ports[iport]->num_pins - 1); + } + /* Update the counter */ + num_dumped_port++; + } + /* Outputs */ + /* Find pb_type output ports */ + pb_type_output_ports = find_pb_type_ports_match_spice_model_port_type(cur_pb_type, SPICE_MODEL_PORT_OUTPUT, &num_pb_type_output_port); + + /* Print all the output ports */ + for (iport = 0; iport < num_pb_type_output_port; iport++) { + if (0 < num_dumped_port) { + if (TRUE == dump_port_type) { + fprintf(fp, ",\n"); + } else { + fprintf(fp, ", "); + } + } + if (TRUE == dump_port_type) { + fprintf(fp, "output "); + fprintf(fp, " %s__%s[0:%d]", + formatted_port_prefix, pb_type_output_ports[iport]->name, + pb_type_output_ports[iport]->num_pins - 1); + } else { + fprintf(fp, " %s__%s[0:%d]", + formatted_port_prefix, pb_type_output_ports[iport]->name, + pb_type_output_ports[iport]->num_pins - 1); + } + /* Update the counter */ + num_dumped_port++; + } + + /* Clocks */ + /* Find pb_type clock ports */ + pb_type_clk_ports = find_pb_type_ports_match_spice_model_port_type(cur_pb_type, SPICE_MODEL_PORT_CLOCK, &num_pb_type_clk_port); + /* Print all the clk ports */ + for (iport = 0; iport < num_pb_type_clk_port; iport++) { + if (0 < num_dumped_port) { + if (TRUE == dump_port_type) { + fprintf(fp, ",\n"); + } else { + fprintf(fp, ", "); + } + } + if (TRUE == dump_port_type) { + fprintf(fp, "input"); + fprintf(fp, " %s__%s[0:%d]", + formatted_port_prefix, pb_type_clk_ports[iport]->name, + pb_type_output_ports[iport]->num_pins - 1); + } else { + fprintf(fp, " %s__%s[0:%d]", + formatted_port_prefix, pb_type_clk_ports[iport]->name, + pb_type_output_ports[iport]->num_pins - 1); + } + /* Update the counter */ + num_dumped_port++; + } + + /* Dump the last comma, when the option is enabled and there is something dumped */ + if ((0 < num_dumped_port)&&(TRUE == dump_last_comma)) { + if (TRUE == dump_port_type) { + fprintf(fp, ",\n"); + } else { + fprintf(fp, ","); + } + } + + /* Free */ + free(formatted_port_prefix); + my_free(pb_type_input_ports); + my_free(pb_type_output_ports); + my_free(pb_type_inout_ports); + my_free(pb_type_clk_ports); + + return; +} + + +/* Print ports of pb_types, + * SRAM ports are not printed here!!! + * Important feature: manage the comma between ports + * Make sure there is no redundant comma and there is no comma after the last element if specified + * Check each ports, if it is defined as a global signal, we should not dump it + */ +void dump_verilog_pb_type_ports(FILE* fp, + char* port_prefix, + int use_global_clock, + t_pb_type* cur_pb_type, + boolean dump_port_type, + boolean dump_last_comma) { + int iport, ipin; + int num_pb_type_input_port = 0; + t_port** pb_type_input_ports = NULL; + + int num_pb_type_output_port = 0; + t_port** pb_type_output_ports = NULL; + + int num_pb_type_inout_port = 0; + t_port** pb_type_inout_ports = NULL; + + int num_pb_type_clk_port = 0; + t_port** pb_type_clk_ports = NULL; + + char* formatted_port_prefix = chomp_verilog_node_prefix(port_prefix); + /* A counter to stats the number of dumped ports and pins */ + int num_dumped_port = 0; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + } + + /* INOUT ports */ + num_dumped_port = 0; + + /* Find pb_type inout ports */ + pb_type_inout_ports = find_pb_type_ports_match_spice_model_port_type(cur_pb_type, SPICE_MODEL_PORT_INOUT, &num_pb_type_inout_port); + + /* Print all the inout ports */ + for (iport = 0; iport < num_pb_type_inout_port; iport++) { + /* only search mapped ports for primitive node */ + if (NULL != cur_pb_type->spice_model) { + /* We need to bypass global ports */ + assert(NULL != pb_type_inout_ports[iport]->spice_model_port); + if (TRUE == pb_type_inout_ports[iport]->spice_model_port->is_global) { + continue; + } + } + /* Dump non-global ports */ + for (ipin = 0; ipin < pb_type_inout_ports[iport]->num_pins; ipin++) { + if (0 < num_dumped_port) { + if (TRUE == dump_port_type) { + fprintf(fp, ",\n"); + } else { + fprintf(fp, ", "); + } + } + if (TRUE == dump_port_type) { + fprintf(fp, "inout wire"); + } + fprintf(fp, "%s__%s_%d_ ", formatted_port_prefix, pb_type_inout_ports[iport]->name, ipin); + /* Update the counter */ + num_dumped_port++; + } + } + + /* Inputs */ + /* Find pb_type input ports */ + pb_type_input_ports = find_pb_type_ports_match_spice_model_port_type(cur_pb_type, SPICE_MODEL_PORT_INPUT, &num_pb_type_input_port); + /* Print all the input ports */ + for (iport = 0; iport < num_pb_type_input_port; iport++) { + /* only search mapped ports for primitive node */ + if (NULL != cur_pb_type->spice_model) { + /* We need to bypass global ports */ + assert(NULL != pb_type_input_ports[iport]->spice_model_port); + if (TRUE == pb_type_input_ports[iport]->spice_model_port->is_global) { + continue; + } + } + /* Dump non-global ports */ + for (ipin = 0; ipin < pb_type_input_ports[iport]->num_pins; ipin++) { + if (0 < num_dumped_port) { + if (TRUE == dump_port_type) { + fprintf(fp, ",\n"); + } else { + fprintf(fp, ", "); + } + } + if (TRUE == dump_port_type) { + fprintf(fp, "input wire"); + } + fprintf(fp, " %s__%s_%d_", formatted_port_prefix, pb_type_input_ports[iport]->name, ipin); + /* Update the counter */ + num_dumped_port++; + } + } + /* Outputs */ + /* Find pb_type output ports */ + pb_type_output_ports = find_pb_type_ports_match_spice_model_port_type(cur_pb_type, SPICE_MODEL_PORT_OUTPUT, &num_pb_type_output_port); + /* Print all the output ports */ + for (iport = 0; iport < num_pb_type_output_port; iport++) { + /* only search mapped ports for primitive node */ + if (NULL != cur_pb_type->spice_model) { + /* We need to bypass global ports */ + assert(NULL != pb_type_output_ports[iport]->spice_model_port); + if (TRUE == pb_type_output_ports[iport]->spice_model_port->is_global) { + continue; + } + } + /* Dump non-global ports */ + for (ipin = 0; ipin < pb_type_output_ports[iport]->num_pins; ipin++) { + if (0 < num_dumped_port) { + if (TRUE == dump_port_type) { + fprintf(fp, ",\n"); + } else { + fprintf(fp, ", "); + } + } + if (TRUE == dump_port_type) { + fprintf(fp, "output wire"); + } + fprintf(fp, " %s__%s_%d_", formatted_port_prefix, pb_type_output_ports[iport]->name, ipin); + /* Update the counter */ + num_dumped_port++; + } + } + + /* Clocks */ + /* Find pb_type clock ports */ + /* Only dump clock ports when global clock is not specified */ + pb_type_clk_ports = find_pb_type_ports_match_spice_model_port_type(cur_pb_type, SPICE_MODEL_PORT_CLOCK, &num_pb_type_clk_port); + + /* Print all the clk ports */ + for (iport = 0; iport < num_pb_type_clk_port; iport++) { + /* only search mapped ports for primitive node */ + if (NULL != cur_pb_type->spice_model) { + /* We need to bypass global ports */ + assert(NULL != pb_type_clk_ports[iport]->spice_model_port); + if (TRUE == pb_type_clk_ports[iport]->spice_model_port->is_global) { + continue; + } + } + /* Dump non-global ports */ + for (ipin = 0; ipin < pb_type_clk_ports[iport]->num_pins; ipin++) { + if (0 < num_dumped_port) { + if (TRUE == dump_port_type) { + fprintf(fp, ",\n"); + } else { + fprintf(fp, ", "); + } + } + if (TRUE == dump_port_type) { + fprintf(fp, "input wire"); + } + fprintf(fp, " %s__%s_%d_", formatted_port_prefix, pb_type_clk_ports[iport]->name, ipin); + /* Update the counter */ + num_dumped_port++; + } + } + + /* Dump the last comma, when the option is enabled and there is something dumped */ + if ((0 < num_dumped_port)&&(TRUE == dump_last_comma)) { + if (TRUE == dump_port_type) { + fprintf(fp, ",\n"); + } else { + fprintf(fp, ","); + } + } + + /* Free */ + free(formatted_port_prefix); + my_free(pb_type_input_ports); + my_free(pb_type_output_ports); + my_free(pb_type_inout_ports); + my_free(pb_type_clk_ports); + + return; +} + +/* This is a truncated version of generate_verilog_src_des_pb_graph_pin_prefix + * Only used to generate prefix for those dangling pin in PB Types + */ +void dump_verilog_dangling_des_pb_graph_pin_interc(FILE* fp, + t_pb_graph_pin* des_pb_graph_pin, + t_mode* cur_mode, + enum e_pin2pin_interc_type pin2pin_interc_type, + char* parent_pin_prefix) { + t_pb_graph_node* des_pb_graph_node = NULL; + t_pb_type* des_pb_type = NULL; + int des_pb_type_index = -1; + int fan_in = 0; + t_interconnect* cur_interc = NULL; + char* des_pin_prefix = NULL; + + /* char* formatted_parent_pin_prefix = format_verilog_node_prefix(parent_pin_prefix);*/ /* Complete a "_" at the end if needed*/ + //char* chomped_parent_pin_prefix = chomp_verilog_node_prefix(parent_pin_prefix); /* Remove a "_" at the end if needed*/ + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check the pb_graph_nodes*/ + if (NULL == des_pb_graph_pin) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid pointer: des_pb_graph_pin.\n", + __FILE__, __LINE__); + exit(1); + } + + verilog_find_interc_fan_in_des_pb_graph_pin(des_pb_graph_pin, cur_mode, &cur_interc, &fan_in); + if ((NULL != cur_interc)&&(0 != fan_in)) { + return; + /* + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Cur_interc not NULL & fan_in not zero!\n", + __FILE__, __LINE__); + exit(1); + */ + } + + /* Initialize */ + des_pb_graph_node = des_pb_graph_pin->parent_node; + des_pb_type = des_pb_graph_node->pb_type; + des_pb_type_index = des_pb_graph_node->placement_index; + + /* generate the pin prefix for src_pb_graph_node and des_pb_graph_node */ + switch (pin2pin_interc_type) { + case INPUT2INPUT_INTERC: + /* src_pb_graph_node.input_pins -----------------> des_pb_graph_node.input_pins + * des_pb_graph_node is a child of src_pb_graph_node + * parent_pin_prefix is the prefix from parent pb_graph_node, in this case, src_pb_graph_node + * src_pin_prefix: we need to handle the feedbacks, they comes from the same-level pb_graph_node + * src_pin_prefix = + * OR + * src_pin_prefix = _[] + * des_pin_prefix = mode[]_[]_ + */ + /* + des_pin_prefix = (char*)my_malloc(sizeof(char)* + (strlen(formatted_parent_pin_prefix) + 5 + strlen(cur_mode->name) + + 2 + strlen(des_pb_type->name) + 1 + strlen(my_itoa(des_pb_type_index)) + 1 + 1)); + sprintf(des_pin_prefix, "%smode[%s]_%s[%d]", + formatted_parent_pin_prefix, cur_mode->name, des_pb_type->name, des_pb_type_index); + */ + /*Simplify the prefix, make the SPICE netlist readable*/ + des_pin_prefix = (char*)my_malloc(sizeof(char)* + (strlen(des_pb_type->name) + 1 + strlen(my_itoa(des_pb_type_index)) + 1 + 1)); + sprintf(des_pin_prefix, "%s_%d_", + des_pb_type->name, des_pb_type_index); + break; + case OUTPUT2OUTPUT_INTERC: + /* src_pb_graph_node.output_pins -----------------> des_pb_graph_node.output_pins + * src_pb_graph_node is a child of des_pb_graph_node + * parent_pin_prefix is the prefix from parent pb_graph_node, in this case, des_pb_graph_node + * src_pin_prefix = mode[]_[]_ + * des_pin_prefix = + */ + /* + des_pin_prefix = (char*)my_malloc(sizeof(char)* + (strlen(formatted_parent_pin_prefix) + 5 + strlen(cur_mode->name) + + 2 + strlen(des_pb_type->name) + 1 + strlen(my_itoa(des_pb_type_index)) + 1 + 1)); + sprintf(des_pin_prefix, "%smode[%s]_%s[%d]", + formatted_parent_pin_prefix, cur_mode->name, des_pb_type->name, des_pb_type_index); + */ + if (des_pb_type == cur_mode->parent_pb_type) { /* Interconnection from parent pb_type*/ + des_pin_prefix = (char*)my_malloc(sizeof(char)* + (5 + strlen(cur_mode->name) + 2 )); + sprintf(des_pin_prefix, "mode_%s_", cur_mode->name); + } else { + des_pin_prefix = (char*)my_malloc(sizeof(char)* + (strlen(des_pb_type->name) + 1 + strlen(my_itoa(des_pb_type_index)) + 1 + 1)); + sprintf(des_pin_prefix, "%s_%d_", + des_pb_type->name, des_pb_type_index); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s [LINE%d])Invalid pin to pin interconnection type!\n", + __FILE__, __LINE__); + exit(1); + } + + my_free(des_pin_prefix); + + return; +} + +void generate_verilog_src_des_pb_graph_pin_prefix(t_pb_graph_node* src_pb_graph_node, + t_pb_graph_node* des_pb_graph_node, + enum e_pin2pin_interc_type pin2pin_interc_type, + t_interconnect* pin2pin_interc, + char* parent_pin_prefix, + char** src_pin_prefix, + char** des_pin_prefix) { + t_pb_type* src_pb_type = NULL; + int src_pb_type_index = -1; + + t_pb_type* des_pb_type = NULL; + int des_pb_type_index = -1; + + /* Check the pb_graph_nodes*/ + if (NULL == src_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid pointer: src_pb_graph_node.\n", + __FILE__, __LINE__); + exit(1); + } + if (NULL == des_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid pointer: des_pb_graph_node.\n", + __FILE__, __LINE__); + exit(1); + } + if (NULL == pin2pin_interc) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid pointer: pin2pin_interc.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Initialize */ + src_pb_type = src_pb_graph_node->pb_type; + src_pb_type_index = src_pb_graph_node->placement_index; + des_pb_type = des_pb_graph_node->pb_type; + des_pb_type_index = des_pb_graph_node->placement_index; + + assert(NULL == (*src_pin_prefix)); + assert(NULL == (*des_pin_prefix)); + /* generate the pin prefix for src_pb_graph_node and des_pb_graph_node */ + switch (pin2pin_interc_type) { + case INPUT2INPUT_INTERC: + /* src_pb_graph_node.input_pins -----------------> des_pb_graph_node.input_pins + * des_pb_graph_node is a child of src_pb_graph_node + * parent_pin_prefix is the prefix from parent pb_graph_node, in this case, src_pb_graph_node + * src_pin_prefix: we need to handle the feedbacks, they comes from the same-level pb_graph_node + * src_pin_prefix = + * OR + * src_pin_prefix = _[] + * des_pin_prefix = mode[]_[]_ + */ + if (src_pb_type == des_pb_type->parent_mode->parent_pb_type) { /* Interconnection from parent pb_type*/ + /* + (*src_pin_prefix) = my_strdup(chomped_parent_pin_prefix); + */ + /*Simplify the prefix, make the SPICE netlist readable*/ + (*src_pin_prefix) = (char*)my_malloc(sizeof(char)* + (5 + strlen(des_pb_type->parent_mode->name) + 2)); + sprintf((*src_pin_prefix), "mode_%s_", des_pb_type->parent_mode->name); + } else { + /* + (*src_pin_prefix) = (char*)my_malloc(sizeof(char)* + (strlen(formatted_parent_pin_prefix) + 5 + strlen(pin2pin_interc_parent_mode->name) + + 2 + strlen(src_pb_type->name) + 1 + strlen(my_itoa(src_pb_type_index)) + 1 + 1)); + sprintf((*src_pin_prefix), "%smode[%s]_%s[%d]", + formatted_parent_pin_prefix, pin2pin_interc_parent_mode->name, src_pb_type->name, src_pb_type_index); + */ + /*Simplify the prefix, make the SPICE netlist readable*/ + (*src_pin_prefix) = (char*)my_malloc(sizeof(char)* + (strlen(src_pb_type->name) + 1 + strlen(my_itoa(src_pb_type_index)) + 1 + 1)); + sprintf((*src_pin_prefix), "%s_%d_", + src_pb_type->name, src_pb_type_index); + } + /* + (*des_pin_prefix) = (char*)my_malloc(sizeof(char)* + (strlen(formatted_parent_pin_prefix) + 5 + strlen(pin2pin_interc_parent_mode->name) + + 2 + strlen(des_pb_type->name) + 1 + strlen(my_itoa(des_pb_type_index)) + 1 + 1)); + sprintf((*des_pin_prefix), "%smode[%s]_%s[%d]", + formatted_parent_pin_prefix, pin2pin_interc_parent_mode->name, des_pb_type->name, des_pb_type_index); + */ + /*Simplify the prefix, make the SPICE netlist readable*/ + (*des_pin_prefix) = (char*)my_malloc(sizeof(char)* + (strlen(des_pb_type->name) + 1 + strlen(my_itoa(des_pb_type_index)) + 1 + 1)); + sprintf((*des_pin_prefix), "%s_%d_", + des_pb_type->name, des_pb_type_index); + break; + case OUTPUT2OUTPUT_INTERC: + /* src_pb_graph_node.output_pins -----------------> des_pb_graph_node.output_pins + * src_pb_graph_node is a child of des_pb_graph_node + * parent_pin_prefix is the prefix from parent pb_graph_node, in this case, des_pb_graph_node + * src_pin_prefix = mode[]_[]_ + * des_pin_prefix = + */ + /* + (*src_pin_prefix) = (char*)my_malloc(sizeof(char)* + (strlen(formatted_parent_pin_prefix) + 5 + strlen(pin2pin_interc_parent_mode->name) + + 2 + strlen(src_pb_type->name) + 1 + strlen(my_itoa(src_pb_type_index)) + 1 + 1)); + sprintf((*src_pin_prefix), "%smode[%s]_%s[%d]", + formatted_parent_pin_prefix, pin2pin_interc_parent_mode->name, src_pb_type->name, src_pb_type_index); + */ + /*Simplify the prefix, make the SPICE netlist readable*/ + (*src_pin_prefix) = (char*)my_malloc(sizeof(char)* + (strlen(src_pb_type->name) + 1 + strlen(my_itoa(src_pb_type_index)) + 1 + 1)); + sprintf((*src_pin_prefix), "%s_%d_", + src_pb_type->name, src_pb_type_index); + if (des_pb_type == src_pb_type->parent_mode->parent_pb_type) { /* Interconnection from parent pb_type*/ + /* + (*des_pin_prefix) = my_strdup(chomped_parent_pin_prefix); + */ + /*Simplify the prefix, make the SPICE netlist readable*/ + (*des_pin_prefix) = (char*)my_malloc(sizeof(char)* + (5 + strlen(src_pb_type->parent_mode->name) + 2)); + sprintf((*des_pin_prefix), "mode_%s_", src_pb_type->parent_mode->name); + } else { + /* + (*des_pin_prefix) = (char*)my_malloc(sizeof(char)* + (strlen(formatted_parent_pin_prefix) + 5 + strlen(pin2pin_interc_parent_mode->name) + + 2 + strlen(des_pb_type->name) + 1 + strlen(my_itoa(des_pb_type_index)) + 1 + 1)); + sprintf((*des_pin_prefix), "%smode[%s]_%s[%d]", + formatted_parent_pin_prefix, pin2pin_interc_parent_mode->name, des_pb_type->name, des_pb_type_index); + */ + /*Simplify the prefix, make the SPICE netlist readable*/ + (*des_pin_prefix) = (char*)my_malloc(sizeof(char)* + (strlen(des_pb_type->name) + 1 + strlen(my_itoa(des_pb_type_index)) + 1 + 1)); + sprintf((*des_pin_prefix), "%s_%d_", + des_pb_type->name, des_pb_type_index); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s [LINE%d])Invalid pin to pin interconnection type!\n", + __FILE__, __LINE__); + exit(1); + } + return; +} + +void verilog_find_interc_fan_in_des_pb_graph_pin(t_pb_graph_pin* des_pb_graph_pin, + t_mode* cur_mode, + t_interconnect** cur_interc, + int* fan_in) { + int iedge; + + (*cur_interc) = NULL; + (*fan_in) = 0; + + /* Search the input edges only, stats on the size of MUX we may need (fan-in) */ + for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { + /* 1. First, we should make sure this interconnect is in the selected mode!!!*/ + if (cur_mode == des_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode) { + /* Check this edge*/ + check_pb_graph_edge(*(des_pb_graph_pin->input_edges[iedge])); + /* Record the interconnection*/ + if (NULL == (*cur_interc)) { + (*cur_interc) = des_pb_graph_pin->input_edges[iedge]->interconnect; + } else { /* Make sure the interconnections for this pin is the same!*/ + assert((*cur_interc) == des_pb_graph_pin->input_edges[iedge]->interconnect); + } + /* Search the input_pins of input_edges only*/ + (*fan_in) += des_pb_graph_pin->input_edges[iedge]->num_input_pins; + } + } + + return; +} + +/* We check output_pins of cur_pb_graph_node and its the input_edges + * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node + * src_pb_graph_node.[in|out]_pins -----------------> des_pb_graph_node.[in|out]pins + * /|\ + * | + * input_pins, edges, output_pins + */ +void dump_verilog_pb_graph_pin_interc(FILE* fp, + char* parent_pin_prefix, + enum e_pin2pin_interc_type pin2pin_interc_type, + t_pb_graph_pin* des_pb_graph_pin, + t_mode* cur_mode, + int select_edge) { + int i, iedge, ipin; + int fan_in = 0; + t_interconnect* cur_interc = NULL; + enum e_interconnect verilog_interc_type = DIRECT_INTERC; + + t_pb_graph_pin* src_pb_graph_pin = NULL; + t_pb_graph_node* src_pb_graph_node = NULL; + t_pb_type* src_pb_type = NULL; + + t_pb_graph_node* des_pb_graph_node = NULL; + + char* formatted_parent_pin_prefix = chomp_verilog_node_prefix(parent_pin_prefix); /* Complete a "_" at the end if needed*/ + char* src_pin_prefix = NULL; + char* des_pin_prefix = NULL; + + int num_mux_sram_bits = 0; + int* mux_sram_bits = NULL; + int cur_num_sram = 0; + int mux_level = 0; + int num_mux_conf_bits = 0; + int num_mux_reserved_conf_bits = 0; + int cur_bl, cur_wl; + t_spice_model* mem_model = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* 1. identify pin interconnection type, + * 2. Identify the number of fan-in (Consider interconnection edges of only selected mode) + * 3. Select and print the SPICE netlist + */ + fan_in = 0; + cur_interc = NULL; + verilog_find_interc_fan_in_des_pb_graph_pin(des_pb_graph_pin, cur_mode, &cur_interc, &fan_in); + if ((NULL == cur_interc)||(0 == fan_in)) { + /* No interconnection matched */ + /* Connect this pin to GND for better convergence */ + /* TODO: find the correct pin name!!!*/ + /* + dump_verilog_dangling_des_pb_graph_pin_interc(fp, des_pb_graph_pin, cur_mode, pin2pin_interc_type, + formatted_parent_pin_prefix); + */ + return; + } + /* Initialize the interconnection type that will be implemented in SPICE netlist*/ + switch (cur_interc->type) { + case DIRECT_INTERC: + assert(1 == fan_in); + verilog_interc_type = DIRECT_INTERC; + break; + case COMPLETE_INTERC: + if (1 == fan_in) { + verilog_interc_type = DIRECT_INTERC; + } else { + assert((2 == fan_in)||(2 < fan_in)); + verilog_interc_type = MUX_INTERC; + } + break; + case MUX_INTERC: + assert((2 == fan_in)||(2 < fan_in)); + verilog_interc_type = MUX_INTERC; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid interconnection type for %s (Arch[LINE%d])!\n", + __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); + exit(1); + } + /* This time, (2nd round), we print the subckt, according to interc type*/ + switch (verilog_interc_type) { + case DIRECT_INTERC: + /* Check : + * 1. Direct interc has only one fan-in! + */ + assert(1 == fan_in); + //assert(1 == des_pb_graph_pin->num_input_edges); + /* For more than one mode defined, the direct interc has more than one input_edge , + * We need to find which edge is connected the pin we want + */ + for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { + if (cur_interc == des_pb_graph_pin->input_edges[iedge]->interconnect) { + break; + } + } + assert(iedge < des_pb_graph_pin->num_input_edges); + /* 2. spice_model is a wire */ + assert(NULL != cur_interc->spice_model); + assert(SPICE_MODEL_WIRE == cur_interc->spice_model->type); + assert(NULL != cur_interc->spice_model->wire_param); + /* Initialize*/ + /* Source pin, node, pb_type*/ + src_pb_graph_pin = des_pb_graph_pin->input_edges[iedge]->input_pins[0]; + src_pb_graph_node = src_pb_graph_pin->parent_node; + src_pb_type = src_pb_graph_node->pb_type; + /* Des pin, node, pb_type */ + des_pb_graph_node = des_pb_graph_pin->parent_node; + /* Generate the pin_prefix for src_pb_graph_node and des_pb_graph_node*/ + generate_verilog_src_des_pb_graph_pin_prefix(src_pb_graph_node, des_pb_graph_node, pin2pin_interc_type, + cur_interc, formatted_parent_pin_prefix, &src_pin_prefix, &des_pin_prefix); + /* Call the subckt that has already been defined before */ + fprintf(fp, "%s ", cur_interc->spice_model->name); + fprintf(fp, "%s_%d_ (", cur_interc->spice_model->prefix, cur_interc->spice_model->cnt); + cur_interc->spice_model->cnt++; /* Stats the number of spice_model used*/ + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE)) { + fprintf(fp, ",\n"); + } + /* Print the pin names! Input and output + * Input: port_prefix_->[pin_index] + * Output: port_prefix_[pin_index] + */ + /* Input */ + /* Make sure correctness*/ + assert(src_pb_type == des_pb_graph_pin->input_edges[iedge]->input_pins[0]->port->parent_pb_type); + /* Print */ + fprintf(fp, "%s__%s_%d_, ", + src_pin_prefix, src_pb_graph_pin->port->name, src_pb_graph_pin->pin_number); + /* Output */ + fprintf(fp, "%s__%s_%d_ ", + des_pin_prefix, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number); + /* Middle output for wires in logic blocks: TODO: Abolish to save simulation time */ + /* fprintf(fp, "gidle_mid_out "); */ + /* Local vdd and gnd, TODO: we should have an independent VDD for all local interconnections*/ + fprintf(fp, ");\n"); + /* Free */ + my_free(src_pin_prefix); + my_free(des_pin_prefix); + src_pin_prefix = NULL; + des_pin_prefix = NULL; + break; + case COMPLETE_INTERC: + case MUX_INTERC: + /* Check : + * MUX should have at least 2 fan_in + */ + assert((2 == fan_in)||(2 < fan_in)); + /* 2. spice_model is a wire */ + assert(NULL != cur_interc->spice_model); + assert(SPICE_MODEL_MUX == cur_interc->spice_model->type); + /* Create a local bus */ + fprintf(fp, "wire [0:%d] in_bus_%s_size%d_%d_ ;\n", fan_in - 1, + cur_interc->spice_model->name, fan_in, cur_interc->spice_model->cnt); + ipin = 0; + for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { + if (cur_mode != des_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode) { + continue; + } + check_pb_graph_edge(*(des_pb_graph_pin->input_edges[iedge])); + /* Initialize*/ + /* Source pin, node, pb_type*/ + src_pb_graph_pin = des_pb_graph_pin->input_edges[iedge]->input_pins[0]; + src_pb_graph_node = src_pb_graph_pin->parent_node; + src_pb_type = src_pb_graph_node->pb_type; + /* Des pin, node, pb_type */ + des_pb_graph_node = des_pb_graph_pin->parent_node; + /* Generate the pin_prefix for src_pb_graph_node and des_pb_graph_node*/ + generate_verilog_src_des_pb_graph_pin_prefix(src_pb_graph_node, des_pb_graph_node, pin2pin_interc_type, + cur_interc, formatted_parent_pin_prefix, &src_pin_prefix, &des_pin_prefix); + /* We need to find out if the des_pb_graph_pin is in the mode we want !*/ + /* Print */ + fprintf(fp, "assign in_bus_%s_size%d_%d_[%d] = ", + cur_interc->spice_model->name, fan_in, cur_interc->spice_model->cnt, ipin); + fprintf(fp, "%s__%s_%d_ ; \n", + src_pin_prefix, src_pb_graph_pin->port->name, src_pb_graph_pin->pin_number); + ipin++; + /* Free */ + my_free(src_pin_prefix); + my_free(des_pin_prefix); + src_pin_prefix = NULL; + des_pin_prefix = NULL; + } + assert(ipin == fan_in); + /* Print SRAMs that configure this MUX */ + /* cur_num_sram = sram_verilog_model->cnt; */ + cur_num_sram = get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info); + get_sram_orgz_info_num_blwl(sram_verilog_orgz_info, &cur_bl, &cur_wl); + /* connect to reserved BL/WLs ? */ + num_mux_reserved_conf_bits = count_num_reserved_conf_bits_one_spice_model(cur_interc->spice_model, + sram_verilog_orgz_info->type, + fan_in); + /* Get the number of configuration bits required by this MUX */ + num_mux_conf_bits = count_num_conf_bits_one_spice_model(cur_interc->spice_model, + sram_verilog_orgz_info->type, + fan_in); + + /* Dump the configuration port bus */ + dump_verilog_mux_config_bus(fp, cur_interc->spice_model, sram_verilog_orgz_info, + fan_in, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits); + + /* Call the subckt that has already been defined before */ + fprintf(fp, "%s_size%d ", cur_interc->spice_model->name, fan_in); + fprintf(fp, "%s_size%d_%d_ (", cur_interc->spice_model->prefix, fan_in, cur_interc->spice_model->cnt); + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE)) { + fprintf(fp, ",\n"); + } + /* Inputs */ + fprintf(fp, "in_bus_%s_size%d_%d_, ", + cur_interc->spice_model->name, fan_in, cur_interc->spice_model->cnt); + /* Generate the pin_prefix for src_pb_graph_node and des_pb_graph_node*/ + generate_verilog_src_des_pb_graph_pin_prefix(src_pb_graph_node, des_pb_graph_node, pin2pin_interc_type, + cur_interc, formatted_parent_pin_prefix, &src_pin_prefix, &des_pin_prefix); + /* Outputs */ + fprintf(fp, "%s__%s_%d_, ", + des_pin_prefix, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number); + + /* Different design technology requires different configuration bus! */ + dump_verilog_mux_config_bus_ports(fp, cur_interc->spice_model, sram_verilog_orgz_info, + fan_in, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits); + + fprintf(fp, ");\n"); + + assert(select_edge < fan_in); + /* SRAMs */ + switch (cur_interc->spice_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + decode_cmos_mux_sram_bits(cur_interc->spice_model, fan_in, select_edge, + &num_mux_sram_bits, &mux_sram_bits, &mux_level); + break; + case SPICE_MODEL_DESIGN_RRAM: + decode_verilog_rram_mux(cur_interc->spice_model, fan_in, select_edge, + &num_mux_sram_bits, &mux_sram_bits, &mux_level); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology for verilog model (%s)!\n", + __FILE__, __LINE__, cur_interc->spice_model->name); + } + + /* Print the encoding in SPICE netlist for debugging */ + switch (cur_interc->spice_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + fprintf(fp, "//----- SRAM bits for MUX[%d], level=%d, select_path_id=%d. -----\n", + cur_interc->spice_model->cnt, mux_level, select_edge); + fprintf(fp, "//----- From LSB(LEFT) TO MSB (RIGHT) -----\n"); + fprintf(fp, "//-----"); + fprint_commented_sram_bits(fp, num_mux_sram_bits, mux_sram_bits); + fprintf(fp, "-----\n"); + break; + case SPICE_MODEL_DESIGN_RRAM: + fprintf(fp, "//----- BL/WL bits for 4T1R MUX[%d], level=%d, select_path_id=%d. -----\n", + cur_interc->spice_model->cnt, mux_level, select_edge); + fprintf(fp, "//----- From LSB(LEFT) TO MSB (RIGHT) -----\n"); + fprintf(fp, "//---- BL: "); + fprint_commented_sram_bits(fp, num_mux_sram_bits/2, mux_sram_bits); + fprintf(fp, "-----\n"); + fprintf(fp, "//----- From LSB(LEFT) TO MSB (RIGHT) -----\n"); + fprintf(fp, "//---- WL: "); + fprint_commented_sram_bits(fp, num_mux_sram_bits/2, mux_sram_bits + num_mux_sram_bits/2); + fprintf(fp, "-----\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology for verilog model (%s)!\n", + __FILE__, __LINE__, cur_interc->spice_model->name); + } + + /* Store the configuraion bit to linked-list */ + add_mux_conf_bits_to_llist(fan_in, sram_verilog_orgz_info, + num_mux_sram_bits, mux_sram_bits, + cur_interc->spice_model); + + get_sram_orgz_info_mem_model(sram_verilog_orgz_info, &mem_model); + /* Dump sram modules */ + switch (cur_interc->spice_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + /* SRAM-based MUX required dumping SRAMs! */ + for (i = 0; i < num_mux_sram_bits; i++) { + dump_verilog_mux_sram_submodule(fp, sram_verilog_orgz_info, cur_interc->spice_model, fan_in, + mem_model); /* use the mem_model in sram_verilog_orgz_info */ + } + break; + case SPICE_MODEL_DESIGN_RRAM: + /* RRAM-based MUX does not need any SRAM dumping + * But we have to get the number of configuration bits required by this MUX + * and update the number of memory bits + */ + update_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info, cur_num_sram + num_mux_conf_bits); + update_sram_orgz_info_num_blwl(sram_verilog_orgz_info, + cur_bl + num_mux_conf_bits, + cur_wl + num_mux_conf_bits); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology for verilog model (%s)!\n", + __FILE__, __LINE__, cur_interc->spice_model->name); + } + + /* update sram counter */ + cur_interc->spice_model->cnt++; + + /* Free */ + my_free(mux_sram_bits); + my_free(src_pin_prefix); + my_free(des_pin_prefix); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid interconnection type for %s (Arch[LINE%d])!\n", + __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); + exit(1); + } + + return; +} + + +/* Print the SPICE interconnections according to pb_graph */ +void dump_verilog_pb_graph_interc(FILE* fp, + char* pin_prefix, + t_pb_graph_node* cur_pb_graph_node, + t_pb* cur_pb, + int select_mode_index, + int is_idle) { + int iport, ipin; + int ipb, jpb; + t_mode* cur_mode = NULL; + t_pb_type* cur_pb_type = cur_pb_graph_node->pb_type; + t_pb_graph_node* child_pb_graph_node = NULL; + t_pb* child_pb = NULL; + int is_child_pb_idle = 0; + + char* formatted_pin_prefix = format_verilog_node_prefix(pin_prefix); /* Complete a "_" at the end if needed*/ + + int node_index = -1; + int prev_node = -1; + int path_id = -1; + t_rr_node* pb_rr_nodes = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check cur_pb_type*/ + if (NULL == cur_pb_type) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb_type.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Assign current mode */ + cur_mode = &(cur_pb_graph_node->pb_type->modes[select_mode_index]); + + /* We check output_pins of cur_pb_graph_node and its the input_edges + * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node + * child_pb_graph_node.output_pins -----------------> cur_pb_graph_node.outpins + * /|\ + * | + * input_pins, edges, output_pins + */ + for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) { + for (ipin = 0; ipin < cur_pb_graph_node->num_output_pins[iport]; ipin++) { + /* If this is a idle block, we set 0 to the selected edge*/ + if (is_idle) { + assert(NULL == cur_pb); + dump_verilog_pb_graph_pin_interc(fp, + formatted_pin_prefix, /* parent_pin_prefix */ + OUTPUT2OUTPUT_INTERC, + &(cur_pb_graph_node->output_pins[iport][ipin]), + cur_mode, + 0); + } else { + /* Get the selected edge of current pin*/ + assert(NULL != cur_pb); + pb_rr_nodes = cur_pb->rr_graph; + node_index = cur_pb_graph_node->output_pins[iport][ipin].pin_count_in_cluster; + prev_node = pb_rr_nodes[node_index].prev_node; + /* Make sure this pb_rr_node is not OPEN and is not a primitive output*/ + if (OPEN == prev_node) { + path_id = 0; // + } else { + /* Find the path_id */ + path_id = verilog_find_path_id_between_pb_rr_nodes(pb_rr_nodes, prev_node, node_index); + assert(-1 != path_id); + } + dump_verilog_pb_graph_pin_interc(fp, + formatted_pin_prefix, /* parent_pin_prefix */ + OUTPUT2OUTPUT_INTERC, + &(cur_pb_graph_node->output_pins[iport][ipin]), + cur_mode, + path_id); + } + } + } + + /* We check input_pins of child_pb_graph_node and its the input_edges + * Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node + * cur_pb_graph_node.input_pins -----------------> child_pb_graph_node.input_pins + * /|\ + * | + * input_pins, edges, output_pins + */ + for (ipb = 0; ipb < cur_pb_type->modes[select_mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb_type->modes[select_mode_index].pb_type_children[ipb].num_pb; jpb++) { + child_pb_graph_node = &(cur_pb_graph_node->child_pb_graph_nodes[select_mode_index][ipb][jpb]); + /* If this is a idle block, we set 0 to the selected edge*/ + if (is_idle) { + assert(NULL == cur_pb); + /* For each child_pb_graph_node input pins*/ + for (iport = 0; iport < child_pb_graph_node->num_input_ports; iport++) { + for (ipin = 0; ipin < child_pb_graph_node->num_input_pins[iport]; ipin++) { + dump_verilog_pb_graph_pin_interc(fp, + formatted_pin_prefix, /* parent_pin_prefix */ + INPUT2INPUT_INTERC, + &(child_pb_graph_node->input_pins[iport][ipin]), + cur_mode, + 0); + } + } + /* TODO: for clock pins, we should do the same work */ + for (iport = 0; iport < child_pb_graph_node->num_clock_ports; iport++) { + for (ipin = 0; ipin < child_pb_graph_node->num_clock_pins[iport]; ipin++) { + dump_verilog_pb_graph_pin_interc(fp, + formatted_pin_prefix, /* parent_pin_prefix */ + INPUT2INPUT_INTERC, + &(child_pb_graph_node->clock_pins[iport][ipin]), + cur_mode, + 0); + } + } + continue; + } + assert(NULL != cur_pb); + child_pb = &(cur_pb->child_pbs[ipb][jpb]); + /* Check if child_pb is empty */ + if (NULL != child_pb->name) { + is_child_pb_idle = 0; + } else { + is_child_pb_idle = 1; + } + /* Get pb_rr_graph of current pb*/ + pb_rr_nodes = child_pb->rr_graph; + /* For each child_pb_graph_node input pins*/ + for (iport = 0; iport < child_pb_graph_node->num_input_ports; iport++) { + for (ipin = 0; ipin < child_pb_graph_node->num_input_pins[iport]; ipin++) { + if (is_child_pb_idle) { + } else { + /* Get the index of the edge that are selected to pass signal*/ + node_index = child_pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster; + prev_node = pb_rr_nodes[node_index].prev_node; + /* Make sure this pb_rr_node is not OPEN and is not a primitive output*/ + if (OPEN == prev_node) { + path_id = 0; // + } else { + /* Find the path_id */ + path_id = verilog_find_path_id_between_pb_rr_nodes(pb_rr_nodes, prev_node, node_index); + assert(-1 != path_id); + } + } + /* Write the interconnection*/ + dump_verilog_pb_graph_pin_interc(fp, + formatted_pin_prefix, /* parent_pin_prefix */ + INPUT2INPUT_INTERC, + &(child_pb_graph_node->input_pins[iport][ipin]), + cur_mode, + path_id); + } + } + /* TODO: for clock pins, we should do the same work */ + for (iport = 0; iport < child_pb_graph_node->num_clock_ports; iport++) { + for (ipin = 0; ipin < child_pb_graph_node->num_clock_pins[iport]; ipin++) { + if (is_child_pb_idle) { + } else { + /* Get the index of the edge that are selected to pass signal*/ + node_index = child_pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster; + prev_node = pb_rr_nodes[node_index].prev_node; + /* Make sure this pb_rr_node is not OPEN and is not a primitive output*/ + if (OPEN == prev_node) { + path_id = 0; // + } else { + /* Find the path_id */ + path_id = verilog_find_path_id_between_pb_rr_nodes(pb_rr_nodes, prev_node, node_index); + assert(-1 != path_id); + } + } + /* Write the interconnection*/ + dump_verilog_pb_graph_pin_interc(fp, + formatted_pin_prefix, /* parent_pin_prefix */ + INPUT2INPUT_INTERC, + &(child_pb_graph_node->clock_pins[iport][ipin]), + cur_mode, + path_id); + } + } + } + } + + return; +} + +/* Print the netlist for primitive pb_types*/ +void dump_verilog_pb_graph_primitive_node(FILE* fp, + char* subckt_prefix, + t_pb* cur_pb, + t_pb_graph_node* cur_pb_graph_node, + int pb_type_index) { + t_pb_type* cur_pb_type = NULL; + char* formatted_subckt_prefix = format_verilog_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/ + t_spice_model* verilog_model = NULL; + char* subckt_name = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check cur_pb_graph_node*/ + if (NULL == cur_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb_graph_node.\n", + __FILE__, __LINE__); + exit(1); + } + + verilog_model = cur_pb_type->spice_model; + /* If we define a SPICE model for the pb_type, + * We should print the subckt of it. + * 1. If the SPICE model defines an included netlist, we quote the netlist subckt + * 2. If not defined an included netlist, we built one only if this is a LUT + */ + /* Example: []*/ + subckt_name = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + + strlen(cur_pb_type->name) + 1 + + strlen(my_itoa(pb_type_index)) + 1 + 1)); /* Plus the '0' at the end of string*/ + sprintf(subckt_name, "%s%s_%d_", formatted_subckt_prefix, cur_pb_type->name, pb_type_index); + /* Check if defines an included netlist*/ + if (NULL == verilog_model->model_netlist) { + if (LUT_CLASS == cur_pb_type->class_type) { + /* For LUT, we have a built-in netlist, See "verilog_lut.c", So we don't do anything here */ + } else { + /* We report an error */ + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Require an included netlist in Pb_type(%s) SPICE_model(%s)!\n", + __FILE__, __LINE__, cur_pb_type->name, verilog_model->name); + exit(1); + } + } + /* Print the definition line + * IMPORTANT: NO SRAMs ports are created here, they are fixed when quoting spice_models + */ + fprintf(fp, "module %s (", subckt_name); + /* subckt_port_name = format_verilog_node_prefix(subckt_name); */ + /* Inputs, outputs, inouts, clocks */ + dump_verilog_pb_type_ports(fp, subckt_name, 0, cur_pb_type, TRUE, FALSE); + /* SRAM ports */ + fprintf(fp, ");\n"); + /* Include the spice_model*/ + fprintf(fp, "%s %s[%d] (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + verilog_model->cnt++; /* Stats the number of verilog_model used*/ + /* Make input, output, inout, clocks connected*/ + /* IMPORTANT: (sequence of these ports should be changed!) */ + dump_verilog_pb_type_ports(fp, subckt_name, 0, cur_pb_type, FALSE, FALSE); + fprintf(fp, ");"); + /* Print end of subckt*/ + fprintf(fp, "endmodule\n"); + /* Free */ + my_free(subckt_name); + + return; +} + +/* Print the subckt of a primitive pb */ +void dump_verilog_pb_primitive_verilog_model(FILE* fp, + char* subckt_prefix, + t_pb* prim_pb, + t_pb_graph_node* prim_pb_graph_node, + int pb_index, + t_spice_model* verilog_model, + int is_idle) { + t_pb_type* prim_pb_type = NULL; + t_logical_block* mapped_logical_block = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check cur_pb_graph_node*/ + if (NULL == prim_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb_graph_node.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Initialize */ + prim_pb_type = prim_pb_graph_node->pb_type; + if (is_idle) { + mapped_logical_block = NULL; + } else { + mapped_logical_block = &logical_block[prim_pb->logical_block]; + } + + /* Asserts*/ + assert(pb_index == prim_pb_graph_node->placement_index); + assert(0 == strcmp(verilog_model->name, prim_pb_type->spice_model->name)); + if (is_idle) { + assert(NULL == prim_pb); + } else { + if (NULL == prim_pb) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid prim_pb.\n", + __FILE__, __LINE__); + exit(1); + } + } + + /* According to different type, we print netlist*/ + switch (verilog_model->type) { + case SPICE_MODEL_LUT: + /* If this is a idle block we should set sram_bits to zero*/ + dump_verilog_pb_primitive_lut(fp, subckt_prefix, mapped_logical_block, prim_pb_graph_node, + pb_index, verilog_model); + break; + case SPICE_MODEL_FF: + assert(NULL != verilog_model->model_netlist); + /* TODO : We should learn trigger type and initial value!!! and how to apply them!!! */ + dump_verilog_pb_primitive_ff(fp, subckt_prefix, mapped_logical_block, prim_pb_graph_node, + pb_index, verilog_model); + break; + case SPICE_MODEL_IOPAD: + assert(NULL != verilog_model->model_netlist); + dump_verilog_pb_primitive_io(fp, subckt_prefix, mapped_logical_block, prim_pb_graph_node, + pb_index, verilog_model); + break; + case SPICE_MODEL_HARDLOGIC: + assert(NULL != verilog_model->model_netlist); + dump_verilog_pb_primitive_hardlogic(fp, subckt_prefix, mapped_logical_block, prim_pb_graph_node, + pb_index, verilog_model); + break; + case SPICE_MODEL_VDD: + /* TODO: Add codes for VDD */ + break; + case SPICE_MODEL_GND: + /* TODO: Add codes for GND */ + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of verilog_model(%s), should be [LUT|FF|HARD_LOGIC|IO]!\n", + __FILE__, __LINE__, verilog_model->name); + exit(1); + break; + } + + return; +} + +/* Print idle pb_types recursively + * search the idle_mode until we reach the leaf node + */ +void dump_verilog_idle_pb_graph_node_rec(FILE* fp, + char* subckt_prefix, + t_pb_graph_node* cur_pb_graph_node, + int pb_type_index) { + int mode_index, ipb, jpb, child_mode_index; + t_pb_type* cur_pb_type = NULL; + char* subckt_name = NULL; + char* formatted_subckt_prefix = format_verilog_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/ + char* pass_on_prefix = NULL; + char* child_pb_type_prefix = NULL; + char* subckt_port_prefix = NULL; + + int child_pb_num_reserved_conf_bits = 0; + int child_pb_num_conf_bits = 0; + int child_pb_num_inpads = 0; + int child_pb_num_outpads = 0; + int child_pb_num_iopads = 0; + + int num_reserved_conf_bits = 0; + int num_conf_bits = 0; + int stamped_sram_cnt = get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info); + int stamped_sram_lsb = get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info); + + int stamped_iopad_cnt = iopad_verilog_model->cnt; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check cur_pb_graph_node*/ + if (NULL == cur_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb_graph_node.\n", + __FILE__, __LINE__); + exit(1); + } + cur_pb_type = cur_pb_graph_node->pb_type; + + /* Recursively finish all the child pb_types*/ + if (NULL == cur_pb_type->spice_model) { + /* Find the mode that define_idle_mode*/ + mode_index = find_pb_type_idle_mode_index((*cur_pb_type)); + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Pass the SPICE mode prefix on, + * mode[]_ + */ + pass_on_prefix = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(cur_pb_type->name) + 1 + + strlen(my_itoa(pb_type_index)) + 7 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1 + 1)); + sprintf(pass_on_prefix, "%s%s_%d__mode_%s__", + formatted_subckt_prefix, cur_pb_type->name, pb_type_index, cur_pb_type->modes[mode_index].name); + /* Recursive*/ + dump_verilog_idle_pb_graph_node_rec(fp, pass_on_prefix, + &(cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), jpb); + /* Free */ + my_free(pass_on_prefix); + } + } + } + + /* Check if this has defined a spice_model*/ + if (NULL != cur_pb_type->spice_model) { + switch (cur_pb_type->class_type) { + case LUT_CLASS: + /* Consider the num_pb, create all the subckts*/ + dump_verilog_pb_primitive_verilog_model(fp, formatted_subckt_prefix, + NULL, cur_pb_graph_node, pb_type_index, + cur_pb_type->spice_model, 1); + /* update the number of SRAM, I/O pads */ + stamped_sram_cnt += cur_pb_type->default_mode_num_conf_bits; + break; + case LATCH_CLASS: + assert(0 == cur_pb_type->num_modes); + /* Consider the num_pb, create all the subckts*/ + dump_verilog_pb_primitive_verilog_model(fp, formatted_subckt_prefix, + NULL, cur_pb_graph_node, pb_type_index, cur_pb_type->spice_model, 1); + /* update the number of SRAM, I/O pads */ + /* update stamped sram counter */ + stamped_sram_cnt += cur_pb_type->default_mode_num_conf_bits; + break; + case UNKNOWN_CLASS: + case MEMORY_CLASS: + /* Consider the num_pb, create all the subckts*/ + dump_verilog_pb_primitive_verilog_model(fp, formatted_subckt_prefix, + NULL, cur_pb_graph_node, pb_type_index, cur_pb_type->spice_model, 1); + /* update the number of SRAM, I/O pads */ + /* update stamped sram counter */ + stamped_sram_cnt += cur_pb_type->default_mode_num_conf_bits; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Unknown class type of pb_type(%s)!\n", + __FILE__, __LINE__, cur_pb_type->name); + exit(1); + } + /* Check */ + assert(stamped_sram_cnt == get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info)); + assert(stamped_iopad_cnt == iopad_verilog_model->cnt); + /* Finish job for primitive node, return */ + return; + } + + /* Find the mode that define_idle_mode*/ + mode_index = find_pb_type_idle_mode_index((*cur_pb_type)); + /* Create a new subckt */ + /* mode[] + */ + subckt_name = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(cur_pb_type->name) + 1 + + strlen(my_itoa(pb_type_index)) + 7 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1)); + /* Definition*/ + sprintf(subckt_name, "%s%s_%d__mode_%s_", + formatted_subckt_prefix, cur_pb_type->name, pb_type_index, cur_pb_type->modes[mode_index].name); + /* Comment lines */ + fprintf(fp, "//----- Idle programmable logic block Verilog module %s -----\n", subckt_name); + fprintf(fp, "module %s (", subckt_name); + fprintf(fp, "\n"); + /* Inputs, outputs, inouts, clocks */ + subckt_port_prefix = (char*)my_malloc(sizeof(char)* + (5 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1)); + sprintf(subckt_port_prefix, "mode_%s_", cur_pb_type->modes[mode_index].name); + /* + dump_verilog_pb_type_ports(fp, subckt_name, 0, cur_pb_type); + */ + /* dump global ports */ + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + fprintf(fp, ",\n"); + } + /* Simplify the port prefix, make SPICE netlist readable */ + dump_verilog_pb_type_ports(fp, subckt_port_prefix, 0, cur_pb_type, TRUE, FALSE); + /* Print Input Pad and Output Pad */ + dump_verilog_grid_common_port(fp, iopad_verilog_model, + gio_inout_prefix, + stamped_iopad_cnt, iopad_verilog_model->cnt - 1, + VERILOG_PORT_INPUT); + /* Print Configuration ports */ + /* sram_verilog_model->cnt should be updated because all the child pbs have been dumped + * stamped_sram_cnt remains the old sram_verilog_model->cnt before all the child pbs are dumped + * Note by far, sram_verilog_model->cnt could be smaller than num_conf_bits + * because the interconnection of current pb_type/pb has not yet dumped, which may contain + * a few configuration bits. + */ + num_reserved_conf_bits = cur_pb_type->default_mode_num_reserved_conf_bits; + if (0 < num_reserved_conf_bits) { + fprintf(fp, ",\n"); + } + dump_verilog_reserved_sram_ports(fp, sram_verilog_orgz_info, + 0, num_reserved_conf_bits - 1, + VERILOG_PORT_INPUT); + num_conf_bits = cur_pb_type->default_mode_num_conf_bits; + if (0 < num_conf_bits) { + fprintf(fp, ",\n"); + } + dump_verilog_sram_ports(fp, sram_verilog_orgz_info, + stamped_sram_cnt, stamped_sram_cnt + num_conf_bits - 1, + VERILOG_PORT_INPUT); + /* Finish with local vdd and gnd */ + fprintf(fp, ");\n"); + + /* Definition ends*/ + /* Quote all child pb_types */ + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + /* Each child may exist multiple times in the hierarchy*/ + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* we should make sure this placement index == child_pb_type[jpb]*/ + assert(jpb == cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb].placement_index); + /* If the pb_type_children is a leaf node, we don't use the mode to name it, + * else we can use the mode to name it + */ + if (NULL == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model) { /* Not a leaf node*/ + child_mode_index = find_pb_type_idle_mode_index(cur_pb_type->modes[mode_index].pb_type_children[ipb]); + fprintf(fp, "%s_%s_%d__mode_%s_ ", + subckt_name, cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb, + cur_pb_type->modes[mode_index].pb_type_children[ipb].modes[child_mode_index].name); + } else { /* Have a verilog model definition, this is a leaf node*/ + fprintf(fp, "%s_%s_%d_ ", + subckt_name, cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); + } + /* Collect information of child pb_type */ + child_pb_num_reserved_conf_bits = cur_pb_type->modes[mode_index].pb_type_children[ipb].default_mode_num_reserved_conf_bits; + child_pb_num_conf_bits = cur_pb_type->modes[mode_index].pb_type_children[ipb].default_mode_num_conf_bits; + child_pb_num_iopads = cur_pb_type->modes[mode_index].pb_type_children[ipb].default_mode_num_iopads; + + /* mode[]_[] + */ + fprintf(fp, "%s_%d_ (", cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); + fprintf(fp, "\n"); + /* dump global ports */ + /* If the child node is a primitive, we only dump global ports belonging to this primitive */ + if (NULL == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + fprintf(fp, ",\n"); + } + } else { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, + cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model, + FALSE, TRUE)) { + fprintf(fp, ",\n"); + } + } + /* Pass the SPICE mode prefix on, + * mode[]_[] + * [] + */ + /* Simplify the prefix! */ + child_pb_type_prefix = (char*)my_malloc(sizeof(char)* + (strlen(cur_pb_type->modes[mode_index].pb_type_children[ipb].name) + 1 + + strlen(my_itoa(jpb)) + 1 + 1)); + sprintf(child_pb_type_prefix, "%s_%d_", + cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); + /* Print inputs, outputs, inouts, clocks + * NO SRAMs !!! They have already been fixed in the bottom level + */ + dump_verilog_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb]),FALSE, FALSE); + /* Print I/O pads */ + dump_verilog_grid_common_port(fp, iopad_verilog_model, + gio_inout_prefix, + stamped_iopad_cnt, + stamped_iopad_cnt + child_pb_num_iopads - 1, + VERILOG_PORT_CONKT); + /* update stamped outpad counter */ + stamped_iopad_cnt += child_pb_num_iopads; + /* Print configuration ports */ + if (0 < child_pb_num_reserved_conf_bits) { + fprintf(fp, ",\n"); + } + dump_verilog_reserved_sram_ports(fp, sram_verilog_orgz_info, + 0, child_pb_num_reserved_conf_bits - 1, + VERILOG_PORT_CONKT); + if (0 < child_pb_num_conf_bits) { + fprintf(fp, ",\n"); + } + dump_verilog_sram_ports(fp, sram_verilog_orgz_info, + stamped_sram_cnt, + stamped_sram_cnt + child_pb_num_conf_bits - 1, + VERILOG_PORT_CONKT); + /* update stamped sram counter */ + stamped_sram_cnt += child_pb_num_conf_bits; + fprintf(fp, ");\n"); /* Local vdd and gnd*/ + /* Finish */ + my_free(child_pb_type_prefix); + } + } + /* Print interconnections, set is_idle as TRUE*/ + dump_verilog_pb_graph_interc(fp, subckt_name, cur_pb_graph_node, NULL, mode_index, 1); + /* Check each pins of pb_graph_node */ + /* Check and update stamped_sram_cnt */ + assert(!(stamped_sram_cnt > (stamped_sram_lsb + num_conf_bits))); + stamped_sram_cnt = stamped_sram_lsb + num_conf_bits; + /* End the subckt */ + fprintf(fp, "endmodule\n"); + /* Comment lines */ + fprintf(fp, "//----- END Idle programmable logic block Verilog module %s -----\n\n", subckt_name); + /* Free subckt name*/ + my_free(subckt_name); + + assert(stamped_sram_cnt == get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info)); + assert(stamped_iopad_cnt == iopad_verilog_model->cnt); + + return; +} + +/* Print SPICE netlist for each pb and corresponding pb_graph_node*/ +void dump_verilog_pb_graph_node_rec(FILE* fp, + char* subckt_prefix, + t_pb* cur_pb, + t_pb_graph_node* cur_pb_graph_node, + int pb_type_index) { + int mode_index, ipb, jpb, child_mode_index; + t_pb_type* cur_pb_type = NULL; + char* subckt_name = NULL; + char* formatted_subckt_prefix = format_verilog_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/ + char* pass_on_prefix = NULL; + char* child_pb_type_prefix = NULL; + + char* subckt_port_prefix = NULL; + + int num_reserved_conf_bits = 0; + int num_conf_bits = 0; + int child_pb_num_reserved_conf_bits = 0; + int child_pb_num_conf_bits = 0; + int child_pb_num_inpads = 0; + int child_pb_num_outpads = 0; + int child_pb_num_iopads = 0; + + int stamped_sram_cnt = get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info); + int stamped_sram_lsb = get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info); + + int stamped_iopad_cnt = iopad_verilog_model->cnt; + t_pb* child_pb = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check cur_pb_graph_node*/ + if (NULL == cur_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb_graph_node.\n", + __FILE__, __LINE__); + exit(1); + } + cur_pb_type = cur_pb_graph_node->pb_type; + mode_index = cur_pb->mode; + + /* Recursively finish all the child pb_types*/ + if (NULL == cur_pb_type->spice_model) { + /* recursive for the child_pbs*/ + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Pass the SPICE mode prefix on, + * []_mode[]_ + */ + pass_on_prefix = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(cur_pb_type->name) + 1 + + strlen(my_itoa(pb_type_index)) + 7 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1 + 1)); + sprintf(pass_on_prefix, "%s%s_%d__mode_%s__", + formatted_subckt_prefix, cur_pb_type->name, pb_type_index, cur_pb_type->modes[mode_index].name); + /* Recursive*/ + /* Refer to pack/output_clustering.c [LINE 392] */ + if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { + dump_verilog_pb_graph_node_rec(fp, pass_on_prefix, &(cur_pb->child_pbs[ipb][jpb]), + cur_pb->child_pbs[ipb][jpb].pb_graph_node, jpb); + } else { + /* Check if this pb has no children, no children mean idle*/ + dump_verilog_idle_pb_graph_node_rec(fp, pass_on_prefix, + cur_pb->child_pbs[ipb][jpb].pb_graph_node, jpb); + } + /* Free */ + my_free(pass_on_prefix); + } + } + } + + /* Check if this has defined a spice_model*/ + if (NULL != cur_pb_type->spice_model) { + switch (cur_pb_type->class_type) { + case LUT_CLASS: + child_pb = get_lut_child_pb(cur_pb, mode_index); + dump_verilog_pb_primitive_verilog_model(fp, formatted_subckt_prefix, + child_pb, cur_pb_graph_node, + pb_type_index, cur_pb_type->spice_model, 0); + /* update the number of SRAM, I/O pads */ + /* update stamped iopad counter */ + stamped_iopad_cnt += cur_pb->num_iopads; + /* update stamped sram counter */ + stamped_sram_cnt += cur_pb->num_conf_bits; + break; + case LATCH_CLASS: + assert(0 == cur_pb_type->num_modes); + /* Consider the num_pb, create all the subckts*/ + dump_verilog_pb_primitive_verilog_model(fp, formatted_subckt_prefix, + cur_pb, cur_pb_graph_node, pb_type_index, cur_pb_type->spice_model, 0); + /* update the number of SRAM, I/O pads */ + /* update stamped iopad counter */ + stamped_iopad_cnt += cur_pb->num_iopads; + /* update stamped sram counter */ + stamped_sram_cnt += cur_pb->num_conf_bits; + break; + case UNKNOWN_CLASS: + case MEMORY_CLASS: + /* Consider the num_pb, create all the subckts*/ + dump_verilog_pb_primitive_verilog_model(fp, formatted_subckt_prefix, + cur_pb, cur_pb_graph_node, pb_type_index, cur_pb_type->spice_model, 0); + /* update the number of SRAM, I/O pads */ + /* update stamped iopad counter */ + stamped_iopad_cnt += cur_pb->num_iopads; + /* update stamped sram counter */ + stamped_sram_cnt += cur_pb->num_conf_bits; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Unknown class type of pb_type(%s)!\n", + __FILE__, __LINE__, cur_pb_type->name); + exit(1); + } + /* Check */ + assert(stamped_sram_cnt == get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info)); + assert(stamped_iopad_cnt == iopad_verilog_model->cnt); + /* Finish job for primitive node, return */ + return; + } + + /* Create a new subckt */ + /* mode[] + */ + subckt_name = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(cur_pb_type->name) + 1 + + strlen(my_itoa(pb_type_index)) + 7 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1)); + /* Definition*/ + sprintf(subckt_name, "%s%s_%d__mode_%s_", + formatted_subckt_prefix, cur_pb_type->name, pb_type_index, cur_pb_type->modes[mode_index].name); + /* Comment lines */ + fprintf(fp, "//----- Programmable logic block Verilog module %s -----\n", subckt_name); + fprintf(fp, "module %s (", subckt_name); + /* Inputs, outputs, inouts, clocks */ + subckt_port_prefix = (char*)my_malloc(sizeof(char)* + (5 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1)); + sprintf(subckt_port_prefix, "mode_%s_", cur_pb_type->modes[mode_index].name); + /* + dump_verilog_pb_type_ports(fp, subckt_name, 0, cur_pb_type); + */ + /* Print global set and reset */ + fprintf(fp, "\n"); + /* dump global ports */ + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + fprintf(fp, ",\n"); + } + /* Simplify the prefix! Make the SPICE netlist readable*/ + dump_verilog_pb_type_ports(fp, subckt_port_prefix, 0, cur_pb_type, TRUE, FALSE); + /* Print Input Pad and Output Pad */ + dump_verilog_grid_common_port(fp, iopad_verilog_model, + gio_inout_prefix, + stamped_iopad_cnt, iopad_verilog_model->cnt - 1, + VERILOG_PORT_INPUT); + /* Print Configuration ports */ + /* sram_verilog_model->cnt should be updated because all the child pbs have been dumped + * stamped_sram_cnt remains the old sram_verilog_model->cnt before all the child pbs are dumped + * Note by far, sram_verilog_model->cnt could be smaller than num_conf_bits + * because the interconnection of current pb_type/pb has not yet dumped, which may contain + * a few configuration bits. + */ + num_reserved_conf_bits = cur_pb->num_reserved_conf_bits; + if (0 < num_reserved_conf_bits) { + fprintf(fp, ",\n"); + } + dump_verilog_reserved_sram_ports(fp, sram_verilog_orgz_info, + 0, num_reserved_conf_bits - 1, + VERILOG_PORT_INPUT); + num_conf_bits = cur_pb->num_conf_bits; + if (0 < num_conf_bits) { + fprintf(fp, ",\n"); + } + dump_verilog_sram_ports(fp, sram_verilog_orgz_info, + stamped_sram_cnt, stamped_sram_cnt + num_conf_bits - 1, + VERILOG_PORT_INPUT); + /* Finish with local vdd and gnd */ + fprintf(fp, ");\n"); + /* Definition ends*/ + + /* Quote all child pb_types */ + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + /* Each child may exist multiple times in the hierarchy*/ + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* we should make sure this placement index == child_pb_type[jpb]*/ + assert(jpb == cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb].placement_index); + /* mode[]_[] + */ + /* Find the pb_type_children mode */ + if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { + child_mode_index = cur_pb->child_pbs[ipb][jpb].mode; + child_pb_num_reserved_conf_bits = cur_pb->child_pbs[ipb][jpb].num_reserved_conf_bits; + child_pb_num_conf_bits = cur_pb->child_pbs[ipb][jpb].num_conf_bits; + child_pb_num_inpads = cur_pb->child_pbs[ipb][jpb].num_inpads; + child_pb_num_outpads = cur_pb->child_pbs[ipb][jpb].num_outpads; + child_pb_num_iopads = cur_pb->child_pbs[ipb][jpb].num_iopads; + } else /*if (NULL == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model)*/ { /* Find the idle_mode_index, if this is not a leaf node */ + child_mode_index = find_pb_type_idle_mode_index(cur_pb_type->modes[mode_index].pb_type_children[ipb]); + child_pb_num_reserved_conf_bits = cur_pb_type->modes[mode_index].pb_type_children[ipb].default_mode_num_reserved_conf_bits; + child_pb_num_conf_bits = cur_pb_type->modes[mode_index].pb_type_children[ipb].default_mode_num_conf_bits; + child_pb_num_iopads = cur_pb_type->modes[mode_index].pb_type_children[ipb].default_mode_num_iopads; + } + /* If the pb_type_children is a leaf node, we don't use the mode to name it, + * else we can use the mode to name it + */ + if (NULL == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model) { /* Not a leaf node*/ + fprintf(fp, "%s_%s_%d__mode_%s_ ", + subckt_name, cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb, + cur_pb_type->modes[mode_index].pb_type_children[ipb].modes[child_mode_index].name); + } else { /* Have a verilog model definition, this is a leaf node*/ + fprintf(fp, "%s_%s_%d_ ", + subckt_name, cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); + } + fprintf(fp, "%s_%d_ (", cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); + fprintf(fp, "\n"); + /* dump global ports */ + /* If the child node is a primitive, we only dump global ports belonging to this primitive */ + if (NULL == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + fprintf(fp, ",\n"); + } + } else { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, + cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model, + FALSE, TRUE)) { + fprintf(fp, ",\n"); + } + } + /* Pass the SPICE mode prefix on, + * mode[]_[] + */ + /* Simplify the prefix! Make the SPICE netlist readable*/ + child_pb_type_prefix = (char*)my_malloc(sizeof(char)* + (strlen(cur_pb_type->modes[mode_index].pb_type_children[ipb].name) + 1 + + strlen(my_itoa(jpb)) + 1 + 1)); + sprintf(child_pb_type_prefix, "%s_%d_", + cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); + /* Print inputs, outputs, inouts, clocks + * NO SRAMs !!! They have already been fixed in the bottom level + */ + dump_verilog_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb]), FALSE, FALSE); + /* Print I/O pads */ + dump_verilog_grid_common_port(fp, iopad_verilog_model, + gio_inout_prefix, + stamped_iopad_cnt, + stamped_iopad_cnt + child_pb_num_iopads - 1, + VERILOG_PORT_CONKT); + /* update stamped outpad counter */ + stamped_iopad_cnt += child_pb_num_iopads; + /* Print configuration ports */ + if (0 < child_pb_num_reserved_conf_bits) { + fprintf(fp, ",\n"); + } + dump_verilog_reserved_sram_ports(fp, sram_verilog_orgz_info, + 0, child_pb_num_reserved_conf_bits - 1, + VERILOG_PORT_CONKT); + if (0 < child_pb_num_conf_bits) { + fprintf(fp, ",\n"); + } + dump_verilog_sram_ports(fp, sram_verilog_orgz_info, + stamped_sram_cnt, + stamped_sram_cnt + child_pb_num_conf_bits - 1, + VERILOG_PORT_CONKT); + /* update stamped sram counter */ + stamped_sram_cnt += child_pb_num_conf_bits; + + fprintf(fp, "); \n"); /* Local vdd and gnd*/ + my_free(child_pb_type_prefix); + } + } + /* Print interconnections, set is_idle as TRUE*/ + dump_verilog_pb_graph_interc(fp, subckt_name, cur_pb_graph_node, cur_pb, mode_index, 0); + /* Check each pins of pb_graph_node */ + /* Check and update stamped_sram_cnt */ + assert(!(stamped_sram_cnt > (stamped_sram_lsb + num_conf_bits))); + stamped_sram_cnt = stamped_sram_lsb + num_conf_bits; + /* End the subckt */ + fprintf(fp, "endmodule\n"); + /* Comment lines */ + fprintf(fp, "//----- END Programmable logic block Verilog module %s -----\n\n", subckt_name); + + /* Free subckt name*/ + my_free(subckt_name); + + assert(stamped_sram_cnt == get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info)); + assert(stamped_iopad_cnt == iopad_verilog_model->cnt); + + return; +} + +/* Print physical mode of pb_types and configure it to the idle pb_types recursively + * search the idle_mode until we reach the leaf node + */ +void dump_verilog_phy_pb_graph_node_rec(FILE* fp, + char* subckt_prefix, + t_pb* cur_pb, + t_pb_graph_node* cur_pb_graph_node, + int pb_type_index) { + int mode_index, ipb, jpb, child_mode_index, is_idle; + t_pb_type* cur_pb_type = NULL; + t_pb* child_pb = NULL; + char* subckt_name = NULL; + char* formatted_subckt_prefix = format_verilog_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/ + char* pass_on_prefix = NULL; + char* child_pb_type_prefix = NULL; + char* subckt_port_prefix = NULL; + + int child_pb_num_reserved_conf_bits = 0; + int child_pb_num_conf_bits = 0; + int child_pb_num_inpads = 0; + int child_pb_num_outpads = 0; + int child_pb_num_iopads = 0; + + int num_reserved_conf_bits = 0; + int num_conf_bits = 0; + int stamped_sram_cnt = get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info); + int stamped_sram_lsb = get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info); + + int stamped_iopad_cnt = iopad_verilog_model->cnt; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check cur_pb_graph_node*/ + if (NULL == cur_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb_graph_node.\n", + __FILE__, __LINE__); + exit(1); + } + + cur_pb_type = cur_pb_graph_node->pb_type; + + is_idle = 1; + if (NULL != cur_pb) { + is_idle = 0; + } + + /* Recursively finish all the child pb_types*/ + if (NULL == cur_pb_type->spice_model) { + /* Find the mode that define_idle_mode*/ + mode_index = find_pb_type_physical_mode_index((*cur_pb_type)); + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* Pass the SPICE mode prefix on, + * mode[]_ + */ + pass_on_prefix = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(cur_pb_type->name) + 1 + + strlen(my_itoa(pb_type_index)) + 7 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1 + 1)); + sprintf(pass_on_prefix, "%s%s_%d__mode_%s__", + formatted_subckt_prefix, cur_pb_type->name, pb_type_index, cur_pb_type->modes[mode_index].name); + /* Recursive*/ + /* Refer to pack/output_clustering.c [LINE 392] */ + /* Find the child pb that is mapped, and the mapping info is not stored in the physical mode ! */ + child_pb = get_child_pb_for_phy_pb_graph_node(cur_pb, ipb, jpb); + dump_verilog_phy_pb_graph_node_rec(fp, pass_on_prefix, child_pb, + &(cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), jpb); + /* Free */ + my_free(pass_on_prefix); + } + } + } + + /* Check if this has defined a spice_model*/ + if (NULL != cur_pb_type->spice_model) { + switch (cur_pb_type->class_type) { + case LUT_CLASS: + /* Consider the num_pb, create all the subckts*/ + if (1 == is_idle) { + dump_verilog_pb_primitive_verilog_model(fp, formatted_subckt_prefix, + NULL, cur_pb_graph_node, pb_type_index, + cur_pb_type->spice_model, is_idle); /* last param means idle */ + } else { + child_pb = get_lut_child_pb(cur_pb, mode_index); + /* Special care for LUT !!! + * Mapped logical block information is stored in child_pbs + */ + dump_verilog_pb_primitive_verilog_model(fp, formatted_subckt_prefix, + child_pb, cur_pb_graph_node, pb_type_index, + cur_pb_type->spice_model, is_idle); /* last param means idle */ + } + case LATCH_CLASS: + assert(0 == cur_pb_type->num_modes); + /* Consider the num_pb, create all the subckts*/ + dump_verilog_pb_primitive_verilog_model(fp, formatted_subckt_prefix, + cur_pb, cur_pb_graph_node, pb_type_index, + cur_pb_type->spice_model, is_idle); /* last param means idle */ + break; + case UNKNOWN_CLASS: + case MEMORY_CLASS: + /* Consider the num_pb, create all the subckts*/ + dump_verilog_pb_primitive_verilog_model(fp, formatted_subckt_prefix, + cur_pb, cur_pb_graph_node, pb_type_index, + cur_pb_type->spice_model, is_idle); /* last param means idle */ + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Unknown class type of pb_type(%s)!\n", + __FILE__, __LINE__, cur_pb_type->name); + exit(1); + } + /* update the number of SRAM, I/O pads */ + /* update stamped iopad counter */ + stamped_iopad_cnt += cur_pb_type->physical_mode_num_iopads; + /* update stamped sram counter */ + stamped_sram_cnt += cur_pb_type->physical_mode_num_conf_bits; + /* Check */ + assert(stamped_sram_cnt == get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info)); + assert(stamped_iopad_cnt == iopad_verilog_model->cnt); + /* Finish for primitive node, return */ + return; + } + + /* Find the mode that define_idle_mode*/ + mode_index = find_pb_type_physical_mode_index((*cur_pb_type)); + /* Create a new subckt */ + /* mode[] + */ + subckt_name = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(cur_pb_type->name) + 1 + + strlen(my_itoa(pb_type_index)) + 7 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1)); + /* Definition*/ + sprintf(subckt_name, "%s%s_%d__mode_%s_", + formatted_subckt_prefix, cur_pb_type->name, pb_type_index, cur_pb_type->modes[mode_index].name); + /* Comment lines */ + fprintf(fp, "//----- Physical programmable logic block Verilog module %s -----\n", subckt_name); + fprintf(fp, "module %s (", subckt_name); + /* Inputs, outputs, inouts, clocks */ + subckt_port_prefix = (char*)my_malloc(sizeof(char)* + (5 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1)); + sprintf(subckt_port_prefix, "mode_%s_", cur_pb_type->modes[mode_index].name); + /* + dump_verilog_pb_type_ports(fp, subckt_name, 0, cur_pb_type); + */ + fprintf(fp, "\n"); + /* dump global ports */ + if(0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + fprintf(fp, ",\n"); + } + /* Simplify the port prefix, make SPICE netlist readable */ + dump_verilog_pb_type_ports(fp, subckt_port_prefix, 0, cur_pb_type, TRUE, FALSE); + /* Print Input Pad and Output Pad */ + dump_verilog_grid_common_port(fp, iopad_verilog_model, + gio_inout_prefix, + stamped_iopad_cnt, iopad_verilog_model->cnt - 1, + VERILOG_PORT_INPUT); + /* Print Configuration ports */ + /* sram_verilog_model->cnt should be updated because all the child pbs have been dumped + * stamped_sram_cnt remains the old sram_verilog_model->cnt before all the child pbs are dumped + * Note by far, sram_verilog_model->cnt could be smaller than num_conf_bits + * because the interconnection of current pb_type/pb has not yet dumped, which may contain + * a few configuration bits. + */ + num_reserved_conf_bits = cur_pb_type->physical_mode_num_reserved_conf_bits; + if (0 < num_reserved_conf_bits) { + fprintf(fp, ",\n"); + } + dump_verilog_reserved_sram_ports(fp, sram_verilog_orgz_info, + 0, num_reserved_conf_bits - 1, + VERILOG_PORT_INPUT); + num_conf_bits = cur_pb_type->physical_mode_num_conf_bits; + if (0 < num_conf_bits) { + fprintf(fp, ",\n"); + } + dump_verilog_sram_ports(fp, sram_verilog_orgz_info, + stamped_sram_cnt, stamped_sram_cnt + num_conf_bits - 1, + VERILOG_PORT_INPUT); + /* Finish with local vdd and gnd */ + fprintf(fp, ");\n"); + + /* Definition ends*/ + /* Quote all child pb_types */ + for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { + /* Each child may exist multiple times in the hierarchy*/ + for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* we should make sure this placement index == child_pb_type[jpb]*/ + assert(jpb == cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb].placement_index); + /* If the pb_type_children is a leaf node, we don't use the mode to name it, + * else we can use the mode to name it + */ + if (NULL == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model) { /* Not a leaf node*/ + child_mode_index = find_pb_type_idle_mode_index(cur_pb_type->modes[mode_index].pb_type_children[ipb]); + fprintf(fp, "%s_%s_%d__mode_%s_ ", + subckt_name, cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb, + cur_pb_type->modes[mode_index].pb_type_children[ipb].modes[child_mode_index].name); + } else { /* Have a verilog model definition, this is a leaf node*/ + fprintf(fp, "%s_%s_%d_ ", + subckt_name, cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); + } + /* Collect information of child pb_type */ + child_pb_num_reserved_conf_bits = cur_pb_type->modes[mode_index].pb_type_children[ipb].physical_mode_num_reserved_conf_bits; + child_pb_num_conf_bits = cur_pb_type->modes[mode_index].pb_type_children[ipb].physical_mode_num_conf_bits; + child_pb_num_iopads = cur_pb_type->modes[mode_index].pb_type_children[ipb].physical_mode_num_iopads; + + /* mode[]_[] + */ + fprintf(fp, "%s_%d_ (", cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); + fprintf(fp, "\n"); + /* dump global ports */ + /* If the child node is a primitive, we only dump global ports belonging to this primitive */ + if (NULL == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + fprintf(fp, ",\n"); + } + } else { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, + cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model, + FALSE, TRUE)) { + fprintf(fp, ",\n"); + } + } + /* Pass the SPICE mode prefix on, + * mode[]_[] + * [] + */ + /* Simplify the prefix! */ + child_pb_type_prefix = (char*)my_malloc(sizeof(char)* + (strlen(cur_pb_type->modes[mode_index].pb_type_children[ipb].name) + 1 + + strlen(my_itoa(jpb)) + 1 + 1)); + sprintf(child_pb_type_prefix, "%s_%d_", + cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); + /* Print inputs, outputs, inouts, clocks + * NO SRAMs !!! They have already been fixed in the bottom level + */ + dump_verilog_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb]),FALSE, FALSE); + /* Print I/O pads */ + dump_verilog_grid_common_port(fp, iopad_verilog_model, + gio_inout_prefix, + stamped_iopad_cnt, + stamped_iopad_cnt + child_pb_num_iopads - 1, + VERILOG_PORT_CONKT); + /* update stamped outpad counter */ + stamped_iopad_cnt += child_pb_num_iopads; + /* Print configuration ports */ + if (0 < child_pb_num_reserved_conf_bits) { + fprintf(fp, ",\n"); + } + dump_verilog_reserved_sram_ports(fp, sram_verilog_orgz_info, + 0, child_pb_num_reserved_conf_bits - 1, + VERILOG_PORT_CONKT); + if (0 < child_pb_num_conf_bits) { + fprintf(fp, ",\n"); + } + dump_verilog_sram_ports(fp, sram_verilog_orgz_info, + stamped_sram_cnt, + stamped_sram_cnt + child_pb_num_conf_bits - 1, + VERILOG_PORT_CONKT); + /* update stamped sram counter */ + stamped_sram_cnt += child_pb_num_conf_bits; + fprintf(fp, ");\n"); /* Local vdd and gnd*/ + my_free(child_pb_type_prefix); + } + } + /* Print interconnections, set is_idle as TRUE*/ + dump_verilog_pb_graph_interc(fp, subckt_name, cur_pb_graph_node, cur_pb, mode_index, is_idle); + /* Check each pins of pb_graph_node */ + /* Check and update stamped_sram_cnt */ + assert(!(stamped_sram_cnt > (stamped_sram_lsb + num_conf_bits))); + stamped_sram_cnt = stamped_sram_lsb + num_conf_bits; + /* End the subckt */ + fprintf(fp, "endmodule\n"); + /* Comment lines */ + fprintf(fp, "//----- END Idle programmable logic block Verilog module %s -----\n\n", subckt_name); + /* Free subckt name*/ + my_free(subckt_name); + + assert(stamped_sram_cnt == get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info)); + assert(stamped_iopad_cnt == iopad_verilog_model->cnt); + + return; +} + +/* Print the SPICE netlist of a block that has been mapped */ +void dump_verilog_block(FILE* fp, + char* subckt_name, + int x, + int y, + int z, + t_type_ptr type_descriptor, + t_block* mapped_block) { + t_pb* top_pb = NULL; + t_pb_graph_node* top_pb_graph_node = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* check */ + assert(x == mapped_block->x); + assert(y == mapped_block->y); + assert(type_descriptor == mapped_block->type); + assert(NULL != type_descriptor); + + /* Print SPICE netlist according to the hierachy of type descriptor recursively*/ + /* Go for the pb_types*/ + top_pb_graph_node = type_descriptor->pb_graph_head; + assert(NULL != top_pb_graph_node); + top_pb = mapped_block->pb; + assert(NULL != top_pb); + + /* Recursively find all mode and print netlist*/ + /* IMPORTANT: type_descriptor just say we have a block that in global view, how it connects to global routing arch. + * Inside the type_descripor, there is a top_pb_graph_node(pb_graph_head), describe the top pb_type defined. + * The index of such top pb_type is always 0. + */ + dump_verilog_pb_graph_node_rec(fp, subckt_name, top_pb, top_pb_graph_node, z); + + return; +} + + +/* Print an idle logic block + * Find the idle_mode in arch files, + * And print the verilog netlist into file + */ +void dump_verilog_idle_block(FILE* fp, + char* subckt_name, + int x, + int y, + int z, + t_type_ptr type_descriptor) { + t_pb_graph_node* top_pb_graph_node = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Ensure we have a valid type_descriptor*/ + assert(NULL != type_descriptor); + + /* Go for the pb_types*/ + top_pb_graph_node = type_descriptor->pb_graph_head; + assert(NULL != top_pb_graph_node); + + /* Recursively find all idle mode and print netlist*/ + dump_verilog_idle_pb_graph_node_rec(fp, subckt_name, top_pb_graph_node, z); + + return; +} + +/* Print an physical logic block + * Find the physical_mode in arch files, + * And print the verilog netlist into file + */ +void dump_verilog_physical_block(FILE* fp, + char* subckt_name, + int x, + int y, + int z, + t_type_ptr type_descriptor) { + t_pb_graph_node* top_pb_graph_node = NULL; + t_block* mapped_block = NULL; + t_pb* top_pb = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Ensure we have a valid type_descriptor*/ + assert(NULL != type_descriptor); + + /* Go for the pb_types*/ + top_pb_graph_node = type_descriptor->pb_graph_head; + assert(NULL != top_pb_graph_node); + + /* Check in all the mapped blocks(clustered logic block), there is a match x,y,z*/ + mapped_block = search_mapped_block(x, y, z); + if (NULL != mapped_block) { + top_pb = mapped_block->pb; + assert(NULL != top_pb); + } + + /* Recursively find all idle mode and print netlist*/ + dump_verilog_phy_pb_graph_node_rec(fp, subckt_name, top_pb, top_pb_graph_node, z); + + return; +} + +/* We print all the pins of a type descriptor in the following sequence + * TOP, RIGHT, BOTTOM, LEFT + */ +void dump_verilog_grid_pins(FILE* fp, + int x, + int y, + int top_level, + boolean dump_port_type, + boolean dump_last_comma) { + int iheight, side, ipin, class_id; + int side_pin_index; + t_type_ptr type_descriptor = grid[x][y].type; + int capacity = grid[x][y].type->capacity; + int num_dumped_port = 0; + int first_dump = 1; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + assert(NULL != type_descriptor); + assert(0 < capacity); + + for (side = 0; side < 4; side++) { + /* Count the number of pins */ + side_pin_index = 0; + //for (iz = 0; iz < capacity; iz++) { + for (iheight = 0; iheight < type_descriptor->height; iheight++) { + for (ipin = 0; ipin < type_descriptor->num_pins; ipin++) { + if (1 == type_descriptor->pinloc[iheight][side][ipin]) { + /* Add comma if needed */ + if (1 == first_dump) { + first_dump = 0; + } else { + if (TRUE == dump_port_type) { + fprintf(fp, ",\n"); + } else { + fprintf(fp, ",\n"); + } + } + if (TRUE == dump_port_type) { + /* Determine this pin is an input or output */ + class_id = type_descriptor->pin_class[ipin]; + switch (type_descriptor->class_inf[class_id].type) { + case RECEIVER: + fprintf(fp, "input "); + break; + case DRIVER: + fprintf(fp, "output "); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid pin_class_type!\n", + __FILE__, __LINE__); + exit(1); + } + } + /* This pin appear at this side! */ + if (1 == top_level) { + fprintf(fp, " grid_%d__%d__pin_%d__%d__%d_", x, y, + iheight, side, ipin); + } else { + fprintf(fp, " %s_height_%d__pin_%d_", + convert_side_index_to_string(side), iheight, ipin); + } + /* Update counter */ + num_dumped_port++; + side_pin_index++; + } + } + } + //} + } + + if ((0 < num_dumped_port)&&(TRUE == dump_last_comma)) { + if (TRUE == dump_port_type) { + fprintf(fp, ",\n"); + } else { + fprintf(fp, ",\n"); + } + } + + return; +} + +/* Special for I/O grid, we need only part of the ports + * i.e., grid[0][0..ny] only need the right side ports. + */ +/* We print all the pins of a type descriptor in the following sequence + * TOP, RIGHT, BOTTOM, LEFT + */ +void dump_verilog_io_grid_pins(FILE* fp, + int x, int y, + int top_level, + boolean dump_port_type, + boolean dump_last_comma) { + int iheight, side, ipin; + int side_pin_index; + t_type_ptr type_descriptor = grid[x][y].type; + int capacity = grid[x][y].type->capacity; + int class_id = -1; + int num_dumped_port = 0; + int first_dump = 1; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + assert(NULL != type_descriptor); + assert(0 < capacity); + /* Make sure this is IO */ + assert(IO_TYPE == type_descriptor); + + /* identify the location of IO grid and + * decide which side of ports we need + */ + side = determine_io_grid_side(x,y); + + /* Count the number of pins */ + side_pin_index = 0; + //for (iz = 0; iz < capacity; iz++) { + for (iheight = 0; iheight < type_descriptor->height; iheight++) { + for (ipin = 0; ipin < type_descriptor->num_pins; ipin++) { + if (1 == type_descriptor->pinloc[iheight][side][ipin]) { + /* Add comma if needed */ + if (1 == first_dump) { + first_dump = 0; + } else { + if (TRUE == dump_port_type) { + fprintf(fp, ",\n"); + } else { + fprintf(fp, ",\n"); + } + } + /* Determine this pin is an input or output */ + if (TRUE == dump_port_type) { + class_id = type_descriptor->pin_class[ipin]; + switch (type_descriptor->class_inf[class_id].type) { + case RECEIVER: + fprintf(fp, "input "); + break; + case DRIVER: + fprintf(fp, "output "); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid pin_class_type!\n", + __FILE__, __LINE__); + exit(1); + } + } + /* This pin appear at this side! */ + if (1 == top_level) { + fprintf(fp, " grid_%d__%d__pin_%d__%d__%d_", x, y, + iheight, side, ipin); + } else { + fprintf(fp, " %s_height_%d__pin_%d_", + convert_side_index_to_string(side), iheight, ipin); + } + /* Update counter */ + num_dumped_port++; + side_pin_index++; + } + } + } + //} + + if ((0 < num_dumped_port)&&(TRUE == dump_last_comma)) { + if (TRUE == dump_port_type) { + fprintf(fp, ",\n"); + } else { + fprintf(fp, ",\n"); + } + } + + return; +} + +char* verilog_get_grid_block_subckt_name(int x, int y, int z, + char* subckt_prefix, + t_block* mapped_block) { + char* ret = NULL; + int imode; + t_type_ptr type_descriptor = NULL; + char* formatted_subckt_prefix = format_verilog_node_prefix(subckt_prefix); + int num_idle_mode = 0; + + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + + type_descriptor = grid[x][y].type; + assert(NULL != type_descriptor); + + if (NULL == mapped_block) { + /* This a NULL logic block... Find the idle mode*/ + for (imode = 0; imode < type_descriptor->pb_type->num_modes; imode++) { + if (1 == type_descriptor->pb_type->modes[imode].define_idle_mode) { + num_idle_mode++; + } + } + assert(1 == num_idle_mode); + for (imode = 0; imode < type_descriptor->pb_type->num_modes; imode++) { + if (1 == type_descriptor->pb_type->modes[imode].define_idle_mode) { + ret = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(type_descriptor->name) + 1 + + strlen(my_itoa(z)) + 7 + strlen(type_descriptor->pb_type->modes[imode].name) + 1 + 1)); + sprintf(ret, "%s%s_%d__mode_%s_", formatted_subckt_prefix, + type_descriptor->name, z, type_descriptor->pb_type->modes[imode].name); + break; + } + } + } else { + /* This is a logic block with specific configurations*/ + assert(NULL != mapped_block->pb); + imode = mapped_block->pb->mode; + ret = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(type_descriptor->name) + 1 + + strlen(my_itoa(z)) + 7 + strlen(type_descriptor->pb_type->modes[imode].name) + 1 + 1)); + sprintf(ret, "%s%s_%d__mode_%s_", formatted_subckt_prefix, + type_descriptor->name, z, type_descriptor->pb_type->modes[imode].name); + } + + return ret; +} + +/* Physical mode subckt name */ +char* verilog_get_grid_phy_block_subckt_name(int x, int y, int z, + char* subckt_prefix, + t_block* mapped_block) { + char* ret = NULL; + int imode; + t_type_ptr type_descriptor = NULL; + char* formatted_subckt_prefix = format_verilog_node_prefix(subckt_prefix); + int num_physical_mode = 0; + + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + + type_descriptor = grid[x][y].type; + assert(NULL != type_descriptor); + + if (NULL == mapped_block) { + /* This a NULL logic block... Find the idle mode*/ + for (imode = 0; imode < type_descriptor->pb_type->num_modes; imode++) { + if (1 == type_descriptor->pb_type->modes[imode].define_physical_mode) { + num_physical_mode++; + } + } + assert(1 == num_physical_mode); + for (imode = 0; imode < type_descriptor->pb_type->num_modes; imode++) { + if (1 == type_descriptor->pb_type->modes[imode].define_physical_mode) { + ret = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(type_descriptor->name) + 1 + + strlen(my_itoa(z)) + 7 + strlen(type_descriptor->pb_type->modes[imode].name) + 1 + 1)); + sprintf(ret, "%s%s_%d__mode_%s_", formatted_subckt_prefix, + type_descriptor->name, z, type_descriptor->pb_type->modes[imode].name); + break; + } + } + } else { + /* This is a logic block with specific configurations*/ + assert(NULL != mapped_block->pb); + imode = mapped_block->pb->mode; + ret = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(type_descriptor->name) + 1 + + strlen(my_itoa(z)) + 7 + strlen(type_descriptor->pb_type->modes[imode].name) + 1 + 1)); + sprintf(ret, "%s%s_%d__mode_%s_", formatted_subckt_prefix, + type_descriptor->name, z, type_descriptor->pb_type->modes[imode].name); + } + + return ret; +} + + +/* Print the pins of grid subblocks */ +void dump_verilog_grid_block_subckt_pins(FILE* fp, + int z, + t_type_ptr type_descriptor) { + int iport, ipin, side, dump_pin_cnt; + int grid_pin_index, pin_height, side_pin_index; + t_pb_graph_node* top_pb_graph_node = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert(NULL != type_descriptor); + top_pb_graph_node = type_descriptor->pb_graph_head; + assert(NULL != top_pb_graph_node); + + dump_pin_cnt = 0; + + for (iport = 0; iport < top_pb_graph_node->num_input_ports; iport++) { + for (ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport]; ipin++) { + grid_pin_index = top_pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster + + z * type_descriptor->num_pins / type_descriptor->capacity; + /* num_pins/capacity = the number of pins that each type_descriptor has. + * Capacity defines the number of type_descriptors in each grid + * so the pin index at grid level = pin_index_in_type_descriptor + * + type_descriptor_index_in_capacity * num_pins_per_type_descriptor + */ + pin_height = type_descriptor->pin_height[grid_pin_index]; + for (side = 0; side < 4; side++) { + if (1 == type_descriptor->pinloc[pin_height][side][grid_pin_index]) { + /* This pin appear at this side! */ + if (0 < dump_pin_cnt) { + fprintf(fp, ",\n"); + } + fprintf(fp, "%s_height_%d__pin_%d_ ", + convert_side_index_to_string(side), pin_height, grid_pin_index); + dump_pin_cnt++; + side_pin_index++; + } + } + } + } + + for (iport = 0; iport < top_pb_graph_node->num_output_ports; iport++) { + for (ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport]; ipin++) { + grid_pin_index = top_pb_graph_node->output_pins[iport][ipin].pin_count_in_cluster + + z * type_descriptor->num_pins / type_descriptor->capacity; + /* num_pins/capacity = the number of pins that each type_descriptor has. + * Capacity defines the number of type_descriptors in each grid + * so the pin index at grid level = pin_index_in_type_descriptor + * + type_descriptor_index_in_capacity * num_pins_per_type_descriptor + */ + pin_height = type_descriptor->pin_height[grid_pin_index]; + for (side = 0; side < 4; side++) { + if (1 == type_descriptor->pinloc[pin_height][side][grid_pin_index]) { + /* This pin appear at this side! */ + if (0 < dump_pin_cnt) { + fprintf(fp, ",\n"); + } + fprintf(fp, "%s_height_%d__pin_%d_ ", + convert_side_index_to_string(side), pin_height, grid_pin_index); + dump_pin_cnt++; + side_pin_index++; + } + } + } + } + + for (iport = 0; iport < top_pb_graph_node->num_clock_ports; iport++) { + for (ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport]; ipin++) { + grid_pin_index = top_pb_graph_node->clock_pins[iport][ipin].pin_count_in_cluster + + z * type_descriptor->num_pins / type_descriptor->capacity; + /* num_pins/capacity = the number of pins that each type_descriptor has. + * Capacity defines the number of type_descriptors in each grid + * so the pin index at grid level = pin_index_in_type_descriptor + * + type_descriptor_index_in_capacity * num_pins_per_type_descriptor + */ + pin_height = type_descriptor->pin_height[grid_pin_index]; + for (side = 0; side < 4; side++) { + if (1 == type_descriptor->pinloc[pin_height][side][grid_pin_index]) { + /* This pin appear at this side! */ + if (0 < dump_pin_cnt) { + fprintf(fp, ",\n"); + } + fprintf(fp, "%s_height_%d__pin_%d_ ", + convert_side_index_to_string(side), pin_height, grid_pin_index); + dump_pin_cnt++; + side_pin_index++; + } + } + } + } + + return; +} + + +/* Print the pins of grid subblocks */ +void dump_verilog_io_grid_block_subckt_pins(FILE* fp, + int x, + int y, + int z, + t_type_ptr type_descriptor) { + int iport, ipin, side, dump_pin_cnt; + int grid_pin_index, pin_height, side_pin_index; + t_pb_graph_node* top_pb_graph_node = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert(NULL != type_descriptor); + top_pb_graph_node = type_descriptor->pb_graph_head; + assert(NULL != top_pb_graph_node); + + /* Make sure this is IO */ + assert(IO_TYPE == type_descriptor); + + /* identify the location of IO grid and + * decide which side of ports we need + */ + if (0 == x) { + /* Left side */ + assert((0 < y)&&(y < (ny + 1))); + /* Print Right side ports*/ + side = RIGHT; + } else if ((nx + 1) == x) { + /* Right side */ + assert((0 < y)&&(y < (ny + 1))); + /* Print Left side ports*/ + side = LEFT; + } else if (0 == y) { + /* Bottom Side */ + assert((0 < x)&&(x < (nx + 1))); + /* Print TOP side ports */ + side = TOP; + } else if ((ny + 1) == y) { + /* TOP Side */ + assert((0 < x)&&(x < (nx + 1))); + /* Print BOTTOM side ports */ + side = BOTTOM; + } else { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid co-ordinators(x=%d, y=%d) for I/O grid!\n", + __FILE__, __LINE__, x, y); + exit(1); + } + + dump_pin_cnt = 0; + + for (iport = 0; iport < top_pb_graph_node->num_input_ports; iport++) { + for (ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport]; ipin++) { + grid_pin_index = top_pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster + + z * type_descriptor->num_pins / type_descriptor->capacity; + /* num_pins/capacity = the number of pins that each type_descriptor has. + * Capacity defines the number of type_descriptors in each grid + * so the pin index at grid level = pin_index_in_type_descriptor + * + type_descriptor_index_in_capacity * num_pins_per_type_descriptor + */ + pin_height = type_descriptor->pin_height[grid_pin_index]; + if (1 == type_descriptor->pinloc[pin_height][side][grid_pin_index]) { + /* This pin appear at this side! */ + if (0 < dump_pin_cnt) { + fprintf(fp, ",\n"); + } + fprintf(fp, "%s_height_%d__pin_%d_", + convert_side_index_to_string(side), pin_height, grid_pin_index); + side_pin_index++; + dump_pin_cnt++; + } + } + } + + for (iport = 0; iport < top_pb_graph_node->num_output_ports; iport++) { + for (ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport]; ipin++) { + grid_pin_index = top_pb_graph_node->output_pins[iport][ipin].pin_count_in_cluster + + z * type_descriptor->num_pins / type_descriptor->capacity; + /* num_pins/capacity = the number of pins that each type_descriptor has. + * Capacity defines the number of type_descriptors in each grid + * so the pin index at grid level = pin_index_in_type_descriptor + * + type_descriptor_index_in_capacity * num_pins_per_type_descriptor + */ + pin_height = type_descriptor->pin_height[grid_pin_index]; + if (1 == type_descriptor->pinloc[pin_height][side][grid_pin_index]) { + /* This pin appear at this side! */ + if (0 < dump_pin_cnt) { + fprintf(fp, ",\n"); + } + fprintf(fp, "%s_height_%d__pin_%d_", + convert_side_index_to_string(side), pin_height, grid_pin_index); + side_pin_index++; + dump_pin_cnt++; + } + } + } + + for (iport = 0; iport < top_pb_graph_node->num_clock_ports; iport++) { + for (ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport]; ipin++) { + grid_pin_index = top_pb_graph_node->clock_pins[iport][ipin].pin_count_in_cluster + + z * type_descriptor->num_pins / type_descriptor->capacity; + /* num_pins/capacity = the number of pins that each type_descriptor has. + * Capacity defines the number of type_descriptors in each grid + * so the pin index at grid level = pin_index_in_type_descriptor + * + type_descriptor_index_in_capacity * num_pins_per_type_descriptor + */ + pin_height = type_descriptor->pin_height[grid_pin_index]; + if (1 == type_descriptor->pinloc[pin_height][side][grid_pin_index]) { + /* This pin appear at this side! */ + if (0 < dump_pin_cnt) { + fprintf(fp, ",\n"); + } + fprintf(fp, "%s_height_%d__pin_%d_", + convert_side_index_to_string(side), pin_height, grid_pin_index); + side_pin_index++; + dump_pin_cnt++; + } + } + } + + return; +} + +/* Print the SPICE netlist for a grid blocks */ +void dump_verilog_grid_blocks(FILE* fp, + int ix, + int iy, + t_arch* arch) { + int subckt_name_str_len = 0; + char* subckt_name = NULL; + t_block* mapped_block = NULL; + int iz; + int cur_block_index = 0; + int capacity; + int cur_num_mem_bit; + int num_reserved_conf_bits; + int temp_reserved_conf_bits_msb; + int temp_conf_bits_lsb, temp_conf_bits_msb; + int temp_inpad_lsb, temp_inpad_msb; + int temp_outpad_lsb, temp_outpad_msb; + int temp_iopad_lsb, temp_iopad_msb; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert((!(0 > ix))&&(!(ix > (nx + 1)))); + assert((!(0 > iy))&&(!(iy > (ny + 1)))); + + /* Make a snapshot for the number of memory bits */ + cur_num_mem_bit = get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info); + + /* Update the grid_index_low for each spice_model */ + update_spice_models_grid_index_low(ix, iy, arch->spice->num_spice_model, arch->spice->spice_models); + + /* generate_grid_subckt, type_descriptor of each grid defines the capacity, + * for example, each grid may contains more than one top-level pb_types, such as I/O + */ + if ((NULL == grid[ix][iy].type)||(0 != grid[ix][iy].offset)) { + /* Update the grid_index_high for each spice_model */ + update_spice_models_grid_index_high(ix, iy, arch->spice->num_spice_model, arch->spice->spice_models); + return; + } + capacity= grid[ix][iy].type->capacity; + assert(0 < capacity); + + /* Make the sub-circuit name*/ + /* Name format: grid[][]_*/ + subckt_name_str_len = 4 + 1 + strlen(my_itoa(ix)) + 2 + + strlen(my_itoa(iy)) + 1 + 1 + 1; /* Plus '0' at the end of string*/ + subckt_name = (char*)my_malloc(sizeof(char)*subckt_name_str_len); + sprintf(subckt_name, "grid_%d__%d__", ix, iy); + + cur_block_index = 0; + /* check capacity and if this has been mapped */ + for (iz = 0; iz < capacity; iz++) { + /* Check in all the blocks(clustered logic block), there is a match x,y,z*/ + mapped_block = search_mapped_block(ix, iy, iz); + /* Comments: Grid [x][y]*/ + fprintf(fp, "//----- Grid[%d][%d] type_descriptor: %s[%d] -----\n", ix, iy, grid[ix][iy].type->name, iz); + if (NULL == mapped_block) { + /* Print a NULL logic block...*/ + dump_verilog_idle_block(fp, subckt_name, ix, iy, iz, grid[ix][iy].type); + } else { + if (iz == mapped_block->z) { + // assert(mapped_block == &(block[grid[ix][iy].blocks[cur_block_index]])); + cur_block_index++; + } + /* Print a logic block with specific configurations*/ + dump_verilog_block(fp, subckt_name, ix, iy, iz, grid[ix][iy].type, mapped_block); + } + fprintf(fp, "//----- END -----\n\n"); + } + assert(cur_block_index == grid[ix][iy].usage); + + /* Update the grid_index_high for each spice_model */ + update_spice_models_grid_index_high(ix, iy, arch->spice->num_spice_model, arch->spice->spice_models); + + /* Print grid[x][y] top-level module */ + fprintf(fp, "//----- Grid[%d][%d], Capactity: %d -----\n", ix, iy, capacity); + fprintf(fp, "//----- Top Protocol -----\n"); + /* Definition */ + fprintf(fp, "module grid_%d__%d_( \n", ix, iy); + fprintf(fp, "\n"); + /* dump global ports */ + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + fprintf(fp, ",\n"); + } + + /* Pins */ + /* Special Care for I/O grid */ + if (IO_TYPE == grid[ix][iy].type) { + dump_verilog_io_grid_pins(fp, ix, iy, 0, TRUE, FALSE); + } else { + dump_verilog_grid_pins(fp, ix, iy, 0, TRUE, FALSE); + } + + /* IO PAD */ + dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix, + iopad_verilog_model->grid_index_low[ix][iy], + iopad_verilog_model->grid_index_high[ix][iy] - 1, + VERILOG_PORT_INPUT); + + /* Print configuration ports */ + /* Reserved configuration ports */ + if (NULL == mapped_block) { + num_reserved_conf_bits = grid[ix][iy].type->pb_type->default_mode_num_reserved_conf_bits; + } else { + num_reserved_conf_bits = mapped_block->pb->num_reserved_conf_bits; + } + if (0 < num_reserved_conf_bits) { + fprintf(fp, ",\n"); + } + dump_verilog_reserved_sram_ports(fp, sram_verilog_orgz_info, + 0, + num_reserved_conf_bits - 1, + VERILOG_PORT_INPUT); + /* Normal configuration ports */ + if (0 < (get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info) - cur_num_mem_bit)) { + fprintf(fp, ",\n"); + dump_verilog_sram_ports(fp, sram_verilog_orgz_info, + cur_num_mem_bit, + get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info) - 1, + VERILOG_PORT_INPUT); + } + fprintf(fp, ");\n"); + + /* Record LSB and MSB of reserved_conf_bits and regular conf_bits in sram_orgz_info */ + sram_verilog_orgz_info->grid_reserved_conf_bits[ix][iy] = num_reserved_conf_bits; + sram_verilog_orgz_info->grid_conf_bits_lsb[ix][iy] = cur_num_mem_bit; + sram_verilog_orgz_info->grid_conf_bits_msb[ix][iy] = get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info); + + /* Initialize temporary counter */ + temp_conf_bits_lsb = cur_num_mem_bit; + temp_iopad_lsb = iopad_verilog_model->grid_index_low[ix][iy]; + + /* Quote all the sub blocks*/ + for (iz = 0; iz < capacity; iz++) { + /* Check in all the blocks(clustered logic block), there is a match x,y,z*/ + mapped_block = search_mapped_block(ix, iy, iz); + /* Local Vdd and Gnd, subckt name*/ + fprintf(fp, "%s ", verilog_get_grid_block_subckt_name(ix, iy, iz, subckt_name, mapped_block)); + fprintf(fp, " grid_%d__%d__%d_ (", ix, iy, iz); + fprintf(fp, "\n"); + /* dump global ports */ + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + fprintf(fp, ",\n"); + } + /* Print all the pins */ + /* Special Care for I/O grid */ + if (IO_TYPE == grid[ix][iy].type) { + dump_verilog_io_grid_block_subckt_pins(fp, ix, iy, iz, grid[ix][iy].type); + } else { + dump_verilog_grid_block_subckt_pins(fp, iz, grid[ix][iy].type); + } + /* Print configuration ports */ + if (NULL == mapped_block) { + temp_reserved_conf_bits_msb = grid[ix][iy].type->pb_type->default_mode_num_reserved_conf_bits; + temp_conf_bits_msb = temp_conf_bits_lsb + grid[ix][iy].type->pb_type->default_mode_num_conf_bits; + temp_iopad_msb = temp_iopad_lsb + grid[ix][iy].type->pb_type->default_mode_num_iopads; + } else { + temp_reserved_conf_bits_msb = mapped_block->pb->num_reserved_conf_bits; + temp_conf_bits_msb = temp_conf_bits_lsb + mapped_block->pb->num_conf_bits; + temp_iopad_msb = temp_iopad_lsb + mapped_block->pb->num_iopads; + } + /* Print Input Pad and Output Pad */ + fprintf(fp, "\n//---- IOPAD ----\n"); + dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix, + temp_iopad_lsb, + temp_iopad_msb - 1, + VERILOG_PORT_CONKT); + /* Reserved configuration ports */ + if (0 < temp_reserved_conf_bits_msb) { + fprintf(fp, ",\n"); + dump_verilog_reserved_sram_ports(fp, sram_verilog_orgz_info, + 0, temp_reserved_conf_bits_msb - 1, + VERILOG_PORT_CONKT); + } + /* Normal configuration ports */ + assert(!(0 > temp_conf_bits_msb - temp_conf_bits_lsb)); + if (0 < (temp_conf_bits_msb - temp_conf_bits_lsb)) { + fprintf(fp, ",\n"); + fprintf(fp, "//---- SRAM ----\n"); + dump_verilog_sram_ports(fp, sram_verilog_orgz_info, + temp_conf_bits_lsb, temp_conf_bits_msb - 1, + VERILOG_PORT_CONKT); + } + /* Update temp_sram_lsb */ + temp_conf_bits_lsb = temp_conf_bits_msb; + temp_inpad_lsb = temp_inpad_msb; + temp_outpad_lsb = temp_outpad_msb; + fprintf(fp, ");\n"); + } + + fprintf(fp, "endmodule\n"); + fprintf(fp, "//----- END Top Protocol -----\n"); + fprintf(fp, "//----- END Grid[%d][%d], Capactity: %d -----\n\n", ix, iy, capacity); + + assert(temp_conf_bits_msb == get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info)); + + /* Free */ + my_free(subckt_name); + + return; +} + +/* Print the SPICE netlist for a I/O grid blocks */ +void dump_verilog_physical_grid_blocks(FILE* fp, + int ix, + int iy, + t_arch* arch) { + int subckt_name_str_len = 0; + char* subckt_name = NULL; + int iz; + int capacity; + int cur_num_mem_bit; + int temp_reserved_conf_bits_msb; + int temp_conf_bits_lsb, temp_conf_bits_msb; + int temp_inpad_lsb, temp_inpad_msb; + int temp_outpad_lsb, temp_outpad_msb; + int temp_iopad_lsb, temp_iopad_msb; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert((!(0 > ix))&&(!(ix > (nx + 1)))); + assert((!(0 > iy))&&(!(iy > (ny + 1)))); + + /* Make a snapshot for the number of memory bits */ + cur_num_mem_bit = get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info); + + /* Update the grid_index_low for each spice_model */ + update_spice_models_grid_index_low(ix, iy, arch->spice->num_spice_model, arch->spice->spice_models); + + /* generate_grid_subckt, type_descriptor of each grid defines the capacity, + * for example, each grid may contains more than one top-level pb_types, such as I/O + */ + if ((NULL == grid[ix][iy].type)||(0 != grid[ix][iy].offset)) { + /* Update the grid_index_high for each spice_model */ + update_spice_models_grid_index_high(ix, iy, arch->spice->num_spice_model, arch->spice->spice_models); + return; + } + capacity= grid[ix][iy].type->capacity; + assert(0 < capacity); + + /* Make the sub-circuit name*/ + /* Name format: grid[][]_*/ + subckt_name_str_len = 4 + 1 + strlen(my_itoa(ix)) + 2 + + strlen(my_itoa(iy)) + 1 + 1 + 1; /* Plus '0' at the end of string*/ + subckt_name = (char*)my_malloc(sizeof(char)*subckt_name_str_len); + sprintf(subckt_name, "grid_%d__%d__", ix, iy); + + /* check capacity and if this has been mapped */ + for (iz = 0; iz < capacity; iz++) { + /* Comments: Grid [x][y]*/ + fprintf(fp, "//----- Grid[%d][%d] type_descriptor: %s[%d] -----\n", ix, iy, grid[ix][iy].type->name, iz); + /* Print a NULL logic block...*/ + dump_verilog_physical_block(fp, subckt_name, ix, iy, iz, grid[ix][iy].type); + fprintf(fp, "//----- END -----\n\n"); + } + + /* Update the grid_index_high for each spice_model */ + update_spice_models_grid_index_high(ix, iy, arch->spice->num_spice_model, arch->spice->spice_models); + + /* Print grid[x][y] top-level module */ + fprintf(fp, "//----- Grid[%d][%d], Capactity: %d -----\n", ix, iy, capacity); + fprintf(fp, "//----- Top Protocol -----\n"); + /* Definition */ + fprintf(fp, "module grid_%d__%d_( \n", ix, iy); + fprintf(fp, "\n"); + /* dump global ports */ + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + fprintf(fp, ",\n"); + } + + /* Pins */ + /* Special Care for I/O grid */ + if (IO_TYPE == grid[ix][iy].type) { + dump_verilog_io_grid_pins(fp, ix, iy, 0, TRUE, FALSE); + } else { + dump_verilog_grid_pins(fp, ix, iy, 0, TRUE, FALSE); + } + + /* IO PAD */ + dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix, + iopad_verilog_model->grid_index_low[ix][iy], + iopad_verilog_model->grid_index_high[ix][iy] - 1, + VERILOG_PORT_INPUT); + + /* Print configuration ports */ + /* Reserved configuration ports */ + temp_reserved_conf_bits_msb = grid[ix][iy].type->pb_type->physical_mode_num_reserved_conf_bits; + if (0 < temp_reserved_conf_bits_msb) { + fprintf(fp, ",\n"); + dump_verilog_reserved_sram_ports(fp, sram_verilog_orgz_info, + 0, + temp_reserved_conf_bits_msb - 1, + VERILOG_PORT_INPUT); + } + /* Normal configuration ports */ + if (0 < (get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info) - cur_num_mem_bit)) { + fprintf(fp, ",\n"); + dump_verilog_sram_ports(fp, sram_verilog_orgz_info, + cur_num_mem_bit, + get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info) - 1, + VERILOG_PORT_INPUT); + } + fprintf(fp, ");\n"); + + /* Record LSB and MSB of reserved_conf_bits and regular conf_bits in sram_orgz_info */ + sram_verilog_orgz_info->grid_reserved_conf_bits[ix][iy] = temp_reserved_conf_bits_msb; + sram_verilog_orgz_info->grid_conf_bits_lsb[ix][iy] = cur_num_mem_bit; + sram_verilog_orgz_info->grid_conf_bits_msb[ix][iy] = get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info); + + /* Initialize temporary counter */ + temp_conf_bits_lsb = cur_num_mem_bit; + temp_iopad_lsb = iopad_verilog_model->grid_index_low[ix][iy]; + + /* Quote all the sub blocks*/ + for (iz = 0; iz < capacity; iz++) { + /* Local Vdd and Gnd, subckt name*/ + fprintf(fp, "%s ", verilog_get_grid_phy_block_subckt_name(ix, iy, iz, subckt_name, NULL)); + fprintf(fp, " grid_%d__%d__%d_ (", ix, iy, iz); + fprintf(fp, "\n"); + /* dump global ports */ + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + fprintf(fp, ",\n"); + } + /* Print all the pins */ + /* Special Care for I/O grid */ + if (IO_TYPE == grid[ix][iy].type) { + dump_verilog_io_grid_block_subckt_pins(fp, ix, iy, iz, grid[ix][iy].type); + } else { + dump_verilog_grid_block_subckt_pins(fp, iz, grid[ix][iy].type); + } + /* Print configuration ports */ + temp_reserved_conf_bits_msb = grid[ix][iy].type->pb_type->physical_mode_num_reserved_conf_bits; + temp_conf_bits_msb = temp_conf_bits_lsb + grid[ix][iy].type->pb_type->physical_mode_num_conf_bits; + temp_iopad_msb = temp_iopad_lsb + grid[ix][iy].type->pb_type->physical_mode_num_iopads; + /* Print Input Pad and Output Pad */ + + fprintf(fp, "\n//---- IOPAD ----\n"); + dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix, + temp_iopad_lsb, + temp_iopad_msb - 1, + VERILOG_PORT_CONKT); + assert(!(0 > temp_conf_bits_msb - temp_conf_bits_lsb)); + /* Reserved configuration ports */ + if (0 < temp_reserved_conf_bits_msb) { + fprintf(fp, ",\n"); + dump_verilog_reserved_sram_ports(fp, sram_verilog_orgz_info, + 0, temp_reserved_conf_bits_msb - 1, + VERILOG_PORT_CONKT); + } + /* Normal configuration ports */ + if (0 < (temp_conf_bits_msb - temp_conf_bits_lsb)) { + fprintf(fp, ",\n"); + fprintf(fp, "//---- SRAM ----\n"); + dump_verilog_sram_ports(fp, sram_verilog_orgz_info, + temp_conf_bits_lsb, temp_conf_bits_msb - 1, + VERILOG_PORT_CONKT); + } + /* Update temp_sram_lsb */ + temp_conf_bits_lsb = temp_conf_bits_msb; + temp_inpad_lsb = temp_inpad_msb; + temp_outpad_lsb = temp_outpad_msb; + temp_iopad_lsb = temp_iopad_msb; + fprintf(fp, ");\n"); + } + + fprintf(fp, "endmodule\n"); + fprintf(fp, "//----- END Top Protocol -----\n"); + fprintf(fp, "//----- END Grid[%d][%d], Capactity: %d -----\n\n", ix, iy, capacity); + + /* Check */ + assert(temp_conf_bits_msb == get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info)); + assert(temp_iopad_msb == iopad_verilog_model->grid_index_high[ix][iy]); + + /* Free */ + my_free(subckt_name); + + return; +} + +/* Print all logic blocks SPICE models + * Each logic blocks in the grid that allocated for the FPGA + * will be printed. May have an additional option that only + * output the used logic blocks + */ +void dump_verilog_logic_blocks(char* subckt_dir, + t_arch* arch) { + /* Create file names */ + char* sp_name = my_strcat(subckt_dir, logic_block_verilog_file_name); + FILE* fp = NULL; + int ix, iy; + + /* Check the grid*/ + if ((0 == nx)||(0 == ny)) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid grid size (nx=%d, ny=%d)!\n", __FILE__, __LINE__, nx, ny); + return; + } + vpr_printf(TIO_MESSAGE_INFO,"Grid size of FPGA: nx=%d ny=%d\n", nx + 1, ny + 1); + assert(NULL != grid); + + /* Create a file*/ + fp = fopen(sp_name, "w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create verilog netlist %s",__FILE__, __LINE__, sp_name); + exit(1); + } + /* Generate the descriptions*/ + dump_verilog_file_header(fp,"Logic Blocks in FPGA"); + + /* Print the core logic block one by one + * Note ix=0 and ix = nx + 1 are IO pads. They surround the core logic blocks + */ + vpr_printf(TIO_MESSAGE_INFO,"Generating core grids...\n"); + for (ix = 1; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + /* Ensure this is not a io */ + assert(IO_TYPE != grid[ix][iy].type); + /* Ensure a valid usage */ + assert((0 == grid[ix][iy].usage)||(0 < grid[ix][iy].usage)); + dump_verilog_grid_blocks(fp, ix, iy, arch); + } + } + + vpr_printf(TIO_MESSAGE_INFO,"Generating IO grids...\n"); + /* Print the IO pads */ + /* Left side: x = 0, y = 1 .. ny*/ + ix = 0; + for (iy = 1; iy < (ny + 1); iy++) { + /* Ensure this is a io */ + assert(IO_TYPE == grid[ix][iy].type); + dump_verilog_physical_grid_blocks(fp, ix, iy, arch); + } + /* Right side : x = nx + 1, y = 1 .. ny*/ + ix = nx + 1; + for (iy = 1; iy < (ny + 1); iy++) { + /* Ensure this is a io */ + assert(IO_TYPE == grid[ix][iy].type); + dump_verilog_physical_grid_blocks(fp, ix, iy, arch); + } + /* Bottom side : x = 1 .. nx + 1, y = 0 */ + iy = 0; + for (ix = 1; ix < (nx + 1); ix++) { + /* Ensure this is a io */ + assert(IO_TYPE == grid[ix][iy].type); + dump_verilog_physical_grid_blocks(fp, ix, iy, arch); + } + /* Top side : x = 1 .. nx + 1, y = nx + 1 */ + iy = ny + 1; + for (ix = 1; ix < (nx + 1); ix++) { + /* Ensure this is a io */ + assert(IO_TYPE == grid[ix][iy].type); + dump_verilog_physical_grid_blocks(fp, ix, iy, arch); + } + + + /* Close the file */ + fclose(fp); + + /* Free */ + my_free(sp_name); + + return; +} diff --git a/vpr7_rram/vpr/SRC/syn_verilog/verilog_pbtypes.h b/vpr7_rram/vpr/SRC/syn_verilog/verilog_pbtypes.h new file mode 100644 index 000000000..71c4b7dde --- /dev/null +++ b/vpr7_rram/vpr/SRC/syn_verilog/verilog_pbtypes.h @@ -0,0 +1,156 @@ + +void match_pb_types_verilog_model_rec(t_pb_type* cur_pb_type, + int num_verilog_model, + t_spice_model* verilog_models); + +int verilog_find_path_id_between_pb_rr_nodes(t_rr_node* local_rr_graph, + int src_node, + int des_node); + +enum e_interconnect verilog_find_pb_graph_pin_in_edges_interc_type(t_pb_graph_pin pb_graph_pin); + +t_spice_model* find_pb_graph_pin_in_edges_interc_verilog_model(t_pb_graph_pin pb_graph_pin); + +void stats_mux_verilog_model_pb_type_rec(t_llist** muxes_head, + t_pb_type* cur_pb_type); + +void stats_mux_verilog_model_pb_node_rec(t_llist** muxes_head, + t_pb_graph_node* cur_pb_node); + + +void dump_verilog_pb_type_bus_ports(FILE* fp, + char* port_prefix, + int use_global_clock, + t_pb_type* cur_pb_type, + boolean dump_port_type, + boolean dump_last_comma); + +void dump_verilog_pb_type_ports(FILE* fp, + char* port_prefix, + int use_global_clock, + t_pb_type* cur_pb_type, + boolean dump_port_type, + boolean dump_last_comma); + +void dump_verilog_dangling_des_pb_graph_pin_interc(FILE* fp, + t_pb_graph_pin* des_pb_graph_pin, + t_mode* cur_mode, + enum e_pin2pin_interc_type pin2pin_interc_type, + char* parent_pin_prefix); + +void generate_verilog_src_des_pb_graph_pin_prefix(t_pb_graph_node* src_pb_graph_node, + t_pb_graph_node* des_pb_graph_node, + enum e_pin2pin_interc_type pin2pin_interc_type, + t_interconnect* pin2pin_interc, + char* parent_pin_prefix, + char** src_pin_prefix, + char** des_pin_prefix); + +void verilog_find_interc_fan_in_des_pb_graph_pin(t_pb_graph_pin* des_pb_graph_pin, + t_mode* cur_mode, + t_interconnect** cur_interc, + int* fan_in); + +void dump_verilog_pb_graph_pin_interc(FILE* fp, + char* parent_pin_prefix, + enum e_pin2pin_interc_type pin2pin_interc_type, + t_pb_graph_pin* des_pb_graph_pin, + t_mode* cur_mode, + int is_idle); + +void dump_verilog_pb_graph_interc(FILE* fp, + char* pin_prefix, + t_pb_graph_node* cur_pb_graph_node, + int select_mode_index, + int is_idle); + +void dump_verilog_pb_graph_primitive_node(FILE* fp, + char* subckt_prefix, + t_pb* cur_pb, + t_pb_graph_node* cur_pb_graph_node, + int pb_type_index); + +void dump_pb_primitive_verilog_model(FILE* fp, + char* subckt_prefix, + t_pb* prim_pb, + t_pb_graph_node* prim_pb_graph_node, + int pb_index, + t_spice_model* verilog_model, + int is_idle); + +void dump_verilog_idle_pb_graph_node_rec(FILE* fp, + char* subckt_prefix, + t_pb_graph_node* cur_pb_graph_node, + int pb_type_index); + +void dump_verilog_pb_graph_node_rec(FILE* fp, + char* subckt_prefix, + t_pb* cur_pb, + t_pb_graph_node* cur_pb_graph_node, + int pb_type_index); + +void dump_verilog_phy_pb_graph_node_rec(FILE* fp, + char* subckt_prefix, + t_pb_graph_node* cur_pb_graph_node, + int pb_type_index); + +void dump_verilog_block(FILE* fp, + char* subckt_name, + int x, + int y, + int z, + t_type_ptr type_descriptor, + t_block* mapped_block); + +void dump_verilog_physical_block(FILE* fp, + char* subckt_name, + int x, + int y, + int z, + t_type_ptr type_descriptor); + +void dump_verilog_grid_pins(FILE* fp, + int x, int y, + int top_level, + boolean dump_port_type, + boolean dump_last_comma); + +void dump_verilog_io_grid_pins(FILE* fp, + int x, int y, + int top_level, + boolean dump_port_type, + boolean dump_last_comma); + +char* get_grid_block_subckt_name(int x, + int y, + int z, + char* subckt_prefix, + t_block* mapped_block); + +void dump_verilog_grid_block_subckt_pins(FILE* fp, + int z, + t_type_ptr type_descriptor); + +void dump_verilog_io_grid_block_subckt_pins(FILE* fp, + int x, + int y, + int z, + t_type_ptr type_descriptor); + +void dump_verilog_grid_blocks(FILE* fp, + int ix, + int iy); + +void dump_verilog_physical_grid_blocks(FILE* fp, + int ix, + int iy, + t_arch* arch); + +void dump_verilog_idle_block(FILE* fp, + char* subckt_name, + int x, + int y, + int z, + t_type_ptr type_descriptor); + +void dump_verilog_logic_blocks(char* subckt_dir, t_arch* arch); diff --git a/vpr7_rram/vpr/SRC/syn_verilog/verilog_primitives.c b/vpr7_rram/vpr/SRC/syn_verilog/verilog_primitives.c new file mode 100644 index 000000000..665574386 --- /dev/null +++ b/vpr7_rram/vpr/SRC/syn_verilog/verilog_primitives.c @@ -0,0 +1,553 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph.h" +#include "rr_graph_swseg.h" +#include "vpr_utils.h" + +/* Include spice support headers*/ +#include "linkedlist.h" +#include "fpga_spice_utils.h" +#include "fpga_spice_globals.h" + +/* Include verilog support headers*/ +#include "verilog_global.h" +#include "verilog_utils.h" +#include "verilog_pbtypes.h" +#include "verilog_primitives.h" + +enum e_ff_trigger_type { + FF_RE, FF_FE +}; + +/* Subroutines */ +void dump_verilog_pb_primitive_ff(FILE* fp, + char* subckt_prefix, + t_logical_block* mapped_logical_block, + t_pb_graph_node* prim_pb_graph_node, + int index, + t_spice_model* verilog_model) { + int i; + /* Default FF settings, applied when this FF is idle*/ + enum e_ff_trigger_type trigger_type = FF_RE; + int init_val = 0; + + int num_input_port = 0; + t_spice_model_port** input_ports = NULL; + int num_output_port = 0; + t_spice_model_port** output_ports = NULL; + int num_clock_port = 0; + t_spice_model_port** clock_ports = NULL; + + char* formatted_subckt_prefix = format_verilog_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/ + t_pb_type* prim_pb_type = NULL; + char* port_prefix = NULL; + + /* Ensure a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Ensure a valid pb_graph_node */ + if (NULL == prim_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid prim_pb_graph_node!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Find ports*/ + input_ports = find_spice_model_ports(verilog_model, SPICE_MODEL_PORT_INPUT, &num_input_port, FALSE); + output_ports = find_spice_model_ports(verilog_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + clock_ports = find_spice_model_ports(verilog_model, SPICE_MODEL_PORT_CLOCK, &num_clock_port, FALSE); + + /* Asserts */ + assert(3 == num_input_port); /* D, Set and Reset*/ + for (i = 0; i < num_input_port; i++) { + assert(1 == input_ports[i]->size); + } + assert(1 == num_output_port); + assert(1 == output_ports[0]->size); + assert(1 == num_clock_port); + assert(1 == clock_ports[0]->size); + + assert(SPICE_MODEL_FF == verilog_model->type); + + /* Initialize */ + prim_pb_type = prim_pb_graph_node->pb_type; + + /* Generate Subckt for pb_type*/ + /* + port_prefix = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(prim_pb_type->name) + 1 + + strlen(my_itoa(index)) + 1 + 1)); + sprintf(port_prefix, "%s%s[%d]", formatted_subckt_prefix, prim_pb_type->name, index); + */ + /* Simplify the port prefix, make SPICE netlist readable */ + port_prefix = (char*)my_malloc(sizeof(char)* + (strlen(prim_pb_type->name) + 1 + + strlen(my_itoa(index)) + 1 + 1)); + sprintf(port_prefix, "%s_%d_", prim_pb_type->name, index); + + + if (NULL != mapped_logical_block) { + fprintf(fp, "//----- Flip-flop Verilog module: %s -----\n", + mapped_logical_block->name); + } + /* Comment lines */ + fprintf(fp, "//----- Flip-flop Verilog module: %s%s -----\n", + formatted_subckt_prefix, port_prefix); + /* Definition line */ + fprintf(fp, "module %s%s (", formatted_subckt_prefix, port_prefix); + /* Only dump the global ports belonging to a spice_model */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE)) { + fprintf(fp, ",\n"); + } + /* print ports*/ + dump_verilog_pb_type_ports(fp, port_prefix, 0, prim_pb_type, TRUE, FALSE); + /* Local vdd and gnd*/ + fprintf(fp, ");\n"); + /* Definition ends*/ + + /* Call the dff subckt*/ + fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + /* Only dump the global ports belonging to a spice_model */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, TRUE)) { + fprintf(fp, ",\n"); + } + /* print ports*/ + dump_verilog_pb_type_ports(fp, port_prefix, 1, prim_pb_type, FALSE, FALSE); /* Use global clock for each DFF...*/ + + /* Local vdd and gnd, verilog_model name + * TODO: global vdd for ff + */ + fprintf(fp, ");\n"); + + /* Apply rising edge, and init value to the ff*/ + if (NULL != mapped_logical_block) { + /* Consider the rising edge|falling edge */ + if (0 == strcmp("re", mapped_logical_block->trigger_type)) { + trigger_type = FF_RE; + } else if (0 == strcmp("fe", mapped_logical_block->trigger_type)) { + trigger_type = FF_FE; + } else { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid ff trigger type! Should be [re|fe].\n", + __FILE__, __LINE__); + exit(1); + } + /* Assign initial value */ + if (1 == mapped_logical_block->init_val) { + init_val = 1; + } else { + init_val = 0; + } + + /* Back-annotate to logical block */ + mapped_logical_block->mapped_spice_model = verilog_model; + mapped_logical_block->mapped_spice_model_index = verilog_model->cnt; + } else { + trigger_type = FF_RE; + init_val = 0; + } + /* TODO: apply falling edge, initial value to FF!!!*/ + /*fprintf(fp, "\n");*/ + + /* End */ + fprintf(fp, "endmodule\n"); + + /* Comment lines */ + fprintf(fp, "//----- END Flip-flop Verilog module: %s%s -----\n\n", + formatted_subckt_prefix, port_prefix); + + verilog_model->cnt++; + + /*Free*/ + my_free(formatted_subckt_prefix); + my_free(port_prefix); + + return; +} + +/* Print hardlogic SPICE subckt*/ +void dump_verilog_pb_primitive_hardlogic(FILE* fp, + char* subckt_prefix, + t_logical_block* mapped_logical_block, + t_pb_graph_node* prim_pb_graph_node, + int index, + t_spice_model* verilog_model) { + int num_input_port = 0; + t_spice_model_port** input_ports = NULL; + int num_output_port = 0; + t_spice_model_port** output_ports = NULL; + int num_clock_port = 0; + t_spice_model_port** clock_ports = NULL; + + char* formatted_subckt_prefix = format_verilog_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/ + t_pb_type* prim_pb_type = NULL; + char* port_prefix = NULL; + + /* Ensure a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Ensure a valid pb_graph_node */ + if (NULL == prim_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid prim_pb_graph_node!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Find ports*/ + input_ports = find_spice_model_ports(verilog_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + output_ports = find_spice_model_ports(verilog_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + clock_ports = find_spice_model_ports(verilog_model, SPICE_MODEL_PORT_CLOCK, &num_clock_port, TRUE); + + /* Asserts */ + assert(SPICE_MODEL_HARDLOGIC == verilog_model->type); + + /* Initialize */ + prim_pb_type = prim_pb_graph_node->pb_type; + + /* Generate Subckt for pb_type*/ + /* + port_prefix = (char*)my_malloc(sizeof(char)* + (strlen(formatted_subckt_prefix) + strlen(prim_pb_type->name) + 1 + + strlen(my_itoa(index)) + 1 + 1)); + sprintf(port_prefix, "%s%s[%d]", formatted_subckt_prefix, prim_pb_type->name, index); + */ + /* Simplify the port prefix, make SPICE netlist readable */ + port_prefix = (char*)my_malloc(sizeof(char)* + (strlen(prim_pb_type->name) + 1 + + strlen(my_itoa(index)) + 1 + 1)); + sprintf(port_prefix, "%s_%d_", prim_pb_type->name, index); + /* Comment lines */ + fprintf(fp, "//----- Hardlogic Verilog module: %s%s -----\n", + formatted_subckt_prefix, port_prefix); + /* Definition line */ + fprintf(fp, "module %s%s (", formatted_subckt_prefix, port_prefix); + fprintf(fp, "\n"); + /* Only dump the global ports belonging to a spice_model */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE)) { + fprintf(fp, ",\n"); + } + /* print ports*/ + dump_verilog_pb_type_ports(fp, port_prefix, 0, prim_pb_type, TRUE, FALSE); + /* Local vdd and gnd*/ + fprintf(fp, ");\n"); + /* Definition ends*/ + + /* Back-annotate to logical block */ + if (NULL != mapped_logical_block) { + mapped_logical_block->mapped_spice_model = verilog_model; + mapped_logical_block->mapped_spice_model_index = verilog_model->cnt; + } + + /* Call the hardlogic subckt*/ + fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + fprintf(fp, "\n"); + /* Only dump the global ports belonging to a spice_model */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, TRUE)) { + fprintf(fp, ",\n"); + } + /* print ports*/ + dump_verilog_pb_type_ports(fp, port_prefix, 0, prim_pb_type, FALSE, FALSE); + /* Local vdd and gnd, verilog_model name, + * Global vdd for hardlogic to split + */ + fprintf(fp, ");\n"); + + /* End */ + fprintf(fp, "endmodule\n"); + /* Comment lines */ + fprintf(fp, "//----- EDN Hardlogic Verilog module: %s%s -----\n", + formatted_subckt_prefix, port_prefix); + + verilog_model->cnt++; + + /*Free*/ + free(formatted_subckt_prefix); + free(port_prefix); + + return; +} + +/* Dump a I/O pad primitive node */ +void dump_verilog_pb_primitive_io(FILE* fp, + char* subckt_prefix, + t_logical_block* mapped_logical_block, + t_pb_graph_node* prim_pb_graph_node, + int index, + t_spice_model* verilog_model) { + int num_pad_port = 0; /* INOUT port */ + t_spice_model_port** pad_ports = NULL; + int num_input_port = 0; + t_spice_model_port** input_ports = NULL; + int num_output_port = 0; + t_spice_model_port** output_ports = NULL; + int num_clock_port = 0; + t_spice_model_port** clock_ports = NULL; + int num_sram_port = 0; + t_spice_model_port** sram_ports = NULL; + + int i; + int num_sram = 0; + int* sram_bits = NULL; + + char* formatted_subckt_prefix = format_verilog_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/ + t_pb_type* prim_pb_type = NULL; + char* port_prefix = NULL; + + /* For each SRAM, we could have multiple BLs/WLs */ + int num_bl_ports = 0; + t_spice_model_port** bl_port = NULL; + int num_wl_ports = 0; + t_spice_model_port** wl_port = NULL; + int num_bl_per_sram = 0; + int num_wl_per_sram = 0; + int expected_num_sram; + + int cur_num_sram = 0; + int num_conf_bits = 0; + int num_reserved_conf_bits = 0; + t_spice_model* mem_model = NULL; + int cur_bl, cur_wl; + + /* Ensure a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Ensure a valid pb_graph_node */ + if (NULL == prim_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid prim_pb_graph_node!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Find ports*/ + pad_ports = find_spice_model_ports(verilog_model, SPICE_MODEL_PORT_INOUT, &num_pad_port, TRUE); + input_ports = find_spice_model_ports(verilog_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + output_ports = find_spice_model_ports(verilog_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + clock_ports = find_spice_model_ports(verilog_model, SPICE_MODEL_PORT_CLOCK, &num_clock_port, TRUE); + sram_ports = find_spice_model_ports(verilog_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); + + /* Asserts */ + assert(SPICE_MODEL_IOPAD == verilog_model->type); /* Support IO PAD which matches the physical design */ + + /* Initialize */ + get_sram_orgz_info_mem_model(sram_verilog_orgz_info, &mem_model); + + prim_pb_type = prim_pb_graph_node->pb_type; + + /* Generate Subckt for pb_type*/ + /* Simplify the port prefix, make SPICE netlist readable */ + port_prefix = (char*)my_malloc(sizeof(char)* + (strlen(prim_pb_type->name) + 1 + + strlen(my_itoa(index)) + 1 + 1)); + sprintf(port_prefix, "%s_%d_", prim_pb_type->name, index); + /* Comment lines */ + fprintf(fp, "//----- IO Verilog module: %s%s -----\n", + formatted_subckt_prefix, port_prefix); + /* Definition line */ + fprintf(fp, "module %s%s (", formatted_subckt_prefix, port_prefix); + fprintf(fp, "\n"); + /* Only dump the global ports belonging to a spice_model + */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE)) { + fprintf(fp, ",\n"); + } + + /* TODO: assert this is physical mode */ + assert((1 == num_sram_port)&&(NULL != sram_ports)&&(1 == sram_ports[0]->size)); + num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1); + /* Get current counter of mem_bits, bl and wl */ + cur_num_sram = get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info); + get_sram_orgz_info_num_blwl(sram_verilog_orgz_info, &cur_bl, &cur_wl); + /* print ports --> input ports */ + dump_verilog_pb_type_ports(fp, port_prefix, 0, prim_pb_type, TRUE, TRUE); + /* Print output port */ + fprintf(fp, "inout [%d:%d] %s%s\n", + verilog_model->cnt, verilog_model->cnt, + gio_inout_prefix, verilog_model->prefix); + /* Print SRAM ports */ + /* connect to reserved BL/WLs ? */ + num_reserved_conf_bits = count_num_reserved_conf_bits_one_spice_model(verilog_model, sram_verilog_orgz_info->type, 0); + /* Get the number of configuration bits required by this MUX */ + num_conf_bits = count_num_conf_bits_one_spice_model(verilog_model, sram_verilog_orgz_info->type, 0); + /* Reserved sram ports */ + if (0 < num_reserved_conf_bits) { + fprintf(fp, ",\n"); + } + dump_verilog_reserved_sram_ports(fp, sram_verilog_orgz_info, + 0, num_reserved_conf_bits - 1, + VERILOG_PORT_INPUT); + /* Normal sram ports */ + if (0 < num_conf_bits) { + fprintf(fp, ",\n"); + } + dump_verilog_sram_ports(fp, sram_verilog_orgz_info, + cur_num_sram, cur_num_sram + num_sram - 1, + VERILOG_PORT_INPUT); + /* Local vdd and gnd*/ + fprintf(fp, ");\n"); + + dump_verilog_sram_config_bus_internal_wires(fp, sram_verilog_orgz_info, + cur_num_sram, cur_num_sram + num_sram - 1); + switch (sram_verilog_orgz_type) { + case SPICE_SRAM_MEMORY_BANK: + /* Local wires */ + /* Find the number of BLs/WLs of each SRAM */ + /* Detect the SRAM SPICE model linked to this SRAM port */ + assert(NULL != sram_ports[0]->spice_model); + assert(SPICE_MODEL_SRAM == sram_ports[0]->spice_model->type); + find_bl_wl_ports_spice_model(sram_ports[0]->spice_model, + &num_bl_ports, &bl_port, &num_wl_ports, &wl_port); + assert(1 == num_bl_ports); + assert(1 == num_wl_ports); + num_bl_per_sram = bl_port[0]->size; + num_wl_per_sram = wl_port[0]->size; + break; + case SPICE_SRAM_STANDALONE: + case SPICE_SRAM_SCAN_CHAIN: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid SRAM organization type!\n", + __FILE__, __LINE__); + exit(1); + } + /* Definition ends*/ + + /* Dump the configuration port bus */ + dump_verilog_mem_config_bus(fp, mem_model, sram_verilog_orgz_info, + cur_num_sram, num_reserved_conf_bits, num_conf_bits); + + /* Call the I/O subckt*/ + fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + fprintf(fp, "\n"); + /* Only dump the global ports belonging to a spice_model + * Disable recursive here ! + */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE)) { + fprintf(fp, ",\n"); + } + + /* assert */ + assert((1 == num_sram_port)&&(NULL != sram_ports)&&(1 == sram_ports[0]->size)); + num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1); + /* print ports --> input ports */ + dump_verilog_pb_type_ports(fp, port_prefix, 0, prim_pb_type, FALSE, TRUE); + /* Print inout port */ + fprintf(fp, "%s%s[%d], ", gio_inout_prefix, + verilog_model->prefix, verilog_model->cnt); + /* Print SRAM ports */ + /* Connect srams: TODO: to find the SRAM model used by this Verilog model */ + dump_verilog_sram_one_outport(fp, sram_verilog_orgz_info, + cur_num_sram, cur_num_sram, + 0, VERILOG_PORT_CONKT); + fprintf(fp, ", "); + dump_verilog_sram_one_outport(fp, sram_verilog_orgz_info, + cur_num_sram, cur_num_sram, + 1, VERILOG_PORT_CONKT); + + /* Local vdd and gnd, verilog_model name, + * TODO: Global vdd for i/o pad to split? + */ + fprintf(fp, ");\n"); + + /* Call SRAM subckt */ + assert((1 == num_sram_port)&&(NULL != sram_ports)&&(1 == sram_ports[0]->size)); + /* what is the SRAM bit of a mode? */ + /* If logical block is not NULL, we need to decode the sram bit */ + if (NULL != mapped_logical_block) { + assert(NULL != mapped_logical_block->pb->pb_graph_node->pb_type->mode_bits); + sram_bits = decode_mode_bits(mapped_logical_block->pb->pb_graph_node->pb_type->mode_bits, &expected_num_sram); + assert(expected_num_sram == num_sram); + } else { + /* Initialize */ + sram_bits = (int*)my_calloc(num_sram, sizeof(int)); + for (i = 0; i < num_sram; i++) { + sram_bits[i] = sram_ports[0]->default_val; + } + } + /* SRAM_bit will be later reconfigured according to operating mode */ + switch (sram_verilog_orgz_type) { + case SPICE_SRAM_MEMORY_BANK: + for (i = 0; i < num_sram; i++) { + /* Decode the SRAM bits to BL/WL bits. + * first half part is BL, the other half part is WL + */ + decode_and_add_verilog_sram_membank_conf_bit_to_llist(sram_verilog_orgz_info, cur_num_sram + i, + num_bl_per_sram, num_wl_per_sram, + sram_bits[i]); + } + break; + case SPICE_SRAM_STANDALONE: + case SPICE_SRAM_SCAN_CHAIN: + /* Store the configuraion bit to linked-list */ + add_mux_conf_bits_to_llist(0, sram_verilog_orgz_info, + num_sram, sram_bits, + verilog_model); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid SRAM organization type!\n", + __FILE__, __LINE__); + exit(1); + } + /* Call SRAM subckts only + * when Configuration organization style is memory bank */ + num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1); + for (i = 0; i < num_sram; i++) { + dump_verilog_sram_submodule(fp, sram_verilog_orgz_info, + mem_model); /* use the mem_model in sram_verilog_orgz_info */ + } + + /* End */ + fprintf(fp, "endmodule\n"); + /* Comment lines */ + fprintf(fp, "//----- END IO Verilog module: %s%s -----\n\n", + formatted_subckt_prefix, port_prefix); + + /* Back-annotate to logical block */ + if (NULL != mapped_logical_block) { + mapped_logical_block->mapped_spice_model = verilog_model; + mapped_logical_block->mapped_spice_model_index = verilog_model->cnt; + } + + /* Update the verilog_model counter */ + verilog_model->cnt++; + + /*Free*/ + free(formatted_subckt_prefix); + free(port_prefix); + my_free(input_ports); + my_free(output_ports); + my_free(pad_ports); + my_free(clock_ports); + my_free(sram_ports); + my_free(sram_bits); + + return; +} + + diff --git a/vpr7_rram/vpr/SRC/syn_verilog/verilog_primitives.h b/vpr7_rram/vpr/SRC/syn_verilog/verilog_primitives.h new file mode 100644 index 000000000..26afa752a --- /dev/null +++ b/vpr7_rram/vpr/SRC/syn_verilog/verilog_primitives.h @@ -0,0 +1,22 @@ + +void dump_verilog_pb_primitive_ff(FILE* fp, + char* subckt_prefix, + t_logical_block* mapped_logical_block, + t_pb_graph_node* prim_pb_graph_node, + int index, + t_spice_model* spice_model); + + +void dump_verilog_pb_primitive_hardlogic(FILE* fp, + char* subckt_prefix, + t_logical_block* mapped_logical_block, + t_pb_graph_node* prim_pb_graph_node, + int index, + t_spice_model* spice_model); + +void dump_verilog_pb_primitive_io(FILE* fp, + char* subckt_prefix, + t_logical_block* mapped_logical_block, + t_pb_graph_node* prim_pb_graph_node, + int index, + t_spice_model* spice_model); diff --git a/vpr7_rram/vpr/SRC/syn_verilog/verilog_routing.c b/vpr7_rram/vpr/SRC/syn_verilog/verilog_routing.c new file mode 100644 index 000000000..1424eabc9 --- /dev/null +++ b/vpr7_rram/vpr/SRC/syn_verilog/verilog_routing.c @@ -0,0 +1,1901 @@ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph_util.h" +#include "rr_graph.h" +#include "rr_graph2.h" +#include "vpr_utils.h" + +/* Include SPICE support headers*/ +#include "linkedlist.h" +#include "fpga_spice_utils.h" +#include "fpga_spice_backannotate_utils.h" +#include "fpga_spice_globals.h" + +/* Include Verilog support headers*/ +#include "verilog_global.h" +#include "verilog_utils.h" +#include "verilog_lut.h" +#include "verilog_primitives.h" +#include "verilog_routing.h" + + +void dump_verilog_routing_chan_subckt(FILE* fp, + int x, int y, + t_rr_type chan_type, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices, + int num_segment, t_segment_inf* segments) { + int itrack, iseg, cost_index; + char* chan_prefix = NULL; + int chan_width = 0; + t_rr_node** chan_rr_nodes = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + assert((CHANX == chan_type)||(CHANY == chan_type)); + + /* Initial chan_prefix*/ + switch (chan_type) { + case CHANX: + chan_prefix = "chanx"; + /* Comment lines */ + fprintf(fp, "//----- Verilog Module of Channel X [%d][%d] -----\n", x, y); + break; + case CHANY: + chan_prefix = "chany"; + /* Comment lines */ + fprintf(fp, "//----- Verilog Module Channel Y [%d][%d] -----\n", x, y); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid Channel type! Should be CHANX or CHANY.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Collect rr_nodes for Tracks for chanx[ix][iy] */ + chan_rr_nodes = get_chan_rr_nodes(&chan_width, chan_type, x, y, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + + /* Chan subckt definition */ + fprintf(fp, "module %s_%d__%d_ ( \n", chan_prefix, x, y); + fprintf(fp, "\n"); + /* dump global ports */ + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + fprintf(fp, ",\n"); + } + /* Inputs and outputs, + * Rules for CHANX: + * print left-hand ports(in) first, then right-hand ports(out) + * Rules for CHANX: + * print bottom ports(in) first, then top ports(out) + */ + for (itrack = 0; itrack < chan_width; itrack++) { + switch (chan_rr_nodes[itrack]->direction) { + case INC_DIRECTION: + fprintf(fp, " input in%d, //--- track %d input \n", itrack, itrack); + break; + case DEC_DIRECTION: + fprintf(fp, " output out%d, //--- track %d output \n", itrack, itrack); + break; + case BI_DIRECTION: + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of rr_node chany[%d][%d]_in/out[%d]!\n", + __FILE__, __LINE__, x, y + 1, itrack); + exit(1); + } + } + for (itrack = 0; itrack < chan_width; itrack++) { + switch (chan_rr_nodes[itrack]->direction) { + case INC_DIRECTION: + fprintf(fp, " output out%d, //--- track %d output\n", itrack, itrack); + break; + case DEC_DIRECTION: + fprintf(fp, " input in%d, //--- track %d input \n", itrack, itrack); + break; + case BI_DIRECTION: + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of rr_node chany[%d][%d]_in/out[%d]!\n", + __FILE__, __LINE__, x, y + 1, itrack); + exit(1); + } + } + /* Middle point output for connection box inputs */ + for (itrack = 0; itrack < chan_width; itrack++) { + fprintf(fp, " output mid_out%d", itrack); + if (itrack < (chan_width - 1)) { + fprintf(fp, ","); + } + fprintf(fp, " // Middle output %d to logic blocks \n", itrack); + } + fprintf(fp, " );\n"); + + /* Print segments models*/ + for (itrack = 0; itrack < chan_width; itrack++) { + cost_index = chan_rr_nodes[itrack]->cost_index; + iseg = rr_indexed_data[cost_index].seg_index; + /* Check */ + assert((!(iseg < 0))&&(iseg < num_segment)); + /* short connecting inputs and outputs: + * length of metal wire and parasitics are handled by semi-custom flow + */ + fprintf(fp, "assign out%d = in%d; \n", itrack, itrack); + fprintf(fp, "assign mid_out%d = in%d; \n", itrack, itrack); + } + + fprintf(fp, "endmodule\n"); + + /* Comment lines */ + switch (chan_type) { + case CHANX: + /* Comment lines */ + fprintf(fp, "//----- END Verilog Module of Channel X [%d][%d] -----\n\n", x, y); + break; + case CHANY: + /* Comment lines */ + fprintf(fp, "//----- END Verilog Module of Channel Y [%d][%d] -----\n\n", x, y); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid Channel type! Should be CHANX or CHANY.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Free */ + my_free(chan_rr_nodes); + + return; +} + +t_rr_node** verilog_get_grid_side_pin_rr_nodes(int* num_pin_rr_nodes, + t_rr_type pin_type, + int x, + int y, + int side, + t_ivec*** LL_rr_node_indices) { + int height, ipin, class_id, inode; + t_type_ptr type = NULL; + t_rr_node** ret = NULL; + enum e_pin_type pin_class_type; + int cur; + + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + type = grid[x][y].type; + assert(NULL != type); + /* Assign the type of PIN*/ + switch (pin_type) { + case IPIN: + /* case SINK: */ + pin_class_type = RECEIVER; /* This is the end of a route path*/ + break; + /*case SOURCE:*/ + case OPIN: + pin_class_type = DRIVER; /* This is the start of a route path */ + break; + /* SINK and SOURCE are hypothesis nodes */ + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid pin_type!\n", __FILE__, __LINE__); + exit(1); + } + + /* Output the pins on the side*/ + (*num_pin_rr_nodes) = 0; + height = grid[x][y].offset; + for (ipin = 0; ipin < type->num_pins; ipin++) { + class_id = type->pin_class[ipin]; + if ((1 == type->pinloc[height][side][ipin])&&(pin_class_type == type->class_inf[class_id].type)) { + (*num_pin_rr_nodes)++; + } + } + /* Malloc */ + ret = (t_rr_node**)my_malloc(sizeof(t_rr_node*)*(*num_pin_rr_nodes)); + + /* Fill the return array*/ + cur = 0; + height = grid[x][y].offset; + for (ipin = 0; ipin < type->num_pins; ipin++) { + class_id = type->pin_class[ipin]; + if ((1 == type->pinloc[height][side][ipin])&&(pin_class_type == type->class_inf[class_id].type)) { + inode = get_rr_node_index(x, y, pin_type, ipin, LL_rr_node_indices); + ret[cur] = &(rr_node[inode]); + cur++; + } + } + assert(cur == (*num_pin_rr_nodes)); + + return ret; +} + +void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, + int pin_index, int side, + int x, int y, + boolean dump_port_type) { + int height; + t_type_ptr type = NULL; + char* verilog_port_type = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + type = grid[x][y].type; + assert(NULL != type); + + assert((!(0 > pin_index))&&(pin_index < type->num_pins)); + assert((!(0 > side))&&(!(side > 3))); + + /* Assign the type of PIN*/ + switch (pin_type) { + case IPIN: + /* case SINK: */ + verilog_port_type = "output"; + break; + /* case SOURCE: */ + case OPIN: + verilog_port_type = "input"; + break; + /* SINK and SOURCE are hypothesis nodes */ + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid pin_type!\n", __FILE__, __LINE__); + exit(1); + } + + /* Output the pins on the side*/ + height = grid[x][y].offset; + if (1 == type->pinloc[height][side][pin_index]) { + /* Not sure if we need to plus a height */ + /* fprintf(fp, "grid_%d__%d__pin_%d__%d__%d_ ", x, y, height, side, pin_index); */ + if (TRUE == dump_port_type) { + fprintf(fp, "%s ", verilog_port_type); + } + fprintf(fp, " grid_%d__%d__pin_%d__%d__%d_", x, y + height, height, side, pin_index); + if (TRUE == dump_port_type) { + fprintf(fp, ",\n"); + } + } else { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Fail to print a grid pin (x=%d, y=%d, height=%d, side=%d, index=%d)", + __FILE__, __LINE__, x, y, height, side, pin_index); + exit(1); + } + + return; +} + +void dump_verilog_grid_side_pins(FILE* fp, + t_rr_type pin_type, + int x, + int y, + int side, + boolean dump_port_type) { + int height, ipin, class_id; + t_type_ptr type = NULL; + enum e_pin_type pin_class_type; + char* verilog_port_type = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert((!(0 > x))&&(!(x > (nx + 1)))); + assert((!(0 > y))&&(!(y > (ny + 1)))); + type = grid[x][y].type; + assert(NULL != type); + + /* Assign the type of PIN*/ + switch (pin_type) { + case IPIN: + /* case SINK: */ + pin_class_type = RECEIVER; /* This is the end of a route path*/ + verilog_port_type = "output"; + break; + /* case SOURCE: */ + case OPIN: + pin_class_type = DRIVER; /* This is the start of a route path */ + verilog_port_type = "input"; + break; + /* SINK and SOURCE are hypothesis nodes */ + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid pin_type!\n", __FILE__, __LINE__); + exit(1); + } + + /* Output the pins on the side*/ + height = grid[x][y].offset; + for (ipin = 0; ipin < type->num_pins; ipin++) { + class_id = type->pin_class[ipin]; + if ((1 == type->pinloc[height][side][ipin])&&(pin_class_type == type->class_inf[class_id].type)) { + if (TRUE == dump_port_type) { + fprintf(fp, "%s ", verilog_port_type); + } + fprintf(fp, " grid_%d__%d__pin_%d__%d__%d_", x, y, height, side, ipin); + if (TRUE == dump_port_type) { + fprintf(fp, ",\n"); + } else { + fprintf(fp, ",\n"); + } + } + } + + return; +} + +/* Determine the channel coordinates in switch box subckt */ +void verilog_determine_src_chan_coordinate_switch_box(t_rr_node* src_rr_node, + t_rr_node* des_rr_node, + int side, + int switch_box_x, + int switch_box_y, + int* src_chan_x, + int* src_chan_y, + char** src_chan_port_name) { + /* Check */ + assert((!(0 > side))&&(side < 4)); + assert((CHANX == src_rr_node->type)||(CHANY == src_rr_node->type)); + assert((CHANX == des_rr_node->type)||(CHANY == des_rr_node->type)); + assert((!(0 > switch_box_x))&&(!(switch_box_x > (nx + 1)))); + assert((!(0 > switch_box_y))&&(!(switch_box_y > (ny + 1)))); + + /* Initialize*/ + (*src_chan_x) = 0; + (*src_chan_y) = 0; + (*src_chan_port_name) = NULL; + + switch (side) { + case 0: /*TOP*/ + /* The destination rr_node only have one condition!!! */ + assert((INC_DIRECTION == des_rr_node->direction)&&(CHANY == des_rr_node->type)); + /* Following cases: + * | + * / | \ + */ + if ((INC_DIRECTION == src_rr_node->direction)&&(CHANY == src_rr_node->type)) { + (*src_chan_x) = switch_box_x; + (*src_chan_y) = switch_box_y; + (*src_chan_port_name) = "in"; + } else if ((INC_DIRECTION == src_rr_node->direction)&&(CHANX == src_rr_node->type)) { + (*src_chan_x) = switch_box_x; + (*src_chan_y) = switch_box_y; + (*src_chan_port_name) = "in"; + } else if ((DEC_DIRECTION == src_rr_node->direction)&&(CHANX == src_rr_node->type)) { + (*src_chan_x) = switch_box_x + 1; + (*src_chan_y) = switch_box_y; + (*src_chan_port_name) = "in"; + } else { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid source channel!\n", __FILE__, __LINE__); + exit(1); + } + break; + case 1: /*RIGHT*/ + /* The destination rr_node only have one condition!!! */ + assert((INC_DIRECTION == des_rr_node->direction)&&(CHANX == des_rr_node->type)); + /* Following cases: + * \ + * --- ---- + * / + */ + if ((DEC_DIRECTION == src_rr_node->direction)&&(CHANY == src_rr_node->type)) { + (*src_chan_x) = switch_box_x; + (*src_chan_y) = switch_box_y + 1; + (*src_chan_port_name) = "in"; + } else if ((INC_DIRECTION == src_rr_node->direction)&&(CHANX == src_rr_node->type)) { + (*src_chan_x) = switch_box_x; + (*src_chan_y) = switch_box_y; + (*src_chan_port_name) = "in"; + } else if ((INC_DIRECTION == src_rr_node->direction)&&(CHANY == src_rr_node->type)) { + (*src_chan_x) = switch_box_x; + (*src_chan_y) = switch_box_y; + (*src_chan_port_name) = "in"; + } else { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid source channel!\n", __FILE__, __LINE__); + exit(1); + } + break; + case 2: /*BOTTOM*/ + /* The destination rr_node only have one condition!!! */ + assert((DEC_DIRECTION == des_rr_node->direction)&&(CHANY == des_rr_node->type)); + /* Following cases: + * | + * \ / + * | + */ + if ((DEC_DIRECTION == src_rr_node->direction)&&(CHANY == src_rr_node->type)) { + (*src_chan_x) = switch_box_x; + (*src_chan_y) = switch_box_y + 1; + (*src_chan_port_name) = "in"; + } else if ((INC_DIRECTION == src_rr_node->direction)&&(CHANX == src_rr_node->type)) { + (*src_chan_x) = switch_box_x; + (*src_chan_y) = switch_box_y; + (*src_chan_port_name) = "in"; + } else if ((DEC_DIRECTION == src_rr_node->direction)&&(CHANX == src_rr_node->type)) { + (*src_chan_x) = switch_box_x + 1; + (*src_chan_y) = switch_box_y; + (*src_chan_port_name) = "in"; + } else { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid source channel!\n", __FILE__, __LINE__); + exit(1); + } + break; + case 3: /*LEFT*/ + /* The destination rr_node only have one condition!!! */ + assert((DEC_DIRECTION == des_rr_node->direction)&&(CHANX == des_rr_node->type)); + /* Following cases: + * / + * --- ---- + * \ + */ + if ((DEC_DIRECTION == src_rr_node->direction)&&(CHANX == src_rr_node->type)) { + (*src_chan_x) = switch_box_x + 1; + (*src_chan_y) = switch_box_y; + (*src_chan_port_name) = "in"; + } else if ((INC_DIRECTION == src_rr_node->direction)&&(CHANY == src_rr_node->type)) { + (*src_chan_x) = switch_box_x; + (*src_chan_y) = switch_box_y; + (*src_chan_port_name) = "in"; + } else if ((DEC_DIRECTION == src_rr_node->direction)&&(CHANY == src_rr_node->type)) { + (*src_chan_x) = switch_box_x; + (*src_chan_y) = switch_box_y + 1; + (*src_chan_port_name) = "in"; + } else { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid source channel!\n", __FILE__, __LINE__); + exit(1); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s, [LINE%d])Invalid side!\n", __FILE__, __LINE__); + exit(1); + } + + /* Make sure the source rr_node (channel) is in the range*/ + assert((!((*src_chan_x) < src_rr_node->xlow))&&(!((*src_chan_x) > src_rr_node->xhigh))); + if (!((!((*src_chan_y) < src_rr_node->ylow))&&(!((*src_chan_y) > src_rr_node->yhigh)))) { + assert((!((*src_chan_y) < src_rr_node->ylow))&&(!((*src_chan_y) > src_rr_node->yhigh))); + } + + return; +} + +void dump_verilog_switch_box_chan_port(FILE* fp, + t_sb* cur_sb_info, + int chan_side, + t_rr_node* cur_rr_node, + enum PORTS cur_rr_node_direction) { + int index = -1; + t_rr_type chan_rr_node_type; + int chan_rr_node_x, chan_rr_node_y; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Get the index in sb_info of cur_rr_node */ + index = get_rr_node_index_in_sb_info(cur_rr_node, (*cur_sb_info), chan_side, cur_rr_node_direction); + /* Make sure this node is included in this sb_info */ + assert((-1 != index)&&(-1 != chan_side)); + + get_chan_rr_node_coorindate_in_sb_info((*cur_sb_info), chan_side, + &chan_rr_node_type, &chan_rr_node_x, &chan_rr_node_y); + + assert(cur_rr_node->type == chan_rr_node_type); + + fprintf(fp, "%s_%d__%d__%s_%d_ ", + convert_chan_type_to_string(chan_rr_node_type), + chan_rr_node_x, chan_rr_node_y, + convert_chan_rr_node_direction_to_string(cur_sb_info->chan_rr_node_direction[chan_side][index]), + cur_rr_node->ptc_num); + + return; +} + +/* Print a short interconneciton in switch box + * There are two cases should be noticed. + * 1. The actual fan-in of cur_rr_node is 0. In this case, + the cur_rr_node need to be short connected to itself which is on the opposite side of this switch + * 2. The actual fan-in of cur_rr_node is 0. In this case, + * The cur_rr_node need to connected to the drive_rr_node + */ +void dump_verilog_switch_box_short_interc(FILE* fp, + t_sb* cur_sb_info, + int chan_side, + t_rr_node* cur_rr_node, + int actual_fan_in, + t_rr_node* drive_rr_node) { + int side, index; + int grid_x, grid_y; + char* chan_name = NULL; + char* des_chan_port_name = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > cur_sb_info->x))&&(!(cur_sb_info->x > (nx + 1)))); + assert((!(0 > cur_sb_info->y))&&(!(cur_sb_info->y > (ny + 1)))); + assert((0 == actual_fan_in)||(1 == actual_fan_in)); + + chan_name = convert_chan_type_to_string(cur_rr_node->type); + + /* Get the index in sb_info of cur_rr_node */ + index = get_rr_node_index_in_sb_info(cur_rr_node, (*cur_sb_info), chan_side, OUT_PORT); + des_chan_port_name = "out"; + + fprintf(fp, "//----- Short connection %s[%d][%d]_%s[%d] -----\n", + chan_name, cur_sb_info->x, cur_sb_info->y, des_chan_port_name, cur_rr_node->ptc_num); + fprintf(fp, "assign "); + + /* Output port */ + dump_verilog_switch_box_chan_port(fp, cur_sb_info, chan_side, cur_rr_node, OUT_PORT); + fprintf(fp, " = "); + + /* Check the driver*/ + if (0 == actual_fan_in) { + assert(drive_rr_node == cur_rr_node); + } else { + /* drive_rr_node = &(rr_node[cur_rr_node->prev_node]); */ + assert(1 == rr_node_drive_switch_box(drive_rr_node, cur_rr_node, cur_sb_info->x, cur_sb_info->y, chan_side)); + } + switch (drive_rr_node->type) { + /* case SOURCE: */ + case OPIN: + /* Indicate a CLB Outpin*/ + /* Search all the sides of a SB, see this drive_rr_node is an INPUT of this SB */ + get_rr_node_side_and_index_in_sb_info(drive_rr_node, (*cur_sb_info), IN_PORT, &side, &index); + /* We need to be sure that drive_rr_node is part of the SB */ + assert((-1 != index)&&(-1 != side)); + /* Find grid_x and grid_y */ + grid_x = drive_rr_node->xlow; + grid_y = drive_rr_node->ylow; /*Plus the offset in function fprint_grid_side_pin_with_given_index */ + /* Print a grid pin */ + dump_verilog_grid_side_pin_with_given_index(fp, IPIN, /* this is an input of a Switch Box */ + drive_rr_node->ptc_num, + cur_sb_info->opin_rr_node_grid_side[side][index], + grid_x, grid_y, + FALSE); /* Do not dump the direction of the port! */ + break; + case CHANX: + case CHANY: + /* Should an input */ + get_rr_node_side_and_index_in_sb_info(drive_rr_node, (*cur_sb_info), IN_PORT, &side, &index); + /* We need to be sure that drive_rr_node is part of the SB */ + assert((-1 != index)&&(-1 != side)); + dump_verilog_switch_box_chan_port(fp, cur_sb_info, side, drive_rr_node, IN_PORT); + break; + /* SOURCE is invalid as well */ + default: /* IPIN, SINK are invalid*/ + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", + __FILE__, __LINE__); + exit(1); + } + + /* END */ + fprintf(fp, ";\n"); + + return; +} + +/* Print the SPICE netlist of multiplexer that drive this rr_node */ +void dump_verilog_switch_box_mux(FILE* fp, + t_sb* cur_sb_info, + int chan_side, + t_rr_node* cur_rr_node, + int mux_size, + t_rr_node** drive_rr_nodes, + int switch_index) { + int i, inode, side, index, input_cnt = 0; + int grid_x, grid_y; + t_spice_model* verilog_model = NULL; + int mux_level, path_id, cur_num_sram; + int num_mux_sram_bits = 0; + int* mux_sram_bits = NULL; + int num_mux_conf_bits = 0; + int num_mux_reserved_conf_bits = 0; + int cur_bl, cur_wl; + t_spice_model* mem_model = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > cur_sb_info->x))&&(!(cur_sb_info->x > (nx + 1)))); + assert((!(0 > cur_sb_info->y))&&(!(cur_sb_info->y > (ny + 1)))); + + /* Check current rr_node is CHANX or CHANY*/ + assert((CHANX == cur_rr_node->type)||(CHANY == cur_rr_node->type)); + + /* Allocate drive_rr_nodes according to the fan-in*/ + assert((2 == mux_size)||(2 < mux_size)); + + /* Get verilog model*/ + verilog_model = switch_inf[switch_index].spice_model; + /* Specify the input bus */ + fprintf(fp, "wire [0:%d] %s_size%d_%d_inbus;\n", + mux_size - 1, + verilog_model->prefix, mux_size, verilog_model->cnt); + + /* Input ports*/ + /* Connect input ports to bus */ + for (inode = 0; inode < mux_size; inode++) { + switch (drive_rr_nodes[inode]->type) { + /* case SOURCE: */ + case OPIN: + /* Indicate a CLB Outpin*/ + /* Search all the sides of a SB, see this drive_rr_node is an INPUT of this SB */ + get_rr_node_side_and_index_in_sb_info(drive_rr_nodes[inode], (*cur_sb_info), IN_PORT, &side, &index); + /* We need to be sure that drive_rr_node is part of the SB */ + if (!((-1 != index)&&(-1 != side))) { + assert((-1 != index)&&(-1 != side)); + } + /* Find grid_x and grid_y */ + grid_x = drive_rr_nodes[inode]->xlow; + grid_y = drive_rr_nodes[inode]->ylow; /*Plus the offset in function fprint_grid_side_pin_with_given_index */ + /* Print a grid pin */ + fprintf(fp, "assign %s_size%d_%d_inbus[%d] = ", + verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt); + dump_verilog_grid_side_pin_with_given_index(fp, IPIN, drive_rr_nodes[inode]->ptc_num, + cur_sb_info->opin_rr_node_grid_side[side][index], + grid_x, grid_y, FALSE); + fprintf(fp, ";\n"); + input_cnt++; + break; + case CHANX: + case CHANY: + /* Should be an input ! */ + get_rr_node_side_and_index_in_sb_info(drive_rr_nodes[inode], (*cur_sb_info), IN_PORT, &side, &index); + /* We need to be sure that drive_rr_node is part of the SB */ + assert((-1 != index)&&(-1 != side)); + fprintf(fp, "assign %s_size%d_%d_inbus[%d] = ", + verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt); + dump_verilog_switch_box_chan_port(fp, cur_sb_info, side, drive_rr_nodes[inode], IN_PORT); + fprintf(fp, ";\n"); + input_cnt++; + break; + default: /* IPIN, SINK are invalid*/ + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", + __FILE__, __LINE__); + exit(1); + } + } + assert(input_cnt == mux_size); + + /* Print SRAMs that configure this MUX */ + /* cur_num_sram = sram_verilog_model->cnt; */ + cur_num_sram = get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info); + get_sram_orgz_info_num_blwl(sram_verilog_orgz_info, &cur_bl, &cur_wl); + /* connect to reserved BL/WLs ? */ + num_mux_reserved_conf_bits = count_num_reserved_conf_bits_one_spice_model(verilog_model, + sram_verilog_orgz_info->type, + mux_size); + /* Get the number of configuration bits required by this MUX */ + num_mux_conf_bits = count_num_conf_bits_one_spice_model(verilog_model, + sram_verilog_orgz_info->type, + mux_size); + + /* Dump the configuration port bus */ + dump_verilog_mux_config_bus(fp, verilog_model, sram_verilog_orgz_info, + mux_size, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits); + + /* Now it is the time print the SPICE netlist of MUX*/ + fprintf(fp, "%s_size%d %s_size%d_%d_ (", + verilog_model->prefix, mux_size, + verilog_model->prefix, mux_size, verilog_model->cnt); + + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE)) { + fprintf(fp, ",\n"); + } + + fprintf(fp, "%s_size%d_%d_inbus, ", + verilog_model->prefix, mux_size, verilog_model->cnt); + + /* Output port */ + dump_verilog_switch_box_chan_port(fp, cur_sb_info, chan_side, cur_rr_node, OUT_PORT); + /* Add a comma because dump_verilog_switch_box_chan_port does not add so */ + fprintf(fp, ", "); + + /* Different design technology requires different configuration bus! */ + dump_verilog_mux_config_bus_ports(fp, verilog_model, sram_verilog_orgz_info, + mux_size, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits); + + fprintf(fp, ");\n"); + + /* Configuration bits for this MUX*/ + path_id = -1; + for (inode = 0; inode < mux_size; inode++) { + if (drive_rr_nodes[inode] == &(rr_node[cur_rr_node->prev_node])) { + path_id = inode; + break; + } + } + + if (!((-1 != path_id)&&(path_id < mux_size))) { + assert((-1 != path_id)&&(path_id < mux_size)); + } + + /* Depend on both technology and structure of this MUX*/ + switch (verilog_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + decode_cmos_mux_sram_bits(verilog_model, mux_size, path_id, &num_mux_sram_bits, &mux_sram_bits, &mux_level); + break; + case SPICE_MODEL_DESIGN_RRAM: + decode_verilog_rram_mux(verilog_model, mux_size, path_id, &num_mux_sram_bits, &mux_sram_bits, &mux_level); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology for verilog model (%s)!\n", + __FILE__, __LINE__, verilog_model->name); + exit(1); + } + + /* Print the encoding in SPICE netlist for debugging */ + switch (verilog_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + fprintf(fp, "//----- SRAM bits for MUX[%d], level=%d, select_path_id=%d. -----\n", + verilog_model->cnt, mux_level, path_id); + fprintf(fp, "//----- From LSB(LEFT) TO MSB (RIGHT) -----\n"); + fprintf(fp, "//-----"); + fprint_commented_sram_bits(fp, num_mux_sram_bits, mux_sram_bits); + fprintf(fp, "-----\n"); + break; + case SPICE_MODEL_DESIGN_RRAM: + fprintf(fp, "//----- BL/WL bits for 4T1R MUX[%d], level=%d, select_path_id=%d. -----\n", + verilog_model->cnt, mux_level, path_id); + fprintf(fp, "//----- From LSB(LEFT) TO MSB (RIGHT) -----\n"); + fprintf(fp, "//---- BL: "); + fprint_commented_sram_bits(fp, num_mux_sram_bits/2, mux_sram_bits); + fprintf(fp, "-----\n"); + fprintf(fp, "//----- From LSB(LEFT) TO MSB (RIGHT) -----\n"); + fprintf(fp, "//---- WL: "); + fprint_commented_sram_bits(fp, num_mux_sram_bits/2, mux_sram_bits + num_mux_sram_bits/2); + fprintf(fp, "-----\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology for verilog model (%s)!\n", + __FILE__, __LINE__, verilog_model->name); + } + + /* Store the configuraion bit to linked-list */ + add_mux_conf_bits_to_llist(mux_size, sram_verilog_orgz_info, + num_mux_sram_bits, mux_sram_bits, + verilog_model); + + get_sram_orgz_info_mem_model(sram_verilog_orgz_info, &mem_model); + /* Dump sram modules */ + switch (verilog_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + /* SRAM-based MUX required dumping SRAMs! */ + for (i = 0; i < num_mux_sram_bits; i++) { + dump_verilog_mux_sram_submodule(fp, sram_verilog_orgz_info, verilog_model, mux_size, + mem_model); /* use the mem_model in sram_verilog_orgz_info */ + } + break; + case SPICE_MODEL_DESIGN_RRAM: + /* RRAM-based MUX does not need any SRAM dumping + * But we have to get the number of configuration bits required by this MUX + * and update the number of memory bits + */ + update_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info, cur_num_sram + num_mux_conf_bits); + update_sram_orgz_info_num_blwl(sram_verilog_orgz_info, + cur_bl + num_mux_conf_bits, + cur_wl + num_mux_conf_bits); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology for verilog model (%s)!\n", + __FILE__, __LINE__, verilog_model->name); + } + + + /* update sram counter */ + verilog_model->cnt++; + + /* Free */ + my_free(mux_sram_bits); + + return; +} + +/* Count the number of configuration bits of a rr_node*/ +int count_verilog_switch_box_interc_conf_bits(int switch_box_x, int switch_box_y, int chan_side, + t_rr_node* cur_rr_node) { + int num_conf_bits = 0; + int switch_idx = 0; + int num_drive_rr_nodes = 0; + + if (NULL == cur_rr_node) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])NULL cur_rr_node!\n", + __FILE__, __LINE__); + exit(1); + return num_conf_bits; + } + + /* Determine if the interc lies inside a channel wire, that is interc between segments */ + if (1 == is_sb_interc_between_segments(switch_box_x, switch_box_y, cur_rr_node, chan_side)) { + num_drive_rr_nodes = 0; + } else { + num_drive_rr_nodes = cur_rr_node->num_drive_rr_nodes; + } + + /* fan_in >= 2 implies a MUX and requires configuration bits */ + if (2 > num_drive_rr_nodes) { + return num_conf_bits; + } else { + switch_idx = cur_rr_node->drive_switches[0]; + assert(-1 < switch_idx); + assert(SPICE_MODEL_MUX == switch_inf[switch_idx].spice_model->type); + num_conf_bits = count_num_conf_bits_one_spice_model(switch_inf[switch_idx].spice_model, + sram_verilog_orgz_info->type, + num_drive_rr_nodes); + return num_conf_bits; + } +} + +/* Count the number of reserved configuration bits of a rr_node*/ +int count_verilog_switch_box_interc_reserved_conf_bits(int switch_box_x, int switch_box_y, int chan_side, + t_rr_node* cur_rr_node) { + int num_reserved_conf_bits = 0; + int switch_idx = 0; + int num_drive_rr_nodes = 0; + + if (NULL == cur_rr_node) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])NULL cur_rr_node!\n", + __FILE__, __LINE__); + exit(1); + return num_reserved_conf_bits; + } + + /* Determine if the interc lies inside a channel wire, that is interc between segments */ + if (1 == is_sb_interc_between_segments(switch_box_x, switch_box_y, cur_rr_node, chan_side)) { + num_drive_rr_nodes = 0; + } else { + num_drive_rr_nodes = cur_rr_node->num_drive_rr_nodes; + } + + /* fan_in >= 2 implies a MUX and requires configuration bits */ + if (2 > num_drive_rr_nodes) { + return num_reserved_conf_bits; + } else { + switch_idx = cur_rr_node->drive_switches[0]; + assert(-1 < switch_idx); + assert(SPICE_MODEL_MUX == switch_inf[switch_idx].spice_model->type); + num_reserved_conf_bits = + count_num_reserved_conf_bits_one_spice_model(switch_inf[switch_idx].spice_model, + sram_verilog_orgz_info->type, + num_drive_rr_nodes); + return num_reserved_conf_bits; + } +} + + +void dump_verilog_switch_box_interc(FILE* fp, + t_sb* cur_sb_info, + int chan_side, + t_rr_node* cur_rr_node) { + int sb_x, sb_y; + int num_drive_rr_nodes = 0; + t_rr_node** drive_rr_nodes = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + sb_x = cur_sb_info->x; + sb_y = cur_sb_info->y; + + /* Check */ + assert((!(0 > sb_x))&&(!(sb_x > (nx + 1)))); + assert((!(0 > sb_y))&&(!(sb_y > (ny + 1)))); + /* + find_drive_rr_nodes_switch_box(switch_box_x, switch_box_y, cur_rr_node, chan_side, 0, + &num_drive_rr_nodes, &drive_rr_nodes, &switch_index); + */ + + /* Determine if the interc lies inside a channel wire, that is interc between segments */ + if (1 == is_sb_interc_between_segments(sb_x, sb_y, cur_rr_node, chan_side)) { + num_drive_rr_nodes = 0; + drive_rr_nodes = NULL; + } else { + num_drive_rr_nodes = cur_rr_node->num_drive_rr_nodes; + drive_rr_nodes = cur_rr_node->drive_rr_nodes; + } + + if (0 == num_drive_rr_nodes) { + /* Print a special direct connection*/ + dump_verilog_switch_box_short_interc(fp, cur_sb_info, chan_side, cur_rr_node, + num_drive_rr_nodes, cur_rr_node); + } else if (1 == num_drive_rr_nodes) { + /* Print a direct connection*/ + dump_verilog_switch_box_short_interc(fp, cur_sb_info, chan_side, cur_rr_node, + num_drive_rr_nodes, drive_rr_nodes[0]); + } else if (1 < num_drive_rr_nodes) { + /* Print the multiplexer, fan_in >= 2 */ + dump_verilog_switch_box_mux(fp, cur_sb_info, chan_side, cur_rr_node, + num_drive_rr_nodes, drive_rr_nodes, + cur_rr_node->drive_switches[0]); + } /*Nothing should be done else*/ + + /* Free */ + + return; +} + +/* Count the number of configuration bits of a Switch Box */ +int count_verilog_switch_box_reserved_conf_bits(t_sb* cur_sb_info) { + int side, itrack; + int num_reserved_conf_bits = 0; + int temp_num_reserved_conf_bits = 0; + + for (side = 0; side < cur_sb_info->num_sides; side++) { + for (itrack = 0; itrack < cur_sb_info->chan_width[side]; itrack++) { + switch (cur_sb_info->chan_rr_node_direction[side][itrack]) { + case OUT_PORT: + temp_num_reserved_conf_bits = + count_verilog_switch_box_interc_reserved_conf_bits(cur_sb_info->x, cur_sb_info->y, side, + cur_sb_info->chan_rr_node[side][itrack]); + /* Always select the largest number of reserved conf_bits */ + if (temp_num_reserved_conf_bits > num_reserved_conf_bits) { + num_reserved_conf_bits = temp_num_reserved_conf_bits; + } + break; + case IN_PORT: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of port sb[%d][%d] Channel node[%d] track[%d]!\n", + __FILE__, __LINE__, cur_sb_info->x, cur_sb_info->y, side, itrack); + exit(1); + } + } + } + + return num_reserved_conf_bits; +} + +/* Count the number of configuration bits of a Switch Box */ +int count_verilog_switch_box_conf_bits(t_sb* cur_sb_info) { + int side, itrack; + int num_conf_bits = 0; + + for (side = 0; side < cur_sb_info->num_sides; side++) { + for (itrack = 0; itrack < cur_sb_info->chan_width[side]; itrack++) { + switch (cur_sb_info->chan_rr_node_direction[side][itrack]) { + case OUT_PORT: + num_conf_bits += count_verilog_switch_box_interc_conf_bits(cur_sb_info->x, cur_sb_info->y, side, + cur_sb_info->chan_rr_node[side][itrack]); + break; + case IN_PORT: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of port sb[%d][%d] Channel node[%d] track[%d]!\n", + __FILE__, __LINE__, cur_sb_info->x, cur_sb_info->y, side, itrack); + exit(1); + } + } + } + + return num_conf_bits; +} + +/* Task: Print the subckt of a Switch Box. + * A Switch Box subckt consists of following ports: + * 1. Channel Y [x][y] inputs + * 2. Channel X [x+1][y] inputs + * 3. Channel Y [x][y-1] outputs + * 4. Channel X [x][y] outputs + * 5. Grid[x][y+1] Right side outputs pins + * 6. Grid[x+1][y+1] Left side output pins + * 7. Grid[x+1][y+1] Bottom side output pins + * 8. Grid[x+1][y] Top side output pins + * 9. Grid[x+1][y] Left side output pins + * 10. Grid[x][y] Right side output pins + * 11. Grid[x][y] Top side output pins + * 12. Grid[x][y+1] Bottom side output pins + * + * -------------- -------------- + * | | | | + * | Grid | ChanY | Grid | + * | [x][y+1] | [x][y+1] | [x+1][y+1] | + * | | | | + * -------------- -------------- + * ---------- + * ChanX | Switch | ChanX + * [x][y] | Box | [x+1][y] + * | [x][y] | + * ---------- + * -------------- -------------- + * | | | | + * | Grid | ChanY | Grid | + * | [x][y] | [x][y] | [x+1][y] | + * | | | | + * -------------- -------------- + */ +void dump_verilog_routing_switch_box_subckt(FILE* fp, t_sb* cur_sb_info, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices) { + int itrack, inode, side, ix, iy, x, y; + int cur_num_sram, num_conf_bits, num_reserved_conf_bits, esti_sram_cnt; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > cur_sb_info->x))&&(!(cur_sb_info->x > (nx + 1)))); + assert((!(0 > cur_sb_info->y))&&(!(cur_sb_info->y > (ny + 1)))); + + x = cur_sb_info->x; + y = cur_sb_info->y; + + /* Count the number of configuration bits to be consumed by this Switch block */ + num_conf_bits = count_verilog_switch_box_conf_bits(cur_sb_info); + /* Count the number of reserved configuration bits to be consumed by this Switch block */ + num_reserved_conf_bits = count_verilog_switch_box_reserved_conf_bits(cur_sb_info); + /* Estimate the sram_verilog_model->cnt */ + cur_num_sram = get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info); + esti_sram_cnt = cur_num_sram + num_conf_bits; + /* Record the index */ + cur_sb_info->num_reserved_conf_bits = num_reserved_conf_bits; + cur_sb_info->conf_bits_lsb = cur_num_sram; + cur_sb_info->conf_bits_msb = cur_num_sram + num_conf_bits; + + /* Comment lines */ + fprintf(fp, "//----- Verilog Module of Switch Box[%d][%d] -----\n", cur_sb_info->x, cur_sb_info->y); + /* Print the definition of subckt*/ + fprintf(fp, "module sb_%d__%d_ ( \n", cur_sb_info->x, cur_sb_info->y); + fprintf(fp, "\n"); + /* dump global ports */ + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + fprintf(fp, ",\n"); + } + + for (side = 0; side < cur_sb_info->num_sides; side++) { + fprintf(fp, "//----- Inputs/outputs of %s side -----\n",convert_side_index_to_string(side)); + determine_sb_port_coordinator((*cur_sb_info), side, &ix, &iy); + + for (itrack = 0; itrack < cur_sb_info->chan_width[side]; itrack++) { + switch (cur_sb_info->chan_rr_node_direction[side][itrack]) { + case OUT_PORT: + fprintf(fp, " output %s_%d__%d__out_%d_,\n", + convert_chan_type_to_string(cur_sb_info->chan_rr_node[side][itrack]->type), + ix, iy, itrack); + break; + case IN_PORT: + fprintf(fp, " input %s_%d__%d__in_%d_,\n", + convert_chan_type_to_string(cur_sb_info->chan_rr_node[side][itrack]->type), + ix, iy, itrack); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of chany[%d][%d]_track[%d]!\n", + __FILE__, __LINE__, x, y + 1, itrack); + exit(1); + } + } + /* Dump OPINs of adjacent CLBs */ + for (inode = 0; inode < cur_sb_info->num_opin_rr_nodes[side]; inode++) { + dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an input of a SB */ + cur_sb_info->opin_rr_node[side][inode]->ptc_num, + cur_sb_info->opin_rr_node_grid_side[side][inode], + cur_sb_info->opin_rr_node[side][inode]->xlow, + cur_sb_info->opin_rr_node[side][inode]->ylow, + TRUE); /* Dump the direction of the port ! */ + } + } + + /* Put down configuration port */ + /* output of each configuration bit */ + /* Reserved sram ports */ + dump_verilog_reserved_sram_ports(fp, sram_verilog_orgz_info, + 0, cur_sb_info->num_reserved_conf_bits - 1, + VERILOG_PORT_INPUT); + if (0 < cur_sb_info->num_reserved_conf_bits) { + fprintf(fp, ",\n"); + } + /* Normal sram ports */ + dump_verilog_sram_ports(fp, sram_verilog_orgz_info, + cur_sb_info->conf_bits_lsb, + cur_sb_info->conf_bits_msb - 1, + VERILOG_PORT_INPUT); + fprintf(fp, "); \n"); + + /* Local wires for memory configurations */ + /* + dump_verilog_sram_config_bus_internal_wires(fp, sram_verilog_orgz_info, + cur_sb_info->conf_bits_lsb, cur_sb_info->conf_bits_msb - 1); + */ + + /* Put down all the multiplexers */ + for (side = 0; side < cur_sb_info->num_sides; side++) { + fprintf(fp, "//----- %s side Multiplexers -----\n", + convert_side_index_to_string(side)); + for (itrack = 0; itrack < cur_sb_info->chan_width[side]; itrack++) { + assert((CHANX == cur_sb_info->chan_rr_node[side][itrack]->type) + ||(CHANY == cur_sb_info->chan_rr_node[side][itrack]->type)); + /* We care INC_DIRECTION tracks at this side*/ + if (OUT_PORT == cur_sb_info->chan_rr_node_direction[side][itrack]) { + dump_verilog_switch_box_interc(fp, cur_sb_info, side, cur_sb_info->chan_rr_node[side][itrack]); + } + } + } + + fprintf(fp, "endmodule\n"); + + /* Comment lines */ + fprintf(fp, "//----- END Verilog Module of Switch Box[%d][%d] -----\n\n", x, y); + + /* Check */ + assert(esti_sram_cnt == get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info)); + + /* Free chan_rr_nodes */ + + return; +} + +/* Count the number of configuration bits of a rr_node*/ +int count_verilog_connection_box_interc_conf_bits(t_rr_node* cur_rr_node) { + int num_conf_bits = 0; + int switch_idx = 0; + int num_drive_rr_nodes = cur_rr_node->num_drive_rr_nodes; + + if (NULL == cur_rr_node) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])NULL cur_rr_node!\n", + __FILE__, __LINE__); + exit(1); + return num_conf_bits; + } + + /* fan_in >= 2 implies a MUX and requires configuration bits */ + if (2 > num_drive_rr_nodes) { + return num_conf_bits; + } else { + switch_idx = cur_rr_node->drive_switches[0]; + assert(-1 < switch_idx); + assert(SPICE_MODEL_MUX == switch_inf[switch_idx].spice_model->type); + num_conf_bits = count_num_conf_bits_one_spice_model(switch_inf[switch_idx].spice_model, + sram_verilog_orgz_info->type, + num_drive_rr_nodes); + return num_conf_bits; + } +} + +/* Count the number of configuration bits of a rr_node*/ +int count_verilog_connection_box_interc_reserved_conf_bits(t_rr_node* cur_rr_node) { + int num_reserved_conf_bits = 0; + int switch_idx = 0; + int num_drive_rr_nodes = cur_rr_node->num_drive_rr_nodes; + + if (NULL == cur_rr_node) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])NULL cur_rr_node!\n", + __FILE__, __LINE__); + exit(1); + return num_reserved_conf_bits; + } + + /* fan_in >= 2 implies a MUX and requires configuration bits */ + if (2 > num_drive_rr_nodes) { + return num_reserved_conf_bits; + } else { + switch_idx = cur_rr_node->drive_switches[0]; + assert(-1 < switch_idx); + assert(SPICE_MODEL_MUX == switch_inf[switch_idx].spice_model->type); + num_reserved_conf_bits = + count_num_reserved_conf_bits_one_spice_model(switch_inf[switch_idx].spice_model, + sram_verilog_orgz_info->type, + num_drive_rr_nodes); + return num_reserved_conf_bits; + } +} + + +int count_verilog_connection_box_one_side_conf_bits(int num_ipin_rr_nodes, + t_rr_node** ipin_rr_node) { + int num_conf_bits = 0; + int inode; + + for (inode = 0; inode < num_ipin_rr_nodes; inode++) { + num_conf_bits += count_verilog_connection_box_interc_conf_bits(ipin_rr_node[inode]); + } + + return num_conf_bits; +} + +int count_verilog_connection_box_one_side_reserved_conf_bits(int num_ipin_rr_nodes, + t_rr_node** ipin_rr_node) { + int num_reserved_conf_bits = 0; + int temp_num_reserved_conf_bits = 0; + int inode; + + for (inode = 0; inode < num_ipin_rr_nodes; inode++) { + temp_num_reserved_conf_bits = count_verilog_connection_box_interc_reserved_conf_bits(ipin_rr_node[inode]); + if (temp_num_reserved_conf_bits > num_reserved_conf_bits) { + num_reserved_conf_bits = temp_num_reserved_conf_bits; + } + } + + return num_reserved_conf_bits; +} + +/* SRC rr_node is the IPIN of a grid.*/ +void dump_verilog_connection_box_short_interc(FILE* fp, + t_cb* cur_cb_info, + t_rr_node* src_rr_node) { + t_rr_node* drive_rr_node = NULL; + int iedge, check_flag; + int xlow, ylow, height, side, index; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > cur_cb_info->x))&&(!(cur_cb_info->x > (nx + 1)))); + assert((!(0 > cur_cb_info->y))&&(!(cur_cb_info->y > (ny + 1)))); + assert(1 == src_rr_node->fan_in); + + /* Check the driver*/ + drive_rr_node = &(rr_node[src_rr_node->prev_node]); + assert((CHANX == drive_rr_node->type)||(CHANY == drive_rr_node->type)); + check_flag = 0; + for (iedge = 0; iedge < drive_rr_node->num_edges; iedge++) { + if (src_rr_node == &(rr_node[drive_rr_node->edges[iedge]])) { + check_flag++; + } + } + assert(1 == check_flag); + + xlow = src_rr_node->xlow; + ylow = src_rr_node->ylow; + height = grid[xlow][ylow].offset; + + /* Call the zero-resistance model */ + switch(cur_cb_info->type) { + case CHANX: + fprintf(fp, "//----- short connection cbx[%d][%d]_grid[%d][%d]_pin[%d] -----\n", + cur_cb_info->x, cur_cb_info->y, xlow, ylow + height, src_rr_node->ptc_num); + break; + case CHANY: + fprintf(fp, "//----- short connection cby[%d][%d]_grid[%d][%d]_pin[%d] ------\n", + cur_cb_info->x, cur_cb_info->y, xlow, ylow + height, src_rr_node->ptc_num); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); + exit(1); + } + + fprintf(fp, "assign "); + /* output port -- > connect to the output at middle point of a channel */ + fprintf(fp, "%s_%d__%d__midout_%d_ ", + convert_chan_type_to_string(drive_rr_node->type), + cur_cb_info->x, cur_cb_info->y, drive_rr_node->ptc_num); + fprintf(fp, "= "); + + /* Input port*/ + assert(IPIN == src_rr_node->type); + /* Search all the sides of a SB, see this drive_rr_node is an INPUT of this SB */ + get_rr_node_side_and_index_in_cb_info(src_rr_node, (*cur_cb_info), OUT_PORT, &side, &index); + /* We need to be sure that drive_rr_node is part of the SB */ + assert((-1 != index)&&(-1 != side)); + dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an output of a Connection Box */ + cur_cb_info->ipin_rr_node[side][index]->ptc_num, + cur_cb_info->ipin_rr_node_grid_side[side][index], + xlow, ylow, /* Coordinator of Grid */ + FALSE); /* Do not specify the direction of this pin */ + + /* End */ + fprintf(fp, "\n"); + + return; +} + +void dump_verilog_connection_box_mux(FILE* fp, + t_cb* cur_cb_info, + t_rr_node* src_rr_node) { + int i, mux_size, cur_num_sram, input_cnt = 0; + t_rr_node** drive_rr_nodes = NULL; + int inode, mux_level, path_id, switch_index; + t_spice_model* verilog_model = NULL; + int num_mux_sram_bits = 0; + int* mux_sram_bits = NULL; + t_rr_type drive_rr_node_type = NUM_RR_TYPES; + int xlow, ylow, side, index; + int num_mux_conf_bits = 0; + int num_mux_reserved_conf_bits = 0; + int cur_bl, cur_wl; + t_spice_model* mem_model = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert((!(0 > cur_cb_info->x))&&(!(cur_cb_info->x > (nx + 1)))); + assert((!(0 > cur_cb_info->y))&&(!(cur_cb_info->y > (ny + 1)))); + + /* Find drive_rr_nodes*/ + mux_size = src_rr_node->num_drive_rr_nodes; + drive_rr_nodes = src_rr_node->drive_rr_nodes; + + /* Configuration bits for MUX*/ + path_id = -1; + for (inode = 0; inode < mux_size; inode++) { + if (drive_rr_nodes[inode] == &(rr_node[src_rr_node->prev_node])) { + path_id = inode; + break; + } + } + assert((-1 != path_id)&&(path_id < mux_size)); + + switch_index = src_rr_node->drive_switches[path_id]; + + verilog_model = switch_inf[switch_index].spice_model; + + /* Specify the input bus */ + fprintf(fp, "wire [0:%d] %s_size%d_%d_inbus;\n", + mux_size - 1, + verilog_model->prefix, mux_size, verilog_model->cnt); + + /* Check drive_rr_nodes type, should be the same*/ + for (inode = 0; inode < mux_size; inode++) { + if (NUM_RR_TYPES == drive_rr_node_type) { + drive_rr_node_type = drive_rr_nodes[inode]->type; + } else { + assert(drive_rr_node_type == drive_rr_nodes[inode]->type); + assert((CHANX == drive_rr_nodes[inode]->type)||(CHANY == drive_rr_nodes[inode]->type)); + } + } + /* input port*/ + for (inode = 0; inode < mux_size; inode++) { + fprintf(fp, "assign %s_size%d_%d_inbus[%d] = ", + verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt); + fprintf(fp, "%s_%d__%d__midout_%d_;\n", + convert_chan_type_to_string(drive_rr_nodes[inode]->type), + cur_cb_info->x, cur_cb_info->y, drive_rr_nodes[inode]->ptc_num); + input_cnt++; + } + assert(input_cnt == mux_size); + + /* Print SRAMs that configure this MUX */ + /* cur_num_sram = sram_verilog_model->cnt; */ + cur_num_sram = get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info); + get_sram_orgz_info_num_blwl(sram_verilog_orgz_info, &cur_bl, &cur_wl); + /* connect to reserved BL/WLs ? */ + num_mux_reserved_conf_bits = count_num_reserved_conf_bits_one_spice_model(verilog_model, + sram_verilog_orgz_info->type, + mux_size); + /* Get the number of configuration bits required by this MUX */ + num_mux_conf_bits = count_num_conf_bits_one_spice_model(verilog_model, + sram_verilog_orgz_info->type, + mux_size); + + /* Dump the configuration port bus */ + dump_verilog_mux_config_bus(fp, verilog_model, sram_verilog_orgz_info, + mux_size, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits); + + /* Call the MUX SPICE model */ + fprintf(fp, "%s_size%d %s_size%d_%d_ (", + verilog_model->name, mux_size, + verilog_model->prefix, mux_size, verilog_model->cnt); + + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE)) { + fprintf(fp, ",\n"); + } + + /* connect to input bus*/ + fprintf(fp, "%s_size%d_%d_inbus,", + verilog_model->prefix, mux_size, verilog_model->cnt); + + /* output port*/ + xlow = src_rr_node->xlow; + ylow = src_rr_node->ylow; + + assert(IPIN == src_rr_node->type); + /* Search all the sides of a CB, see this drive_rr_node is an INPUT of this SB */ + get_rr_node_side_and_index_in_cb_info(src_rr_node, (*cur_cb_info), OUT_PORT, &side, &index); + /* We need to be sure that drive_rr_node is part of the CB */ + assert((-1 != index)&&(-1 != side)); + dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an output of a connection box */ + cur_cb_info->ipin_rr_node[side][index]->ptc_num, + cur_cb_info->ipin_rr_node_grid_side[side][index], + xlow, ylow, /* Coordinator of Grid */ + FALSE); /* Do not specify the direction of port */ + fprintf(fp, ", "); + + /* Different design technology requires different configuration bus! */ + dump_verilog_mux_config_bus_ports(fp, verilog_model, sram_verilog_orgz_info, + mux_size, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits); + + + fprintf(fp, ");\n"); + + switch (verilog_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + decode_cmos_mux_sram_bits(verilog_model, mux_size, path_id, &num_mux_sram_bits, &mux_sram_bits, &mux_level); + break; + case SPICE_MODEL_DESIGN_RRAM: + decode_verilog_rram_mux(verilog_model, mux_size, path_id, &num_mux_sram_bits, &mux_sram_bits, &mux_level); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology for verilog model (%s)!\n", + __FILE__, __LINE__, verilog_model->name); + } + + /* Print the encoding in SPICE netlist for debugging */ + switch (verilog_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + fprintf(fp, "//----- SRAM bits for MUX[%d], level=%d, select_path_id=%d. -----\n", + verilog_model->cnt, mux_level, path_id); + fprintf(fp, "//----- From LSB(LEFT) TO MSB (RIGHT) -----\n"); + fprintf(fp, "//-----"); + fprint_commented_sram_bits(fp, num_mux_sram_bits, mux_sram_bits); + fprintf(fp, "-----\n"); + break; + case SPICE_MODEL_DESIGN_RRAM: + fprintf(fp, "//----- BL/WL bits for 4T1R MUX[%d], level=%d, select_path_id=%d. -----\n", + verilog_model->cnt, mux_level, path_id); + fprintf(fp, "//----- From LSB(LEFT) TO MSB (RIGHT) -----\n"); + fprintf(fp, "//---- BL: "); + fprint_commented_sram_bits(fp, num_mux_sram_bits/2, mux_sram_bits); + fprintf(fp, "-----\n"); + fprintf(fp, "//----- From LSB(LEFT) TO MSB (RIGHT) -----\n"); + fprintf(fp, "//---- WL: "); + fprint_commented_sram_bits(fp, num_mux_sram_bits/2, mux_sram_bits + num_mux_sram_bits/2); + fprintf(fp, "-----\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology for verilog model (%s)!\n", + __FILE__, __LINE__, verilog_model->name); + } + + /* Store the configuraion bit to linked-list */ + add_mux_conf_bits_to_llist(mux_size, sram_verilog_orgz_info, + num_mux_sram_bits, mux_sram_bits, + verilog_model); + + get_sram_orgz_info_mem_model(sram_verilog_orgz_info, &mem_model); + /* Dump sram modules */ + switch (verilog_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + /* SRAM-based MUX required dumping SRAMs! */ + for (i = 0; i < num_mux_sram_bits; i++) { + dump_verilog_mux_sram_submodule(fp, sram_verilog_orgz_info, verilog_model, mux_size, + mem_model); /* use the mem_model in sram_verilog_orgz_info */ + } + break; + case SPICE_MODEL_DESIGN_RRAM: + /* RRAM-based MUX does not need any SRAM dumping + * But we have to get the number of configuration bits required by this MUX + * and update the number of memory bits + */ + update_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info, cur_num_sram + num_mux_conf_bits); + update_sram_orgz_info_num_blwl(sram_verilog_orgz_info, + cur_bl + num_mux_conf_bits, + cur_wl + num_mux_conf_bits); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology for verilog model (%s)!\n", + __FILE__, __LINE__, verilog_model->name); + } + + /* update sram counter */ + verilog_model->cnt++; + + /* Free */ + my_free(mux_sram_bits); + + return; +} + +void dump_verilog_connection_box_interc(FILE* fp, + t_cb* cur_cb_info, + t_rr_node* src_rr_node) { + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > cur_cb_info->x))&&(!(cur_cb_info->x > (nx + 1)))); + assert((!(0 > cur_cb_info->y))&&(!(cur_cb_info->y > (ny + 1)))); + + if (1 == src_rr_node->fan_in) { + /* Print a direct connection*/ + dump_verilog_connection_box_short_interc(fp, cur_cb_info, src_rr_node); + } else if (1 < src_rr_node->fan_in) { + /* Print the multiplexer, fan_in >= 2 */ + dump_verilog_connection_box_mux(fp, cur_cb_info, src_rr_node); + } /*Nothing should be done else*/ + + return; +} + +/* Count the number of configuration bits of a connection box */ +int count_verilog_connection_box_conf_bits(t_cb* cur_cb_info) { + int side; + int side_cnt = 0; + int num_conf_bits = 0; + + for (side = 0; side < cur_cb_info->num_sides; side++) { + /* Bypass side with zero IPINs*/ + if (0 == cur_cb_info->num_ipin_rr_nodes[side]) { + continue; + } + side_cnt++; + assert(0 < cur_cb_info->num_ipin_rr_nodes[side]); + assert(NULL != cur_cb_info->ipin_rr_node[side]); + /* Count the number of configuration bits */ + num_conf_bits += count_verilog_connection_box_one_side_conf_bits(cur_cb_info->num_ipin_rr_nodes[side], cur_cb_info->ipin_rr_node[side]); + } + /* Make sure only 2 sides of IPINs are printed */ + assert((1 == side_cnt)||(2 == side_cnt)); + + return num_conf_bits; +} + +/* Count the number of reserved configuration bits of a connection box */ +int count_verilog_connection_box_reserved_conf_bits(t_cb* cur_cb_info) { + int side; + int side_cnt = 0; + int num_reserved_conf_bits = 0; + int temp_num_reserved_conf_bits = 0; + + for (side = 0; side < cur_cb_info->num_sides; side++) { + /* Bypass side with zero IPINs*/ + if (0 == cur_cb_info->num_ipin_rr_nodes[side]) { + continue; + } + side_cnt++; + assert(0 < cur_cb_info->num_ipin_rr_nodes[side]); + assert(NULL != cur_cb_info->ipin_rr_node[side]); + /* Count the number of reserved configuration bits */ + temp_num_reserved_conf_bits = count_verilog_connection_box_one_side_reserved_conf_bits(cur_cb_info->num_ipin_rr_nodes[side], cur_cb_info->ipin_rr_node[side]); + /* Only consider the largest reserved configuration bits */ + if (temp_num_reserved_conf_bits > num_reserved_conf_bits) { + num_reserved_conf_bits = temp_num_reserved_conf_bits; + } + } + /* Make sure only 2 sides of IPINs are printed */ + assert((1 == side_cnt)||(2 == side_cnt)); + + return num_reserved_conf_bits; +} + + +/* Print connection boxes + * Print the sub-circuit of a connection Box (Type: [CHANX|CHANY]) + * Actually it is very similiar to switch box but + * the difference is connection boxes connect Grid INPUT Pins to channels + * TODO: merge direct connections into CB + * -------------- -------------- + * | | | | + * | Grid | ChanY | Grid | + * | [x][y+1] | [x][y] | [x+1][y+1] | + * | | Connection | | + * -------------- Box_Y[x][y] -------------- + * ---------- + * ChanX | Switch | ChanX + * [x][y] | Box | [x+1][y] + * Connection | [x][y] | Connection + * Box_X[x][y] ---------- Box_X[x+1][y] + * -------------- -------------- + * | | | | + * | Grid | ChanY | Grid | + * | [x][y] | [x][y-1] | [x+1][y] | + * | | Connection | | + * --------------Box_Y[x][y-1]-------------- + */ +void dump_verilog_routing_connection_box_subckt(FILE* fp, t_cb* cur_cb_info, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices) { + int itrack, inode, side, x, y; + int side_cnt = 0; + + int cur_num_sram, num_conf_bits, num_reserved_conf_bits, esti_sram_cnt; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert((!(0 > cur_cb_info->x))&&(!(cur_cb_info->x > (nx + 1)))); + assert((!(0 > cur_cb_info->y))&&(!(cur_cb_info->y > (ny + 1)))); + + x= cur_cb_info->x; + y= cur_cb_info->y; + + /* Print the definition of subckt*/ + /* Identify the type of connection box */ + switch(cur_cb_info->type) { + case CHANX: + /* Comment lines */ + fprintf(fp, "//----- Verilog Module of Connection Box -X direction [%d][%d] -----\n", x, y); + fprintf(fp, "module "); + fprintf(fp, "cbx_%d__%d_ ", cur_cb_info->x, cur_cb_info->y); + break; + case CHANY: + /* Comment lines */ + fprintf(fp, "//----- Verilog Module of Connection Box -Y direction [%d][%d] -----\n", x, y); + fprintf(fp, "module "); + fprintf(fp, "cby_%d__%d_ ", cur_cb_info->x, cur_cb_info->y); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); + exit(1); + } + + fprintf(fp, "(\n"); + /* dump global ports */ + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + fprintf(fp, ",\n"); + } + /* Print the ports of channels*/ + /*connect to the mid point of a track*/ + /* Get the chan_rr_nodes: Only one side of a cb_info has chan_rr_nodes*/ + side_cnt = 0; + for (side = 0; side < cur_cb_info->num_sides; side++) { + /* Bypass side with zero channel width */ + if (0 == cur_cb_info->chan_width[side]) { + continue; + } + assert (0 < cur_cb_info->chan_width[side]); + side_cnt++; + for (itrack = 0; itrack < cur_cb_info->chan_width[side]; itrack++) { + fprintf(fp, "input %s_%d__%d__midout_%d_, \n", + convert_chan_type_to_string(cur_cb_info->type), + cur_cb_info->x, cur_cb_info->y, itrack); + fprintf(fp, "\n"); + } + } + /*check side_cnt */ + assert((1 == side_cnt)||(2 == side_cnt)); + + side_cnt = 0; + /* Print the ports of grids*/ + /* only check ipin_rr_nodes of cur_cb_info */ + for (side = 0; side < cur_cb_info->num_sides; side++) { + /* Bypass side with zero IPINs*/ + if (0 == cur_cb_info->num_ipin_rr_nodes[side]) { + continue; + } + side_cnt++; + assert(0 < cur_cb_info->num_ipin_rr_nodes[side]); + assert(NULL != cur_cb_info->ipin_rr_node[side]); + for (inode = 0; inode < cur_cb_info->num_ipin_rr_nodes[side]; inode++) { + /* Print each INPUT Pins of a grid */ + dump_verilog_grid_side_pin_with_given_index(fp, IPIN, /* This is an output of a connection box */ + cur_cb_info->ipin_rr_node[side][inode]->ptc_num, + cur_cb_info->ipin_rr_node_grid_side[side][inode], + cur_cb_info->ipin_rr_node[side][inode]->xlow, + cur_cb_info->ipin_rr_node[side][inode]->ylow, + TRUE); + + fprintf(fp, "\n"); + } + } + /* Make sure only 2 sides of IPINs are printed */ + assert((1 == side_cnt)||(2 == side_cnt)); + + /* Count the number of configuration bits */ + /* Count the number of configuration bits to be consumed by this Switch block */ + num_conf_bits = count_verilog_connection_box_conf_bits(cur_cb_info); + /* Count the number of reserved configuration bits to be consumed by this Switch block */ + num_reserved_conf_bits = count_verilog_connection_box_reserved_conf_bits(cur_cb_info); + /* Estimate the sram_verilog_model->cnt */ + cur_num_sram = get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info); + esti_sram_cnt = cur_num_sram + num_conf_bits; + /* Record index */ + cur_cb_info->num_reserved_conf_bits = num_reserved_conf_bits; + cur_cb_info->conf_bits_lsb = cur_num_sram; + cur_cb_info->conf_bits_msb = cur_num_sram + num_conf_bits; + + /* Put down configuration port */ + /* output of each configuration bit */ + /* Reserved sram ports */ + dump_verilog_reserved_sram_ports(fp, sram_verilog_orgz_info, + 0, cur_cb_info->num_reserved_conf_bits - 1, + VERILOG_PORT_INPUT); + if (0 < cur_cb_info->num_reserved_conf_bits) { + fprintf(fp, ",\n"); + } + /* Normal sram ports */ + dump_verilog_sram_ports(fp, sram_verilog_orgz_info, + cur_cb_info->conf_bits_lsb, + cur_cb_info->conf_bits_msb - 1, + VERILOG_PORT_INPUT); + /* subckt definition ends with svdd and sgnd*/ + fprintf(fp, ");\n"); + + /* Local wires for memory configurations */ + /* + dump_verilog_sram_config_bus_internal_wires(fp, sram_verilog_orgz_info, + cur_cb_info->conf_bits_lsb, cur_cb_info->conf_bits_msb - 1); + */ + + /* Record LSB and MSB of reserved_conf_bits and normal conf_bits */ + + /* Print multiplexers or direct interconnect*/ + side_cnt = 0; + for (side = 0; side < cur_cb_info->num_sides; side++) { + /* Bypass side with zero IPINs*/ + if (0 == cur_cb_info->num_ipin_rr_nodes[side]) { + continue; + } + side_cnt++; + assert(0 < cur_cb_info->num_ipin_rr_nodes[side]); + assert(NULL != cur_cb_info->ipin_rr_node[side]); + for (inode = 0; inode < cur_cb_info->num_ipin_rr_nodes[side]; inode++) { + dump_verilog_connection_box_interc(fp, cur_cb_info, cur_cb_info->ipin_rr_node[side][inode]); + } + } + + fprintf(fp, "endmodule\n"); + + /* Comment lines */ + switch(cur_cb_info->type) { + case CHANX: + fprintf(fp, "//----- END Verilog Module of Connection Box -X direction [%d][%d] -----\n\n", x, y); + break; + case CHANY: + fprintf(fp, "//----- END Verilog Module of Connection Box -Y direction [%d][%d] -----\n\n", x, y); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert(esti_sram_cnt == get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info)); + + /* Free */ + + return; +} + + +/* Top Function*/ +/* Build the routing resource SPICE sub-circuits*/ +void dump_verilog_routing_resources(char* subckt_dir, + t_arch arch, + t_det_routing_arch* routing_arch, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices) { + FILE* fp = NULL; + char* verilog_name = my_strcat(subckt_dir, routing_verilog_file_name); + int ix, iy; + + assert(UNI_DIRECTIONAL == routing_arch->directionality); + + /* Create FILE */ + fp = fopen(verilog_name, "w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create verilog netlist %s",__FILE__, __LINE__, routing_verilog_file_name); + exit(1); + } + dump_verilog_file_header(fp,"Routing Resources"); + + /* Two major tasks: + * 1. Generate sub-circuits for Routing Channels + * 2. Generate sub-circuits for Switch Boxes + */ + /* Now: First task: Routing channels + * Sub-circuits are named as chanx[ix][iy] or chany[ix][iy] for horizontal or vertical channels + * each channels consist of a number of routing tracks. (Actually they are metal wires) + * We only support single-driver routing architecture. + * The direction is defined as INC_DIRECTION ------> and DEC_DIRECTION <-------- for chanx + * The direction is defined as INC_DIRECTION /|\ and DEC_DIRECTION | for chany + * | | + * | | + * | \|/ + * For INC_DIRECTION chanx, the inputs are at the left of channels, the outputs are at the right of channels + * For DEC_DIRECTION chanx, the inputs are at the right of channels, the outputs are at the left of channels + * For INC_DIRECTION chany, the inputs are at the bottom of channels, the outputs are at the top of channels + * For DEC_DIRECTION chany, the inputs are at the top of channels, the outputs are at the bottom of channels + */ + /* X - channels [1...nx][0..ny]*/ + vpr_printf(TIO_MESSAGE_INFO, "Writing X-direction Channels...\n"); + for (iy = 0; iy < (ny + 1); iy++) { + for (ix = 1; ix < (nx + 1); ix++) { + dump_verilog_routing_chan_subckt(fp, ix, iy, CHANX, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, + arch.num_segments, arch.Segments); + } + } + /* Y - channels [1...ny][0..nx]*/ + vpr_printf(TIO_MESSAGE_INFO, "Writing Y-direction Channels...\n"); + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + dump_verilog_routing_chan_subckt(fp, ix, iy, CHANY, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, + arch.num_segments, arch.Segments); + } + } + + /* Switch Boxes*/ + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 0; iy < (ny + 1); iy++) { + vpr_printf(TIO_MESSAGE_INFO, "Writing Switch Boxes[%d][%d]...\n", ix, iy); + update_spice_models_routing_index_low(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models); + dump_verilog_routing_switch_box_subckt(fp, &(sb_info[ix][iy]), + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + update_spice_models_routing_index_high(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models); + } + } + + /* Connection Boxes */ + /* X - channels [1...nx][0..ny]*/ + for (iy = 0; iy < (ny + 1); iy++) { + for (ix = 1; ix < (nx + 1); ix++) { + vpr_printf(TIO_MESSAGE_INFO, "Writing X-direction Connection Boxes[%d][%d]...\n", ix, iy); + update_spice_models_routing_index_low(ix, iy, CHANX, arch.spice->num_spice_model, arch.spice->spice_models); + dump_verilog_routing_connection_box_subckt(fp, &(cbx_info[ix][iy]), + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + update_spice_models_routing_index_high(ix, iy, CHANX, arch.spice->num_spice_model, arch.spice->spice_models); + } + } + /* Y - channels [1...ny][0..nx]*/ + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + vpr_printf(TIO_MESSAGE_INFO, "Writing Y-direction Connection Boxes[%d][%d]...\n", ix, iy); + update_spice_models_routing_index_low(ix, iy, CHANY, arch.spice->num_spice_model, arch.spice->spice_models); + dump_verilog_routing_connection_box_subckt(fp, &(cby_info[ix][iy]), + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + update_spice_models_routing_index_high(ix, iy, CHANY, arch.spice->num_spice_model, arch.spice->spice_models); + } + } + + /* Close the file*/ + fclose(fp); + + return; +} diff --git a/vpr7_rram/vpr/SRC/syn_verilog/verilog_routing.h b/vpr7_rram/vpr/SRC/syn_verilog/verilog_routing.h new file mode 100644 index 000000000..cf43c2f00 --- /dev/null +++ b/vpr7_rram/vpr/SRC/syn_verilog/verilog_routing.h @@ -0,0 +1,87 @@ + +void dump_verilog_routing_chan_subckt(FILE* fp, + int x, int y, t_rr_type chan_type, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices, + int num_segment, t_segment_inf* segments); + +void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, + int pin_index, int side, + int x, int y, + boolean dump_port_type); + +void dump_verilog_grid_side_pins(FILE* fp, + t_rr_type pin_type, int x, int y, int side, + boolean dump_port_type); + +void dump_verilog_switch_box_chan_port(FILE* fp, + t_sb* cur_sb_info, + int chan_side, + t_rr_node* cur_rr_node, + enum PORTS cur_rr_node_direction); + +void dump_verilog_switch_box_short_interc(FILE* fp, + t_sb* cur_sb_info, + int chan_side, + t_rr_node* cur_rr_node, + int actual_fan_in, + t_rr_node* drive_rr_node); + +void dump_verilog_switch_box_mux(FILE* fp, + t_sb* cur_sb_info, + int chan_side, + t_rr_node* cur_rr_node, + int mux_size, + t_rr_node** drive_rr_nodes, + int switch_index); + +int count_verilog_switch_box_interc_conf_bits(int switch_box_x, int switch_box_y, int chan_side, + t_rr_node* cur_rr_node); + +int count_verilog_switch_box_interc_reserved_conf_bits(int switch_box_x, int switch_box_y, int chan_side, + t_rr_node* cur_rr_node); + +void dump_verilog_switch_box_interc(FILE* fp, + t_sb* cur_sb_info, + int chan_side, + t_rr_node* cur_rr_node); + +int count_verilog_switch_box_reserved_conf_bits(t_sb cur_sb_info); +int count_verilog_switch_box_conf_bits(t_sb cur_sb_info); + +void dump_verilog_routing_switch_box_subckt(FILE* fp, t_sb* cur_sb_info, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices); + +void dump_verilog_connection_box_short_interc(FILE* fp, + t_cb* cur_cb_info, + t_rr_node* src_rr_node); + +void dump_verilog_connection_box_mux(FILE* fp, + t_cb* cur_cb_info, + t_rr_node* src_rr_node); + +void dump_verilog_connection_box_interc(FILE* fp, + t_cb* cur_cb_info, + t_rr_node* src_rr_node); + + +int count_verilog_connection_box_interc_conf_bits(t_rr_node* cur_rr_node); +int count_verilog_connection_box_interc_reserved_conf_bits(t_rr_node* cur_rr_node); +int count_verilog_connection_box_one_side_conf_bits(int num_ipin_rr_nodes, + t_rr_node** ipin_rr_node); +int count_verilog_connection_box_one_side_reserved_conf_bits(int num_ipin_rr_nodes, + t_rr_node** ipin_rr_node); +int count_verilog_connection_box_conf_bits(t_cb* cur_cb_info); +int count_verilog_connection_box_reserved_conf_bits(t_cb* cur_cb_info); + +void dump_verilog_routing_connection_box_subckt(FILE* fp, t_cb* cur_cb_info, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices); + +void dump_verilog_routing_resources(char* subckt_dir, + t_arch arch, + t_det_routing_arch* routing_arch, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices); + diff --git a/vpr7_rram/vpr/SRC/syn_verilog/verilog_submodules.c b/vpr7_rram/vpr/SRC/syn_verilog/verilog_submodules.c new file mode 100644 index 000000000..c7d142555 --- /dev/null +++ b/vpr7_rram/vpr/SRC/syn_verilog/verilog_submodules.c @@ -0,0 +1,2255 @@ +/***********************************/ +/* Synthesizable Verilog Dumping */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph.h" +#include "vpr_utils.h" +#include "path_delay.h" +#include "stats.h" + +/* Include FPGA-SPICE utils */ +#include "linkedlist.h" +#include "fpga_spice_utils.h" +#include "spice_mux.h" +#include "fpga_spice_globals.h" + +/* Include verilog utils */ +#include "verilog_global.h" +#include "verilog_utils.h" +#include "verilog_pbtypes.h" + +/***** Subroutines *****/ +/* Dump a module of inverter or buffer or tapered buffer */ +void dump_verilog_invbuf_module(FILE* fp, + t_spice_model* invbuf_spice_model) { + int ipin, iport, port_cnt; + int num_input_port = 0; + int num_output_port = 0; + int num_powergate_port = 0; + t_spice_model_port** input_port = NULL; + t_spice_model_port** output_port = NULL; + t_spice_model_port** powergate_port = NULL; + + /* Ensure a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File handler.\n", + __FILE__, __LINE__); + exit(1); + } + + fprintf(fp, "//----- Verilog module for %s -----\n", + invbuf_spice_model->name); + + /* Find the input port, output port*/ + input_port = find_spice_model_ports(invbuf_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + output_port = find_spice_model_ports(invbuf_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + powergate_port = find_spice_model_config_done_ports(invbuf_spice_model, SPICE_MODEL_PORT_INPUT, &num_powergate_port, FALSE); + + /* Make sure: + * There is only 1 input port and 1 output port, + * each size of which is 1 + */ + assert(1 == num_input_port); + assert(1 == input_port[0]->size); + assert(1 == num_output_port); + assert(1 == output_port[0]->size); + + /* If power-gated, we need to find enable signals */ + if (TRUE == invbuf_spice_model->design_tech_info.power_gated) { + if (0 == num_powergate_port) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Inverter, buffer SPICE model is power-gated, but cannot find any power-gate port!\n", + __FILE__, __LINE__); + exit(1); + } + assert ( 0 < num_powergate_port); + } + + /* dump module body */ + fprintf(fp, "module %s (\n", + invbuf_spice_model->name); + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, invbuf_spice_model, TRUE, FALSE)) { + fprintf(fp, ",\n"); + } + /* Dump ports */ + fprintf(fp, "input %s,\n", input_port[0]->prefix); + fprintf(fp, "output %s\n", output_port[0]->prefix); + fprintf(fp, ");\n"); + /* Finish dumping ports */ + + /* Assign logics : depending on topology */ + switch (invbuf_spice_model->design_tech_info.buffer_info->type) { + case SPICE_MODEL_BUF_INV: + if (TRUE == invbuf_spice_model->design_tech_info.power_gated) { + /* Create a sensitive list */ + fprintf(fp, "reg %s_reg;\n", output_port[0]->prefix); + fprintf(fp, "always @("); + /* Power-gate port first*/ + for (iport = 0; iport < num_powergate_port; iport++) { + fprintf(fp, "%s,", powergate_port[iport]->prefix); + } + fprintf(fp, "%s) begin\n", + input_port[0]->prefix); + /* Dump the case of power-gated */ + fprintf(fp, " if ("); + port_cnt = 0; /* Initialize the counter: decide if we need to put down '&&' */ + for (iport = 0; iport < num_powergate_port; iport++) { + if (0 == powergate_port[iport]->default_val) { + for (ipin = 0; ipin < powergate_port[iport]->size; ipin++) { + if ( 0 < port_cnt ) { + fprintf(fp, "\n\t&&"); + } + /* Power-gated signal are disable during operating, enabled during configuration, + * Therefore, we need to reverse them here + */ + fprintf(fp, "(~%s[%d])", + powergate_port[iport]->prefix, + ipin); + port_cnt++; /* Update port counter*/ + } + } else { + assert (1 == powergate_port[iport]->default_val); + for (ipin = 0; ipin < powergate_port[iport]->size; ipin++) { + if ( 0 < port_cnt ) { + fprintf(fp, "\n\t&&"); + } + /* Power-gated signal are disable during operating, enabled during configuration, + * Therefore, we need to reverse them here + */ + fprintf(fp, "(%s[%d])", + powergate_port[iport]->prefix, + ipin); + port_cnt++; /* Update port counter*/ + } + } + } + fprintf(fp, ") begin\n"); + fprintf(fp, "\t\tassign %s_reg = ~%s;\n", + output_port[0]->prefix, + input_port[0]->prefix); + fprintf(fp, "\tend else begin\n"); + fprintf(fp, "\t\tassign %s_reg = 1'bz;\n", + output_port[0]->prefix); + fprintf(fp, "\tend\n"); + fprintf(fp, "end\n"); + fprintf(fp, "assign %s = %s_reg;\n", + output_port[0]->prefix, + output_port[0]->prefix); + } else { + fprintf(fp, "assign %s = ~%s;\n", + output_port[0]->prefix, + input_port[0]->prefix); + } + break; + case SPICE_MODEL_BUF_BUF: + if (TRUE == invbuf_spice_model->design_tech_info.power_gated) { + /* Create a sensitive list */ + fprintf(fp, "reg %s_reg;\n", output_port[0]->prefix); + fprintf(fp, "always @("); + /* Power-gate port first*/ + for (iport = 0; iport < num_powergate_port; iport++) { + fprintf(fp, "%s,", powergate_port[iport]->prefix); + } + fprintf(fp, "%s) begin\n", + input_port[0]->prefix); + /* Dump the case of power-gated */ + fprintf(fp, " if ("); + port_cnt = 0; /* Initialize the counter: decide if we need to put down '&&' */ + for (iport = 0; iport < num_powergate_port; iport++) { + if (0 == powergate_port[iport]->default_val) { + for (ipin = 0; ipin < powergate_port[iport]->size; ipin++) { + if ( 0 < port_cnt ) { + fprintf(fp, "\n\t&&"); + } + /* Power-gated signal are disable during operating, enabled during configuration, + * Therefore, we need to reverse them here + */ + fprintf(fp, "(~%s[%d])", + powergate_port[iport]->prefix, + ipin); + port_cnt++; /* Update port counter*/ + } + } else { + assert (1 == powergate_port[iport]->default_val); + for (ipin = 0; ipin < powergate_port[iport]->size; ipin++) { + if ( 0 < port_cnt ) { + fprintf(fp, "\n\t&&"); + } + /* Power-gated signal are disable during operating, enabled during configuration, + * Therefore, we need to reverse them here + */ + fprintf(fp, "(%s[%d])", + powergate_port[iport]->prefix, + ipin); + port_cnt++; /* Update port counter*/ + } + } + } + fprintf(fp, ") begin\n"); + fprintf(fp, "\t\tassign %s_reg = %s;\n", + output_port[0]->prefix, + input_port[0]->prefix); + fprintf(fp, "\tend else begin\n"); + fprintf(fp, "\t\tassign %s_reg = 1'bz;\n", + output_port[0]->prefix); + fprintf(fp, "\tend\n"); + fprintf(fp, "end\n"); + fprintf(fp, "assign %s = %s_reg;\n", + output_port[0]->prefix, + output_port[0]->prefix); + + } else { + fprintf(fp, "assign %s = %s;\n", + output_port[0]->prefix, + input_port[0]->prefix); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid topology for spice model (%s)!\n", + __FILE__, __LINE__, invbuf_spice_model->name); + exit(1); + } + + fprintf(fp, "endmodule\n"); + + fprintf(fp, "\n"); + + /* Free */ + my_free(input_port); + my_free(output_port); + + return; +} + +/* Dump a module of pass-gate logic */ +void dump_verilog_passgate_module(FILE* fp, + t_spice_model* passgate_spice_model) { + int iport; + int num_input_port = 0; + int num_output_port = 0; + t_spice_model_port** input_port = NULL; + t_spice_model_port** output_port = NULL; + + /* Ensure a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Find the input port, output port*/ + input_port = find_spice_model_ports(passgate_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + output_port = find_spice_model_ports(passgate_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + + /* Make sure: + * There is only 1 output port, + * each size of which is 1 + */ + assert(1 == num_output_port); + assert(1 == output_port[0]->size); + + fprintf(fp, "//----- Verilog module for %s -----\n", + passgate_spice_model->name); + + /* dump module body */ + fprintf(fp, "module %s (\n", + passgate_spice_model->name); + + /* Assign ports : depending on topology */ + switch (passgate_spice_model->design_tech_info.pass_gate_info->type) { + case SPICE_MODEL_PASS_GATE_TRANSMISSION: + /* Make sure: + * There is only 3 input port (in, sel, selb), + * each size of which is 1 + */ + assert(3 == num_input_port); + for (iport = 0; iport < num_input_port; iport++) { + assert(1 == input_port[iport]->size); + } + /* Dump ports */ + fprintf(fp, "input in,\n"); + fprintf(fp, "input sel,\n"); + fprintf(fp, "input selb,\n"); + fprintf(fp, "output %s\n", output_port[0]->prefix); + fprintf(fp, ");\n"); + /* Finish dumping ports */ + + break; + case SPICE_MODEL_PASS_GATE_TRANSISTOR: + /* Make sure: + * There is only 2 input port (in, sel), + * each size of which is 1 + */ + assert(2 == num_input_port); + for (iport = 0; iport < num_input_port; iport++) { + assert(1 == input_port[iport]->size); + } + /* Dump ports */ + fprintf(fp, "input in,\n"); + fprintf(fp, "input sel,\n"); + fprintf(fp, "output %s\n", output_port[0]->prefix); + fprintf(fp, ");\n"); + /* Finish dumping ports */ + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid topology for spice model (%s)!\n", + __FILE__, __LINE__, passgate_spice_model->name); + exit(1); + } + + /* Dump logics */ + fprintf(fp, "assign %s = sel? in : 1'bz;\n", + output_port[0]->prefix); + + fprintf(fp, "endmodule\n"); + + fprintf(fp, "\n"); + + /* Free */ + my_free(input_port); + my_free(output_port); + + return; +} + + +/* Dump Essential modules: + * 1. inverters + * 2. buffers + * 3. pass-gate logics */ +void dump_verilog_submodule_essentials(char* submodule_dir, + int num_spice_model, + t_spice_model* spice_models) { + int imodel; + char* verilog_name = my_strcat(submodule_dir, essentials_verilog_file_name); + FILE* fp = NULL; + + /* Create file */ + fp = fopen(verilog_name, "w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create Verilog netlist %s", + __FILE__, __LINE__, essentials_verilog_file_name); + exit(1); + } + dump_verilog_file_header(fp,"Essential gates"); + + /* Output essential models*/ + for (imodel = 0; imodel < num_spice_model; imodel++) { + /* By pass user-defined modules */ + if (NULL != spice_models[imodel].verilog_netlist) { + continue; + } + if (SPICE_MODEL_INVBUF == spice_models[imodel].type) { + dump_verilog_invbuf_module(fp, &(spice_models[imodel])); + } + if (SPICE_MODEL_PASSGATE == spice_models[imodel].type) { + dump_verilog_passgate_module(fp, &(spice_models[imodel])); + } + } + + /* Close file handler*/ + fclose(fp); + + /* Free */ + + return; +} + +/* Dump a CMOS MUX basis module */ +void dump_verilog_cmos_mux_one_basis_module(FILE* fp, + char* mux_basis_subckt_name, + int mux_size, + int num_input_basis_subckt, + t_spice_model* cur_spice_model, + boolean special_basis) { + int cur_mem, i; + int num_mem = num_input_basis_subckt; + + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + + /* Determine the number of memory bit + * The function considers a special case : + * 2-input basis in tree-like MUX only requires 1 memory bit */ + num_mem = determine_num_sram_bits_mux_basis_subckt(cur_spice_model, mux_size, num_input_basis_subckt, special_basis); + + /* Comment lines */ + fprintf(fp, "//---- CMOS MUX basis module: %s -----\n", mux_basis_subckt_name); + + /* Print the port list and definition */ + fprintf(fp, "module %s (\n", mux_basis_subckt_name); + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE)) { + fprintf(fp, ",\n"); + } + /* Port list */ + fprintf(fp, "input [0:%d] in,\n", num_input_basis_subckt - 1); + fprintf(fp, "output out,\n"); + fprintf(fp, "input [0:%d] mem,\n", + num_mem - 1); + fprintf(fp, "input [0:%d] mem_inv);\n", + num_mem - 1); + /* Verilog Behavior description for a MUX */ + fprintf(fp, "//---- Behavior-level description -----\n"); + /* Special case: only one memory, switch case is simpler + * When mem = 1, propagate input 0; + * when mem = 0, propagate input 1; + */ + if (1 == num_mem) { + fprintf(fp, " reg out_reg;\n"); + fprintf(fp, " always @(in, mem)\n"); + fprintf(fp, " case (mem)\n"); + fprintf(fp, " 1'b1: out_reg = in[0];\n"); + fprintf(fp, " 1'b0: out_reg = in[1];\n"); + fprintf(fp, " default: out_reg <= 1'bz;\n"); + fprintf(fp, " endcase\n"); + fprintf(fp, " assign out = out_reg;\n"); + } else { + /* Other cases, we need to follow the rules: + * When mem[k] is enabled, switch on input[k] + * Only one memory bit is enabled! + */ + fprintf(fp, " reg out_reg;\n"); + fprintf(fp, " always @(in, mem)\n"); + fprintf(fp, " case (mem)\n"); + fprintf(fp, "//---- Note that MSB is mem[0] while LSB is mem[%d] -----\n", num_mem-1); + fprintf(fp, "//---- Due to the delcare convention of port [MSB:LSB] -----\n"); + for (cur_mem = 0; cur_mem < num_mem; cur_mem++) { + fprintf(fp, " %d'b", num_mem); + for (i = 0; i < cur_mem; i++) { + fprintf(fp, "0"); + } + fprintf(fp, "1"); + for (i = cur_mem + 1; i < num_mem; i++) { + fprintf(fp, "0"); + } + fprintf(fp, ":"); + fprintf(fp, " out_reg <= in[%d];\n", cur_mem); + } + fprintf(fp, " default: out_reg <= 1'bz;\n"); + fprintf(fp, " endcase\n"); + + fprintf(fp, " assign out = out_reg;\n"); + } + + /* Put an end to this module */ + fprintf(fp, "endmodule\n"); + + /* Comment lines */ + fprintf(fp, "//---- END CMOS MUX basis module: %s -----\n\n", mux_basis_subckt_name); + + return; +} + +/* Dump a structural verilog for SRAM-based MUX basis module + * This is only called when structural verilog dumping option is enabled for this spice model + * Note that the structural verilog may be used for functionality verification!!! + */ +static +void dump_verilog_cmos_mux_one_basis_module_structural(FILE* fp, + char* mux_basis_subckt_name, + int mux_size, + int num_input_basis_subckt, + t_spice_model* cur_spice_model, + boolean special_basis) { + int cur_mem, i; + int num_mem = num_input_basis_subckt; + /* Get the tgate module name */ + char* tgate_module_name = cur_spice_model->pass_gate_logic->spice_model_name; + + assert(TRUE == cur_spice_model->dump_structural_verilog); + + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + /* Determine the number of memory bit + * The function considers a special case : + * 2-input basis in tree-like MUX only requires 1 memory bit */ + num_mem = determine_num_sram_bits_mux_basis_subckt(cur_spice_model, mux_size, num_input_basis_subckt, special_basis); + + /* Comment lines */ + fprintf(fp, "//---- Structural Verilog for CMOS MUX basis module: %s -----\n", mux_basis_subckt_name); + + /* Print the port list and definition */ + fprintf(fp, "module %s (\n", mux_basis_subckt_name); + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE)) { + fprintf(fp, ",\n"); + } + /* Port list */ + fprintf(fp, "input [0:%d] in,\n", num_input_basis_subckt - 1); + fprintf(fp, "output out,\n"); + fprintf(fp, "input [0:%d] mem,\n", + num_mem - 1); + fprintf(fp, "input [0:%d] mem_inv);\n", + num_mem - 1); + /* Verilog Behavior description for a MUX */ + fprintf(fp, "//---- Structure-level description -----\n"); + /* Special case: only one memory, switch case is simpler + * When mem = 1, propagate input 0; + * when mem = 0, propagate input 1; + */ + if (1 == num_mem) { + /* Transmission gates are connected to each input and also the output*/ + fprintf(fp, " %s %s_0 (in[0], mem[0], mem_inv[0], out);\n", + tgate_module_name, tgate_module_name); + fprintf(fp, " %s %s_1 (in[1], mem_inv[0], mem[0], out);\n", + tgate_module_name, tgate_module_name); + } else { + /* Other cases, we need to follow the rules: + * When mem[k] is enabled, switch on input[k] + * Only one memory bit is enabled! + */ + for (i = 0; i < num_mem; i++) { + fprintf(fp, " %s %s_%d (in[%d], mem[%d], mem_inv[%d], out);\n", + tgate_module_name, tgate_module_name, i, + i, i, i); + } + } + + /* Put an end to this module */ + fprintf(fp, "endmodule\n"); + + /* Comment lines */ + fprintf(fp, "//---- END Structural Verilog CMOS MUX basis module: %s -----\n\n", mux_basis_subckt_name); + + return; +} + +/* Dump a structural verilog for RRAM MUX basis module + * This is only called when structural verilog dumping option is enabled for this spice model + * Note that the structural verilog cannot be used for functionality verification!!! + */ +static +void dump_verilog_rram_mux_one_basis_module_structural(FILE* fp, + char* mux_basis_subckt_name, + int num_input_basis_subckt, + t_spice_model* cur_spice_model) { + /* RRAM MUX needs 2*(input_size + 1) memory bits for configuration purpose */ + int num_mem = num_input_basis_subckt + 1; + int i, iport, ipin; + int find_prog_EN = 0; + int find_prog_ENb = 0; + char* progTE_module_name = "PROG_TE"; + char* progBE_module_name = "PROG_BE"; + + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + + assert(TRUE == cur_spice_model->dump_structural_verilog); + + /* Comment lines */ + fprintf(fp, "//---- Structural Verilog for RRAM MUX basis module: %s -----\n", mux_basis_subckt_name); + + /* Print the port list and definition */ + fprintf(fp, "module %s (\n", mux_basis_subckt_name); + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE)) { + fprintf(fp, ",\n"); + } + /* Port list */ + fprintf(fp, "input wire [0:%d] in,\n", num_input_basis_subckt - 1); + fprintf(fp, "output wire out,\n"); + fprintf(fp, "input wire [0:%d] bl,\n", + num_mem - 1); + fprintf(fp, "input wire [0:%d] wl);\n", + num_mem - 1); + + /* Print internal structure of 4T1R programming structures + * Written in structural Verilog + * The whole structure-level description is divided into two parts: + * 1. Left part consists of N PROG_TE modules, each of which + * includes a PMOS, a NMOS and a RRAM, which is actually the left + * part of a 4T1R programming structure + * 2. Right part includes only a PROG_BE module, which consists + * of a PMOS and a NMOS, which is actually the right part of a + * 4T1R programming sturcture + */ + /* LEFT part */ + for (i = 0; i < num_input_basis_subckt - 1; i++) { + fprintf(fp, "%s %s_%d (in[%d], wl[%d], bl[%d], out);\n", + progTE_module_name, progTE_module_name, i, + i, i, i); + } + /* RIGHT part */ + fprintf(fp, "%s %s_%d (out, wl[%d], bl[%d]);\n", + progBE_module_name, progBE_module_name, i, + i, i); + + /* Put an end to this module */ + fprintf(fp, "endmodule\n"); + + /* Comment lines */ + fprintf(fp, "//---- END Structural Verilog for RRAM MUX basis module: %s -----\n\n", mux_basis_subckt_name); + + return; +} + + +/* Dump a RRAM MUX basis module */ +void dump_verilog_rram_mux_one_basis_module(FILE* fp, + char* mux_basis_subckt_name, + int num_input_basis_subckt, + t_spice_model* cur_spice_model) { + /* RRAM MUX needs 2*(input_size + 1) memory bits for configuration purpose */ + int num_mem = num_input_basis_subckt + 1; + int i, iport, ipin; + int find_prog_EN = 0; + int find_prog_ENb = 0; + + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + + /* Comment lines */ + fprintf(fp, "//---- RRAM MUX basis module: %s -----\n", mux_basis_subckt_name); + + /* Print the port list and definition */ + fprintf(fp, "module %s (\n", mux_basis_subckt_name); + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE)) { + fprintf(fp, ",\n"); + } + /* Port list */ + fprintf(fp, "input wire [0:%d] in,\n", num_input_basis_subckt - 1); + fprintf(fp, "output wire out,\n"); + fprintf(fp, "input wire [0:%d] bl,\n", + num_mem - 1); + fprintf(fp, "input wire [0:%d] wl);\n", + num_mem - 1); + + /* Print the internal logics: + * ONLY 4T1R programming structure is supported up to now + */ + fprintf(fp, "reg [0:%d] reg_out;\n", num_input_basis_subckt - 1); + fprintf(fp, "always @("); + for (i = 0; i < num_mem; i++) { + if (0 < i) { + fprintf(fp, ","); + } + fprintf(fp, "wl[%d], bl[%d] ", i, i); + } + fprintf(fp, ")\n"); + fprintf(fp, "begin \n"); + + /* Only when the last bit of wl is enabled, + * the propagating path can be changed + * (RRAM value can be changed) */ + fprintf(fp, "\tif ((wl[%d])", num_mem - 1); + /* Find the config_enable ports (prog_EN and prog_ENb) + * in global ports*/ + for (iport = 0; iport < cur_spice_model->num_port; iport++) { + if (FALSE == cur_spice_model->ports[iport].is_config_enable) { + continue; + } + /* Reach here, the port should be is_config_enable */ + if (0 == cur_spice_model->ports[iport].default_val) { + for (ipin = 0; ipin < cur_spice_model->ports[iport].size; ipin++) { + fprintf(fp, "\n\t&&(%s[%d])", + cur_spice_model->ports[iport].prefix, + ipin); + } + /* Update counter */ + find_prog_EN++; + } else { + assert (1 == cur_spice_model->ports[iport].default_val); + for (ipin = 0; ipin < cur_spice_model->ports[iport].size; ipin++) { + fprintf(fp, "\n\t&&(~%s[%d])", + cur_spice_model->ports[iport].prefix, + ipin); + } + /* Update counter */ + find_prog_ENb++; + } + } + /* Check if we find any config_enable signals */ + if (0 == find_prog_EN) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Unable to find a config_enable signal with default value 0 for a RRAM MUX (%s)!\n", + __FILE__, __LINE__, cur_spice_model->name); + exit(1); + } + if (0 == find_prog_ENb) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Unable to find a config_enable signal with default value 1 for a RRAM MUX (%s)!\n", + __FILE__, __LINE__, cur_spice_model->name); + exit(1); + } + + /* Finish the if clause */ + fprintf(fp, ") begin\n"); + + for (i = 0; i < num_input_basis_subckt; i++) { + fprintf(fp, "\tif (1 == bl[%d]) begin\n", i); + fprintf(fp, "\t\tassign reg_out = %d;\n",i); + fprintf(fp, "\tend else "); + } + fprintf(fp, "\tbegin\n"); + fprintf(fp, "\t\t\tassign reg_out = 0;\n"); + fprintf(fp, "\t\tend\n"); + fprintf(fp, "\tend\n"); + fprintf(fp, "end\n"); + + fprintf(fp, "assign out = in[reg_out];\n"); + + /* Put an end to this module */ + fprintf(fp, "endmodule\n"); + + /* Comment lines */ + fprintf(fp, "//---- END RRAM MUX basis module: %s -----\n\n", mux_basis_subckt_name); + + return; +} + +/* Print a basis submodule */ +void dump_verilog_mux_one_basis_module(FILE* fp, + char* mux_basis_subckt_name, + int mux_size, + int num_input_basis_subckt, + t_spice_model* cur_spice_model, + boolean special_basis) { + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + /* Depend on the technology */ + switch (cur_spice_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + if (TRUE == cur_spice_model->dump_structural_verilog) { + dump_verilog_cmos_mux_one_basis_module_structural(fp, mux_basis_subckt_name, + mux_size, + num_input_basis_subckt, + cur_spice_model, + special_basis); + } else { + dump_verilog_cmos_mux_one_basis_module(fp, mux_basis_subckt_name, + mux_size, + num_input_basis_subckt, + cur_spice_model, + special_basis); + } + break; + case SPICE_MODEL_DESIGN_RRAM: + /* If requested, we can dump structural verilog for basis module */ + if (TRUE == cur_spice_model->dump_structural_verilog) { + dump_verilog_rram_mux_one_basis_module_structural(fp, mux_basis_subckt_name, + num_input_basis_subckt, + cur_spice_model); + } else { + dump_verilog_rram_mux_one_basis_module(fp, mux_basis_subckt_name, + num_input_basis_subckt, + cur_spice_model); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of MUX(name: %s)\n", + __FILE__, __LINE__, cur_spice_model->name); + exit(1); + } + + return; +} + +/** + * Dump a verilog module for the basis circuit of a MUX + */ +void dump_verilog_mux_basis_module(FILE* fp, + t_spice_mux_model* spice_mux_model) { + /** Act depends on the structure of MUX + * 1. tree-like/one-level: we generate a basis module + * 2. two/multi-level: we generate a basis and a special module (if required) + */ + int num_input_basis_subckt = 0; + int num_input_special_basis_subckt = 0; + + char* mux_basis_subckt_name = NULL; + char* special_basis_subckt_name = NULL; + + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + + /* Try to find a mux in cmos technology, + * if we have, then build CMOS 2:1 MUX, and given cmos_mux2to1_subckt_name + */ + /* Exception: LUT require an auto-generation of netlist can run as well*/ + assert((SPICE_MODEL_MUX == spice_mux_model->spice_model->type) + ||(SPICE_MODEL_LUT == spice_mux_model->spice_model->type)); + + /* Generate the spice_mux_arch */ + spice_mux_model->spice_mux_arch = (t_spice_mux_arch*)my_malloc(sizeof(t_spice_mux_arch)); + init_spice_mux_arch(spice_mux_model->spice_model, spice_mux_model->spice_mux_arch, spice_mux_model->size); + + /* Corner case: Error out MUX_SIZE = 2, automatcially give a one-level structure */ + if ((2 == spice_mux_model->size)&&(SPICE_MODEL_STRUCTURE_ONELEVEL != spice_mux_model->spice_model->design_tech_info.structure)) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Structure of SPICE model (%s) should be one-level because it is linked to a 2:1 MUX!\n", + __FILE__, __LINE__, spice_mux_model->spice_model->name); + exit(1); + } + + /* Prepare the basis subckt name: + */ + mux_basis_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_mux_model->spice_model->name) + 5 + + strlen(my_itoa(spice_mux_model->size)) + strlen(verilog_mux_basis_posfix) + 1)); + sprintf(mux_basis_subckt_name, "%s_size%d%s", + spice_mux_model->spice_model->name, spice_mux_model->size, verilog_mux_basis_posfix); + + special_basis_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_mux_model->spice_model->name) + 5 + + strlen(my_itoa(spice_mux_model->size)) + strlen(verilog_mux_special_basis_posfix) + 1)); + sprintf(special_basis_subckt_name, "%s_size%d%s", + spice_mux_model->spice_model->name, spice_mux_model->size, verilog_mux_special_basis_posfix); + + /* deteremine the number of inputs of basis subckt */ + num_input_basis_subckt = spice_mux_model->spice_mux_arch->num_input_basis; + + /* Print the basis subckt*/ + dump_verilog_mux_one_basis_module(fp, mux_basis_subckt_name, spice_mux_model->size, + num_input_basis_subckt, spice_mux_model->spice_model, + FALSE); + /* See if we need a special basis */ + switch (spice_mux_model->spice_model->design_tech_info.structure) { + case SPICE_MODEL_STRUCTURE_TREE: + case SPICE_MODEL_STRUCTURE_ONELEVEL: + break; + case SPICE_MODEL_STRUCTURE_MULTILEVEL: + num_input_special_basis_subckt = find_spice_mux_arch_special_basis_size(*(spice_mux_model->spice_mux_arch)); + if (0 < num_input_special_basis_subckt) { + dump_verilog_mux_one_basis_module(fp, special_basis_subckt_name, spice_mux_model->size, + num_input_special_basis_subckt, spice_mux_model->spice_model, + FALSE); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n", + __FILE__, __LINE__, spice_mux_model->spice_model->name); + exit(1); + } + + /* Free */ + my_free(mux_basis_subckt_name); + my_free(special_basis_subckt_name); + + return; +} + +void dump_verilog_cmos_mux_tree_structure(FILE* fp, + char* mux_basis_subckt_name, + t_spice_model spice_model, + t_spice_mux_arch spice_mux_arch, + int num_sram_port, t_spice_model_port** sram_port) { + int i, j, level, nextlevel; + int nextj, out_idx; + int mux_basis_cnt = 0; + + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + + mux_basis_cnt = 0; + for (i = 0; i < spice_mux_arch.num_level; i++) { + level = spice_mux_arch.num_level - i; + nextlevel = spice_mux_arch.num_level - i - 1; + /* Check */ + assert(nextlevel > -1); + fprintf(fp, "wire [%d:%d] mux2_l%d_in; \n", + 0, spice_mux_arch.num_input_per_level[nextlevel] -1, /* input0 input1 */ + level); + } + fprintf(fp, "wire [%d:%d] mux2_l%d_in; \n", + 0, 0, 0); + + for (i = 0; i < spice_mux_arch.num_level; i++) { + level = spice_mux_arch.num_level - i; + nextlevel = spice_mux_arch.num_level - i - 1; + /* Check */ + assert(nextlevel > -1); + /* Print basis mux2to1 for each level*/ + for (j = 0; j < spice_mux_arch.num_input_per_level[nextlevel]; j++) { + nextj = j + 1; + out_idx = j/2; + /* Each basis mux2to1: svdd sgnd */ + fprintf(fp, "%s mux_basis_no%d (", mux_basis_subckt_name, mux_basis_cnt); /* given_name */ + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, nextj); /* input0 input1 */ + fprintf(fp, "mux2_l%d_in[%d], ", nextlevel, out_idx); /* output */ + fprintf(fp, "%s[%d], %s_inv[%d]);\n", sram_port[0]->prefix, i, sram_port[0]->prefix, i); /* sram sram_inv */ + /* Update the counter */ + j = nextj; + mux_basis_cnt++; + } + } + /* Assert */ + assert(0 == nextlevel); + assert(0 == out_idx); + assert(mux_basis_cnt == spice_mux_arch.num_input - 1); + + return; +} + +void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, + char* mux_basis_subckt_name, + char* mux_special_basis_subckt_name, + t_spice_model spice_model, + t_spice_mux_arch spice_mux_arch, + int num_sram_port, t_spice_model_port** sram_port) { + int i, j, level, nextlevel, sram_idx; + int out_idx; + int mux_basis_cnt = 0; + int special_basis_cnt = 0; + int cur_num_input_basis = 0; + + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + + mux_basis_cnt = 0; + assert((2 == spice_mux_arch.num_input_basis)||(2 < spice_mux_arch.num_input_basis)); + for (i = 0; i < spice_mux_arch.num_level; i++) { + level = spice_mux_arch.num_level - i; + nextlevel = spice_mux_arch.num_level - i - 1; + sram_idx = nextlevel * spice_mux_arch.num_input_basis; + /* Check */ + assert(nextlevel > -1); + fprintf(fp, "wire [%d:%d] mux2_l%d_in; \n", + 0, spice_mux_arch.num_input_per_level[nextlevel] -1, /* input0 input1 */ + level); + } + fprintf(fp, "wire [%d:%d] mux2_l%d_in; \n", + 0, 0, 0); + + for (i = 0; i < spice_mux_arch.num_level; i++) { + level = spice_mux_arch.num_level - i; + nextlevel = spice_mux_arch.num_level - i - 1; + sram_idx = nextlevel * spice_mux_arch.num_input_basis; + /* Check */ + assert(nextlevel > -1); + /* Print basis muxQto1 for each level*/ + for (j = 0; j < spice_mux_arch.num_input_per_level[nextlevel]; j = j+cur_num_input_basis) { + /* output index */ + out_idx = j/spice_mux_arch.num_input_basis; + /* Determine the number of input of this basis */ + cur_num_input_basis = spice_mux_arch.num_input_basis; + if ((j + cur_num_input_basis) > spice_mux_arch.num_input_per_level[nextlevel]) { + cur_num_input_basis = find_spice_mux_arch_special_basis_size(spice_mux_arch); + if (0 < cur_num_input_basis) { + /* Print the special basis */ + fprintf(fp, "%s special_basis(", mux_special_basis_subckt_name); + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, j + cur_num_input_basis - 1); /* input0 input1 */ + fprintf(fp, "mux2_l%d_in[%d], ", nextlevel, out_idx); /* output */ + fprintf(fp, "%s[%d:%d], %s_inv[%d:%d] ", + sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1, + sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); + fprintf(fp, ");\n"); + special_basis_cnt++; + } + continue; + } + /* Each basis muxQto1: svdd sgnd */ + fprintf(fp, "%s ", mux_basis_subckt_name); /* subckt_name */ + fprintf(fp, "mux_basis_no%d (", mux_basis_cnt); /* given_name */ + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, j + cur_num_input_basis - 1); /* input0 input1 */ + fprintf(fp, "mux2_l%d_in[%d], ", nextlevel, out_idx); /* output */ + /* Print number of sram bits for this basis */ + fprintf(fp, "%s[%d:%d], %s_inv[%d:%d] ", + sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1, + sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); + fprintf(fp, ");\n"); + fprintf(fp, "\n"); + /* Update the counter */ + mux_basis_cnt++; + } + } + /* Assert */ + assert(0 == nextlevel); + assert(0 == out_idx); + assert((1 == special_basis_cnt)||(0 == special_basis_cnt)); + /* assert((mux_basis_cnt + special_basis_cnt) == (int)((spice_mux_arch.num_input - 1)/(spice_mux_arch.num_input_basis - 1)) + 1); */ + + return; +} + +void dump_verilog_cmos_mux_onelevel_structure(FILE* fp, + char* mux_basis_subckt_name, + t_spice_model spice_model, + t_spice_mux_arch spice_mux_arch, + int num_sram_port, t_spice_model_port** sram_port) { + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + + assert(SPICE_MODEL_DESIGN_CMOS == spice_model.design_tech); + + fprintf(fp, "wire [0:%d] mux2_l%d_in; \n", spice_mux_arch.num_input - 1, 1); /* input0 */ + fprintf(fp, "wire [0:%d] mux2_l%d_in; \n", 0, 0); /* output */ + + fprintf(fp, "%s mux_basis (\n", mux_basis_subckt_name); /* given_name */ + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "//----- MUX inputs -----\n"); + fprintf(fp, "mux2_l%d_in[0:%d], ", 1, spice_mux_arch.num_input - 1); /* input0 */ + fprintf(fp, "mux2_l%d_in[%d], ", 0, 0); /* output */ + fprintf(fp, "\n"); + fprintf(fp, "//----- SRAM ports -----\n"); + /* Special basis for 2-input MUX, there is only one configuration bit */ + if (2 == spice_mux_arch.num_input) { + fprintf(fp, "%s[0:%d], %s_inv[0:%d] ", + sram_port[0]->prefix, 0, + sram_port[0]->prefix, 0); /* sram sram_inv */ + } else { + fprintf(fp, "%s[0:%d], %s_inv[0:%d] ", + sram_port[0]->prefix, spice_mux_arch.num_input - 1, + sram_port[0]->prefix, spice_mux_arch.num_input - 1); /* sram sram_inv */ + } + fprintf(fp, "\n"); + fprintf(fp, ");\n"); + + return; +} + +void dump_verilog_cmos_mux_submodule(FILE* fp, + int mux_size, + t_spice_model spice_model, + t_spice_mux_arch spice_mux_arch) { + int i, num_conf_bits; + int num_input_port = 0; + int num_output_port = 0; + int num_sram_port = 0; + t_spice_model_port** input_port = NULL; + t_spice_model_port** output_port = NULL; + t_spice_model_port** sram_port = NULL; + t_spice_model* input_invbuf_spice_model = NULL; + t_spice_model* output_invbuf_spice_model = NULL; + + /* Find the basis subckt*/ + char* mux_basis_subckt_name = NULL; + char* mux_special_basis_subckt_name = NULL; + + mux_basis_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model.name) + 5 + + strlen(my_itoa(mux_size)) + strlen(verilog_mux_basis_posfix) + 1)); + sprintf(mux_basis_subckt_name, "%s_size%d%s", + spice_model.name, mux_size, verilog_mux_basis_posfix); + + mux_special_basis_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model.name) + 5 + + strlen(my_itoa(spice_mux_arch.num_input)) + + strlen(verilog_mux_special_basis_posfix) + 1)); + sprintf(mux_special_basis_subckt_name, "%s_size%d%s", + spice_model.name, spice_mux_arch.num_input, verilog_mux_special_basis_posfix); + + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + + /* Ensure we have a CMOS MUX, + * ATTENTION: support LUT as well + */ + assert((SPICE_MODEL_MUX == spice_model.type)||(SPICE_MODEL_LUT == spice_model.type)); + assert(SPICE_MODEL_DESIGN_CMOS == spice_model.design_tech); + + /* Find the input port, output port, and sram port*/ + input_port = find_spice_model_ports(&spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + output_port = find_spice_model_ports(&spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + sram_port = find_spice_model_ports(&spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); + + /* Asserts*/ + assert(1 == num_input_port); + assert(1 == num_output_port); + assert(1 == num_sram_port); + assert(1 == output_port[0]->size); + + /* We have two types of naming rules in terms of the usage of MUXes: + * 1. MUXes, the naming rule is __size + * 2. LUTs, the naming rule is _mux_size + */ + num_conf_bits = count_num_sram_bits_one_spice_model(&spice_model, + /* sram_verilog_orgz_info->type, */ + mux_size); + if (SPICE_MODEL_LUT == spice_model.type) { + /* Special for LUT MUX */ + fprintf(fp, "//------ CMOS MUX info: spice_model_name= %s_MUX, size=%d -----\n", spice_model.name, mux_size); + fprintf(fp, "module %s_mux(\n", spice_model.name); + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, TRUE, FALSE)) { + fprintf(fp, ",\n"); + } + /* Print input ports*/ + assert(mux_size == num_conf_bits); + fprintf(fp, "input wire [0:%d] %s,\n", num_conf_bits - 1, input_port[0]->prefix); + /* Print output ports*/ + fprintf(fp, "output wire %s,\n", output_port[0]->prefix); + /* Print configuration ports*/ + /* The configuration port in MUX context is the input port in LUT context ! */ + fprintf(fp, "input wire [0:%d] %s,\n", + input_port[0]->size - 1, sram_port[0]->prefix); + fprintf(fp, "input wire [0:%d] %s_inv\n", + input_port[0]->size - 1, sram_port[0]->prefix); + } else { + fprintf(fp, "//----- CMOS MUX info: spice_model_name=%s, size=%d, structure: %s -----\n", + spice_model.name, mux_size, gen_str_spice_model_structure(spice_model.design_tech_info.structure)); + fprintf(fp, "module %s_size%d (", spice_model.name, mux_size); + /* Print input ports*/ + fprintf(fp, "input wire [0:%d] %s,\n", mux_size - 1, input_port[0]->prefix); + /* Print output ports*/ + fprintf(fp, "output wire %s,\n", output_port[0]->prefix); + /* Print configuration ports*/ + fprintf(fp, "input wire [0:%d] %s,\n", + num_conf_bits - 1, sram_port[0]->prefix); + fprintf(fp, "input wire [0:%d] %s_inv\n", + num_conf_bits - 1, sram_port[0]->prefix); + } + + /* Print local vdd and gnd*/ + fprintf(fp, ");"); + fprintf(fp, "\n"); + + /* Print internal architecture*/ + switch (spice_model.design_tech_info.structure) { + case SPICE_MODEL_STRUCTURE_TREE: + dump_verilog_cmos_mux_tree_structure(fp, mux_basis_subckt_name, + spice_model, spice_mux_arch, num_sram_port, sram_port); + break; + case SPICE_MODEL_STRUCTURE_ONELEVEL: + dump_verilog_cmos_mux_onelevel_structure(fp, mux_basis_subckt_name, + spice_model, spice_mux_arch, num_sram_port, sram_port); + break; + case SPICE_MODEL_STRUCTURE_MULTILEVEL: + dump_verilog_cmos_mux_multilevel_structure(fp, mux_basis_subckt_name, mux_special_basis_subckt_name, + spice_model, spice_mux_arch, num_sram_port, sram_port); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n", + __FILE__, __LINE__, spice_model.name); + exit(1); + } + + /* To connect the input ports*/ + for (i = 0; i < mux_size; i++) { + if (1 == spice_model.input_buffer->exist) { + switch (spice_model.input_buffer->type) { + case SPICE_MODEL_BUF_INV: + /* Each inv: svdd sgnd size=param*/ + fprintf(fp, "%s inv%d (", + spice_model.input_buffer->spice_model_name, i); /* Given name*/ + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE, FALSE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "%s[%d], ", input_port[0]->prefix, i); /* input port */ + fprintf(fp, "mux2_l%d_in[%d]); ", spice_mux_arch.input_level[i], spice_mux_arch.input_offset[i]); /* output port*/ + fprintf(fp, "\n"); + break; + case SPICE_MODEL_BUF_BUF: + /* TODO: what about tapered buffer, can we support? */ + /* Each buf: svdd sgnd size=param*/ + fprintf(fp, "%s buf%d (", + spice_model.input_buffer->spice_model_name, i); /* Given name*/ + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE, FALSE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "%s[%d], ", input_port[0]->prefix, i); /* input port */ + fprintf(fp, "mux2_l%d_in[%d]); ", spice_mux_arch.input_level[i], spice_mux_arch.input_offset[i]); /* output port*/ + fprintf(fp, "\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type for spice_model_buffer.\n", + __FILE__, __LINE__); + exit(1); + } + } else { + /* There is no buffer, I create a zero resisitance between*/ + /* Resistance R 0*/ + fprintf(fp, "assign %s[%d] = mux2_l%d_in[%d];\n", + input_port[0]->prefix, i, spice_mux_arch.input_level[i], + spice_mux_arch.input_offset[i]); + } + } + + /* Output buffer*/ + if (1 == spice_model.output_buffer->exist) { + switch (spice_model.output_buffer->type) { + case SPICE_MODEL_BUF_INV: + if (TRUE == spice_model.output_buffer->tapered_buf) { + break; + } + /* Each inv: svdd sgnd size=param*/ + fprintf(fp, "%s inv_out (", + spice_model.output_buffer->spice_model_name); /* Given name*/ + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "mux2_l%d_in[%d], ", 0, 0); /* input port */ + fprintf(fp, "%s );", output_port[0]->prefix); /* Output port*/ + fprintf(fp, "\n"); + break; + case SPICE_MODEL_BUF_BUF: + if (TRUE == spice_model.output_buffer->tapered_buf) { + break; + } + /* Each buf: svdd sgnd size=param*/ + fprintf(fp, "%s buf_out (", + spice_model.output_buffer->spice_model_name); /* Given name*/ + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "mux2_l%d_in[%d], ", 0, 0); /* input port */ + fprintf(fp, "%s );", output_port[0]->prefix); /* Output port*/ + fprintf(fp, "\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type for spice_model_buffer.\n", + __FILE__, __LINE__); + exit(1); + } + /* Tapered buffer support */ + if (TRUE == spice_model.output_buffer->tapered_buf) { + /* Each buf: svdd sgnd size=param*/ + fprintf(fp, "%s buf_out (", + spice_model.output_buffer->spice_model_name); /* subckt name */ + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "mux2_l%d_in[%d], ", 0, 0); /* input port */ + fprintf(fp, "%s );", output_port[0]->prefix); /* Output port*/ + fprintf(fp, "\n"); + } + } else { + /* There is no buffer, I create a zero resisitance between*/ + /* Resistance R 0*/ + fprintf(fp, "assign mux2_l0_in[0] = %s;\n",output_port[0]->prefix); + } + + fprintf(fp, "endmodule\n"); + fprintf(fp, "//----- END CMOS MUX info: spice_model_name=%s, size=%d -----\n\n", spice_model.name, mux_size); + fprintf(fp, "\n"); + + /* Free */ + my_free(mux_basis_subckt_name); + my_free(mux_special_basis_subckt_name); + my_free(input_port); + my_free(output_port); + my_free(sram_port); + + return; +} + +/* Print the RRAM MUX SPICE model. + * The internal structures of CMOS and RRAM MUXes are similar. + * This one can be merged to CMOS function. + * However I use another function, because in future the internal structure may change. + * We will suffer less software problems. + */ +void dump_verilog_rram_mux_tree_structure(FILE* fp, + char* mux_basis_subckt_name, + t_spice_model spice_model, + t_spice_mux_arch spice_mux_arch, + int num_sram_port, t_spice_model_port** sram_port) { + int i, j, level, nextlevel; + int nextj, out_idx; + int mux_basis_cnt = 0; + int cur_mem_lsb = 0; + int cur_mem_msb = 0; + + assert(SPICE_MODEL_DESIGN_RRAM == spice_model.design_tech); + + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + + for (i = 0; i < spice_mux_arch.num_level; i++) { + level = spice_mux_arch.num_level - i; + nextlevel = spice_mux_arch.num_level - i - 1; + /* Check */ + assert(nextlevel > -1); + fprintf(fp, "wire [%d:%d] mux2_l%d_in; \n", + 0, spice_mux_arch.num_input_per_level[nextlevel] -1, /* input0 input1 */ + level); + } + fprintf(fp, "wire [%d:%d] mux2_l%d_in; \n", + 0, 0, 0); + + mux_basis_cnt = 0; + for (i = 0; i < spice_mux_arch.num_level; i++) { + level = spice_mux_arch.num_level - i; + nextlevel = spice_mux_arch.num_level - i - 1; + /* Check */ + assert(nextlevel > -1); + /* Print basis mux2to1 for each level*/ + for (j = 0; j < spice_mux_arch.num_input_per_level[nextlevel]; j++) { + nextj = j + 1; + out_idx = j/2; + cur_mem_lsb = cur_mem_msb; + cur_mem_msb += 6; + /* Each basis mux2to1: svdd sgnd */ + fprintf(fp, "%s mux_basis_no%d (", mux_basis_subckt_name, mux_basis_cnt); /* given_name */ + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, nextj); /* input0 input1 */ + fprintf(fp, "mux2_l%d_in[%d], ", nextlevel, out_idx); /* output */ + fprintf(fp, "%s[%d:%d] %s_inv[%d:%d]);\n", + sram_port[0]->prefix, cur_mem_lsb, cur_mem_msb - 1, + sram_port[0]->prefix, cur_mem_lsb, cur_mem_msb - 1); /* sram sram_inv */ + /* Update the counter */ + j = nextj; + mux_basis_cnt++; + } + } + /* Assert */ + assert(0 == nextlevel); + assert(0 == out_idx); + assert(mux_basis_cnt == spice_mux_arch.num_input - 1); + assert(cur_mem_msb == 6 * spice_mux_arch.num_level); + + return; +} + +void dump_verilog_rram_mux_multilevel_structure(FILE* fp, + char* mux_basis_subckt_name, + char* mux_special_basis_subckt_name, + t_spice_model spice_model, + t_spice_mux_arch spice_mux_arch, + int num_sram_port, t_spice_model_port** sram_port) { + int i, j, level, nextlevel, sram_idx; + int out_idx; + int mux_basis_cnt = 0; + int special_basis_cnt = 0; + int cur_num_input_basis = 0; + + int cur_mem_lsb = 0; + int cur_mem_msb = 0; + + assert(SPICE_MODEL_DESIGN_RRAM == spice_model.design_tech); + + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + + for (i = 0; i < spice_mux_arch.num_level; i++) { + level = spice_mux_arch.num_level - i; + nextlevel = spice_mux_arch.num_level - i - 1; + sram_idx = nextlevel * spice_mux_arch.num_input_basis; + /* Check */ + assert(nextlevel > -1); + fprintf(fp, "wire [%d:%d] mux2_l%d_in; \n", + 0, spice_mux_arch.num_input_per_level[nextlevel] -1, /* input0 input1 */ + level); + } + fprintf(fp, "wire [%d:%d] mux2_l%d_in; \n", + 0, 0, 0); + + mux_basis_cnt = 0; + assert((2 == spice_mux_arch.num_input_basis)||(2 < spice_mux_arch.num_input_basis)); + for (i = 0; i < spice_mux_arch.num_level; i++) { + level = spice_mux_arch.num_level - i; + nextlevel = spice_mux_arch.num_level - i - 1; + /* Check */ + assert(nextlevel > -1); + /* Memory port offset update */ + cur_mem_lsb = cur_mem_msb; + /* Print basis muxQto1 for each level*/ + for (j = 0; j < spice_mux_arch.num_input_per_level[nextlevel]; j = j+cur_num_input_basis) { + /* output index */ + out_idx = j/spice_mux_arch.num_input_basis; + /* Determine the number of input of this basis */ + cur_num_input_basis = spice_mux_arch.num_input_basis; + cur_mem_msb = cur_mem_lsb + (cur_num_input_basis + 1); + if ((j + cur_num_input_basis) > spice_mux_arch.num_input_per_level[nextlevel]) { + cur_num_input_basis = find_spice_mux_arch_special_basis_size(spice_mux_arch); + if (0 < cur_num_input_basis) { + /* Print the special basis */ + fprintf(fp, "%s special_basis(\n", mux_special_basis_subckt_name); + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, j + cur_num_input_basis - 1); /* inputs */ + fprintf(fp, "mux2_l%d_in[%d], ", nextlevel, out_idx); /* output */ + cur_mem_msb = cur_mem_lsb + (cur_num_input_basis + 1); + fprintf(fp, "%s[%d:%d], %s_inv[%d,%d]", + sram_port[0]->prefix, cur_mem_lsb, cur_mem_msb - 1, + sram_port[0]->prefix, cur_mem_lsb, cur_mem_msb - 1); /* sram sram_inv */ + fprintf(fp, ");\n"); + special_basis_cnt++; + continue; + } + } + /* Each basis muxQto1: svdd sgnd */ + fprintf(fp, "%s ", mux_basis_subckt_name); /* subckt_name */ + fprintf(fp, "mux_basis_no%d (", mux_basis_cnt); /* given_name */ + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, j + cur_num_input_basis - 1); /* input0 input1 */ + fprintf(fp, "mux2_l%d_in[%d], ", nextlevel, out_idx); /* output */ + /* Print number of sram bits for this basis */ + fprintf(fp, "%s[%d:%d], %s_inv[%d:%d]", + sram_port[0]->prefix, cur_mem_lsb, cur_mem_msb - 1, + sram_port[0]->prefix, cur_mem_lsb, cur_mem_msb - 1); /* sram sram_inv */ + fprintf(fp, ");\n"); + /* Update the counter */ + mux_basis_cnt++; + } + } + /* Assert */ + assert(0 == nextlevel); + assert(0 == out_idx); + assert((1 == special_basis_cnt)||(0 == special_basis_cnt)); + /* assert((mux_basis_cnt + special_basis_cnt) == (int)((spice_mux_arch.num_input - 1)/(spice_mux_arch.num_input_basis - 1)) + 1); */ + + /* Free */ + + return; +} + +void dump_verilog_rram_mux_onelevel_structure(FILE* fp, + char* mux_basis_subckt_name, + t_spice_model spice_model, + t_spice_mux_arch spice_mux_arch, + int num_sram_port, t_spice_model_port** sram_port) { + int num_conf_bits; + + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + + assert(SPICE_MODEL_DESIGN_RRAM == spice_model.design_tech); + + fprintf(fp, "wire [0:%d] mux2_l%d_in; \n", spice_mux_arch.num_input - 1, 1); /* input0 */ + fprintf(fp, "wire [0:%d] mux2_l%d_in; \n", 0, 0); /* output */ + + fprintf(fp, "%s mux_basis (\n", mux_basis_subckt_name); /* given_name */ + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "//----- MUX inputs -----\n"); + fprintf(fp, "mux2_l%d_in[0:%d],\n ", 1, spice_mux_arch.num_input - 1); /* inputs */ + fprintf(fp, "mux2_l%d_in[%d],\n", 0, 0); /* output */ + fprintf(fp, "//----- SRAM ports -----\n"); + num_conf_bits = count_num_sram_bits_one_spice_model(&spice_model, + /* sram_verilog_orgz_info->type,*/ + spice_mux_arch.num_input); + fprintf(fp, "%s[0:%d], %s_inv[0:%d]", + sram_port[0]->prefix, num_conf_bits - 1, + sram_port[0]->prefix, num_conf_bits - 1); /* sram sram_inv */ + fprintf(fp, "\n"); + fprintf(fp, ");\n"); + + return; +} + +void dump_verilog_rram_mux_submodule(FILE* fp, + int mux_size, + t_spice_model spice_model, + t_spice_mux_arch spice_mux_arch) { + int i, num_conf_bits; + int num_input_port = 0; + int num_output_port = 0; + int num_sram_port = 0; + t_spice_model_port** input_port = NULL; + t_spice_model_port** output_port = NULL; + t_spice_model_port** sram_port = NULL; + + /* Find the basis subckt*/ + char* mux_basis_subckt_name = NULL; + char* mux_special_basis_subckt_name = NULL; + + mux_basis_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model.name) + 5 + + strlen(my_itoa(mux_size)) + strlen(verilog_mux_basis_posfix) + 1)); + sprintf(mux_basis_subckt_name, "%s_size%d%s", + spice_model.name, mux_size, verilog_mux_basis_posfix); + + mux_special_basis_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model.name) + 5 + + strlen(my_itoa(spice_mux_arch.num_input)) + + strlen(verilog_mux_special_basis_posfix) + 1)); + sprintf(mux_special_basis_subckt_name, "%s_size%d%s", + spice_model.name, spice_mux_arch.num_input, verilog_mux_special_basis_posfix); + + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + + /* Ensure we have a RRAM MUX*/ + assert((SPICE_MODEL_MUX == spice_model.type)||(SPICE_MODEL_LUT == spice_model.type)); + assert(SPICE_MODEL_DESIGN_RRAM == spice_model.design_tech); + + /* Find the input port, output port, and sram port*/ + input_port = find_spice_model_ports(&spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + output_port = find_spice_model_ports(&spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + sram_port = find_spice_model_ports(&spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); + + /* Asserts*/ + assert(1 == num_input_port); + assert(1 == num_output_port); + assert(1 == num_sram_port); + assert(1 == output_port[0]->size); + + /* Print the definition of subckt*/ + if (SPICE_MODEL_LUT == spice_model.type) { + /* RRAM LUT is not supported now... */ + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])RRAM LUT is not supported!\n", + __FILE__, __LINE__); + exit(1); + /* Special for LUT MUX*/ + /* + fprintf(fp, "***** RRAM MUX info: spice_model_name= %s_MUX, size=%d *****\n", spice_model.name, mux_size); + fprintf(fp, ".subckt %s_mux_size%d ", spice_model.name, mux_size); + */ + } else { + fprintf(fp, "//----- RRAM MUX info: spice_model_name=%s, size=%d, structure: %s -----\n", + spice_model.name, mux_size, gen_str_spice_model_structure(spice_model.design_tech_info.structure)); + fprintf(fp, "module %s_size%d( \n", spice_model.name, mux_size); + } + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, TRUE, FALSE)) { + fprintf(fp, ",\n"); + } + /* Print input ports*/ + fprintf(fp, "input wire [0:%d] %s,\n ", mux_size - 1, input_port[0]->prefix); + /* Print output ports*/ + fprintf(fp, "output wire %s,\n ", output_port[0]->prefix); + /* Print configuration ports */ + num_conf_bits = count_num_sram_bits_one_spice_model(&spice_model, + /* sram_verilog_orgz_info->type,*/ + mux_size); + fprintf(fp, "input wire [0:%d] %s,\n", + num_conf_bits - 1, sram_port[0]->prefix); + fprintf(fp, "input wire [0:%d] %s_inv\n", + num_conf_bits - 1, sram_port[0]->prefix); + /* Print local vdd and gnd*/ + fprintf(fp, ");\n"); + + /* Print internal architecture*/ + /* RRAM MUX is optimal in terms of area, delay and power for one-level structure. + */ + switch (spice_model.design_tech_info.structure) { + case SPICE_MODEL_STRUCTURE_TREE: + dump_verilog_rram_mux_tree_structure(fp, mux_basis_subckt_name, + spice_model, spice_mux_arch, num_sram_port, sram_port); + break; + case SPICE_MODEL_STRUCTURE_MULTILEVEL: + dump_verilog_rram_mux_multilevel_structure(fp, mux_basis_subckt_name, mux_special_basis_subckt_name, + spice_model, spice_mux_arch, num_sram_port, sram_port); + break; + case SPICE_MODEL_STRUCTURE_ONELEVEL: + dump_verilog_rram_mux_onelevel_structure(fp, mux_basis_subckt_name, + spice_model, spice_mux_arch, num_sram_port, sram_port); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n", + __FILE__, __LINE__, spice_model.name); + exit(1); + } + + /* To connect the input ports*/ + for (i = 0; i < mux_size; i++) { + if (1 == spice_model.input_buffer->exist) { + switch (spice_model.input_buffer->type) { + case SPICE_MODEL_BUF_INV: + /* Each inv: svdd sgnd size=param*/ + fprintf(fp, "%s inv%d (", + spice_model.input_buffer->spice_model_name, i); /* Given name*/ + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE, FALSE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "%s[%d], ", input_port[0]->prefix, i); /* input port */ + fprintf(fp, "mux2_l%d_in[%d]);", spice_mux_arch.input_level[i], spice_mux_arch.input_offset[i]); /* output port*/ + fprintf(fp, "\n"); + break; + case SPICE_MODEL_BUF_BUF: + /* TODO: what about tapered buffer, can we support? */ + /* Each buf: svdd sgnd size=param*/ + fprintf(fp, "%s buf%d (", + spice_model.input_buffer->spice_model_name, i); /* Given name*/ + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE, FALSE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "%s[%d], ", input_port[0]->prefix, i); /* input port */ + fprintf(fp, "mux2_l%d_in[%d)];", spice_mux_arch.input_level[i], spice_mux_arch.input_offset[i]); /* output port*/ + fprintf(fp, "\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type for spice_model_buffer.\n", + __FILE__, __LINE__); + exit(1); + } + } else { + /* There is no buffer, I create a zero resisitance between*/ + /* Resistance R 0*/ + fprintf(fp, "assign %s[%d] = mux2_l%d_in[%d];\n", + input_port[0]->prefix, i, spice_mux_arch.input_level[i], + spice_mux_arch.input_offset[i]); + } + } + + /* Output buffer*/ + if (1 == spice_model.output_buffer->exist) { + switch (spice_model.output_buffer->type) { + case SPICE_MODEL_BUF_INV: + if (TRUE == spice_model.output_buffer->tapered_buf) { + break; + } + /* Each inv: svdd sgnd size=param*/ + fprintf(fp, "%s inv_out (", + spice_model.output_buffer->spice_model_name); /* Given name*/ + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "mux2_l%d_in[%d], ", 0, 0); /* input port */ + fprintf(fp, "%s );", output_port[0]->prefix); /* Output port*/ + fprintf(fp, "\n"); + break; + case SPICE_MODEL_BUF_BUF: + if (TRUE == spice_model.output_buffer->tapered_buf) { + break; + } + /* Each buf: svdd sgnd size=param*/ + fprintf(fp, "%s buf_out (", + spice_model.output_buffer->spice_model_name); /* Given name*/ + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "mux2_l%d_in[%d], ", 0, 0); /* input port */ + fprintf(fp, "%s );", output_port[0]->prefix); /* Output port*/ + fprintf(fp, "\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type for spice_model_buffer.\n", + __FILE__, __LINE__); + exit(1); + } + /* Tapered buffer support */ + if (TRUE == spice_model.output_buffer->tapered_buf) { + /* Each buf: svdd sgnd size=param*/ + fprintf(fp, "%s buf_out (", + spice_model.output_buffer->spice_model_name); /* subckt name */ + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "mux2_l%d_in[%d], ", 0 , 0); /* input port */ + fprintf(fp, "%s );", output_port[0]->prefix); /* Output port*/ + fprintf(fp, "\n"); + } + } else { + /* There is no buffer, I create a zero resisitance between*/ + /* Resistance R 0*/ + fprintf(fp, "assign mux2_l0_in[0] %s;\n",output_port[0]->prefix); + } + + fprintf(fp, "endmodule\n"); + fprintf(fp, "//------ END RRAM MUX info: spice_model_name=%s, size=%d -----\n\n", spice_model.name, mux_size); + fprintf(fp, "\n"); + + /* Free */ + my_free(mux_basis_subckt_name); + my_free(mux_special_basis_subckt_name); + my_free(input_port); + my_free(output_port); + my_free(sram_port); + + return; +} + +/** Dump a verilog module for a MUX + * We always dump a basis submodule for a MUX + * whatever structure it is: one-level, two-level or multi-level + */ +void dump_verilog_mux_module(FILE* fp, + t_spice_mux_model* spice_mux_model) { + /* Make sure we have a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); + exit(1); + } + /* Make sure we have a valid spice_model*/ + if (NULL == spice_mux_model) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid spice_mux_model!\n",__FILE__, __LINE__); + exit(1); + } + /* Make sure we have a valid spice_model*/ + if (NULL == spice_mux_model->spice_model) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid spice_model!\n",__FILE__, __LINE__); + exit(1); + } + + /* Check the mux size*/ + if (spice_mux_model->size < 2) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid MUX size(=%d)! Should be at least 2.\n", + __FILE__, __LINE__, spice_mux_model->size); + exit(1); + } + + /* Corner case: Error out MUX_SIZE = 2, automatcially give a one-level structure */ + if ((2 == spice_mux_model->size)&&(SPICE_MODEL_STRUCTURE_ONELEVEL != spice_mux_model->spice_model->design_tech_info.structure)) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Structure of SPICE model (%s) should be one-level because it is linked to a 2:1 MUX!\n", + __FILE__, __LINE__, spice_mux_model->spice_model->name); + exit(1); + } + + /* Print the definition of subckt*/ + /* Check the design technology*/ + switch (spice_mux_model->spice_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + dump_verilog_cmos_mux_submodule(fp, spice_mux_model->size, + *(spice_mux_model->spice_model), + *(spice_mux_model->spice_mux_arch)); + break; + case SPICE_MODEL_DESIGN_RRAM: + dump_verilog_rram_mux_submodule(fp, spice_mux_model->size, + *(spice_mux_model->spice_model), + *(spice_mux_model->spice_mux_arch)); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of MUX(name: %s)\n", + __FILE__, __LINE__, spice_mux_model->spice_model->name); + exit(1); + } + + return; +} + + +/*** Top-level function *****/ + +/* We should count how many multiplexers with different sizes are needed */ + +/**/ +void dump_verilog_submodule_muxes(char* submodule_dir, + int num_switch, + t_switch_inf* switches, + t_spice* spice, + t_det_routing_arch* routing_arch) { + + /* Statisitcs for input sizes and structures of MUXes + * used in FPGA architecture + */ + /* We have linked list whichs stores spice model information of multiplexer*/ + t_llist* muxes_head = NULL; + t_llist* temp = NULL; + int mux_cnt = 0; + int max_mux_size = -1; + int min_mux_size = -1; + FILE* fp = NULL; + char* verilog_name = my_strcat(submodule_dir,muxes_verilog_file_name); + int num_input_ports = 0; + t_spice_model_port** input_ports = NULL; + int num_sram_ports = 0; + t_spice_model_port** sram_ports = NULL; + + int num_input_basis = 0; + t_spice_mux_model* cur_spice_mux_model = NULL; + + int cur_bl, cur_wl; + int max_routing_mux_size = -1; + + /* Alloc the muxes*/ + muxes_head = stats_spice_muxes(num_switch, switches, spice, routing_arch); + + /* Print the muxes netlist*/ + fp = fopen(verilog_name, "w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create subckt SPICE netlist %s",__FILE__, __LINE__, verilog_name); + exit(1); + } + /* Generate the descriptions*/ + dump_verilog_file_header(fp,"MUXes used in FPGA"); + + /* Print mux netlist one by one*/ + temp = muxes_head; + while(temp) { + assert(NULL != temp->dptr); + cur_spice_mux_model = (t_spice_mux_model*)(temp->dptr); + /* Bypass the spice models who has a user-defined subckt */ + if (NULL != cur_spice_mux_model->spice_model->verilog_netlist) { + input_ports = find_spice_model_ports(cur_spice_mux_model->spice_model, SPICE_MODEL_PORT_INPUT, &num_input_ports, TRUE); + sram_ports = find_spice_model_ports(cur_spice_mux_model->spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_ports, TRUE); + assert(0 != num_input_ports); + assert(0 != num_sram_ports); + /* Check the Input port size */ + if (cur_spice_mux_model->size != input_ports[0]->size) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])User-defined MUX SPICE MODEL(%s) size(%d) unmatch with the architecture needs(%d)!\n", + __FILE__, __LINE__, cur_spice_mux_model->spice_model->name, input_ports[0]->size,cur_spice_mux_model->size); + exit(1); + } + /* Check the SRAM port size */ + num_input_basis = determine_num_input_basis_multilevel_mux(cur_spice_mux_model->size, + cur_spice_mux_model->spice_model->design_tech_info.mux_num_level); + if ((num_input_basis * cur_spice_mux_model->spice_model->design_tech_info.mux_num_level) != sram_ports[0]->size) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])User-defined MUX SPICE MODEL(%s) SRAM size(%d) unmatch with the num of level(%d)!\n", + __FILE__, __LINE__, cur_spice_mux_model->spice_model->name, sram_ports[0]->size, cur_spice_mux_model->spice_model->design_tech_info.mux_num_level*num_input_basis); + exit(1); + } + /* Move on to the next*/ + temp = temp->next; + continue; + } + /* Let's have a N:1 MUX as basis*/ + dump_verilog_mux_basis_module(fp, cur_spice_mux_model); + /* Print the mux subckt */ + dump_verilog_mux_module(fp, cur_spice_mux_model); + /* Update the statistics*/ + mux_cnt++; + if ((-1 == max_mux_size)||(max_mux_size < cur_spice_mux_model->size)) { + max_mux_size = cur_spice_mux_model->size; + } + if ((-1 == min_mux_size)||(min_mux_size > cur_spice_mux_model->size)) { + min_mux_size = cur_spice_mux_model->size; + } + /* Exclude LUT MUX from this statistics */ + if ((SPICE_MODEL_MUX == cur_spice_mux_model->spice_model->type) + &&((-1 == max_routing_mux_size)||(max_routing_mux_size < cur_spice_mux_model->size))) { + max_routing_mux_size = cur_spice_mux_model->size; + } + /* Move on to the next*/ + temp = temp->next; + } + + /* TODO: + * Scan-chain configuration circuit does not need any BLs/WLs! + * SRAM MUX does not need any reserved BL/WLs! + */ + /* Determine reserved Bit/Word Lines if a memory bank is specified, + * At least 1 BL/WL should be reserved! + */ + try_update_sram_orgz_info_reserved_blwl(sram_verilog_orgz_info, + max_routing_mux_size, max_routing_mux_size); + + vpr_printf(TIO_MESSAGE_INFO,"Generated %d Multiplexer submodules.\n", + mux_cnt); + vpr_printf(TIO_MESSAGE_INFO,"Max. MUX size = %d.\t", + max_mux_size); + vpr_printf(TIO_MESSAGE_INFO,"Min. MUX size = %d.\n", + min_mux_size); + + /* remember to free the linked list*/ + free_muxes_llist(muxes_head); + /* Free strings */ + free(verilog_name); + + /* Close the file*/ + fclose(fp); + + return; +} + +void dump_verilog_wire_module(FILE* fp, + char* wire_subckt_name, + t_spice_model verilog_model) { + int num_input_port = 0; + int num_output_port = 0; + t_spice_model_port** input_port = NULL; + t_spice_model_port** output_port = NULL; + + /* Ensure a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check the wire model*/ + assert(NULL != verilog_model.wire_param); + assert(0 < verilog_model.wire_param->level); + /* Find the input port, output port*/ + input_port = find_spice_model_ports(&verilog_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + output_port = find_spice_model_ports(&verilog_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + + /* Asserts*/ + assert(1 == num_input_port); + assert(1 == num_output_port); + assert(1 == input_port[0]->size); + assert(1 == output_port[0]->size); + /* print the spice model*/ + fprintf(fp, "//-----Wire module, verilog_model_name=%s -----\n", verilog_model.name); + switch (verilog_model.type) { + case SPICE_MODEL_CHAN_WIRE: + /* Add an output at middle point for connecting CB inputs */ + fprintf(fp, "module %s (\n", wire_subckt_name); + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &verilog_model, TRUE, FALSE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "input wire %s, output wire %s, output wire mid_out);\n", + input_port[0]->prefix, output_port[0]->prefix); + fprintf(fp, "\tassign %s = %s;\n", output_port[0]->prefix, input_port[0]->prefix); + fprintf(fp, "\tassign mid_out = %s;\n", input_port[0]->prefix); + break; + case SPICE_MODEL_WIRE: + /* Add an output at middle point for connecting CB inputs */ + fprintf(fp, "module %s (\n", + wire_subckt_name); + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &verilog_model, TRUE, FALSE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "input wire %s, output wire %s);\n", + input_port[0]->prefix, output_port[0]->prefix); + /* Direct shortcut */ + fprintf(fp, "\t\tassign %s = %s;\n", output_port[0]->prefix, input_port[0]->prefix); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of spice_model! Expect [chan_wire|wire].\n", + __FILE__, __LINE__); + exit(1); + } + + /* Finish*/ + fprintf(fp, "endmodule\n"); + fprintf(fp, "//-----END Wire module, verilog_model_name=%s -----\n", verilog_model.name); + fprintf(fp, "\n"); + + return; +} + +/* Dump one module of a LUT */ +void dump_verilog_submodule_one_lut(FILE* fp, + t_spice_model* verilog_model) { + int num_input_port = 0; + int num_output_port = 0; + int num_sram_port = 0; + t_spice_model_port** input_port = NULL; + t_spice_model_port** output_port = NULL; + t_spice_model_port** sram_port = NULL; + + /* Check */ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File handler.\n", + __FILE__, __LINE__); + exit(1); + } + assert(SPICE_MODEL_LUT == verilog_model->type); + + /* Print module name */ + fprintf(fp, "//-----LUT module, verilog_model_name=%s -----\n", verilog_model->name); + fprintf(fp, "module %s (", verilog_model->name); + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, FALSE)) { + fprintf(fp, ",\n"); + } + /* Print module port list */ + /* Find the input port, output port, and sram port*/ + input_port = find_spice_model_ports(verilog_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + output_port = find_spice_model_ports(verilog_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + sram_port = find_spice_model_ports(verilog_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); + + /* Asserts*/ + assert(1 == num_input_port); + assert(1 == num_output_port); + assert(1 == num_sram_port); + assert(1 == output_port[0]->size); + + /* input port */ + fprintf(fp, "input wire [0:%d] %s,\n", + input_port[0]->size - 1, input_port[0]->prefix); + /* Print output ports*/ + fprintf(fp, "output wire [0:%d] %s,\n", + output_port[0]->size - 1, output_port[0]->prefix); + /* Print configuration ports*/ + fprintf(fp, "input wire [0:%d] %s_out,\n", + sram_port[0]->size - 1, sram_port[0]->prefix); + /* Inverted configuration port is not connected to any internal signal of a LUT */ + fprintf(fp, "input wire [0:%d] %s_outb\n", + sram_port[0]->size - 1, sram_port[0]->prefix); + /* End of port list */ + fprintf(fp, ");\n"); + + /* Create inverted input port */ + fprintf(fp, " wire [0:%d] %s_b;\n", + input_port[0]->size - 1, input_port[0]->prefix); + /* Create inverters between input port and its inversion */ + fprintf(fp, " assign %s_b = ~ %s;\n", + input_port[0]->prefix, input_port[0]->prefix); + + /* Internal structure of a LUT */ + /* Call the LUT MUX */ + fprintf(fp, " %s_mux %s_mux_0_ (", + verilog_model->name, verilog_model->name); + /* Connect MUX inputs to LUT configuration port */ + fprintf(fp, " %s_out,", + sram_port[0]->prefix); + /* Connect MUX output to LUT output */ + fprintf(fp, " %s,", + output_port[0]->prefix); + /* Connect MUX configuration port to LUT inputs */ + fprintf(fp, " %s,", + input_port[0]->prefix); + /* Connect MUX inverted configuration port to inverted LUT inputs */ + fprintf(fp, " %s_b", + input_port[0]->prefix); + /* End of call LUT MUX */ + fprintf(fp, ");\n"); + + /* Print end of module */ + fprintf(fp, "endmodule\n"); + fprintf(fp, "//-----END LUT module, verilog_model_name=%s -----\n", verilog_model->name); + fprintf(fp, "\n"); + + return; +} + +/* Dump verilog top-level module for LUTs */ +void dump_verilog_submodule_luts(char* submodule_dir, + int num_spice_model, + t_spice_model* spice_models) { + FILE* fp = NULL; + char* verilog_name = my_strcat(submodule_dir, luts_verilog_file_name); + int imodel; + + /* Create File Handlers */ + fp = fopen(verilog_name, "w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create Verilog netlist %s",__FILE__, __LINE__, luts_verilog_file_name); + exit(1); + } + dump_verilog_file_header(fp,"Look-Up Tables"); + + /* Search for each LUT spice model */ + for (imodel = 0; imodel < num_spice_model; imodel++) { + /* Bypass user-defined spice models */ + if (NULL != spice_models[imodel].verilog_netlist) { + continue; + } + if (SPICE_MODEL_LUT == spice_models[imodel].type) { + dump_verilog_submodule_one_lut(fp, &(spice_models[imodel])); + } + } + + /* Close the file handler */ + fclose(fp); + + return; +} + +/* Dump a submodule which is a constant vdd */ +void dump_verilog_hard_wired_vdd(FILE* fp, + t_spice_model verilog_model) { + int num_output_port = 0; + t_spice_model_port** output_port = NULL; + + /* Find the input port, output port*/ + output_port = find_spice_model_ports(&verilog_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + + /* Asserts*/ + assert(1 == num_output_port); + assert(1 == output_port[0]->size); + + /* Ensure a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* print the spice model*/ + fprintf(fp, "//-----Hard-wired VDD module, verilog_model_name=%s -----\n", verilog_model.name); + fprintf(fp, "module %s(output wire %s);\n", verilog_model.name, output_port[0]->prefix); + /* Constant logic 1*/ + fprintf(fp, "assign %s = 1\'b1;\n", output_port[0]->prefix); + /* Finish*/ + fprintf(fp, "endmodule\n"); + fprintf(fp, "//-----END VDD module, verilog_model_name=%s -----\n", verilog_model.name); + fprintf(fp, "\n"); + return; +} + +/* Dump a submodule which is a constant vdd */ +void dump_verilog_hard_wired_gnd(FILE* fp, + t_spice_model verilog_model) { + int num_output_port = 0; + t_spice_model_port** output_port = NULL; + + /* Find the input port, output port*/ + output_port = find_spice_model_ports(&verilog_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + + /* Asserts*/ + assert(1 == num_output_port); + assert(1 == output_port[0]->size); + + /* Ensure a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* print the spice model*/ + fprintf(fp, "//-----Hard-wired GND module, verilog_model_name=%s -----\n", verilog_model.name); + fprintf(fp, "module %s(output wire %s);\n", verilog_model.name, output_port[0]->prefix); + /* Constant logic 1*/ + fprintf(fp, "assign %s = 1\'b0;\n", output_port[0]->prefix); + /* Finish*/ + fprintf(fp, "endmodule\n"); + fprintf(fp, "//-----END GND module, verilog_model_name=%s -----\n", verilog_model.name); + fprintf(fp, "\n"); + return; +} + +void dump_verilog_submodule_wires(char* subckt_dir, + int num_segments, + t_segment_inf* segments, + int num_spice_model, + t_spice_model* spice_models) { + FILE* fp = NULL; + char* verilog_name = my_strcat(subckt_dir, wires_verilog_file_name); + char* seg_wire_subckt_name = NULL; + char* seg_index_str = NULL; + int iseg, imodel, len_seg_subckt_name; + + fp = fopen(verilog_name, "w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create Verilog netlist %s",__FILE__, __LINE__, wires_verilog_file_name); + exit(1); + } + dump_verilog_file_header(fp,"Wires"); + /* Output wire models*/ + for (imodel = 0; imodel < num_spice_model; imodel++) { + /* Bypass user-defined spice models */ + if (NULL != spice_models[imodel].verilog_netlist) { + continue; + } + if (SPICE_MODEL_WIRE == spice_models[imodel].type) { + assert(NULL != spice_models[imodel].wire_param); + dump_verilog_wire_module(fp, spice_models[imodel].name, + spice_models[imodel]); + } + } + + /* Create wire models for routing segments*/ + fprintf(fp,"//----- Wire models for segments in routing -----\n"); + for (iseg = 0; iseg < num_segments; iseg++) { + assert(NULL != segments[iseg].spice_model); + assert(SPICE_MODEL_CHAN_WIRE == segments[iseg].spice_model->type); + assert(NULL != segments[iseg].spice_model->wire_param); + /* Give a unique name for subckt of wire_model of segment, + * spice_model name is unique, and segment name is unique as well + */ + seg_index_str = my_itoa(iseg); + len_seg_subckt_name = strlen(segments[iseg].spice_model->name) + + 4 + strlen(seg_index_str) + 1; /* '\0'*/ + seg_wire_subckt_name = (char*)my_malloc(sizeof(char)*len_seg_subckt_name); + sprintf(seg_wire_subckt_name,"%s_seg%s", + segments[iseg].spice_model->name, seg_index_str); + /* Bypass user-defined spice models */ + if (NULL != segments[iseg].spice_model->verilog_netlist) { + continue; + } + dump_verilog_wire_module(fp, seg_wire_subckt_name, + *(segments[iseg].spice_model)); + } + + /* Create module for hard-wired VDD and GND */ + for (imodel = 0; imodel < num_spice_model; imodel++) { + if (SPICE_MODEL_VDD == spice_models[imodel].type) { + dump_verilog_hard_wired_vdd(fp, spice_models[imodel]); + } else if (SPICE_MODEL_GND == spice_models[imodel].type) { + dump_verilog_hard_wired_gnd(fp, spice_models[imodel]); + } + } + + /* Close the file handler */ + fclose(fp); + + /*Free*/ + my_free(seg_index_str); + my_free(seg_wire_subckt_name); + + return; +} + + +/* Dump verilog files of submodules to be used in FPGA components : + * 1. MUXes + */ +void dump_verilog_submodules(char* submodule_dir, + t_arch Arch, + t_det_routing_arch* routing_arch) { + + /* 0. basic units: inverter, buffers and pass-gate logics, */ + vpr_printf(TIO_MESSAGE_INFO, "Generating essential modules...\n"); + dump_verilog_submodule_essentials(submodule_dir, + Arch.spice->num_spice_model, + Arch.spice->spice_models); + + /* 1. MUXes */ + vpr_printf(TIO_MESSAGE_INFO, "Generating modules of multiplexers...\n"); + dump_verilog_submodule_muxes(submodule_dir, routing_arch->num_switch, + switch_inf, Arch.spice, routing_arch); + + /* 2. LUTes */ + vpr_printf(TIO_MESSAGE_INFO, "Generating modules of LUTs...\n"); + dump_verilog_submodule_luts(submodule_dir, + Arch.spice->num_spice_model, Arch.spice->spice_models); + + /* 3. Hardwires */ + vpr_printf(TIO_MESSAGE_INFO, "Generating modules of hardwires...\n"); + dump_verilog_submodule_wires(submodule_dir, Arch.num_segments, Arch.Segments, + Arch.spice->num_spice_model, Arch.spice->spice_models); + + return; +} + diff --git a/vpr7_rram/vpr/SRC/syn_verilog/verilog_submodules.h b/vpr7_rram/vpr/SRC/syn_verilog/verilog_submodules.h new file mode 100644 index 000000000..f52eb6b16 --- /dev/null +++ b/vpr7_rram/vpr/SRC/syn_verilog/verilog_submodules.h @@ -0,0 +1,4 @@ + +void dump_verilog_submodules(char* submodule_dir, + t_arch Arch, + t_det_routing_arch* routing_arch); diff --git a/vpr7_rram/vpr/SRC/syn_verilog/verilog_top_netlist.c b/vpr7_rram/vpr/SRC/syn_verilog/verilog_top_netlist.c new file mode 100644 index 000000000..f882dc3d6 --- /dev/null +++ b/vpr7_rram/vpr/SRC/syn_verilog/verilog_top_netlist.c @@ -0,0 +1,2673 @@ +/***********************************/ +/* Dump Synthesizable Veriolog */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph.h" +#include "vpr_utils.h" + +/* Include spice support headers*/ +#include "read_xml_spice_util.h" +#include "linkedlist.h" +#include "fpga_spice_utils.h" +#include "fpga_spice_backannotate_utils.h" +#include "fpga_spice_globals.h" +#include "fpga_spice_bitstream.h" + +/* Include verilog support headers*/ +#include "verilog_global.h" +#include "verilog_utils.h" +#include "verilog_routing.h" +#include "verilog_pbtypes.h" +#include "verilog_decoder.h" +#include "verilog_top_netlist.h" + + +/* Global varaiable only accessible in this source file*/ +static char* top_netlist_bl_enable_port_name = "en_bl"; +static char* top_netlist_wl_enable_port_name = "en_wl"; +static char* top_netlist_bl_data_in_port_name = "data_in"; +static char* top_netlist_addr_bl_port_name = "addr_bl"; +static char* top_netlist_addr_wl_port_name = "addr_wl"; +static char* top_netlist_array_bl_port_name = "bl_bus"; +static char* top_netlist_array_wl_port_name = "wl_bus"; +static char* top_netlist_array_blb_port_name = "blb_bus"; +static char* top_netlist_array_wlb_port_name = "wlb_bus"; +static char* top_netlist_reserved_bl_port_postfix = "_reserved_bl"; +static char* top_netlist_reserved_wl_port_postfix = "_reserved_wl"; +static char* top_netlist_normal_bl_port_postfix = "_bl"; +static char* top_netlist_normal_wl_port_postfix = "_wl"; +static char* top_netlist_normal_blb_port_postfix = "_blb"; +static char* top_netlist_normal_wlb_port_postfix = "_wlb"; +static char* top_netlist_scan_chain_head_prefix = "sc_in"; + +static float verilog_sim_timescale = 1e-9; // Verilog Simulation time scale (minimum time unit) : 1ns +static char* top_tb_reset_port_name = "greset"; +static char* top_tb_set_port_name = "gset"; +static char* top_tb_prog_reset_port_name = "prog_reset"; +static char* top_tb_prog_set_port_name = "prog_set"; +static char* top_tb_config_done_port_name = "config_done"; +static char* top_tb_op_clock_port_name = "op_clock"; +static char* top_tb_prog_clock_port_name = "prog_clock"; +static char* top_tb_inout_reg_postfix = "_reg"; +static char* top_tb_clock_reg_postfix = "_reg"; + +/* Local Subroutines declaration */ + +/******** Subroutines ***********/ + +static +void dump_verilog_top_netlist_memory_bank_ports(FILE* fp, + enum e_dump_verilog_port_type dump_port_type) { + t_spice_model* mem_model = NULL; + int num_array_bl, num_array_wl; + int bl_decoder_size, wl_decoder_size; + char split_sign; + + split_sign = determine_verilog_generic_port_split_sign(dump_port_type); + + /* Only accept two types of dump_port_type here! */ + assert((VERILOG_PORT_INPUT == dump_port_type)||(VERILOG_PORT_CONKT == dump_port_type)); + + /* Check */ + assert (sram_verilog_orgz_info->type == SPICE_SRAM_MEMORY_BANK); + + /* A valid file handler */ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* Depending on the memory technology*/ + get_sram_orgz_info_mem_model(sram_verilog_orgz_info, &mem_model); + assert(NULL != mem_model); + + determine_verilog_blwl_decoder_size(sram_verilog_orgz_info, + &num_array_bl, &num_array_wl, &bl_decoder_size, &wl_decoder_size); + + /* Depend on the memory technology */ + switch (mem_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + dump_verilog_generic_port(fp, dump_port_type, + top_netlist_bl_enable_port_name, 0, 0); + fprintf(fp, "%c //--- BL enable port \n", split_sign); + dump_verilog_generic_port(fp, dump_port_type, + top_netlist_wl_enable_port_name, 0, 0); + fprintf(fp, "%c //--- WL enable port \n", split_sign); + dump_verilog_generic_port(fp, dump_port_type, + top_netlist_bl_data_in_port_name, 0, 0); + fprintf(fp, "%c //--- BL data input port \n", split_sign); + break; + case SPICE_MODEL_DESIGN_RRAM: + dump_verilog_generic_port(fp, dump_port_type, + top_netlist_bl_enable_port_name, 0, 0); + fprintf(fp, "%c //--- BL enable port \n", split_sign); + dump_verilog_generic_port(fp, dump_port_type, + top_netlist_wl_enable_port_name, 0, 0); + fprintf(fp, "%c //--- WL enable port \n", split_sign); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization in Verilog Generator!\n", + __FILE__, __LINE__); + exit(1); + } + + dump_verilog_generic_port(fp, dump_port_type, + top_netlist_addr_bl_port_name, bl_decoder_size - 1, 0); + fprintf(fp, "%c //--- Address of bit lines \n", split_sign); + dump_verilog_generic_port(fp, dump_port_type, + top_netlist_addr_wl_port_name, wl_decoder_size - 1, 0); + fprintf(fp, " //--- Address of word lines \n"); + + return; +} + +/* Connect BLs and WLs to configuration bus in the top-level Verilog netlist*/ +static +void dump_verilog_top_netlist_memory_bank_internal_wires(FILE* fp) { + t_spice_model* mem_model = NULL; + int iinv, icol, irow; + int num_bl, num_wl; + int num_array_bl, num_array_wl; + int num_reserved_bl, num_reserved_wl; + int cur_bl_lsb, cur_wl_lsb; + int cur_bl_msb, cur_wl_msb; + int bl_decoder_size, wl_decoder_size; + int num_blb_ports, num_wlb_ports; + t_spice_model_port** blb_port = NULL; + t_spice_model_port** wlb_port = NULL; + t_spice_model* blb_inv_spice_model = NULL; + t_spice_model* wlb_inv_spice_model = NULL; + + /* Check */ + assert (sram_verilog_orgz_info->type == SPICE_SRAM_MEMORY_BANK); + + /* A valid file handler */ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* Depending on the memory technology*/ + get_sram_orgz_info_mem_model(sram_verilog_orgz_info, &mem_model); + assert(NULL != mem_model); + + /* Get the total number of BLs and WLs */ + get_sram_orgz_info_num_blwl(sram_verilog_orgz_info, &num_bl, &num_wl); + /* Get the reserved BLs and WLs */ + get_sram_orgz_info_reserved_blwl(sram_verilog_orgz_info, &num_reserved_bl, &num_reserved_wl); + + determine_verilog_blwl_decoder_size(sram_verilog_orgz_info, + &num_array_bl, &num_array_wl, &bl_decoder_size, &wl_decoder_size); + + /* Get BLB and WLB ports */ + find_blb_wlb_ports_spice_model(mem_model, &num_blb_ports, &blb_port, + &num_wlb_ports, &wlb_port); + /* Get inverter spice_model */ + + /* Important!!!: + * BL/WL should always start from LSB to MSB! + * In order to follow this convention in primitive nodes. + */ + /* No. of BLs and WLs in the array */ + dump_verilog_generic_port(fp, VERILOG_PORT_WIRE, + top_netlist_array_bl_port_name, 0, num_array_bl - 1); + fprintf(fp, "; //--- Array Bit lines bus \n"); + dump_verilog_generic_port(fp, VERILOG_PORT_WIRE, + top_netlist_array_wl_port_name, 0, num_array_wl - 1); + fprintf(fp, "; //--- Array Bit lines bus \n"); + if (1 == num_blb_ports) { + dump_verilog_generic_port(fp, VERILOG_PORT_WIRE, + top_netlist_array_blb_port_name, 0, num_array_bl - 1); + fprintf(fp, "; //--- Inverted Array Bit lines bus \n"); + } + if (1 == num_wlb_ports) { + dump_verilog_generic_port(fp, VERILOG_PORT_WIRE, + top_netlist_array_wlb_port_name, 0, num_array_wl - 1); + fprintf(fp, "; //--- Inverted Array Word lines bus \n"); + } + fprintf(fp, "\n"); + + switch (mem_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + assert( 0 == num_reserved_bl ); + assert( 0 == num_reserved_wl ); + /* SRAMs are place in an array + * BLs of SRAMs in the same column are connected to a common BL + * BLs of SRAMs in the same row are connected to a common WL + */ + /* Declare wires */ + fprintf(fp, " wire [%d:%d] %s%s; //---- Normal Bit lines \n", + 0, num_bl - 1, mem_model->prefix, top_netlist_normal_bl_port_postfix); + fprintf(fp, " wire [%d:%d] %s%s; //---- Normal Word lines \n", + 0, num_wl - 1, mem_model->prefix, top_netlist_normal_wl_port_postfix); + /* Declare inverted wires if needed */ + if (1 == num_blb_ports) { + fprintf(fp, " wire [%d:%d] %s%s; //---- Inverted Normal Bit lines \n", + 0, num_bl - 1, mem_model->prefix, top_netlist_normal_blb_port_postfix); + /* get inv_spice_model */ + blb_inv_spice_model = blb_port[0]->inv_spice_model; + /* Make an inversion of the BL */ + for (iinv = 0; iinv < num_array_bl - 1; iinv++) { + fprintf(fp, " %s %s_blb_%d (%s[%d], %s[%d]);\n", + blb_inv_spice_model->name, blb_inv_spice_model->prefix, + iinv, + top_netlist_array_bl_port_name, iinv, + top_netlist_array_blb_port_name, iinv); + } + } + if (1 == num_wlb_ports) { + fprintf(fp, " wire [%d:%d] %s%s; //---- Inverted Normal Word lines \n", + 0, num_wl - 1, mem_model->prefix, top_netlist_normal_wlb_port_postfix); + /* get inv_spice_model */ + wlb_inv_spice_model = wlb_port[0]->inv_spice_model; + /* Make an inversion of the WL */ + for (iinv = 0; iinv < num_array_wl - 1; iinv++) { + fprintf(fp, " %s %s_wlb_%d (%s[%d], %s[%d]);\n", + wlb_inv_spice_model->name, wlb_inv_spice_model->prefix, + iinv, + top_netlist_array_wl_port_name, iinv, + top_netlist_array_wlb_port_name, iinv); + } + } + /* Connections for columns */ + for (icol = 0; icol < num_array_bl; icol++) { + cur_bl_lsb = icol * num_array_bl; + cur_bl_msb = (icol + 1) * num_array_bl - 1; + /* Check if the msb exceeds the upbound of num_bl */ + if (cur_bl_msb > num_bl - 1) { + cur_bl_msb = num_bl - 1; + } + /* connect to the BLs of all the SRAMs in the column */ + fprintf(fp, " assign %s%s[%d:%d] = %s[%d:%d];\n", + mem_model->prefix, top_netlist_normal_bl_port_postfix, cur_bl_lsb, cur_bl_msb, + top_netlist_array_bl_port_name, 0, cur_bl_msb - cur_bl_lsb); + if (1 == num_blb_ports) { + fprintf(fp, " assign %s%s[%d:%d] = %s[%d:%d];\n", + mem_model->prefix, top_netlist_normal_blb_port_postfix, cur_bl_lsb, cur_bl_msb, + top_netlist_array_blb_port_name, 0, cur_bl_msb - cur_bl_lsb); + } + /* Finish if MSB meets the upbound */ + if (cur_bl_msb == num_bl - 1) { + break; + } + } + /* Connections for rows */ + for (irow = 0; irow < num_array_wl; irow++) { + cur_wl_lsb = irow * num_array_wl; + cur_wl_msb = (irow + 1) * num_array_wl - 1; + /* Check if the msb exceeds the upbound of num_bl */ + if (cur_wl_msb > num_wl - 1) { + cur_wl_msb = num_wl - 1; + } + /* connect to the BLs of all the SRAMs in the column */ + for (icol = cur_wl_lsb; icol < cur_wl_msb + 1; icol++) { + fprintf(fp, " assign %s%s[%d] = %s[%d];\n", + mem_model->prefix, top_netlist_normal_wl_port_postfix, icol, + top_netlist_array_wl_port_name, irow); + if (1 == num_wlb_ports) { + fprintf(fp, " assign %s%s[%d] = %s[%d];\n", + mem_model->prefix, top_netlist_normal_wlb_port_postfix, icol, + top_netlist_array_wlb_port_name, irow); + } + } + /* Finish if MSB meets the upbound */ + if (cur_wl_msb == num_wl - 1) { + break; + } + } + break; + case SPICE_MODEL_DESIGN_RRAM: + /* Check: there should be reserved BLs and WLs */ + assert( 0 < num_reserved_bl ); + assert( 0 < num_reserved_wl ); + /* Declare reserved and normal conf_bits ports */ + fprintf(fp, " wire [0:%d] %s%s; //---- Reserved Bit lines \n", + num_reserved_bl - 1, mem_model->prefix, top_netlist_reserved_bl_port_postfix); + fprintf(fp, " wire [0:%d] %s%s; //---- Reserved Word lines \n", + num_reserved_wl - 1, mem_model->prefix, top_netlist_reserved_wl_port_postfix); + fprintf(fp, " wire [%d:%d] %s%s; //---- Normal Bit lines \n", + num_reserved_bl, num_array_bl - 1, mem_model->prefix, top_netlist_normal_bl_port_postfix); + fprintf(fp, " wire [%d:%d] %s%s; //---- Normal Word lines \n", + num_reserved_wl, num_array_wl - 1, mem_model->prefix, top_netlist_normal_wl_port_postfix); + /* Connect reserved conf_bits and normal conf_bits to the bus */ + fprintf(fp, " assign %s%s[0:%d] = %s[0:%d];\n", + mem_model->prefix, top_netlist_reserved_bl_port_postfix, num_reserved_bl - 1, + top_netlist_array_bl_port_name, num_reserved_bl - 1); + fprintf(fp, " assign %s%s[0:%d] = %s[0:%d];\n", + mem_model->prefix, top_netlist_reserved_wl_port_postfix, num_reserved_wl - 1, + top_netlist_array_wl_port_name, num_reserved_wl - 1); + fprintf(fp, " assign %s%s[%d:%d] = %s[%d:%d];\n", + mem_model->prefix, top_netlist_normal_bl_port_postfix, num_reserved_bl, num_array_bl - 1, + top_netlist_array_bl_port_name, num_reserved_bl, num_array_bl - 1); + fprintf(fp, " assign %s%s[%d:%d] = %s[%d:%d];\n", + mem_model->prefix, top_netlist_normal_wl_port_postfix, num_reserved_wl, num_array_wl - 1, + top_netlist_array_wl_port_name, num_reserved_wl, num_array_wl - 1); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization in Verilog Generator!\n", + __FILE__, __LINE__); + exit(1); + } + + return; +} + +/* Delcare primary inputs/outputs for scan-chains in the top-level netlists + */ +static +void dump_verilog_top_netlist_scan_chain_ports(FILE* fp, + enum e_dump_verilog_port_type dump_port_type) { + /* Only accept two types of dump_port_type here! */ + assert((VERILOG_PORT_INPUT == dump_port_type)||(VERILOG_PORT_CONKT == dump_port_type)); + + /* Check */ + assert (sram_verilog_orgz_info->type == SPICE_SRAM_SCAN_CHAIN); + + /* A valid file handler */ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* Only the head of scan-chain will be the primary input in the top-level netlist + * TODO: we may have multiple scan-chains, their heads will be the primary outputs + */ + dump_verilog_generic_port(fp, dump_port_type, + top_netlist_scan_chain_head_prefix, 0, 0); + fprintf(fp, " //---- Scan-chain head \n"); + + return; +} + +/* Connect scan-chain flip-flops in the top-level netlist */ +static +void dump_verilog_top_netlist_scan_chain_internal_wires(FILE* fp) { + t_spice_model* scff_mem_model = NULL; + int iscff, num_scffs; + + /* A valid file handler */ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + num_scffs = get_sram_orgz_info_num_mem_bit(sram_verilog_orgz_info); + get_sram_orgz_info_mem_model(sram_verilog_orgz_info, &scff_mem_model); + /* Check */ + assert( SPICE_MODEL_SCFF == scff_mem_model->type ); + + /* Delcare local wires */ + fprintf(fp, " wire [0:%d] %s_scff_in;\n", + num_scffs - 1, scff_mem_model->prefix); + + fprintf(fp, " wire [0:%d] %s_scff_out;\n", + num_scffs - 1, scff_mem_model->prefix); + + /* Exception for head: connect to primary inputs */ + fprintf(fp, " assign %s_scff_in[%d] = %s;\n", + scff_mem_model->prefix, 0, + top_netlist_scan_chain_head_prefix); + + /* Connected the scan-chain flip-flops */ + /* Ensure we are in the correct range */ + /* + fprintf(fp, " genvar i;\n"); + fprintf(fp, " generate\n"); + fprintf(fp, " for (i = %d; i < %d; i = i + 1) begin\n", + 1, num_scffs - 1); + fprintf(fp, "assign %s_scff_in[i] = %s_scff_out[i - 1];\n", + scff_mem_model->prefix, + scff_mem_model->prefix); + fprintf(fp, " end\n"); + fprintf(fp, " endgenerate;\n"); + */ + + return; +} + +/* Dump ports for the top-level module in Verilog netlist */ +static +void dump_verilog_top_module_ports(FILE* fp, + enum e_dump_verilog_port_type dump_port_type) { + char* port_name = NULL; + char split_sign; + enum e_dump_verilog_port_type actual_dump_port_type; + boolean dump_global_port_type = FALSE; + + split_sign = determine_verilog_generic_port_split_sign(dump_port_type); + + /* Only accept two types of dump_port_type here! */ + assert((VERILOG_PORT_INPUT == dump_port_type)||(VERILOG_PORT_CONKT == dump_port_type)); + + if (VERILOG_PORT_INPUT == dump_port_type) { + dump_global_port_type = TRUE; + } + + /* dump global ports */ + if (0 < dump_verilog_global_ports(fp, global_ports_head, dump_global_port_type)) { + fprintf(fp, "%c\n", split_sign); + } + /* Inputs and outputs of I/O pads */ + /* Inout Pads */ + assert(NULL != iopad_verilog_model); + if ((NULL == iopad_verilog_model) + ||(iopad_verilog_model->cnt > 0)) { + actual_dump_port_type = VERILOG_PORT_CONKT; + if (VERILOG_PORT_INPUT == dump_port_type) { + actual_dump_port_type = VERILOG_PORT_INOUT; + } + /* Malloc and assign port_name */ + port_name = (char*)my_malloc(sizeof(char)*(strlen(gio_inout_prefix) + strlen(iopad_verilog_model->prefix) + 1)); + sprintf(port_name, "%s%s", gio_inout_prefix, iopad_verilog_model->prefix); + /* Dump a register port */ + dump_verilog_generic_port(fp, actual_dump_port_type, + port_name, iopad_verilog_model->cnt - 1, 0); + fprintf(fp, "%c //---FPGA inouts \n", split_sign); + /* Free port_name */ + my_free(port_name); + } + + /* Configuration ports depend on the organization of SRAMs */ + switch(sram_verilog_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + dump_verilog_generic_port(fp, dump_port_type, + sram_verilog_model->prefix, sram_verilog_model->cnt - 1, 0); + fprintf(fp, " //--- SRAM outputs \n"); + /* Definition ends */ + break; + case SPICE_SRAM_SCAN_CHAIN: + dump_verilog_top_netlist_scan_chain_ports(fp, dump_port_type); + /* Definition ends */ + break; + case SPICE_SRAM_MEMORY_BANK: + dump_verilog_top_netlist_memory_bank_ports(fp, dump_port_type); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization in Verilog Generator!\n", + __FILE__, __LINE__); + exit(1); + } + + return; +} + + +/* Dump ports for the top-level Verilog netlist */ +static +void dump_verilog_top_netlist_ports(FILE* fp, + int num_clocks, + char* circuit_name, + t_spice verilog) { + int num_array_bl, num_array_wl; + int bl_decoder_size, wl_decoder_size; + char* port_name = NULL; + + /* A valid file handler */ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + fprintf(fp, "//----- Top-level Verilog Module -----\n"); + fprintf(fp, "module %s_top (\n", circuit_name); + fprintf(fp, "\n"); + + dump_verilog_top_module_ports(fp, VERILOG_PORT_INPUT); + + fprintf(fp, ");\n"); + + return; +} + + +static +void dump_verilog_top_netlist_internal_wires(FILE* fp) { + /* Configuration ports depend on the organization of SRAMs */ + switch(sram_verilog_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + /* Definition ends */ + break; + case SPICE_SRAM_SCAN_CHAIN: + dump_verilog_top_netlist_scan_chain_internal_wires(fp); + /* Definition ends */ + break; + case SPICE_SRAM_MEMORY_BANK: + dump_verilog_top_netlist_memory_bank_internal_wires(fp); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization in Verilog Generator!\n", + __FILE__, __LINE__); + exit(1); + } + + return; +} + +static +void dump_verilog_defined_one_grid(FILE* fp, + int ix, int iy) { + /* Comment lines */ + fprintf(fp, "//----- BEGIN Call Grid[%d][%d] module -----\n", ix, iy); + /* Print the Grid module */ + fprintf(fp, "grid_%d__%d_ ", ix, iy); /* Call the name of subckt */ + fprintf(fp, "grid_%d__%d__0_ ", ix, iy); + fprintf(fp, "("); + fprintf(fp, "\n"); + /* dump global ports */ + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + fprintf(fp, ",\n"); + } + + if (IO_TYPE == grid[ix][iy].type) { + dump_verilog_io_grid_pins(fp, ix, iy, 1, FALSE, FALSE); + } else { + dump_verilog_grid_pins(fp, ix, iy, 1, FALSE, FALSE); + } + + /* IO PAD */ + dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix, + iopad_verilog_model->grid_index_low[ix][iy], + iopad_verilog_model->grid_index_high[ix][iy] - 1, + VERILOG_PORT_CONKT); + + /* Print configuration ports */ + /* Reserved configuration ports */ + if (0 < sram_verilog_orgz_info->grid_reserved_conf_bits[ix][iy]) { + fprintf(fp, ",\n"); + } + dump_verilog_reserved_sram_ports(fp, sram_verilog_orgz_info, + 0, + sram_verilog_orgz_info->grid_reserved_conf_bits[ix][iy] - 1, + VERILOG_PORT_CONKT); + /* Normal configuration ports */ + if (0 < (sram_verilog_orgz_info->grid_conf_bits_msb[ix][iy] + - sram_verilog_orgz_info->grid_conf_bits_lsb[ix][iy])) { + fprintf(fp, ",\n"); + } + dump_verilog_sram_ports(fp, sram_verilog_orgz_info, + sram_verilog_orgz_info->grid_conf_bits_lsb[ix][iy], + sram_verilog_orgz_info->grid_conf_bits_msb[ix][iy] - 1, + VERILOG_PORT_CONKT); + fprintf(fp, ");\n"); + /* Comment lines */ + fprintf(fp, "//----- END call Grid[%d][%d] module -----\n\n", ix, iy); + + return; +} + + +/***** Print (call) the defined grids *****/ +void dump_verilog_defined_grids(FILE* fp) { + int ix, iy; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* Normal Grids */ + for (ix = 1; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + assert(IO_TYPE != grid[ix][iy].type); + dump_verilog_defined_one_grid(fp, ix, iy); + } + } + + /* IO Grids */ + /* LEFT side */ + ix = 0; + for (iy = 1; iy < (ny + 1); iy++) { + assert(IO_TYPE == grid[ix][iy].type); + dump_verilog_defined_one_grid(fp, ix, iy); + } + + /* RIGHT side */ + ix = nx + 1; + for (iy = 1; iy < (ny + 1); iy++) { + assert(IO_TYPE == grid[ix][iy].type); + dump_verilog_defined_one_grid(fp, ix, iy); + } + + /* BOTTOM side */ + iy = 0; + for (ix = 1; ix < (nx + 1); ix++) { + assert(IO_TYPE == grid[ix][iy].type); + dump_verilog_defined_one_grid(fp, ix, iy); + } + + /* TOP side */ + iy = ny + 1; + for (ix = 1; ix < (nx + 1); ix++) { + assert(IO_TYPE == grid[ix][iy].type); + dump_verilog_defined_one_grid(fp, ix, iy); + } + + return; +} + +/* Call defined channels. + * Ensure the port name here is co-herent to other sub-circuits(SB,CB,grid)!!! + */ +void dump_verilog_defined_one_channel(FILE* fp, + t_rr_type chan_type, int x, int y, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices) { + int itrack; + int chan_width = 0; + t_rr_node** chan_rr_nodes = NULL; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((CHANX == chan_type)||(CHANY == chan_type)); + /* check x*/ + assert((!(0 > x))&&(x < (nx + 1))); + /* check y*/ + assert((!(0 > y))&&(y < (ny + 1))); + + /* Collect rr_nodes for Tracks for chanx[ix][iy] */ + chan_rr_nodes = get_chan_rr_nodes(&chan_width, chan_type, x, y, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + + /* Comment lines */ + switch (chan_type) { + case CHANX: + fprintf(fp, "//----- BEGIN Call Channel-X [%d][%d] module -----\n", x, y); + break; + case CHANY: + fprintf(fp, "//----- BEGIN call Channel-Y [%d][%d] module -----\n\n", x, y); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid Channel Type!\n", __FILE__, __LINE__); + exit(1); + } + + /* Call the define sub-circuit */ + fprintf(fp, "%s_%d__%d_ ", + convert_chan_type_to_string(chan_type), + x, y); + fprintf(fp, "%s_%d__%d__0_ ", + convert_chan_type_to_string(chan_type), + x, y); + fprintf(fp, "("); + fprintf(fp, "\n"); + /* dump global ports */ + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + fprintf(fp, ",\n"); + } + + /* LEFT/BOTTOM side port of CHANX/CHANY */ + /* We apply an opposite port naming rule than function: fprint_routing_chan_subckt + * In top-level netlists, we follow the same port name as switch blocks and connection blocks + * When a track is in INC_DIRECTION, the LEFT/BOTTOM port would be an output of a switch block + * When a track is in DEC_DIRECTION, the LEFT/BOTTOM port would be an input of a switch block + */ + for (itrack = 0; itrack < chan_width; itrack++) { + switch (chan_rr_nodes[itrack]->direction) { + case INC_DIRECTION: + fprintf(fp, "%s_%d__%d__out_%d_, ", + convert_chan_type_to_string(chan_type), + x, y, itrack); + fprintf(fp, "\n"); + break; + case DEC_DIRECTION: + fprintf(fp, "%s_%d__%d__in_%d_, ", + convert_chan_type_to_string(chan_type), + x, y, itrack); + fprintf(fp, "\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of %s[%d][%d]_track[%d]!\n", + __FILE__, __LINE__, + convert_chan_type_to_string(chan_type), + x, y, itrack); + exit(1); + } + } + /* RIGHT/TOP side port of CHANX/CHANY */ + /* We apply an opposite port naming rule than function: fprint_routing_chan_subckt + * In top-level netlists, we follow the same port name as switch blocks and connection blocks + * When a track is in INC_DIRECTION, the RIGHT/TOP port would be an input of a switch block + * When a track is in DEC_DIRECTION, the RIGHT/TOP port would be an output of a switch block + */ + for (itrack = 0; itrack < chan_width; itrack++) { + switch (chan_rr_nodes[itrack]->direction) { + case INC_DIRECTION: + fprintf(fp, "%s_%d__%d__in_%d_, ", + convert_chan_type_to_string(chan_type), + x, y, itrack); + fprintf(fp, "\n"); + break; + case DEC_DIRECTION: + fprintf(fp, "%s_%d__%d__out_%d_, ", + convert_chan_type_to_string(chan_type), + x, y, itrack); + fprintf(fp, "\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of %s[%d][%d]_track[%d]!\n", + __FILE__, __LINE__, + convert_chan_type_to_string(chan_type), + x, y, itrack); + exit(1); + } + } + + /* output at middle point */ + for (itrack = 0; itrack < chan_width; itrack++) { + fprintf(fp, "%s_%d__%d__midout_%d_ ", + convert_chan_type_to_string(chan_type), + x, y, itrack); + if (itrack < chan_width - 1) { + fprintf(fp, ","); + } + fprintf(fp, "\n"); + } + fprintf(fp, ");\n"); + + /* Comment lines */ + switch (chan_type) { + case CHANX: + fprintf(fp, "//----- END Call Channel-X [%d][%d] module -----\n", x, y); + break; + case CHANY: + fprintf(fp, "//----- END call Channel-Y [%d][%d] module -----\n\n", x, y); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid Channel Type!\n", __FILE__, __LINE__); + exit(1); + } + + /* Free */ + my_free(chan_rr_nodes); + + return; +} + +/* Call the sub-circuits for channels : Channel X and Channel Y*/ +void dump_verilog_defined_channels(FILE* fp, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices) { + int ix, iy; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* Channel X */ + for (iy = 0; iy < (ny + 1); iy++) { + for (ix = 1; ix < (nx + 1); ix++) { + dump_verilog_defined_one_channel(fp, CHANX, ix, iy, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + } + } + + /* Channel Y */ + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + dump_verilog_defined_one_channel(fp, CHANY, ix, iy, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + } + } + + return; +} + +/* Call the defined sub-circuit of connection box + * TODO: actually most of this function is copied from + * spice_routing.c : dump_verilog_conneciton_box_interc + * Should be more clever to use the original function + */ +void dump_verilog_defined_one_connection_box(FILE* fp, + t_cb cur_cb_info) { + int itrack, inode, side, x, y; + int side_cnt = 0; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check */ + assert((!(0 > cur_cb_info.x))&&(!(cur_cb_info.x > (nx + 1)))); + assert((!(0 > cur_cb_info.y))&&(!(cur_cb_info.y > (ny + 1)))); + + x = cur_cb_info.x; + y = cur_cb_info.y; + + /* Print the definition of subckt*/ + /* Identify the type of connection box */ + switch(cur_cb_info.type) { + case CHANX: + /* Comment lines */ + fprintf(fp, "//----- BEGIN Call Connection Box-X direction [%d][%d] module -----\n", x, y); + /* Print module */ + fprintf(fp, "cbx_%d__%d_ ", x, y); + fprintf(fp, "cbx_%d__%d__0_ ", x, y); + break; + case CHANY: + /* Comment lines */ + fprintf(fp, "//----- BEGIN Call Connection Box-Y direction [%d][%d] module -----\n", x, y); + /* Print module */ + fprintf(fp, "cby_%d__%d_ ", x, y); + fprintf(fp, "cby_%d__%d__0_ ", x, y); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); + exit(1); + } + + fprintf(fp, "("); + fprintf(fp, "\n"); + /* dump global ports */ + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + fprintf(fp, ",\n"); + } + + /* Print the ports of channels*/ + /* connect to the mid point of a track*/ + side_cnt = 0; + for (side = 0; side < cur_cb_info.num_sides; side++) { + /* Bypass side with zero channel width */ + if (0 == cur_cb_info.chan_width[side]) { + continue; + } + assert (0 < cur_cb_info.chan_width[side]); + side_cnt++; + fprintf(fp, "//----- %s side inputs: channel track middle outputs -----\n", convert_side_index_to_string(side)); + for (itrack = 0; itrack < cur_cb_info.chan_width[side]; itrack++) { + fprintf(fp, "%s_%d__%d__midout_%d_, ", + convert_chan_type_to_string(cur_cb_info.type), + cur_cb_info.x, cur_cb_info.y, itrack); + fprintf(fp, "\n"); + } + } + /*check side_cnt */ + assert(1 == side_cnt); + + side_cnt = 0; + /* Print the ports of grids*/ + for (side = 0; side < cur_cb_info.num_sides; side++) { + /* Bypass side with zero IPINs*/ + if (0 == cur_cb_info.num_ipin_rr_nodes[side]) { + continue; + } + side_cnt++; + assert(0 < cur_cb_info.num_ipin_rr_nodes[side]); + assert(NULL != cur_cb_info.ipin_rr_node[side]); + fprintf(fp, "//----- %s side outputs: CLB input pins -----\n", convert_side_index_to_string(side)); + for (inode = 0; inode < cur_cb_info.num_ipin_rr_nodes[side]; inode++) { + /* Print each INPUT Pins of a grid */ + dump_verilog_grid_side_pin_with_given_index(fp, OPIN, + cur_cb_info.ipin_rr_node[side][inode]->ptc_num, + cur_cb_info.ipin_rr_node_grid_side[side][inode], + cur_cb_info.ipin_rr_node[side][inode]->xlow, + cur_cb_info.ipin_rr_node[side][inode]->ylow, + FALSE); /* Do not specify direction of port */ + fprintf(fp, ", \n"); + } + } + /* Make sure only 2 sides of IPINs are printed */ + assert((1 == side_cnt)||(2 == side_cnt)); + + /* Configuration ports */ + /* Reserved sram ports */ + dump_verilog_reserved_sram_ports(fp, sram_verilog_orgz_info, + 0, cur_cb_info.num_reserved_conf_bits - 1, + VERILOG_PORT_CONKT); + /* Normal sram ports */ + if (0 < (cur_cb_info.num_reserved_conf_bits)) { + fprintf(fp, ",\n"); + } + dump_verilog_sram_ports(fp, sram_verilog_orgz_info, + cur_cb_info.conf_bits_lsb, cur_cb_info.conf_bits_msb - 1, + VERILOG_PORT_CONKT); + + fprintf(fp, ");\n"); + + /* Comment lines */ + switch(cur_cb_info.type) { + case CHANX: + fprintf(fp, "//----- END call Connection Box-X direction [%d][%d] module -----\n\n", x, y); + break; + case CHANY: + fprintf(fp, "//----- END call Connection Box-Y direction [%d][%d] module -----\n\n", x, y); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((1 == side_cnt)||(2 == side_cnt)); + + return; +} + +/* Call the sub-circuits for connection boxes */ +void dump_verilog_defined_connection_boxes(FILE* fp) { + int ix, iy; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* X - channels [1...nx][0..ny]*/ + for (iy = 0; iy < (ny + 1); iy++) { + for (ix = 1; ix < (nx + 1); ix++) { + dump_verilog_defined_one_connection_box(fp, cbx_info[ix][iy]); + } + } + /* Y - channels [1...ny][0..nx]*/ + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + dump_verilog_defined_one_connection_box(fp, cby_info[ix][iy]); + } + } + + return; +} + +/* Call the defined switch box sub-circuit + * TODO: This function is also copied from + * spice_routing.c : dump_verilog_routing_switch_box_subckt + */ +void dump_verilog_defined_one_switch_box(FILE* fp, + t_sb cur_sb_info) { + int ix, iy, side, itrack, x, y, inode; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(0 > cur_sb_info.x))&&(!(cur_sb_info.x > (nx + 1)))); + assert((!(0 > cur_sb_info.y))&&(!(cur_sb_info.y > (ny + 1)))); + + x = cur_sb_info.x; + y = cur_sb_info.y; + + /* Comment lines */ + fprintf(fp, "//----- BEGIN call module Switch blocks [%d][%d] -----\n", + cur_sb_info.x, cur_sb_info.y); + /* Print module*/ + fprintf(fp, "sb_%d__%d_ ", cur_sb_info.x, cur_sb_info.y); + fprintf(fp, "sb_%d__%d__0_ ", cur_sb_info.x, cur_sb_info.y); + fprintf(fp, "("); + + fprintf(fp, "\n"); + /* dump global ports */ + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + fprintf(fp, ",\n"); + } + + for (side = 0; side < cur_sb_info.num_sides; side++) { + determine_sb_port_coordinator(cur_sb_info, side, &ix, &iy); + + fprintf(fp, "//----- %s side channel ports-----\n", convert_side_index_to_string(side)); + for (itrack = 0; itrack < cur_sb_info.chan_width[side]; itrack++) { + switch (cur_sb_info.chan_rr_node_direction[side][itrack]) { + case OUT_PORT: + fprintf(fp, "%s_%d__%d__out_%d_, ", + convert_chan_type_to_string(cur_sb_info.chan_rr_node[side][itrack]->type), + ix, iy, itrack); + break; + case IN_PORT: + fprintf(fp, "%s_%d__%d__in_%d_, ", + convert_chan_type_to_string(cur_sb_info.chan_rr_node[side][itrack]->type), + ix, iy, itrack); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of sb[%d][%d] side[%d] track[%d]!\n", + __FILE__, __LINE__, x, y, side, itrack); + exit(1); + } + } + fprintf(fp, "\n"); + fprintf(fp, "//----- %s side inputs: CLB output pins -----\n", convert_side_index_to_string(side)); + /* Dump OPINs of adjacent CLBs */ + for (inode = 0; inode < cur_sb_info.num_opin_rr_nodes[side]; inode++) { + dump_verilog_grid_side_pin_with_given_index(fp, IPIN, + cur_sb_info.opin_rr_node[side][inode]->ptc_num, + cur_sb_info.opin_rr_node_grid_side[side][inode], + cur_sb_info.opin_rr_node[side][inode]->xlow, + cur_sb_info.opin_rr_node[side][inode]->ylow, + FALSE); /* Do not specify the direction of port */ + fprintf(fp, ","); + } + fprintf(fp, "\n"); + } + + /* Configuration ports */ + /* output of each configuration bit */ + /* Reserved sram ports */ + dump_verilog_reserved_sram_ports(fp, sram_verilog_orgz_info, + 0, cur_sb_info.num_reserved_conf_bits - 1, + VERILOG_PORT_CONKT); + /* Normal sram ports */ + if (0 < (cur_sb_info.num_reserved_conf_bits)) { + fprintf(fp, ",\n"); + } + dump_verilog_sram_ports(fp, sram_verilog_orgz_info, + cur_sb_info.conf_bits_lsb, + cur_sb_info.conf_bits_msb - 1, + VERILOG_PORT_CONKT); + + fprintf(fp, ");\n"); + + /* Comment lines */ + fprintf(fp, "//----- END call module Switch blocks [%d][%d] -----\n\n", x, y); + + /* Free */ + + return; +} + +void dump_verilog_defined_switch_boxes(FILE* fp) { + int ix, iy; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 0; iy < (ny + 1); iy++) { + dump_verilog_defined_one_switch_box(fp, sb_info[ix][iy]); + } + } + + return; +} + +/** Dump Standalone SRAMs + */ +void dump_verilog_configuration_circuits_standalone_srams(FILE* fp) { + int i; + /* Check */ + assert(SPICE_SRAM_STANDALONE == sram_verilog_orgz_type); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File handler!",__FILE__, __LINE__); + exit(1); + } + + /* Dump each SRAM */ + fprintf(fp, "//------ Standalone SRAMs -----\n"); + for (i = 0; i < sram_verilog_model->cnt; i++) { + fprintf(fp, "%s %s_%d (\n", + sram_verilog_model->name, sram_verilog_model->prefix, i); + /* Input and 2 outputs */ + fprintf(fp, "%s_in[%d] %s_out[%d] %s_outb[%d] ", + sram_verilog_model->prefix, i, + sram_verilog_model->prefix, i, + sram_verilog_model->prefix, i); + fprintf(fp, ");\n"); + } + fprintf(fp, "//------ END Standalone SRAMs -----\n"); + + return; +} + +/** Dump scan-chains + */ +void dump_verilog_configuration_circuits_scan_chains(FILE* fp) { + int i; + /* Check */ + assert(SPICE_SRAM_SCAN_CHAIN == sram_verilog_orgz_type); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!",__FILE__, __LINE__); + exit(1); + } + + /* Dump each Scan-chain FF */ + fprintf(fp, "//------ Scan-chain FFs -----\n"); + for (i = 0; i < sram_verilog_model->cnt; i++) { + /* Connect the head of current scff to the tail of previous scff*/ + if (0 < i) { + fprintf(fp, " "); + fprintf(fp, "assign "); + dump_verilog_sram_one_port(fp, sram_verilog_orgz_info, i, i, 0, VERILOG_PORT_CONKT); + fprintf(fp, " = "); + dump_verilog_sram_one_port(fp, sram_verilog_orgz_info, i - 1, i - 1, 1, VERILOG_PORT_CONKT); + fprintf(fp, ";\n"); + } + } + fprintf(fp, "//------ END Scan-chain FFs -----\n"); + + return; +} + +/* Dump a memory bank to configure all the Bit lines and Word lines */ +void dump_verilog_configuration_circuits_memory_bank(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info) { + int bl_decoder_size, wl_decoder_size; + int num_array_bl, num_array_wl; + t_spice_model* mem_model = NULL; + + /* Check */ + assert(SPICE_SRAM_MEMORY_BANK == cur_sram_orgz_info->type); + assert(NULL != cur_sram_orgz_info->mem_bank_info); + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!",__FILE__, __LINE__); + exit(1); + } + + determine_verilog_blwl_decoder_size(sram_verilog_orgz_info, + &num_array_bl, &num_array_wl, &bl_decoder_size, &wl_decoder_size); + /* Get memory model */ + get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); + assert(NULL != mem_model); + + /* Comment lines */ + fprintf(fp, "//----- BEGIN call decoders for memory bank controller -----\n"); + + /* Dump Decoders for Bit lines and Word lines */ + /* Two huge decoders + * TODO: divide to a number of small decoders ? + */ + /* Bit lines decoder */ + fprintf(fp, "bl_decoder%dto%d mem_bank_bl_decoder (", + bl_decoder_size, num_array_bl); + /* Prefix of BL & WL is fixed, in order to simplify grouping nets */ + fprintf(fp, "%s, %s[%d:0], ", + top_netlist_bl_enable_port_name, + top_netlist_addr_bl_port_name, bl_decoder_size - 1); + /* Port map depends on the memory technology */ + switch (mem_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + /* Data input port of BL decoder, only required by SRAM array */ + fprintf(fp, "%s, ", + top_netlist_bl_data_in_port_name); + break; + case SPICE_MODEL_DESIGN_RRAM: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization in Verilog Generator!\n", + __FILE__, __LINE__); + exit(1); + } + fprintf(fp, "%s[0:%d]", + top_netlist_array_bl_port_name, num_array_bl - 1); + fprintf(fp, ");\n"); + + /* Word lines decoder is the same for both technology */ + fprintf(fp, "wl_decoder%dto%d mem_bank_wl_decoder (", + wl_decoder_size, num_array_wl); + fprintf(fp, "%s, %s[%d:0], ", + top_netlist_wl_enable_port_name, + top_netlist_addr_wl_port_name, wl_decoder_size - 1); + fprintf(fp, "%s[0:%d]", + top_netlist_array_wl_port_name, num_array_wl - 1); + fprintf(fp, ");\n"); + + /* Comment lines */ + fprintf(fp, "//----- END call decoders for memory bank controller -----\n\n"); + + return; +} + +/* Dump the configuration circuits in verilog according to user-specification + * Supported styles of configuration circuits: + * 1. Scan-chains + * 2. Memory banks + * 3. Standalone SRAMs + */ +void dump_verilog_configuration_circuits(FILE* fp) { + switch(sram_verilog_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + dump_verilog_configuration_circuits_standalone_srams(fp); + break; + case SPICE_SRAM_SCAN_CHAIN: + dump_verilog_configuration_circuits_scan_chains(fp); + break; + case SPICE_SRAM_MEMORY_BANK: + dump_verilog_configuration_circuits_memory_bank(fp, sram_verilog_orgz_info); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization in Verilog Generator!\n", + __FILE__, __LINE__); + exit(1); + } + return; +} + +/* Dump all the global ports that are stored in the linked list */ +static +void dump_verilog_top_testbench_global_ports(FILE* fp, t_llist* head, + enum e_dump_verilog_port_type dump_port_type) { + t_llist* temp = head; + t_spice_model_port* cur_global_port = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + } + + fprintf(fp, "//----- BEGIN Global ports -----\n"); + while(NULL != temp) { + cur_global_port = (t_spice_model_port*)(temp->dptr); + dump_verilog_generic_port(fp, dump_port_type, + cur_global_port->prefix, 0, cur_global_port->size - 1); + fprintf(fp, ";\n"); + /* Go to the next */ + temp = temp->next; + } + fprintf(fp, "//----- END Global ports -----\n"); + + return; +} + +/* Connect a global port to a voltage stimuli */ +static +void dump_verilog_top_testbench_wire_one_global_port_stimuli(FILE* fp, t_spice_model_port* cur_global_port, + char* voltage_stimuli_port_name) { + int ipin; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + assert(NULL != cur_global_port); + + for (ipin = 0; ipin < cur_global_port->size; ipin++) { + fprintf(fp, "assign %s[%d] = ", + cur_global_port->prefix, ipin); + assert((0 == cur_global_port->default_val)||(1 == cur_global_port->default_val)); + if (1 == cur_global_port->default_val) { + fprintf(fp, "~"); + } + fprintf(fp, "%s;\n", + voltage_stimuli_port_name); + } + + return; +} + +/* Print stimuli for global ports in top-level testbench */ +static +void dump_verilog_top_testbench_global_ports_stimuli(FILE* fp, t_llist* head) { + t_llist* temp = head; + t_spice_model_port* cur_global_port = NULL; + int ipin; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + fprintf(fp, "//----- Connecting Global ports -----\n"); + while(NULL != temp) { + cur_global_port = (t_spice_model_port*)(temp->dptr); + /* Make sure this is a global port */ + assert(TRUE == cur_global_port->is_global); + /* If this is a clock signal, connect to op_clock signal */ + if (SPICE_MODEL_PORT_CLOCK == cur_global_port->type) { + /* Special for programming clock */ + if (TRUE == cur_global_port->is_prog) { + dump_verilog_top_testbench_wire_one_global_port_stimuli(fp, cur_global_port, top_tb_prog_clock_port_name); + } else { + assert(FALSE == cur_global_port->is_prog); + dump_verilog_top_testbench_wire_one_global_port_stimuli(fp, cur_global_port, top_tb_op_clock_port_name); + } + /* If this is a config_enable signal, connect to config_done signal */ + } else if (TRUE == cur_global_port->is_config_enable) { + dump_verilog_top_testbench_wire_one_global_port_stimuli(fp, cur_global_port, top_tb_prog_clock_port_name); + /* If this is a set/reset signal, connect to global reset and set signals */ + } else if (TRUE == cur_global_port->is_reset) { + /* Special for programming reset */ + if (TRUE == cur_global_port->is_prog) { + dump_verilog_top_testbench_wire_one_global_port_stimuli(fp, cur_global_port, top_tb_prog_reset_port_name); + } else { + assert(FALSE == cur_global_port->is_prog); + dump_verilog_top_testbench_wire_one_global_port_stimuli(fp, cur_global_port, top_tb_reset_port_name); + } + /* If this is a set/reset signal, connect to global reset and set signals */ + } else if (TRUE == cur_global_port->is_set) { + /* Special for programming reset */ + if (TRUE == cur_global_port->is_prog) { + dump_verilog_top_testbench_wire_one_global_port_stimuli(fp, cur_global_port, top_tb_prog_set_port_name); + } else { + assert(FALSE == cur_global_port->is_prog); + dump_verilog_top_testbench_wire_one_global_port_stimuli(fp, cur_global_port, top_tb_set_port_name); + } + } else { + /* Other global signals stuck at the default values */ + for (ipin = 0; ipin < cur_global_port->size; ipin++) { + fprintf(fp, "assign %s[%d] = 1'b%d;\n", + cur_global_port->prefix, ipin, cur_global_port->default_val); + } + } + /* Go to the next */ + temp = temp->next; + } + fprintf(fp, "//----- End Connecting Global ports -----\n"); + + return; +} + +static +void dump_verilog_top_testbench_ports(FILE* fp, + char* circuit_name) { + int num_array_bl, num_array_wl; + int bl_decoder_size, wl_decoder_size; + int iblock, iopad_idx; + t_spice_model* mem_model = NULL; + char* port_name = NULL; + + get_sram_orgz_info_mem_model(sram_verilog_orgz_info, &mem_model); + + fprintf(fp, "module %s_top_tb;\n", circuit_name); + /* Local wires */ + /* 1. reset, set, clock signals */ + /* 2. iopad signals */ + + /* Connect to defined signals */ + /* set and reset signals */ + fprintf(fp, "\n"); + dump_verilog_top_testbench_global_ports(fp, global_ports_head, VERILOG_PORT_WIRE); + fprintf(fp, "\n"); + + /* TODO: dump each global signal as reg here */ + + /* Inputs and outputs of I/O pads */ + /* Inout Pads */ + assert(NULL != iopad_verilog_model); + if ((NULL == iopad_verilog_model) + ||(iopad_verilog_model->cnt > 0)) { + /* Malloc and assign port_name */ + port_name = (char*)my_malloc(sizeof(char)*(strlen(gio_inout_prefix) + strlen(iopad_verilog_model->prefix) + 1)); + sprintf(port_name, "%s%s", gio_inout_prefix, iopad_verilog_model->prefix); + /* Dump a wired port */ + dump_verilog_generic_port(fp, VERILOG_PORT_WIRE, + port_name, iopad_verilog_model->cnt - 1, 0); + fprintf(fp, "; //--- FPGA inouts \n"); + /* Free port_name */ + my_free(port_name); + /* Malloc and assign port_name */ + port_name = (char*)my_malloc(sizeof(char)*(strlen(gio_inout_prefix) + strlen(iopad_verilog_model->prefix) + strlen(top_tb_inout_reg_postfix) + 1)); + sprintf(port_name, "%s%s%s", gio_inout_prefix, iopad_verilog_model->prefix, top_tb_inout_reg_postfix); + /* Dump a wired port */ + dump_verilog_generic_port(fp, VERILOG_PORT_REG, + port_name, iopad_verilog_model->cnt - 1, 0); + fprintf(fp, "; //--- reg for FPGA inouts \n"); + /* Free port_name */ + my_free(port_name); + } + + /* Add a signal to identify the configuration phase is finished */ + fprintf(fp, "reg [0:0] %s;\n", top_tb_config_done_port_name); + /* Programming clock */ + fprintf(fp, "wire [0:0] %s;\n", top_tb_prog_clock_port_name); + fprintf(fp, "reg [0:0] %s%s;\n", top_tb_prog_clock_port_name, top_tb_clock_reg_postfix); + /* Operation clock */ + fprintf(fp, "wire [0:0] %s;\n", top_tb_op_clock_port_name); + fprintf(fp, "reg [0:0] %s%s;\n", top_tb_op_clock_port_name, top_tb_clock_reg_postfix); + /* Programming set and reset */ + fprintf(fp, "reg [0:0] %s;\n", top_tb_prog_reset_port_name); + fprintf(fp, "reg [0:0] %s;\n", top_tb_prog_set_port_name); + /* Global set and reset */ + fprintf(fp, "reg [0:0] %s;\n", top_tb_reset_port_name); + fprintf(fp, "reg [0:0] %s;\n", top_tb_set_port_name); + /* Generate stimuli for global ports or connect them to existed signals */ + dump_verilog_top_testbench_global_ports_stimuli(fp, global_ports_head); + + /* Configuration ports depend on the organization of SRAMs */ + switch(sram_verilog_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + dump_verilog_generic_port(fp, VERILOG_PORT_WIRE, + sram_verilog_model->prefix, sram_verilog_model->cnt - 1, 0); + fprintf(fp, "; //---- SRAM outputs \n"); + break; + case SPICE_SRAM_SCAN_CHAIN: + /* We put the head of scan-chains here + */ + dump_verilog_generic_port(fp, VERILOG_PORT_REG, + top_netlist_scan_chain_head_prefix, 0, 0); + fprintf(fp, "; //---- Scan-chain head \n"); + break; + case SPICE_SRAM_MEMORY_BANK: + /* Get the number of array BLs/WLs, decoder sizes */ + determine_verilog_blwl_decoder_size(sram_verilog_orgz_info, + &num_array_bl, &num_array_wl, &bl_decoder_size, &wl_decoder_size); + + fprintf(fp, " wire [0:0] %s;\n", + top_netlist_bl_enable_port_name + ); + fprintf(fp, " wire [0:0] %s;\n", + top_netlist_wl_enable_port_name + ); + /* Wire en_bl, en_wl to prog_clock */ + fprintf(fp, "assign %s[0:0] = %s[0:0];\n", + top_netlist_bl_enable_port_name, + top_tb_prog_clock_port_name); + fprintf(fp, "assign %s [0:0]= %s[0:0];\n", + top_netlist_wl_enable_port_name, + top_tb_prog_clock_port_name); + dump_verilog_generic_port(fp, VERILOG_PORT_REG, + top_netlist_addr_bl_port_name, bl_decoder_size - 1, 0); + fprintf(fp, "; //--- Address of bit lines \n"); + dump_verilog_generic_port(fp, VERILOG_PORT_REG, + top_netlist_addr_wl_port_name, wl_decoder_size - 1, 0); + fprintf(fp, "; //--- Address of word lines \n"); + /* data_in is only require by BL decoder of SRAM array + * As for RRAM array, the data_in signal will not be used + */ + if (SPICE_MODEL_DESIGN_CMOS == mem_model->design_tech) { + fprintf(fp, " reg [0:0] %s; // --- Data_in signal for BL decoder, only required by SRAM array \n", + top_netlist_bl_data_in_port_name); + } + /* I add all the Bit lines and Word lines here just for testbench usage + fprintf(fp, " input wire [%d:0] %s_out; //--- Bit lines \n", + sram_verilog_model->cnt - 1, sram_verilog_model->prefix); + fprintf(fp, " input wire [%d:0] %s_outb; //--- Word lines \n", + sram_verilog_model->cnt - 1, sram_verilog_model->prefix); + */ + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization in Verilog Generator!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Add signals from blif benchmark and short-wire them to FPGA I/O PADs + * This brings convenience to checking functionality + */ + fprintf(fp, "//-----Link Blif Benchmark inputs to FPGA IOPADs -----\n"); + for (iblock = 0; iblock < num_logical_blocks; iblock++) { + /* General INOUT*/ + if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) { + iopad_idx = logical_block[iblock].mapped_spice_model_index; + /* Make sure We find the correct logical block !*/ + assert((VPACK_INPAD == logical_block[iblock].type)||(VPACK_OUTPAD == logical_block[iblock].type)); + fprintf(fp, "//----- Blif Benchmark inout %s is mapped to FPGA IOPAD %s[%d] -----\n", + logical_block[iblock].name, gio_inout_prefix, iopad_idx); + fprintf(fp, "wire %s_%s_%d_;\n", + logical_block[iblock].name, gio_inout_prefix, iopad_idx); + fprintf(fp, "assign %s_%s_%d_ = %s%s[%d];\n", + logical_block[iblock].name, gio_inout_prefix, iopad_idx, + gio_inout_prefix, iopad_verilog_model->prefix, iopad_idx); + } + } + + return; +} + +static +void dump_verilog_top_testbench_call_top_module(FILE* fp, + char* circuit_name) { + int iblock, iopad_idx; + + /* Include defined top-level module */ + fprintf(fp, "//----- Device Under Test (DUT) ----\n"); + fprintf(fp, "//------Call defined Top-level Verilog Module -----\n"); + fprintf(fp, "%s_top U0 (\n", circuit_name); + + dump_verilog_top_module_ports(fp, VERILOG_PORT_CONKT); + + fprintf(fp, ");\n"); + return; +} + +/* Find the number of configuration clock cycles for a top-level testbench + * A valid configuration clock cycle is allocated for an element with + * (1) SRAM_val=1; + * (2) BL = 1 && WL = 1; + * (3) BL = 1 && WL = 0 with a paired conf_bit; + */ +int dump_verilog_top_testbench_find_num_config_clock_cycles(t_llist* head) { + int cnt = 0; + t_llist* temp = head; + t_conf_bit_info* temp_conf_bit_info = NULL; + + while (NULL != temp) { + /* Fetch the conf_bit_info */ + temp_conf_bit_info = (t_conf_bit_info*)(temp->dptr); + /* Check if conf_bit_info needs a clock cycle*/ + switch (sram_verilog_orgz_type) { + case SPICE_SRAM_STANDALONE: + case SPICE_SRAM_SCAN_CHAIN: + cnt++; + temp_conf_bit_info->index_in_top_tb = cnt; + break; + case SPICE_SRAM_MEMORY_BANK: + cnt++; + temp_conf_bit_info->index_in_top_tb = cnt; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization in Verilog Generator!\n", + __FILE__, __LINE__); + exit(1); + } + /* Go to the next */ + temp = temp->next; + } + + return cnt; +} + + +/* Dump configuration bits of a SRAM memory bank + * The efficient sharing BLs/WLs force configuration to be done WL by WL + * (We always assume that Word Lines are the write/read enable signal for SRAMs) + * All the SRAMs controlled by the same WL will be configuration during one programming cycle + * by assign different BL values for each of them. + */ +static +void dump_verilog_top_testbench_sram_memory_bank_conf_bits_serial(FILE* fp, + t_llist* cur_conf_bit) { + int num_array_bl, num_array_wl; + int bl_decoder_size, wl_decoder_size; + int** array_bit = NULL; + t_conf_bit_info*** array_conf_bit_info = NULL; + + int ibl, iwl, cur_wl, cur_bl; + char* wl_addr = NULL; + char* bl_addr = NULL; + + t_llist* temp = cur_conf_bit; + t_conf_bit_info* cur_conf_bit_info = NULL; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!",__FILE__, __LINE__); + exit(1); + } + + /* Dump one configuring operation on BL and WL addresses */ + determine_verilog_blwl_decoder_size(sram_verilog_orgz_info, + &num_array_bl, &num_array_wl, &bl_decoder_size, &wl_decoder_size); + + /* We will allocate the configuration bits to be written for each programming cycle */ + array_bit = (int**)my_malloc(sizeof(int*)*num_array_wl); + array_conf_bit_info = (t_conf_bit_info***)my_malloc(sizeof(t_conf_bit_info**)*num_array_wl); + /* Initialization */ + for (iwl = 0; iwl < num_array_wl; iwl++) { + array_bit[iwl] = (int*)my_malloc(sizeof(int)*num_array_bl); + array_conf_bit_info[iwl] = (t_conf_bit_info**)my_malloc(sizeof(t_conf_bit_info*)*num_array_bl); + for (ibl = 0; ibl < num_array_bl; ibl++) { + array_bit[iwl][ibl] = 0; + array_conf_bit_info[iwl][ibl] = NULL; + } + } + + /* Classify each configuration bit info to its assciated bl/wl codes + * The bl_addr and wl_addr recorded in the list is the absoluate address, + */ + while (NULL != temp) { + cur_conf_bit_info = (t_conf_bit_info*)(temp->dptr); + /* Memory bank requires the address to be given to the decoder*/ + assert( cur_conf_bit_info->bl->addr == cur_conf_bit_info->wl->addr ); + cur_wl = cur_conf_bit_info->bl->addr / num_array_bl; + cur_bl = cur_conf_bit_info->bl->addr % num_array_bl; + /* Update the SRAM bit array */ + array_bit[cur_wl][cur_bl] = cur_conf_bit_info->bl->val; + array_conf_bit_info[cur_wl][cur_bl] = cur_conf_bit_info; + /* Check if SRAM bit is valid */ + assert( (0 == array_bit[cur_wl][cur_bl]) || (1 == array_bit[cur_wl][cur_bl]) ); + /* Go to next */ + temp = temp->next; + } + + /* Dump decoder input for each programming cycle */ + for (iwl = 0; iwl < num_array_wl; iwl++) { + for (ibl = 0; ibl < num_array_bl; ibl++) { + /* Bypass configuration bit not available */ + if ( NULL == array_conf_bit_info[iwl][ibl]) { + continue; + } + /* Check */ + assert(( 1 == array_bit[iwl][ibl] )||( 0 == array_bit[iwl][ibl] )); + assert( NULL != array_conf_bit_info[iwl][ibl]); + /* If this WL is selected , we decode its index to address */ + bl_addr = (char*)my_calloc(bl_decoder_size + 1, sizeof(char)); + /* If this WL is selected , we decode its index to address */ + encode_decoder_addr(ibl, bl_decoder_size, bl_addr); + /* Word line address */ + wl_addr = (char*)my_calloc(wl_decoder_size + 1, sizeof(char)); + encode_decoder_addr(iwl, wl_decoder_size, wl_addr); + /* Get corresponding conf_bit */ + cur_conf_bit_info = array_conf_bit_info[iwl][ibl]; + /* One operation per clock cycle */ + /* Information about this configuration bit */ + fprintf(fp, " //--- Configuration bit No.: %d \n", cur_conf_bit_info->index); + fprintf(fp, " //--- Bit Line Address: %d, \n", cur_conf_bit_info->bl->addr); + fprintf(fp, " //--- Word Line Address: %d \n ", cur_conf_bit_info->wl->addr); + fprintf(fp, " //--- Bit Line index: %d, \n", ibl); + fprintf(fp, " //--- Word Line index: %d \n ", iwl); + fprintf(fp, " //--- Bit Line Value: %d, \n", cur_conf_bit_info->bl->val); + fprintf(fp, " //--- Word Line Value: %d \n ", cur_conf_bit_info->wl->val); + fprintf(fp, " //--- SPICE model name: %s \n", cur_conf_bit_info->parent_spice_model->name); + fprintf(fp, " //--- SPICE model index: %d \n", cur_conf_bit_info->parent_spice_model_index); + fprintf(fp, " prog_cycle_blwl(%d'b%s, %d'b%s, 1'b%d); //--- (BL_addr_code, WL_addr_code, bl_data_in) \n", + bl_decoder_size, bl_addr, wl_decoder_size, wl_addr, array_bit[iwl][ibl]); + fprintf(fp, "\n"); + } + } + + /* Free */ + for (iwl = 0; iwl < num_array_wl; iwl++) { + my_free(array_bit[iwl]); + my_free(array_conf_bit_info[iwl]); + } + my_free(array_bit); + my_free(array_conf_bit_info); + + return; +} + +static +void dump_verilog_top_testbench_rram_memory_bank_conf_bits_serial(FILE* fp, + t_llist* cur_conf_bit) { + int num_bl, num_wl; + int bl_decoder_size, wl_decoder_size; + char* wl_addr = NULL; + char* bl_addr = NULL; + + t_llist* temp = cur_conf_bit; + t_conf_bit_info* cur_conf_bit_info = NULL; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!",__FILE__, __LINE__); + exit(1); + } + + + /* Dump one configuring operation on BL and WL addresses */ + determine_verilog_blwl_decoder_size(sram_verilog_orgz_info, + &num_bl, &num_wl, &bl_decoder_size, &wl_decoder_size); + + while (NULL != temp) { + cur_conf_bit_info = (t_conf_bit_info*)(temp->dptr); + /* For memory bank, we do not care the sequence. + * To be easy to understand, we go from the first to the last + * IMPORTANT: sequence seems to be critical. + * Reversing the sequence leading to functional incorrect. + */ + /* Memory bank requires the address to be given to the decoder*/ + /* Decode address to BLs and WLs*/ + /* Encode addresses */ + /* Bit line address */ + /* If this WL is selected , we decode its index to address */ + bl_addr = (char*)my_calloc(bl_decoder_size + 1, sizeof(char)); + /* If this WL is selected , we decode its index to address */ + assert(NULL != cur_conf_bit_info->bl); + encode_decoder_addr(cur_conf_bit_info->bl->addr, bl_decoder_size, bl_addr); + /* Word line address */ + wl_addr = (char*)my_calloc(wl_decoder_size + 1, sizeof(char)); + encode_decoder_addr(cur_conf_bit_info->wl->addr, wl_decoder_size, wl_addr); + assert(NULL != cur_conf_bit_info->wl); + /* One operation per clock cycle */ + /* Information about this configuration bit */ + fprintf(fp, " //--- Configuration bit No.: %d \n", cur_conf_bit_info->index); + fprintf(fp, " //--- Bit Line: %d, \n", cur_conf_bit_info->bl->val); + fprintf(fp, " //--- Word Line: %d \n ", cur_conf_bit_info->wl->val); + fprintf(fp, " //--- SPICE model name: %s \n", cur_conf_bit_info->parent_spice_model->name); + fprintf(fp, " //--- SPICE model index: %d \n", cur_conf_bit_info->parent_spice_model_index); + fprintf(fp, " prog_cycle_blwl(%d'b%s, %d'b%s); //--- (BL_addr_code, WL_addr_code) \n", + bl_decoder_size, bl_addr, wl_decoder_size, wl_addr); + fprintf(fp, "\n"); + /* Free */ + my_free(wl_addr); + my_free(bl_addr); + /* Go to next */ + temp = temp->next; + } + + return; +} + +static +void dump_verilog_top_testbench_memory_bank_conf_bits_serial(FILE* fp, + t_llist* cur_conf_bit) { + t_spice_model* mem_model = NULL; + + /* Depending on the memory technology*/ + get_sram_orgz_info_mem_model(sram_verilog_orgz_info, &mem_model); + assert(NULL != mem_model); + + /* Check */ + assert(SPICE_SRAM_MEMORY_BANK == sram_verilog_orgz_info->type); + + /* fork on the memory technology */ + switch (mem_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + dump_verilog_top_testbench_sram_memory_bank_conf_bits_serial(fp, cur_conf_bit); + break; + case SPICE_MODEL_DESIGN_RRAM: + dump_verilog_top_testbench_rram_memory_bank_conf_bits_serial(fp, cur_conf_bit); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology for memory in Verilog Generator!\n", + __FILE__, __LINE__); + exit(1); + } + + return; +} + +/* For scan chain, the last bit should go first!*/ +/* The sequence of linked list is already reversed, we just need to output each bit */ +static +void dump_verilog_top_testbench_scan_chain_conf_bits_serial(FILE* fp, + t_llist* cur_conf_bit) { + t_llist* temp = cur_conf_bit; + t_conf_bit_info* cur_conf_bit_info = NULL; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!",__FILE__, __LINE__); + exit(1); + } + + /* Configuration phase: configure each SRAM or BL/WL */ + fprintf(fp, "//----- Configuration phase -----\n"); + fprintf(fp, "initial\n"); + fprintf(fp, " begin //--- Scan_chain default input\n"); + /* Initial value should be the first configuration bits + * In the rest of programming cycles, + * configuration bits are fed at the falling edge of programming clock. + */ + /* We do not care the value of scan_chain head during the first programming cycle + * It is reset anyway + */ + fprintf(fp, " "); + dump_verilog_generic_port(fp, VERILOG_PORT_CONKT, + top_netlist_scan_chain_head_prefix, 0, 0); + fprintf(fp, " = 1'b%d;\n", + 0 ); + fprintf(fp, "\n"); + /* Check we have a valid first bit */ + while (NULL != temp) { + cur_conf_bit_info = (t_conf_bit_info*)(temp->dptr); + /* Scan-chain only loads the SRAM values */ + fprintf(fp, "//---- Configuration bit No.: %d \n ", cur_conf_bit_info->index); + fprintf(fp, "//---- SRAM value: %d \n", cur_conf_bit_info->sram_bit->val); + fprintf(fp, "//---- SPICE model name: %s \n ", cur_conf_bit_info->parent_spice_model->name); + fprintf(fp, "//---- SPICE model index: %d \n", cur_conf_bit_info->parent_spice_model_index); + fprintf(fp, "\n"); + /* First bit is special */ + fprintf(fp, " prog_cycle_scan_chain(1'b%d); //--- (Scan_chain bits) \n", + cur_conf_bit_info->sram_bit->val); + fprintf(fp, "\n"); + /* Go to next */ + temp = temp->next; + } + fprintf(fp, " end\n"); + fprintf(fp, "//----- END of Configuration phase -----\n"); + + return; +} + +/* dump configuration bits which are stored in the linked list + * USE while LOOP !!! Recursive method causes memory corruptions! + * We start dump configuration bit from the tail of the linked list + * until the head of the linked list + */ +static +void dump_verilog_top_testbench_one_conf_bit_serial(FILE* fp, + t_llist* cur_conf_bit) { + + /* We already touch the tail, start dump */ + switch (sram_verilog_orgz_type) { + case SPICE_SRAM_STANDALONE: + case SPICE_SRAM_SCAN_CHAIN: + dump_verilog_top_testbench_scan_chain_conf_bits_serial(fp, cur_conf_bit); + break; + case SPICE_SRAM_MEMORY_BANK: + /* Should work differently depending on memory technology */ + dump_verilog_top_testbench_memory_bank_conf_bits_serial(fp, cur_conf_bit); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization in Verilog Generator!\n", + __FILE__, __LINE__); + exit(1); + } + + return; +} + +static +void dump_verilog_top_testbench_conf_bits_serial(FILE* fp, + t_llist* head) { + int num_bl, num_wl; + int bl_decoder_size, wl_decoder_size; + t_llist* new_head = head; + + switch (sram_verilog_orgz_type) { + case SPICE_SRAM_STANDALONE: + case SPICE_SRAM_SCAN_CHAIN: + /* For scan chain, the last bit should go first!*/ + /* We do not need to reverse the linked list HERE !!! + * Because, it is already arranged in the seqence of MSB to LSB + * Note that the first element in the linked list is the last bit now! + */ + /* For each element in linked list, generate a voltage stimuli */ + dump_verilog_top_testbench_one_conf_bit_serial(fp, head); + break; + case SPICE_SRAM_MEMORY_BANK: + /* Configuration bits are loaded differently depending on memory technology */ + determine_verilog_blwl_decoder_size(sram_verilog_orgz_info, + &num_bl, &num_wl, &bl_decoder_size, &wl_decoder_size); + /* Configuration phase: configure each SRAM or BL/WL */ + fprintf(fp, "//----- Configuration phase -----\n"); + fprintf(fp, "initial\n"); + fprintf(fp, " begin //--- BL_WL_ADDR\n"); + fprintf(fp, " addr_bl = {%d {1'b0}};\n", bl_decoder_size); + fprintf(fp, " addr_wl = {%d {1'b0}};\n", wl_decoder_size); + /* For each element in linked list, generate a voltage stimuli */ + /* Reverse the linked list first !!! */ + new_head = reverse_llist(new_head); + dump_verilog_top_testbench_one_conf_bit_serial(fp, new_head); + /* Recover the sequence of linked list (reverse again) !!! */ + new_head = reverse_llist(new_head); + /* Check */ + assert(head == new_head); + fprintf(fp, " end\n"); + fprintf(fp, "//----- END of Configuration phase -----\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization in Verilog Generator!\n", + __FILE__, __LINE__); + exit(1); + } + + return; +} + +/* Print tasks, which is very useful in generating stimuli for each clock cycle + * For memory-bank manipulations only + */ +static +void dump_verilog_top_testbench_stimuli_serial_version_tasks_memory_bank(FILE* fp) { + int num_array_bl, num_array_wl; + int bl_decoder_size, wl_decoder_size; + t_spice_model* mem_model = NULL; + + /* Check */ + assert (sram_verilog_orgz_info->type == SPICE_SRAM_MEMORY_BANK); + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Find the number of array BLs/WLs and decoder sizes */ + determine_verilog_blwl_decoder_size(sram_verilog_orgz_info, + &num_array_bl, &num_array_wl, &bl_decoder_size, &wl_decoder_size); + + /* Depending on the memory technology*/ + get_sram_orgz_info_mem_model(sram_verilog_orgz_info, &mem_model); + assert(NULL != mem_model); + + /* Depend on the memory technology */ + switch (mem_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + /* Declare two tasks: + * 1. assign BL/WL IO pads values during a programming clock cycle + * 2. assign BL/WL IO pads values during a operating clock cycle + */ + fprintf(fp, "\n"); + fprintf(fp, "//----- Task 1: input values during a programming clock cycle -----\n"); + fprintf(fp, "task prog_cycle_blwl;\n"); + fprintf(fp, " input [%d:0] bl_addr_val;\n", bl_decoder_size - 1); + fprintf(fp, " input [%d:0] wl_addr_val;\n", wl_decoder_size - 1); + fprintf(fp, " input [0:0] bl_data_in_val;\n"); + fprintf(fp, " begin\n"); + fprintf(fp, " @(posedge %s);\n", top_tb_prog_clock_port_name); + /* + fprintf(fp, " $display($time, \"Programming cycle: load BL address with \%h, load WL address with \%h\",\n"); + fprintf(fp, " bl_addr_val, wl_addr_val);\n"); + */ + fprintf(fp, " %s = bl_addr_val;\n", top_netlist_addr_bl_port_name); + fprintf(fp, " %s = wl_addr_val;\n", top_netlist_addr_wl_port_name); + fprintf(fp, " %s = bl_data_in_val;\n", top_netlist_bl_data_in_port_name); + fprintf(fp, " end\n"); + fprintf(fp, "endtask //---prog_cycle_stimuli\n"); + fprintf(fp, "\n"); + fprintf(fp, "//----- Task 2: input values during a operating clock cycle -----\n"); + fprintf(fp, "task op_cycle_blwl;\n"); + fprintf(fp, " input [%d:0] bl_addr_val;\n", bl_decoder_size - 1); + fprintf(fp, " input [%d:0] wl_addr_val;\n", wl_decoder_size - 1); + fprintf(fp, " input [0:0] bl_data_in_val;\n"); + fprintf(fp, " begin\n"); + fprintf(fp, " @(posedge %s);\n", top_tb_op_clock_port_name); + /* + fprintf(fp, " $display($time, \"Operating cycle: load BL address with \%h, load WL address with \%h\",\n"); + fprintf(fp, " bl_addr_val, wl_addr_val);\n"); + */ + fprintf(fp, " %s = bl_addr_val;\n", top_netlist_addr_bl_port_name); + fprintf(fp, " %s = wl_addr_val;\n", top_netlist_addr_wl_port_name); + fprintf(fp, " %s = bl_data_in_val;\n", top_netlist_bl_data_in_port_name); + fprintf(fp, " end\n"); + fprintf(fp, "endtask //---op_cycle_stimuli\n"); + fprintf(fp, "\n"); + break; + case SPICE_MODEL_DESIGN_RRAM: + /* Declare two tasks: + * 1. assign BL/WL IO pads values during a programming clock cycle + * 2. assign BL/WL IO pads values during a operating clock cycle + */ + fprintf(fp, "\n"); + fprintf(fp, "//----- Task 1: input values during a programming clock cycle -----\n"); + fprintf(fp, "task prog_cycle_blwl;\n"); + fprintf(fp, " input [%d:0] bl_addr_val;\n", bl_decoder_size - 1); + fprintf(fp, " input [%d:0] wl_addr_val;\n", wl_decoder_size - 1); + fprintf(fp, " begin\n"); + fprintf(fp, " @(posedge %s);\n", top_tb_prog_clock_port_name); + /* + fprintf(fp, " $display($time, \"Programming cycle: load BL address with \%h, load WL address with \%h\",\n"); + fprintf(fp, " bl_addr_val, wl_addr_val);\n"); + */ + fprintf(fp, " %s = bl_addr_val;\n", top_netlist_addr_bl_port_name); + fprintf(fp, " %s = wl_addr_val;\n", top_netlist_addr_wl_port_name); + fprintf(fp, " end\n"); + fprintf(fp, "endtask //---prog_cycle_stimuli\n"); + fprintf(fp, "\n"); + fprintf(fp, "//----- Task 2: input values during a operating clock cycle -----\n"); + fprintf(fp, "task op_cycle_blwl;\n"); + fprintf(fp, " input [%d:0] bl_addr_val;\n", bl_decoder_size - 1); + fprintf(fp, " input [%d:0] wl_addr_val;\n", wl_decoder_size - 1); + fprintf(fp, " begin\n"); + fprintf(fp, " @(posedge %s);\n", top_tb_op_clock_port_name); + /* + fprintf(fp, " $display($time, \"Operating cycle: load BL address with \%h, load WL address with \%h\",\n"); + fprintf(fp, " bl_addr_val, wl_addr_val);\n"); + */ + fprintf(fp, " %s = bl_addr_val;\n", top_netlist_addr_bl_port_name); + fprintf(fp, " %s = wl_addr_val;\n", top_netlist_addr_wl_port_name); + fprintf(fp, " end\n"); + fprintf(fp, "endtask //---op_cycle_stimuli\n"); + fprintf(fp, "\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization in Verilog Generator!\n", + __FILE__, __LINE__); + exit(1); + } + + return; +} + +/* Print tasks, which is very useful in generating stimuli for each clock cycle + * For scan-chain manipulation: + * During each programming cycle, we feed the input of scan chain with a memory bit + */ +static +void dump_verilog_top_testbench_stimuli_serial_version_tasks_scan_chain(FILE* fp) { + + /* Check */ + assert ( SPICE_SRAM_SCAN_CHAIN == sram_verilog_orgz_info->type); + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Feed the scan-chain input at each falling edge of programming clock + * It aims at avoid racing the programming clock (scan-chain data changes at the rising edge). + */ + fprintf(fp, "\n"); + fprintf(fp, "//----- Task: input values during a programming clock cycle -----\n"); + fprintf(fp, "task prog_cycle_scan_chain;\n"); + fprintf(fp, " input %s_val;\n", + top_netlist_scan_chain_head_prefix); + fprintf(fp, " begin\n"); + fprintf(fp, " @(negedge %s);\n", top_tb_prog_clock_port_name); + fprintf(fp, " "); + dump_verilog_generic_port(fp, VERILOG_PORT_CONKT, + top_netlist_scan_chain_head_prefix, 0, 0); + fprintf(fp, " = %s_val;\n", + top_netlist_scan_chain_head_prefix); + fprintf(fp, " end\n"); + fprintf(fp, "endtask //---prog_cycle_stimuli\n"); + fprintf(fp, "\n"); + + return; +} + +/* Print tasks, which is very useful in generating stimuli for each clock cycle */ +static +void dump_verilog_top_testbench_stimuli_serial_version_tasks(FILE* fp) { + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + switch (sram_verilog_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + break; + case SPICE_SRAM_SCAN_CHAIN: + dump_verilog_top_testbench_stimuli_serial_version_tasks_scan_chain(fp); + break; + case SPICE_SRAM_MEMORY_BANK: + dump_verilog_top_testbench_stimuli_serial_version_tasks_memory_bank(fp); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization in Verilog Generator!\n", + __FILE__, __LINE__); + exit(1); + } + + return; +} + + +/* Print Stimulations for top-level netlist + * Test a complete configuration phase: + * configuration bits are programming in serial (one by one) + * Task list: + * 1. For clock signal, we should create voltage waveforms for two types of clock signals: + * a. operation clock + * b. programming clock + * 2. For Set/Reset, TODO: should we reset the chip after programming phase ends and before operation phase starts + * 3. For input/output clb nets (mapped to I/O grids), we should create voltage waveforms only after programming phase + */ +static +void dump_verilog_top_testbench_stimuli_serial_version(FILE* fp, + int num_clock, + t_spice spice) { + int inet, iblock, iopad_idx; + int found_mapped_inpad = 0; + int num_config_clock_cycles = 0; + float prog_clock_period = (1./spice.spice_params.stimulate_params.prog_clock_freq); + float op_clock_period = (1./spice.spice_params.stimulate_params.op_clock_freq); + + /* Find Input Pad Spice model */ + t_spice_net_info* cur_spice_net_info = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Dump tasks */ + dump_verilog_top_testbench_stimuli_serial_version_tasks(fp); + + /* Estimate the number of configuration clock cycles + * by traversing the linked-list and count the number of SRAM=1 or BL=1&WL=1 in it. + * We plus 1 additional config clock cycle here because we need to reset everything during the first clock cycle + */ + num_config_clock_cycles = 1 + dump_verilog_top_testbench_find_num_config_clock_cycles(sram_verilog_orgz_info->conf_bit_head); + fprintf(fp, "//----- Number of clock cycles in configuration phase: %d -----\n", + num_config_clock_cycles); + + /* config_done signal: indicate when configuration is finished */ + fprintf(fp, "//----- %s ----\n", top_tb_config_done_port_name); + fprintf(fp, "initial\n"); + fprintf(fp, " begin //--- CONFIG_DONE GENERATOR\n"); + fprintf(fp, " %s = 1'b0;\n", top_tb_config_done_port_name); + fprintf(fp, " //----- %s signal is enabled after %d configurating operations are done ----\n", + top_tb_config_done_port_name, num_config_clock_cycles); + fprintf(fp, " #%.2f %s = 1'b1;\n", + num_config_clock_cycles * prog_clock_period / verilog_sim_timescale, top_tb_config_done_port_name); + fprintf(fp, " end\n"); + fprintf(fp, "//----- END of %s ----\n", + top_tb_config_done_port_name); + fprintf(fp, "\n"); + + /* Generate stimilus of programming clock */ + fprintf(fp, "//----- Raw Programming clock ----\n"); + fprintf(fp, "initial\n"); + fprintf(fp, " begin //--- PROG_CLOCK INITIALIZATION\n"); + fprintf(fp, " %s%s = 1'b0;\n", top_tb_prog_clock_port_name, top_tb_clock_reg_postfix); + fprintf(fp, " end\n"); + fprintf(fp, "always\n"); + fprintf(fp, " begin //--- PROG_CLOCK GENERATOR\n"); + fprintf(fp, " #%.2f %s%s = ~%s%s;\n", + 0.5*prog_clock_period / verilog_sim_timescale, + top_tb_prog_clock_port_name, top_tb_clock_reg_postfix, + top_tb_prog_clock_port_name, top_tb_clock_reg_postfix); + fprintf(fp, " end\n"); + fprintf(fp, "//----- END of Programming clock ----\n"); + fprintf(fp, "\n"); + /* Programming clock should be only enabled during programming phase. + * When configuration is done (config_done is enabled), programming clock should be always zero. + */ + fprintf(fp, "//---- Actual programming clock is triggered only when %s and %s are disabled\n", + top_tb_config_done_port_name, + top_tb_prog_reset_port_name); + fprintf(fp, " assign %s = %s%s & (~%s) & (~%s);\n", + top_tb_prog_clock_port_name, + top_tb_prog_clock_port_name, top_tb_clock_reg_postfix, + top_tb_config_done_port_name, + top_tb_prog_reset_port_name); + /* + fprintf(fp, " assign %s = %s%s & (~%s);\n", + top_tb_prog_clock_port_name, + top_tb_prog_clock_port_name, top_tb_clock_reg_postfix, + top_tb_config_done_port_name); + */ + fprintf(fp, "//----- END of Actual Programming clock ----\n"); + fprintf(fp, "\n"); + + /* Generate stimilus of programming clock */ + fprintf(fp, "//----- Raw Operation clock ----\n"); + fprintf(fp, "initial\n"); + fprintf(fp, " begin //--- OP_CLOCK INITIALIZATION\n"); + fprintf(fp, " %s%s = 1'b0;\n", top_tb_op_clock_port_name, top_tb_clock_reg_postfix); + fprintf(fp, " end\n"); + fprintf(fp, "always wait(~%s)\n", top_tb_reset_port_name); + fprintf(fp, " begin //--- OP_CLOCK GENERATOR\n"); + fprintf(fp, " #%.2f %s%s = ~%s%s;\n", + 0.5*op_clock_period / verilog_sim_timescale, + top_tb_op_clock_port_name, top_tb_clock_reg_postfix, + top_tb_op_clock_port_name, top_tb_clock_reg_postfix); + fprintf(fp, " end\n"); + fprintf(fp, "//----- END of Operation clock ----\n"); + /* Operation clock should be enabled after programming phase finishes. + * Before configuration is done (config_done is enabled), operation clock should be always zero. + */ + fprintf(fp, "//---- Actual operation clock is triggered only when %s is enabled \n", + top_tb_config_done_port_name); + fprintf(fp, " assign %s = %s%s & (%s);\n", + top_tb_op_clock_port_name, + top_tb_op_clock_port_name, top_tb_clock_reg_postfix, + top_tb_config_done_port_name); + fprintf(fp, "//----- END of Actual Operation clock ----\n"); + fprintf(fp, "\n"); + + /* Reset signal for configuration circuit : only enable during the first clock cycle in programming phase */ + fprintf(fp, "//----- Programming Reset Stimuli ----\n"); + fprintf(fp, "initial\n"); + fprintf(fp, " begin //--- PROGRAMMING RESET GENERATOR\n"); + fprintf(fp, " %s = 1'b1;\n", top_tb_prog_reset_port_name); + /* Reset is enabled until the first clock cycle in operation phase */ + fprintf(fp, "//----- Reset signal is enabled until the first clock cycle in programming phase ----\n"); + fprintf(fp, "#%.2f %s = 1'b0;\n", + (1 * prog_clock_period) / verilog_sim_timescale, + top_tb_prog_reset_port_name); + fprintf(fp, "end\n"); + fprintf(fp, "\n"); + + /* Set signal for configuration circuit : only enable during the first clock cycle in programming phase */ + fprintf(fp, "//----- Programming set Stimuli ----\n"); + fprintf(fp, "initial\n"); + fprintf(fp, " begin //--- PROGRAMMING SET GENERATOR\n"); + fprintf(fp, "%s = 1'b0;\n", top_tb_prog_set_port_name); + fprintf(fp, "//----- Programming set signal is always disabled -----\n"); + fprintf(fp, "end\n"); + fprintf(fp, "\n"); + + /* reset signals: only enabled during the first clock cycle in operation phase */ + fprintf(fp, "//----- Reset Stimuli ----\n"); + fprintf(fp, "initial\n"); + fprintf(fp, " begin //--- RESET GENERATOR\n"); + fprintf(fp, " %s = 1'b1;\n", top_tb_reset_port_name); + /* Reset is enabled until the first clock cycle in operation phase */ + fprintf(fp, "//----- Reset signal is enabled until the first clock cycle in operation phase ----\n"); + fprintf(fp, "wait(%s);\n", + top_tb_config_done_port_name); + fprintf(fp, "#%.2f %s = 1'b1;\n", + (1 * op_clock_period)/ verilog_sim_timescale, + top_tb_reset_port_name); + fprintf(fp, "#%.2f %s = 1'b0;\n", + (2 * op_clock_period) / verilog_sim_timescale, + top_tb_reset_port_name); + fprintf(fp, "end\n"); + fprintf(fp, "\n"); + + /* set signals */ + fprintf(fp, "//----- Set Stimuli ----\n"); + fprintf(fp, "initial\n"); + fprintf(fp, " begin //--- SET GENERATOR\n"); + fprintf(fp, "%s = 1'b0;\n", top_tb_set_port_name); + fprintf(fp, "//----- Set signal is always disabled -----\n"); + fprintf(fp, "end\n"); + fprintf(fp, "\n"); + + /* Inputs stimuli: BL/WL address lines */ + dump_verilog_top_testbench_conf_bits_serial(fp, sram_verilog_orgz_info->conf_bit_head); + + /* For each input_signal + * TODO: this part is low-efficent for run-time concern... Need improve + */ + assert(NULL != iopad_verilog_model); + for (iopad_idx = 0; iopad_idx < iopad_verilog_model->cnt; iopad_idx++) { + /* Find if this inpad is mapped to a logical block */ + found_mapped_inpad = 0; + for (iblock = 0; iblock < num_logical_blocks; iblock++) { + /* Bypass OUTPAD: donot put any voltage stimuli */ + /* Make sure We find the correct logical block !*/ + if ((iopad_verilog_model == logical_block[iblock].mapped_spice_model) + &&(iopad_idx == logical_block[iblock].mapped_spice_model_index)) { + /* Output PAD only need a short connection */ + if (VPACK_OUTPAD == logical_block[iblock].type) { + fprintf(fp, "//----- Output %s does not need a Stimuli ----\n", logical_block[iblock].name); + fprintf(fp, "initial\n"); + fprintf(fp, " begin //--- Input %s[%d] GENERATOR\n", gio_inout_prefix, iopad_idx); + fprintf(fp, " %s%s%s[%d] = 1'b%d;\n", + gio_inout_prefix, iopad_verilog_model->prefix, top_tb_inout_reg_postfix, iopad_idx, + verilog_default_signal_init_value); + fprintf(fp, "end\n"); + found_mapped_inpad = 1; + break; + } + /* Input PAD only need a short connection */ + assert(VPACK_INPAD == logical_block[iblock].type); + cur_spice_net_info = NULL; + for (inet = 0; inet < num_nets; inet++) { + if (0 == strcmp(clb_net[inet].name, logical_block[iblock].name)) { + cur_spice_net_info = clb_net[inet].spice_net_info; + break; + } + } + assert(NULL != cur_spice_net_info); + assert(!(0 > cur_spice_net_info->density)); + assert(!(1 < cur_spice_net_info->density)); + assert(!(0 > cur_spice_net_info->probability)); + assert(!(1 < cur_spice_net_info->probability)); + /* Connect the reg to inouts */ + fprintf(fp, "//----- Input %s Stimuli ----\n", logical_block[iblock].name); + fprintf(fp, "assign %s%s[%d] = %s%s%s[%d];\n", + gio_inout_prefix, iopad_verilog_model->prefix, iopad_idx, + gio_inout_prefix, iopad_verilog_model->prefix, top_tb_inout_reg_postfix, iopad_idx); + /* Get the net information */ + /* TODO: Give the net name in the blif file !*/ + fprintf(fp, "initial\n"); + fprintf(fp, " begin //--- Input %s GENERATOR\n", logical_block[iblock].name); + fprintf(fp, " %s%s%s[%d] = 1'b%d;\n", + gio_inout_prefix, iopad_verilog_model->prefix, top_tb_inout_reg_postfix, iopad_idx, + cur_spice_net_info->init_val); + fprintf(fp, "end\n"); + fprintf(fp, "always wait (~%s)\n", top_tb_reset_port_name); + fprintf(fp, " begin \n"); + fprintf(fp, " #%.2f %s%s%s[%d] = ~%s%s%s[%d];\n", + (op_clock_period * cur_spice_net_info->density * 2. / cur_spice_net_info->probability) / verilog_sim_timescale, + gio_inout_prefix, iopad_verilog_model->prefix, top_tb_inout_reg_postfix, iopad_idx, + gio_inout_prefix, iopad_verilog_model->prefix, top_tb_inout_reg_postfix, iopad_idx); + fprintf(fp, " end \n"); + fprintf(fp, "\n"); + found_mapped_inpad++; + } + } + assert((0 == found_mapped_inpad)||(1 == found_mapped_inpad)); + /* If we find one iopad already, we finished in this round here */ + if (1 == found_mapped_inpad) { + continue; + } + /* if we cannot find any mapped inpad from tech.-mapped netlist, give a default */ + /* Connect the reg to inouts */ + fprintf(fp, "//----- Input %s[%d] Stimuli ----\n", gio_inout_prefix, iopad_idx); + fprintf(fp, "assign %s%s[%d] = %s%s%s[%d];\n", + gio_inout_prefix, iopad_verilog_model->prefix, iopad_idx, + gio_inout_prefix, iopad_verilog_model->prefix, top_tb_inout_reg_postfix, iopad_idx); + /* TODO: Give the net name in the blif file !*/ + fprintf(fp, "initial\n"); + fprintf(fp, " begin //--- Input %s[%d] GENERATOR\n", gio_inout_prefix, iopad_idx); + fprintf(fp, " %s%s%s[%d] = 1'b%d;\n", + gio_inout_prefix, iopad_verilog_model->prefix, top_tb_inout_reg_postfix, iopad_idx, + verilog_default_signal_init_value); + fprintf(fp, "end\n"); + } + + /* Finish */ + + return; +} + +/* Generate the stimuli for the top-level testbench + * The simulation consists of two phases: configuration phase and operation phase + * We have two choices for the configuration phase: + * 1. Configuration bits are loaded serially. + * This is actually what we do for a physical FPGA + * 2. Configuration bits are loaded parallel. + * This is only feasible in simulation, which is convenient to check functionality. + */ +void dump_verilog_top_testbench_stimuli(FILE* fp, + int num_clock, + t_syn_verilog_opts syn_verilog_opts, + t_spice verilog) { + + /* Only serial version is avaiable now */ + dump_verilog_top_testbench_stimuli_serial_version(fp, num_clock, verilog); + /* + if (TRUE == syn_verilog_opts.tb_serial_config_mode) { + } else { + dump_verilog_top_testbench_stimuli_parallel_version(fp, num_clock, verilog); + } + */ + + return; +} + +/* Dump the ports for input blif nestlist */ +static +void dump_verilog_input_blif_testbench_ports(FILE* fp, + char* circuit_name) { + int iblock; + + fprintf(fp, "module %s_blif_tb;\n", circuit_name); + + fprintf(fp, " reg %s;\n", top_tb_reset_port_name); + + /* Print all the inputs/outputs*/ + for (iblock = 0; iblock < num_logical_blocks; iblock++) { + /* Make sure We find the correct logical block !*/ + switch (logical_block[iblock].type) { + case VPACK_INPAD: + fprintf(fp, " reg %s;\n", logical_block[iblock].name); + break; + case VPACK_OUTPAD: + fprintf(fp, " wire %s;\n", logical_block[iblock].name); + break; + case VPACK_COMB: + case VPACK_LATCH: + case VPACK_EMPTY: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) Invalid type of logical block[%d]!\n", + __FILE__, __LINE__, iblock); + exit(1); + } + } + + return; +} + +/* Dump the module to be tested for input blif nestlist */ +static +void dump_verilog_input_blif_testbench_call_top_module(FILE* fp, + char* circuit_name) { + int iblock, cnt; + /* Initialize a counter */ + cnt = 0; + + fprintf(fp, "%s uut (\n", circuit_name); + /* Print all the inputs/outputs*/ + for (iblock = 0; iblock < num_logical_blocks; iblock++) { + /* Make sure We find the correct logical block !*/ + switch (logical_block[iblock].type) { + case VPACK_INPAD: + case VPACK_OUTPAD: + /* Dump a comma only when needed*/ + if (0 < cnt) { + fprintf(fp, ",\n"); + } + /* Dump an input/output, avoid additional comma leading to wrong connections */ + fprintf(fp, "%s", logical_block[iblock].name); + /* Update counter */ + cnt++; + break; + case VPACK_COMB: + case VPACK_LATCH: + case VPACK_EMPTY: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) Invalid type of logical block[%d]!\n", + __FILE__, __LINE__, iblock); + exit(1); + } + } + fprintf(fp, ");\n"); + fprintf(fp, "//---- End call module %s (%d inputs and outputs) -----\n", + circuit_name, cnt); + + return; +} + +/* Dump voltage stimuli for input blif nestlist */ +static +void dump_verilog_input_blif_testbench_stimuli(FILE* fp, + int num_clock, + t_syn_verilog_opts syn_verilog_opts, + t_spice spice) { + int iblock, inet; + t_spice_net_info* cur_spice_net_info = NULL; + float op_clock_period = 1./spice.spice_params.stimulate_params.op_clock_freq; + + fprintf(fp, "//----- Operation clock period: %.2g -----\n", op_clock_period); + + /* reset signals: only enabled during the first clock cycle in operation phase */ + fprintf(fp, "//----- Reset Stimuli ----\n"); + fprintf(fp, "initial\n"); + fprintf(fp, " begin //--- RESET GENERATOR\n"); + fprintf(fp, " %s = 1'b1;\n", top_tb_reset_port_name); + /* Reset is enabled until the first clock cycle in operation phase */ + fprintf(fp, "//----- Reset signal is enabled until the first clock cycle in operation phase ----\n"); + fprintf(fp, "#%.2f %s = 1'b0;\n", + (1 * op_clock_period) / verilog_sim_timescale, + top_tb_reset_port_name); + fprintf(fp, "end\n"); + fprintf(fp, "\n"); + + /* Regular inputs */ + for (iblock = 0; iblock < num_logical_blocks; iblock++) { + /* Make sure We find the correct logical block !*/ + switch (logical_block[iblock].type) { + case VPACK_INPAD: + cur_spice_net_info = NULL; + for (inet = 0; inet < num_nets; inet++) { + if (0 == strcmp(clb_net[inet].name, logical_block[iblock].name)) { + cur_spice_net_info = clb_net[inet].spice_net_info; + break; + } + } + assert(NULL != cur_spice_net_info); + assert(!(0 > cur_spice_net_info->density)); + assert(!(1 < cur_spice_net_info->density)); + assert(!(0 > cur_spice_net_info->probability)); + assert(!(1 < cur_spice_net_info->probability)); + /* Get the net information */ + /* TODO: Give the net name in the blif file !*/ + fprintf(fp, "//----- Input %s Stimuli ----\n", logical_block[iblock].name); + fprintf(fp, "initial\n"); + fprintf(fp, " begin //--- Input %s GENERATOR\n", logical_block[iblock].name); + fprintf(fp, " %s = 1'b%d;\n", + logical_block[iblock].name, + cur_spice_net_info->init_val); + fprintf(fp, "end\n"); + fprintf(fp, "always wait (~%s)\n", top_tb_reset_port_name); + fprintf(fp, " begin \n"); + fprintf(fp, " #%.2f %s = ~%s;\n", + (op_clock_period * cur_spice_net_info->density * 2. / cur_spice_net_info->probability) / verilog_sim_timescale, + logical_block[iblock].name, + logical_block[iblock].name); + fprintf(fp, " end \n"); + fprintf(fp, "\n"); + break; + case VPACK_OUTPAD: + case VPACK_COMB: + case VPACK_LATCH: + case VPACK_EMPTY: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) Invalid type of logical block[%d]!\n", + __FILE__, __LINE__, iblock); + exit(1); + } + } + + return; +} + +/***** Print Top-level SPICE netlist *****/ +void dump_verilog_top_netlist(char* circuit_name, + char* top_netlist_name, + char* include_dir_path, + char* subckt_dir_path, + int LL_num_rr_nodes, + t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices, + int num_clock, + t_spice verilog) { + FILE* fp = NULL; + char* formatted_subckt_dir_path = format_dir_path(subckt_dir_path); + char* temp_include_file_path = NULL; + char* title = my_strcat("FPGA Verilog Netlist for Design: ", circuit_name); + + /* Check if the path exists*/ + fp = fopen(top_netlist_name,"w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create top Verilog netlist %s!",__FILE__, __LINE__, top_netlist_name); + exit(1); + } + + vpr_printf(TIO_MESSAGE_INFO, "Writing FPGA Top-level Verilog Netlist for %s...\n", circuit_name); + + /* Print the title */ + dump_verilog_file_header(fp, title); + my_free(title); + + /* Include user-defined sub-circuit netlist */ + fprintf(fp, "//----- Include User-defined netlists -----\n"); + init_include_user_defined_verilog_netlists(verilog); + dump_include_user_defined_verilog_netlists(fp, verilog); + + /* Special subckts for Top-level SPICE netlist */ + fprintf(fp, "//----- Include subckt netlists: Multiplexers -----\n"); + temp_include_file_path = my_strcat(formatted_subckt_dir_path, muxes_verilog_file_name); + fprintf(fp, "// `include \"%s\"\n", temp_include_file_path); + my_free(temp_include_file_path); + + fprintf(fp, "//----- Include subckt netlists: Wires -----\n"); + temp_include_file_path = my_strcat(formatted_subckt_dir_path, wires_verilog_file_name); + fprintf(fp, "// `include \"%s\"\n", temp_include_file_path); + my_free(temp_include_file_path); + + fprintf(fp, "//----- Include subckt netlists: Look-Up Tables (LUTs) -----\n"); + temp_include_file_path = my_strcat(formatted_subckt_dir_path, luts_verilog_file_name); + fprintf(fp, "// `include \"%s\"\n", temp_include_file_path); + my_free(temp_include_file_path); + + fprintf(fp, "//------ Include subckt netlists: Logic Blocks -----\n"); + temp_include_file_path = my_strcat(formatted_subckt_dir_path, logic_block_verilog_file_name); + fprintf(fp, "// `include \"%s\"\n", temp_include_file_path); + my_free(temp_include_file_path); + + fprintf(fp, "//----- Include subckt netlists: Routing structures (Switch Boxes, Channels, Connection Boxes) -----\n"); + temp_include_file_path = my_strcat(formatted_subckt_dir_path, routing_verilog_file_name); + fprintf(fp, "// `include \"%s\"\n", temp_include_file_path); + my_free(temp_include_file_path); + + /* Include decoders if required */ + switch(sram_verilog_orgz_type) { + case SPICE_SRAM_STANDALONE: + case SPICE_SRAM_SCAN_CHAIN: + break; + case SPICE_SRAM_MEMORY_BANK: + /* Include verilog decoder */ + fprintf(fp, "//----- Include subckt netlists: Decoders (controller for memeory bank) -----\n"); + temp_include_file_path = my_strcat(formatted_subckt_dir_path, decoders_verilog_file_name); + fprintf(fp, "// `include \"%s\"\n", temp_include_file_path); + my_free(temp_include_file_path); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization in Verilog Generator!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Print all global wires*/ + dump_verilog_top_netlist_ports(fp, num_clock, circuit_name, verilog); + + dump_verilog_top_netlist_internal_wires(fp); + + /* Quote defined Logic blocks subckts (Grids) */ + dump_verilog_defined_grids(fp); + + /* Quote Routing structures: Channels */ + dump_verilog_defined_channels(fp, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + + /* Quote Routing structures: Conneciton Boxes */ + dump_verilog_defined_connection_boxes(fp); + + /* Quote Routing structures: Switch Boxes */ + dump_verilog_defined_switch_boxes(fp); + + /* Dump configuration circuits */ + dump_verilog_configuration_circuits(fp); + + /* verilog ends*/ + fprintf(fp, "endmodule\n"); + + /* Close the file*/ + fclose(fp); + + return; +} + +/** Top level function 2: Testbench for the top-level netlist + * This testbench includes a top-level module of a mapped FPGA and voltage pulses + */ +void dump_verilog_top_testbench(char* circuit_name, + char* top_netlist_name, + int num_clock, + t_syn_verilog_opts syn_verilog_opts, + t_spice verilog) { + FILE* fp = NULL; + char* title = my_strcat("FPGA Verilog Testbench for Top-level netlist of Design: ", circuit_name); + + /* Check if the path exists*/ + fp = fopen(top_netlist_name,"w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create top Verilog testbench %s!",__FILE__, __LINE__, top_netlist_name); + exit(1); + } + + vpr_printf(TIO_MESSAGE_INFO, "Writing Testbench for FPGA Top-level Verilog netlist for %s...\n", circuit_name); + + /* Print the title */ + dump_verilog_file_header(fp, title); + my_free(title); + + /* Start of testbench */ + dump_verilog_top_testbench_ports(fp, circuit_name); + + /* Call defined top-level module */ + dump_verilog_top_testbench_call_top_module(fp, circuit_name); + + /* Add stimuli for reset, set, clock and iopad signals */ + dump_verilog_top_testbench_stimuli(fp, num_clock, syn_verilog_opts, verilog); + + /* Testbench ends*/ + fprintf(fp, "endmodule\n"); + + /* Close the file*/ + fclose(fp); + + return; +} + +/** Top level function 3: Testbench for the top-level blif netlist (before FPGA mapping) + * This testbench includes a top-level module of a mapped FPGA and voltage pulses + */ +void dump_verilog_input_blif_testbench(char* circuit_name, + char* top_netlist_name, + int num_clock, + t_syn_verilog_opts syn_verilog_opts, + t_spice verilog) { + FILE* fp = NULL; + char* title = my_strcat("FPGA Verilog Testbench for input blif netlist of Design: ", circuit_name); + + /* Check if the path exists*/ + fp = fopen(top_netlist_name,"w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create top Verilog testbench %s!",__FILE__, __LINE__, top_netlist_name); + exit(1); + } + + vpr_printf(TIO_MESSAGE_INFO, "Writing Testbench for blif netlist: %s...\n", circuit_name); + + /* Print the title */ + dump_verilog_file_header(fp, title); + my_free(title); + + /* Start of testbench */ + dump_verilog_input_blif_testbench_ports(fp, circuit_name); + + /* Call defined top-level module */ + dump_verilog_input_blif_testbench_call_top_module(fp, circuit_name); + + /* Add stimuli for reset, set, clock and iopad signals */ + dump_verilog_input_blif_testbench_stimuli(fp, num_clock, syn_verilog_opts, verilog); + + /* Testbench ends*/ + fprintf(fp, "endmodule\n"); + + /* Close the file*/ + fclose(fp); + + return; + +} diff --git a/vpr7_rram/vpr/SRC/syn_verilog/verilog_top_netlist.h b/vpr7_rram/vpr/SRC/syn_verilog/verilog_top_netlist.h new file mode 100644 index 000000000..72829d050 --- /dev/null +++ b/vpr7_rram/vpr/SRC/syn_verilog/verilog_top_netlist.h @@ -0,0 +1,22 @@ + +void dump_verilog_top_netlist(char* circuit_name, + char* top_netlist_name, + char* include_dir_path, + char* subckt_dir_path, + int LL_num_rr_nodes, + t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices, + int num_clock, + t_spice spice); + +void dump_verilog_top_testbench(char* circuit_name, + char* top_netlist_name, + int num_clock, + t_syn_verilog_opts syn_verilog_opts, + t_spice verilog); + +void dump_verilog_input_blif_testbench(char* circuit_name, + char* top_netlist_name, + int num_clock, + t_syn_verilog_opts syn_verilog_opts, + t_spice verilog); diff --git a/vpr7_rram/vpr/SRC/syn_verilog/verilog_utils.c b/vpr7_rram/vpr/SRC/syn_verilog/verilog_utils.c new file mode 100644 index 000000000..9b9c9ca4b --- /dev/null +++ b/vpr7_rram/vpr/SRC/syn_verilog/verilog_utils.c @@ -0,0 +1,2021 @@ +/***********************************/ +/* Synthesizable Verilog Dumping */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph_util.h" +#include "rr_graph.h" +#include "rr_graph2.h" +#include "vpr_utils.h" + +/* FPGA-SPICE utils */ +#include "read_xml_spice_util.h" +#include "linkedlist.h" +#include "fpga_spice_utils.h" +#include "fpga_spice_globals.h" + +/* syn_verilog globals */ +#include "verilog_global.h" +#include "verilog_utils.h" + +/****** Subroutines *******/ +void init_list_include_verilog_netlists(t_spice* spice) { + int i, j, cur; + int to_include = 0; + int num_to_include = 0; + + /* Initialize */ + for (i = 0; i < spice->num_include_netlist; i++) { + FreeSpiceModelNetlist(&(spice->include_netlists[i])); + } + my_free(spice->include_netlists); + spice->include_netlists = NULL; + spice->num_include_netlist = 0; + + /* Generate include netlist list */ + vpr_printf(TIO_MESSAGE_INFO, "Listing Verilog Netlist Names to be included...\n"); + for (i = 0; i < spice->num_spice_model; i++) { + if (NULL != spice->spice_models[i].verilog_netlist) { + /* Check if this netlist name has already existed in the list */ + to_include = 1; + for (j = 0; j < i; j++) { + if (NULL == spice->spice_models[j].verilog_netlist) { + continue; + } + if (0 == strcmp(spice->spice_models[j].verilog_netlist, spice->spice_models[i].verilog_netlist)) { + to_include = 0; + break; + } + } + /* Increamental */ + if (1 == to_include) { + num_to_include++; + } + } + } + + /* realloc */ + spice->include_netlists = (t_spice_model_netlist*)my_realloc(spice->include_netlists, + sizeof(t_spice_model_netlist)*(num_to_include + spice->num_include_netlist)); + + /* Fill the new included netlists */ + cur = spice->num_include_netlist; + for (i = 0; i < spice->num_spice_model; i++) { + if (NULL != spice->spice_models[i].verilog_netlist) { + /* Check if this netlist name has already existed in the list */ + to_include = 1; + for (j = 0; j < i; j++) { + if (NULL == spice->spice_models[j].verilog_netlist) { + continue; + } + if (0 == strcmp(spice->spice_models[j].verilog_netlist, spice->spice_models[i].verilog_netlist)) { + to_include = 0; + break; + } + } + /* Increamental */ + if (1 == to_include) { + spice->include_netlists[cur].path = my_strdup(spice->spice_models[i].verilog_netlist); + spice->include_netlists[cur].included = 0; + vpr_printf(TIO_MESSAGE_INFO, "[%d] %s\n", cur+1, spice->include_netlists[cur].path); + cur++; + } + } + } + /* Check */ + assert(cur == (num_to_include + spice->num_include_netlist)); + /* Update */ + spice->num_include_netlist += num_to_include; + + return; +} + + +void init_include_user_defined_verilog_netlists(t_spice spice) { + int i; + + /* Include user-defined sub-circuit netlist */ + for (i = 0; i < spice.num_include_netlist; i++) { + spice.include_netlists[i].included = 0; + } + + return; +} + +void dump_include_user_defined_verilog_netlists(FILE* fp, + t_spice spice) { + int i; + + /* A valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* Include user-defined sub-circuit netlist */ + for (i = 0; i < spice.num_include_netlist; i++) { + if (0 == spice.include_netlists[i].included) { + assert(NULL != spice.include_netlists[i].path); + fprintf(fp, "// `include \"%s\"\n", spice.include_netlists[i].path); + spice.include_netlists[i].included = 1; + } else { + assert(1 == spice.include_netlists[i].included); + } + } + + return; +} + +void dump_verilog_file_header(FILE* fp, + char* usage) { + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d]) FileHandle is NULL!\n",__FILE__,__LINE__); + exit(1); + } + fprintf(fp,"//-------------------------------------------\n"); + fprintf(fp,"// FPGA Synthesizable Verilog Netlist \n"); + fprintf(fp,"// Description: %s \n",usage); + fprintf(fp,"// Author: Xifan TANG \n"); + fprintf(fp,"// Organization: EPFL/IC/LSI \n"); + fprintf(fp,"// Date: %s \n",my_gettime()); + fprintf(fp,"//-------------------------------------------\n"); + fprintf(fp,"//----- Time scale -----\n"); + fprintf(fp,"`timescale 1ns / 1ps\n"); + fprintf(fp,"\n"); + + return; +} + +/* Determine the split sign for generic port */ +char determine_verilog_generic_port_split_sign(enum e_dump_verilog_port_type dump_port_type) { + char ret; + + switch (dump_port_type) { + case VERILOG_PORT_INPUT: + case VERILOG_PORT_OUTPUT: + case VERILOG_PORT_INOUT: + case VERILOG_PORT_CONKT: + ret = ','; + break; + case VERILOG_PORT_WIRE: + case VERILOG_PORT_REG: + ret = ';'; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of Verilog port to be dumped !\n", + __FILE__, __LINE__); + exit(1); + } + + return ret; +} + +/* Dump a generic Verilog port */ +void dump_verilog_generic_port(FILE* fp, + enum e_dump_verilog_port_type dump_port_type, + char* port_name, int port_lsb, int port_msb) { + boolean dump_single_port = FALSE; + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert((!(port_lsb < 0))&&(!(port_msb < 0))); + if (port_lsb == port_msb) { + dump_single_port = TRUE; + } + dump_single_port = FALSE; /* Disable it for a clear synthesis */ + + switch (dump_port_type) { + case VERILOG_PORT_INPUT: + if (TRUE == dump_single_port) { + fprintf(fp,"input %s ", + port_name); + } else { + assert(FALSE == dump_single_port); + fprintf(fp,"input [%d:%d] %s ", + port_lsb, port_msb, + port_name); + } + break; + case VERILOG_PORT_OUTPUT: + if (TRUE == dump_single_port) { + fprintf(fp,"output %s ", + port_name); + } else { + assert(FALSE == dump_single_port); + fprintf(fp,"output [%d:%d] %s ", + port_lsb, port_msb, + port_name); + } + break; + case VERILOG_PORT_INOUT: + if (TRUE == dump_single_port) { + fprintf(fp,"inout %s ", + port_name); + } else { + assert(FALSE == dump_single_port); + fprintf(fp,"inout [%d:%d] %s ", + port_lsb, port_msb, + port_name); + } + break; + case VERILOG_PORT_WIRE: + if (TRUE == dump_single_port) { + fprintf(fp,"wire %s ", + port_name); + } else { + assert(FALSE == dump_single_port); + fprintf(fp,"wire [%d:%d] %s ", + port_lsb, port_msb, + port_name); + } + break; + case VERILOG_PORT_REG: + if (TRUE == dump_single_port) { + fprintf(fp,"reg %s ", + port_name); + } else { + assert(FALSE == dump_single_port); + fprintf(fp,"reg [%d:%d] %s ", + port_lsb, port_msb, + port_name); + } + break; + case VERILOG_PORT_CONKT: + if (TRUE == dump_single_port) { + fprintf(fp,"%s ", + port_name); + } else { + assert(FALSE == dump_single_port); + fprintf(fp,"%s[%d:%d] ", + port_name, + port_lsb, port_msb); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of Verilog port to be dumped !\n", + __FILE__, __LINE__); + exit(1); + } + + return; +} + + + +/* Decode BL and WL bits for a SRAM + * SRAM could be + * 1. NV SRAM + * or + * 2. SRAM + */ +void decode_verilog_memory_bank_sram(t_spice_model* cur_sram_spice_model, int sram_bit, + int bl_len, int wl_len, int bl_offset, int wl_offset, + int* bl_conf_bits, int* wl_conf_bits) { + int i; + + /* Check */ + assert(NULL != cur_sram_spice_model); + assert(NULL != bl_conf_bits); + assert(NULL != wl_conf_bits); + assert((1 == sram_bit)||(0 == sram_bit)); + + /* All the others should be zero */ + for (i = 0; i < bl_len; i++) { + bl_conf_bits[i] = 0; + } + for (i = 0; i < wl_len; i++) { + wl_conf_bits[i] = 0; + } + + /* Depending on the design technology of SRAM */ + switch (cur_sram_spice_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + /* CMOS SRAM */ + /* Make sure there is only 1 BL and 1 WL */ + assert((1 == bl_len)&&(1 == wl_len)); + /* We always assume that WL is a write-enable signal + * While BL contains what data will be written into SRAM + */ + bl_conf_bits[0] = sram_bit; + wl_conf_bits[0] = 1; + break; + case SPICE_MODEL_DESIGN_RRAM: + /* NV SRAM (RRAM-based) */ + /* We need at least 2 BLs and 2 WLs but no more than 3, See schematic in manual */ + /* Whatever the number of BLs and WLs, (RRAM0) + * when sram bit is 1, last bit of BL should be enabled + * while first bit of WL should be enabled at the same time + * when sram bit is 0, last bit of WL should be enabled + * while first bit of BL should be enabled at the same time + */ + assert((1 < bl_len)&&(bl_len < 4)); + assert((1 < wl_len)&&(wl_len < 4)); + assert((-1 < bl_offset)&&(bl_offset < bl_len)); + assert((-1 < wl_offset)&&(wl_offset < wl_len)); + /* In addition, we will may need two programing cycles. + * The first cycle is dedicated to programming RRAM0 + * The second cycle is dedicated to programming RRAM1 + */ + if (1 == sram_bit) { + bl_conf_bits[bl_len-1] = 1; + wl_conf_bits[0 + wl_offset] = 1; + } else { + assert(0 == sram_bit); + bl_conf_bits[0 + bl_offset] = 1; + wl_conf_bits[wl_len-1] = 1; + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology for SRAM!\n", + __FILE__, __LINE__); + exit(1); + } + + return; +} + +/* Decode one SRAM bit for memory-bank-style configuration circuit, and add it to linked list */ +void +decode_and_add_verilog_sram_membank_conf_bit_to_llist(t_sram_orgz_info* cur_sram_orgz_info, + int mem_index, + int num_bl_per_sram, int num_wl_per_sram, + int cur_sram_bit) { + int j; + int* conf_bits_per_sram = NULL; + t_spice_model* mem_model = NULL; + + /* Check */ + assert( SPICE_SRAM_MEMORY_BANK == cur_sram_orgz_info->type ); + + /* Get memory model */ + get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); + assert(NULL != mem_model); + + /* Malloc/Calloc */ + conf_bits_per_sram = (int*)my_calloc(num_bl_per_sram + num_wl_per_sram, sizeof(int)); + + /* Depend on the memory technology, we have different configuration bits */ + switch (mem_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + /* Check */ + assert((1 == num_bl_per_sram) && (1 == num_wl_per_sram)); + /* For CMOS SRAM */ + decode_verilog_memory_bank_sram(mem_model, cur_sram_bit, + num_bl_per_sram, num_wl_per_sram, 0, 0, + conf_bits_per_sram, conf_bits_per_sram + num_bl_per_sram); + /* Use memory model here! Design technology of memory model determines the decoding strategy, instead of LUT model*/ + add_sram_conf_bits_to_llist(cur_sram_orgz_info, mem_index, + num_bl_per_sram + num_wl_per_sram, conf_bits_per_sram); + break; + case SPICE_MODEL_DESIGN_RRAM: + /* Decode the SRAM bits to BL/WL bits. + * first half part is BL, the other half part is WL + */ + /* Store the configuraion bit to linked-list */ + assert(num_bl_per_sram == num_wl_per_sram); + /* When the number of BL/WL is more than 1, we need multiple programming cycles to configure a SRAM */ + /* ONLY valid for NV SRAM !!!*/ + for (j = 0; j < num_bl_per_sram - 1; j++) { + if (0 == j) { + /* Store the configuraion bit to linked-list */ + decode_verilog_memory_bank_sram(mem_model, cur_sram_bit, + num_bl_per_sram, num_wl_per_sram, j, j, + conf_bits_per_sram, conf_bits_per_sram + num_bl_per_sram); + } else { + /* Store the configuraion bit to linked-list */ + decode_verilog_memory_bank_sram(mem_model, 1 - cur_sram_bit, + num_bl_per_sram, num_wl_per_sram, j, j, + conf_bits_per_sram, conf_bits_per_sram + num_bl_per_sram); + } + /* Use memory model here! Design technology of memory model determines the decoding strategy, instead of LUT model*/ + add_sram_conf_bits_to_llist(cur_sram_orgz_info, mem_index, + num_bl_per_sram + num_wl_per_sram, conf_bits_per_sram); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid design technology!", + __FILE__, __LINE__); + exit(1); + } + + /* Free */ + my_free(conf_bits_per_sram); + + return; +} + + +/** Decode 1-level 4T1R MUX + */ +void decode_verilog_one_level_4t1r_mux(int path_id, + int bit_len, int* conf_bits) { + int i; + + /* Check */ + assert(0 < bit_len); + assert(NULL != conf_bits); + assert((-1 < path_id)&&((path_id < bit_len/2 - 1)||(path_id == bit_len/2 - 1))); + + /* All the others should be zero */ + for (i = 0; i < bit_len; i++) { + conf_bits[i] = 0; + } + + /* Last bit of WL should be 1 */ + conf_bits[bit_len-1] = 1; + /* determine which BL should be 1*/ + conf_bits[path_id] = 1; + + return; +} + +/** Decode multi-level 4T1R MUX + */ +void decode_verilog_multilevel_4t1r_mux(int num_level, int num_input_basis, + int mux_size, int path_id, + int bit_len, int* conf_bits) { + int i, active_basis_path_id; + + /* Check */ + assert(0 < bit_len); + assert(NULL != conf_bits); + /* assert((-1 < path_id)&&(path_id < bit_len/2 - 1)); */ + /* Start from first level to the last level */ + active_basis_path_id = path_id; + for (i = 0; i < num_level; i++) { + /* Treat each basis as a 1-level 4T1R MUX */ + active_basis_path_id = active_basis_path_id % num_input_basis; + /* Last bit of WL should be 1 */ + conf_bits[bit_len/2 + (num_input_basis+1)*(i+1) - 1] = 1; + /* determine which BL should be 1*/ + conf_bits[(num_input_basis+1)*i + active_basis_path_id] = 1; + } + + return; +} + +/** Decode the configuration bits for a 4T1R-based MUX + * Determine the number of configuration bits + * Configuration bits are decoded depending on the MUX structure: + * 1. 1-level; 2. multi-level (tree-like); + */ +void decode_verilog_rram_mux(t_spice_model* mux_spice_model, + int mux_size, int path_id, + int* bit_len, int** conf_bits, int* mux_level) { + int num_level, num_input_basis; + + /* Check */ + assert(NULL != mux_level); + assert(NULL != bit_len); + assert(NULL != conf_bits); + assert((-1 < path_id)&&(path_id < mux_size)); + assert(SPICE_MODEL_MUX == mux_spice_model->type); + assert(SPICE_MODEL_DESIGN_RRAM == mux_spice_model->design_tech); + + /* Initialization */ + (*mux_level) = 0; + (*bit_len) = 0; + (*conf_bits) = NULL; + + (*bit_len) = 2 * count_num_sram_bits_one_spice_model(mux_spice_model, mux_size); + + /* Switch cases: MUX structure */ + switch (mux_spice_model->design_tech_info.structure) { + case SPICE_MODEL_STRUCTURE_ONELEVEL: + /* Number of configuration bits is 2*(input_size+1) */ + num_level = 1; + break; + case SPICE_MODEL_STRUCTURE_TREE: + /* Number of configuration bits is num_level* 2*(basis+1) */ + num_level = determine_tree_mux_level(mux_size); + num_input_basis = 2; + break; + case SPICE_MODEL_STRUCTURE_MULTILEVEL: + /* Number of configuration bits is num_level* 2*(basis+1) */ + num_level = mux_spice_model->design_tech_info.mux_num_level; + num_input_basis = determine_num_input_basis_multilevel_mux(mux_size, num_level); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid MUX structure!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Malloc configuration bits */ + (*conf_bits) = (int*)my_calloc((*bit_len), sizeof(int)); + + /* Decode configuration bits : BL & WL*/ + /* Switch cases: MUX structure */ + switch (mux_spice_model->design_tech_info.structure) { + case SPICE_MODEL_STRUCTURE_ONELEVEL: + decode_verilog_one_level_4t1r_mux(path_id, (*bit_len), (*conf_bits)); + break; + case SPICE_MODEL_STRUCTURE_TREE: + case SPICE_MODEL_STRUCTURE_MULTILEVEL: + decode_verilog_multilevel_4t1r_mux(num_level, num_input_basis, mux_size, + path_id, (*bit_len), (*conf_bits)); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid MUX structure!\n", + __FILE__, __LINE__); + exit(1); + } + + (*mux_level) = num_level; + + return; +} + +/* Determine the size of input address of a decoder */ +int determine_decoder_size(int num_addr_out) { + return ceil(log(num_addr_out)/log(2.)); +} + +char* chomp_verilog_node_prefix(char* verilog_node_prefix) { + int len = 0; + char* ret = NULL; + + if (NULL == verilog_node_prefix) { + return NULL; + } + + len = strlen(verilog_node_prefix); /* String length without the last "\0"*/ + ret = (char*)my_malloc(sizeof(char)*(len+1)); + + /* Don't do anything when input is NULL*/ + if (NULL == verilog_node_prefix) { + my_free(ret); + return NULL; + } + + strcpy(ret,verilog_node_prefix); + /* If the path end up with "_" we should remove it*/ + /* + if ('_' == ret[len-1]) { + ret[len-1] = ret[len]; + } + */ + + return ret; +} + +char* format_verilog_node_prefix(char* verilog_node_prefix) { + int len = strlen(verilog_node_prefix); /* String length without the last "\0"*/ + char* ret = (char*)my_malloc(sizeof(char)*(len+1)); + + /* Don't do anything when input is NULL*/ + if (NULL == verilog_node_prefix) { + my_free(ret); + return NULL; + } + + strcpy(ret,verilog_node_prefix); + /* If the path does not end up with "_" we should complete it*/ + /* + if (ret[len-1] != '_') { + strcat(ret, "_"); + } + */ + return ret; +} + +/* Return the port_type in a verilog format */ +char* verilog_convert_port_type_to_string(enum e_spice_model_port_type port_type) { + switch (port_type) { + case SPICE_MODEL_PORT_INPUT: + case SPICE_MODEL_PORT_CLOCK: + case SPICE_MODEL_PORT_SRAM: + case SPICE_MODEL_PORT_BL: + case SPICE_MODEL_PORT_WL: + return "input"; + case SPICE_MODEL_PORT_OUTPUT: + return "output"; + case SPICE_MODEL_PORT_INOUT: + return "inout"; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s, [LINE%d])Invalid port type!\n", + __FILE__, __LINE__); + exit(1); + } + + return NULL; +} + +/* Dump all the global ports that are stored in the linked list + * Return the number of ports that have been dumped + */ +int rec_dump_verilog_spice_model_global_ports(FILE* fp, + t_spice_model* cur_spice_model, + boolean dump_port_type, boolean recursive) { + int iport, dumped_port_cnt, rec_dumped_port_cnt; + boolean dump_comma = FALSE; + + dumped_port_cnt = 0; + rec_dumped_port_cnt = 0; + + /* Check */ + assert(NULL != cur_spice_model); + if (0 < cur_spice_model->num_port) { + assert(NULL != cur_spice_model->ports); + } + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + } + + for (iport = 0; iport < cur_spice_model->num_port; iport++) { + /* if this spice model requires customized netlist to be included, we do not go recursively */ + if (TRUE == recursive) { + /* GO recursively first, and meanwhile count the number of global ports */ + /* For the port that requires another spice_model, i.e., SRAM + * We need include any global port in that spice model + */ + if (NULL != cur_spice_model->ports[iport].spice_model) { + /* Check if we need to dump a comma */ + if (TRUE == dump_comma) { + fprintf(fp, ",\n"); + } + rec_dumped_port_cnt += + rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model->ports[iport].spice_model, + dump_port_type, recursive); + /* Decide if we need a comma */ + if (0 < rec_dumped_port_cnt) { + dump_comma = TRUE; + } + /* Update counter */ + dumped_port_cnt += rec_dumped_port_cnt; + continue; + } + } + /* By pass non-global ports*/ + if (FALSE == cur_spice_model->ports[iport].is_global) { + continue; + } + + /* We have some port to dump ! + * Print a comment line + */ + if (0 == dumped_port_cnt) { + fprintf(fp, "//----- BEGIN Global ports of SPICE_MODEL(%s) -----\n", + cur_spice_model->name); + } + + /* Check if we need to dump a comma */ + if (TRUE == dump_comma) { + fprintf(fp, ",\n"); + } + if (TRUE == dump_port_type) { + fprintf(fp, "%s [0:%d] %s", + verilog_convert_port_type_to_string(cur_spice_model->ports[iport].type), + cur_spice_model->ports[iport].size - 1, + cur_spice_model->ports[iport].prefix); + } else { + fprintf(fp, "%s[0:%d]", + cur_spice_model->ports[iport].prefix, + cur_spice_model->ports[iport].size - 1); + } + /* Decide if we need a comma */ + dump_comma = TRUE; + /* Update counter */ + dumped_port_cnt++; + } + + + /* We have dumped some port! + * Print another comment line + */ + if (0 < dumped_port_cnt) { + fprintf(fp, "\n"); + fprintf(fp, "//----- END Global ports of SPICE_MODEL(%s)-----\n", + cur_spice_model->name); + } + + return dumped_port_cnt; +} + +/* Dump all the global ports that are stored in the linked list */ +int dump_verilog_global_ports(FILE* fp, t_llist* head, + boolean dump_port_type) { + t_llist* temp = head; + t_spice_model_port* cur_global_port = NULL; + int dumped_port_cnt = 0; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + } + + fprintf(fp, "//----- BEGIN Global ports -----\n"); + while(NULL != temp) { + cur_global_port = (t_spice_model_port*)(temp->dptr); + if (TRUE == dump_port_type) { + fprintf(fp, "%s [0:%d] %s", + verilog_convert_port_type_to_string(cur_global_port->type), + cur_global_port->size - 1, + cur_global_port->prefix); + } else { + fprintf(fp, "%s[0:%d]", + cur_global_port->prefix, + cur_global_port->size - 1); + } + /* if this is the tail, we do not dump a comma */ + if (NULL != temp->next) { + fprintf(fp, ","); + } + fprintf(fp, "\n"); + /* Update counter */ + dumped_port_cnt++; + /* Go to the next */ + temp = temp->next; + } + fprintf(fp, "//----- END Global ports -----\n"); + + return dumped_port_cnt; +} + +/* Always dump the output ports of a SRAM in MUX */ +void dump_verilog_mux_sram_one_outport(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info, + t_spice_model* cur_mux_spice_model, int mux_size, + int sram_lsb, int sram_msb, + int port_type_index, + enum e_dump_verilog_port_type dump_port_type) { + t_spice_model* mem_model = NULL; + char* port_name = NULL; + char* port_full_name = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Get memory_model */ + get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); + + /* Keep the branch as it is, in case thing may become more complicated*/ + switch (cur_sram_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + if (0 == port_type_index) { + port_name = "out"; + } else { + assert(1 == port_type_index); + port_name = "outb"; + } + break; + case SPICE_SRAM_SCAN_CHAIN: + if (0 == port_type_index) { + port_name = "out"; + } else { + assert(1 == port_type_index); + port_name = "outb"; + } + break; + case SPICE_SRAM_MEMORY_BANK: + if (0 == port_type_index) { + port_name = "out"; + } else { + assert(1 == port_type_index); + port_name = "outb"; + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization !\n", + __FILE__, __LINE__); + exit(1); + } + + /*Malloc and generate the full name of port */ + port_full_name = (char*)my_malloc(sizeof(char)* + (strlen(cur_mux_spice_model->prefix) + 5 + + strlen(my_itoa(mux_size)) + 1 + + strlen(my_itoa(cur_mux_spice_model->cnt)) + 1 + + strlen(mem_model->prefix) + 1 + + strlen(port_name) + 1)); + sprintf(port_full_name, "%s_size%d_%d_%s_%s", + cur_mux_spice_model->prefix, mux_size, + cur_mux_spice_model->cnt, + mem_model->prefix, port_name); + + dump_verilog_generic_port(fp, dump_port_type, port_full_name, sram_lsb, sram_msb); + + /* Free */ + /* Local variables such as port1_name and port2 name are automatically freed */ + my_free(port_full_name); + + return; +} + + +/* Always dump the output ports of a SRAM */ +void dump_verilog_sram_one_outport(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info, + int sram_lsb, int sram_msb, + int port_type_index, + enum e_dump_verilog_port_type dump_port_type) { + t_spice_model* mem_model = NULL; + char* port_name = NULL; + char* port_full_name = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Get memory_model */ + get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); + + /* Keep the branch as it is, in case thing may become more complicated*/ + switch (cur_sram_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + if (0 == port_type_index) { + port_name = "out"; + } else { + assert(1 == port_type_index); + port_name = "outb"; + } + break; + case SPICE_SRAM_SCAN_CHAIN: + if (0 == port_type_index) { + port_name = "scff_out"; + } else { + assert(1 == port_type_index); + port_name = "scff_outb"; + } + break; + case SPICE_SRAM_MEMORY_BANK: + if (0 == port_type_index) { + port_name = "out"; + } else { + assert(1 == port_type_index); + port_name = "outb"; + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization !\n", + __FILE__, __LINE__); + exit(1); + } + + /*Malloc and generate the full name of port */ + port_full_name = (char*)my_malloc(sizeof(char)*(strlen(mem_model->prefix) + strlen(port_name) + 1 + 1)); + sprintf(port_full_name, "%s_%s", mem_model->prefix, port_name); + + dump_verilog_generic_port(fp, dump_port_type, port_full_name, sram_lsb, sram_msb); + + /* Free */ + /* Local variables such as port1_name and port2 name are automatically freed */ + my_free(port_full_name); + + return; +} + +/* Dump SRAM output ports, including two ports, out and outb */ +void dump_verilog_sram_outports(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info, + int sram_lsb, int sram_msb, + enum e_dump_verilog_port_type dump_port_type) { + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + if (0 > (sram_msb - sram_lsb)) { + return; + } + + if ((sram_lsb < 0)||(sram_msb < 0)) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid sram_lsb(%d) and sram_msb(%d)!\n", + __FILE__, __LINE__, sram_lsb, sram_msb); + return; + } + + /* Dump the first port: SRAM_out of CMOS MUX or BL of RRAM MUX */ + dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, + sram_lsb, sram_msb, + 0, dump_port_type); + fprintf(fp, ",\n"); + /* Dump the first port: SRAM_outb of CMOS MUX or WL of RRAM MUX */ + dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, + sram_lsb, sram_msb, + 1, dump_port_type); + + return; +} + +void dump_verilog_sram_one_port(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info, + int sram_lsb, int sram_msb, + int port_type_index, + enum e_dump_verilog_port_type dump_port_type) { + t_spice_model* mem_model = NULL; + char* port_name = NULL; + char* port_full_name = NULL; + enum e_dump_verilog_port_type actual_dump_port_type = dump_port_type; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Get memory_model */ + get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); + + switch (cur_sram_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + mem_model = cur_sram_orgz_info->standalone_sram_info->mem_model; + if (0 == port_type_index) { + port_name = "out"; + } else { + assert(1 == port_type_index); + port_name = "outb"; + } + break; + case SPICE_SRAM_SCAN_CHAIN: + mem_model = cur_sram_orgz_info->scff_info->mem_model; + if (0 == port_type_index) { + port_name = "scff_in"; + } else { + assert(1 == port_type_index); + port_name = "scff_out"; + /* Special case: scan-chain ff output should be an output always */ + if (VERILOG_PORT_INPUT == dump_port_type) { + actual_dump_port_type = VERILOG_PORT_OUTPUT; + } + } + break; + case SPICE_SRAM_MEMORY_BANK: + mem_model = cur_sram_orgz_info->mem_bank_info->mem_model; + if (0 == port_type_index) { + port_name = "bl"; + } else if (1 == port_type_index) { + port_name = "wl"; + /* Create inverted BL and WL signals */ + } else if (2 == port_type_index) { + port_name = "blb"; + } else if (3 == port_type_index) { + port_name = "wlb"; + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization !\n", + __FILE__, __LINE__); + exit(1); + } + + /*Malloc and generate the full name of port */ + port_full_name = (char*)my_malloc(sizeof(char)*(strlen(mem_model->prefix) + strlen(port_name) + 1 + 1)); + sprintf(port_full_name, "%s_%s", mem_model->prefix, port_name); + + dump_verilog_generic_port(fp, actual_dump_port_type, port_full_name, sram_lsb, sram_msb); + + /* Free */ + /* Local variables such as port1_name and port2 name are automatically freed */ + my_free(port_full_name); + + return; +} + +/* Dump SRAM ports, which is supposed to be the last port in the port list */ +void dump_verilog_sram_ports(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info, + int sram_lsb, int sram_msb, + enum e_dump_verilog_port_type dump_port_type) { + /* Need to dump inverted BL/WL if needed */ + int num_blb_ports, num_wlb_ports; + t_spice_model_port** blb_port = NULL; + t_spice_model_port** wlb_port = NULL; + t_spice_model* cur_sram_verilog_model = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + if (0 > (sram_msb - sram_lsb)) { + return; + } + + if ((sram_lsb < 0)||(sram_msb < 0)) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid sram_lsb(%d) and sram_msb(%d)!\n", + __FILE__, __LINE__, sram_lsb, sram_msb); + return; + } + + /* Dump the first port: SRAM_out of CMOS MUX or BL of RRAM MUX */ + dump_verilog_sram_one_port(fp, cur_sram_orgz_info, + sram_lsb, sram_msb, + 0, dump_port_type); + fprintf(fp, ",\n"); + /* Dump the first port: SRAM_outb of CMOS MUX or WL of RRAM MUX */ + dump_verilog_sram_one_port(fp, cur_sram_orgz_info, + sram_lsb, sram_msb, + 1, dump_port_type); + + /* Find the BLB and WLB port, if there is any */ + get_sram_orgz_info_mem_model(cur_sram_orgz_info, &cur_sram_verilog_model); + find_blb_wlb_ports_spice_model(cur_sram_verilog_model, + &num_blb_ports, &blb_port, &num_wlb_ports, &wlb_port); + /* BL inverted port */ + if (1 == num_blb_ports) { + fprintf(fp, ",\n"); + dump_verilog_sram_one_port(fp, cur_sram_orgz_info, + sram_lsb, sram_msb, + 2, dump_port_type); + } + /* WL inverted port */ + if (1 == num_wlb_ports) { + fprintf(fp, ",\n"); + dump_verilog_sram_one_port(fp, cur_sram_orgz_info, + sram_lsb, sram_msb, + 3, dump_port_type); + } + + return; +} + +void dump_verilog_reserved_sram_one_port(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info, + int sram_lsb, int sram_msb, + int port_type_index, + enum e_dump_verilog_port_type dump_port_type) { + t_spice_model* mem_model = NULL; + char* port_name = NULL; + char* port_full_name = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + switch (cur_sram_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + case SPICE_SRAM_SCAN_CHAIN: + return; + case SPICE_SRAM_MEMORY_BANK: + get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); + if (0 == port_type_index) { + port_name = "reserved_bl"; + } else { + assert(1 == port_type_index); + port_name = "reserved_wl"; + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization !\n", + __FILE__, __LINE__); + exit(1); + } + + /*Malloc and generate the full name of port */ + port_full_name = (char*)my_malloc(sizeof(char)*(strlen(mem_model->prefix) + strlen(port_name) + 1 + 1)); + sprintf(port_full_name, "%s_%s", mem_model->prefix, port_name); + + dump_verilog_generic_port(fp, dump_port_type, port_full_name, sram_lsb, sram_msb); + + /* Free */ + /* Local variables such as port1_name and port2 name are automatically freed */ + my_free(port_full_name); + + return; +} + + +/* Dump SRAM ports, which is supposed to be the last port in the port list */ +void dump_verilog_reserved_sram_ports(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info, + int sram_lsb, int sram_msb, + enum e_dump_verilog_port_type dump_port_type) { + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + if (0 > (sram_msb - sram_lsb)) { + return; + } + + /* Dump the first port: SRAM_out of CMOS MUX or BL of RRAM MUX */ + + if ((sram_lsb < 0)||(sram_msb < 0)) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid sram_lsb(%d) and sram_msb(%d)!\n", + __FILE__, __LINE__, sram_lsb, sram_msb); + return; + } + + dump_verilog_reserved_sram_one_port(fp, cur_sram_orgz_info, + sram_lsb, sram_msb, + 0, dump_port_type); + fprintf(fp, ",\n"); + /* Dump the first port: SRAM_outb of CMOS MUX or WL of RRAM MUX */ + dump_verilog_reserved_sram_one_port(fp, cur_sram_orgz_info, + sram_lsb, sram_msb, + 1, dump_port_type); + + return; +} + +/* Dump a verilog submodule of SRAMs in MUX, according to SRAM organization type */ +void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, + t_spice_model* cur_mux_verilog_model, int mux_size, + t_spice_model* cur_sram_verilog_model) { + int cur_bl, cur_wl, cur_num_sram; + int num_bl_ports, num_wl_ports; + t_spice_model_port** bl_port = NULL; + t_spice_model_port** wl_port = NULL; + int num_blb_ports, num_wlb_ports; + t_spice_model_port** blb_port = NULL; + t_spice_model_port** wlb_port = NULL; + + int num_bl_per_sram = 0; + int num_wl_per_sram = 0; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + assert(NULL != cur_sram_orgz_info); + assert(NULL != cur_sram_verilog_model); + assert((SPICE_MODEL_SRAM == cur_sram_verilog_model->type) + || (SPICE_MODEL_SCFF == cur_sram_verilog_model->type)); + + /* Get current index of SRAM module */ + cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); + + switch (cur_sram_orgz_info->type) { + case SPICE_SRAM_MEMORY_BANK: + /* Detect the SRAM SPICE model linked to this SRAM port */ + find_bl_wl_ports_spice_model(cur_sram_verilog_model, + &num_bl_ports, &bl_port, &num_wl_ports, &wl_port); + assert(1 == num_bl_ports); + assert(1 == num_wl_ports); + num_bl_per_sram = bl_port[0]->size; + num_wl_per_sram = wl_port[0]->size; + /* Find the BLB and WLB port, if there is any */ + find_blb_wlb_ports_spice_model(cur_sram_verilog_model, + &num_blb_ports, &blb_port, &num_wlb_ports, &wlb_port); + if (1 == num_blb_ports) { + assert(num_bl_per_sram == blb_port[0]->size); + } else { + assert(0 == num_blb_ports); + } + if (1 == num_wlb_ports) { + assert(num_wl_per_sram == wlb_port[0]->size); + } else { + assert(0 == num_wlb_ports); + } + + /* SRAM subckts*/ + fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, + cur_sram_verilog_model->cnt); + /* Only dump the global ports belonging to a spice_model */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE)) { + fprintf(fp, ",\n"); + } + dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, + cur_mux_verilog_model, mux_size, + cur_num_sram, cur_num_sram, + 0, VERILOG_PORT_CONKT); + fprintf(fp, ","); + dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, + cur_mux_verilog_model, mux_size, + cur_num_sram, cur_num_sram, + 0, VERILOG_PORT_CONKT); + fprintf(fp, ","); + dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, + cur_mux_verilog_model, mux_size, + cur_num_sram, cur_num_sram, + 1, VERILOG_PORT_CONKT); + fprintf(fp, ","); + get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_bl, &cur_wl); + /* Connect to Bit lines and Word lines, consider each conf_bit */ + fprintf(fp, "%s_size%d_%d_configbus0[%d:%d], ", + cur_mux_verilog_model->prefix, mux_size, cur_mux_verilog_model->cnt, + cur_num_sram, cur_num_sram + num_bl_per_sram - 1); + fprintf(fp, "%s_size%d_%d_configbus1[%d:%d] ", + cur_mux_verilog_model->prefix, mux_size, cur_mux_verilog_model->cnt, + cur_num_sram, cur_num_sram + num_wl_per_sram - 1); /* Outputs */ + /* If we have a BLB or WLB, we need to dump inverted config_bus */ + if (1 == num_blb_ports) { + fprintf(fp, ", "); + fprintf(fp, "%s_size%d_%d_configbus0_b[%d:%d] ", + cur_mux_verilog_model->prefix, mux_size, cur_mux_verilog_model->cnt, + cur_num_sram, cur_num_sram + num_bl_per_sram - 1); + } + if (1 == num_wlb_ports) { + fprintf(fp, ", "); + fprintf(fp, "%s_size%d_%d_configbus1_b[%d:%d] ", + cur_mux_verilog_model->prefix, mux_size, cur_mux_verilog_model->cnt, + cur_num_sram, cur_num_sram + num_wl_per_sram - 1); + } + + fprintf(fp, ");\n"); // + /* Update the counter */ + update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, + cur_num_sram + 1); + update_sram_orgz_info_num_blwl(cur_sram_orgz_info, + cur_bl + 1, + cur_wl + 1); + break; + case SPICE_SRAM_STANDALONE: + /* SRAM subckts*/ + fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, + cur_sram_verilog_model->cnt); + /* Only dump the global ports belonging to a spice_model */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "%s_out[%d], ", cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Input*/ + fprintf(fp, "%s_out[%d], %s_outb[%d] ", + cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt, + cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Outputs */ + fprintf(fp, ");\n"); // + /* Update the counter */ + update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, + cur_num_sram + 1); + break; + case SPICE_SRAM_SCAN_CHAIN: + /* Add a scan-chain DFF module here ! */ + fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, + cur_sram_verilog_model->cnt); + /* Only dump the global ports belonging to a spice_model */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE)) { + fprintf(fp, ",\n"); + } + /* Input of Scan-chain DFF, should be connected to the output of its precedent */ + dump_verilog_sram_one_port(fp, cur_sram_orgz_info, + cur_num_sram, + cur_num_sram, + 0, VERILOG_PORT_CONKT); + fprintf(fp, ", \n"); // + /* Output of Scan-chain DFF, should be connected to the output of its successor */ + dump_verilog_sram_one_port(fp, cur_sram_orgz_info, + cur_num_sram, + cur_num_sram, + 1, VERILOG_PORT_CONKT); + fprintf(fp, ", \n"); // + /* Memory outputs of Scan-chain DFF, should be connected to the SRAM(memory port) of IOPAD, MUX and LUT */ + dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, + cur_mux_verilog_model, mux_size, + cur_num_sram, + cur_num_sram, + 1, VERILOG_PORT_CONKT); + fprintf(fp, ");\n"); // + /* Update the counter */ + update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, + cur_num_sram + 1); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid SRAM organization type!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Update the counter */ + cur_sram_verilog_model->cnt++; + + return; +} + + + +/* Dump a verilog submodule of SRAM, according to SRAM organization type */ +void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, + t_spice_model* cur_sram_verilog_model) { + int cur_bl, cur_wl, cur_num_sram; + int num_bl_ports, num_wl_ports; + t_spice_model_port** bl_port = NULL; + t_spice_model_port** wl_port = NULL; + int num_blb_ports, num_wlb_ports; + t_spice_model_port** blb_port = NULL; + t_spice_model_port** wlb_port = NULL; + + int num_bl_per_sram = 0; + int num_wl_per_sram = 0; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + assert(NULL != cur_sram_orgz_info); + assert(NULL != cur_sram_verilog_model); + assert((SPICE_MODEL_SRAM == cur_sram_verilog_model->type) + || (SPICE_MODEL_SCFF == cur_sram_verilog_model->type)); + + /* Get current index of SRAM module */ + cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); + + switch (cur_sram_orgz_info->type) { + case SPICE_SRAM_MEMORY_BANK: + /* Detect the SRAM SPICE model linked to this SRAM port */ + find_bl_wl_ports_spice_model(cur_sram_verilog_model, + &num_bl_ports, &bl_port, &num_wl_ports, &wl_port); + assert(1 == num_bl_ports); + assert(1 == num_wl_ports); + num_bl_per_sram = bl_port[0]->size; + num_wl_per_sram = wl_port[0]->size; + /* Find the BLB and WLB port, if there is any */ + find_blb_wlb_ports_spice_model(cur_sram_verilog_model, + &num_blb_ports, &blb_port, &num_wlb_ports, &wlb_port); + if (1 == num_blb_ports) { + assert(num_bl_per_sram == blb_port[0]->size); + } else { + assert(0 == num_blb_ports); + } + if (1 == num_wlb_ports) { + assert(num_wl_per_sram == wlb_port[0]->size); + } else { + assert(0 == num_wlb_ports); + } + + /* SRAM subckts*/ + fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, + cur_sram_verilog_model->cnt); + /* Only dump the global ports belonging to a spice_model */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "%s_out[%d], ", cur_sram_verilog_model->prefix, cur_num_sram); /* Input*/ + fprintf(fp, "%s_out[%d], %s_outb[%d], ", + cur_sram_verilog_model->prefix, cur_num_sram, + cur_sram_verilog_model->prefix, cur_num_sram); /* Outputs */ + get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_bl, &cur_wl); + /* Connect to Bit lines and Word lines, consider each conf_bit */ + fprintf(fp, "%s_%d_configbus0[%d:%d], ", + cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt, + cur_bl, cur_bl + num_bl_per_sram - 1); + fprintf(fp, "%s_%d_configbus1[%d:%d] ", + cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt, + cur_wl, cur_wl + num_wl_per_sram - 1); /* Outputs */ + if (1 == num_blb_ports) { + fprintf(fp, ", "); + fprintf(fp, "%s_%d_configbus0_b[%d:%d] ", + cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt, + cur_bl, cur_bl + num_bl_per_sram - 1); + } + if (1 == num_wlb_ports) { + fprintf(fp, ", "); + fprintf(fp, "%s_%d_configbus1_b[%d:%d] ", + cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt, + cur_wl, cur_wl + num_wl_per_sram - 1); /* Outputs */ + } + fprintf(fp, ");\n"); // + /* Update the counter */ + update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, + cur_num_sram + 1); + update_sram_orgz_info_num_blwl(cur_sram_orgz_info, + cur_bl + 1, + cur_wl + 1); + break; + case SPICE_SRAM_STANDALONE: + /* SRAM subckts*/ + fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, + cur_sram_verilog_model->cnt); + /* Only dump the global ports belonging to a spice_model */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "%s_out[%d], ", cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Input*/ + fprintf(fp, "%s_out[%d], %s_outb[%d] ", + cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt, + cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Outputs */ + fprintf(fp, ");\n"); // + /* Update the counter */ + update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, + cur_num_sram + 1); + break; + case SPICE_SRAM_SCAN_CHAIN: + /* Add a scan-chain DFF module here ! */ + fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, + cur_sram_verilog_model->cnt); + /* Only dump the global ports belonging to a spice_model */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE)) { + fprintf(fp, ",\n"); + } + /* Input of Scan-chain DFF, should be connected to the output of its precedent */ + dump_verilog_sram_one_port(fp, cur_sram_orgz_info, + cur_num_sram, + cur_num_sram, + 0, VERILOG_PORT_CONKT); + fprintf(fp, ", \n"); // + /* Output of Scan-chain DFF, should be connected to the output of its successor */ + dump_verilog_sram_one_port(fp, cur_sram_orgz_info, + cur_num_sram, + cur_num_sram, + 1, VERILOG_PORT_CONKT); + fprintf(fp, ", \n"); // + /* Memory outputs of Scan-chain DFF, should be connected to the SRAM(memory port) of IOPAD, MUX and LUT */ + dump_verilog_sram_one_outport(fp, + cur_sram_orgz_info, + cur_num_sram, cur_num_sram, + 1, VERILOG_PORT_CONKT); + fprintf(fp, ");\n"); // + /* Update the counter */ + update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, + cur_num_sram + 1); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid SRAM organization type!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Update the counter */ + cur_sram_verilog_model->cnt++; + + return; +} + +void dump_verilog_scff_config_bus(FILE* fp, + t_spice_model* mem_spice_model, + t_sram_orgz_info* cur_sram_orgz_info, + int lsb, int msb, + enum e_dump_verilog_port_type dump_port_type) { + char* port_full_name = NULL; + + /* Check */ + assert(NULL != mem_spice_model); + assert(SPICE_MODEL_SCFF == mem_spice_model->type); + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /*Malloc and generate the full name of port */ + port_full_name = (char*)my_malloc(sizeof(char)* + ( strlen(mem_spice_model->prefix) + 1 + + strlen(my_itoa(mem_spice_model->cnt)) + 12 + 1)); + sprintf(port_full_name, "%s_%d_config_bus0", mem_spice_model->prefix, mem_spice_model->cnt); + + dump_verilog_generic_port(fp, dump_port_type, port_full_name, lsb, msb); + + /* Free */ + /* Local variables such as port1_name and port2 name are automatically freed */ + my_free(port_full_name); + + return; +} + +/* Dump MUX reserved and normal configuration wire bus */ +void dump_verilog_mem_config_bus(FILE* fp, t_spice_model* mem_spice_model, + t_sram_orgz_info* cur_sram_orgz_info, + int cur_num_sram, + int num_mem_reserved_conf_bits, + int num_mem_conf_bits) { + int num_blb_ports, num_wlb_ports; + t_spice_model_port** blb_port = NULL; + t_spice_model_port** wlb_port = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert(NULL != mem_spice_model); + assert((SPICE_MODEL_SRAM == mem_spice_model->type) + || (SPICE_MODEL_SCFF == mem_spice_model->type)); + + /* Depend on the style of configuraion circuit */ + switch (cur_sram_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + break; + case SPICE_SRAM_SCAN_CHAIN: + /* We do not need any configuration bus + * Scan-chain FF outputs are directly wired to SRAM inputs of MUXes + dump_verilog_scff_config_bus(fp, mem_spice_model, + cur_sram_orgz_info, + cur_num_sram, cur_num_sram + num_mem_conf_bits - 1, + VERILOG_PORT_WIRE); + fprintf(fp, ";\n"); + */ + break; + case SPICE_SRAM_MEMORY_BANK: + /* Find the BLB and WLB port, if there is any */ + find_blb_wlb_ports_spice_model(mem_spice_model, + &num_blb_ports, &blb_port, &num_wlb_ports, &wlb_port); + /* configuration wire bus */ + if (0 < (num_mem_reserved_conf_bits + num_mem_conf_bits)) { + /* First bus is for sram_out in CMOS MUX or BL in RRAM MUX */ + fprintf(fp, "wire [%d:%d] %s_%d_configbus0;\n", + cur_num_sram, + cur_num_sram + num_mem_reserved_conf_bits + num_mem_conf_bits - 1, + mem_spice_model->prefix, mem_spice_model->cnt); + /* Second bus is for sram_out_inv in CMOS MUX or WL in RRAM MUX */ + fprintf(fp, "wire [%d:%d] %s_%d_configbus1;\n", + cur_num_sram, + cur_num_sram + num_mem_reserved_conf_bits + num_mem_conf_bits - 1, + mem_spice_model->prefix, mem_spice_model->cnt); + if (1 == num_blb_ports) { + fprintf(fp, "wire [%d:%d] %s_%d_configbus0_b;\n", + cur_num_sram, + cur_num_sram + num_mem_reserved_conf_bits + num_mem_conf_bits - 1, + mem_spice_model->prefix, mem_spice_model->cnt); + } + if (1 == num_wlb_ports) { + fprintf(fp, "wire [%d:%d] %s_%d_configbus1_b;\n", + cur_num_sram, + cur_num_sram + num_mem_reserved_conf_bits + num_mem_conf_bits - 1, + mem_spice_model->prefix, mem_spice_model->cnt); + } + } + /* Connect wires to config bus */ + /* reserved configuration bits */ + if (0 < num_mem_reserved_conf_bits) { + fprintf(fp, "assign %s_%d_configbus0[%d:%d] = ", + mem_spice_model->prefix, mem_spice_model->cnt, + cur_num_sram, + cur_num_sram + num_mem_reserved_conf_bits - 1); + dump_verilog_reserved_sram_one_port(fp, cur_sram_orgz_info, + 0, num_mem_reserved_conf_bits - 1, + 0, VERILOG_PORT_CONKT); + fprintf(fp, ";\n"); + fprintf(fp, "assign %s_%d_configbus1[%d:%d] = ", + mem_spice_model->prefix, mem_spice_model->cnt, + cur_num_sram, + cur_num_sram + num_mem_reserved_conf_bits - 1); + dump_verilog_reserved_sram_one_port(fp, cur_sram_orgz_info, + 0, num_mem_reserved_conf_bits - 1, + 1, VERILOG_PORT_CONKT); + fprintf(fp, ";\n"); + } + /* normal configuration bits */ + if (0 < num_mem_conf_bits) { + fprintf(fp, "assign %s_%d_configbus0[%d:%d] = ", + mem_spice_model->prefix, mem_spice_model->cnt, + cur_num_sram + num_mem_reserved_conf_bits, + cur_num_sram + num_mem_reserved_conf_bits + num_mem_conf_bits - 1); + dump_verilog_sram_one_port(fp, cur_sram_orgz_info, + cur_num_sram, cur_num_sram + num_mem_conf_bits - 1, + 0, VERILOG_PORT_CONKT); + fprintf(fp, ";\n"); + fprintf(fp, "assign %s_%d_configbus1[%d:%d] = ", + mem_spice_model->prefix, mem_spice_model->cnt, + cur_num_sram + num_mem_reserved_conf_bits, + cur_num_sram + num_mem_reserved_conf_bits + num_mem_conf_bits - 1); + dump_verilog_sram_one_port(fp, cur_sram_orgz_info, + cur_num_sram, cur_num_sram + num_mem_conf_bits - 1, + 1, VERILOG_PORT_CONKT); + fprintf(fp, ";\n"); + /* Dump inverted config_bus if needed */ + if (1 == num_blb_ports) { + fprintf(fp, "assign %s_%d_configbus0_b[%d:%d] = ", + mem_spice_model->prefix, mem_spice_model->cnt, + cur_num_sram + num_mem_reserved_conf_bits, + cur_num_sram + num_mem_reserved_conf_bits + num_mem_conf_bits - 1); + dump_verilog_sram_one_port(fp, cur_sram_orgz_info, + cur_num_sram, cur_num_sram + num_mem_conf_bits - 1, + 2, VERILOG_PORT_CONKT); + fprintf(fp, ";\n"); + } + if (1 == num_wlb_ports) { + fprintf(fp, "assign %s_%d_configbus1_b[%d:%d] = ", + mem_spice_model->prefix, mem_spice_model->cnt, + cur_num_sram + num_mem_reserved_conf_bits, + cur_num_sram + num_mem_reserved_conf_bits + num_mem_conf_bits - 1); + dump_verilog_sram_one_port(fp, cur_sram_orgz_info, + cur_num_sram, cur_num_sram + num_mem_conf_bits - 1, + 3, VERILOG_PORT_CONKT); + fprintf(fp, ";\n"); + } + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid SRAM organization type!\n", + __FILE__, __LINE__); + exit(1); + } + + return; +} + +/* Dump MUX reserved and normal configuration wire bus */ +void dump_verilog_cmos_mux_config_bus(FILE* fp, t_spice_model* mux_spice_model, + t_sram_orgz_info* cur_sram_orgz_info, + int mux_size, int cur_num_sram, + int num_mux_reserved_conf_bits, + int num_mux_conf_bits) { + int num_blb_ports, num_wlb_ports; + t_spice_model_port** blb_port = NULL; + t_spice_model_port** wlb_port = NULL; + t_spice_model* cur_sram_verilog_model = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert(NULL != mux_spice_model); + assert(SPICE_MODEL_MUX == mux_spice_model->type); + + switch(cur_sram_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + break; + case SPICE_SRAM_SCAN_CHAIN: + /* We do not need any configuration bus + * Scan-chain FF outputs are directly wired to SRAM inputs of MUXes + */ + dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, + mux_spice_model, mux_size, + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + 1, VERILOG_PORT_WIRE); + fprintf(fp, ";\n"); + break; + case SPICE_SRAM_MEMORY_BANK: + /* configuration wire bus */ + /* First bus is for sram_out in CMOS MUX */ + fprintf(fp, "wire [%d:%d] %s_size%d_%d_configbus0;\n", + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + mux_spice_model->prefix, mux_size, mux_spice_model->cnt); + /* Second bus is for sram_out_inv in CMOS MUX */ + fprintf(fp, "wire [%d:%d] %s_size%d_%d_configbus1;\n", + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + mux_spice_model->prefix, mux_size, mux_spice_model->cnt); + /* Declare output ports as wires */ + dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, + mux_spice_model, mux_size, + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + 0, VERILOG_PORT_WIRE); + fprintf(fp, ";\n"); + /* Declare output ports as wires */ + dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, + mux_spice_model, mux_size, + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + 1, VERILOG_PORT_WIRE); + fprintf(fp, ";\n"); + /* Connect wires to config bus */ + fprintf(fp, "assign %s_size%d_%d_configbus0[%d:%d] = ", + mux_spice_model->prefix, mux_size, mux_spice_model->cnt, + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1); + dump_verilog_sram_one_port(fp, cur_sram_orgz_info, + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + 0, VERILOG_PORT_CONKT); + fprintf(fp, ";\n"); + fprintf(fp, "assign %s_size%d_%d_configbus1[%d:%d] = ", + mux_spice_model->prefix, mux_size, mux_spice_model->cnt, + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1); + dump_verilog_sram_one_port(fp, cur_sram_orgz_info, + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + 1, VERILOG_PORT_CONKT); + fprintf(fp, ";\n"); + /* Find the BLB and WLB port, if there is any */ + get_sram_orgz_info_mem_model(cur_sram_orgz_info, &cur_sram_verilog_model); + find_blb_wlb_ports_spice_model(cur_sram_verilog_model, + &num_blb_ports, &blb_port, &num_wlb_ports, &wlb_port); + /* Dump inverted config_bus if needed */ + if (1 == num_blb_ports) { + fprintf(fp, "wire [%d:%d] %s_size%d_%d_configbus0_b;\n", + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + mux_spice_model->prefix, mux_size, mux_spice_model->cnt); + fprintf(fp, "assign %s_size%d_%d_configbus0_b[%d:%d] = ", + mux_spice_model->prefix, mux_size, mux_spice_model->cnt, + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1); + dump_verilog_sram_one_port(fp, cur_sram_orgz_info, + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + 2, VERILOG_PORT_CONKT); + fprintf(fp, ";\n"); + } + if (1 == num_wlb_ports) { + fprintf(fp, "wire [%d:%d] %s_size%d_%d_configbus1_b;\n", + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + mux_spice_model->prefix, mux_size, mux_spice_model->cnt); + fprintf(fp, "assign %s_size%d_%d_configbus1_b[%d:%d] = ", + mux_spice_model->prefix, mux_size, mux_spice_model->cnt, + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1); + dump_verilog_sram_one_port(fp, cur_sram_orgz_info, + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + 3, VERILOG_PORT_CONKT); + fprintf(fp, ";\n"); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } + return; + +} + +/* Dump MUX reserved and normal configuration wire bus */ +void dump_verilog_mux_config_bus(FILE* fp, t_spice_model* mux_spice_model, + t_sram_orgz_info* cur_sram_orgz_info, + int mux_size, int cur_num_sram, + int num_mux_reserved_conf_bits, + int num_mux_conf_bits) { + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert(NULL != mux_spice_model); + assert(SPICE_MODEL_MUX == mux_spice_model->type); + + /* depend on the design technology of this MUX: + * bus connections are different + * SRAM MUX: bus is connected to the output ports of SRAM + * RRAM MUX: bus is connected to the BL/WL of MUX + * TODO: Maybe things will become even more complicated, + * the bus connections may depend on the type of configuration circuit... + * Currently, this is fine. + */ + switch (mux_spice_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + dump_verilog_cmos_mux_config_bus(fp, mux_spice_model, cur_sram_orgz_info, + mux_size, cur_num_sram, + num_mux_reserved_conf_bits, num_mux_conf_bits); + break; + case SPICE_MODEL_DESIGN_RRAM: + /* configuration wire bus */ + /* First bus is for sram_out in CMOS MUX or BL in RRAM MUX */ + fprintf(fp, "wire [0:%d] %s_size%d_%d_configbus0;\n", + num_mux_reserved_conf_bits + num_mux_conf_bits - 1, + mux_spice_model->prefix, mux_size, mux_spice_model->cnt); + /* Second bus is for sram_out_inv in CMOS MUX or WL in RRAM MUX */ + fprintf(fp, "wire [0:%d] %s_size%d_%d_configbus1;\n", + num_mux_reserved_conf_bits + num_mux_conf_bits - 1, + mux_spice_model->prefix, mux_size, mux_spice_model->cnt); + /* Connect wires to config bus */ + /* reserved configuration bits */ + if (0 < num_mux_reserved_conf_bits) { + fprintf(fp, "assign %s_size%d_%d_configbus0[%d:%d] = ", + mux_spice_model->prefix, mux_size, mux_spice_model->cnt, + 0, num_mux_reserved_conf_bits - 1); + dump_verilog_reserved_sram_one_port(fp, cur_sram_orgz_info, + 0, num_mux_reserved_conf_bits - 1, + 0, VERILOG_PORT_CONKT); + fprintf(fp, ";\n"); + fprintf(fp, "assign %s_size%d_%d_configbus1[%d:%d] = ", + mux_spice_model->prefix, mux_size, mux_spice_model->cnt, + 0, num_mux_reserved_conf_bits - 1); + dump_verilog_reserved_sram_one_port(fp, cur_sram_orgz_info, + 0, num_mux_reserved_conf_bits - 1, + 1, VERILOG_PORT_CONKT); + fprintf(fp, ";\n"); + } + /* normal configuration bits */ + if (0 < num_mux_conf_bits) { + fprintf(fp, "assign %s_size%d_%d_configbus0[%d:%d] = ", + mux_spice_model->prefix, mux_size, mux_spice_model->cnt, + num_mux_reserved_conf_bits, + num_mux_reserved_conf_bits + num_mux_conf_bits - 1); + dump_verilog_sram_one_port(fp, cur_sram_orgz_info, + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + 0, VERILOG_PORT_CONKT); + fprintf(fp, ";\n"); + fprintf(fp, "assign %s_size%d_%d_configbus1[%d:%d] = ", + mux_spice_model->prefix, mux_size, mux_spice_model->cnt, + num_mux_reserved_conf_bits, + num_mux_reserved_conf_bits + num_mux_conf_bits - 1); + dump_verilog_sram_one_port(fp, cur_sram_orgz_info, + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + 1, VERILOG_PORT_CONKT); + fprintf(fp, ";\n"); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology for SRAM!\n", + __FILE__, __LINE__); + exit(1); + } + + return; +} + +/* Dump CMOS verilog MUX configuraiton bus ports */ +void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model, + t_sram_orgz_info* cur_sram_orgz_info, + int mux_size, int cur_num_sram, + int num_mux_reserved_conf_bits, + int num_mux_conf_bits) { + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert(NULL != mux_spice_model); + assert(SPICE_MODEL_MUX == mux_spice_model->type); + + switch(cur_sram_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + break; + case SPICE_SRAM_SCAN_CHAIN: + /* configuration wire bus */ + /* FOR Scan-chain, we need regular output of a scan-chain FF + * We do not need a prefix implying MUX name, size and index + */ + dump_verilog_sram_one_port(fp, cur_sram_orgz_info, + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + 1, VERILOG_PORT_CONKT); + fprintf(fp, ",\n"); + dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, + mux_spice_model, mux_size, + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + 1, VERILOG_PORT_CONKT); + break; + case SPICE_SRAM_MEMORY_BANK: + /* configuration wire bus */ + /* First bus is for sram_out in CMOS MUX + * We need a prefix implying MUX name, size and index + */ + dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, + mux_spice_model, mux_size, + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + 0, VERILOG_PORT_CONKT); + fprintf(fp, ",\n"); + dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, + mux_spice_model, mux_size, + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + 1, VERILOG_PORT_CONKT); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } + return; +} + + +/* Dump MUX reserved and normal configuration wire bus */ +void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model, + t_sram_orgz_info* cur_sram_orgz_info, + int mux_size, int cur_num_sram, + int num_mux_reserved_conf_bits, + int num_mux_conf_bits) { + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Check */ + assert(NULL != mux_spice_model); + assert(SPICE_MODEL_MUX == mux_spice_model->type); + + /* depend on the design technology of this MUX: + * bus connections are different + * SRAM MUX: bus is connected to the output ports of SRAM + */ + switch (mux_spice_model->design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + dump_verilog_cmos_mux_config_bus_ports(fp, mux_spice_model, cur_sram_orgz_info, + mux_size, cur_num_sram, + num_mux_reserved_conf_bits, num_mux_conf_bits); + break; + case SPICE_MODEL_DESIGN_RRAM: + /* configuration wire bus */ + fprintf(fp, "%s_size%d_%d_configbus0, ", + mux_spice_model->prefix, mux_size, mux_spice_model->cnt); + + fprintf(fp, "%s_size%d_%d_configbus1 ", + mux_spice_model->prefix, mux_size, mux_spice_model->cnt); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology for SRAM!\n", + __FILE__, __LINE__); + exit(1); + } + + return; +} + + +/* Dump common ports of each pb_type in physical mode, + * common ports include: + * 1. inpad; 2. outpad; 3. iopad; TODO: merge other two to iopad + * 4. SRAMs (standalone) + * 5. BL/WLs + * 6. Scan-chain FFs + */ +void dump_verilog_grid_common_port(FILE* fp, t_spice_model* cur_verilog_model, + char* general_port_prefix, int lsb, int msb, + enum e_dump_verilog_port_type dump_port_type) { + char* port_full_name = NULL; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + assert(NULL != cur_verilog_model); + if (0 > msb- lsb) { + return; + } + + /*Malloc and generate the full name of port */ + port_full_name = (char*)my_malloc(sizeof(char)*(strlen(general_port_prefix) + strlen(cur_verilog_model->prefix) + 1)); + sprintf(port_full_name, "%s%s", general_port_prefix, cur_verilog_model->prefix); + + fprintf(fp, ",\n"); + dump_verilog_generic_port(fp, dump_port_type, port_full_name, msb, lsb); + + /* Free */ + /* Local variables such as port1_name and port2 name are automatically freed */ + my_free(port_full_name); + + return; +} + +/* A widely used function to dump the configuration bus + * This is supposed to be called when declaring local wires in the main body of a module + * We will the internal wires (bus) used for connect SRAMs/RRAMs to other modules, + * such as LUTs, MUXes and IOs + */ +void dump_verilog_sram_config_bus_internal_wires(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, + int lsb, int msb) { + t_spice_model* mem_model = NULL; + + /* Get the memory spice model*/ + get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); + assert (NULL != mem_model); + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Depend on the configuraion style */ + switch(cur_sram_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + break; + case SPICE_SRAM_SCAN_CHAIN: + dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, lsb, msb, 1, VERILOG_PORT_WIRE); + fprintf(fp, ";\n"); + break; + case SPICE_SRAM_MEMORY_BANK: + dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, lsb, msb, 0, VERILOG_PORT_WIRE); + fprintf(fp, ";\n"); + dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, lsb, msb, 1, VERILOG_PORT_WIRE); + fprintf(fp, ";\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } + + return; +} + diff --git a/vpr7_rram/vpr/SRC/syn_verilog/verilog_utils.h b/vpr7_rram/vpr/SRC/syn_verilog/verilog_utils.h new file mode 100644 index 000000000..901abfffe --- /dev/null +++ b/vpr7_rram/vpr/SRC/syn_verilog/verilog_utils.h @@ -0,0 +1,140 @@ + + +void init_list_include_verilog_netlists(t_spice* spice); + +void init_include_user_defined_verilog_netlists(t_spice spice); + +void dump_include_user_defined_verilog_netlists(FILE* fp, + t_spice spice); + +void dump_verilog_file_header(FILE* fp, + char* usage); + +char determine_verilog_generic_port_split_sign(enum e_dump_verilog_port_type dump_port_type); + +void dump_verilog_generic_port(FILE* fp, + enum e_dump_verilog_port_type dump_port_type, + char* port_name, int port_lsb, int port_msb); + +void decode_verilog_memory_bank_sram(t_spice_model* cur_sram_spice_model, int sram_bit, + int bl_len, int wl_len, int bl_offset, int wl_offset, + int* bl_conf_bits, int* wl_conf_bits); + +void +decode_and_add_verilog_sram_membank_conf_bit_to_llist(t_sram_orgz_info* cur_sram_orgz_info, + int mem_index, + int num_bl_per_sram, int num_wl_per_sram, + int cur_sram_bit); + + +void decode_verilog_one_level_4t1r_mux(int path_id, + int bit_len, int* conf_bits); + +void decode_verilog_rram_mux(t_spice_model* mux_spice_model, + int mux_size, int path_id, + int* bit_len, int** conf_bits, int* mux_level); + +int determine_decoder_size(int num_addr_out); + +char* chomp_verilog_node_prefix(char* verilog_node_prefix); + +char* format_verilog_node_prefix(char* verilog_node_prefix); + +char* verilog_convert_port_type_to_string(enum e_spice_model_port_type port_type); + +int rec_dump_verilog_spice_model_global_ports(FILE* fp, + t_spice_model* cur_spice_model, + boolean dump_port_type, + boolean recursive); + +int dump_verilog_global_ports(FILE* fp, t_llist* head, + boolean dump_port_type); + +void dump_verilog_mux_sram_one_outport(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info, + t_spice_model* cur_mux_spice_model, int mux_size, + int sram_lsb, int sram_msb, + int port_type_index, + enum e_dump_verilog_port_type dump_port_type); + +void dump_verilog_sram_one_outport(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info, + int sram_lsb, int sram_msb, + int port_type_index, + enum e_dump_verilog_port_type dump_port_type); + +void dump_verilog_sram_outports(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info, + int sram_lsb, int sram_msb, + enum e_dump_verilog_port_type dump_port_type); + +void dump_verilog_sram_one_port(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info, + int sram_lsb, int sram_msb, + int port_type_index, + enum e_dump_verilog_port_type dump_port_type); + +void dump_verilog_sram_ports(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, + int sram_lsb, int sram_msb, + enum e_dump_verilog_port_type dump_port_type); + +void dump_verilog_reserved_sram_one_port(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info, + int sram_lsb, int sram_msb, + int port_type_index, + enum e_dump_verilog_port_type dump_port_type); + +void dump_verilog_reserved_sram_ports(FILE* fp, + t_sram_orgz_info* cur_sram_orgz_info, + int sram_lsb, int sram_msb, + enum e_dump_verilog_port_type dump_port_type); + +void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, + t_spice_model* cur_mux_verilog_model, int mux_size, + t_spice_model* cur_sram_verilog_model); + +void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, + t_spice_model* sram_verilog_model); + +void dump_verilog_scff_config_bus(FILE* fp, + t_spice_model* mem_spice_model, + t_sram_orgz_info* cur_sram_orgz_info, + int lsb, int msb, + enum e_dump_verilog_port_type dump_port_type); + +void dump_verilog_mem_config_bus(FILE* fp, t_spice_model* mem_spice_model, + t_sram_orgz_info* cur_sram_orgz_info, + int cur_num_sram, + int num_mem_reserved_conf_bits, + int num_mem_conf_bits); + +void dump_verilog_cmos_mux_config_bus(FILE* fp, t_spice_model* mux_spice_model, + t_sram_orgz_info* cur_sram_orgz_info, + int mux_size, int cur_num_sram, + int num_mux_reserved_conf_bits, + int num_mux_conf_bits); + +void dump_verilog_mux_config_bus(FILE* fp, t_spice_model* mux_spice_model, + t_sram_orgz_info* cur_sram_orgz_info, + int mux_size, int cur_num_sram, + int num_mux_reserved_conf_bits, + int num_mux_conf_bits); + +void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model, + t_sram_orgz_info* cur_sram_orgz_info, + int mux_size, int cur_num_sram, + int num_mux_reserved_conf_bits, + int num_mux_conf_bits); + +void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model, + t_sram_orgz_info* cur_sram_orgz_info, + int mux_size, int cur_num_sram, + int num_mux_reserved_conf_bits, + int num_mux_conf_bits); + +void dump_verilog_grid_common_port(FILE* fp, t_spice_model* cur_verilog_model, + char* general_port_prefix, int lsb, int msb, + enum e_dump_verilog_port_type dump_port_type); + +void dump_verilog_sram_config_bus_internal_wires(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, + int lsb, int msb); diff --git a/vpr7_rram/vpr/SRC/tags b/vpr7_rram/vpr/SRC/tags new file mode 100644 index 000000000..e8d1bf24d --- /dev/null +++ b/vpr7_rram/vpr/SRC/tags @@ -0,0 +1,5087 @@ +!_TAG_FILE_FORMAT 2 /extended format; --format=1 will not append ;" to lines/ +!_TAG_FILE_SORTED 1 /0=unsorted, 1=sorted, 2=foldcase/ +!_TAG_PROGRAM_AUTHOR Darren Hiebert /dhiebert@users.sourceforge.net/ +!_TAG_PROGRAM_NAME Exuberant Ctags // +!_TAG_PROGRAM_URL http://ctags.sourceforge.net /official site/ +!_TAG_PROGRAM_VERSION 5.8 // +AAPACK_MAX_FEASIBLE_BLOCK_ARRAY_SIZE pack/cluster.c 35;" d file: +AAPACK_MAX_HIGH_FANOUT_EXPLORE pack/cluster.c 37;" d file: +AAPACK_MAX_NET_SINKS_IGNORE pack/cluster.c 36;" d file: +AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST pack/cluster.c 33;" d file: +AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC pack/cluster.c 32;" d file: +ABORTED place/place.c /^ REJECTED, ACCEPTED, ABORTED$/;" e enum:swap_result file: +ABSOLUTE ../../libarchfpga/include/physical_types.h /^ ABSOLUTE, FRACTIONAL$/;" e enum:e_Fc_type +ABS_DIFF place/place_stats.c 7;" d file: +ACCEPTED place/place.c /^ REJECTED, ACCEPTED, ABORTED$/;" e enum:swap_result file: +ALLOW_SWITCH_OFF route/rr_graph2.c 16;" d file: +ALL_NETS base/draw.c /^ ALL_NETS, HIGHLIGHTED$/;" e enum:e_draw_net_type file: +ANY timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: +ANYBUT timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: +ANYOF timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: +ARCH_TYPES_H ../../libarchfpga/include/arch_types.h 9;" d +AUTO_SCHED base/vpr_types.h /^ AUTO_SCHED, USER_SCHED$/;" e enum:sched_type +ActFile base/ReadOptions.h /^ char *ActFile;$/;" m struct:s_options +ActFile base/vpr_types.h /^ char *ActFile;$/;" m struct:s_file_name_opts +AnnealSched base/vpr_types.h /^ struct s_annealing_sched AnnealSched; \/* Placement option annealing schedule *\/$/;" m struct:s_vpr_setup typeref:struct:s_vpr_setup::s_annealing_sched +ArchFile base/ReadOptions.h /^ char *ArchFile;$/;" m struct:s_options +ArchFile base/vpr_types.h /^ char *ArchFile;$/;" m struct:s_file_name_opts +Aspect ../../libarchfpga/include/physical_types.h /^ float Aspect;$/;" m struct:s_clb_grid +BISQUE base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types +BI_DIRECTION base/vpr_types.h /^ INC_DIRECTION = 0, DEC_DIRECTION = 1, BI_DIRECTION = 2$/;" e enum:e_direction +BI_DIRECTIONAL ../../libarchfpga/include/physical_types.h /^ UNI_DIRECTIONAL, BI_DIRECTIONAL$/;" e enum:e_directionality +BLACK base/easygl_constants.h /^enum color_types {WHITE, BLACK, DARKGREY, LIGHTGREY, BLUE, GREEN, YELLOW,$/;" e enum:color_types +BLIF_TOKENS base/read_blif.c 235;" d file: +BLK_FAILED_FEASIBLE base/vpr_types.h /^ BLK_PASSED, BLK_FAILED_FEASIBLE, BLK_FAILED_ROUTE, BLK_STATUS_UNDEFINED$/;" e enum:e_block_pack_status +BLK_FAILED_ROUTE base/vpr_types.h /^ BLK_PASSED, BLK_FAILED_FEASIBLE, BLK_FAILED_ROUTE, BLK_STATUS_UNDEFINED$/;" e enum:e_block_pack_status +BLK_PASSED base/vpr_types.h /^ BLK_PASSED, BLK_FAILED_FEASIBLE, BLK_FAILED_ROUTE, BLK_STATUS_UNDEFINED$/;" e enum:e_block_pack_status +BLK_STATUS_UNDEFINED base/vpr_types.h /^ BLK_PASSED, BLK_FAILED_FEASIBLE, BLK_FAILED_ROUTE, BLK_STATUS_UNDEFINED$/;" e enum:e_block_pack_status +BLOCK_COUNT place/timing_place_lookup.c 52;" d file: +BLUE base/easygl_constants.h /^enum color_types {WHITE, BLACK, DARKGREY, LIGHTGREY, BLUE, GREEN, YELLOW,$/;" e enum:color_types +BOL timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: +BOTTOM ../../libarchfpga/include/physical_types.h /^ TOP = 0, RIGHT = 1, BOTTOM = 2, LEFT = 3$/;" e enum:e_side +BOUNDARY ../../libarchfpga/include/physical_types.h /^ BOUNDARY = 0, FILL, COL_REPEAT, COL_REL$/;" e enum:e_grid_loc_type +BOUNDING_BOX_PLACE base/vpr_types.h /^ BOUNDING_BOX_PLACE, NET_TIMING_DRIVEN_PLACE, PATH_TIMING_DRIVEN_PLACE$/;" e enum:e_place_algorithm +BRANCH timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: +BREADTH_FIRST base/vpr_types.h /^ BREADTH_FIRST, TIMING_DRIVEN, NO_TIMING$/;" e enum:e_router_algorithm +BUFFER_INSERTION_H mrfpga/buffer_insertion.h 2;" d +BUFSIZE ../../libarchfpga/include/util.h 23;" d +BUFSIZE base/graphics.c 184;" d file: +BUF_AND_PTRANS_FLAG route/check_rr_graph.c 16;" d file: +BUF_FLAG route/check_rr_graph.c 14;" d file: +BUTTON_POLY base/graphics.c /^ BUTTON_POLY,$/;" e enum:__anon3 file: +BUTTON_SEPARATOR base/graphics.c /^ BUTTON_SEPARATOR$/;" e enum:__anon3 file: +BUTTON_TEXT base/graphics.c /^ BUTTON_TEXT = 0,$/;" e enum:__anon3 file: +BUTTON_TEXT_LEN base/graphics.c 183;" d file: +BlifFile base/ReadOptions.h /^ char *BlifFile;$/;" m struct:s_options +BlifFile base/vpr_types.h /^ char *BlifFile;$/;" m struct:s_file_name_opts +ButtonsWND base/graphics.c /^ButtonsWND(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)$/;" f file: +C ../../libarchfpga/include/arch_types_mrfpga.h /^ float C; $/;" m struct:s_memristor_inf +C ../../libarchfpga/include/arch_types_mrfpga.h /^ float C;$/;" m struct:s_buffer_inf +C ../../libarchfpga/include/physical_types.h /^ float C;$/;" m union:s_port_power::__anon22 +C base/vpr_types.h /^ float C;$/;" m struct:s_rr_node +CAD_TYPES_H ../../libarchfpga/include/cad_types.h 5;" d +CAL_CAPACITANCE_H mrfpga/cal_capacitance.h 2;" d +CHANX base/vpr_types.h /^ SOURCE = 0, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_CLUSTER_EDGE, NUM_RR_TYPES$/;" e enum:e_rr_type +CHANX_COST_INDEX_START base/vpr_types.h /^ CHANX_COST_INDEX_START$/;" e enum:e_cost_indices +CHANY base/vpr_types.h /^ SOURCE = 0, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_CLUSTER_EDGE, NUM_RR_TYPES$/;" e enum:e_rr_type +CHECK place/place.c /^ NORMAL, CHECK$/;" e enum:cost_methods file: +CHECK_NETLIST_H base/check_netlist.h 2;" d +CHECK_RAND ../../libarchfpga/util.c 734;" d file: +CHECK_RR_GRAPH_H route/check_rr_graph.h 2;" d +CHUNK_SIZE ../../libarchfpga/util.c 208;" d file: +CLOCK_DENS power/power.h 37;" d +CLOCK_PROB power/power.h 36;" d +CLOSE timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: +CLUSTER_FEASIBILITY_CHECK_H pack/cluster_feasibility_filter.h 23;" d +CLUSTER_LEGALITY_H pack/cluster_legality.h 2;" d +CLUSTER_PLACEMENT_H pack/cluster_placement.h 7;" d +COL_REL ../../libarchfpga/include/physical_types.h /^ BOUNDARY = 0, FILL, COL_REPEAT, COL_REL$/;" e enum:e_grid_loc_type +COL_REPEAT ../../libarchfpga/include/physical_types.h /^ BOUNDARY = 0, FILL, COL_REPEAT, COL_REL$/;" e enum:e_grid_loc_type +COMPLETE_INTERC ../../libarchfpga/include/physical_types.h /^ COMPLETE_INTERC = 1, DIRECT_INTERC = 2, MUX_INTERC = 3$/;" e enum:e_interconnect +CONV ../../libarchfpga/include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp +CONVERT_NM_PER_M power/power.c 50;" d file: +CONVERT_UM_PER_M power/power.c 51;" d file: +CORAL base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types +CREATE_ERROR base/graphics.c 219;" d file: +CYAN base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types +C_d power/power.h /^ float C_d;$/;" m struct:s_transistor_size_inf +C_downstream mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan {t_linked_int* inode_head; t_linked_int* sink_head; float* sink_delay; float C_downstream; float Tdel;} t_buffer_plan;$/;" m struct:s_buffer_plan file: +C_downstream route/route_tree_timing.h /^ float C_downstream;$/;" m struct:s_rt_node +C_downstream timing/net_delay_types.h /^ float C_downstream;$/;" m struct:s_rc_node +C_g power/power.h /^ float C_g;$/;" m struct:s_transistor_size_inf +C_internal ../../libarchfpga/include/physical_types.h /^ float C_internal; \/*Internal capacitance of the pb *\/$/;" m struct:s_pb_type_power +C_ipin_cblock ../../libarchfpga/include/physical_types.h /^ float C_ipin_cblock;$/;" m struct:s_arch +C_ipin_cblock ../../libarchfpga/include/physical_types.h /^ float C_ipin_cblock;$/;" m struct:s_timing_inf +C_load base/vpr_types.h /^ float C_load;$/;" m struct:s_rr_indexed_data +C_s power/power.h /^ float C_s;$/;" m struct:s_transistor_size_inf +C_tile_per_m base/vpr_types.h /^ float C_tile_per_m;$/;" m struct:s_rr_indexed_data +C_wire ../../libarchfpga/include/physical_types.h /^ float C_wire; \/* Wire capacitance (per meter) *\/$/;" m struct:s_clock_network +C_wire ../../libarchfpga/include/physical_types.h /^ float C_wire;$/;" m struct:s_pb_graph_pin_power +C_wire_local ../../libarchfpga/include/physical_types.h /^ float C_wire_local; \/* Capacitance of local interconnect (per meter) *\/$/;" m struct:s_power_arch +Chans ../../libarchfpga/include/physical_types.h /^ t_chan_width_dist Chans;$/;" m struct:s_arch +CheckArch base/CheckArch.c /^void CheckArch(INP t_arch Arch, INP boolean TimingEnabled) {$/;" f +CheckElement ../../libarchfpga/read_xml_util.c /^void CheckElement(INP ezxml_t Node, INP const char *Name) {$/;" f +CheckGrid base/SetupGrid.c /^static void CheckGrid() {$/;" f file: +CheckOptions base/CheckOptions.c /^void CheckOptions(INP t_options Options, INP boolean TimingEnabled) {$/;" f +CheckSegments base/CheckArch.c /^static void CheckSegments(INP t_arch Arch) {$/;" f file: +CheckSetup base/CheckSetup.c /^void CheckSetup(INP enum e_operation Operation,$/;" f +CheckSwitches base/CheckArch.c /^static void CheckSwitches(INP t_arch Arch, INP boolean TimingEnabled) {$/;" f file: +Cin ../../libarchfpga/include/physical_types.h /^ float Cin;$/;" m struct:s_switch_inf +CircuitName base/ReadOptions.h /^ char *CircuitName;$/;" m struct:s_options +CircuitName base/vpr_types.h /^ char *CircuitName;$/;" m struct:s_file_name_opts +Cmetal ../../libarchfpga/include/physical_types.h /^ float Cmetal;$/;" m struct:s_segment_inf +Cmetal base/vpr_types.h /^ float Cmetal;$/;" m struct:s_seg_details +Cmetal_per_m base/vpr_types.h /^ float Cmetal_per_m; \/* Used for power *\/$/;" m struct:s_seg_details +CmosTechFile base/ReadOptions.h /^ char *CmosTechFile;$/;" m struct:s_options +CmosTechFile base/vpr_types.h /^ char *CmosTechFile;$/;" m struct:s_file_name_opts +Count base/ReadOptions.h /^ int Count[OT_BASE_UNKNOWN];$/;" m struct:s_options +CountChildren ../../libarchfpga/read_xml_util.c /^extern int CountChildren(INP ezxml_t Node, INP const char *Name,$/;" f +CountTokens ../../libarchfpga/ReadLine.c /^int CountTokens(INP char **Tokens) {$/;" f +CountTokensInString ../../libarchfpga/read_xml_util.c /^extern void CountTokensInString(INP const char *Str, OUTP int *Num,$/;" f +Cout ../../libarchfpga/include/physical_types.h /^ float Cout;$/;" m struct:s_switch_inf +CreateEchoFile base/ReadOptions.h /^ boolean CreateEchoFile;$/;" m struct:s_options +CreateModelLibrary ../../libarchfpga/read_xml_arch_file.c /^static void CreateModelLibrary(OUTP struct s_arch *arch) {$/;" f file: +Cseg_global ../../libarchfpga/include/arch_types_mrfpga.h /^ float Cseg_global;$/;" m struct:s_arch_mrfpga +Cseg_global mrfpga/mrfpga_globals.c /^float Rseg_global, Cseg_global;$/;" v +DARKGREEN base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types +DARKGREY base/easygl_constants.h /^enum color_types {WHITE, BLACK, DARKGREY, LIGHTGREY, BLUE, GREEN, YELLOW,$/;" e enum:color_types +DARKKHAKI base/easygl_constants.h /^TURQUOISE, MEDIUMPURPLE, DARKSLATEBLUE, DARKKHAKI, NUM_COLOR};$/;" e enum:color_types +DARKSLATEBLUE base/easygl_constants.h /^TURQUOISE, MEDIUMPURPLE, DARKSLATEBLUE, DARKKHAKI, NUM_COLOR};$/;" e enum:color_types +DASHED base/easygl_constants.h /^enum line_types {SOLID, DASHED};$/;" e enum:line_types +DEBUG base/vpr_types.h 46;" d +DEBUG_TIMING_PLACE_LOOKUP place/timing_place_lookup.c 61;" d file: +DEC_DIRECTION base/vpr_types.h /^ INC_DIRECTION = 0, DEC_DIRECTION = 1, BI_DIRECTION = 2$/;" e enum:e_direction +DEGTORAD base/graphics.c 228;" d file: +DELAY_NORMALIZED base/vpr_types.h /^ INTRINSIC_DELAY, DELAY_NORMALIZED, DEMAND_ONLY$/;" e enum:e_base_cost_type +DELETE_ERROR base/graphics.c 218;" d file: +DELTA ../../libarchfpga/include/physical_types.h /^ UNIFORM, GAUSSIAN, PULSE, DELTA$/;" e enum:e_stat +DEMAND_ONLY base/vpr_types.h /^ INTRINSIC_DELAY, DELAY_NORMALIZED, DEMAND_ONLY$/;" e enum:e_base_cost_type +DETAILED base/vpr_types.h /^ GLOBAL, DETAILED$/;" e enum:e_route_type +DIGIT timing/slre.c /^ STARQ, PLUSQ, QUEST, SPACE, NONSPACE, DIGIT$/;" e enum:__anon19 file: +DIRECT_INTERC ../../libarchfpga/include/physical_types.h /^ COMPLETE_INTERC = 1, DIRECT_INTERC = 2, MUX_INTERC = 3$/;" e enum:e_interconnect +DISCOUNT_FUNCTION_BASE timing/path_delay.h 23;" d +DO_NOT_ANALYSE timing/path_delay.h 4;" d +DRAW_ALL_BUT_BUFFERS_RR base/draw.c /^ DRAW_ALL_BUT_BUFFERS_RR,$/;" e enum:e_draw_rr_toggle file: +DRAW_ALL_RR base/draw.c /^ DRAW_ALL_RR,$/;" e enum:e_draw_rr_toggle file: +DRAW_ERROR base/graphics.c 220;" d file: +DRAW_NODES_AND_SBOX_RR base/draw.c /^ DRAW_NODES_AND_SBOX_RR,$/;" e enum:e_draw_rr_toggle file: +DRAW_NODES_RR base/draw.c /^ DRAW_NODES_RR,$/;" e enum:e_draw_rr_toggle file: +DRAW_NORMAL base/graphics.h /^enum e_draw_mode {DRAW_NORMAL = 0, DRAW_XOR};$/;" e enum:e_draw_mode +DRAW_NO_RR base/draw.c /^ DRAW_NO_RR = 0,$/;" e enum:e_draw_rr_toggle file: +DRAW_RR_TOGGLE_MAX base/draw.c /^ DRAW_RR_TOGGLE_MAX$/;" e enum:e_draw_rr_toggle file: +DRAW_XOR base/graphics.h /^enum e_draw_mode {DRAW_NORMAL = 0, DRAW_XOR};$/;" e enum:e_draw_mode +DRIVER ../../libarchfpga/include/physical_types.h /^ OPEN = -1, DRIVER = 0, RECEIVER = 1$/;" e enum:e_pin_type +DUMPFILE place/timing_place_lookup.c 63;" d file: +Directs ../../libarchfpga/include/physical_types.h /^ t_direct_inf *Directs;$/;" m struct:s_arch +EASYGL_CONSTANTS_H base/easygl_constants.h 2;" d +EMPTY base/vpr_types.h 90;" d +EMPTY_TYPE ../../libarchfpga/read_xml_arch_file.c /^static t_type_ptr EMPTY_TYPE = NULL;$/;" v file: +EMPTY_TYPE base/globals.c /^t_type_ptr EMPTY_TYPE = NULL;$/;" v +EMPTY_TYPE_BACKUP place/timing_place_lookup.c /^static t_type_ptr EMPTY_TYPE_BACKUP;$/;" v file: +EMPTY_TYPE_INDEX ../../libarchfpga/include/read_xml_arch_file.h 15;" d +ENABLE_REVERSE route/rr_graph2.c 21;" d file: +END timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: +EOL timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: +EPSILON base/vpr_types.h 83;" d +ERROR_THRESHOLD base/check_netlist.c 15;" d file: +ERROR_TOL place/place.c 31;" d file: +ERROR_TOL route/route_timing.c 884;" d file: +ERRTAG ../../libarchfpga/include/util.h 26;" d +ERR_PORT ../../libarchfpga/include/logic_types.h /^ IN_PORT, OUT_PORT, INOUT_PORT, ERR_PORT$/;" e enum:PORTS +EXACT timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: +EZXML_BUFSIZE ../../libarchfpga/include/ezxml.h 37;" d +EZXML_DUP ../../libarchfpga/include/ezxml.h 40;" d +EZXML_ERRL ../../libarchfpga/include/ezxml.h 41;" d +EZXML_NAMEM ../../libarchfpga/include/ezxml.h 38;" d +EZXML_NIL ../../libarchfpga/ezxml.c /^char *EZXML_NIL[] = { NULL }; \/* empty, null terminated array of strings *\/$/;" v +EZXML_NOMMAP ../../libarchfpga/ezxml.c 26;" d file: +EZXML_TXTM ../../libarchfpga/include/ezxml.h 39;" d +EZXML_WS ../../libarchfpga/ezxml.c 64;" d file: +E_ANNOT_PIN_TO_PIN_CAPACITANCE ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_CAPACITANCE,$/;" e enum:e_pin_to_pin_annotation_type +E_ANNOT_PIN_TO_PIN_CAPACITANCE_C ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_CAPACITANCE_C = 0$/;" e enum:e_pin_to_pin_capacitance_annotations +E_ANNOT_PIN_TO_PIN_CONSTANT ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_MATRIX = 0, E_ANNOT_PIN_TO_PIN_CONSTANT$/;" e enum:e_pin_to_pin_annotation_format +E_ANNOT_PIN_TO_PIN_DELAY ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY = 0,$/;" e enum:e_pin_to_pin_annotation_type +E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX,$/;" e enum:e_pin_to_pin_delay_annotations +E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN,$/;" e enum:e_pin_to_pin_delay_annotations +E_ANNOT_PIN_TO_PIN_DELAY_MAX ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_MAX,$/;" e enum:e_pin_to_pin_delay_annotations +E_ANNOT_PIN_TO_PIN_DELAY_MIN ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_MIN = 0,$/;" e enum:e_pin_to_pin_delay_annotations +E_ANNOT_PIN_TO_PIN_DELAY_THOLD ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_THOLD$/;" e enum:e_pin_to_pin_delay_annotations +E_ANNOT_PIN_TO_PIN_DELAY_TSETUP ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_TSETUP,$/;" e enum:e_pin_to_pin_delay_annotations +E_ANNOT_PIN_TO_PIN_MATRIX ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_MATRIX = 0, E_ANNOT_PIN_TO_PIN_CONSTANT$/;" e enum:e_pin_to_pin_annotation_format +E_ANNOT_PIN_TO_PIN_MODE_SELECT ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_MODE_SELECT$/;" e enum:e_pin_to_pin_annotation_type +E_ANNOT_PIN_TO_PIN_MODE_SELECT_MODE_NAME ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_MODE_SELECT_MODE_NAME = 0$/;" e enum:e_pin_to_pin_mode_select_annotations +E_ANNOT_PIN_TO_PIN_PACK_PATTERN ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_PACK_PATTERN,$/;" e enum:e_pin_to_pin_annotation_type +E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME ../../libarchfpga/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME = 0$/;" e enum:e_pin_to_pin_pack_pattern_annotations +E_CRITICALITY_FILE base/ReadOptions.h /^ E_CRITICALITY_FILE,$/;" e enum:e_output_files +E_CRIT_PATH_FILE base/ReadOptions.h /^ E_CRIT_PATH_FILE,$/;" e enum:e_output_files +E_CUSTOM_PIN_DISTR ../../libarchfpga/include/physical_types.h /^ E_SPREAD_PIN_DISTR = 1, E_CUSTOM_PIN_DISTR = 2$/;" e enum:e_pin_location_distr +E_DETAILED_ROUTE_AT_END_ONLY pack/cluster.c /^ E_DETAILED_ROUTE_AT_END_ONLY = 0, E_DETAILED_ROUTE_FOR_EACH_ATOM, E_DETAILED_ROUTE_END$/;" e enum:e_detailed_routing_stages file: +E_DETAILED_ROUTE_END pack/cluster.c /^ E_DETAILED_ROUTE_AT_END_ONLY = 0, E_DETAILED_ROUTE_FOR_EACH_ATOM, E_DETAILED_ROUTE_END$/;" e enum:e_detailed_routing_stages file: +E_DETAILED_ROUTE_FOR_EACH_ATOM pack/cluster.c /^ E_DETAILED_ROUTE_AT_END_ONLY = 0, E_DETAILED_ROUTE_FOR_EACH_ATOM, E_DETAILED_ROUTE_END$/;" e enum:e_detailed_routing_stages file: +E_DIR_EXIST fpga_spice/fpga_spice_utils.c /^ E_DIR_EXIST$/;" e enum:e_dir_err file: +E_DIR_NOT_EXIST fpga_spice/fpga_spice_utils.c /^ E_DIR_NOT_EXIST,$/;" e enum:e_dir_err file: +E_ECHO_ARCH base/ReadOptions.h /^ E_ECHO_ARCH,$/;" e enum:e_echo_files +E_ECHO_BLIF_INPUT base/ReadOptions.h /^ E_ECHO_BLIF_INPUT,$/;" e enum:e_echo_files +E_ECHO_CLUSTERING_BLOCK_CRITICALITIES base/ReadOptions.h /^ E_ECHO_CLUSTERING_BLOCK_CRITICALITIES,$/;" e enum:e_echo_files +E_ECHO_CLUSTERING_TIMING_INFO base/ReadOptions.h /^ E_ECHO_CLUSTERING_TIMING_INFO,$/;" e enum:e_echo_files +E_ECHO_COMPLETE_NET_TRACE base/ReadOptions.h /^ E_ECHO_COMPLETE_NET_TRACE,$/;" e enum:e_echo_files +E_ECHO_CRITICALITY base/ReadOptions.h /^ E_ECHO_CRITICALITY,$/;" e enum:e_echo_files +E_ECHO_CRITICAL_PATH base/ReadOptions.h /^ E_ECHO_CRITICAL_PATH,$/;" e enum:e_echo_files +E_ECHO_END_CLB_PLACEMENT base/ReadOptions.h /^ E_ECHO_END_CLB_PLACEMENT,$/;" e enum:e_echo_files +E_ECHO_END_TOKEN base/ReadOptions.h /^ E_ECHO_END_TOKEN$/;" e enum:e_echo_files +E_ECHO_FINAL_PLACEMENT_CRITICALITY base/ReadOptions.h /^ E_ECHO_FINAL_PLACEMENT_CRITICALITY,$/;" e enum:e_echo_files +E_ECHO_FINAL_PLACEMENT_SLACK base/ReadOptions.h /^ E_ECHO_FINAL_PLACEMENT_SLACK,$/;" e enum:e_echo_files +E_ECHO_FINAL_PLACEMENT_TIMING_GRAPH base/ReadOptions.h /^ E_ECHO_FINAL_PLACEMENT_TIMING_GRAPH,$/;" e enum:e_echo_files +E_ECHO_INITIAL_CLB_PLACEMENT base/ReadOptions.h /^ E_ECHO_INITIAL_CLB_PLACEMENT = 0,$/;" e enum:e_echo_files +E_ECHO_INITIAL_PLACEMENT_CRITICALITY base/ReadOptions.h /^ E_ECHO_INITIAL_PLACEMENT_CRITICALITY,$/;" e enum:e_echo_files +E_ECHO_INITIAL_PLACEMENT_SLACK base/ReadOptions.h /^ E_ECHO_INITIAL_PLACEMENT_SLACK,$/;" e enum:e_echo_files +E_ECHO_INITIAL_PLACEMENT_TIMING_GRAPH base/ReadOptions.h /^ E_ECHO_INITIAL_PLACEMENT_TIMING_GRAPH,$/;" e enum:e_echo_files +E_ECHO_LUT_REMAPPING base/ReadOptions.h /^ E_ECHO_LUT_REMAPPING,$/;" e enum:e_echo_files +E_ECHO_MEM base/ReadOptions.h /^ E_ECHO_MEM,$/;" e enum:e_echo_files +E_ECHO_NET_DELAY base/ReadOptions.h /^ E_ECHO_NET_DELAY,$/;" e enum:e_echo_files +E_ECHO_PB_GRAPH base/ReadOptions.h /^ E_ECHO_PB_GRAPH,$/;" e enum:e_echo_files +E_ECHO_PLACEMENT_CRITICAL_PATH base/ReadOptions.h /^ E_ECHO_PLACEMENT_CRITICAL_PATH,$/;" e enum:e_echo_files +E_ECHO_PLACEMENT_CRIT_PATH base/ReadOptions.h /^ E_ECHO_PLACEMENT_CRIT_PATH,$/;" e enum:e_echo_files +E_ECHO_PLACEMENT_LOGIC_SINK_DELAYS base/ReadOptions.h /^ E_ECHO_PLACEMENT_LOGIC_SINK_DELAYS,$/;" e enum:e_echo_files +E_ECHO_PLACEMENT_LOWER_BOUND_SINK_DELAYS base/ReadOptions.h /^ E_ECHO_PLACEMENT_LOWER_BOUND_SINK_DELAYS,$/;" e enum:e_echo_files +E_ECHO_PLACEMENT_SINK_DELAYS base/ReadOptions.h /^ E_ECHO_PLACEMENT_SINK_DELAYS,$/;" e enum:e_echo_files +E_ECHO_POST_FLOW_TIMING_GRAPH base/ReadOptions.h /^ E_ECHO_POST_FLOW_TIMING_GRAPH,$/;" e enum:e_echo_files +E_ECHO_POST_PACK_NETLIST base/ReadOptions.h /^ E_ECHO_POST_PACK_NETLIST,$/;" e enum:e_echo_files +E_ECHO_PRE_PACKING_CRITICALITY base/ReadOptions.h /^ E_ECHO_PRE_PACKING_CRITICALITY,$/;" e enum:e_echo_files +E_ECHO_PRE_PACKING_MOLECULES_AND_PATTERNS base/ReadOptions.h /^ E_ECHO_PRE_PACKING_MOLECULES_AND_PATTERNS,$/;" e enum:e_echo_files +E_ECHO_PRE_PACKING_SLACK base/ReadOptions.h /^ E_ECHO_PRE_PACKING_SLACK,$/;" e enum:e_echo_files +E_ECHO_PRE_PACKING_TIMING_GRAPH base/ReadOptions.h /^ E_ECHO_PRE_PACKING_TIMING_GRAPH,$/;" e enum:e_echo_files +E_ECHO_PRE_PACKING_TIMING_GRAPH_AS_BLIF base/ReadOptions.h /^ E_ECHO_PRE_PACKING_TIMING_GRAPH_AS_BLIF,$/;" e enum:e_echo_files +E_ECHO_ROUTING_SINK_DELAYS base/ReadOptions.h /^ E_ECHO_ROUTING_SINK_DELAYS,$/;" e enum:e_echo_files +E_ECHO_RR_GRAPH base/ReadOptions.h /^ E_ECHO_RR_GRAPH,$/;" e enum:e_echo_files +E_ECHO_SEG_DETAILS base/ReadOptions.h /^ E_ECHO_SEG_DETAILS,$/;" e enum:e_echo_files +E_ECHO_SLACK base/ReadOptions.h /^ E_ECHO_SLACK,$/;" e enum:e_echo_files +E_ECHO_TIMING_CONSTRAINTS base/ReadOptions.h /^ E_ECHO_TIMING_CONSTRAINTS,$/;" e enum:e_echo_files +E_ECHO_TIMING_GRAPH base/ReadOptions.h /^ E_ECHO_TIMING_GRAPH,$/;" e enum:e_echo_files +E_EXIST_BUT_NOT_DIR fpga_spice/fpga_spice_utils.c /^ E_EXIST_BUT_NOT_DIR,$/;" e enum:e_dir_err file: +E_FILE_END_TOKEN base/ReadOptions.h /^ E_FILE_END_TOKEN$/;" e enum:e_output_files +E_SLACK_FILE base/ReadOptions.h /^ E_SLACK_FILE,$/;" e enum:e_output_files +E_SPREAD_PIN_DISTR ../../libarchfpga/include/physical_types.h /^ E_SPREAD_PIN_DISTR = 1, E_CUSTOM_PIN_DISTR = 2$/;" e enum:e_pin_location_distr +EchoArch ../../libarchfpga/read_xml_arch_file.c /^void EchoArch(INP const char *EchoFile, INP const t_type_descriptor * Types,$/;" f +EchoEnabled base/ReadOptions.c /^static boolean EchoEnabled;$/;" v file: +Enum base/vpr_types.h /^ int Enum;$/;" m struct:s_TokenPair +Error base/ReadOptions.c /^static void Error(INP const char *Token) {$/;" f file: +FALSE ../../libarchfpga/include/util.h /^ FALSE, TRUE$/;" e enum:__anon23 +FALSE base/graphics.c 146;" d file: +FC_ABS ../../libarchfpga/read_xml_arch_file.c /^ FC_ABS, FC_FRAC, FC_FULL$/;" e enum:Fc_type file: +FC_FRAC ../../libarchfpga/read_xml_arch_file.c /^ FC_ABS, FC_FRAC, FC_FULL$/;" e enum:Fc_type file: +FC_FULL ../../libarchfpga/read_xml_arch_file.c /^ FC_ABS, FC_FRAC, FC_FULL$/;" e enum:Fc_type file: +FEASIBLE pack/cluster.c /^ FEASIBLE, INFEASIBLE$/;" e enum:e_feasibility file: +FF_FE spice/spice_primitives.c /^ FF_RE, FF_FE$/;" e enum:e_ff_trigger_type file: +FF_FE syn_verilog/verilog_primitives.c /^ FF_RE, FF_FE$/;" e enum:e_ff_trigger_type file: +FF_RE spice/spice_primitives.c /^ FF_RE, FF_FE$/;" e enum:e_ff_trigger_type file: +FF_RE syn_verilog/verilog_primitives.c /^ FF_RE, FF_FE$/;" e enum:e_ff_trigger_type file: +FF_size ../../libarchfpga/include/physical_types.h /^ float FF_size;$/;" m struct:s_power_arch +FILL ../../libarchfpga/include/physical_types.h /^ BOUNDARY = 0, FILL, COL_REPEAT, COL_REL$/;" e enum:e_grid_loc_type +FILL_TYPE ../../libarchfpga/read_xml_arch_file.c /^static t_type_ptr FILL_TYPE = NULL;$/;" v file: +FILL_TYPE base/globals.c /^t_type_ptr FILL_TYPE = NULL;$/;" v +FILL_TYPE_BACKUP place/timing_place_lookup.c /^static t_type_ptr FILL_TYPE_BACKUP;$/;" v file: +FINAL_DISCOUNT_FUNCTION_BASE timing/path_delay.h 28;" d +FIRST_ITER_WIRELENTH_LIMIT base/vpr_types.h 88;" d +FONTMAG base/graphics.c 229;" d file: +FPGA_SPICE_Opts base/vpr_types.h /^ t_fpga_spice_opts FPGA_SPICE_Opts; \/* Xifan TANG: FPGA-SPICE support *\/$/;" m struct:s_vpr_setup +FRACTIONAL ../../libarchfpga/include/physical_types.h /^ ABSOLUTE, FRACTIONAL$/;" e enum:e_Fc_type +FRAGMENT_THRESHOLD ../../libarchfpga/util.c 209;" d file: +FREE base/vpr_types.h /^ FREE, RANDOM, USER$/;" e enum:e_pad_loc_type +FROM_X_TO_Y base/draw.c /^ FROM_X_TO_Y, FROM_Y_TO_X$/;" e enum:e_edge_dir file: +FROM_Y_TO_X base/draw.c /^ FROM_X_TO_Y, FROM_Y_TO_X$/;" e enum:e_edge_dir file: +FULL ../../libarchfpga/include/physical_types.h /^ SUBSET, WILTON, UNIVERSAL, FULL$/;" e enum:e_switch_block_type +Fc ../../libarchfpga/include/physical_types.h /^ float *Fc; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor +Fc_type ../../libarchfpga/read_xml_arch_file.c /^enum Fc_type {$/;" g file: +FileNameOpts base/vpr_types.h /^ struct s_file_name_opts FileNameOpts; \/* File names *\/$/;" m struct:s_vpr_setup typeref:struct:s_vpr_setup::s_file_name_opts +FindElement ../../libarchfpga/read_xml_util.c /^ezxml_t FindElement(INP ezxml_t Parent, INP const char *Name,$/;" f +FindFirstElement ../../libarchfpga/read_xml_util.c /^ezxml_t FindFirstElement(INP ezxml_t Parent, INP const char *Name,$/;" f +FindProperty ../../libarchfpga/read_xml_util.c /^FindProperty(INP ezxml_t Parent, INP const char *Name, INP boolean Required) {$/;" f +FreeNode ../../libarchfpga/read_xml_util.c /^void FreeNode(INOUTP ezxml_t Node) {$/;" f +FreeSpice ../../libarchfpga/read_xml_spice_util.c /^void FreeSpice(t_spice* spice) {$/;" f +FreeSpiceMeasParams ../../libarchfpga/read_xml_spice_util.c /^void FreeSpiceMeasParams(t_spice_meas_params* meas_params) {$/;" f +FreeSpiceModel ../../libarchfpga/read_xml_spice_util.c /^void FreeSpiceModel(t_spice_model* spice_model) {$/;" f +FreeSpiceModelBuffer ../../libarchfpga/read_xml_spice_util.c /^void FreeSpiceModelBuffer(t_spice_model_buffer* spice_model_buffer) {$/;" f +FreeSpiceModelNetlist ../../libarchfpga/read_xml_spice_util.c /^void FreeSpiceModelNetlist(t_spice_model_netlist* spice_model_netlist) {$/;" f +FreeSpiceModelPassGateLogic ../../libarchfpga/read_xml_spice_util.c /^void FreeSpiceModelPassGateLogic(t_spice_model_pass_gate_logic* spice_model_pass_gate_logic) {$/;" f +FreeSpiceModelPort ../../libarchfpga/read_xml_spice_util.c /^void FreeSpiceModelPort(t_spice_model_port* spice_model_port) {$/;" f +FreeSpiceModelWireParam ../../libarchfpga/read_xml_spice_util.c /^void FreeSpiceModelWireParam(t_spice_model_wire_param* spice_model_wire_param) {$/;" f +FreeSpiceMonteCarloParams ../../libarchfpga/read_xml_spice_util.c /^void FreeSpiceMonteCarloParams(t_spice_mc_params* mc_params) {$/;" f +FreeSpiceMuxArch ../../libarchfpga/read_xml_spice_util.c /^void FreeSpiceMuxArch(t_spice_mux_arch* spice_mux_arch) {$/;" f +FreeSpiceParams ../../libarchfpga/read_xml_spice_util.c /^void FreeSpiceParams(t_spice_params* params) {$/;" f +FreeSpiceStimulateParams ../../libarchfpga/read_xml_spice_util.c /^void FreeSpiceStimulateParams(t_spice_stimulate_params* stimulate_params) {$/;" f +FreeSpiceVariationParams ../../libarchfpga/read_xml_spice_util.c /^void FreeSpiceVariationParams(t_spice_mc_variation_params* mc_variation_params) {$/;" f +FreeSramInf ../../libarchfpga/read_xml_spice_util.c /^void FreeSramInf(t_sram_inf* sram_inf) {$/;" f +FreeSramInfOrgz ../../libarchfpga/read_xml_spice_util.c /^void FreeSramInfOrgz(t_sram_inf_orgz* sram_inf_orgz) {$/;" f +FreeTokens ../../libarchfpga/ReadLine.c /^void FreeTokens(INOUTP char ***TokensPtr) {$/;" f +Fs ../../libarchfpga/include/physical_types.h /^ int Fs;$/;" m struct:s_arch +Fs base/vpr_types.h /^ int Fs;$/;" m struct:s_det_routing_arch +Fs_seed base/globals.c /^int Fs_seed = -1;$/;" v +GAIN pack/cluster.c /^ GAIN, NO_GAIN$/;" e enum:e_gain_update file: +GAUSSIAN ../../libarchfpga/include/physical_types.h /^ UNIFORM, GAUSSIAN, PULSE, DELTA$/;" e enum:e_stat +GLOBAL base/vpr_types.h /^ GLOBAL, DETAILED$/;" e enum:e_route_type +GLOBALS_H base/globals.h 13;" d +GOT_FROM_SCRATCH place/place.c 47;" d file: +GRAPHICS_H base/graphics.h 3;" d +GRAPH_BIDIR route/rr_graph.h /^ GRAPH_BIDIR, \/* Detailed bidirectional graph *\/$/;" e enum:e_graph_type +GRAPH_GLOBAL route/rr_graph.h /^ GRAPH_GLOBAL, \/* One node per channel with wire capacity > 1 and full connectivity *\/$/;" e enum:e_graph_type +GRAPH_UNIDIR route/rr_graph.h /^ GRAPH_UNIDIR, \/* Detailed unidir graph, untilable *\/$/;" e enum:e_graph_type +GRAPH_UNIDIR_TILEABLE route/rr_graph.h /^ GRAPH_UNIDIR_TILEABLE \/* Detail unidir graph with wire groups multiples of 2*L *\/$/;" e enum:e_graph_type +GREEN base/easygl_constants.h /^enum color_types {WHITE, BLACK, DARKGREY, LIGHTGREY, BLUE, GREEN, YELLOW,$/;" e enum:color_types +Generate_PostSynthesis_Netlist base/ReadOptions.c /^static boolean Generate_PostSynthesis_Netlist;$/;" v file: +Generate_Post_Synthesis_Netlist base/ReadOptions.h /^ boolean Generate_Post_Synthesis_Netlist;$/;" m struct:s_options +GetBooleanProperty ../../libarchfpga/read_xml_util.c /^extern boolean GetBooleanProperty(INP ezxml_t Parent, INP char *Name,$/;" f +GetFloatProperty ../../libarchfpga/read_xml_util.c /^extern float GetFloatProperty(INP ezxml_t Parent, INP char *Name,$/;" f +GetIntProperty ../../libarchfpga/read_xml_util.c /^extern int GetIntProperty(INP ezxml_t Parent, INP char *Name,$/;" f +GetNodeTokens ../../libarchfpga/read_xml_util.c /^GetNodeTokens(INP ezxml_t Node) {$/;" f +GetPostSynthesisOption base/ReadOptions.c /^boolean GetPostSynthesisOption(void){$/;" f +GetTokenTypeFromChar util/token.c /^enum e_token_type GetTokenTypeFromChar(INP enum e_token_type cur_token_type,$/;" f +GetTokensFromString util/token.c /^t_token *GetTokensFromString(INP const char* inString, OUTP int * num_tokens) {$/;" f +GraphPause base/ReadOptions.h /^ int GraphPause;$/;" m struct:s_options +GraphPause base/vpr_types.h /^ int GraphPause; \/* user interactiveness graphics option *\/$/;" m struct:s_vpr_setup +GraphicsWND base/graphics.c /^GraphicsWND(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)$/;" f file: +H ../../libarchfpga/include/physical_types.h /^ int H;$/;" m struct:s_clb_grid +HASHSIZE util/hash.h 1;" d +HIGHLIGHTED base/draw.c /^ ALL_NETS, HIGHLIGHTED$/;" e enum:e_draw_net_type file: +HIGH_FANOUT_NET_LIM base/vpr_types.h 86;" d +HILL_CLIMBING pack/cluster.c /^ HILL_CLIMBING, NOT_HILL_CLIMBING$/;" e enum:e_gain_type file: +HUGE_NEGATIVE_FLOAT base/vpr_types.h 80;" d +HUGE_POSITIVE_FLOAT base/vpr_types.h 79;" d +IA ../../libarchfpga/util.c 731;" d file: +IC ../../libarchfpga/util.c 732;" d file: +IM ../../libarchfpga/util.c 733;" d file: +IMPOSSIBLE place/timing_place_lookup.h 1;" d +INC_DIRECTION base/vpr_types.h /^ INC_DIRECTION = 0, DEC_DIRECTION = 1, BI_DIRECTION = 2$/;" e enum:e_direction +INFEASIBLE pack/cluster.c /^ FEASIBLE, INFEASIBLE$/;" e enum:e_feasibility file: +INFINITE base/place_and_route.h 1;" d +INOUTP ../../libarchfpga/include/util.h 21;" d +INOUT_PORT ../../libarchfpga/include/logic_types.h /^ IN_PORT, OUT_PORT, INOUT_PORT, ERR_PORT$/;" e enum:PORTS +INP ../../libarchfpga/include/util.h 19;" d +INPUT pack/cluster.c /^ INPUT, OUTPUT$/;" e enum:e_net_relation_to_clustered_block file: +INPUT2INPUT_INTERC fpga_spice/fpga_spice_globals.h /^ INPUT2INPUT_INTERC, OUTPUT2OUTPUT_INTERC$/;" e enum:e_pin2pin_interc_type +INTRA_CLUSTER_EDGE base/vpr_types.h /^ SOURCE = 0, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_CLUSTER_EDGE, NUM_RR_TYPES$/;" e enum:e_rr_type +INTRINSIC_DELAY base/vpr_types.h /^ INTRINSIC_DELAY, DELAY_NORMALIZED, DEMAND_ONLY$/;" e enum:e_base_cost_type +INV_1X_C power/power.h /^ float INV_1X_C;$/;" m struct:s_power_commonly_used +INV_1X_C_in power/power.h /^ float INV_1X_C_in;$/;" m struct:s_power_commonly_used +INV_2X_C power/power.h /^ float INV_2X_C;$/;" m struct:s_power_commonly_used +IN_PORT ../../libarchfpga/include/logic_types.h /^ IN_PORT, OUT_PORT, INOUT_PORT, ERR_PORT$/;" e enum:PORTS +IO_TYPE ../../libarchfpga/read_xml_arch_file.c /^static t_type_ptr IO_TYPE = NULL;$/;" v file: +IO_TYPE base/globals.c /^t_type_ptr IO_TYPE = NULL;$/;" v +IO_TYPE_BACKUP place/timing_place_lookup.c /^static t_type_ptr IO_TYPE_BACKUP;$/;" v file: +IO_TYPE_INDEX ../../libarchfpga/include/read_xml_arch_file.h 16;" d +IPIN base/vpr_types.h /^ SOURCE = 0, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_CLUSTER_EDGE, NUM_RR_TYPES$/;" e enum:e_rr_type +IPIN_COST_INDEX base/vpr_types.h /^ IPIN_COST_INDEX,$/;" e enum:e_cost_indices +InEventLoop base/graphics.c /^static boolean InEventLoop = FALSE;$/;" v file: +InitSpice ../../libarchfpga/read_xml_spice_util.c /^void InitSpice(t_spice* spice) {$/;" f +InitSpiceMeasParams ../../libarchfpga/read_xml_spice_util.c /^void InitSpiceMeasParams(t_spice_meas_params* meas_params) {$/;" f +InitSpiceMonteCarloParams ../../libarchfpga/read_xml_spice_util.c /^void InitSpiceMonteCarloParams(t_spice_mc_params* mc_params) {$/;" f +InitSpiceParams ../../libarchfpga/read_xml_spice_util.c /^void InitSpiceParams(t_spice_params* params) {$/;" f +InitSpiceStimulateParams ../../libarchfpga/read_xml_spice_util.c /^void InitSpiceStimulateParams(t_spice_stimulate_params* stimulate_params) {$/;" f +InitSpiceVariationParams ../../libarchfpga/read_xml_spice_util.c /^void InitSpiceVariationParams(t_spice_mc_variation_params* mc_variation_params) {$/;" f +IsAuto ../../libarchfpga/include/physical_types.h /^ boolean IsAuto;$/;" m struct:s_clb_grid +IsEchoEnabled base/ReadOptions.c /^boolean IsEchoEnabled(INP t_options *Options) {$/;" f +IsPostSynthesisEnabled base/ReadOptions.c /^boolean IsPostSynthesisEnabled(INP t_options *Options) {$/;" f +IsTimingEnabled base/ReadOptions.c /^boolean IsTimingEnabled(INP t_options *Options) {$/;" f +IsWhitespace ../../libarchfpga/read_xml_util.c /^boolean IsWhitespace(char c) {$/;" f +KHAKI base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types +LATCH_CLASS ../../libarchfpga/include/physical_types.h /^ UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3$/;" e enum:e_pb_type_class +LEAVE_CLUSTERED pack/cluster.c /^ REMOVE_CLUSTERED, LEAVE_CLUSTERED$/;" e enum:e_removal_policy file: +LEFT ../../libarchfpga/include/physical_types.h /^ TOP = 0, RIGHT = 1, BOTTOM = 2, LEFT = 3$/;" e enum:e_side +LIGHTBLUE base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types +LIGHTGREY base/easygl_constants.h /^enum color_types {WHITE, BLACK, DARKGREY, LIGHTGREY, BLUE, GREEN, YELLOW,$/;" e enum:color_types +LINELENGTH pack/output_blif.c 18;" d file: +LINELENGTH pack/output_clustering.c 16;" d file: +LINKEDLIST_H ../../libarchfpga/fpga_spice_include/linkedlist.h 2;" d +LOGIC_TYPES_H ../../libarchfpga/include/logic_types.h 10;" d +LONGLINE route/segment_stats.c 9;" d file: +LUT_CLASS ../../libarchfpga/include/physical_types.h /^ UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3$/;" e enum:e_pb_type_class +LUT_transistor_size ../../libarchfpga/include/physical_types.h /^ float LUT_transistor_size;$/;" m struct:s_power_arch +LookaheadNodeTokens ../../libarchfpga/read_xml_util.c /^LookaheadNodeTokens(INP ezxml_t Node) {$/;" f +MAGENTA base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types +MAJOR base/vpr_types.h 73;" d +MARKED_FRAC pack/cluster.c 87;" d file: +MAXPIXEL base/graphics.c 202;" d file: +MAXPIXEL base/graphics.c 225;" d file: +MAXPTS base/easygl_constants.h 10;" d +MAX_ATOM_PARSE base/read_blif.c 20;" d file: +MAX_BLOCK_COLOURS base/draw.c 21;" d file: +MAX_CHANNEL_WIDTH ../../libarchfpga/include/arch_types.h 25;" d +MAX_FONT_SIZE base/graphics.c 179;" d file: +MAX_INV_TIMING_COST place/place.c 64;" d file: +MAX_LEN place/place_stats.c 9;" d file: +MAX_LOGS power/power.h 33;" d +MAX_MOVES_BEFORE_RECOMPUTE place/place.c 36;" d file: +MAX_NUM_TRIES_TO_PLACE_MACROS_RANDOMLY place/place.c 41;" d file: +MAX_SHORT base/vpr_types.h 75;" d +MAX_STRING_LEN util/vpr_utils.c 18;" d file: +MAX_X place/place_stats.c 8;" d file: +MEDIUMPURPLE base/easygl_constants.h /^TURQUOISE, MEDIUMPURPLE, DARKSLATEBLUE, DARKKHAKI, NUM_COLOR};$/;" e enum:color_types +MEMORY_CLASS ../../libarchfpga/include/physical_types.h /^ UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3$/;" e enum:e_pb_type_class +MINOR base/vpr_types.h 72;" d +MINPIXEL base/graphics.c 203;" d file: +MINPIXEL base/graphics.c 226;" d file: +MODEL_INPUT base/vpr_types.h 297;" d +MODEL_LATCH base/vpr_types.h 296;" d +MODEL_LOGIC base/vpr_types.h 295;" d +MODEL_OUTPUT base/vpr_types.h 298;" d +MOLECULE_FORCED_PACK base/vpr_types.h /^ MOLECULE_SINGLE_ATOM, MOLECULE_FORCED_PACK$/;" e enum:e_pack_pattern_molecule_type +MOLECULE_SINGLE_ATOM base/vpr_types.h /^ MOLECULE_SINGLE_ATOM, MOLECULE_FORCED_PACK$/;" e enum:e_pack_pattern_molecule_type +MONO ../../libarchfpga/include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp +MRFPGA_H mrfpga/mrfpga_globals.h 2;" d +MULTI_BUFFERED base/vpr_types.h /^ MULTI_BUFFERED, SINGLE$/;" e enum:e_drivers +MUX_INTERC ../../libarchfpga/include/physical_types.h /^ COMPLETE_INTERC = 1, DIRECT_INTERC = 2, MUX_INTERC = 3$/;" e enum:e_interconnect +MWIDTH base/graphics.c 177;" d file: +MainWND base/graphics.c /^MainWND(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)$/;" f file: +MergeOptions base/ReadOptions.c /^static void MergeOptions(INOUTP t_options * dest, INP t_options * src, int id)$/;" f file: +NDEBUG base/vpr_types.h 63;" d +NEGATIVE_EPSILON base/vpr_types.h 84;" d +NEM ../../libarchfpga/include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp +NET_COUNT place/timing_place_lookup.c 41;" d file: +NET_TIMING_DRIVEN_PLACE base/vpr_types.h /^ BOUNDING_BOX_PLACE, NET_TIMING_DRIVEN_PLACE, PATH_TIMING_DRIVEN_PLACE$/;" e enum:e_place_algorithm +NET_USED place/timing_place_lookup.c 45;" d file: +NET_USED_SINK_BLOCK place/timing_place_lookup.c 48;" d file: +NET_USED_SOURCE_BLOCK place/timing_place_lookup.c 47;" d file: +NEVER_CLUSTER base/vpr_types.h 99;" d +NMOS power/power.h /^ NMOS, PMOS$/;" e enum:__anon11 +NMOS_1X_C_d power/power.h /^ float NMOS_1X_C_d;$/;" m struct:s_power_commonly_used +NMOS_1X_C_g power/power.h /^ float NMOS_1X_C_g;$/;" m struct:s_power_commonly_used +NMOS_1X_C_s power/power.h /^ float NMOS_1X_C_s;$/;" m struct:s_power_commonly_used +NMOS_1X_st_leakage power/power.h /^ float NMOS_1X_st_leakage;$/;" m struct:s_power_commonly_used +NMOS_2X_st_leakage power/power.h /^ float NMOS_2X_st_leakage;$/;" m struct:s_power_commonly_used +NMOS_inf power/power.h /^ t_transistor_inf NMOS_inf;$/;" m struct:s_power_tech +NONSPACE timing/slre.c /^ STARQ, PLUSQ, QUEST, SPACE, NONSPACE, DIGIT$/;" e enum:__anon19 file: +NORMAL place/place.c /^ NORMAL, CHECK$/;" e enum:cost_methods file: +NOT_FOUND base/place_and_route.h 2;" d +NOT_HILL_CLIMBING pack/cluster.c /^ HILL_CLIMBING, NOT_HILL_CLIMBING$/;" e enum:e_gain_type file: +NOT_UPDATED_YET place/place.c 45;" d file: +NOT_VALID base/vpr_types.h 100;" d +NO_CLUSTER base/vpr_types.h 98;" d +NO_FIXED_CHANNEL_WIDTH base/vpr_types.h 729;" d +NO_GAIN pack/cluster.c /^ GAIN, NO_GAIN$/;" e enum:e_gain_update file: +NO_GRAPHICS base/vpr_types.h 62;" d +NO_PICTURE base/vpr_types.h /^ NO_PICTURE, PLACEMENT, ROUTING$/;" e enum:pic_type +NO_PREVIOUS base/vpr_types.h 929;" d +NO_ROUTE_THROUGHS route/route_tree_timing.c 255;" d file: +NO_TIMING base/vpr_types.h /^ BREADTH_FIRST, TIMING_DRIVEN, NO_TIMING$/;" e enum:e_router_algorithm +NUM_BUCKETS timing/path_delay.c 148;" d file: +NUM_COLOR base/easygl_constants.h /^TURQUOISE, MEDIUMPURPLE, DARKSLATEBLUE, DARKKHAKI, NUM_COLOR};$/;" e enum:color_types +NUM_FONT_TYPES base/graphics.c 2781;" d file: +NUM_MODELS_IN_LIBRARY ../../libarchfpga/include/read_xml_arch_file.h 14;" d +NUM_RR_TYPES base/vpr_types.h /^ SOURCE = 0, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_CLUSTER_EDGE, NUM_RR_TYPES$/;" e enum:e_rr_type +NUM_TYPES_USED place/timing_place_lookup.c 59;" d file: +NetFile base/ReadOptions.h /^ char *NetFile;$/;" m struct:s_options +NetFile base/vpr_types.h /^ char *NetFile;$/;" m struct:s_file_name_opts +OFF base/graphics.c 1362;" d file: +ON base/graphics.c 1363;" d file: +OPEN ../../libarchfpga/include/physical_types.h /^ OPEN = -1, DRIVER = 0, RECEIVER = 1$/;" e enum:e_pin_type +OPEN timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: +OPIN base/vpr_types.h /^ SOURCE = 0, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_CLUSTER_EDGE, NUM_RR_TYPES$/;" e enum:e_rr_type +OPIN_COST_INDEX base/vpr_types.h /^ OPIN_COST_INDEX,$/;" e enum:e_cost_indices +OPTIONTOKENS_H base/OptionTokens.h 2;" d +OT_ACC_FAC base/OptionTokens.h /^ OT_ACC_FAC,$/;" e enum:e_OptionBaseToken +OT_ACTIVITY_FILE base/OptionTokens.h /^ OT_ACTIVITY_FILE,$/;" e enum:e_OptionBaseToken +OT_ALLOW_EARLY_EXIT base/OptionTokens.h /^ OT_ALLOW_EARLY_EXIT,$/;" e enum:e_OptionBaseToken +OT_ALLOW_UNRELATED_CLUSTERING base/OptionTokens.h /^ OT_ALLOW_UNRELATED_CLUSTERING,$/;" e enum:e_OptionBaseToken +OT_ALPHA_CLUSTERING base/OptionTokens.h /^ OT_ALPHA_CLUSTERING,$/;" e enum:e_OptionBaseToken +OT_ALPHA_T base/OptionTokens.h /^ OT_ALPHA_T,$/;" e enum:e_OptionBaseToken +OT_ARG_UNKNOWN base/OptionTokens.h /^ OT_ARG_UNKNOWN \/* Must be last since used for counting enum items *\/$/;" e enum:e_OptionArgToken +OT_ASTAR_FAC base/OptionTokens.h /^ OT_ASTAR_FAC,$/;" e enum:e_OptionBaseToken +OT_AUTO base/OptionTokens.h /^ OT_AUTO,$/;" e enum:e_OptionBaseToken +OT_BASE_COST_TYPE base/OptionTokens.h /^ OT_BASE_COST_TYPE,$/;" e enum:e_OptionBaseToken +OT_BASE_UNKNOWN base/OptionTokens.h /^ OT_BASE_UNKNOWN \/* Must be last since used for counting enum items *\/$/;" e enum:e_OptionBaseToken +OT_BB_FACTOR base/OptionTokens.h /^ OT_BB_FACTOR,$/;" e enum:e_OptionBaseToken +OT_BEND_COST base/OptionTokens.h /^ OT_BEND_COST,$/;" e enum:e_OptionBaseToken +OT_BETA_CLUSTERING base/OptionTokens.h /^ OT_BETA_CLUSTERING,$/;" e enum:e_OptionBaseToken +OT_BLIF_FILE base/OptionTokens.h /^ OT_BLIF_FILE,$/;" e enum:e_OptionBaseToken +OT_BLOCK_DIST base/OptionTokens.h /^ OT_BLOCK_DIST,$/;" e enum:e_OptionBaseToken +OT_BOUNDING_BOX base/OptionTokens.h /^ OT_BOUNDING_BOX,$/;" e enum:e_OptionArgToken +OT_BREADTH_FIRST base/OptionTokens.h /^ OT_BREADTH_FIRST,$/;" e enum:e_OptionArgToken +OT_BRUTE_FORCE base/OptionTokens.h /^ OT_BRUTE_FORCE,$/;" e enum:e_OptionArgToken +OT_CLUSTER_BLOCK_DELAY base/OptionTokens.h /^ OT_CLUSTER_BLOCK_DELAY,$/;" e enum:e_OptionBaseToken +OT_CLUSTER_SEED base/OptionTokens.h /^ OT_CLUSTER_SEED,$/;" e enum:e_OptionBaseToken +OT_CMOS_TECH_BEHAVIOR_FILE base/OptionTokens.h /^ OT_CMOS_TECH_BEHAVIOR_FILE,$/;" e enum:e_OptionBaseToken +OT_CONNECTION_DRIVEN_CLUSTERING base/OptionTokens.h /^ OT_CONNECTION_DRIVEN_CLUSTERING,$/;" e enum:e_OptionBaseToken +OT_CREATE_ECHO_FILE base/OptionTokens.h /^ OT_CREATE_ECHO_FILE,$/;" e enum:e_OptionBaseToken +OT_CRITICALITY_EXP base/OptionTokens.h /^ OT_CRITICALITY_EXP,$/;" e enum:e_OptionBaseToken +OT_DELAY_NORMALIZED base/OptionTokens.h /^ OT_DELAY_NORMALIZED,$/;" e enum:e_OptionArgToken +OT_DEMAND_ONLY base/OptionTokens.h /^ OT_DEMAND_ONLY,$/;" e enum:e_OptionArgToken +OT_DETAILED base/OptionTokens.h /^ OT_DETAILED,$/;" e enum:e_OptionArgToken +OT_ENABLE_TIMING_COMPUTATIONS base/OptionTokens.h /^ OT_ENABLE_TIMING_COMPUTATIONS,$/;" e enum:e_OptionBaseToken +OT_EXIT_T base/OptionTokens.h /^ OT_EXIT_T,$/;" e enum:e_OptionBaseToken +OT_FAST base/OptionTokens.h /^ OT_FAST,$/;" e enum:e_OptionBaseToken +OT_FIRST_ITER_PRES_FAC base/OptionTokens.h /^ OT_FIRST_ITER_PRES_FAC,$/;" e enum:e_OptionBaseToken +OT_FIX_PINS base/OptionTokens.h /^ OT_FIX_PINS,$/;" e enum:e_OptionBaseToken +OT_FPGA_SPICE base/OptionTokens.h /^ OT_FPGA_SPICE, \/* Xifan TANG: FPGA SPICE Model Support *\/$/;" e enum:e_OptionBaseToken +OT_FPGA_SPICE_LEAKAGE_ONLY base/OptionTokens.h /^ OT_FPGA_SPICE_LEAKAGE_ONLY, \/* Xifan TANG: Print SPICE Testbench for MUXes *\/$/;" e enum:e_OptionBaseToken +OT_FPGA_SPICE_PARASITIC_NET_ESTIMATION_OFF base/OptionTokens.h /^ OT_FPGA_SPICE_PARASITIC_NET_ESTIMATION_OFF, \/* Xifan TANG: turn off the parasitic net estimation*\/$/;" e enum:e_OptionBaseToken +OT_FPGA_SPICE_RENAME_ILLEGAL_PORT base/OptionTokens.h /^ OT_FPGA_SPICE_RENAME_ILLEGAL_PORT, $/;" e enum:e_OptionBaseToken +OT_FPGA_SPICE_SIGNAL_DENSITY_WEIGHT base/OptionTokens.h /^ OT_FPGA_SPICE_SIGNAL_DENSITY_WEIGHT, \/* The weight of signal density in determining number of clock cycles in simulation *\/$/;" e enum:e_OptionBaseToken +OT_FPGA_SPICE_SIM_MT_NUM base/OptionTokens.h /^ OT_FPGA_SPICE_SIM_MT_NUM, \/* number of multi-thread used in simulation *\/$/;" e enum:e_OptionBaseToken +OT_FPGA_SPICE_SIM_WINDOW_SIZE base/OptionTokens.h /^ OT_FPGA_SPICE_SIM_WINDOW_SIZE, \/* Window size in determining number of clock cycles in simulation *\/$/;" e enum:e_OptionBaseToken +OT_FPGA_SPICE_TESTBENCH_LOAD_EXTRACTION_OFF base/OptionTokens.h /^ OT_FPGA_SPICE_TESTBENCH_LOAD_EXTRACTION_OFF, \/* Xifan TANG: turn off the testbench load extraction *\/$/;" e enum:e_OptionBaseToken +OT_FPGA_VERILOG_SYN base/OptionTokens.h /^ OT_FPGA_VERILOG_SYN, \/* Xifan TANG: Synthesizable Verilog Dump *\/$/;" e enum:e_OptionBaseToken +OT_FPGA_VERILOG_SYN_DIR base/OptionTokens.h /^ OT_FPGA_VERILOG_SYN_DIR, \/* Xifan TANG: Synthesizable Verilog Dump *\/$/;" e enum:e_OptionBaseToken +OT_FPGA_VERILOG_SYN_TB_SERIAL_CONFIG_MODE base/OptionTokens.h /^ OT_FPGA_VERILOG_SYN_TB_SERIAL_CONFIG_MODE, \/* Xifan TANG: Synthesizable Verilog Dump *\/$/;" e enum:e_OptionBaseToken +OT_FULL_STATS base/OptionTokens.h /^ OT_FULL_STATS,$/;" e enum:e_OptionBaseToken +OT_GENERATE_POST_SYNTHESIS_NETLIST base/OptionTokens.h /^ OT_GENERATE_POST_SYNTHESIS_NETLIST,$/;" e enum:e_OptionBaseToken +OT_GLOBAL base/OptionTokens.h /^ OT_GLOBAL,$/;" e enum:e_OptionArgToken +OT_GLOBAL_CLOCKS base/OptionTokens.h /^ OT_GLOBAL_CLOCKS,$/;" e enum:e_OptionBaseToken +OT_GREEDY base/OptionTokens.h /^ OT_GREEDY,$/;" e enum:e_OptionArgToken +OT_HILL_CLIMBING_FLAG base/OptionTokens.h /^ OT_HILL_CLIMBING_FLAG,$/;" e enum:e_OptionBaseToken +OT_INITIAL_PRES_FAC base/OptionTokens.h /^ OT_INITIAL_PRES_FAC,$/;" e enum:e_OptionBaseToken +OT_INIT_T base/OptionTokens.h /^ OT_INIT_T,$/;" e enum:e_OptionBaseToken +OT_INNER_LOOP_RECOMPUTE_DIVIDER base/OptionTokens.h /^ OT_INNER_LOOP_RECOMPUTE_DIVIDER,$/;" e enum:e_OptionBaseToken +OT_INNER_NUM base/OptionTokens.h /^ OT_INNER_NUM,$/;" e enum:e_OptionBaseToken +OT_INTER_CLUSTER_NET_DELAY base/OptionTokens.h /^ OT_INTER_CLUSTER_NET_DELAY,$/;" e enum:e_OptionBaseToken +OT_INTRA_CLUSTER_NET_DELAY base/OptionTokens.h /^ OT_INTRA_CLUSTER_NET_DELAY,$/;" e enum:e_OptionBaseToken +OT_INTRINSIC_DELAY base/OptionTokens.h /^ OT_INTRINSIC_DELAY,$/;" e enum:e_OptionArgToken +OT_LP base/OptionTokens.h /^ OT_LP,$/;" e enum:e_OptionArgToken +OT_MAX_CRITICALITY base/OptionTokens.h /^ OT_MAX_CRITICALITY,$/;" e enum:e_OptionBaseToken +OT_MAX_INPUTS base/OptionTokens.h /^ OT_MAX_INPUTS,$/;" e enum:e_OptionArgToken +OT_MAX_ROUTER_ITERATIONS base/OptionTokens.h /^ OT_MAX_ROUTER_ITERATIONS,$/;" e enum:e_OptionBaseToken +OT_NET_FILE base/OptionTokens.h /^ OT_NET_FILE,$/;" e enum:e_OptionBaseToken +OT_NET_TIMING_DRIVEN base/OptionTokens.h /^ OT_NET_TIMING_DRIVEN,$/;" e enum:e_OptionArgToken +OT_NODISP base/OptionTokens.h /^ OT_NODISP,$/;" e enum:e_OptionBaseToken +OT_NO_TIMING base/OptionTokens.h /^ OT_NO_TIMING,$/;" e enum:e_OptionArgToken +OT_OFF base/OptionTokens.h /^ OT_OFF,$/;" e enum:e_OptionArgToken +OT_ON base/OptionTokens.h /^ OT_ON,$/;" e enum:e_OptionArgToken +OT_OUTFILE_PREFIX base/OptionTokens.h /^ OT_OUTFILE_PREFIX,$/;" e enum:e_OptionBaseToken +OT_PACK base/OptionTokens.h /^ OT_PACK,$/;" e enum:e_OptionBaseToken +OT_PACKER_ALGORITHM base/OptionTokens.h /^ OT_PACKER_ALGORITHM,$/;" e enum:e_OptionBaseToken +OT_PACK_CLB_PIN_REMAP base/OptionTokens.h /^ OT_PACK_CLB_PIN_REMAP,$/;" e enum:e_OptionBaseToken +OT_PATH_TIMING_DRIVEN base/OptionTokens.h /^ OT_PATH_TIMING_DRIVEN,$/;" e enum:e_OptionArgToken +OT_PLACE base/OptionTokens.h /^ OT_PLACE,$/;" e enum:e_OptionBaseToken +OT_PLACE_ALGORITHM base/OptionTokens.h /^ OT_PLACE_ALGORITHM,$/;" e enum:e_OptionBaseToken +OT_PLACE_CHAN_WIDTH base/OptionTokens.h /^ OT_PLACE_CHAN_WIDTH,$/;" e enum:e_OptionBaseToken +OT_PLACE_CLB_PIN_REMAP base/OptionTokens.h /^ OT_PLACE_CLB_PIN_REMAP,$/;" e enum:e_OptionBaseToken +OT_PLACE_COST_EXP base/OptionTokens.h /^ OT_PLACE_COST_EXP,$/;" e enum:e_OptionBaseToken +OT_PLACE_FILE base/OptionTokens.h /^ OT_PLACE_FILE,$/;" e enum:e_OptionBaseToken +OT_POWER base/OptionTokens.h /^ OT_POWER,$/;" e enum:e_OptionBaseToken +OT_POWER_OUT_FILE base/OptionTokens.h /^ OT_POWER_OUT_FILE,$/;" e enum:e_OptionBaseToken +OT_PRES_FAC_MULT base/OptionTokens.h /^ OT_PRES_FAC_MULT,$/;" e enum:e_OptionBaseToken +OT_RANDOM base/OptionTokens.h /^ OT_RANDOM,$/;" e enum:e_OptionArgToken +OT_READ_PLACE_ONLY base/OptionTokens.h /^ OT_READ_PLACE_ONLY,$/;" e enum:e_OptionBaseToken +OT_RECOMPUTE_CRIT_ITER base/OptionTokens.h /^ OT_RECOMPUTE_CRIT_ITER,$/;" e enum:e_OptionBaseToken +OT_RECOMPUTE_TIMING_AFTER base/OptionTokens.h /^ OT_RECOMPUTE_TIMING_AFTER,$/;" e enum:e_OptionBaseToken +OT_ROUTE base/OptionTokens.h /^ OT_ROUTE,$/;" e enum:e_OptionBaseToken +OT_ROUTER_ALGORITHM base/OptionTokens.h /^ OT_ROUTER_ALGORITHM,$/;" e enum:e_OptionBaseToken +OT_ROUTE_CHAN_WIDTH base/OptionTokens.h /^ OT_ROUTE_CHAN_WIDTH,$/;" e enum:e_OptionBaseToken +OT_ROUTE_FILE base/OptionTokens.h /^ OT_ROUTE_FILE,$/;" e enum:e_OptionBaseToken +OT_ROUTE_TYPE base/OptionTokens.h /^ OT_ROUTE_TYPE,$/;" e enum:e_OptionBaseToken +OT_SDC_FILE base/OptionTokens.h /^ OT_SDC_FILE,$/;" e enum:e_OptionBaseToken +OT_SEED base/OptionTokens.h /^ OT_SEED,$/;" e enum:e_OptionBaseToken +OT_SETTINGS_FILE base/OptionTokens.h /^ OT_SETTINGS_FILE,$/;" e enum:e_OptionBaseToken +OT_SHOW_PASS_TRANS base/OptionTokens.h /^ OT_SHOW_PASS_TRANS,$/;" e enum:e_OptionBaseToken +OT_SHOW_SRAM base/OptionTokens.h /^ OT_SHOW_SRAM,$/;" e enum:e_OptionBaseToken +OT_SKIP_CLUSTERING base/OptionTokens.h /^ OT_SKIP_CLUSTERING,$/;" e enum:e_OptionBaseToken +OT_SPICE_DIR base/OptionTokens.h /^ OT_SPICE_DIR, \/* Xifan TANG: FPGA SPICE Model Support *\/$/;" e enum:e_OptionBaseToken +OT_SPICE_PRINT_CB_MUX_TESTBENCH base/OptionTokens.h /^ OT_SPICE_PRINT_CB_MUX_TESTBENCH, \/* Xifan TANG: Print SPICE Testbench for MUXes *\/$/;" e enum:e_OptionBaseToken +OT_SPICE_PRINT_CB_TESTBENCH base/OptionTokens.h /^ OT_SPICE_PRINT_CB_TESTBENCH, \/* Xifan TANG: Print SPICE Testbench for CBs *\/$/;" e enum:e_OptionBaseToken +OT_SPICE_PRINT_GRID_TESTBENCH base/OptionTokens.h /^ OT_SPICE_PRINT_GRID_TESTBENCH, \/* Xifan TANG: Print SPICE Testbench for Grids *\/$/;" e enum:e_OptionBaseToken +OT_SPICE_PRINT_HARDLOGIC_TESTBENCH base/OptionTokens.h /^ OT_SPICE_PRINT_HARDLOGIC_TESTBENCH, \/* Xifan TANG: Print SPICE Testbench for hard logic s *\/$/;" e enum:e_OptionBaseToken +OT_SPICE_PRINT_LUT_TESTBENCH base/OptionTokens.h /^ OT_SPICE_PRINT_LUT_TESTBENCH, \/* Xifan TANG: Print SPICE Testbench for LUTs *\/$/;" e enum:e_OptionBaseToken +OT_SPICE_PRINT_PB_MUX_TESTBENCH base/OptionTokens.h /^ OT_SPICE_PRINT_PB_MUX_TESTBENCH, \/* Xifan TANG: Print SPICE Testbench for MUXes *\/$/;" e enum:e_OptionBaseToken +OT_SPICE_PRINT_SB_MUX_TESTBENCH base/OptionTokens.h /^ OT_SPICE_PRINT_SB_MUX_TESTBENCH, \/* Xifan TANG: Print SPICE Testbench for MUXes *\/$/;" e enum:e_OptionBaseToken +OT_SPICE_PRINT_SB_TESTBENCH base/OptionTokens.h /^ OT_SPICE_PRINT_SB_TESTBENCH, \/* Xifan TANG: Print SPICE Testbench for SBs *\/$/;" e enum:e_OptionBaseToken +OT_SPICE_PRINT_TOP_TESTBENCH base/OptionTokens.h /^ OT_SPICE_PRINT_TOP_TESTBENCH, \/* Xifan TANG: Print Top-level SPICE Testbench *\/$/;" e enum:e_OptionBaseToken +OT_SWEEP_HANGING_NETS_AND_INPUTS base/OptionTokens.h /^ OT_SWEEP_HANGING_NETS_AND_INPUTS,$/;" e enum:e_OptionBaseToken +OT_TD_PLACE_EXP_FIRST base/OptionTokens.h /^ OT_TD_PLACE_EXP_FIRST,$/;" e enum:e_OptionBaseToken +OT_TD_PLACE_EXP_LAST base/OptionTokens.h /^ OT_TD_PLACE_EXP_LAST,$/;" e enum:e_OptionBaseToken +OT_TIMING base/OptionTokens.h /^ OT_TIMING,$/;" e enum:e_OptionArgToken +OT_TIMING_ANALYSIS base/OptionTokens.h /^ OT_TIMING_ANALYSIS,$/;" e enum:e_OptionBaseToken +OT_TIMING_ANALYZE_ONLY_WITH_NET_DELAY base/OptionTokens.h /^ OT_TIMING_ANALYZE_ONLY_WITH_NET_DELAY,$/;" e enum:e_OptionBaseToken +OT_TIMING_DRIVEN base/OptionTokens.h /^ OT_TIMING_DRIVEN,$/;" e enum:e_OptionArgToken +OT_TIMING_DRIVEN_CLUSTERING base/OptionTokens.h /^ OT_TIMING_DRIVEN_CLUSTERING,$/;" e enum:e_OptionBaseToken +OT_TIMING_TRADEOFF base/OptionTokens.h /^ OT_TIMING_TRADEOFF,$/;" e enum:e_OptionBaseToken +OT_VERIFY_BINARY_SEARCH base/OptionTokens.h /^ OT_VERIFY_BINARY_SEARCH,$/;" e enum:e_OptionBaseToken +OUTP ../../libarchfpga/include/util.h 20;" d +OUTPUT pack/cluster.c /^ INPUT, OUTPUT$/;" e enum:e_net_relation_to_clustered_block file: +OUTPUT2OUTPUT_INTERC fpga_spice/fpga_spice_globals.h /^ INPUT2INPUT_INTERC, OUTPUT2OUTPUT_INTERC$/;" e enum:e_pin2pin_interc_type +OUT_PORT ../../libarchfpga/include/logic_types.h /^ IN_PORT, OUT_PORT, INOUT_PORT, ERR_PORT$/;" e enum:PORTS +Operation base/vpr_types.h /^ enum e_operation Operation; \/* run VPR or do analysis only *\/$/;" m struct:s_vpr_setup typeref:enum:s_vpr_setup::e_operation +OptionArgTokenList base/OptionTokens.c /^struct s_TokenPair OptionArgTokenList[] = { { "on", OT_ON }, { "off", OT_OFF },$/;" v typeref:struct:s_TokenPair +OptionBaseTokenList base/OptionTokens.c /^struct s_TokenPair OptionBaseTokenList[] = {$/;" v typeref:struct:s_TokenPair +PACK_BRUTE_FORCE base/vpr_types.h /^ PACK_GREEDY, PACK_BRUTE_FORCE$/;" e enum:e_packer_algorithm +PACK_GREEDY base/vpr_types.h /^ PACK_GREEDY, PACK_BRUTE_FORCE$/;" e enum:e_packer_algorithm +PACK_PATH_WEIGHT timing/path_delay.h 34;" d +PALCE_MACRO_H place/place_macro.h 136;" d +PATH_DELAY timing/path_delay.h 2;" d +PATH_TIMING_DRIVEN_PLACE base/vpr_types.h /^ BOUNDING_BOX_PLACE, NET_TIMING_DRIVEN_PLACE, PATH_TIMING_DRIVEN_PLACE$/;" e enum:e_place_algorithm +PB_PIN_CLOCK ../../libarchfpga/include/physical_types.h /^ PB_PIN_CLOCK$/;" e enum:e_pb_graph_pin_type +PB_PIN_EQ_AUTO_DETECT_H route/pb_pin_eq_auto_detect.h 3;" d +PB_PIN_INPAD ../../libarchfpga/include/physical_types.h /^ PB_PIN_INPAD,$/;" e enum:e_pb_graph_pin_type +PB_PIN_NORMAL ../../libarchfpga/include/physical_types.h /^ PB_PIN_NORMAL = 0,$/;" e enum:e_pb_graph_pin_type +PB_PIN_OUTPAD ../../libarchfpga/include/physical_types.h /^ PB_PIN_OUTPAD,$/;" e enum:e_pb_graph_pin_type +PB_PIN_SEQUENTIAL ../../libarchfpga/include/physical_types.h /^ PB_PIN_SEQUENTIAL,$/;" e enum:e_pb_graph_pin_type +PB_PIN_TERMINAL ../../libarchfpga/include/physical_types.h /^ PB_PIN_TERMINAL,$/;" e enum:e_pb_graph_pin_type +PB_TYPE_GRAPH_ANNOTATIONS_H pack/pb_type_graph_annotations.h 8;" d +PB_TYPE_GRAPH_H pack/pb_type_graph.h 2;" d +PCRAM_Pierre ../../libarchfpga/include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp +PCRAM_Xie ../../libarchfpga/include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp +PHYSICAL_TYPES_H ../../libarchfpga/include/physical_types.h 27;" d +PI base/graphics.c 181;" d file: +PLACEMENT base/vpr_types.h /^ NO_PICTURE, PLACEMENT, ROUTING$/;" e enum:pic_type +PLACE_ALWAYS base/vpr_types.h /^ PLACE_NEVER, PLACE_ONCE, PLACE_ALWAYS$/;" e enum:pfreq +PLACE_NEVER base/vpr_types.h /^ PLACE_NEVER, PLACE_ONCE, PLACE_ALWAYS$/;" e enum:pfreq +PLACE_ONCE base/vpr_types.h /^ PLACE_NEVER, PLACE_ONCE, PLACE_ALWAYS$/;" e enum:pfreq +PLACE_PATH_WEIGHT timing/path_delay.h 36;" d +PLUM base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types +PLUS timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: +PLUSQ timing/slre.c /^ STARQ, PLUSQ, QUEST, SPACE, NONSPACE, DIGIT$/;" e enum:__anon19 file: +PMOS power/power.h /^ NMOS, PMOS$/;" e enum:__anon11 +PMOS_1X_C_d power/power.h /^ float PMOS_1X_C_d;$/;" m struct:s_power_commonly_used +PMOS_1X_C_g power/power.h /^ float PMOS_1X_C_g;$/;" m struct:s_power_commonly_used +PMOS_1X_C_s power/power.h /^ float PMOS_1X_C_s;$/;" m struct:s_power_commonly_used +PMOS_1X_st_leakage power/power.h /^ float PMOS_1X_st_leakage;$/;" m struct:s_power_commonly_used +PMOS_2X_st_leakage power/power.h /^ float PMOS_2X_st_leakage;$/;" m struct:s_power_commonly_used +PMOS_inf power/power.h /^ t_transistor_inf PMOS_inf;$/;" m struct:s_power_tech +PN_ratio power/power.h /^ float PN_ratio; \/* Ratio of PMOS to NMOS in inverter *\/$/;" m struct:s_power_tech +PORTS ../../libarchfpga/include/logic_types.h /^enum PORTS {$/;" g +POSTSCRIPT base/graphics.c /^ POSTSCRIPT = 1$/;" e enum:__anon2 file: +POWER_BREAKDOWN_ENTRY_TYPE_BUFS_WIRES power/power.c /^ POWER_BREAKDOWN_ENTRY_TYPE_BUFS_WIRES$/;" e enum:__anon8 file: +POWER_BREAKDOWN_ENTRY_TYPE_COMPONENT power/power.c /^ POWER_BREAKDOWN_ENTRY_TYPE_COMPONENT,$/;" e enum:__anon8 file: +POWER_BREAKDOWN_ENTRY_TYPE_INTERC power/power.c /^ POWER_BREAKDOWN_ENTRY_TYPE_INTERC,$/;" e enum:__anon8 file: +POWER_BREAKDOWN_ENTRY_TYPE_MODE power/power.c /^ POWER_BREAKDOWN_ENTRY_TYPE_MODE,$/;" e enum:__anon8 file: +POWER_BREAKDOWN_ENTRY_TYPE_PB power/power.c /^ POWER_BREAKDOWN_ENTRY_TYPE_PB,$/;" e enum:__anon8 file: +POWER_BREAKDOWN_ENTRY_TYPE_TITLE power/power.c /^ POWER_BREAKDOWN_ENTRY_TYPE_TITLE = 0,$/;" e enum:__anon8 file: +POWER_BUFFER_TYPE_ABSOLUTE_SIZE ../../libarchfpga/include/physical_types.h /^ POWER_BUFFER_TYPE_ABSOLUTE_SIZE$/;" e enum:__anon21 +POWER_BUFFER_TYPE_AUTO ../../libarchfpga/include/physical_types.h /^ POWER_BUFFER_TYPE_AUTO,$/;" e enum:__anon21 +POWER_BUFFER_TYPE_NONE ../../libarchfpga/include/physical_types.h /^ POWER_BUFFER_TYPE_NONE,$/;" e enum:__anon21 +POWER_BUFFER_TYPE_UNDEFINED ../../libarchfpga/include/physical_types.h /^ POWER_BUFFER_TYPE_UNDEFINED = 0,$/;" e enum:__anon21 +POWER_CALLIB_COMPONENT_BUFFER power/power_callibrate.h /^ POWER_CALLIB_COMPONENT_BUFFER = 0,$/;" e enum:__anon12 +POWER_CALLIB_COMPONENT_BUFFER_WITH_LEVR power/power_callibrate.h /^ POWER_CALLIB_COMPONENT_BUFFER_WITH_LEVR,$/;" e enum:__anon12 +POWER_CALLIB_COMPONENT_FF power/power_callibrate.h /^ POWER_CALLIB_COMPONENT_FF,$/;" e enum:__anon12 +POWER_CALLIB_COMPONENT_LUT power/power_callibrate.h /^ POWER_CALLIB_COMPONENT_LUT,$/;" e enum:__anon12 +POWER_CALLIB_COMPONENT_MAX power/power_callibrate.h /^ POWER_CALLIB_COMPONENT_MAX$/;" e enum:__anon12 +POWER_CALLIB_COMPONENT_MUX power/power_callibrate.h /^ POWER_CALLIB_COMPONENT_MUX,$/;" e enum:__anon12 +POWER_COMPONENT_CLOCK power/power_components.h /^ POWER_COMPONENT_CLOCK, \/* Clock network *\/$/;" e enum:__anon13 +POWER_COMPONENT_CLOCK_BUFFER power/power_components.h /^ POWER_COMPONENT_CLOCK_BUFFER, \/* Buffers in clock network *\/$/;" e enum:__anon13 +POWER_COMPONENT_CLOCK_WIRE power/power_components.h /^ POWER_COMPONENT_CLOCK_WIRE, \/* Wires in clock network *\/$/;" e enum:__anon13 +POWER_COMPONENT_IGNORE power/power_components.h /^ POWER_COMPONENT_IGNORE = 0, \/* *\/$/;" e enum:__anon13 +POWER_COMPONENT_MAX_NUM power/power_components.h /^ POWER_COMPONENT_MAX_NUM$/;" e enum:__anon13 +POWER_COMPONENT_PB power/power_components.h /^ POWER_COMPONENT_PB, \/* Logic Blocks, and other hard blocks *\/$/;" e enum:__anon13 +POWER_COMPONENT_PB_BUFS_WIRE power/power_components.h /^ POWER_COMPONENT_PB_BUFS_WIRE, \/* Local buffers and wire capacitance *\/$/;" e enum:__anon13 +POWER_COMPONENT_PB_INTERC_MUXES power/power_components.h /^ POWER_COMPONENT_PB_INTERC_MUXES, \/* Local interconnect structures (muxes) *\/$/;" e enum:__anon13 +POWER_COMPONENT_PB_OTHER power/power_components.h /^ POWER_COMPONENT_PB_OTHER, \/* Power from other estimation methods - not transistor-level *\/$/;" e enum:__anon13 +POWER_COMPONENT_PB_PRIMITIVES power/power_components.h /^ POWER_COMPONENT_PB_PRIMITIVES, \/* Primitives (LUTs, FF, etc) *\/$/;" e enum:__anon13 +POWER_COMPONENT_ROUTE_CB power/power_components.h /^ POWER_COMPONENT_ROUTE_CB, \/* Connection box*\/$/;" e enum:__anon13 +POWER_COMPONENT_ROUTE_GLB_WIRE power/power_components.h /^ POWER_COMPONENT_ROUTE_GLB_WIRE, \/* Wires *\/$/;" e enum:__anon13 +POWER_COMPONENT_ROUTE_SB power/power_components.h /^ POWER_COMPONENT_ROUTE_SB, \/* Switch-box *\/$/;" e enum:__anon13 +POWER_COMPONENT_ROUTING power/power_components.h /^ POWER_COMPONENT_ROUTING, \/* Power for routing fabric (not local routing) *\/$/;" e enum:__anon13 +POWER_COMPONENT_TOTAL power/power_components.h /^ POWER_COMPONENT_TOTAL, \/* Total power for entire FPGA *\/$/;" e enum:__anon13 +POWER_DRC_MIN_DIFF_L power/power_sizing.h 34;" d +POWER_DRC_MIN_L power/power_sizing.h 32;" d +POWER_DRC_MIN_W power/power_sizing.h 33;" d +POWER_DRC_POLY_OVERHANG power/power_sizing.h 36;" d +POWER_DRC_SPACING power/power_sizing.h 35;" d +POWER_LOG_ERROR power/power.h /^ POWER_LOG_ERROR, POWER_LOG_WARNING, POWER_LOG_NUM_TYPES$/;" e enum:__anon10 +POWER_LOG_NUM_TYPES power/power.h /^ POWER_LOG_ERROR, POWER_LOG_WARNING, POWER_LOG_NUM_TYPES$/;" e enum:__anon10 +POWER_LOG_WARNING power/power.h /^ POWER_LOG_ERROR, POWER_LOG_WARNING, POWER_LOG_NUM_TYPES$/;" e enum:__anon10 +POWER_LUT_SLOW power/power_components.h 37;" d +POWER_LUT_SLOW power/power_components.h 39;" d +POWER_METHOD_ABSOLUTE ../../libarchfpga/include/physical_types.h /^ POWER_METHOD_ABSOLUTE \/* Dynamic: Aboslute, Static: Absolute *\/$/;" e enum:e_power_estimation_method_ +POWER_METHOD_AUTO_SIZES ../../libarchfpga/include/physical_types.h /^ POWER_METHOD_AUTO_SIZES, \/* Transistor-level, auto-sized buffers\/wires *\/$/;" e enum:e_power_estimation_method_ +POWER_METHOD_C_INTERNAL ../../libarchfpga/include/physical_types.h /^ POWER_METHOD_C_INTERNAL, \/* Dynamic: Equiv. Internal capacitance, Static: Absolute *\/$/;" e enum:e_power_estimation_method_ +POWER_METHOD_IGNORE ../../libarchfpga/include/physical_types.h /^ POWER_METHOD_UNDEFINED = 0, POWER_METHOD_IGNORE, \/* Ignore power of this PB, and all children PB *\/$/;" e enum:e_power_estimation_method_ +POWER_METHOD_SPECIFY_SIZES ../../libarchfpga/include/physical_types.h /^ POWER_METHOD_SPECIFY_SIZES, \/* Transistor-level, user-specified buffers\/wires *\/$/;" e enum:e_power_estimation_method_ +POWER_METHOD_SUM_OF_CHILDREN ../../libarchfpga/include/physical_types.h /^ POWER_METHOD_SUM_OF_CHILDREN, \/* Ignore power of this PB, but consider children *\/$/;" e enum:e_power_estimation_method_ +POWER_METHOD_TOGGLE_PINS ../../libarchfpga/include/physical_types.h /^ POWER_METHOD_TOGGLE_PINS, \/* Dynamic: Energy per pin toggle, Static: Absolute *\/$/;" e enum:e_power_estimation_method_ +POWER_METHOD_UNDEFINED ../../libarchfpga/include/physical_types.h /^ POWER_METHOD_UNDEFINED = 0, POWER_METHOD_IGNORE, \/* Ignore power of this PB, and all children PB *\/$/;" e enum:e_power_estimation_method_ +POWER_MTA_L power/power_sizing.h 39;" d +POWER_MTA_W power/power_sizing.h 38;" d +POWER_RET_CODE_ERRORS power/power.h /^ POWER_RET_CODE_SUCCESS = 0, POWER_RET_CODE_ERRORS, POWER_RET_CODE_WARNINGS$/;" e enum:__anon9 +POWER_RET_CODE_SUCCESS power/power.h /^ POWER_RET_CODE_SUCCESS = 0, POWER_RET_CODE_ERRORS, POWER_RET_CODE_WARNINGS$/;" e enum:__anon9 +POWER_RET_CODE_WARNINGS power/power.h /^ POWER_RET_CODE_SUCCESS = 0, POWER_RET_CODE_ERRORS, POWER_RET_CODE_WARNINGS$/;" e enum:__anon9 +POWER_WIRE_TYPE_ABSOLUTE_LENGTH ../../libarchfpga/include/physical_types.h /^ POWER_WIRE_TYPE_ABSOLUTE_LENGTH,$/;" e enum:__anon20 +POWER_WIRE_TYPE_AUTO ../../libarchfpga/include/physical_types.h /^ POWER_WIRE_TYPE_AUTO$/;" e enum:__anon20 +POWER_WIRE_TYPE_C ../../libarchfpga/include/physical_types.h /^ POWER_WIRE_TYPE_C,$/;" e enum:__anon20 +POWER_WIRE_TYPE_IGNORED ../../libarchfpga/include/physical_types.h /^ POWER_WIRE_TYPE_IGNORED,$/;" e enum:__anon20 +POWER_WIRE_TYPE_RELATIVE_LENGTH ../../libarchfpga/include/physical_types.h /^ POWER_WIRE_TYPE_RELATIVE_LENGTH,$/;" e enum:__anon20 +POWER_WIRE_TYPE_UNDEFINED ../../libarchfpga/include/physical_types.h /^ POWER_WIRE_TYPE_UNDEFINED = 0,$/;" e enum:__anon20 +PREPACK_H pack/prepack.h 8;" d +PROC_TIME base/place_and_route.h 6;" d +PTRANS_FLAG route/check_rr_graph.c 15;" d file: +PULSE ../../libarchfpga/include/physical_types.h /^ UNIFORM, GAUSSIAN, PULSE, DELTA$/;" e enum:e_stat +PackerOpts base/vpr_types.h /^ struct s_packer_opts PackerOpts; \/* Options for packer *\/$/;" m struct:s_vpr_setup typeref:struct:s_vpr_setup::s_packer_opts +PinFile base/ReadOptions.h /^ char *PinFile;$/;" m struct:s_options +PlaceAlgorithm base/ReadOptions.h /^ enum e_place_algorithm PlaceAlgorithm;$/;" m struct:s_options typeref:enum:s_options::e_place_algorithm +PlaceAlphaT base/ReadOptions.h /^ float PlaceAlphaT;$/;" m struct:s_options +PlaceChanWidth base/ReadOptions.h /^ int PlaceChanWidth;$/;" m struct:s_options +PlaceExitT base/ReadOptions.h /^ float PlaceExitT;$/;" m struct:s_options +PlaceFile base/ReadOptions.h /^ char *PlaceFile;$/;" m struct:s_options +PlaceFile base/vpr_types.h /^ char *PlaceFile;$/;" m struct:s_file_name_opts +PlaceInitT base/ReadOptions.h /^ float PlaceInitT;$/;" m struct:s_options +PlaceInnerNum base/ReadOptions.h /^ float PlaceInnerNum;$/;" m struct:s_options +PlaceTimingTradeoff base/ReadOptions.h /^ float PlaceTimingTradeoff;$/;" m struct:s_options +PlacerOpts base/vpr_types.h /^ struct s_placer_opts PlacerOpts; \/* Options for placer *\/$/;" m struct:s_vpr_setup typeref:struct:s_vpr_setup::s_placer_opts +PowerCallibInputs power/PowerSpicedComponent.c /^PowerCallibInputs::PowerCallibInputs(PowerSpicedComponent * parent_,$/;" f class:PowerCallibInputs +PowerCallibInputs power/PowerSpicedComponent.h /^class PowerCallibInputs {$/;" c +PowerCallibSize power/PowerSpicedComponent.h /^ PowerCallibSize(float size, float power_) :$/;" f class:PowerCallibSize +PowerCallibSize power/PowerSpicedComponent.h /^class PowerCallibSize {$/;" c +PowerFile base/ReadOptions.h /^ char *PowerFile;$/;" m struct:s_options +PowerFile base/vpr_types.h /^ char *PowerFile;$/;" m struct:s_file_name_opts +PowerOpts base/vpr_types.h /^ t_power_opts PowerOpts;$/;" m struct:s_vpr_setup +PowerSpicedComponent power/PowerSpicedComponent.c /^PowerSpicedComponent::PowerSpicedComponent($/;" f class:PowerSpicedComponent +PowerSpicedComponent power/PowerSpicedComponent.h /^class PowerSpicedComponent {$/;" c +PrintPb_types_rec ../../libarchfpga/read_xml_arch_file.c /^static void PrintPb_types_rec(INP FILE * Echo, INP const t_pb_type * pb_type,$/;" f file: +ProceedPressed base/graphics.c /^static int ProceedPressed;$/;" v file: +ProcessCB_SB ../../libarchfpga/read_xml_arch_file.c /^static void ProcessCB_SB(INOUTP ezxml_t Node, INOUTP boolean * list,$/;" f file: +ProcessChanWidthDistr ../../libarchfpga/read_xml_arch_file.c /^static void ProcessChanWidthDistr(INOUTP ezxml_t Node,$/;" f file: +ProcessChanWidthDistrDir ../../libarchfpga/read_xml_arch_file.c /^static void ProcessChanWidthDistrDir(INOUTP ezxml_t Node, OUTP t_chan * chan) {$/;" f file: +ProcessClocks ../../libarchfpga/read_xml_arch_file.c /^static void ProcessClocks(ezxml_t Parent, t_clock_arch * clocks) {$/;" f file: +ProcessComplexBlockProps ../../libarchfpga/read_xml_arch_file.c /^static void ProcessComplexBlockProps(ezxml_t Node, t_type_descriptor * Type) {$/;" f file: +ProcessComplexBlocks ../../libarchfpga/read_xml_arch_file.c /^static void ProcessComplexBlocks(INOUTP ezxml_t Node,$/;" f file: +ProcessDevice ../../libarchfpga/read_xml_arch_file.c /^static void ProcessDevice(INOUTP ezxml_t Node, OUTP struct s_arch *arch,$/;" f file: +ProcessDirects ../../libarchfpga/read_xml_arch_file.c /^static void ProcessDirects(INOUTP ezxml_t Parent, OUTP t_direct_inf **Directs,$/;" f file: +ProcessInterconnect ../../libarchfpga/read_xml_arch_file.c /^static void ProcessInterconnect(INOUTP ezxml_t Parent, t_mode * mode) {$/;" f file: +ProcessLayout ../../libarchfpga/read_xml_arch_file.c /^static void ProcessLayout(INOUTP ezxml_t Node, OUTP struct s_arch *arch) {$/;" f file: +ProcessLutClass ../../libarchfpga/read_xml_arch_file.c /^void ProcessLutClass(INOUTP t_pb_type *lut_pb_type) {$/;" f +ProcessMemoryClass ../../libarchfpga/read_xml_arch_file.c /^static void ProcessMemoryClass(INOUTP t_pb_type *mem_pb_type) {$/;" f file: +ProcessMode ../../libarchfpga/read_xml_arch_file.c /^static void ProcessMode(INOUTP ezxml_t Parent, t_mode * mode,$/;" f file: +ProcessModels ../../libarchfpga/read_xml_arch_file.c /^static void ProcessModels(INOUTP ezxml_t Node, OUTP struct s_arch *arch) {$/;" f file: +ProcessMrFPGATiming ../../libarchfpga/read_xml_mrfpga.c /^void ProcessMrFPGATiming(INOUTP ezxml_t Cur, $/;" f +ProcessOption base/ReadOptions.c /^ProcessOption(INP char **Args, INOUTP t_options * Options) {$/;" f file: +ProcessPb_Type ../../libarchfpga/read_xml_arch_file.c /^static void ProcessPb_Type(INOUTP ezxml_t Parent, t_pb_type * pb_type,$/;" f file: +ProcessPb_TypePort ../../libarchfpga/read_xml_arch_file.c /^static void ProcessPb_TypePort(INOUTP ezxml_t Parent, t_port * port,$/;" f file: +ProcessPb_TypePort_Power ../../libarchfpga/read_xml_arch_file.c /^static void ProcessPb_TypePort_Power(ezxml_t Parent, t_port * port,$/;" f file: +ProcessPb_TypePower ../../libarchfpga/read_xml_arch_file.c /^static void ProcessPb_TypePower(ezxml_t Parent, t_pb_type * pb_type) {$/;" f file: +ProcessPb_TypePowerEstMethod ../../libarchfpga/read_xml_arch_file.c /^static void ProcessPb_TypePowerEstMethod(ezxml_t Parent, t_pb_type * pb_type) {$/;" f file: +ProcessPb_TypePowerPinToggle ../../libarchfpga/read_xml_arch_file.c /^static void ProcessPb_TypePowerPinToggle(ezxml_t parent, t_pb_type * pb_type) {$/;" f file: +ProcessPinToPinAnnotations ../../libarchfpga/read_xml_arch_file.c /^static void ProcessPinToPinAnnotations(ezxml_t Parent,$/;" f file: +ProcessPower ../../libarchfpga/read_xml_arch_file.c /^static void ProcessPower( INOUTP ezxml_t parent,$/;" f file: +ProcessSegments ../../libarchfpga/read_xml_arch_file.c /^static void ProcessSegments(INOUTP ezxml_t Parent,$/;" f file: +ProcessSpiceMCVariationParams ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceMCVariationParams(ezxml_t Parent,$/;" f file: +ProcessSpiceMeasParams ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceMeasParams(ezxml_t Parent,$/;" f file: +ProcessSpiceModel ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceModel(ezxml_t Parent,$/;" f file: +ProcessSpiceModelBuffer ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceModelBuffer(ezxml_t Node,$/;" f file: +ProcessSpiceModelPassGateLogic ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceModelPassGateLogic(ezxml_t Node,$/;" f file: +ProcessSpiceModelPort ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceModelPort(ezxml_t Node,$/;" f file: +ProcessSpiceModelWireParam ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceModelWireParam(ezxml_t Parent,$/;" f file: +ProcessSpiceMonteCarloParams ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceMonteCarloParams(ezxml_t Parent, $/;" f file: +ProcessSpiceParams ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceParams(ezxml_t Parent,$/;" f file: +ProcessSpiceSRAM ../../libarchfpga/read_xml_spice.c /^void ProcessSpiceSRAM(INOUTP ezxml_t Node, OUTP struct s_arch* arch) {$/;" f +ProcessSpiceSRAMOrganization ../../libarchfpga/read_xml_spice.c /^void ProcessSpiceSRAMOrganization(INOUTP ezxml_t Node, $/;" f file: +ProcessSpiceSettings ../../libarchfpga/read_xml_spice.c /^void ProcessSpiceSettings(ezxml_t Parent,$/;" f +ProcessSpiceStimulateParams ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceStimulateParams(ezxml_t Parent,$/;" f file: +ProcessSpiceStimulateParamsRiseFall ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceStimulateParamsRiseFall(ezxml_t Parent,$/;" f file: +ProcessSpiceTechLibTransistors ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceTechLibTransistors(ezxml_t Parent,$/;" f file: +ProcessSpiceTransistorType ../../libarchfpga/read_xml_spice.c /^static void ProcessSpiceTransistorType(ezxml_t Parent,$/;" f file: +ProcessSwitchSegmentPatterns ../../libarchfpga/read_xml_arch_file.c /^static void ProcessSwitchSegmentPatterns(INOUTP ezxml_t Parent,$/;" f file: +ProcessSwitches ../../libarchfpga/read_xml_arch_file.c /^static void ProcessSwitches(INOUTP ezxml_t Parent,$/;" f file: +ProcessTechComp ../../libarchfpga/read_xml_mrfpga.c /^ProcessTechComp(INOUTP ezxml_t Node,$/;" f +ProcessTechHack ../../libarchfpga/read_xml_mrfpga.c /^ProcessTechHack(INOUTP ezxml_t Node,$/;" f +ProcessTechnology ../../libarchfpga/read_xml_mrfpga.c /^ProcessTechnology(INOUTP ezxml_t Node,$/;" f +ProcessWireBuffer ../../libarchfpga/read_xml_mrfpga.c /^ProcessWireBuffer(INOUTP ezxml_t Node,$/;" f +Process_Fc ../../libarchfpga/read_xml_arch_file.c /^static void Process_Fc(ezxml_t Node, t_type_descriptor * Type) {$/;" f file: +ProcessmrFPGA ../../libarchfpga/read_xml_mrfpga.c /^ProcessmrFPGA(INOUTP ezxml_t Node,$/;" f +Provenance base/ReadOptions.h /^ int Provenance[OT_BASE_UNKNOWN];$/;" m struct:s_options +QUEST timing/slre.c /^ STARQ, PLUSQ, QUEST, SPACE, NONSPACE, DIGIT$/;" e enum:__anon19 file: +R ../../libarchfpga/include/arch_types_mrfpga.h /^ float R; $/;" m struct:s_memristor_inf +R ../../libarchfpga/include/arch_types_mrfpga.h /^ float R;$/;" m struct:s_buffer_inf +R ../../libarchfpga/include/physical_types.h /^ float R;$/;" m struct:s_switch_inf +R base/vpr_types.h /^ float R;$/;" m struct:s_rr_node +RANDOM base/vpr_types.h /^ FREE, RANDOM, USER$/;" e enum:e_pad_loc_type +READLINE_H ../../libarchfpga/include/ReadLine.h 2;" d +READOPTIONS_H base/ReadOptions.h 2;" d +READ_BLIF_H base/read_blif.h 2;" d +READ_NETLIST_H base/read_netlist.h 9;" d +READ_PLACE_H base/read_place.h 2;" d +READ_SDC_H timing/read_sdc.h 2;" d +READ_SETTINGS_H base/read_settings.h 2;" d +READ_XML_ARCH_FILE_H ../../libarchfpga/include/read_xml_arch_file.h 2;" d +READ_XML_UTIL_H ../../libarchfpga/include/read_xml_util.h 2;" d +RECEIVER ../../libarchfpga/include/physical_types.h /^ OPEN = -1, DRIVER = 0, RECEIVER = 1$/;" e enum:e_pin_type +RED base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types +REJECTED place/place.c /^ REJECTED, ACCEPTED, ABORTED$/;" e enum:swap_result file: +REMOVE_CLUSTERED pack/cluster.c /^ REMOVE_CLUSTERED, LEAVE_CLUSTERED$/;" e enum:e_removal_policy file: +RET_SWSEG_TRACK_APPLIED route/rr_graph_swseg.c /^ RET_SWSEG_TRACK_APPLIED$/;" e enum:ret_track_swseg_pattern file: +RET_SWSEG_TRACK_DIR_UNMATCH route/rr_graph_swseg.c /^ RET_SWSEG_TRACK_DIR_UNMATCH,$/;" e enum:ret_track_swseg_pattern file: +RET_SWSEG_TRACK_NON_SEG_LEN_PATTERN route/rr_graph_swseg.c /^ RET_SWSEG_TRACK_NON_SEG_LEN_PATTERN,$/;" e enum:ret_track_swseg_pattern file: +RIGHT ../../libarchfpga/include/physical_types.h /^ TOP = 0, RIGHT = 1, BOTTOM = 2, LEFT = 3$/;" e enum:e_side +ROUND_UP route/route_timing.c 682;" d file: +ROUTE_PATH_WEIGHT timing/path_delay.h 37;" d +ROUTING base/vpr_types.h /^ NO_PICTURE, PLACEMENT, ROUTING$/;" e enum:pic_type +RR_GRAPH2_H route/rr_graph2.h 2;" d +RR_GRAPH_H route/rr_graph.h 2;" d +RR_GRAPH_NO_WARN route/rr_graph.h /^ RR_GRAPH_NO_WARN = 0x00,$/;" e enum:__anon17 +RR_GRAPH_SBOX_H route/rr_graph_sbox.h 2;" d +RR_GRAPH_WARN_CHAN_WIDTH_CHANGED route/rr_graph.h /^ RR_GRAPH_WARN_CHAN_WIDTH_CHANGED = 0x02$/;" e enum:__anon17 +RR_GRAPH_WARN_FC_CLIPPED route/rr_graph.h /^ RR_GRAPH_WARN_FC_CLIPPED = 0x01,$/;" e enum:__anon17 +RUN_FLOW base/vpr_types.h /^ RUN_FLOW, TIMING_ANALYSIS_ONLY$/;" e enum:e_operation +R_minW_nmos ../../libarchfpga/include/physical_types.h /^ float R_minW_nmos;$/;" m struct:s_arch +R_minW_nmos base/vpr_types.h /^ float R_minW_nmos;$/;" m struct:s_det_routing_arch +R_minW_pmos ../../libarchfpga/include/physical_types.h /^ float R_minW_pmos;$/;" m struct:s_arch +R_minW_pmos base/vpr_types.h /^ float R_minW_pmos;$/;" m struct:s_det_routing_arch +R_opin_cblock ../../libarchfpga/include/arch_types_mrfpga.h /^ float R_opin_cblock;$/;" m struct:s_arch_mrfpga +R_opin_cblock ../../libarchfpga/include/physical_types.h /^ float R_opin_cblock;$/;" m struct:s_timing_inf +R_upstream route/route_common.h /^ float R_upstream;$/;" m struct:s_heap +R_upstream route/route_tree_timing.h /^ float R_upstream;$/;" m struct:s_rt_node +ReadBaseCostType base/ReadOptions.c /^ReadBaseCostType(INP char **Args, OUTP enum e_base_cost_type *BaseCostType) {$/;" f file: +ReadBaseToken base/ReadOptions.c /^ReadBaseToken(INP char **Args, OUTP enum e_OptionBaseToken *Token) {$/;" f file: +ReadClusterSeed base/ReadOptions.c /^ReadClusterSeed(INP char **Args, OUTP enum e_cluster_seed *Type) {$/;" f file: +ReadFixPins base/ReadOptions.c /^ReadFixPins(INP char **Args, OUTP char **PinFile) {$/;" f file: +ReadFloat base/ReadOptions.c /^ReadFloat(INP char ** Args, OUTP float *Val) {$/;" f file: +ReadInt base/ReadOptions.c /^ReadInt(INP char **Args, OUTP int *Val) {$/;" f file: +ReadLineTokens ../../libarchfpga/ReadLine.c /^ReadLineTokens(INOUTP FILE * InFile, INOUTP int *LineNum) {$/;" f +ReadOnOff base/ReadOptions.c /^ReadOnOff(INP char **Args, OUTP boolean * Val) {$/;" f file: +ReadOptions base/ReadOptions.c /^void ReadOptions(INP int argc, INP char **argv, OUTP t_options * Options) {$/;" f +ReadPackerAlgorithm base/ReadOptions.c /^ReadPackerAlgorithm(INP char **Args, OUTP enum e_packer_algorithm *Algo) {$/;" f file: +ReadPlaceAlgorithm base/ReadOptions.c /^ReadPlaceAlgorithm(INP char **Args, OUTP enum e_place_algorithm *Algo) {$/;" f file: +ReadRouteType base/ReadOptions.c /^ReadRouteType(INP char **Args, OUTP enum e_route_type *Type) {$/;" f file: +ReadRouterAlgorithm base/ReadOptions.c /^ReadRouterAlgorithm(INP char **Args, OUTP enum e_router_algorithm *Algo) {$/;" f file: +ReadString base/ReadOptions.c /^ReadString(INP char **Args, OUTP char **Val) {$/;" f file: +ReadToken base/ReadOptions.c /^ReadToken(INP char **Args, OUTP enum e_OptionArgToken *Token) {$/;" f file: +RecomputeCritIter base/ReadOptions.h /^ int RecomputeCritIter;$/;" m struct:s_options +Rmetal ../../libarchfpga/include/physical_types.h /^ float Rmetal;$/;" m struct:s_segment_inf +Rmetal base/vpr_types.h /^ float Rmetal;$/;" m struct:s_seg_details +RouteChanWidth base/ReadOptions.h /^ int RouteChanWidth;$/;" m struct:s_options +RouteFile base/ReadOptions.h /^ char *RouteFile;$/;" m struct:s_options +RouteFile base/vpr_types.h /^ char *RouteFile;$/;" m struct:s_file_name_opts +RouteType base/ReadOptions.h /^ enum e_route_type RouteType;$/;" m struct:s_options typeref:enum:s_options::e_route_type +RouterAlgorithm base/ReadOptions.h /^ enum e_router_algorithm RouterAlgorithm;$/;" m struct:s_options typeref:enum:s_options::e_router_algorithm +RouterOpts base/vpr_types.h /^ struct s_router_opts RouterOpts; \/* router options *\/$/;" m struct:s_vpr_setup typeref:struct:s_vpr_setup::s_router_opts +RoutingArch base/vpr_types.h /^ struct s_det_routing_arch RoutingArch; \/* routing architecture *\/$/;" m struct:s_vpr_setup typeref:struct:s_vpr_setup::s_det_routing_arch +Rseg_global ../../libarchfpga/include/arch_types_mrfpga.h /^ float Rseg_global;$/;" m struct:s_arch_mrfpga +Rseg_global mrfpga/mrfpga_globals.c /^float Rseg_global, Cseg_global;$/;" v +SAME_TRACK route/rr_graph2.c 23;" d file: +SBOX_ERROR route/rr_graph_sbox.c 99;" d file: +SBType ../../libarchfpga/include/physical_types.h /^ enum e_switch_block_type SBType;$/;" m struct:s_arch typeref:enum:s_arch::e_switch_block_type +SCALE_DISTANCE_VAL pack/cluster.c 48;" d file: +SCALE_NUM_PATHS pack/cluster.c 39;" d file: +SCREEN base/graphics.c /^ SCREEN = 0,$/;" e enum:__anon2 file: +SDCFile ../../libarchfpga/include/physical_types.h /^ char * SDCFile; \/* only here for convenience of passing to path_delay.c *\/$/;" m struct:s_timing_inf +SDCFile base/ReadOptions.h /^ char *SDCFile;$/;" m struct:s_options +SDC_TOKENS timing/read_sdc.c 452;" d file: +SDF_Adder_delay_printing base/verilog_writer.c /^void SDF_Adder_delay_printing(FILE *SDF , t_pb *pb)$/;" f +SDF_Mult_delay_printing base/verilog_writer.c /^void SDF_Mult_delay_printing(FILE *SDF , t_pb *pb)$/;" f +SDF_interconnect_delay_printing base/verilog_writer.c /^void SDF_interconnect_delay_printing(FILE *SDF , conn_list *downhill)$/;" f +SDF_ram_dual_port_delay_printing base/verilog_writer.c /^void SDF_ram_dual_port_delay_printing(FILE *SDF , t_pb *pb)$/;" f +SDF_ram_single_port_delay_printing base/verilog_writer.c /^void SDF_ram_single_port_delay_printing(FILE *SDF , t_pb *pb)$/;" f +SELECT_ERROR base/graphics.c 217;" d file: +SETUPGRID_H base/SetupGrid.h 2;" d +SETUPVPR_H base/SetupVPR.h 2;" d +SINGLE base/vpr_types.h /^ MULTI_BUFFERED, SINGLE$/;" e enum:e_drivers +SINK base/vpr_types.h /^ SOURCE = 0, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_CLUSTER_EDGE, NUM_RR_TYPES$/;" e enum:e_rr_type +SINK_BLOCK place/timing_place_lookup.c 50;" d file: +SINK_COST_INDEX base/vpr_types.h /^ SINK_COST_INDEX,$/;" e enum:e_cost_indices +SLACK_DEFINITION timing/path_delay.h 8;" d +SLRE_CASE_INSENSITIVE timing/slre.h /^enum slre_option {SLRE_CASE_INSENSITIVE = 1};$/;" e enum:slre_option +SLRE_FLOAT timing/slre.h /^enum slre_capture {SLRE_STRING, SLRE_INT, SLRE_FLOAT};$/;" e enum:slre_capture +SLRE_H timing/slre.h 78;" d +SLRE_INT timing/slre.h /^enum slre_capture {SLRE_STRING, SLRE_INT, SLRE_FLOAT};$/;" e enum:slre_capture +SLRE_STRING timing/slre.h /^enum slre_capture {SLRE_STRING, SLRE_INT, SLRE_FLOAT};$/;" e enum:slre_capture +SMALL_NET place/place.c 27;" d file: +SOLID base/easygl_constants.h /^enum line_types {SOLID, DASHED};$/;" e enum:line_types +SOURCE base/vpr_types.h /^ SOURCE = 0, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_CLUSTER_EDGE, NUM_RR_TYPES$/;" e enum:e_rr_type +SOURCE_BLOCK place/timing_place_lookup.c 49;" d file: +SOURCE_COST_INDEX base/vpr_types.h /^ SOURCE_COST_INDEX = 0,$/;" e enum:e_cost_indices +SPACE timing/slre.c /^ STARQ, PLUSQ, QUEST, SPACE, NONSPACE, DIGIT$/;" e enum:__anon19 file: +SPICE_ABS ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_FRAC, SPICE_ABS$/;" e enum:e_spice_accuracy_type +SPICE_CB_MUX_TB spice/spice_mux_testbench.h /^ SPICE_CB_MUX_TB, SPICE_SB_MUX_TB, SPICE_PB_MUX_TB $/;" e enum:e_spice_mux_tb_type +SPICE_FRAC ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_FRAC, SPICE_ABS$/;" e enum:e_spice_accuracy_type +SPICE_LIB_ACADEMIA ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_LIB_INDUSTRY,SPICE_LIB_ACADEMIA$/;" e enum:e_spice_tech_lib_type +SPICE_LIB_INDUSTRY ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_LIB_INDUSTRY,SPICE_LIB_ACADEMIA$/;" e enum:e_spice_tech_lib_type +SPICE_MEASURE_DYNAMIC_POWER spice/spice_utils.h /^ SPICE_MEASURE_LEAKAGE_POWER, SPICE_MEASURE_DYNAMIC_POWER$/;" e enum:e_measure_type +SPICE_MEASURE_LEAKAGE_POWER spice/spice_utils.h /^ SPICE_MEASURE_LEAKAGE_POWER, SPICE_MEASURE_DYNAMIC_POWER$/;" e enum:e_measure_type +SPICE_MODEL_BUF_BUF ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_BUF_BUF$/;" e enum:e_spice_model_buffer_type +SPICE_MODEL_BUF_INV ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_BUF_INV, $/;" e enum:e_spice_model_buffer_type +SPICE_MODEL_CHAN_WIRE ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_CHAN_WIRE, $/;" e enum:e_spice_model_type +SPICE_MODEL_DESIGN_CMOS ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_DESIGN_CMOS, $/;" e enum:e_spice_model_design_tech +SPICE_MODEL_DESIGN_RRAM ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_DESIGN_RRAM$/;" e enum:e_spice_model_design_tech +SPICE_MODEL_FF ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_FF, $/;" e enum:e_spice_model_type +SPICE_MODEL_GND ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_GND, $/;" e enum:e_spice_model_type +SPICE_MODEL_HARDLOGIC ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_HARDLOGIC,$/;" e enum:e_spice_model_type +SPICE_MODEL_INVBUF ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_INVBUF, $/;" e enum:e_spice_model_type +SPICE_MODEL_IOPAD ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_IOPAD, $/;" e enum:e_spice_model_type +SPICE_MODEL_LUT ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_LUT, $/;" e enum:e_spice_model_type +SPICE_MODEL_MUX ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_MUX, $/;" e enum:e_spice_model_type +SPICE_MODEL_PASSGATE ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PASSGATE $/;" e enum:e_spice_model_type +SPICE_MODEL_PASS_GATE_TRANSISTOR ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PASS_GATE_TRANSMISSION, SPICE_MODEL_PASS_GATE_TRANSISTOR$/;" e enum:e_spice_model_pass_gate_logic_type +SPICE_MODEL_PASS_GATE_TRANSMISSION ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PASS_GATE_TRANSMISSION, SPICE_MODEL_PASS_GATE_TRANSISTOR$/;" e enum:e_spice_model_pass_gate_logic_type +SPICE_MODEL_PORT_BL ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_BL,$/;" e enum:e_spice_model_port_type +SPICE_MODEL_PORT_BLB ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_BLB,$/;" e enum:e_spice_model_port_type +SPICE_MODEL_PORT_CLOCK ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_CLOCK, $/;" e enum:e_spice_model_port_type +SPICE_MODEL_PORT_INOUT ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_INOUT, $/;" e enum:e_spice_model_port_type +SPICE_MODEL_PORT_INPUT ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_INPUT, $/;" e enum:e_spice_model_port_type +SPICE_MODEL_PORT_OUTPUT ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_OUTPUT, $/;" e enum:e_spice_model_port_type +SPICE_MODEL_PORT_SRAM ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_SRAM,$/;" e enum:e_spice_model_port_type +SPICE_MODEL_PORT_WL ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_WL,$/;" e enum:e_spice_model_port_type +SPICE_MODEL_PORT_WLB ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_WLB$/;" e enum:e_spice_model_port_type +SPICE_MODEL_SCFF ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_SCFF,$/;" e enum:e_spice_model_type +SPICE_MODEL_SRAM ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_SRAM, $/;" e enum:e_spice_model_type +SPICE_MODEL_STRUCTURE_CROSSBAR ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_STRUCTURE_CROSSBAR $/;" e enum:e_spice_model_structure +SPICE_MODEL_STRUCTURE_MULTILEVEL ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_STRUCTURE_MULTILEVEL, $/;" e enum:e_spice_model_structure +SPICE_MODEL_STRUCTURE_ONELEVEL ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_STRUCTURE_ONELEVEL, $/;" e enum:e_spice_model_structure +SPICE_MODEL_STRUCTURE_TREE ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_STRUCTURE_TREE, $/;" e enum:e_spice_model_structure +SPICE_MODEL_VDD ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_VDD, $/;" e enum:e_spice_model_type +SPICE_MODEL_WIRE ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_MODEL_WIRE, $/;" e enum:e_spice_model_type +SPICE_PB_MUX_TB spice/spice_mux_testbench.h /^ SPICE_CB_MUX_TB, SPICE_SB_MUX_TB, SPICE_PB_MUX_TB $/;" e enum:e_spice_mux_tb_type +SPICE_SB_MUX_TB spice/spice_mux_testbench.h /^ SPICE_CB_MUX_TB, SPICE_SB_MUX_TB, SPICE_PB_MUX_TB $/;" e enum:e_spice_mux_tb_type +SPICE_SRAM_MEMORY_BANK ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_SRAM_MEMORY_BANK$/;" e enum:e_sram_orgz +SPICE_SRAM_SCAN_CHAIN ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_SRAM_SCAN_CHAIN,$/;" e enum:e_sram_orgz +SPICE_SRAM_STANDALONE ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_SRAM_STANDALONE,$/;" e enum:e_sram_orgz +SPICE_TRANS_IO_NMOS ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_TRANS_NMOS, SPICE_TRANS_PMOS, SPICE_TRANS_IO_NMOS, SPICE_TRANS_IO_PMOS$/;" e enum:e_spice_trans_type +SPICE_TRANS_IO_PMOS ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_TRANS_NMOS, SPICE_TRANS_PMOS, SPICE_TRANS_IO_NMOS, SPICE_TRANS_IO_PMOS$/;" e enum:e_spice_trans_type +SPICE_TRANS_NMOS ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_TRANS_NMOS, SPICE_TRANS_PMOS, SPICE_TRANS_IO_NMOS, SPICE_TRANS_IO_PMOS$/;" e enum:e_spice_trans_type +SPICE_TRANS_PMOS ../../libarchfpga/fpga_spice_include/spice_types.h /^ SPICE_TRANS_NMOS, SPICE_TRANS_PMOS, SPICE_TRANS_IO_NMOS, SPICE_TRANS_IO_PMOS$/;" e enum:e_spice_trans_type +STAR timing/slre.c /^ END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS,$/;" e enum:__anon19 file: +STARQ timing/slre.c /^ STARQ, PLUSQ, QUEST, SPACE, NONSPACE, DIGIT$/;" e enum:__anon19 file: +STTRAM ../../libarchfpga/include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp +SUBSET ../../libarchfpga/include/physical_types.h /^ SUBSET, WILTON, UNIVERSAL, FULL$/;" e enum:e_switch_block_type +SWSEG_UNBUF_CB ../../libarchfpga/include/physical_types.h /^ SWSEG_UNBUF_SB, SWSEG_UNBUF_CB$/;" e enum:e_swseg_pattern_type +SWSEG_UNBUF_SB ../../libarchfpga/include/physical_types.h /^ SWSEG_UNBUF_SB, SWSEG_UNBUF_CB$/;" e enum:e_swseg_pattern_type +Seed base/ReadOptions.h /^ int Seed;$/;" m struct:s_options +Segments ../../libarchfpga/include/physical_types.h /^ t_segment_inf * Segments;$/;" m struct:s_arch +Segments base/vpr_types.h /^ t_segment_inf * Segments; \/* wires in routing architecture *\/$/;" m struct:s_vpr_setup +SetPostSynthesisOption base/ReadOptions.c /^void SetPostSynthesisOption(boolean post_synthesis_enabled){$/;" f +SettingsFile base/ReadOptions.h /^ char *SettingsFile;$/;" m struct:s_options +SetupAnnealSched base/SetupVPR.c /^static void SetupAnnealSched(INP t_options Options,$/;" f file: +SetupEmptyType ../../libarchfpga/read_xml_arch_file.c /^static void SetupEmptyType(void) {$/;" f file: +SetupFpgaSpiceOpts base/SetupVPR.c /^static void SetupFpgaSpiceOpts(t_options Options, $/;" f file: +SetupGridLocations ../../libarchfpga/read_xml_arch_file.c /^static void SetupGridLocations(ezxml_t Locations, t_type_descriptor * Type) {$/;" f file: +SetupOperation base/SetupVPR.c /^static void SetupOperation(INP t_options Options,$/;" f file: +SetupPackerOpts base/SetupVPR.c /^void SetupPackerOpts(INP t_options Options, INP boolean TimingEnabled,$/;" f +SetupPinEquivalenceAutoDetect ../../libarchfpga/read_xml_arch_file.c /^void SetupPinEquivalenceAutoDetect(ezxml_t Parent, t_type_descriptor* Type) {$/;" f file: +SetupPinLocationsAndPinClasses ../../libarchfpga/read_xml_arch_file.c /^static void SetupPinLocationsAndPinClasses(ezxml_t Locations,$/;" f file: +SetupPlacerOpts base/SetupVPR.c /^static void SetupPlacerOpts(INP t_options Options, INP boolean TimingEnabled,$/;" f file: +SetupPowerOpts base/SetupVPR.c /^static void SetupPowerOpts(t_options Options, t_power_opts *power_opts,$/;" f file: +SetupRouterOpts base/SetupVPR.c /^static void SetupRouterOpts(INP t_options Options, INP boolean TimingEnabled,$/;" f file: +SetupRoutingArch base/SetupVPR.c /^static void SetupRoutingArch(INP t_arch Arch,$/;" f file: +SetupSpiceOpts base/SetupVPR.c /^static void SetupSpiceOpts(t_options Options, $/;" f file: +SetupSwitches base/SetupVPR.c /^static void SetupSwitches(INP t_arch Arch,$/;" f file: +SetupSwitches_mrFPGA base/SetupVPR.c /^static void SetupSwitches_mrFPGA(INP t_arch Arch,$/;" f file: +SetupSynVerilogOpts base/SetupVPR.c /^static void SetupSynVerilogOpts(t_options Options, $/;" f file: +SetupTiming base/SetupVPR.c /^static void SetupTiming(INP t_options Options, INP t_arch Arch,$/;" f file: +SetupVPR base/SetupVPR.c /^void SetupVPR(INP t_options *Options, INP boolean TimingEnabled,$/;" f +ShowAnnealSched base/ShowSetup.c /^static void ShowAnnealSched(INP struct s_annealing_sched AnnealSched) {$/;" f file: +ShowGraphics base/vpr_types.h /^ boolean ShowGraphics; \/* option to show graphics *\/$/;" m struct:s_vpr_setup +ShowOperation base/ShowSetup.c /^static void ShowOperation(INP enum e_operation Operation) {$/;" f file: +ShowPackerOpts base/ShowSetup.c /^static void ShowPackerOpts(INP struct s_packer_opts PackerOpts) {$/;" f file: +ShowPlaceTiming base/ReadOptions.h /^ boolean ShowPlaceTiming;$/;" m struct:s_options +ShowPlacerOpts base/ShowSetup.c /^static void ShowPlacerOpts(INP t_options Options,$/;" f file: +ShowRouterOpts base/ShowSetup.c /^static void ShowRouterOpts(INP struct s_router_opts RouterOpts) {$/;" f file: +ShowRoutingArch base/ShowSetup.c /^static void ShowRoutingArch(INP struct s_det_routing_arch RoutingArch) {$/;" f file: +ShowSetup base/ShowSetup.c /^void ShowSetup(INP t_options options, INP t_vpr_setup vpr_setup) {$/;" f +SpiceOpts base/vpr_types.h /^ t_spice_opts SpiceOpts; \/* Xifan TANG: SPICE Support*\/$/;" m struct:s_fpga_spice_opts +StatusWND base/graphics.c /^StatusWND(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)$/;" f file: +Str base/vpr_types.h /^ const char *Str;$/;" m struct:s_TokenPair +Switches ../../libarchfpga/include/physical_types.h /^ struct s_switch_inf *Switches;$/;" m struct:s_arch typeref:struct:s_arch::s_switch_inf +SynVerilogOpts base/vpr_types.h /^ t_syn_verilog_opts SynVerilogOpts; \/* Xifan TANG: Synthesizable verilog dumping*\/$/;" m struct:s_fpga_spice_opts +SyncModelsPbTypes ../../libarchfpga/read_xml_arch_file.c /^static void SyncModelsPbTypes(INOUTP struct s_arch *arch,$/;" f file: +SyncModelsPbTypes_rec ../../libarchfpga/read_xml_arch_file.c /^static void SyncModelsPbTypes_rec(INOUTP struct s_arch *arch,$/;" f file: +TABLENGTH pack/output_blif.c 19;" d file: +TAB_LENGTH pack/output_clustering.c 17;" d file: +THISTLE base/easygl_constants.h /^CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL,$/;" e enum:color_types +TIMING_ANALYSIS_ONLY base/vpr_types.h /^ RUN_FLOW, TIMING_ANALYSIS_ONLY$/;" e enum:e_operation +TIMING_DRIVEN base/vpr_types.h /^ BREADTH_FIRST, TIMING_DRIVEN, NO_TIMING$/;" e enum:e_router_algorithm +TIMING_GAIN_PATH_WEIGHT timing/path_delay.h 35;" d +TIMING_PLACE place/timing_place.h 2;" d +TN_CB_IPIN base/vpr_types.h /^ TN_CB_IPIN, \/* input pin to complex block *\/$/;" e enum:__anon7 +TN_CB_OPIN base/vpr_types.h /^ TN_CB_OPIN, \/* output pin from complex block *\/$/;" e enum:__anon7 +TN_CONSTANT_GEN_SOURCE base/vpr_types.h /^ TN_CONSTANT_GEN_SOURCE \/* source of a constant logic 1 or 0 *\/$/;" e enum:__anon7 +TN_FF_CLOCK base/vpr_types.h /^ TN_FF_CLOCK, \/* clock pin of flip-flop *\/$/;" e enum:__anon7 +TN_FF_IPIN base/vpr_types.h /^ TN_FF_IPIN, \/* input pin to a flip-flop - goes to TN_FF_SINK *\/$/;" e enum:__anon7 +TN_FF_OPIN base/vpr_types.h /^ TN_FF_OPIN, \/* output pin from a flip-flop - comes from TN_FF_SOURCE *\/$/;" e enum:__anon7 +TN_FF_SINK base/vpr_types.h /^ TN_FF_SINK, \/* sink (D) pin of flip-flop *\/$/;" e enum:__anon7 +TN_FF_SOURCE base/vpr_types.h /^ TN_FF_SOURCE, \/* source (Q) pin of flip-flop *\/$/;" e enum:__anon7 +TN_INPAD_OPIN base/vpr_types.h /^ TN_INPAD_OPIN, \/* output from an input I\/O pad *\/$/;" e enum:__anon7 +TN_INPAD_SOURCE base/vpr_types.h /^ TN_INPAD_SOURCE, \/* input to an input I\/O pad *\/$/;" e enum:__anon7 +TN_INTERMEDIATE_NODE base/vpr_types.h /^ TN_INTERMEDIATE_NODE, \/* Used in post-packed timing graph only: $/;" e enum:__anon7 +TN_OUTPAD_IPIN base/vpr_types.h /^ TN_OUTPAD_IPIN, \/* input to an output I\/O pad *\/$/;" e enum:__anon7 +TN_OUTPAD_SINK base/vpr_types.h /^ TN_OUTPAD_SINK, \/* output from an output I\/O pad *\/$/;" e enum:__anon7 +TN_PRIMITIVE_IPIN base/vpr_types.h /^ TN_PRIMITIVE_IPIN, \/* input pin to a primitive (e.g. a LUT) *\/$/;" e enum:__anon7 +TN_PRIMITIVE_OPIN base/vpr_types.h /^ TN_PRIMITIVE_OPIN, \/* output pin from a primitive (e.g. a LUT) *\/$/;" e enum:__anon7 +TOKENS ../../libarchfpga/include/arch_types.h 19;" d +TOKENS base/vpr_types.h 66;" d +TOKEN_CLOSE_SQUARE_BRACKET util/token.h /^ TOKEN_CLOSE_SQUARE_BRACKET,$/;" e enum:e_token_type +TOKEN_CLOSE_SQUIG_BRACKET util/token.h /^ TOKEN_CLOSE_SQUIG_BRACKET,$/;" e enum:e_token_type +TOKEN_COLON util/token.h /^ TOKEN_COLON,$/;" e enum:e_token_type +TOKEN_DOT util/token.h /^ TOKEN_DOT$/;" e enum:e_token_type +TOKEN_H util/token.h 8;" d +TOKEN_INT util/token.h /^ TOKEN_INT,$/;" e enum:e_token_type +TOKEN_NULL util/token.h /^ TOKEN_NULL,$/;" e enum:e_token_type +TOKEN_OPEN_SQUARE_BRACKET util/token.h /^ TOKEN_OPEN_SQUARE_BRACKET,$/;" e enum:e_token_type +TOKEN_OPEN_SQUIG_BRACKET util/token.h /^ TOKEN_OPEN_SQUIG_BRACKET,$/;" e enum:e_token_type +TOKEN_STRING util/token.h /^ TOKEN_STRING,$/;" e enum:e_token_type +TOP ../../libarchfpga/include/physical_types.h /^ TOP = 0, RIGHT = 1, BOTTOM = 2, LEFT = 3$/;" e enum:e_side +TRUE ../../libarchfpga/include/util.h /^ FALSE, TRUE$/;" e enum:__anon23 +TRUE base/graphics.c 145;" d file: +TURQUOISE base/easygl_constants.h /^TURQUOISE, MEDIUMPURPLE, DARKSLATEBLUE, DARKKHAKI, NUM_COLOR};$/;" e enum:color_types +T_AREA_HEIGHT base/graphics.c 178;" d file: +T_arr base/vpr_types.h /^ float T_arr; \/* Arrival time of the last input signal to this node. *\/$/;" m struct:s_tnode +T_crit power/power.h /^ float T_crit;$/;" m struct:s_solution_inf +T_ipin_cblock ../../libarchfpga/include/physical_types.h /^ float T_ipin_cblock;$/;" m struct:s_arch +T_ipin_cblock ../../libarchfpga/include/physical_types.h /^ float T_ipin_cblock;$/;" m struct:s_timing_inf +T_linear base/vpr_types.h /^ float T_linear;$/;" m struct:s_rr_indexed_data +T_opin_cblock ../../libarchfpga/include/arch_types_mrfpga.h /^ float T_opin_cblock;$/;" m struct:s_arch_mrfpga +T_opin_cblock ../../libarchfpga/include/physical_types.h /^ float T_opin_cblock;$/;" m struct:s_timing_inf +T_quadratic base/vpr_types.h /^ float T_quadratic;$/;" m struct:s_rr_indexed_data +T_req base/vpr_types.h /^ float T_req; \/* Required arrival time of the last input signal to this node $/;" m struct:s_tnode +Tdel ../../libarchfpga/include/arch_types_mrfpga.h /^ float Tdel; $/;" m struct:s_memristor_inf +Tdel ../../libarchfpga/include/arch_types_mrfpga.h /^ float Tdel;$/;" m struct:s_buffer_inf +Tdel ../../libarchfpga/include/physical_types.h /^ float Tdel;$/;" m struct:s_switch_inf +Tdel base/vpr_types.h /^ float Tdel; \/* delay to go to to_node along this edge *\/$/;" m struct:s_tedge +Tdel mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan {t_linked_int* inode_head; t_linked_int* sink_head; float* sink_delay; float C_downstream; float Tdel;} t_buffer_plan;$/;" m struct:s_buffer_plan file: +Tdel route/route_tree_timing.h /^ float Tdel;$/;" m struct:s_rt_node +Tdel timing/net_delay_types.h /^ float Tdel;$/;" m struct:s_rc_node +Timing base/vpr_types.h /^ t_timing_inf Timing; \/* timing information *\/$/;" m struct:s_vpr_setup +TimingAnalysis base/ReadOptions.h /^ boolean TimingAnalysis;$/;" m struct:s_options +TimingEnabled base/vpr_types.h /^ boolean TimingEnabled; \/* Is VPR timing enabled *\/$/;" m struct:s_vpr_setup +UNDEFINED ../../libarchfpga/include/arch_types.h 22;" d +UNDEFINED base/vpr_types.h 103;" d +UNIFORM ../../libarchfpga/include/physical_types.h /^ UNIFORM, GAUSSIAN, PULSE, DELTA$/;" e enum:e_stat +UNIVERSAL ../../libarchfpga/include/physical_types.h /^ SUBSET, WILTON, UNIVERSAL, FULL$/;" e enum:e_switch_block_type +UNI_DIRECTIONAL ../../libarchfpga/include/physical_types.h /^ UNI_DIRECTIONAL, BI_DIRECTIONAL$/;" e enum:e_directionality +UNKNOWN_CLASS ../../libarchfpga/include/physical_types.h /^ UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3$/;" e enum:e_pb_type_class +UN_SET route/rr_graph2.c 24;" d file: +UPDATED_ONCE place/place.c 46;" d file: +USER base/vpr_types.h /^ FREE, RANDOM, USER$/;" e enum:e_pad_loc_type +USER_SCHED base/vpr_types.h /^ AUTO_SCHED, USER_SCHED$/;" e enum:sched_type +UTIL_H ../../libarchfpga/include/util.h 2;" d +UpdateAndCheckModels ../../libarchfpga/read_xml_arch_file.c /^static void UpdateAndCheckModels(INOUTP struct s_arch *arch) {$/;" f file: +VERILOG_PORT_CONKT syn_verilog/verilog_global.h /^VERILOG_PORT_CONKT$/;" e enum:e_dump_verilog_port_type +VERILOG_PORT_INOUT syn_verilog/verilog_global.h /^VERILOG_PORT_INOUT,$/;" e enum:e_dump_verilog_port_type +VERILOG_PORT_INPUT syn_verilog/verilog_global.h /^VERILOG_PORT_INPUT,$/;" e enum:e_dump_verilog_port_type +VERILOG_PORT_OUTPUT syn_verilog/verilog_global.h /^VERILOG_PORT_OUTPUT,$/;" e enum:e_dump_verilog_port_type +VERILOG_PORT_REG syn_verilog/verilog_global.h /^VERILOG_PORT_REG,$/;" e enum:e_dump_verilog_port_type +VERILOG_PORT_WIRE syn_verilog/verilog_global.h /^VERILOG_PORT_WIRE,$/;" e enum:e_dump_verilog_port_type +VPACK_COMB base/vpr_types.h /^ VPACK_INPAD = -2, VPACK_OUTPAD, VPACK_COMB, VPACK_LATCH, VPACK_EMPTY$/;" e enum:logical_block_types +VPACK_EMPTY base/vpr_types.h /^ VPACK_INPAD = -2, VPACK_OUTPAD, VPACK_COMB, VPACK_LATCH, VPACK_EMPTY$/;" e enum:logical_block_types +VPACK_INPAD base/vpr_types.h /^ VPACK_INPAD = -2, VPACK_OUTPAD, VPACK_COMB, VPACK_LATCH, VPACK_EMPTY$/;" e enum:logical_block_types +VPACK_LATCH base/vpr_types.h /^ VPACK_INPAD = -2, VPACK_OUTPAD, VPACK_COMB, VPACK_LATCH, VPACK_EMPTY$/;" e enum:logical_block_types +VPACK_MAX_INPUTS base/vpr_types.h /^ VPACK_TIMING, VPACK_MAX_INPUTS$/;" e enum:e_cluster_seed +VPACK_OUTPAD base/vpr_types.h /^ VPACK_INPAD = -2, VPACK_OUTPAD, VPACK_COMB, VPACK_LATCH, VPACK_EMPTY$/;" e enum:logical_block_types +VPACK_TIMING base/vpr_types.h /^ VPACK_TIMING, VPACK_MAX_INPUTS$/;" e enum:e_cluster_seed +VPR_API_H base/vpr_api.h 27;" d +VPR_TYPES_H base/vpr_types.h 34;" d +VPR_UTILS_H util/vpr_utils.h 2;" d +VPR_VERSION ../../libarchfpga/include/arch_types.h 16;" d +Vdd power/power.h /^ float Vdd;$/;" m struct:s_power_tech +W ../../libarchfpga/include/physical_types.h /^ int W;$/;" m struct:s_clb_grid +WARNTAG ../../libarchfpga/include/util.h 27;" d +WHITE base/easygl_constants.h /^enum color_types {WHITE, BLACK, DARKGREY, LIGHTGREY, BLUE, GREEN, YELLOW,$/;" e enum:color_types +WILTON ../../libarchfpga/include/physical_types.h /^ SUBSET, WILTON, UNIVERSAL, FULL$/;" e enum:e_switch_block_type +WIRE_MODEL_PIE ../../libarchfpga/fpga_spice_include/spice_types.h /^ WIRE_MODEL_PIE,$/;" e enum:e_wire_model_type +WIRE_MODEL_T ../../libarchfpga/fpga_spice_include/spice_types.h /^ WIRE_MODEL_T$/;" e enum:e_wire_model_type +WIRE_SEGMENT_LENGTH base/vpr_api.c 491;" d file: +WL base/place_and_route.h 5;" d +WNEED base/place_and_route.h 4;" d +W_seed base/globals.c /^int W_seed = -1;$/;" v +X11 base/graphics.h 13;" d +XPOST base/graphics.c 161;" d file: +XTOWORLD base/graphics.c 167;" d file: +XmlReadArch ../../libarchfpga/read_xml_arch_file.c /^void XmlReadArch(INP const char *ArchFile, INP boolean timing_enabled,$/;" f +YELLOW base/easygl_constants.h /^enum color_types {WHITE, BLACK, DARKGREY, LIGHTGREY, BLUE, GREEN, YELLOW,$/;" e enum:color_types +YPOST base/graphics.c 162;" d file: +YTOWORLD base/graphics.c 168;" d file: +_EZXML_H ../../libarchfpga/include/ezxml.h 26;" d +__POWER_CMOS_TECH_H__ power/power_cmos_tech.h 26;" d +__POWER_COMPONENTS_H__ power/power_components.h 24;" d +__POWER_H__ power/power.h 23;" d +__POWER_LOW_LEVEL_H__ power/power_lowlevel.h 24;" d +__POWER_MISC_H__ power/power_callibrate.h 23;" d +__POWER_POWERSPICEDCOMPONENT_NMOS_H__ power/PowerSpicedComponent.h 19;" d +__POWER_TRANSISTOR_CNT_H__ power/power_sizing.h 24;" d +__POWER_UTIL_H__ power/power_util.h 23;" d +_drawcurve base/graphics.c /^static void _drawcurve(t_point *points, int npoints, int fill) {$/;" f file: +abs_variation ../../libarchfpga/fpga_spice_include/spice_types.h /^ float abs_variation;$/;" m struct:s_spice_mc_variation_params +absolute_length ../../libarchfpga/include/physical_types.h /^ float absolute_length;$/;" m union:s_port_power::__anon22 +absolute_power_per_instance ../../libarchfpga/include/physical_types.h /^ t_power_usage absolute_power_per_instance; \/* User-provided absolute power per block *\/$/;" m struct:s_pb_type_power +absorb_buffer_luts base/read_blif.c /^static void absorb_buffer_luts(void) {$/;" f file: +acc_cost route/route_common.h /^ float acc_cost;$/;" m struct:__anon15 +acc_fac base/ReadOptions.h /^ float acc_fac;$/;" m struct:s_options +acc_fac base/vpr_types.h /^ float acc_fac;$/;" m struct:s_router_opts +accuracy ../../libarchfpga/fpga_spice_include/spice_types.h /^ float accuracy;$/;" m struct:s_spice_meas_params +accuracy_type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type accuracy_type;$/;" m struct:s_spice_meas_params typeref:enum:s_spice_meas_params::e_spice_accuracy_type +add_activity_to_net base/read_blif.c /^bool add_activity_to_net(char * net_name, float probability, float density) {$/;" f +add_conf_bit_info_to_llist fpga_spice/fpga_spice_utils.c /^add_conf_bit_info_to_llist(t_llist* head, int index, $/;" f +add_data_point power/PowerSpicedComponent.c /^void PowerSpicedComponent::add_data_point(int num_inputs, float transistor_size,$/;" f class:PowerSpicedComponent +add_delay_to_array mrfpga/buffer_insertion.c /^static void add_delay_to_array( float* sink_delay, t_linked_int* index, float delay_addition )$/;" f file: +add_delay_to_buffer_list mrfpga/buffer_insertion.c /^static void add_delay_to_buffer_list( t_buffer_plan_list list, float Tdel , boolean skip_first )$/;" f file: +add_delay_to_buffer_plan mrfpga/buffer_insertion.c /^static t_buffer_plan add_delay_to_buffer_plan( t_buffer_plan plan, float Tdel )$/;" f file: +add_entry power/PowerSpicedComponent.c /^PowerCallibInputs * PowerSpicedComponent::add_entry(int num_inputs) {$/;" f class:PowerSpicedComponent +add_latch base/read_blif.c /^static void add_latch(int doall, INP t_model *latch_model) {$/;" f file: +add_lut base/read_blif.c /^static boolean add_lut(int doall, t_model *logic_model) {$/;" f file: +add_molecule_to_pb_stats_candidates pack/cluster.c /^static void add_molecule_to_pb_stats_candidates(t_pack_molecule *molecule,$/;" f file: +add_mux_conf_bits_to_llist fpga_spice/fpga_spice_utils.c /^add_mux_conf_bits_to_llist(int mux_size,$/;" f +add_mux_membank_conf_bits_to_llist fpga_spice/fpga_spice_utils.c /^add_mux_membank_conf_bits_to_llist(int mux_size,$/;" f +add_mux_scff_conf_bits_to_llist fpga_spice/fpga_spice_utils.c /^add_mux_scff_conf_bits_to_llist(int mux_size,$/;" f +add_net_rr_terminal_cluster pack/cluster_legality.c /^static void add_net_rr_terminal_cluster(int iblk_net,$/;" f file: +add_net_to_hash base/read_netlist.c /^static int add_net_to_hash(INOUTP struct s_hash **nhash, INP char *net_name,$/;" f file: +add_one_spice_tb_info_to_llist spice/spice_utils.c /^t_llist* add_one_spice_tb_info_to_llist(t_llist* cur_head, $/;" f +add_opin_fast_edge_to_ipin route/rr_graph_opincb.c /^int add_opin_fast_edge_to_ipin(t_rr_node* opin, $/;" f file: +add_opin_list_ipin_list_fast_edge route/rr_graph_opincb.c /^int add_opin_list_ipin_list_fast_edge(int num_opins, t_rr_node** opin_list, $/;" f file: +add_opin_rr_edges_to_chan_rr_node route/pb_pin_eq_auto_detect.c /^int add_opin_rr_edges_to_chan_rr_node(t_rr_node* chan_rr_node,$/;" f +add_override_constraint timing/read_sdc.c /^static void add_override_constraint(char ** from_list, int num_from, char ** to_list, int num_to, $/;" f file: +add_path_to_route_tree route/route_tree_timing.c /^add_path_to_route_tree(struct s_heap *hptr, t_rt_node ** sink_rt_node_ptr) {$/;" f file: +add_pattern_name_to_hash pack/prepack.c /^static int add_pattern_name_to_hash(INOUTP struct s_hash **nhash,$/;" f file: +add_route_tree_to_heap route/route_timing.c /^static void add_route_tree_to_heap(t_rt_node * rt_node, int target_node,$/;" f file: +add_rr_graph_C_from_switches route/rr_graph_timing_params.c /^void add_rr_graph_C_from_switches(float C_ipin_cblock) {$/;" f +add_rr_graph_fast_edge_opin_to_cb route/rr_graph_opincb.c /^int add_rr_graph_fast_edge_opin_to_cb(t_ivec*** LL_rr_node_indices) {$/;" f +add_rr_graph_one_grid_fast_edge_opin_to_cb route/rr_graph_opincb.c /^int add_rr_graph_one_grid_fast_edge_opin_to_cb(int grid_x, $/;" f file: +add_rr_graph_switch_segment_pattern route/rr_graph_swseg.c /^int add_rr_graph_switch_segment_pattern(enum e_directionality directionality,$/;" f +add_size power/PowerSpicedComponent.c /^void PowerCallibInputs::add_size(float transistor_size, float power) {$/;" f class:PowerCallibInputs +add_sram_conf_bits_to_llist fpga_spice/fpga_spice_utils.c /^add_sram_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, int mem_index, $/;" f +add_sram_membank_conf_bits_to_llist fpga_spice/fpga_spice_utils.c /^void add_sram_membank_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, int mem_index, $/;" f +add_sram_scff_conf_bits_to_llist fpga_spice/fpga_spice_utils.c /^add_sram_scff_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, $/;" f +add_subckt base/read_blif.c /^static void add_subckt(int doall, t_model *user_models) {$/;" f file: +add_to_heap route/route_common.c /^static void add_to_heap(struct s_heap *hptr) {$/;" f file: +add_to_mod_list route/route_common.c /^void add_to_mod_list(float *fptr) {$/;" f +add_to_rc_tree timing/net_delay.c /^void add_to_rc_tree(t_rc_node * parent_rc, t_rc_node * child_rc,$/;" f +add_to_sort_heap util/heapsort.c /^static void add_to_sort_heap(int *heap, float *sort_values, int index,$/;" f file: +add_vpack_net base/read_blif.c /^static int add_vpack_net(char *ptr, int type, int bnum, int bport, int bpin,$/;" f file: +add_wire_to_switch base/SetupVPR.c /^static void add_wire_to_switch(struct s_det_routing_arch *det_routing_arch) {$/;" f file: +addr ../../libarchfpga/fpga_spice_include/spice_types.h /^ int addr; \/* Address to write the value *\/$/;" m struct:s_conf_bit +adjustButton base/graphics.c /^static int windowAdjustFlag = 0, adjustButton = -1;$/;" v file: +adjustRect base/graphics.c /^static RECT adjustRect, updateRect;$/;" v file: +adjust_one_rr_occ_and_pcost route/route_common.c /^static void adjust_one_rr_occ_and_pcost(int inode, int add_or_sub,$/;" f file: +adjustwin base/graphics.c /^adjustwin (void (*drawscreen) (void)) $/;" f file: +advanced_rram_design ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean advanced_rram_design;$/;" m struct:s_spice_model_design_tech_info +alloc_SRAM_values_from_truth_table power/power_util.c /^char * alloc_SRAM_values_from_truth_table(int LUT_size,$/;" f +alloc_and_add_fully_capacity_rr_edges_to_one_grid route/pb_pin_eq_auto_detect.c /^int alloc_and_add_fully_capacity_rr_edges_to_one_grid(int grid_x, int grid_y, int grid_z,$/;" f +alloc_and_add_fully_capacity_rr_edges_to_source_opin route/pb_pin_eq_auto_detect.c /^int alloc_and_add_fully_capacity_rr_edges_to_source_opin(t_type_ptr cur_type_descriptor,$/;" f +alloc_and_add_fully_capacity_sb_rr_edges_to_one_grid route/pb_pin_eq_auto_detect.c /^int alloc_and_add_fully_capacity_sb_rr_edges_to_one_grid(int grid_x, int grid_y, int grid_z,$/;" f +alloc_and_add_grids_fully_capacity_rr_edges route/pb_pin_eq_auto_detect.c /^int alloc_and_add_grids_fully_capacity_rr_edges(t_ivec*** LL_rr_node_indices,$/;" f +alloc_and_add_grids_fully_capacity_sb_rr_edges route/pb_pin_eq_auto_detect.c /^int alloc_and_add_grids_fully_capacity_sb_rr_edges(t_ivec*** LL_rr_node_indices,$/;" f +alloc_and_assign_internal_structures place/timing_place_lookup.c /^static void alloc_and_assign_internal_structures(struct s_net **original_net,$/;" f file: +alloc_and_build_connection_blocks_info fpga_spice/fpga_spice_backannotate_utils.c /^void alloc_and_build_connection_blocks_info(t_det_routing_arch RoutingArch,$/;" f file: +alloc_and_build_switch_blocks_info fpga_spice/fpga_spice_backannotate_utils.c /^void alloc_and_build_switch_blocks_info(t_det_routing_arch RoutingArch,$/;" f file: +alloc_and_init_clustering pack/cluster.c /^static void alloc_and_init_clustering(boolean global_clocks, float alpha,$/;" f file: +alloc_and_init_netlist_from_hash base/read_netlist.c /^static struct s_net *alloc_and_init_netlist_from_hash(INP int ncount,$/;" f file: +alloc_and_init_pattern_list_from_hash pack/prepack.c /^static t_pack_patterns *alloc_and_init_pattern_list_from_hash(INP int ncount,$/;" f file: +alloc_and_load_actual_fc route/rr_graph.c /^alloc_and_load_actual_fc(INP int L_num_types, INP t_type_ptr types,$/;" f file: +alloc_and_load_all_pb_graphs pack/pb_type_graph.c /^void alloc_and_load_all_pb_graphs(boolean load_power_structures) {$/;" f +alloc_and_load_blk_pin_from_port_pin util/vpr_utils.c /^static void alloc_and_load_blk_pin_from_port_pin(void) {$/;" f file: +alloc_and_load_clb_opins_used_locally route/route_common.c /^alloc_and_load_clb_opins_used_locally(void) {$/;" f file: +alloc_and_load_clb_to_clb_directs route/rr_graph.c /^static t_clb_to_clb_directs * alloc_and_load_clb_to_clb_directs(INP t_direct_inf *directs, INP int num_directs) {$/;" f file: +alloc_and_load_cluster_info pack/cluster.c /^static void alloc_and_load_cluster_info(INP int num_clb, INOUTP t_block *clb) {$/;" f file: +alloc_and_load_cluster_legality_checker pack/cluster_legality.c /^void alloc_and_load_cluster_legality_checker(void) {$/;" f +alloc_and_load_cluster_placement_stats pack/cluster_placement.c /^t_cluster_placement_stats *alloc_and_load_cluster_placement_stats(void) {$/;" f +alloc_and_load_complete_interc_edges pack/pb_type_graph.c /^static void alloc_and_load_complete_interc_edges($/;" f file: +alloc_and_load_default_child_for_pb_type ../../libarchfpga/read_xml_arch_file.c /^static void alloc_and_load_default_child_for_pb_type( INOUTP t_pb_type *pb_type,$/;" f file: +alloc_and_load_direct_interc_edges pack/pb_type_graph.c /^static void alloc_and_load_direct_interc_edges($/;" f file: +alloc_and_load_echo_file_info base/ReadOptions.c /^void alloc_and_load_echo_file_info() {$/;" f +alloc_and_load_edges_and_switches route/rr_graph.c /^void alloc_and_load_edges_and_switches(INP t_rr_node * L_rr_node, INP int inode,$/;" f +alloc_and_load_final_routing_trace base/vpr_api.c /^static t_trace *alloc_and_load_final_routing_trace() {$/;" f file: +alloc_and_load_for_fast_cost_update place/place.c /^static void alloc_and_load_for_fast_cost_update(float place_cost_exp) {$/;" f file: +alloc_and_load_global_route_seg_details route/rr_graph.c /^alloc_and_load_global_route_seg_details(INP int nodes_per_chan,$/;" f file: +alloc_and_load_grid base/SetupGrid.c /^void alloc_and_load_grid(INOUTP int *num_instances_type) {$/;" f +alloc_and_load_idirect_from_blk_pin util/vpr_utils.c /^void alloc_and_load_idirect_from_blk_pin(t_direct_inf* directs, int num_directs, $/;" f +alloc_and_load_imacro_from_iblk place/place_macro.c /^static void alloc_and_load_imacro_from_iblk(t_pl_macro * macros, int num_macros) {$/;" f file: +alloc_and_load_interconnect_pins pack/pb_type_graph.c /^static void alloc_and_load_interconnect_pins(t_interconnect_pins * interc_pins,$/;" f file: +alloc_and_load_is_clock pack/pack.c /^boolean *alloc_and_load_is_clock(boolean global_clocks) {$/;" f +alloc_and_load_legalizer_for_cluster pack/cluster_legality.c /^void alloc_and_load_legalizer_for_cluster(INP t_block* clb, INP int clb_index,$/;" f +alloc_and_load_mode_interconnect pack/pb_type_graph.c /^static void alloc_and_load_mode_interconnect($/;" f file: +alloc_and_load_mux_graph power/power_util.c /^static t_mux_node * alloc_and_load_mux_graph(int num_inputs, int levels) {$/;" f file: +alloc_and_load_mux_graph_recursive power/power_util.c /^static void alloc_and_load_mux_graph_recursive(t_mux_node * node,$/;" f file: +alloc_and_load_mux_interc_edges pack/pb_type_graph.c /^static void alloc_and_load_mux_interc_edges( INP t_interconnect * interconnect,$/;" f file: +alloc_and_load_net_pin_index util/vpr_utils.c /^int ** alloc_and_load_net_pin_index() {$/;" f +alloc_and_load_netlist_clocks_and_ios timing/read_sdc.c /^static void alloc_and_load_netlist_clocks_and_ios(void) {$/;" f file: +alloc_and_load_output_file_names base/ReadOptions.c /^void alloc_and_load_output_file_names(const char *default_name) {$/;" f +alloc_and_load_pack_molecules pack/prepack.c /^t_pack_molecule *alloc_and_load_pack_molecules($/;" f +alloc_and_load_pack_patterns pack/prepack.c /^t_pack_patterns *alloc_and_load_pack_patterns(OUTP int *num_packing_patterns) {$/;" f +alloc_and_load_pb_graph pack/pb_type_graph.c /^static void alloc_and_load_pb_graph(INOUTP t_pb_graph_node *pb_graph_node,$/;" f file: +alloc_and_load_pb_stats pack/cluster.c /^static void alloc_and_load_pb_stats(t_pb *pb, int max_models,$/;" f file: +alloc_and_load_perturb_ipins route/rr_graph.c /^alloc_and_load_perturb_ipins(INP int nodes_per_chan, INP int L_num_types,$/;" f file: +alloc_and_load_pin_locations_from_pb_graph pack/pb_type_graph.c /^static void alloc_and_load_pin_locations_from_pb_graph(t_type_descriptor *type) {$/;" f file: +alloc_and_load_pin_to_track_map route/rr_graph.c /^alloc_and_load_pin_to_track_map(INP enum e_pin_type pin_type,$/;" f file: +alloc_and_load_placement_macros place/place_macro.c /^int alloc_and_load_placement_macros(t_direct_inf* directs, int num_directs, t_pl_macro ** macros){$/;" f +alloc_and_load_placement_structs place/place.c /^static void alloc_and_load_placement_structs($/;" f file: +alloc_and_load_port_pin_from_blk_pin util/vpr_utils.c /^static void alloc_and_load_port_pin_from_blk_pin(void) {$/;" f file: +alloc_and_load_port_pin_ptrs_from_string pack/pb_type_graph.c /^t_pb_graph_pin *** alloc_and_load_port_pin_ptrs_from_string(INP int line_num,$/;" f +alloc_and_load_pre_packing_timing_graph timing/path_delay.c /^t_slack * alloc_and_load_pre_packing_timing_graph(float block_delay,$/;" f +alloc_and_load_rc_tree timing/net_delay.c /^alloc_and_load_rc_tree(int inet, t_rc_node ** rc_node_free_list_ptr,$/;" f +alloc_and_load_rr_clb_source route/rr_graph.c /^static void alloc_and_load_rr_clb_source(t_ivec *** L_rr_node_indices) {$/;" f file: +alloc_and_load_rr_graph route/rr_graph.c /^static void alloc_and_load_rr_graph(INP int num_nodes,$/;" f file: +alloc_and_load_rr_graph_for_pb_graph_node pack/cluster_legality.c /^void alloc_and_load_rr_graph_for_pb_graph_node($/;" f +alloc_and_load_rr_indexed_data route/rr_graph_indexed_data.c /^void alloc_and_load_rr_indexed_data(INP t_segment_inf * segment_inf,$/;" f +alloc_and_load_rr_node_indices route/rr_graph2.c /^alloc_and_load_rr_node_indices(INP int nodes_per_chan, INP int L_nx,$/;" f +alloc_and_load_rr_node_route_structs route/route_common.c /^void alloc_and_load_rr_node_route_structs(void) {$/;" f +alloc_and_load_seg_details route/rr_graph2.c /^alloc_and_load_seg_details(INOUTP int *nodes_per_chan, INP int max_len,$/;" f +alloc_and_load_sharable_switch_trans route/rr_graph_area.c /^alloc_and_load_sharable_switch_trans(int num_switch, float trans_sram_bit,$/;" f file: +alloc_and_load_switch_block_conn route/rr_graph_sbox.c /^alloc_and_load_switch_block_conn(INP int nodes_per_chan,$/;" f +alloc_and_load_timing_graph timing/path_delay.c /^t_slack * alloc_and_load_timing_graph(t_timing_inf timing_inf) {$/;" f +alloc_and_load_timing_graph_levels timing/path_delay2.c /^int alloc_and_load_timing_graph_levels(void) {$/;" f +alloc_and_load_tnode_fanin_and_check_edges timing/path_delay2.c /^alloc_and_load_tnode_fanin_and_check_edges(int *num_sinks_ptr) {$/;" f file: +alloc_and_load_tnodes timing/path_delay.c /^static void alloc_and_load_tnodes(t_timing_inf timing_inf) {$/;" f file: +alloc_and_load_tnodes_from_prepacked_netlist timing/path_delay.c /^static void alloc_and_load_tnodes_from_prepacked_netlist(float block_delay,$/;" f file: +alloc_and_load_track_to_pin_lookup route/rr_graph.c /^alloc_and_load_track_to_pin_lookup(INP int ****pin_to_track_map, INP int *Fc,$/;" f file: +alloc_and_load_try_swap_structs place/place.c /^static void alloc_and_load_try_swap_structs() {$/;" f file: +alloc_and_load_unsharable_switch_trans route/rr_graph_area.c /^alloc_and_load_unsharable_switch_trans(int num_switch, float trans_sram_bit,$/;" f file: +alloc_block place/timing_place_lookup.c /^static void alloc_block(void) {$/;" f file: +alloc_cb_info_array fpga_spice/fpga_spice_backannotate_utils.c /^t_cb** alloc_cb_info_array(int LL_nx, int LL_ny) {$/;" f +alloc_crit place/timing_place.c /^static float ** alloc_crit(t_chunk *chunk_list_ptr) {$/;" f file: +alloc_delta_arrays place/timing_place_lookup.c /^static void alloc_delta_arrays(void) {$/;" f file: +alloc_draw_structs base/draw.c /^void alloc_draw_structs(void) {$/;" f +alloc_global_routing_conf_bits syn_verilog/syn_verilog_api.c /^void alloc_global_routing_conf_bits() {$/;" f file: +alloc_hash_table util/hash.c /^alloc_hash_table(void) {$/;" f +alloc_heap_data route/route_common.c /^alloc_heap_data(void) {$/;" f file: +alloc_internal_cb_nets base/read_netlist.c /^static void alloc_internal_cb_nets(INOUTP t_pb *top_level,$/;" f file: +alloc_isink_to_inode mrfpga/buffer_insertion.c /^static int alloc_isink_to_inode( int inet, int** isink_to_inode_ptr )$/;" f file: +alloc_ivector_and_copy_int_list ../../libarchfpga/util.c /^void alloc_ivector_and_copy_int_list(t_linked_int ** list_head_ptr,$/;" f +alloc_legal_placements place/place.c /^static void alloc_legal_placements() {$/;" f file: +alloc_linked_f_pointer route/route_common.c /^alloc_linked_f_pointer(void) {$/;" f file: +alloc_linked_rc_edge timing/net_delay.c /^alloc_linked_rc_edge(t_linked_rc_edge ** rc_edge_free_list_ptr) {$/;" f +alloc_linked_rt_edge route/route_tree_timing.c /^alloc_linked_rt_edge(void) {$/;" f file: +alloc_lookups_and_criticalities place/timing_place.c /^t_slack * alloc_lookups_and_criticalities(t_chan_width_dist chan_width_dist,$/;" f +alloc_matrix ../../libarchfpga/util.c /^alloc_matrix(int nrmin, int nrmax, int ncmin, int ncmax, size_t elsize) {$/;" f +alloc_matrix3 ../../libarchfpga/util.c /^alloc_matrix3(int nrmin, int nrmax, int ncmin, int ncmax, int ndmin, int ndmax,$/;" f +alloc_matrix4 ../../libarchfpga/util.c /^alloc_matrix4(int nrmin, int nrmax, int ncmin, int ncmax, int ndmin, int ndmax,$/;" f +alloc_net place/timing_place_lookup.c /^static void alloc_net(void) {$/;" f file: +alloc_net_delay timing/net_delay.c /^alloc_net_delay(t_chunk *chunk_list_ptr, struct s_net *nets,$/;" f +alloc_net_rr_terminals route/rr_graph.c /^static void alloc_net_rr_terminals(void) {$/;" f file: +alloc_net_rr_terminals_cluster pack/cluster_legality.c /^static void alloc_net_rr_terminals_cluster(void) {$/;" f file: +alloc_one_conf_bit_info fpga_spice/fpga_spice_utils.c /^alloc_one_conf_bit_info(int index,$/;" f +alloc_one_mem_bank_info fpga_spice/fpga_spice_utils.c /^t_mem_bank_info* alloc_one_mem_bank_info() {$/;" f +alloc_one_scff_info fpga_spice/fpga_spice_utils.c /^t_scff_info* alloc_one_scff_info() {$/;" f +alloc_one_sram_orgz_info fpga_spice/fpga_spice_utils.c /^t_sram_orgz_info* alloc_one_sram_orgz_info() {$/;" f +alloc_one_standalone_sram_info fpga_spice/fpga_spice_utils.c /^t_standalone_sram_info* alloc_one_standalone_sram_info() {$/;" f +alloc_pin_classes_in_pb_graph_node pack/cluster_feasibility_filter.c /^static void alloc_pin_classes_in_pb_graph_node($/;" f file: +alloc_rc_node timing/net_delay.c /^alloc_rc_node(t_rc_node ** rc_node_free_list_ptr) {$/;" f +alloc_route_static_structs route/route_common.c /^void alloc_route_static_structs(void) {$/;" f +alloc_route_structs route/route_common.c /^alloc_route_structs(void) {$/;" f +alloc_route_tree_timing_structs route/route_tree_timing.c /^void alloc_route_tree_timing_structs(void) {$/;" f +alloc_routing_structs place/timing_place_lookup.c /^static void alloc_routing_structs(struct s_router_opts router_opts,$/;" f file: +alloc_rt_node route/route_tree_timing.c /^alloc_rt_node(void) {$/;" f file: +alloc_saved_routing route/route_common.c /^alloc_saved_routing(t_ivec ** clb_opins_used_locally,$/;" f +alloc_sb_info_array fpga_spice/fpga_spice_backannotate_utils.c /^t_sb** alloc_sb_info_array(int LL_nx, int LL_ny) {$/;" f +alloc_sblock_pattern_lookup route/rr_graph2.c /^alloc_sblock_pattern_lookup(INP int L_nx, INP int L_ny, INP int nodes_per_chan) {$/;" f +alloc_slacks timing/path_delay.c /^static t_slack * alloc_slacks(void) {$/;" f file: +alloc_spice_model_grid_index_low_high fpga_spice/fpga_spice_utils.c /^void alloc_spice_model_grid_index_low_high(t_spice_model* cur_spice_model) {$/;" f +alloc_spice_model_routing_index_low_high fpga_spice/fpga_spice_utils.c /^void alloc_spice_model_routing_index_low_high(t_spice_model* cur_spice_model) {$/;" f +alloc_timing_driven_route_structs route/route_timing.c /^void alloc_timing_driven_route_structs(float **pin_criticality_ptr,$/;" f +alloc_timing_stats timing/path_delay.c /^static void alloc_timing_stats(void) {$/;" f file: +alloc_trace_data route/route_common.c /^alloc_trace_data(void) {$/;" f file: +allocate_and_load_critical_path timing/path_delay.c /^t_linked_int * allocate_and_load_critical_path(void) {$/;" f +allow_early_exit base/ReadOptions.h /^ boolean allow_early_exit;$/;" m struct:s_options +allow_early_exit base/vpr_types.h /^ boolean allow_early_exit;$/;" m struct:s_packer_opts +allow_unrelated_clustering base/ReadOptions.h /^ boolean allow_unrelated_clustering;$/;" m struct:s_options +allow_unrelated_clustering base/vpr_types.h /^ boolean allow_unrelated_clustering;$/;" m struct:s_packer_opts +alpha base/ReadOptions.h /^ float alpha;$/;" m struct:s_options +alpha base/vpr_types.h /^ float alpha;$/;" m struct:s_packer_opts +alpha_t base/vpr_types.h /^ float alpha_t;$/;" m struct:s_annealing_sched +anchored timing/slre.c /^ int anchored; \/\/ Must match from string start$/;" m struct:slre file: +angnorm base/graphics.c /^angnorm (float ang) $/;" f file: +annotations ../../libarchfpga/include/physical_types.h /^ t_pin_to_pin_annotation *annotations; \/* [0..num_annotations-1] *\/$/;" m struct:s_interconnect +annotations ../../libarchfpga/include/physical_types.h /^ t_pin_to_pin_annotation *annotations; \/* [0..num_annotations-1] *\/$/;" m struct:s_pb_type +anyof timing/slre.c /^static void anyof(struct slre *r, const char **re) {$/;" f file: +apply_swseg_pattern_chanx_track route/rr_graph_swseg.c /^ apply_swseg_pattern_chanx_track(INP int track_id,$/;" f file: +apply_swseg_pattern_chany_track route/rr_graph_swseg.c /^ apply_swseg_pattern_chany_track(INP int track_id,$/;" f file: +arch_mrfpga ../../libarchfpga/include/physical_types.h /^ t_arch_mrfpga arch_mrfpga;$/;" m struct:s_arch +area ../../libarchfpga/fpga_spice_include/spice_types.h /^ float area; \/\/Xifan TANG$/;" m struct:s_sram_inf +area ../../libarchfpga/include/physical_types.h /^ float area;$/;" m struct:s_type_descriptor +aspect base/vpr_types.h /^ float aspect;$/;" m struct:s_packer_opts +assess_swap place/place.c /^static enum swap_result assess_swap(float delta_c, float t) {$/;" f file: +assign_blocks_and_route_net place/timing_place_lookup.c /^static float assign_blocks_and_route_net(t_type_ptr source_type,$/;" f file: +assign_locations place/timing_place_lookup.c /^static void assign_locations(t_type_ptr source_type, int source_x_loc,$/;" f file: +assign_lut_truth_table fpga_spice/fpga_spice_utils.c /^char** assign_lut_truth_table(t_logical_block* mapped_logical_block,$/;" f +assign_pb_graph_node_pin_temp_net_num_by_mode_index fpga_spice/fpga_spice_utils.c /^void assign_pb_graph_node_pin_temp_net_num_by_mode_index(t_pb_graph_pin* cur_pb_graph_pin,$/;" f +astar_fac base/ReadOptions.h /^ float astar_fac;$/;" m struct:s_options +astar_fac base/vpr_types.h /^ float astar_fac;$/;" m struct:s_router_opts +attr ../../libarchfpga/include/ezxml.h /^ char ***attr; \/* default attributes *\/$/;" m struct:ezxml_root +attr ../../libarchfpga/include/ezxml.h /^ char **attr; \/* tag attributes { name, value, name, value, ... NULL } *\/$/;" m struct:ezxml +auto_compute_inter_cluster_net_delay base/vpr_types.h /^ boolean auto_compute_inter_cluster_net_delay;$/;" m struct:s_packer_opts +auto_detect_and_reserve_locally_used_opins route/route_common.c /^void auto_detect_and_reserve_locally_used_opins(float pres_fac, boolean rip_up_local_opins,$/;" f +auto_detect_and_reserve_used_opins route/pb_pin_eq_auto_detect.c /^void auto_detect_and_reserve_used_opins(float pres_fac) {$/;" f +auto_select_max_sim_num_clock_cycles spice/spice_grid_testbench.c /^static int auto_select_max_sim_num_clock_cycles = TRUE;$/;" v file: +auto_select_max_sim_num_clock_cycles spice/spice_hardlogic_testbench.c /^static int auto_select_max_sim_num_clock_cycles = TRUE;$/;" v file: +auto_select_max_sim_num_clock_cycles spice/spice_lut_testbench.c /^static int auto_select_max_sim_num_clock_cycles = TRUE;$/;" v file: +auto_select_max_sim_num_clock_cycles spice/spice_mux_testbench.c /^static int auto_select_max_sim_num_clock_cycles = TRUE;$/;" v file: +auto_select_max_sim_num_clock_cycles spice/spice_routing_testbench.c /^static int auto_select_max_sim_num_clock_cycles = TRUE;$/;" v file: +auto_select_num_sim_clock_cycle fpga_spice/fpga_spice_utils.c /^void auto_select_num_sim_clock_cycle(t_spice* spice,$/;" f +auto_select_sim_num_clk_cycle ../../libarchfpga/fpga_spice_include/spice_types.h /^ int auto_select_sim_num_clk_cycle;$/;" m struct:s_spice_meas_params +autosize_buffer ../../libarchfpga/include/physical_types.h /^ boolean autosize_buffer; \/* autosize clock buffers *\/$/;" m struct:s_clock_network +available_in_packing ../../libarchfpga/include/physical_types.h /^ int available_in_packing;$/;" m struct:s_mode +back_annotate_one_pb_rr_node_map_info_rec fpga_spice/fpga_spice_backannotate_utils.c /^void back_annotate_one_pb_rr_node_map_info_rec(t_pb* cur_pb) {$/;" f file: +back_annotate_pb_rr_node_map_info fpga_spice/fpga_spice_backannotate_utils.c /^void back_annotate_pb_rr_node_map_info() {$/;" f file: +back_annotate_rr_node_map_info fpga_spice/fpga_spice_backannotate_utils.c /^void back_annotate_rr_node_map_info() {$/;" f file: +backannotate_clb_nets_act_info fpga_spice/fpga_spice_backannotate_utils.c /^void backannotate_clb_nets_act_info() {$/;" f file: +backannotate_clb_nets_init_val fpga_spice/fpga_spice_backannotate_utils.c /^void backannotate_clb_nets_init_val() {$/;" f file: +backannotate_one_pb_rr_nodes_net_info_rec fpga_spice/fpga_spice_backannotate_utils.c /^void backannotate_one_pb_rr_nodes_net_info_rec(t_pb* cur_pb) {$/;" f file: +backannotate_pb_rr_nodes_net_info fpga_spice/fpga_spice_backannotate_utils.c /^void backannotate_pb_rr_nodes_net_info() {$/;" f file: +backannotate_rr_nodes_parasitic_net_info fpga_spice/fpga_spice_backannotate_utils.c /^void backannotate_rr_nodes_parasitic_net_info() {$/;" f file: +backannotate_vpr_post_route_info fpga_spice/fpga_spice_backannotate_utils.c /^void backannotate_vpr_post_route_info(t_det_routing_arch RoutingArch) { $/;" f +background_cindex base/graphics.c /^ int background_cindex;$/;" m struct:__anon5 file: +backup_one_pb_rr_node_pack_prev_node_edge fpga_spice/fpga_spice_backannotate_utils.c /^void backup_one_pb_rr_node_pack_prev_node_edge(t_rr_node* pb_rr_node) {$/;" f +backward_expand_pack_pattern_from_edge pack/prepack.c /^static void backward_expand_pack_pattern_from_edge($/;" f file: +backward_infer_pattern pack/prepack.c /^static void backward_infer_pattern(INOUTP t_pb_graph_pin *pb_graph_pin) {$/;" f file: +backward_path_cost route/route_common.h /^ float backward_path_cost;$/;" m struct:__anon15 +backward_path_cost route/route_common.h /^ float backward_path_cost;$/;" m struct:s_heap +backward_weight base/vpr_types.h /^ float forward_weight, backward_weight; \/* Weightings of the importance of paths $/;" m struct:s_tnode +base_cost ../../libarchfpga/include/cad_types.h /^ float base_cost; \/* base cost of pattern eg. If a group of logical blocks match a pattern of smaller primitives, that is better than the same group using bigger primitives *\/$/;" m struct:s_pack_patterns +base_cost ../../libarchfpga/include/cad_types.h /^ float base_cost; \/* cost independant of current status of packing *\/$/;" m struct:s_cluster_placement_primitive +base_cost base/vpr_types.h /^ float base_cost;$/;" m struct:s_rr_indexed_data +base_cost_type base/ReadOptions.h /^ enum e_base_cost_type base_cost_type;$/;" m struct:s_options typeref:enum:s_options::e_base_cost_type +base_cost_type base/vpr_types.h /^ enum e_base_cost_type base_cost_type;$/;" m struct:s_router_opts typeref:enum:s_router_opts::e_base_cost_type +base_gain base/vpr_types.h /^ float base_gain; \/* Intrinsic "goodness" score for molecule independant of rest of netlist *\/$/;" m struct:s_pack_molecule +basics_spice_file_name spice/spice_globals.c /^char* basics_spice_file_name = "inv_buf_trans_gate.sp";$/;" v +bb_coords place/place.c /^static struct s_bb *bb_coords = NULL, *bb_num_on_edges = NULL;$/;" v typeref:struct:s_bb file: +bb_factor base/ReadOptions.h /^ int bb_factor;$/;" m struct:s_options +bb_factor base/vpr_types.h /^ int bb_factor;$/;" m struct:s_router_opts +bb_num_on_edges place/place.c /^static struct s_bb *bb_coords = NULL, *bb_num_on_edges = NULL;$/;" v typeref:struct: file: +bb_updated_before place/place.c /^static char * bb_updated_before = NULL;$/;" v file: +bend_cost base/ReadOptions.h /^ float bend_cost;$/;" m struct:s_options +bend_cost base/vpr_types.h /^ float bend_cost;$/;" m struct:s_router_opts +best_routing pack/cluster_legality.c /^static struct s_trace **best_routing;$/;" v typeref:struct:s_trace file: +beta base/ReadOptions.h /^ float beta;$/;" m struct:s_options +beta base/vpr_types.h /^ float beta;$/;" m struct:s_packer_opts +binary_not power/power_callibrate.c /^static char binary_not(char c) {$/;" f file: +binary_search base/globals.c /^int binary_search = -1;$/;" v +binary_search_place_and_route base/place_and_route.c /^static int binary_search_place_and_route(struct s_placer_opts placer_opts,$/;" f file: +bitfield base/vpr_types.h /^typedef size_t bitfield;$/;" t +bitstream_spice_file_postfix spice/spice_globals.c /^char* bitstream_spice_file_postfix = ".bitstream";$/;" v +bitstream_verilog_file_postfix syn_verilog/verilog_global.c /^char* bitstream_verilog_file_postfix = ".bitstream";$/;" v +bl ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_conf_bit* bl;$/;" m struct:s_conf_bit_info +blif base/read_blif.c /^static FILE *blif;$/;" v file: +blif_circuit_name base/globals.c /^char *blif_circuit_name = NULL;$/;" v +blif_file_name base/vpr_types.h /^ char *blif_file_name;$/;" m struct:s_packer_opts +blif_hash base/read_blif.c /^static struct s_hash **blif_hash;$/;" v typeref:struct:s_hash file: +blif_model ../../libarchfpga/include/physical_types.h /^ char *blif_model;$/;" m struct:s_pb_type +blif_testbench_verilog_file_postfix syn_verilog/verilog_global.c /^char* blif_testbench_verilog_file_postfix = "_blif_tb.v";$/;" v +blk_index place/place_macro.h /^ int blk_index;$/;" m struct:s_pl_macro_member +block base/globals.c /^struct s_block *block = NULL;$/;" v typeref:struct:s_block +block base/globals_declare.h /^struct s_block *block;$/;" v typeref:struct:s_block +block base/vpr_types.h /^ int block; \/* logical block primitive which this tnode is part of *\/$/;" m struct:s_tnode +block_color base/draw.c /^static enum color_types *net_color, *block_color;$/;" v typeref:enum: file: +block_criticality pack/cluster.c /^static float *block_criticality = NULL;$/;" v file: +block_delay base/ReadOptions.h /^ float block_delay;$/;" m struct:s_options +block_delay base/vpr_types.h /^ float block_delay;$/;" m struct:s_packer_opts +block_dist base/ReadOptions.h /^ int block_dist;$/;" m struct:s_options +block_dist base/vpr_types.h /^ int block_dist;$/;" m struct:s_placer_opts +block_id ../../libarchfpga/include/cad_types.h /^ int block_id;$/;" m struct:s_pack_pattern_block +block_num place/place.c /^ int block_num;$/;" m struct:s_pl_moved_block file: +blocks base/vpr_types.h /^ int *blocks;$/;" m struct:s_grid_tile +blocks_affected place/place.c /^static t_pl_blocks_to_be_moved blocks_affected;$/;" v file: +boolean ../../libarchfpga/include/util.h /^typedef int boolean;$/;" t +boolean ../../libarchfpga/include/util.h /^} boolean;$/;" t typeref:enum:__anon23 +breadth_first_add_source_to_heap route/route_breadth_first.c /^static void breadth_first_add_source_to_heap(int inet) {$/;" f file: +breadth_first_add_source_to_heap_cluster pack/cluster_legality.c /^static void breadth_first_add_source_to_heap_cluster(int inet) {$/;" f file: +breadth_first_expand_neighbours route/route_breadth_first.c /^static void breadth_first_expand_neighbours(int inode, float pcost, int inet,$/;" f file: +breadth_first_expand_neighbours_cluster pack/cluster_legality.c /^static void breadth_first_expand_neighbours_cluster(int inode, float pcost,$/;" f file: +breadth_first_expand_trace_segment route/route_breadth_first.c /^static void breadth_first_expand_trace_segment(struct s_trace *start_ptr,$/;" f file: +breadth_first_expand_trace_segment_cluster pack/cluster_legality.c /^static void breadth_first_expand_trace_segment_cluster($/;" f file: +breadth_first_route_net route/route_breadth_first.c /^static boolean breadth_first_route_net(int inet, float bend_cost) {$/;" f file: +breadth_first_route_net_cluster pack/cluster_legality.c /^static boolean breadth_first_route_net_cluster(int inet) {$/;" f file: +buf_size ../../libarchfpga/include/physical_types.h /^ float buf_size;$/;" m struct:s_switch_inf +buffer_info ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_buffer* buffer_info;$/;" m struct:s_spice_model_design_tech_info +buffer_net place/timing_place_lookup.c /^static void buffer_net( float* cur_net_delay )$/;" f file: +buffer_size ../../libarchfpga/include/physical_types.h /^ float buffer_size; \/* if not autosized, the clock buffer size *\/$/;" m struct:s_clock_network +buffer_size ../../libarchfpga/include/physical_types.h /^ float buffer_size;$/;" m struct:s_pb_graph_pin_power +buffer_size ../../libarchfpga/include/physical_types.h /^ float buffer_size;$/;" m struct:s_port_power +buffer_size_inf power/power.h /^ t_power_buffer_size_inf * buffer_size_inf;$/;" m struct:s_power_tech +buffer_type ../../libarchfpga/include/physical_types.h /^ e_power_buffer_type buffer_type;$/;" m struct:s_port_power +buffered ../../libarchfpga/include/physical_types.h /^ boolean buffered;$/;" m struct:s_switch_inf +buffered base/vpr_types.h /^ int buffered;$/;" m struct:s_rr_node +build_bidir_rr_opins route/rr_graph.c /^static void build_bidir_rr_opins(INP int i, INP int j,$/;" f file: +build_default_menu base/graphics.c /^build_default_menu (void) $/;" f file: +build_one_connection_block_info fpga_spice/fpga_spice_backannotate_utils.c /^void build_one_connection_block_info(t_cb* cur_cb, int cb_x, int cb_y, t_rr_type cb_type,$/;" f +build_one_switch_block_info fpga_spice/fpga_spice_backannotate_utils.c /^void build_one_switch_block_info(t_sb* cur_sb, int sb_x, int sb_y, $/;" f +build_prev_node_list_rr_nodes fpga_spice/fpga_spice_backannotate_utils.c /^void build_prev_node_list_rr_nodes(int LL_num_rr_nodes,$/;" f file: +build_rr_graph route/rr_graph.c /^void build_rr_graph(INP t_graph_type graph_type, INP int L_num_types,$/;" f +build_rr_sinks_sources route/rr_graph.c /^static void build_rr_sinks_sources(INP int i, INP int j,$/;" f file: +build_rr_xchan route/rr_graph.c /^static void build_rr_xchan(INP int i, INP int j,$/;" f file: +build_rr_ychan route/rr_graph.c /^static void build_rr_ychan(INP int i, INP int j,$/;" f file: +build_textarea base/graphics.c /^static void build_textarea (void) $/;" f file: +build_unidir_rr_opins route/rr_graph.c /^static void build_unidir_rr_opins(INP int i, INP int j,$/;" f file: +button base/graphics.c /^static t_button *button = NULL; \/* [0..num_buttons-1] *\/$/;" v file: +cal_capacitance_from_routing mrfpga/cal_capacitance.c /^void cal_capacitance_from_routing ( ) {$/;" f +calc_buffer_stage_effort power/power_util.c /^float calc_buffer_stage_effort(int N, float final_stage_size) {$/;" f +calculate_constraint timing/read_sdc.c /^static float calculate_constraint(t_sdc_clock source_domain, t_sdc_clock sink_domain) {$/;" f file: +callibrate power/PowerSpicedComponent.c /^void PowerCallibInputs::callibrate() {$/;" f class:PowerCallibInputs +callibrate power/PowerSpicedComponent.c /^void PowerSpicedComponent::callibrate(void) {$/;" f class:PowerSpicedComponent +cap timing/slre.c /^struct cap {$/;" s file: +cap_val ../../libarchfpga/fpga_spice_include/spice_types.h /^ float cap_val; $/;" m struct:s_spice_model_wire_param +capacitance ../../libarchfpga/include/physical_types.h /^ float capacitance;$/;" m struct:s_pb_graph_edge +capacity ../../libarchfpga/include/physical_types.h /^ int capacity;$/;" m struct:s_type_descriptor +capacity base/vpr_types.h /^ float capacity;$/;" m struct:s_place_region +capacity base/vpr_types.h /^ short capacity;$/;" m struct:s_rr_node +captab ../../libarchfpga/fpga_spice_include/spice_types.h /^ int captab;$/;" m struct:s_spice_params +capture timing/slre.c /^static const char *capture(const struct cap *caps, int num_caps, va_list ap) {$/;" f file: +capture_float timing/slre.c /^static const char *capture_float(const struct cap *cap, void *p, size_t len) {$/;" f file: +capture_int timing/slre.c /^static const char *capture_int(const struct cap *cap, void *p, size_t len) {$/;" f file: +capture_string timing/slre.c /^static const char *capture_string(const struct cap *cap, void *p, size_t len) {$/;" f file: +casecmp timing/slre.c /^static int casecmp(const void *p1, const void *p2, size_t len) {$/;" f file: +cat_llists ../../libarchfpga/linkedlist.c /^t_llist* cat_llists(t_llist* head1,$/;" f +cb ../../libarchfpga/include/physical_types.h /^ boolean *cb;$/;" m struct:s_segment_inf +cb base/vpr_types.h /^ boolean *cb;$/;" m struct:s_seg_details +cb_len ../../libarchfpga/include/physical_types.h /^ int cb_len;$/;" m struct:s_segment_inf +cb_switches ../../libarchfpga/include/physical_types.h /^ t_switch_inf* cb_switches;$/;" m struct:s_arch +cb_type_descriptors ../../libarchfpga/read_xml_arch_file.c /^static struct s_type_descriptor *cb_type_descriptors;$/;" v typeref:struct:s_type_descriptor file: +cbx_index_high ../../libarchfpga/fpga_spice_include/spice_types.h /^ int** cbx_index_high;$/;" m struct:s_spice_model +cbx_index_low ../../libarchfpga/fpga_spice_include/spice_types.h /^ int** cbx_index_low;$/;" m struct:s_spice_model +cbx_info base/globals.c /^t_cb** cbx_info = NULL;$/;" v +cby_index_high ../../libarchfpga/fpga_spice_include/spice_types.h /^ int** cby_index_high;$/;" m struct:s_spice_model +cby_index_low ../../libarchfpga/fpga_spice_include/spice_types.h /^ int** cby_index_low;$/;" m struct:s_spice_model +cby_info base/globals.c /^t_cb** cby_info = NULL;$/;" v +cc_constraints base/vpr_types.h /^ t_override_constraint * cc_constraints; \/* [0..num_cc_constraints - 1] array of such constraints *\/$/;" m struct:s_timing_constraints +cf_constraints base/vpr_types.h /^ t_override_constraint * cf_constraints; \/* [0..num_cf_constraints - 1] array of such constraints *\/$/;" m struct:s_timing_constraints +chain_name ../../libarchfpga/include/physical_types.h /^ char *chain_name;$/;" m struct:s_port +chain_pattern base/vpr_types.h /^ t_model_chain_pattern *chain_pattern; \/* If this is a chain molecule, chain that this molecule matches *\/$/;" m struct:s_pack_molecule +chain_root_pin ../../libarchfpga/include/cad_types.h /^ t_pb_graph_pin *chain_root_pin; \/* pointer to logic block input pin that drives this chain from the preceding logic block *\/ $/;" m struct:s_pack_patterns +chan_length ../../libarchfpga/fpga_spice_include/spice_types.h /^ float chan_length;$/;" m struct:s_spice_transistor_type +chan_rr_node base/vpr_types.h /^ t_rr_node*** chan_rr_node;$/;" m struct:s_cb +chan_rr_node base/vpr_types.h /^ t_rr_node*** chan_rr_node;$/;" m struct:s_sb +chan_rr_node_direction base/vpr_types.h /^ enum PORTS** chan_rr_node_direction;$/;" m struct:s_cb typeref:enum:s_cb::PORTS +chan_rr_node_direction base/vpr_types.h /^ enum PORTS** chan_rr_node_direction;$/;" m struct:s_sb typeref:enum:s_sb::PORTS +chan_width base/vpr_types.h /^ int* chan_width;$/;" m struct:s_cb +chan_width base/vpr_types.h /^ int* chan_width;$/;" m struct:s_sb +chan_width_io ../../libarchfpga/include/physical_types.h /^ float chan_width_io;$/;" m struct:s_chan_width_dist +chan_width_x base/globals.c /^int *chan_width_x = NULL; \/* [0..ny] *\/$/;" v +chan_width_x base/globals_declare.h /^int *chan_width_x, *chan_width_y; \/* numerical form *\/$/;" v +chan_width_y base/globals.c /^int *chan_width_y = NULL; \/* [0..nx] *\/$/;" v +chan_width_y base/globals_declare.h /^int *chan_width_x, *chan_width_y; \/* numerical form *\/$/;" v +chan_x_dist ../../libarchfpga/include/physical_types.h /^ t_chan chan_x_dist;$/;" m struct:s_chan_width_dist +chan_y_dist ../../libarchfpga/include/physical_types.h /^ t_chan chan_y_dist;$/;" m struct:s_chan_width_dist +change_button_text base/graphics.c /^void change_button_text(const char *button_name, const char *new_button_text) {$/;" f +change_button_text base/graphics.c /^void change_button_text(const char *button_text, const char *new_button_text) { }$/;" f +channel_width power/power.h /^ int channel_width;$/;" m struct:s_solution_inf +chanx_chany_adjacent route/check_route.c /^static int chanx_chany_adjacent(int chanx_node, int chany_node) {$/;" f file: +chanx_place_cost_fac place/place.c /^static float **chanx_place_cost_fac, **chany_place_cost_fac;$/;" v file: +chany_place_cost_fac place/place.c /^static float **chanx_place_cost_fac, **chany_place_cost_fac;$/;" v file: +checkTokenType util/token.c /^boolean checkTokenType(INP t_token token, OUTP enum e_token_type token_type) {$/;" f +check_adjacent route/check_route.c /^static boolean check_adjacent(int from_node, int to_node) {$/;" f file: +check_all_tracks_reach_pins route/rr_graph.c /^static void check_all_tracks_reach_pins(t_type_ptr type,$/;" f file: +check_and_add_mux_to_linked_list fpga_spice/fpga_spice_utils.c /^void check_and_add_mux_to_linked_list(t_llist** muxes_head,$/;" f +check_and_add_one_global_port_to_llist fpga_spice/fpga_spice_setup.c /^t_llist* check_and_add_one_global_port_to_llist(t_llist* old_head, $/;" f file: +check_and_count_models base/read_blif.c /^static void check_and_count_models(int doall, const char* model_name,$/;" f file: +check_and_rename_logical_block_and_net_names fpga_spice/fpga_spice_setup.c /^int check_and_rename_logical_block_and_net_names(t_llist* LL_reserved_syntax_char_head, $/;" f file: +check_clb_conn base/check_netlist.c /^static int check_clb_conn(int iblk, int num_conn) {$/;" f file: +check_clb_internal_nets base/check_netlist.c /^static int check_clb_internal_nets(int iblk) {$/;" f file: +check_clocks pack/cluster.c /^static void check_clocks(boolean *is_clock) {$/;" f file: +check_cluster_logical_blocks pack/cluster.c /^static void check_cluster_logical_blocks(t_pb *pb, boolean *blocks_checked) {$/;" f file: +check_clustering pack/cluster.c /^static void check_clustering(int num_clb, t_block *clb, boolean *is_clock) {$/;" f file: +check_conflict_syntax_char_in_string fpga_spice/fpga_spice_setup.c /^int check_conflict_syntax_char_in_string(t_llist* LL_reserved_syntax_char_head,$/;" f file: +check_connections_to_global_clb_pins base/check_netlist.c /^static int check_connections_to_global_clb_pins(int inet) {$/;" f file: +check_consistency_logical_block_net_num fpga_spice/fpga_spice_utils.c /^int check_consistency_logical_block_net_num(t_logical_block* lgk_blk, $/;" f +check_des_blk_pin clb_pin_remap/clb_pin_remap_util.c /^int check_des_blk_pin(int n_blks, t_block* blk,$/;" f +check_ff_spice_model_ports fpga_spice/fpga_spice_utils.c /^void check_ff_spice_model_ports(t_spice_model* cur_spice_model,$/;" f +check_fontsize base/graphics.c /^static int check_fontsize(int pointsize,$/;" f file: +check_for_duplicated_names base/check_netlist.c /^static int check_for_duplicated_names(void) {$/;" f file: +check_keywords_conflict fpga_spice/fpga_spice_setup.c /^void check_keywords_conflict(t_arch Arch) {$/;" f +check_locally_used_clb_opins route/check_route.c /^static void check_locally_used_clb_opins(t_ivec ** clb_opins_used_locally,$/;" f file: +check_lookahead_pins_used pack/cluster.c /^static boolean check_lookahead_pins_used(t_pb *cur_pb) {$/;" f file: +check_macro_can_be_placed place/place.c /^static int check_macro_can_be_placed(int imacro, int itype, int x, int y, int z) {$/;" f file: +check_macros_contained place/place_macro.c /^int check_macros_contained(t_pl_macro pl_macro_a,$/;" f +check_mem_model_blwl_inverted fpga_spice/fpga_spice_utils.c /^void check_mem_model_blwl_inverted(t_spice_model* cur_mem_model, $/;" f +check_negative_variation fpga_spice/fpga_spice_utils.c /^boolean check_negative_variation(float avg_val, $/;" f +check_net base/read_blif.c /^static void check_net(boolean sweep_hanging_nets_and_inputs) {$/;" f file: +check_netlist base/check_netlist.c /^void check_netlist() {$/;" f +check_node route/check_rr_graph.c /^void check_node(int inode, enum e_route_type route_type) {$/;" f +check_node_and_range route/check_route.c /^static void check_node_and_range(int inode, enum e_route_type route_type) {$/;" f file: +check_pass_transistors route/check_rr_graph.c /^static void check_pass_transistors(int from_node) {$/;" f file: +check_pb_graph pack/pb_type_graph.c /^static int check_pb_graph(void) {$/;" f file: +check_pb_graph_edge fpga_spice/fpga_spice_utils.c /^void check_pb_graph_edge(t_pb_graph_edge pb_graph_edge) {$/;" f +check_pb_graph_pin_edges fpga_spice/fpga_spice_utils.c /^void check_pb_graph_pin_edges(t_pb_graph_pin pb_graph_pin) {$/;" f +check_place place/place.c /^static void check_place(float bb_cost, float timing_cost, $/;" f file: +check_primitives base/check_netlist.c /^static int check_primitives(int iblk, int isub) {$/;" f file: +check_route route/check_route.c /^void check_route(enum e_route_type route_type, int num_switch,$/;" f +check_rr_graph route/check_rr_graph.c /^void check_rr_graph(INP t_graph_type graph_type, INP t_type_ptr types,$/;" f +check_sink route/check_route.c /^static void check_sink(int inode, int inet, boolean * pin_done) {$/;" f file: +check_source route/check_route.c /^static void check_source(int inode, int inet) {$/;" f file: +check_spice_model_name_conflict_syntax_char fpga_spice/fpga_spice_setup.c /^void check_spice_model_name_conflict_syntax_char(t_arch Arch,$/;" f file: +check_spice_model_structure_match_switch_inf fpga_spice/fpga_spice_utils.c /^boolean check_spice_model_structure_match_switch_inf(t_switch_inf target_switch_inf) {$/;" f +check_spice_models ../../libarchfpga/read_xml_spice.c /^static void check_spice_models(int num_spice_model,$/;" f file: +check_spice_models_grid_tb_cnt fpga_spice/fpga_spice_utils.c /^void check_spice_models_grid_tb_cnt(int num_spice_models,$/;" f +check_sram_spice_model_ports fpga_spice/fpga_spice_utils.c /^void check_sram_spice_model_ports(t_spice_model* cur_spice_model,$/;" f +check_src_blk_pin clb_pin_remap/clb_pin_remap_util.c /^int check_src_blk_pin(int n_blks, t_block* blk,$/;" f +check_subblock_internal_nets base/check_netlist.c /^static int check_subblock_internal_nets(int iblk, int isub) {$/;" f file: +check_subblocks base/check_netlist.c /^static int check_subblocks(int iblk) {$/;" f file: +check_switch route/check_route.c /^static void check_switch(struct s_trace *tptr, int num_switch) {$/;" f file: +check_tech_lib ../../libarchfpga/read_xml_spice.c /^static void check_tech_lib(t_spice_tech_lib tech_lib, $/;" f file: +check_timing_graph timing/path_delay2.c /^void check_timing_graph(int num_sinks) {$/;" f +child ../../libarchfpga/include/ezxml.h /^ ezxml_t child; \/* head of sub tag list, NULL if none *\/$/;" m struct:ezxml +child route/route_tree_timing.h /^ struct s_rt_node *child;$/;" m struct:s_linked_rt_edge typeref:struct:s_linked_rt_edge::s_rt_node +child timing/net_delay_types.h /^ struct s_rc_node *child;$/;" m struct:s_linked_rc_edge typeref:struct:s_linked_rc_edge::s_rc_node +child_list route/route_tree_timing.h /^ t_linked_rt_edge *child_list;$/;" m union:s_rt_node::__anon16 +child_list timing/net_delay_types.h /^ t_linked_rc_edge *child_list;$/;" m union:s_rc_node::__anon18 +child_pb_graph_nodes ../../libarchfpga/include/physical_types.h /^ struct s_pb_graph_node ***child_pb_graph_nodes; \/* [0..num_modes-1][0..num_pb_type_in_mode-1][0..num_pb-1] *\/$/;" m struct:s_pb_graph_node typeref:struct:s_pb_graph_node::s_pb_graph_node +child_pbs base/vpr_types.h /^ struct s_pb **child_pbs; \/* children pbs attached to this pb [0..num_child_pb_types - 1][0..child_type->num_pb - 1] *\/$/;" m struct:s_pb typeref:struct:s_pb::s_pb +children power/power.h /^ t_mux_node * children; \/* Multiplexers that drive the inputs [0..num_inputs-1] *\/$/;" m struct:s_mux_node +chomp_file_name_postfix fpga_spice/fpga_spice_utils.c /^char* chomp_file_name_postfix(char* file_name) {$/;" f +chomp_spice_node_prefix fpga_spice/fpga_spice_utils.c /^char* chomp_spice_node_prefix(char* spice_node_prefix) {$/;" f +chomp_verilog_node_prefix syn_verilog/verilog_utils.c /^char* chomp_verilog_node_prefix(char* verilog_node_prefix) {$/;" f +chunk_ptr_head ../../libarchfpga/include/util.h /^ struct s_linked_vptr *chunk_ptr_head; $/;" m struct:s_chunk typeref:struct:s_chunk::s_linked_vptr +circuit_p_io_removed base/globals.c /^struct s_linked_vptr *circuit_p_io_removed = NULL;$/;" v typeref:struct:s_linked_vptr +class_inf ../../libarchfpga/include/physical_types.h /^ struct s_class *class_inf; \/* [0..num_class-1] *\/$/;" m struct:s_type_descriptor typeref:struct:s_type_descriptor::s_class +class_type ../../libarchfpga/include/physical_types.h /^ enum e_pb_type_class class_type;$/;" m struct:s_pb_type typeref:enum:s_pb_type::e_pb_type_class +clay_logical_equivalence_handling base/vpr_api.c /^static void clay_logical_equivalence_handling(const t_arch *arch) {$/;" f file: +clay_lut_input_rebalancing base/vpr_api.c /^static void clay_lut_input_rebalancing(int iblock, t_pb *pb) {$/;" f file: +clay_reload_ble_locations base/vpr_api.c /^static void clay_reload_ble_locations(int iblock) {$/;" f file: +clb_grid ../../libarchfpga/include/physical_types.h /^ struct s_clb_grid clb_grid;$/;" m struct:s_arch typeref:struct:s_arch::s_clb_grid +clb_index base/vpr_types.h /^ int clb_index; \/* Complex block index that this logical block got mapped to *\/$/;" m struct:s_logical_block +clb_net base/globals.c /^struct s_net *clb_net = NULL;$/;" v typeref:struct:s_net +clb_net_density power/power_util.c /^float clb_net_density(int net_idx) {$/;" f +clb_net_prob power/power_util.c /^float clb_net_prob(int net_idx) {$/;" f +clb_opins_used_locally place/timing_place_lookup.c /^static t_ivec **clb_opins_used_locally;$/;" v file: +clb_to_vpack_net_mapping base/globals.c /^int *clb_to_vpack_net_mapping = NULL; \/* [0..num_clb_nets - 1] *\/$/;" v +clear_buffer mrfpga/buffer_insertion.c /^void clear_buffer( )$/;" f +clearscreen base/graphics.c /^clearscreen (void) $/;" f +clearscreen base/graphics.c /^void clearscreen (void) { }$/;" f +clock ../../libarchfpga/include/physical_types.h /^ char * clock;$/;" m struct:s_pin_to_pin_annotation +clock_delay base/vpr_types.h /^ float clock_delay; \/* The time taken for a clock signal to get to the flip-flop or I\/O (assumed 0 for I\/Os). *\/$/;" m struct:s_tnode +clock_domain base/vpr_types.h /^ int clock_domain; \/* Index of the clock in g_sdc->constrained_clocks which this flip-flop or I\/O is constrained on. *\/$/;" m struct:s_tnode +clock_inf ../../libarchfpga/include/physical_types.h /^ t_clock_network *clock_inf; \/* Details about each clock *\/$/;" m struct:s_clock_arch +clock_name base/vpr_types.h /^ char * clock_name; \/* Clock it was constrained on *\/$/;" m struct:s_io +clock_names timing/read_sdc.c /^ char ** clock_names;$/;" m struct:s_sdc_exclusive_group file: +clock_net base/vpr_types.h /^ int clock_net; \/* Clock net connected to this logical_block. *\/$/;" m struct:s_logical_block +clock_net base/vpr_types.h /^ int clock_net; \/* Records clock net driving a flip-flop, valid only for lowest-level, flip-flop PBs *\/$/;" m struct:s_pb +clock_net_tnode base/vpr_types.h /^ struct s_tnode *clock_net_tnode; \/* correspnding clock net tnode *\/$/;" m struct:s_logical_block typeref:struct:s_logical_block::s_tnode +clock_pins ../../libarchfpga/include/physical_types.h /^ t_pb_graph_pin **clock_pins; \/* [0..num_clock_ports-1] [0..num_port_pins-1]*\/$/;" m struct:s_pb_graph_node +clock_slew_fall_time ../../libarchfpga/fpga_spice_include/spice_types.h /^ float clock_slew_fall_time; $/;" m struct:s_spice_stimulate_params +clock_slew_fall_type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type clock_slew_fall_type;$/;" m struct:s_spice_stimulate_params typeref:enum:s_spice_stimulate_params::e_spice_accuracy_type +clock_slew_rise_time ../../libarchfpga/fpga_spice_include/spice_types.h /^ float clock_slew_rise_time; $/;" m struct:s_spice_stimulate_params +clock_slew_rise_type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type clock_slew_rise_type;$/;" m struct:s_spice_stimulate_params typeref:enum:s_spice_stimulate_params::e_spice_accuracy_type +clocks ../../libarchfpga/include/physical_types.h /^ t_clock_arch * clocks;$/;" m struct:s_arch +close ../../libarchfpga/ezxml.c 61;" d file: +close_graphics base/graphics.c /^close_graphics (void) $/;" f +close_graphics base/graphics.c /^void close_graphics (void) { }$/;" f +close_postscript base/graphics.c /^void close_postscript (void) $/;" f +close_postscript base/graphics.c /^void close_postscript (void) { }$/;" f +cluster_placement_primitive ../../libarchfpga/include/physical_types.h /^ struct s_cluster_placement_primitive *cluster_placement_primitive; \/* pointer to indexing structure useful during packing stage *\/$/;" m struct:s_pb_graph_node typeref:struct:s_pb_graph_node::s_cluster_placement_primitive +cluster_seed_type base/ReadOptions.h /^ enum e_cluster_seed cluster_seed_type;$/;" m struct:s_options typeref:enum:s_options::e_cluster_seed +cluster_seed_type base/vpr_types.h /^ enum e_cluster_seed cluster_seed_type;$/;" m struct:s_packer_opts typeref:enum:s_packer_opts::e_cluster_seed +cluster_size base/ReadOptions.h /^ int cluster_size;$/;" m struct:s_options +cmos_variation ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_mc_variation_params cmos_variation;$/;" m struct:s_spice_mc_params +cnt ../../libarchfpga/fpga_spice_include/spice_types.h /^ int cnt; \/* Used in mux_testbench only*\/$/;" m struct:s_spice_mux_model +cnt ../../libarchfpga/fpga_spice_include/spice_types.h /^ int cnt;$/;" m struct:s_spice_model +code timing/slre.c /^ unsigned char code[256];$/;" m struct:slre file: +code_size timing/slre.c /^ int code_size;$/;" m struct:slre file: +col_rel ../../libarchfpga/include/physical_types.h /^ float col_rel;$/;" m struct:s_grid_loc_def +color_types base/easygl_constants.h /^enum color_types {WHITE, BLACK, DARKGREY, LIGHTGREY, BLUE, GREEN, YELLOW,$/;" g +colors base/graphics.c /^static int colors[NUM_COLOR];$/;" v file: +combine_buffer_plan mrfpga/buffer_insertion.c /^static t_buffer_plan combine_buffer_plan( t_buffer_plan slow_branch, t_buffer_plan* plan_whole, int num_whole, int num_pins )$/;" f file: +commit_lookahead_pins_used pack/cluster.c /^static void commit_lookahead_pins_used(t_pb *cur_pb) {$/;" f file: +commit_primitive pack/cluster_placement.c /^void commit_primitive(INOUTP t_cluster_placement_stats *cluster_placement_stats,$/;" f +comp_bb_cost place/place.c /^static float comp_bb_cost(enum cost_methods method) {$/;" f file: +comp_delta_td_cost place/place.c /^static void comp_delta_td_cost(float *delta_timing, float *delta_delay) {$/;" f file: +comp_td_costs place/place.c /^static void comp_td_costs(float *timing_cost, float *connection_delay_sum) {$/;" f file: +comp_td_point_to_point_delay place/place.c /^static float comp_td_point_to_point_delay(int inet, int ipin) {$/;" f file: +comp_width base/place_and_route.c /^static float comp_width(t_chan * chan, float x, float separation) {$/;" f file: +compare_molecule_gain pack/cluster.c /^static int compare_molecule_gain(const void *a, const void *b) {$/;" f file: +compare_pack_pattern pack/prepack.c /^static int compare_pack_pattern(const t_pack_patterns *pattern_a, const t_pack_patterns *pattern_b) {$/;" f file: +compile timing/slre.c /^static void compile(struct slre *r, const char **re) {$/;" f file: +compile2 timing/slre.c /^static const char *compile2(struct slre *r, const char *re) {$/;" f file: +complete_truth_table_line fpga_spice/fpga_spice_utils.c /^char* complete_truth_table_line(int lut_size,$/;" f +component_callibration power/power.h /^ PowerSpicedComponent ** component_callibration;$/;" m struct:s_power_commonly_used +component_usage power/PowerSpicedComponent.h /^ float (*component_usage)(int num_inputs, float transistor_size);$/;" m class:PowerSpicedComponent +components power/power_components.h /^ t_power_usage * components;$/;" m struct:s_power_breakdown +compress_netlist base/read_blif.c /^static void compress_netlist(void) {$/;" f file: +compute_and_mark_lookahead_pins_used pack/cluster.c /^static void compute_and_mark_lookahead_pins_used(int ilogical_block) {$/;" f file: +compute_and_mark_lookahead_pins_used_for_pin pack/cluster.c /^static void compute_and_mark_lookahead_pins_used_for_pin($/;" f file: +compute_delay_lookup_tables place/timing_place_lookup.c /^void compute_delay_lookup_tables(struct s_router_opts router_opts,$/;" f +compute_delta_arrays place/timing_place_lookup.c /^static void compute_delta_arrays(struct s_router_opts router_opts,$/;" f file: +compute_delta_clb_to_clb place/timing_place_lookup.c /^static void compute_delta_clb_to_clb(struct s_router_opts router_opts,$/;" f file: +compute_delta_clb_to_io place/timing_place_lookup.c /^static void compute_delta_clb_to_io(struct s_router_opts router_opts,$/;" f file: +compute_delta_io_to_clb place/timing_place_lookup.c /^static void compute_delta_io_to_clb(struct s_router_opts router_opts,$/;" f file: +compute_delta_io_to_io place/timing_place_lookup.c /^static void compute_delta_io_to_io(struct s_router_opts router_opts,$/;" f file: +compute_primitive_base_cost util/vpr_utils.c /^float compute_primitive_base_cost(INP t_pb_graph_node *primitive) {$/;" f +conf_bit_head ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_llist* conf_bit_head; $/;" m struct:s_sram_orgz_info +conf_bits_head syn_verilog/verilog_global.c /^t_llist* conf_bits_head = NULL;$/;" v +conf_bits_lsb base/vpr_types.h /^ int conf_bits_lsb; \/* LSB of configuration bits *\/$/;" m struct:s_cb +conf_bits_lsb base/vpr_types.h /^ int conf_bits_lsb; \/* LSB of configuration bits *\/$/;" m struct:s_sb +conf_bits_msb base/vpr_types.h /^ int conf_bits_msb; \/* MSB of configuration bits *\/$/;" m struct:s_cb +conf_bits_msb base/vpr_types.h /^ int conf_bits_msb; \/* MSB of configuration bits *\/$/;" m struct:s_sb +config_spice_model_input_output_buffers_pass_gate fpga_spice/fpga_spice_utils.c /^void config_spice_model_input_output_buffers_pass_gate(int num_spice_models, $/;" f +config_spice_model_port_inv_spice_model fpga_spice/fpga_spice_utils.c /^void config_spice_model_port_inv_spice_model(int num_spice_models, $/;" f +config_spice_models_sram_port_spice_model fpga_spice/fpga_spice_utils.c /^void config_spice_models_sram_port_spice_model(int num_spice_model,$/;" f +configure_lut_sram_bits_per_line_rec fpga_spice/fpga_spice_utils.c /^void configure_lut_sram_bits_per_line_rec(int** sram_bits, $/;" f +conn_list base/verilog_writer.h /^}conn_list;$/;" t typeref:struct:found_connectivity +connect_pb_des_pin_to_src_pin clb_pin_remap/clb_pin_remap_util.c /^void connect_pb_des_pin_to_src_pin(t_pb* src_pb,$/;" f +connection_driven base/ReadOptions.h /^ boolean connection_driven;$/;" m struct:s_options +connection_driven base/vpr_types.h /^ boolean connection_driven;$/;" m struct:s_packer_opts +connectiongain base/vpr_types.h /^ std::map connectiongain; \/* [0..num_logical_blocks-1] Weighted sum of connections to attraction function *\/$/;" m struct:s_pb_stats +connections ../../libarchfpga/include/cad_types.h /^ struct s_pack_pattern_connections *connections; \/* linked list of connections of logic blocks in pattern *\/$/;" m struct:s_pack_pattern_block typeref:struct:s_pack_pattern_block::s_pack_pattern_connections +constant_net_delay base/ReadOptions.h /^ float constant_net_delay;$/;" m struct:s_options +constant_net_delay base/vpr_types.h /^ float constant_net_delay; \/* timing information when place and route not run *\/$/;" m struct:s_vpr_setup +constrained_clocks base/vpr_types.h /^ t_clock * constrained_clocks; \/* [0..g_sdc->num_constrained_clocks - 1] array of clocks with timing constraints *\/$/;" m struct:s_timing_constraints +constrained_inputs base/vpr_types.h /^ t_io * constrained_inputs; \/* [0..num_constrained_inputs - 1] array of inputs with timing constraints *\/$/;" m struct:s_timing_constraints +constrained_outputs base/vpr_types.h /^ t_io * constrained_outputs; \/* [0..num_constrained_outputs - 1] array of outputs with timing constraints *\/$/;" m struct:s_timing_constraints +constraint base/vpr_types.h /^ float constraint;$/;" m struct:s_override_constraint +cont ../../libarchfpga/util.c /^static int cont; \/* line continued? *\/$/;" v file: +convert_chan_rr_node_direction_to_string fpga_spice/fpga_spice_utils.c /^char* convert_chan_rr_node_direction_to_string(enum PORTS chan_rr_node_direction) {$/;" f +convert_chan_type_to_string fpga_spice/fpga_spice_utils.c /^char* convert_chan_type_to_string(t_rr_type chan_type) {$/;" f +convert_side_index_to_string fpga_spice/fpga_spice_utils.c /^char* convert_side_index_to_string(int side) {$/;" f +copy_delay mrfpga/buffer_insertion.c /^static void copy_delay( float* base, float* source, t_linked_int* index )$/;" f file: +copy_from_float_array mrfpga/buffer_insertion.c /^static float* copy_from_float_array( float* source, int num )$/;" f file: +copy_from_list mrfpga/mrfpga_util.c /^t_linked_int* copy_from_list( t_linked_int* base, t_linked_int* target )$/;" f +cost base/vpr_types.h /^ float cost;$/;" m struct:s_place_region +cost route/route_common.h /^ float cost;$/;" m struct:s_heap +cost_index base/vpr_types.h /^ short cost_index;$/;" m struct:s_rr_node +cost_methods place/place.c /^enum cost_methods {$/;" g file: +count base/read_blif.c /^ int count;$/;" m struct:s_model_stats file: +count util/hash.h /^ int count;$/;" m struct:s_hash +count_bidir_routing_transistors route/rr_graph_area.c /^void count_bidir_routing_transistors(int num_switch, float R_minW_nmos,$/;" f +count_blk_one_class_num_conflict clb_pin_remap/clb_pin_remap_util.c /^int count_blk_one_class_num_conflict(t_block* target_blk, int class_index,$/;" f +count_connections place/place.c /^static int count_connections() {$/;" f file: +count_netlist_clocks base/stats.c /^int count_netlist_clocks(void) {$/;" f +count_netlist_clocks_as_constrained_clocks timing/read_sdc.c /^static void count_netlist_clocks_as_constrained_clocks(void) {$/;" f file: +count_netlist_ios_as_constrained_ios timing/read_sdc.c /^static void count_netlist_ios_as_constrained_ios(char * clock_name, float io_delay) {$/;" f file: +count_num_conf_bit_one_interc fpga_spice/fpga_spice_utils.c /^int count_num_conf_bit_one_interc(t_interconnect* cur_interc,$/;" f +count_num_conf_bits_one_spice_model fpga_spice/fpga_spice_utils.c /^int count_num_conf_bits_one_spice_model(t_spice_model* cur_spice_model,$/;" f +count_num_conf_bits_pb_type_mode_interc fpga_spice/fpga_spice_utils.c /^int count_num_conf_bits_pb_type_mode_interc(t_mode* cur_pb_type_mode,$/;" f +count_num_reserved_conf_bit_one_interc fpga_spice/fpga_spice_utils.c /^int count_num_reserved_conf_bit_one_interc(t_interconnect* cur_interc,$/;" f +count_num_reserved_conf_bits_one_lut_spice_model fpga_spice/fpga_spice_utils.c /^int count_num_reserved_conf_bits_one_lut_spice_model(t_spice_model* cur_spice_model,$/;" f +count_num_reserved_conf_bits_one_mux_spice_model fpga_spice/fpga_spice_utils.c /^int count_num_reserved_conf_bits_one_mux_spice_model(t_spice_model* cur_spice_model,$/;" f +count_num_reserved_conf_bits_one_rram_sram_spice_model fpga_spice/fpga_spice_utils.c /^int count_num_reserved_conf_bits_one_rram_sram_spice_model(t_spice_model* cur_spice_model,$/;" f +count_num_reserved_conf_bits_one_spice_model fpga_spice/fpga_spice_utils.c /^int count_num_reserved_conf_bits_one_spice_model(t_spice_model* cur_spice_model,$/;" f +count_num_reserved_conf_bits_pb_type_mode_interc fpga_spice/fpga_spice_utils.c /^int count_num_reserved_conf_bits_pb_type_mode_interc(t_mode* cur_pb_type_mode,$/;" f +count_num_sram_bits_one_spice_model fpga_spice/fpga_spice_utils.c /^int count_num_sram_bits_one_spice_model(t_spice_model* cur_spice_model,$/;" f +count_routing_memristor_buffer mrfpga/buffer_insertion.c /^void count_routing_memristor_buffer( int num_per_channel, float buffer_size )$/;" f +count_routing_transistors route/rr_graph_area.c /^void count_routing_transistors(enum e_directionality directionality,$/;" f +count_sinks_internal_cb_rr_graph_net_nums base/read_netlist.c /^static int count_sinks_internal_cb_rr_graph_net_nums($/;" f file: +count_unidir_routing_transistors route/rr_graph_area.c /^void count_unidir_routing_transistors(t_segment_inf * segment_inf,$/;" f +count_verilog_connection_box_conf_bits syn_verilog/verilog_routing.c /^int count_verilog_connection_box_conf_bits(t_cb* cur_cb_info) {$/;" f +count_verilog_connection_box_interc_conf_bits syn_verilog/verilog_routing.c /^int count_verilog_connection_box_interc_conf_bits(t_rr_node* cur_rr_node) {$/;" f +count_verilog_connection_box_interc_reserved_conf_bits syn_verilog/verilog_routing.c /^int count_verilog_connection_box_interc_reserved_conf_bits(t_rr_node* cur_rr_node) {$/;" f +count_verilog_connection_box_one_side_conf_bits syn_verilog/verilog_routing.c /^int count_verilog_connection_box_one_side_conf_bits(int num_ipin_rr_nodes,$/;" f +count_verilog_connection_box_one_side_reserved_conf_bits syn_verilog/verilog_routing.c /^int count_verilog_connection_box_one_side_reserved_conf_bits(int num_ipin_rr_nodes,$/;" f +count_verilog_connection_box_reserved_conf_bits syn_verilog/verilog_routing.c /^int count_verilog_connection_box_reserved_conf_bits(t_cb* cur_cb_info) {$/;" f +count_verilog_switch_box_conf_bits syn_verilog/verilog_routing.c /^int count_verilog_switch_box_conf_bits(t_sb* cur_sb_info) {$/;" f +count_verilog_switch_box_interc_conf_bits syn_verilog/verilog_routing.c /^int count_verilog_switch_box_interc_conf_bits(int switch_box_x, int switch_box_y, int chan_side, $/;" f +count_verilog_switch_box_interc_reserved_conf_bits syn_verilog/verilog_routing.c /^int count_verilog_switch_box_interc_reserved_conf_bits(int switch_box_x, int switch_box_y, int chan_side, $/;" f +count_verilog_switch_box_reserved_conf_bits syn_verilog/verilog_routing.c /^int count_verilog_switch_box_reserved_conf_bits(t_sb* cur_sb_info) {$/;" f +cpd base/vpr_types.h /^ float ** cpd;$/;" m struct:s_timing_stats +cpt_subckt_name spice/spice_globals.c /^char* cpt_subckt_name = "cpt";$/;" v +create_button base/graphics.c /^void create_button (const char *prev_button_text , const char *button_text, $/;" f +create_button base/graphics.c /^void create_button (const char *prev_button_text , const char *button_text,$/;" f +create_dir_path fpga_spice/fpga_spice_utils.c /^int create_dir_path(char* dir_path) {$/;" f +create_llist ../../libarchfpga/linkedlist.c /^t_llist* create_llist(int len) {$/;" f +criticality_exp base/ReadOptions.h /^ float criticality_exp;$/;" m struct:s_options +criticality_exp base/vpr_types.h /^ float criticality_exp;$/;" m struct:s_router_opts +critindexarray pack/cluster.c /^static int *critindexarray = NULL;$/;" v file: +cross_count place/place.c /^static const float cross_count[50] = { \/* [0..49] *\/1.0, 1.0, 1.0, 1.0828, 1.1536, 1.2206, 1.2823, 1.3385, 1.3991, 1.4493, 1.4974,$/;" v file: +cur ../../libarchfpga/include/ezxml.h /^ ezxml_t cur; \/* current xml tree insertion point *\/$/;" m struct:ezxml_root +curr_cluster_index pack/cluster_legality.c /^static int curr_cluster_index;$/;" v file: +curr_molecule base/vpr_types.h /^ t_pack_molecule *curr_molecule; \/* current molecule being considered for packing *\/$/;" m struct:s_cluster_placement_stats +current_draw_mode base/graphics.c /^static e_draw_mode current_draw_mode;$/;" v file: +current_gc base/graphics.c /^static GC gc, gcxor, gc_menus, current_gc;$/;" v file: +current_random ../../libarchfpga/util.c /^static unsigned int current_random = 0;$/;" v file: +currentcolor base/graphics.c /^static int currentcolor;$/;" v file: +currentfontsize base/graphics.c /^static int currentfontsize;$/;" v file: +currentlinestyle base/graphics.c /^static int currentlinestyle;$/;" v file: +currentlinewidth base/graphics.c /^static int currentlinewidth;$/;" v file: +cxClient base/graphics.c /^static int cxClient, cyClient;$/;" v file: +cyClient base/graphics.c /^static int cxClient, cyClient;$/;" v file: +data ../../libarchfpga/include/util.h /^ int data;$/;" m struct:s_linked_int +data timing/slre.c /^ unsigned char data[256];$/;" m struct:slre file: +data util/token.h /^ char *data;$/;" m struct:s_token +data_size timing/slre.c /^ int data_size;$/;" m struct:slre file: +data_vptr ../../libarchfpga/include/util.h /^ void *data_vptr;$/;" m struct:s_linked_vptr +dc ../../libarchfpga/include/physical_types.h /^ float dc;$/;" m struct:s_chan +dealloc_mux_graph power/power.c /^static void dealloc_mux_graph(t_mux_node * node) {$/;" f file: +dealloc_mux_graph_rec power/power.c /^static void dealloc_mux_graph_rec(t_mux_node * node) {$/;" f file: +decode_and_add_verilog_sram_membank_conf_bit_to_llist syn_verilog/verilog_utils.c /^decode_and_add_verilog_sram_membank_conf_bit_to_llist(t_sram_orgz_info* cur_sram_orgz_info,$/;" f +decode_cmos_mux_sram_bits fpga_spice/fpga_spice_utils.c /^void decode_cmos_mux_sram_bits(t_spice_model* mux_spice_model,$/;" f +decode_mode_bits fpga_spice/fpga_spice_utils.c /^int* decode_mode_bits(char* mode_bits, int* num_sram_bits) {$/;" f +decode_multilevel_mux_sram_bits fpga_spice/fpga_spice_utils.c /^int* decode_multilevel_mux_sram_bits(int fan_in,$/;" f +decode_onelevel_mux_sram_bits fpga_spice/fpga_spice_utils.c /^int* decode_onelevel_mux_sram_bits(int fan_in,$/;" f +decode_tree_mux_sram_bits fpga_spice/fpga_spice_utils.c /^int* decode_tree_mux_sram_bits(int fan_in,$/;" f +decode_verilog_memory_bank_sram syn_verilog/verilog_utils.c /^void decode_verilog_memory_bank_sram(t_spice_model* cur_sram_spice_model, int sram_bit,$/;" f +decode_verilog_multilevel_4t1r_mux syn_verilog/verilog_utils.c /^void decode_verilog_multilevel_4t1r_mux(int num_level, int num_input_basis,$/;" f +decode_verilog_one_level_4t1r_mux syn_verilog/verilog_utils.c /^void decode_verilog_one_level_4t1r_mux(int path_id, $/;" f +decode_verilog_rram_mux syn_verilog/verilog_utils.c /^void decode_verilog_rram_mux(t_spice_model* mux_spice_model,$/;" f +decoders_verilog_file_name syn_verilog/verilog_global.c /^char* decoders_verilog_file_name = "decoders.v";$/;" v +default_lb_dir_name syn_verilog/syn_verilog_api.c /^static char* default_lb_dir_name = "lb\/";$/;" v file: +default_message base/draw.c /^static char default_message[BUFSIZE]; \/* Default screen message on screen *\/$/;" v file: +default_mode_num_conf_bits ../../libarchfpga/include/physical_types.h /^ int default_mode_num_conf_bits;$/;" m struct:s_pb_type +default_mode_num_iopads ../../libarchfpga/include/physical_types.h /^ int default_mode_num_iopads;$/;" m struct:s_pb_type +default_mode_num_mode_bits ../../libarchfpga/include/physical_types.h /^ int default_mode_num_mode_bits;$/;" m struct:s_pb_type +default_mode_num_reserved_conf_bits ../../libarchfpga/include/physical_types.h /^ int default_mode_num_reserved_conf_bits;$/;" m struct:s_pb_type +default_output_name base/globals.c /^char *default_output_name = NULL;$/;" v +default_rr_dir_name syn_verilog/syn_verilog_api.c /^static char* default_rr_dir_name = "routing\/";$/;" v file: +default_signal_init_value fpga_spice/fpga_spice_globals.c /^int default_signal_init_value = 0;$/;" v +default_spice_dir_path spice/spice_api.c /^static char* default_spice_dir_path = "spice_netlists\/";$/;" v file: +default_submodule_dir_name syn_verilog/syn_verilog_api.c /^static char* default_submodule_dir_name = "sub_module\/";$/;" v file: +default_val ../../libarchfpga/fpga_spice_include/spice_types.h /^ int default_val;$/;" m struct:s_spice_model_port +default_verilog_dir_name syn_verilog/syn_verilog_api.c /^static char* default_verilog_dir_name = "syn_verilogs\/";$/;" v file: +define_idle_mode ../../libarchfpga/include/physical_types.h /^ int define_idle_mode; $/;" m struct:s_mode +define_physical_mode ../../libarchfpga/include/physical_types.h /^ int define_physical_mode; $/;" m struct:s_mode +delay base/vpr_types.h /^ float delay; \/* Delay through the I\/O in this constraint *\/$/;" m struct:s_io +delay_max ../../libarchfpga/include/physical_types.h /^ float delay_max;$/;" m struct:s_pb_graph_edge +delay_min ../../libarchfpga/include/physical_types.h /^ float delay_min;$/;" m struct:s_pb_graph_edge +delayless_switch base/vpr_types.h /^ short delayless_switch;$/;" m struct:s_det_routing_arch +delete_in_vptr_list ../../libarchfpga/util.c /^delete_in_vptr_list(struct s_linked_vptr *head) {$/;" f +delta_clb_to_clb place/timing_place_lookup.c /^float **delta_clb_to_clb;$/;" v +delta_clb_to_io place/timing_place_lookup.c /^float **delta_clb_to_io;$/;" v +delta_io_to_clb place/timing_place_lookup.c /^float **delta_io_to_clb;$/;" v +delta_io_to_io place/timing_place_lookup.c /^float **delta_io_to_io;$/;" v +dens ../../libarchfpga/include/physical_types.h /^ float dens; \/* Switching density of net assigned to this clock *\/$/;" m struct:s_clock_network +density ../../libarchfpga/fpga_spice_include/spice_types.h /^ float density;$/;" m struct:s_spice_net_info +density base/vpr_types.h /^ float density;$/;" m struct:s_net_power +depth ../../libarchfpga/include/physical_types.h /^ int depth; \/* depth of pb_type *\/$/;" m struct:s_pb_type +deselect_all base/draw.c /^static void deselect_all(void) {$/;" f file: +design_param_header_file_name spice/spice_globals.c /^char* design_param_header_file_name = "design_params.sp";$/;" v +design_param_postfix_input_buf_size spice/spice_globals.c /^char* design_param_postfix_input_buf_size = "_input_buf_size"; $/;" v +design_param_postfix_output_buf_size spice/spice_globals.c /^char* design_param_postfix_output_buf_size = "_output_buf_size"; $/;" v +design_param_postfix_pass_gate_logic_nmos_size spice/spice_globals.c /^char* design_param_postfix_pass_gate_logic_nmos_size = "_pgl_nmos_size"; $/;" v +design_param_postfix_pass_gate_logic_pmos_size spice/spice_globals.c /^char* design_param_postfix_pass_gate_logic_pmos_size = "_pgl_pmos_size"; $/;" v +design_param_postfix_rram_roff spice/spice_globals.c /^char* design_param_postfix_rram_roff = "_rram_roff"; $/;" v +design_param_postfix_rram_ron spice/spice_globals.c /^char* design_param_postfix_rram_ron = "_rram_ron"; $/;" v +design_param_postfix_rram_wprog_reset_nmos spice/spice_globals.c /^char* design_param_postfix_rram_wprog_reset_nmos = "_rram_wprog_reset_nmos"; $/;" v +design_param_postfix_rram_wprog_reset_pmos spice/spice_globals.c /^char* design_param_postfix_rram_wprog_reset_pmos = "_rram_wprog_reset_pmos"; $/;" v +design_param_postfix_rram_wprog_set_nmos spice/spice_globals.c /^char* design_param_postfix_rram_wprog_set_nmos = "_rram_wprog_set_nmos"; $/;" v +design_param_postfix_rram_wprog_set_pmos spice/spice_globals.c /^char* design_param_postfix_rram_wprog_set_pmos = "_rram_wprog_set_pmos"; $/;" v +design_param_postfix_wire_param_cap_val spice/spice_globals.c /^char* design_param_postfix_wire_param_cap_val = "_wire_param_cap_val"; $/;" v +design_param_postfix_wire_param_res_val spice/spice_globals.c /^char* design_param_postfix_wire_param_res_val = "_wire_param_res_val"; $/;" v +design_tech ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_model_design_tech design_tech;$/;" m struct:s_spice_model typeref:enum:s_spice_model::e_spice_model_design_tech +design_tech_info ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_design_tech_info design_tech_info;$/;" m struct:s_spice_model +destroy_button base/graphics.c /^destroy_button (const char *button_text) $/;" f +destroy_button base/graphics.c /^void destroy_button (const char *button_text) { }$/;" f +determine_decoder_size syn_verilog/verilog_utils.c /^int determine_decoder_size(int num_addr_out) {$/;" f +determine_io_grid_side fpga_spice/fpga_spice_utils.c /^int determine_io_grid_side(int x,$/;" f +determine_lut_path_id fpga_spice/fpga_spice_utils.c /^int determine_lut_path_id(int lut_size,$/;" f +determine_num_input_basis_multilevel_mux fpga_spice/fpga_spice_utils.c /^int determine_num_input_basis_multilevel_mux(int mux_size,$/;" f +determine_num_sram_bits_mux_basis_subckt fpga_spice/fpga_spice_utils.c /^int determine_num_sram_bits_mux_basis_subckt(t_spice_model* mux_spice_model,$/;" f +determine_sb_port_coordinator fpga_spice/fpga_spice_utils.c /^void determine_sb_port_coordinator(t_sb cur_sb_info, int side, $/;" f +determine_tree_mux_level fpga_spice/fpga_spice_utils.c /^int determine_tree_mux_level(int mux_size) {$/;" f +determine_verilog_blwl_decoder_size syn_verilog/verilog_decoder.c /^void determine_verilog_blwl_decoder_size(INP t_sram_orgz_info* cur_sram_verilog_orgz_info,$/;" f +determine_verilog_generic_port_split_sign syn_verilog/verilog_utils.c /^char determine_verilog_generic_port_split_sign(enum e_dump_verilog_port_type dump_port_type) {$/;" f +dir ../../libarchfpga/include/logic_types.h /^ enum PORTS dir; \/* port direction *\/$/;" m struct:s_model_ports typeref:enum:s_model_ports::PORTS +direction base/vpr_types.h /^ enum e_direction direction; \/* UDSD by AY *\/$/;" m struct:s_rr_node typeref:enum:s_rr_node::e_direction +direction base/vpr_types.h /^ enum e_direction direction; \/* UDSD by AY *\/$/;" m struct:s_seg_details typeref:enum:s_seg_details::e_direction +directionality ../../libarchfpga/include/physical_types.h /^ enum e_directionality directionality;$/;" m struct:s_segment_inf typeref:enum:s_segment_inf::e_directionality +directionality base/vpr_types.h /^ enum e_directionality directionality; \/* UDSD by AY *\/$/;" m struct:s_det_routing_arch typeref:enum:s_det_routing_arch::e_directionality +directionality base/vpr_types.h /^ enum e_directionality directionality; \/* UDSD by AY *\/$/;" m struct:s_cb typeref:enum:s_cb::e_directionality +directionality base/vpr_types.h /^ enum e_directionality directionality; \/* UDSD by AY *\/$/;" m struct:s_sb typeref:enum:s_sb::e_directionality +discover_all_forced_connections pack/cluster_feasibility_filter.c /^static void discover_all_forced_connections(INOUTP t_pb_graph_node *pb_graph_node) {$/;" f file: +discover_pattern_names_in_pb_graph_node pack/prepack.c /^static void discover_pattern_names_in_pb_graph_node($/;" f file: +disp_type base/graphics.c /^ int disp_type;$/;" m struct:__anon5 file: +display base/graphics.c /^static Display *display;$/;" v file: +display_height base/graphics.c /^static int display_width, display_height; \/* screen size *\/$/;" v file: +display_width base/graphics.c /^static int display_width, display_height; \/* screen size *\/$/;" v file: +displaybuffer base/graphics.c /^void displaybuffer(void) { }$/;" f +displaybuffer base/graphics.c /^void displaybuffer(void) {$/;" f +distr route/rr_graph.c /^ int *distr;$/;" m struct:s_mux_size_distribution file: +doPacking base/vpr_types.h /^ boolean doPacking;$/;" m struct:s_packer_opts +doPlacement base/vpr_types.h /^ boolean doPlacement;$/;" m struct:s_placer_opts +doRouting base/vpr_types.h /^ boolean doRouting;$/;" m struct:s_router_opts +do_clustering pack/cluster.c /^void do_clustering(const t_arch *arch, t_pack_molecule *molecule_head,$/;" f +do_constant_net_delay_timing_analysis timing/path_delay.c /^void do_constant_net_delay_timing_analysis(t_timing_inf timing_inf,$/;" f +do_fpga_spice base/vpr_types.h /^ boolean do_fpga_spice;$/;" m struct:s_fpga_spice_opts +do_lut_rebalancing timing/path_delay.c /^static void do_lut_rebalancing() {$/;" f file: +do_path_counting timing/path_delay.c /^static void do_path_counting(float criticality_denom) {$/;" f file: +do_power base/vpr_types.h /^ boolean do_power; \/* Perform power estimation? *\/$/;" m struct:s_power_opts +do_quicksort_float_index fpga_spice/quicksort.c /^void do_quicksort_float_index(int len, $/;" f +do_spice base/vpr_types.h /^ boolean do_spice;$/;" m struct:s_spice_opts +do_timing_analysis timing/path_delay.c /^void do_timing_analysis(t_slack * slacks, boolean is_prepacked, boolean do_lut_input_balancing, boolean is_final_analysis) {$/;" f +do_timing_analysis_for_constraint timing/path_delay.c /^static float do_timing_analysis_for_constraint(int source_clock_domain, int sink_clock_domain, $/;" f file: +domain_constraint base/vpr_types.h /^ float ** domain_constraint; \/* [0..num_constrained_clocks - 1 (source)][0..num_constrained_clocks - 1 (destination)] *\/$/;" m struct:s_timing_constraints +done_callibration power/PowerSpicedComponent.h /^ bool done_callibration;$/;" m class:PowerCallibInputs +done_callibration power/PowerSpicedComponent.h /^ bool done_callibration;$/;" m class:PowerSpicedComponent +dptr ../../libarchfpga/fpga_spice_include/linkedlist.h /^ void* dptr;$/;" m struct:s_llist +draw_chanx_to_chanx_edge base/draw.c /^static void draw_chanx_to_chanx_edge(int from_node, int from_track, int to_node,$/;" f file: +draw_chanx_to_chany_edge base/draw.c /^static void draw_chanx_to_chany_edge(int chanx_node, int chanx_track,$/;" f file: +draw_chany_to_chany_edge base/draw.c /^static void draw_chany_to_chany_edge(int from_node, int from_track, int to_node,$/;" f file: +draw_congestion base/draw.c /^static void draw_congestion(void) {$/;" f file: +draw_message base/graphics.c /^draw_message (void) $/;" f +draw_message base/graphics.c /^void draw_message (void) { }$/;" f +draw_pin_to_chan_edge base/draw.c /^static void draw_pin_to_chan_edge(int pin_node, int chan_node) {$/;" f file: +draw_pin_to_pin base/draw.c /^static void draw_pin_to_pin(int opin_node, int ipin_node) {$/;" f file: +draw_route_type base/draw.c /^static enum e_route_type draw_route_type;$/;" v typeref:enum:e_route_type file: +draw_rr base/draw.c /^void draw_rr(void) {$/;" f +draw_rr_chanx base/draw.c /^static void draw_rr_chanx(int inode, int itrack) {$/;" f file: +draw_rr_chany base/draw.c /^static void draw_rr_chany(int inode, int itrack) {$/;" f file: +draw_rr_edges base/draw.c /^static void draw_rr_edges(int inode) {$/;" f file: +draw_rr_pin base/draw.c /^static void draw_rr_pin(int inode, enum color_types color) {$/;" f file: +draw_rr_switch base/draw.c /^static void draw_rr_switch(float from_x, float from_y, float to_x, float to_y,$/;" f file: +draw_rr_toggle base/draw.c /^static enum e_draw_rr_toggle draw_rr_toggle = DRAW_NO_RR; \/* UDSD by AY *\/$/;" v typeref:enum:e_draw_rr_toggle file: +draw_triangle_along_line base/draw.c /^static void draw_triangle_along_line(float xend, float yend, float x1, float x2,$/;" f file: +draw_x base/draw.c /^static void draw_x(float x, float y, float size) {$/;" f file: +drawarc base/graphics.c /^drawarc (float xc, float yc, float rad, float startang, $/;" f +drawarc base/graphics.c /^void drawarc (float xcen, float ycen, float rad, float startang,$/;" f +drawbut base/graphics.c /^static void drawbut (int bnum) $/;" f file: +drawcurve base/graphics.c /^void drawcurve(t_point *points, int npoints) { }$/;" f +drawcurve base/graphics.c /^void drawcurve(t_point *points,$/;" f +drawellipticarc base/graphics.c /^drawellipticarc (float xc, float yc, float radx, float rady, float startang, float angextent) $/;" f +drawellipticarc base/graphics.c /^void drawellipticarc (float xc, float yc, float radx, float rady, float startang, float angextent) { }$/;" f +drawline base/graphics.c /^drawline (float x1, float y1, float x2, float y2) $/;" f +drawline base/graphics.c /^void drawline (float x1, float y1, float x2, float y2) { }$/;" f +drawmenu base/graphics.c /^static void drawmenu(void) $/;" f file: +drawnets base/draw.c /^static void drawnets(void) {$/;" f file: +drawplace base/draw.c /^static void drawplace(void) {$/;" f file: +drawrect base/graphics.c /^drawrect (float x1, float y1, float x2, float y2) $/;" f +drawrect base/graphics.c /^void drawrect (float x1, float y1, float x2, float y2) { }$/;" f +drawroute base/draw.c /^static void drawroute(enum e_draw_net_type draw_net_type) {$/;" f file: +drawscreen base/draw.c /^static void drawscreen() {$/;" f file: +drawscreen_ptr base/graphics.c /^static void (*drawscreen_ptr)(void);$/;" v file: +drawtext base/graphics.c /^drawtext (float xc, float yc, const char *text, float boundx) $/;" f +drawtext base/graphics.c /^void drawtext (float xc, float yc, const char *text, float boundx) { }$/;" f +drawtobuffer base/graphics.c /^void drawtobuffer(void) { }$/;" f +drawtobuffer base/graphics.c /^void drawtobuffer(void) {$/;" f +drawtoscreen base/graphics.c /^void drawtoscreen(void) { }$/;" f +drawtoscreen base/graphics.c /^void drawtoscreen(void) {$/;" f +drive_rr_nodes base/vpr_types.h /^ t_rr_node** drive_rr_nodes;$/;" m struct:s_rr_node +drive_switches base/vpr_types.h /^ int* drive_switches;$/;" m struct:s_rr_node +driver_pb base/verilog_writer.h /^ t_pb *driver_pb;$/;" m struct:found_connectivity +driver_pin ../../libarchfpga/include/physical_types.h /^ int driver_pin;$/;" m struct:s_pb_graph_edge +driver_pin base/verilog_writer.h /^ t_pb_graph_pin *driver_pin;$/;" m struct:found_connectivity +driver_set ../../libarchfpga/include/physical_types.h /^ int driver_set;$/;" m struct:s_pb_graph_edge +driver_switch base/vpr_types.h /^ short driver_switch; \/* Xifan TANG: Switch Segment Pattern Support*\/$/;" m struct:s_rr_node +driver_switch_type power/power.h /^ short driver_switch_type; \/* Switch type that drives this resource *\/$/;" m struct:s_rr_node_power +driver_to_load_delay base/verilog_writer.h /^ float driver_to_load_delay;$/;" m struct:found_connectivity +drivers base/vpr_types.h /^ enum e_drivers drivers; \/* UDSD by AY *\/$/;" m struct:s_rr_node typeref:enum:s_rr_node::e_drivers +drivers base/vpr_types.h /^ enum e_drivers drivers; \/* UDSD by AY *\/$/;" m struct:s_seg_details typeref:enum:s_seg_details::e_drivers +dum_parse base/read_blif.c /^void dum_parse(char *buf) {$/;" f +dummy_type_descriptors place/timing_place_lookup.c /^static t_type_descriptor dummy_type_descriptors[NUM_TYPES_USED];$/;" v file: +dump_conf_bits_to_bitstream_file fpga_spice/fpga_spice_bitstream.c /^void dump_conf_bits_to_bitstream_file(FILE* fp, $/;" f file: +dump_fpga_spice_bitstream fpga_spice/fpga_spice_bitstream.c /^void dump_fpga_spice_bitstream(char* bitstream_file_name, $/;" f +dump_include_user_defined_verilog_netlists syn_verilog/verilog_utils.c /^void dump_include_user_defined_verilog_netlists(FILE* fp,$/;" f +dump_rr_graph route/rr_graph.c /^void dump_rr_graph(INP const char *file_name) {$/;" f +dump_seg_details route/rr_graph2.c /^void dump_seg_details(t_seg_details * seg_details, int nodes_per_chan,$/;" f +dump_structural_verilog ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean dump_structural_verilog;$/;" m struct:s_spice_model +dump_syn_verilog base/vpr_types.h /^ boolean dump_syn_verilog;$/;" m struct:s_syn_verilog_opts +dump_verilog_block syn_verilog/verilog_pbtypes.c /^void dump_verilog_block(FILE* fp,$/;" f +dump_verilog_cmos_mux_config_bus syn_verilog/verilog_utils.c /^void dump_verilog_cmos_mux_config_bus(FILE* fp, t_spice_model* mux_spice_model, $/;" f +dump_verilog_cmos_mux_config_bus_ports syn_verilog/verilog_utils.c /^void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model, $/;" f +dump_verilog_cmos_mux_multilevel_structure syn_verilog/verilog_submodules.c /^void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, $/;" f +dump_verilog_cmos_mux_one_basis_module syn_verilog/verilog_submodules.c /^void dump_verilog_cmos_mux_one_basis_module(FILE* fp, $/;" f +dump_verilog_cmos_mux_one_basis_module_structural syn_verilog/verilog_submodules.c /^void dump_verilog_cmos_mux_one_basis_module_structural(FILE* fp, $/;" f file: +dump_verilog_cmos_mux_onelevel_structure syn_verilog/verilog_submodules.c /^void dump_verilog_cmos_mux_onelevel_structure(FILE* fp, $/;" f +dump_verilog_cmos_mux_submodule syn_verilog/verilog_submodules.c /^void dump_verilog_cmos_mux_submodule(FILE* fp,$/;" f +dump_verilog_cmos_mux_tree_structure syn_verilog/verilog_submodules.c /^void dump_verilog_cmos_mux_tree_structure(FILE* fp, $/;" f +dump_verilog_configuration_circuits syn_verilog/verilog_top_netlist.c /^void dump_verilog_configuration_circuits(FILE* fp) {$/;" f +dump_verilog_configuration_circuits_memory_bank syn_verilog/verilog_top_netlist.c /^void dump_verilog_configuration_circuits_memory_bank(FILE* fp, $/;" f +dump_verilog_configuration_circuits_scan_chains syn_verilog/verilog_top_netlist.c /^void dump_verilog_configuration_circuits_scan_chains(FILE* fp) {$/;" f +dump_verilog_configuration_circuits_standalone_srams syn_verilog/verilog_top_netlist.c /^void dump_verilog_configuration_circuits_standalone_srams(FILE* fp) {$/;" f +dump_verilog_connection_box_interc syn_verilog/verilog_routing.c /^void dump_verilog_connection_box_interc(FILE* fp,$/;" f +dump_verilog_connection_box_mux syn_verilog/verilog_routing.c /^void dump_verilog_connection_box_mux(FILE* fp,$/;" f +dump_verilog_connection_box_short_interc syn_verilog/verilog_routing.c /^void dump_verilog_connection_box_short_interc(FILE* fp,$/;" f +dump_verilog_dangling_des_pb_graph_pin_interc syn_verilog/verilog_pbtypes.c /^void dump_verilog_dangling_des_pb_graph_pin_interc(FILE* fp,$/;" f +dump_verilog_decoder syn_verilog/verilog_decoder.c /^void dump_verilog_decoder(char* submodule_dir) {$/;" f +dump_verilog_defined_channels syn_verilog/verilog_top_netlist.c /^void dump_verilog_defined_channels(FILE* fp,$/;" f +dump_verilog_defined_connection_boxes syn_verilog/verilog_top_netlist.c /^void dump_verilog_defined_connection_boxes(FILE* fp) {$/;" f +dump_verilog_defined_grids syn_verilog/verilog_top_netlist.c /^void dump_verilog_defined_grids(FILE* fp) {$/;" f +dump_verilog_defined_one_channel syn_verilog/verilog_top_netlist.c /^void dump_verilog_defined_one_channel(FILE* fp,$/;" f +dump_verilog_defined_one_connection_box syn_verilog/verilog_top_netlist.c /^void dump_verilog_defined_one_connection_box(FILE* fp,$/;" f +dump_verilog_defined_one_grid syn_verilog/verilog_top_netlist.c /^void dump_verilog_defined_one_grid(FILE* fp,$/;" f file: +dump_verilog_defined_one_switch_box syn_verilog/verilog_top_netlist.c /^void dump_verilog_defined_one_switch_box(FILE* fp,$/;" f +dump_verilog_defined_switch_boxes syn_verilog/verilog_top_netlist.c /^void dump_verilog_defined_switch_boxes(FILE* fp) {$/;" f +dump_verilog_file_header syn_verilog/verilog_utils.c /^void dump_verilog_file_header(FILE* fp,$/;" f +dump_verilog_generic_port syn_verilog/verilog_utils.c /^void dump_verilog_generic_port(FILE* fp, $/;" f +dump_verilog_global_ports syn_verilog/verilog_utils.c /^int dump_verilog_global_ports(FILE* fp, t_llist* head,$/;" f +dump_verilog_grid_block_subckt_pins syn_verilog/verilog_pbtypes.c /^void dump_verilog_grid_block_subckt_pins(FILE* fp,$/;" f +dump_verilog_grid_blocks syn_verilog/verilog_pbtypes.c /^void dump_verilog_grid_blocks(FILE* fp,$/;" f +dump_verilog_grid_common_port syn_verilog/verilog_utils.c /^void dump_verilog_grid_common_port(FILE* fp, t_spice_model* cur_verilog_model,$/;" f +dump_verilog_grid_pins syn_verilog/verilog_pbtypes.c /^void dump_verilog_grid_pins(FILE* fp,$/;" f +dump_verilog_grid_side_pin_with_given_index syn_verilog/verilog_routing.c /^void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, $/;" f +dump_verilog_grid_side_pins syn_verilog/verilog_routing.c /^void dump_verilog_grid_side_pins(FILE* fp,$/;" f +dump_verilog_hard_wired_gnd syn_verilog/verilog_submodules.c /^void dump_verilog_hard_wired_gnd(FILE* fp, $/;" f +dump_verilog_hard_wired_vdd syn_verilog/verilog_submodules.c /^void dump_verilog_hard_wired_vdd(FILE* fp, $/;" f +dump_verilog_idle_block syn_verilog/verilog_pbtypes.c /^void dump_verilog_idle_block(FILE* fp,$/;" f +dump_verilog_idle_pb_graph_node_rec syn_verilog/verilog_pbtypes.c /^void dump_verilog_idle_pb_graph_node_rec(FILE* fp,$/;" f +dump_verilog_input_blif_testbench syn_verilog/verilog_top_netlist.c /^void dump_verilog_input_blif_testbench(char* circuit_name,$/;" f +dump_verilog_input_blif_testbench_call_top_module syn_verilog/verilog_top_netlist.c /^void dump_verilog_input_blif_testbench_call_top_module(FILE* fp, $/;" f file: +dump_verilog_input_blif_testbench_ports syn_verilog/verilog_top_netlist.c /^void dump_verilog_input_blif_testbench_ports(FILE* fp,$/;" f file: +dump_verilog_input_blif_testbench_stimuli syn_verilog/verilog_top_netlist.c /^void dump_verilog_input_blif_testbench_stimuli(FILE* fp,$/;" f file: +dump_verilog_invbuf_module syn_verilog/verilog_submodules.c /^void dump_verilog_invbuf_module(FILE* fp,$/;" f +dump_verilog_io_grid_block_subckt_pins syn_verilog/verilog_pbtypes.c /^void dump_verilog_io_grid_block_subckt_pins(FILE* fp,$/;" f +dump_verilog_io_grid_pins syn_verilog/verilog_pbtypes.c /^void dump_verilog_io_grid_pins(FILE* fp,$/;" f +dump_verilog_logic_blocks syn_verilog/verilog_pbtypes.c /^void dump_verilog_logic_blocks(char* subckt_dir,$/;" f +dump_verilog_mem_config_bus syn_verilog/verilog_utils.c /^void dump_verilog_mem_config_bus(FILE* fp, t_spice_model* mem_spice_model, $/;" f +dump_verilog_mux_basis_module syn_verilog/verilog_submodules.c /^void dump_verilog_mux_basis_module(FILE* fp, $/;" f +dump_verilog_mux_config_bus syn_verilog/verilog_utils.c /^void dump_verilog_mux_config_bus(FILE* fp, t_spice_model* mux_spice_model, $/;" f +dump_verilog_mux_config_bus_ports syn_verilog/verilog_utils.c /^void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model, $/;" f +dump_verilog_mux_module syn_verilog/verilog_submodules.c /^void dump_verilog_mux_module(FILE* fp, $/;" f +dump_verilog_mux_one_basis_module syn_verilog/verilog_submodules.c /^void dump_verilog_mux_one_basis_module(FILE* fp, $/;" f +dump_verilog_mux_sram_one_outport syn_verilog/verilog_utils.c /^void dump_verilog_mux_sram_one_outport(FILE* fp, $/;" f +dump_verilog_mux_sram_submodule syn_verilog/verilog_utils.c /^void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,$/;" f +dump_verilog_passgate_module syn_verilog/verilog_submodules.c /^void dump_verilog_passgate_module(FILE* fp,$/;" f +dump_verilog_pb_graph_interc syn_verilog/verilog_pbtypes.c /^void dump_verilog_pb_graph_interc(FILE* fp, $/;" f +dump_verilog_pb_graph_node_rec syn_verilog/verilog_pbtypes.c /^void dump_verilog_pb_graph_node_rec(FILE* fp, $/;" f +dump_verilog_pb_graph_pin_interc syn_verilog/verilog_pbtypes.c /^void dump_verilog_pb_graph_pin_interc(FILE* fp,$/;" f +dump_verilog_pb_graph_primitive_node syn_verilog/verilog_pbtypes.c /^void dump_verilog_pb_graph_primitive_node(FILE* fp,$/;" f +dump_verilog_pb_primitive_ff syn_verilog/verilog_primitives.c /^void dump_verilog_pb_primitive_ff(FILE* fp,$/;" f +dump_verilog_pb_primitive_hardlogic syn_verilog/verilog_primitives.c /^void dump_verilog_pb_primitive_hardlogic(FILE* fp,$/;" f +dump_verilog_pb_primitive_io syn_verilog/verilog_primitives.c /^void dump_verilog_pb_primitive_io(FILE* fp,$/;" f +dump_verilog_pb_primitive_lut syn_verilog/verilog_lut.c /^void dump_verilog_pb_primitive_lut(FILE* fp,$/;" f +dump_verilog_pb_primitive_verilog_model syn_verilog/verilog_pbtypes.c /^void dump_verilog_pb_primitive_verilog_model(FILE* fp,$/;" f +dump_verilog_pb_type_bus_ports syn_verilog/verilog_pbtypes.c /^void dump_verilog_pb_type_bus_ports(FILE* fp,$/;" f +dump_verilog_pb_type_ports syn_verilog/verilog_pbtypes.c /^void dump_verilog_pb_type_ports(FILE* fp,$/;" f +dump_verilog_phy_pb_graph_node_rec syn_verilog/verilog_pbtypes.c /^void dump_verilog_phy_pb_graph_node_rec(FILE* fp,$/;" f +dump_verilog_physical_block syn_verilog/verilog_pbtypes.c /^void dump_verilog_physical_block(FILE* fp,$/;" f +dump_verilog_physical_grid_blocks syn_verilog/verilog_pbtypes.c /^void dump_verilog_physical_grid_blocks(FILE* fp,$/;" f +dump_verilog_reserved_sram_one_port syn_verilog/verilog_utils.c /^void dump_verilog_reserved_sram_one_port(FILE* fp, $/;" f +dump_verilog_reserved_sram_ports syn_verilog/verilog_utils.c /^void dump_verilog_reserved_sram_ports(FILE* fp, $/;" f +dump_verilog_routing_chan_subckt syn_verilog/verilog_routing.c /^void dump_verilog_routing_chan_subckt(FILE* fp,$/;" f +dump_verilog_routing_connection_box_subckt syn_verilog/verilog_routing.c /^void dump_verilog_routing_connection_box_subckt(FILE* fp, t_cb* cur_cb_info,$/;" f +dump_verilog_routing_resources syn_verilog/verilog_routing.c /^void dump_verilog_routing_resources(char* subckt_dir,$/;" f +dump_verilog_routing_switch_box_subckt syn_verilog/verilog_routing.c /^void dump_verilog_routing_switch_box_subckt(FILE* fp, t_sb* cur_sb_info, $/;" f +dump_verilog_rram_mux_multilevel_structure syn_verilog/verilog_submodules.c /^void dump_verilog_rram_mux_multilevel_structure(FILE* fp, $/;" f +dump_verilog_rram_mux_one_basis_module syn_verilog/verilog_submodules.c /^void dump_verilog_rram_mux_one_basis_module(FILE* fp, $/;" f +dump_verilog_rram_mux_one_basis_module_structural syn_verilog/verilog_submodules.c /^void dump_verilog_rram_mux_one_basis_module_structural(FILE* fp, $/;" f file: +dump_verilog_rram_mux_onelevel_structure syn_verilog/verilog_submodules.c /^void dump_verilog_rram_mux_onelevel_structure(FILE* fp, $/;" f +dump_verilog_rram_mux_submodule syn_verilog/verilog_submodules.c /^void dump_verilog_rram_mux_submodule(FILE* fp,$/;" f +dump_verilog_rram_mux_tree_structure syn_verilog/verilog_submodules.c /^void dump_verilog_rram_mux_tree_structure(FILE* fp, $/;" f +dump_verilog_scff_config_bus syn_verilog/verilog_utils.c /^void dump_verilog_scff_config_bus(FILE* fp,$/;" f +dump_verilog_sram_config_bus_internal_wires syn_verilog/verilog_utils.c /^void dump_verilog_sram_config_bus_internal_wires(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, $/;" f +dump_verilog_sram_one_outport syn_verilog/verilog_utils.c /^void dump_verilog_sram_one_outport(FILE* fp, $/;" f +dump_verilog_sram_one_port syn_verilog/verilog_utils.c /^void dump_verilog_sram_one_port(FILE* fp, $/;" f +dump_verilog_sram_outports syn_verilog/verilog_utils.c /^void dump_verilog_sram_outports(FILE* fp, $/;" f +dump_verilog_sram_ports syn_verilog/verilog_utils.c /^void dump_verilog_sram_ports(FILE* fp, $/;" f +dump_verilog_sram_submodule syn_verilog/verilog_utils.c /^void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,$/;" f +dump_verilog_submodule_essentials syn_verilog/verilog_submodules.c /^void dump_verilog_submodule_essentials(char* submodule_dir,$/;" f +dump_verilog_submodule_luts syn_verilog/verilog_submodules.c /^void dump_verilog_submodule_luts(char* submodule_dir,$/;" f +dump_verilog_submodule_muxes syn_verilog/verilog_submodules.c /^void dump_verilog_submodule_muxes(char* submodule_dir,$/;" f +dump_verilog_submodule_one_lut syn_verilog/verilog_submodules.c /^void dump_verilog_submodule_one_lut(FILE* fp, $/;" f +dump_verilog_submodule_wires syn_verilog/verilog_submodules.c /^void dump_verilog_submodule_wires(char* subckt_dir,$/;" f +dump_verilog_submodules syn_verilog/verilog_submodules.c /^void dump_verilog_submodules(char* submodule_dir, $/;" f +dump_verilog_switch_box_chan_port syn_verilog/verilog_routing.c /^void dump_verilog_switch_box_chan_port(FILE* fp,$/;" f +dump_verilog_switch_box_interc syn_verilog/verilog_routing.c /^void dump_verilog_switch_box_interc(FILE* fp, $/;" f +dump_verilog_switch_box_mux syn_verilog/verilog_routing.c /^void dump_verilog_switch_box_mux(FILE* fp, $/;" f +dump_verilog_switch_box_short_interc syn_verilog/verilog_routing.c /^void dump_verilog_switch_box_short_interc(FILE* fp, $/;" f +dump_verilog_top_module_ports syn_verilog/verilog_top_netlist.c /^void dump_verilog_top_module_ports(FILE* fp,$/;" f file: +dump_verilog_top_netlist syn_verilog/verilog_top_netlist.c /^void dump_verilog_top_netlist(char* circuit_name,$/;" f +dump_verilog_top_netlist_internal_wires syn_verilog/verilog_top_netlist.c /^void dump_verilog_top_netlist_internal_wires(FILE* fp) {$/;" f file: +dump_verilog_top_netlist_memory_bank_internal_wires syn_verilog/verilog_top_netlist.c /^void dump_verilog_top_netlist_memory_bank_internal_wires(FILE* fp) {$/;" f file: +dump_verilog_top_netlist_memory_bank_ports syn_verilog/verilog_top_netlist.c /^void dump_verilog_top_netlist_memory_bank_ports(FILE* fp, $/;" f file: +dump_verilog_top_netlist_ports syn_verilog/verilog_top_netlist.c /^void dump_verilog_top_netlist_ports(FILE* fp,$/;" f file: +dump_verilog_top_netlist_scan_chain_internal_wires syn_verilog/verilog_top_netlist.c /^void dump_verilog_top_netlist_scan_chain_internal_wires(FILE* fp) {$/;" f file: +dump_verilog_top_netlist_scan_chain_ports syn_verilog/verilog_top_netlist.c /^void dump_verilog_top_netlist_scan_chain_ports(FILE* fp,$/;" f file: +dump_verilog_top_testbench syn_verilog/verilog_top_netlist.c /^void dump_verilog_top_testbench(char* circuit_name,$/;" f +dump_verilog_top_testbench_call_top_module syn_verilog/verilog_top_netlist.c /^void dump_verilog_top_testbench_call_top_module(FILE* fp,$/;" f file: +dump_verilog_top_testbench_conf_bits_serial syn_verilog/verilog_top_netlist.c /^void dump_verilog_top_testbench_conf_bits_serial(FILE* fp, $/;" f file: +dump_verilog_top_testbench_find_num_config_clock_cycles syn_verilog/verilog_top_netlist.c /^int dump_verilog_top_testbench_find_num_config_clock_cycles(t_llist* head) {$/;" f +dump_verilog_top_testbench_global_ports syn_verilog/verilog_top_netlist.c /^void dump_verilog_top_testbench_global_ports(FILE* fp, t_llist* head,$/;" f file: +dump_verilog_top_testbench_global_ports_stimuli syn_verilog/verilog_top_netlist.c /^void dump_verilog_top_testbench_global_ports_stimuli(FILE* fp, t_llist* head) {$/;" f file: +dump_verilog_top_testbench_memory_bank_conf_bits_serial syn_verilog/verilog_top_netlist.c /^void dump_verilog_top_testbench_memory_bank_conf_bits_serial(FILE* fp, $/;" f file: +dump_verilog_top_testbench_one_conf_bit_serial syn_verilog/verilog_top_netlist.c /^void dump_verilog_top_testbench_one_conf_bit_serial(FILE* fp, $/;" f file: +dump_verilog_top_testbench_ports syn_verilog/verilog_top_netlist.c /^void dump_verilog_top_testbench_ports(FILE* fp,$/;" f file: +dump_verilog_top_testbench_rram_memory_bank_conf_bits_serial syn_verilog/verilog_top_netlist.c /^void dump_verilog_top_testbench_rram_memory_bank_conf_bits_serial(FILE* fp, $/;" f file: +dump_verilog_top_testbench_scan_chain_conf_bits_serial syn_verilog/verilog_top_netlist.c /^void dump_verilog_top_testbench_scan_chain_conf_bits_serial(FILE* fp, $/;" f file: +dump_verilog_top_testbench_sram_memory_bank_conf_bits_serial syn_verilog/verilog_top_netlist.c /^void dump_verilog_top_testbench_sram_memory_bank_conf_bits_serial(FILE* fp, $/;" f file: +dump_verilog_top_testbench_stimuli syn_verilog/verilog_top_netlist.c /^void dump_verilog_top_testbench_stimuli(FILE* fp,$/;" f +dump_verilog_top_testbench_stimuli_serial_version syn_verilog/verilog_top_netlist.c /^void dump_verilog_top_testbench_stimuli_serial_version(FILE* fp,$/;" f file: +dump_verilog_top_testbench_stimuli_serial_version_tasks syn_verilog/verilog_top_netlist.c /^void dump_verilog_top_testbench_stimuli_serial_version_tasks(FILE* fp) {$/;" f file: +dump_verilog_top_testbench_stimuli_serial_version_tasks_memory_bank syn_verilog/verilog_top_netlist.c /^void dump_verilog_top_testbench_stimuli_serial_version_tasks_memory_bank(FILE* fp) {$/;" f file: +dump_verilog_top_testbench_stimuli_serial_version_tasks_scan_chain syn_verilog/verilog_top_netlist.c /^void dump_verilog_top_testbench_stimuli_serial_version_tasks_scan_chain(FILE* fp) {$/;" f file: +dump_verilog_top_testbench_wire_one_global_port_stimuli syn_verilog/verilog_top_netlist.c /^void dump_verilog_top_testbench_wire_one_global_port_stimuli(FILE* fp, t_spice_model_port* cur_global_port, $/;" f file: +dump_verilog_wire_module syn_verilog/verilog_submodules.c /^void dump_verilog_wire_module(FILE* fp,$/;" f +dumped_num_conf_bits fpga_spice/fpga_spice_bitstream.c /^static int dumped_num_conf_bits = 0;$/;" v file: +dynamic ../../libarchfpga/include/physical_types.h /^ float dynamic;$/;" m struct:s_power_usage +e ../../libarchfpga/include/ezxml.h /^ char *e; \/* end of work area *\/$/;" m struct:ezxml_root +e_Fc_type ../../libarchfpga/include/physical_types.h /^enum e_Fc_type {$/;" g +e_OptionArgToken base/OptionTokens.h /^enum e_OptionArgToken {$/;" g +e_OptionBaseToken base/OptionTokens.h /^enum e_OptionBaseToken {$/;" g +e_base_cost_type base/vpr_types.h /^enum e_base_cost_type {$/;" g +e_block_pack_status base/vpr_types.h /^enum e_block_pack_status {$/;" g +e_cluster_seed base/vpr_types.h /^enum e_cluster_seed {$/;" g +e_cost_indices base/vpr_types.h /^enum e_cost_indices {$/;" g +e_detailed_routing_stages pack/cluster.c /^enum e_detailed_routing_stages {$/;" g file: +e_dir_err fpga_spice/fpga_spice_utils.c /^enum e_dir_err {$/;" g file: +e_direction base/vpr_types.h /^enum e_direction {$/;" g +e_directionality ../../libarchfpga/include/physical_types.h /^enum e_directionality {$/;" g +e_draw_mode base/graphics.h /^enum e_draw_mode {DRAW_NORMAL = 0, DRAW_XOR};$/;" g +e_draw_net_type base/draw.c /^enum e_draw_net_type {$/;" g file: +e_draw_rr_toggle base/draw.c /^enum e_draw_rr_toggle {$/;" g file: +e_drivers base/vpr_types.h /^enum e_drivers {$/;" g +e_dump_verilog_port_type syn_verilog/verilog_global.h /^enum e_dump_verilog_port_type {$/;" g +e_echo_files base/ReadOptions.h /^enum e_echo_files {$/;" g +e_edge_dir base/draw.c /^enum e_edge_dir {$/;" g file: +e_feasibility pack/cluster.c /^enum e_feasibility {$/;" g file: +e_ff_trigger_type spice/spice_primitives.c /^enum e_ff_trigger_type {$/;" g file: +e_ff_trigger_type syn_verilog/verilog_primitives.c /^enum e_ff_trigger_type {$/;" g file: +e_gain_type pack/cluster.c /^enum e_gain_type {$/;" g file: +e_gain_update pack/cluster.c /^enum e_gain_update {$/;" g file: +e_graph_type route/rr_graph.h /^enum e_graph_type {$/;" g +e_grid_loc_type ../../libarchfpga/include/physical_types.h /^enum e_grid_loc_type {$/;" g +e_interconnect ../../libarchfpga/include/physical_types.h /^enum e_interconnect {$/;" g +e_measure_type spice/spice_utils.h /^enum e_measure_type {$/;" g +e_net_relation_to_clustered_block pack/cluster.c /^enum e_net_relation_to_clustered_block {$/;" g file: +e_operation base/vpr_types.h /^enum e_operation {$/;" g +e_output_files base/ReadOptions.h /^enum e_output_files {$/;" g +e_pack_pattern_molecule_type base/vpr_types.h /^enum e_pack_pattern_molecule_type {$/;" g +e_packer_algorithm base/vpr_types.h /^enum e_packer_algorithm {$/;" g +e_pad_loc_type base/vpr_types.h /^enum e_pad_loc_type {$/;" g +e_pb_graph_pin_type ../../libarchfpga/include/physical_types.h /^enum e_pb_graph_pin_type {$/;" g +e_pb_type_class ../../libarchfpga/include/physical_types.h /^enum e_pb_type_class {$/;" g +e_pin2pin_interc_type fpga_spice/fpga_spice_globals.h /^enum e_pin2pin_interc_type {$/;" g +e_pin_location_distr ../../libarchfpga/include/physical_types.h /^enum e_pin_location_distr {$/;" g +e_pin_to_pin_annotation_format ../../libarchfpga/include/physical_types.h /^enum e_pin_to_pin_annotation_format {$/;" g +e_pin_to_pin_annotation_type ../../libarchfpga/include/physical_types.h /^enum e_pin_to_pin_annotation_type {$/;" g +e_pin_to_pin_capacitance_annotations ../../libarchfpga/include/physical_types.h /^enum e_pin_to_pin_capacitance_annotations {$/;" g +e_pin_to_pin_delay_annotations ../../libarchfpga/include/physical_types.h /^enum e_pin_to_pin_delay_annotations {$/;" g +e_pin_to_pin_mode_select_annotations ../../libarchfpga/include/physical_types.h /^enum e_pin_to_pin_mode_select_annotations {$/;" g +e_pin_to_pin_pack_pattern_annotations ../../libarchfpga/include/physical_types.h /^enum e_pin_to_pin_pack_pattern_annotations {$/;" g +e_pin_type ../../libarchfpga/include/physical_types.h /^enum e_pin_type {$/;" g +e_place_algorithm base/vpr_types.h /^enum e_place_algorithm {$/;" g +e_power_breakdown_entry_type power/power.c /^} e_power_breakdown_entry_type;$/;" t typeref:enum:__anon8 file: +e_power_buffer_type ../../libarchfpga/include/physical_types.h /^} e_power_buffer_type;$/;" t typeref:enum:__anon21 +e_power_callib_component power/power_callibrate.h /^} e_power_callib_component;$/;" t typeref:enum:__anon12 +e_power_component_type power/power_components.h /^} e_power_component_type;$/;" t typeref:enum:__anon13 +e_power_estimation_method ../../libarchfpga/include/physical_types.h /^typedef enum e_power_estimation_method_ e_power_estimation_method;$/;" t typeref:enum:e_power_estimation_method_ +e_power_estimation_method_ ../../libarchfpga/include/physical_types.h /^enum e_power_estimation_method_ {$/;" g +e_power_log_type power/power.h /^} e_power_log_type;$/;" t typeref:enum:__anon10 +e_power_ret_code power/power.h /^} e_power_ret_code;$/;" t typeref:enum:__anon9 +e_power_wire_type ../../libarchfpga/include/physical_types.h /^} e_power_wire_type;$/;" t typeref:enum:__anon20 +e_removal_policy pack/cluster.c /^enum e_removal_policy {$/;" g file: +e_route_type base/vpr_types.h /^enum e_route_type {$/;" g +e_router_algorithm base/vpr_types.h /^enum e_router_algorithm {$/;" g +e_rr_type base/vpr_types.h /^typedef enum e_rr_type {$/;" g +e_side ../../libarchfpga/include/physical_types.h /^enum e_side {$/;" g +e_spice_accuracy_type ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_spice_accuracy_type {$/;" g +e_spice_model_buffer_type ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_spice_model_buffer_type {$/;" g +e_spice_model_design_tech ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_spice_model_design_tech {$/;" g +e_spice_model_pass_gate_logic_type ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_spice_model_pass_gate_logic_type {$/;" g +e_spice_model_port_type ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_spice_model_port_type {$/;" g +e_spice_model_structure ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_spice_model_structure {$/;" g +e_spice_model_type ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_spice_model_type {$/;" g +e_spice_mux_tb_type spice/spice_mux_testbench.h /^enum e_spice_mux_tb_type {$/;" g +e_spice_tech_lib_type ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_spice_tech_lib_type {$/;" g +e_spice_trans_type ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_spice_trans_type {$/;" g +e_sram_orgz ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_sram_orgz {$/;" g +e_stat ../../libarchfpga/include/physical_types.h /^enum e_stat {$/;" g +e_switch_block_type ../../libarchfpga/include/physical_types.h /^enum e_switch_block_type {$/;" g +e_swseg_pattern_type ../../libarchfpga/include/physical_types.h /^enum e_swseg_pattern_type {$/;" g +e_tech_comp ../../libarchfpga/include/arch_types_mrfpga.h /^enum e_tech_comp { $/;" g +e_tnode_type base/vpr_types.h /^} e_tnode_type;$/;" t typeref:enum:__anon7 +e_token_type util/token.h /^enum e_token_type {$/;" g +e_tx_type power/power.h /^} e_tx_type;$/;" t typeref:enum:__anon11 +e_wire_model_type ../../libarchfpga/fpga_spice_include/spice_types.h /^enum e_wire_model_type {$/;" g +echoFileEnabled base/ReadOptions.c /^static boolean *echoFileEnabled = NULL;$/;" v file: +echoFileNames base/ReadOptions.c /^static char **echoFileNames = NULL;$/;" v file: +echo_input base/read_blif.c /^void echo_input(char *blif_file, char *echo_file, t_model *library_models) {$/;" f +echo_pb_graph pack/pb_type_graph.c /^void echo_pb_graph(char * filename) {$/;" f +echo_pb_pins pack/pb_type_graph.c /^static void echo_pb_pins(INP t_pb_graph_pin **pb_graph_pins, INP int num_ports,$/;" f file: +echo_pb_rec pack/pb_type_graph.c /^static void echo_pb_rec(const INP t_pb_graph_node *pb_graph_node, INP int level,$/;" f file: +edge route/rr_graph_util.h /^ int edge;$/;" m struct:s_linked_edge +edges base/vpr_types.h /^ int *edges;$/;" m struct:s_rr_node +edges_head pack/pb_type_graph.c /^static struct s_linked_vptr *edges_head;$/;" v typeref:struct:s_linked_vptr file: +emit timing/slre.c /^static void emit(struct slre *r, int code) {$/;" f file: +empty_heap route/route_common.c /^void empty_heap(void) {$/;" f +enable_or_disable_button base/graphics.c /^void enable_or_disable_button (int ibutton, bool enabled) {$/;" f +enable_or_disable_button base/graphics.c /^void enable_or_disable_button(int ibutton, bool enabled) { }$/;" f +enable_timing_computations base/vpr_types.h /^ boolean enable_timing_computations;$/;" m struct:s_placer_opts +enabled base/graphics.c /^ bool enabled;$/;" m struct:__anon4 file: +encode_decoder_addr fpga_spice/fpga_spice_bitstream.c /^void encode_decoder_addr(int input,$/;" f +endlines base/read_blif.c /^static int ilines, olines, model_lines, endlines;$/;" v file: +energy_per_toggle ../../libarchfpga/include/physical_types.h /^ float energy_per_toggle;$/;" m struct:s_port_power +ent ../../libarchfpga/include/ezxml.h /^ char **ent; \/* general entities (ampersand sequences) *\/$/;" m struct:ezxml_root +entries power/PowerSpicedComponent.h /^ std::vector entries;$/;" m class:PowerSpicedComponent +entries power/PowerSpicedComponent.h /^ std::vector entries;$/;" m class:PowerCallibInputs +equivalent ../../libarchfpga/include/physical_types.h /^ boolean equivalent;$/;" m struct:s_port +err ../../libarchfpga/include/ezxml.h /^ char err[EZXML_ERRL]; \/* error string *\/$/;" m struct:ezxml_root +error_no_match timing/slre.c /^static const char *error_no_match = "No match";$/;" v file: +error_string timing/slre.c /^ const char *error_string; \/\/ Error string$/;" m struct:slre file: +essentials_verilog_file_name syn_verilog/verilog_global.c /^char* essentials_verilog_file_name = "inv_buf_passgate.v";$/;" v +esti_distance_num_seg_delay clb_pin_remap/post_place_timing.c /^float esti_distance_num_seg_delay(int distance,$/;" f +esti_one_segment_net_delay clb_pin_remap/post_place_timing.c /^float esti_one_segment_net_delay(int distance, t_segment_inf segment_inf) {$/;" f +esti_pin2pin_one_net_delay clb_pin_remap/post_place_timing.c /^float esti_pin2pin_one_net_delay(t_block src_blk,$/;" f +esti_pin_chan_coordinate clb_pin_remap/clb_pin_remap_util.c /^void esti_pin_chan_coordinate(int* pin_x, int* pin_y,$/;" f +estimate_post_place_one_net_sink_delay clb_pin_remap/post_place_timing.c /^float estimate_post_place_one_net_sink_delay(int net_index, $/;" f +estimation_method ../../libarchfpga/include/physical_types.h /^ e_power_estimation_method estimation_method;$/;" m struct:s_pb_type_power +event_loop base/graphics.c /^event_loop (void (*act_on_mousebutton)(float x, float y), $/;" f +event_loop base/graphics.c /^void event_loop (void (*act_on_mousebutton) (float x, float y),$/;" f +exact timing/slre.c /^static void exact(struct slre *r, const char **re) {$/;" f file: +exact_one_char timing/slre.c /^static void exact_one_char(struct slre *r, int ch) {$/;" f file: +exist ../../libarchfpga/fpga_spice_include/spice_types.h /^ int exist;$/;" m struct:s_spice_model_buffer +exists_free_primitive_for_logical_block pack/cluster_placement.c /^boolean exists_free_primitive_for_logical_block($/;" f +exit_crit place/place.c /^static int exit_crit(float t, float cost,$/;" f file: +exit_t base/vpr_types.h /^ float exit_t;$/;" m struct:s_annealing_sched +expand_forced_pack_molecule_placement pack/cluster_placement.c /^static boolean expand_forced_pack_molecule_placement($/;" f file: +expand_pack_molecule_pin_edge pack/cluster_placement.c /^static t_pb_graph_pin *expand_pack_molecule_pin_edge(INP int pattern_id,$/;" f file: +expand_pb_graph_node_and_load_output_to_input_connections pack/cluster_feasibility_filter.c /^static void expand_pb_graph_node_and_load_output_to_input_connections($/;" f file: +expand_pb_graph_node_and_load_pin_class_by_depth pack/cluster_feasibility_filter.c /^static void expand_pb_graph_node_and_load_pin_class_by_depth($/;" f file: +expand_routing_trace base/vpr_api.c /^static t_trace *expand_routing_trace(t_trace *trace, int ivpack_net) {$/;" f file: +expected_lowest_cost_primitive base/vpr_types.h /^ t_pb_graph_node *expected_lowest_cost_primitive; \/* predicted ideal primitive to use for this logical block *\/$/;" m struct:s_logical_block +ext_clock_rr_node_index pack/cluster_legality.c /^ ext_clock_rr_node_index, max_ext_index;$/;" v file: +ext_input_rr_node_index pack/cluster_legality.c /^static int ext_input_rr_node_index, ext_output_rr_node_index,$/;" v file: +ext_output_rr_node_index pack/cluster_legality.c /^static int ext_input_rr_node_index, ext_output_rr_node_index,$/;" v file: +ezxml ../../libarchfpga/include/ezxml.h /^struct ezxml {$/;" s +ezxml_add_child ../../libarchfpga/ezxml.c /^ezxml_t ezxml_add_child(ezxml_t xml, char *name, size_t off) {$/;" f +ezxml_add_child_d ../../libarchfpga/include/ezxml.h 149;" d +ezxml_ampencode ../../libarchfpga/ezxml.c /^ezxml_ampencode(const char *s, size_t len, char **dst, size_t * dlen,$/;" f file: +ezxml_attr ../../libarchfpga/ezxml.c /^ezxml_attr(ezxml_t xml, const char *attr) {$/;" f +ezxml_char_content ../../libarchfpga/ezxml.c /^static void ezxml_char_content(ezxml_root_t root, char *s,$/;" f file: +ezxml_child ../../libarchfpga/ezxml.c /^ezxml_t ezxml_child(ezxml_t xml, const char *name) {$/;" f +ezxml_close_tag ../../libarchfpga/ezxml.c /^static ezxml_t ezxml_close_tag(ezxml_root_t root, char *name, char *s) {$/;" f file: +ezxml_cut ../../libarchfpga/ezxml.c /^ezxml_t ezxml_cut(ezxml_t xml) {$/;" f +ezxml_decode ../../libarchfpga/ezxml.c /^ezxml_decode(char *s, char **ent, char t) {$/;" f file: +ezxml_ent_ok ../../libarchfpga/ezxml.c /^static int ezxml_ent_ok(char *name, char *s, char **ent) {$/;" f file: +ezxml_err ../../libarchfpga/ezxml.c /^static ezxml_t ezxml_err(ezxml_root_t root, char *s, const char *err, ...) {$/;" f file: +ezxml_error ../../libarchfpga/ezxml.c /^ezxml_error(ezxml_t xml) {$/;" f +ezxml_free ../../libarchfpga/ezxml.c /^void ezxml_free(ezxml_t xml) {$/;" f +ezxml_free_attr ../../libarchfpga/ezxml.c /^static void ezxml_free_attr(char **attr) {$/;" f file: +ezxml_get ../../libarchfpga/ezxml.c /^ezxml_t ezxml_get(ezxml_t xml, ...) {$/;" f +ezxml_idx ../../libarchfpga/ezxml.c /^ezxml_t ezxml_idx(ezxml_t xml, int idx) {$/;" f +ezxml_insert ../../libarchfpga/ezxml.c /^ezxml_t ezxml_insert(ezxml_t xml, ezxml_t dest, size_t off) {$/;" f +ezxml_internal_dtd ../../libarchfpga/ezxml.c /^static short ezxml_internal_dtd(ezxml_root_t root, char *s,$/;" f file: +ezxml_move ../../libarchfpga/include/ezxml.h 178;" d +ezxml_name ../../libarchfpga/include/ezxml.h 108;" d +ezxml_new ../../libarchfpga/ezxml.c /^ezxml_t ezxml_new(char *name) {$/;" f +ezxml_new_d ../../libarchfpga/include/ezxml.h 142;" d +ezxml_next ../../libarchfpga/include/ezxml.h 101;" d +ezxml_open_tag ../../libarchfpga/ezxml.c /^static void ezxml_open_tag(ezxml_root_t root, int line, char *name, char **attr) {$/;" f file: +ezxml_parse_fd ../../libarchfpga/ezxml.c /^ezxml_t ezxml_parse_fd(int fd) {$/;" f +ezxml_parse_file ../../libarchfpga/ezxml.c /^ezxml_t ezxml_parse_file(const char *file) {$/;" f +ezxml_parse_fp ../../libarchfpga/ezxml.c /^ezxml_t ezxml_parse_fp(FILE * fp) {$/;" f +ezxml_parse_str ../../libarchfpga/ezxml.c /^ezxml_t ezxml_parse_str(char *s, size_t len) {$/;" f +ezxml_pi ../../libarchfpga/ezxml.c /^ezxml_pi(ezxml_t xml, const char *target) {$/;" f +ezxml_proc_inst ../../libarchfpga/ezxml.c /^static void ezxml_proc_inst(ezxml_root_t root, char *s, size_t len) {$/;" f file: +ezxml_remove ../../libarchfpga/include/ezxml.h 181;" d +ezxml_root ../../libarchfpga/include/ezxml.h /^struct ezxml_root { \/* additional data for the root tag *\/$/;" s +ezxml_root_t ../../libarchfpga/include/ezxml.h /^typedef struct ezxml_root *ezxml_root_t;$/;" t typeref:struct:ezxml_root +ezxml_set_attr ../../libarchfpga/ezxml.c /^ezxml_t ezxml_set_attr(ezxml_t xml, char *name, char *value) {$/;" f +ezxml_set_attr_d ../../libarchfpga/include/ezxml.h 164;" d +ezxml_set_flag ../../libarchfpga/ezxml.c /^ezxml_t ezxml_set_flag(ezxml_t xml, short flag) {$/;" f +ezxml_set_txt ../../libarchfpga/ezxml.c /^ezxml_t ezxml_set_txt(ezxml_t xml, char *txt) {$/;" f +ezxml_set_txt_d ../../libarchfpga/include/ezxml.h 156;" d +ezxml_str2utf8 ../../libarchfpga/ezxml.c /^ezxml_str2utf8(char **s, size_t * len) {$/;" f file: +ezxml_t ../../libarchfpga/include/ezxml.h /^typedef struct ezxml *ezxml_t;$/;" t typeref:struct:ezxml +ezxml_toxml ../../libarchfpga/ezxml.c /^ezxml_toxml(ezxml_t xml) {$/;" f +ezxml_toxml_r ../../libarchfpga/ezxml.c /^ezxml_toxml_r(ezxml_t xml, char **s, size_t * len, size_t * max, size_t start,$/;" f file: +ezxml_txt ../../libarchfpga/include/ezxml.h 111;" d +ezxml_vget ../../libarchfpga/ezxml.c /^ezxml_t ezxml_vget(ezxml_t xml, va_list ap) {$/;" f +f_blk_pin_from_port_pin util/vpr_utils.c /^static int *** f_blk_pin_from_port_pin = NULL;$/;" v file: +f_direct_type_from_blk_pin place/place_macro.c /^static int ** f_direct_type_from_blk_pin = NULL;$/;" v file: +f_idirect_from_blk_pin place/place_macro.c /^static int ** f_idirect_from_blk_pin = NULL;$/;" v file: +f_imacro_from_iblk place/place_macro.c /^static int * f_imacro_from_iblk = NULL;$/;" v file: +f_net_to_driver_tnode timing/path_delay.c /^static int * f_net_to_driver_tnode; $/;" v file: +f_per_stage ../../libarchfpga/fpga_spice_include/spice_types.h /^ int f_per_stage;$/;" m struct:s_spice_model_buffer +f_port_from_blk_pin util/vpr_utils.c /^static int ** f_port_from_blk_pin = NULL;$/;" v file: +f_port_pin_from_blk_pin util/vpr_utils.c /^static int ** f_port_pin_from_blk_pin = NULL;$/;" v file: +f_timing_stats timing/path_delay.c /^static t_timing_stats * f_timing_stats = NULL; \/* Critical path delay and worst-case slack per constraint. *\/$/;" v file: +factor power/PowerSpicedComponent.h /^ float factor;$/;" m class:PowerCallibSize +falling_edge timing/read_sdc.c /^ float falling_edge;$/;" m struct:s_sdc_clock file: +fan_in ../../libarchfpga/include/physical_types.h /^ int fan_in;$/;" m struct:s_interconnect +fan_in base/vpr_types.h /^ short fan_in;$/;" m struct:s_rr_node +fan_out ../../libarchfpga/include/physical_types.h /^ int fan_out;$/;" m struct:s_interconnect +fanout base/vpr_types.h /^ int fanout;$/;" m struct:s_clock +fast ../../libarchfpga/fpga_spice_include/spice_types.h /^ int fast;$/;" m struct:s_spice_params +fc base/place_and_route.h /^ int fc; \/* at this fc *\/$/;" m struct:s_fmap_cell +fc_constraints base/vpr_types.h /^ t_override_constraint * fc_constraints; \/* [0..num_fc_constraints - 1] *\/$/;" m struct:s_timing_constraints +fc_in base/vpr_types.h /^ int fc_in;$/;" m struct:s_cb +fc_out base/vpr_types.h /^ int fc_out;$/;" m struct:s_sb +fcn base/graphics.c /^ void (*fcn) (void (*drawscreen) (void));$/;" m struct:__anon4 file: +feasible_blocks base/vpr_types.h /^ struct s_pack_molecule **feasible_blocks;$/;" m struct:s_pb_stats typeref:struct:s_pb_stats::s_pack_molecule +feasible_routing route/route_common.c /^boolean feasible_routing(void) {$/;" f +ff_constraints base/vpr_types.h /^ t_override_constraint * ff_constraints; \/* [0..num_ff_constraints - 1] array of such constraints *\/$/;" m struct:s_timing_constraints +file_exists ../../libarchfpga/util.c /^boolean file_exists(const char * filename) {$/;" f +file_line_number ../../libarchfpga/util.c /^int file_line_number; \/* file in line number being parsed *\/$/;" v +file_line_number base/vpr_types.h /^ int file_line_number; \/* line in the SDC file I\/O was constrained on - used for error reporting *\/$/;" m struct:s_io +file_line_number base/vpr_types.h /^ int file_line_number; \/* line in the SDC file clock was constrained on - used for error reporting *\/$/;" m struct:s_override_constraint +fillarc base/graphics.c /^fillarc (float xc, float yc, float rad, float startang, float angextent) {$/;" f +fillarc base/graphics.c /^void fillarc (float xcen, float ycen, float rad, float startang,$/;" f +fillcurve base/graphics.c /^void fillcurve(t_point *points, int npoints) { }$/;" f +fillcurve base/graphics.c /^void fillcurve(t_point *points,$/;" f +fillellipticarc base/graphics.c /^fillellipticarc (float xc, float yc, float radx, float rady, float startang, $/;" f +fillellipticarc base/graphics.c /^void fillellipticarc (float xc, float yc, float radx, float rady, float startang, float angextent) { }$/;" f +fillpoly base/graphics.c /^fillpoly (t_point *points, int npoints) $/;" f +fillpoly base/graphics.c /^void fillpoly (t_point *points, int npoints) { }$/;" f +fillrect base/graphics.c /^fillrect (float x1, float y1, float x2, float y2) $/;" f +fillrect base/graphics.c /^void fillrect (float x1, float y1, float x2, float y2) { }$/;" f +findPortByName ../../libarchfpga/read_xml_arch_file.c /^static t_port * findPortByName(const char * name, t_pb_type * pb_type,$/;" f file: +find_affected_blocks place/place.c /^static int find_affected_blocks(int b_from, int x_to, int y_to, int z_to) {$/;" f file: +find_affected_nets place/place.c /^static int find_affected_nets(int *nets_to_update) {$/;" f file: +find_all_the_macro place/place_macro.c /^static void find_all_the_macro (int * num_of_macro, int * pl_macro_member_blk_num_of_this_blk, $/;" f file: +find_bl_wl_ports_spice_model fpga_spice/fpga_spice_utils.c /^void find_bl_wl_ports_spice_model(t_spice_model* cur_spice_model,$/;" f +find_blb_wlb_ports_spice_model fpga_spice/fpga_spice_utils.c /^void find_blb_wlb_ports_spice_model(t_spice_model* cur_spice_model,$/;" f +find_blk_net_pin_side clb_pin_remap/clb_pin_remap_util.c /^int find_blk_net_pin_side(t_block target_blk,$/;" f +find_blk_net_pin_sides clb_pin_remap/clb_pin_remap_util.c /^void find_blk_net_pin_sides(t_block target_blk,$/;" f +find_blk_net_type_pins clb_pin_remap/clb_pin_remap_util.c /^void find_blk_net_type_pins(int n_blks, t_block* blk,$/;" f +find_cc_constraint timing/read_sdc.c /^static int find_cc_constraint(char * source_clock_name, char * sink_clock_name) {$/;" f file: +find_cf_constraint timing/path_delay.c /^static int find_cf_constraint(char * source_clock_name, char * sink_ff_name) {$/;" f file: +find_clock timing/path_delay.c /^static int find_clock(char * net_name) {$/;" f file: +find_clock_name base/verilog_writer.c /^char *find_clock_name(void)$/;" f +find_connected_primitives_downhill base/verilog_writer.c /^conn_list *find_connected_primitives_downhill(int block_num , t_pb *pb , conn_list*list)$/;" f +find_constrained_clock timing/read_sdc.c /^static int find_constrained_clock(char * ptr) {$/;" f file: +find_drive_rr_nodes_switch_box fpga_spice/fpga_spice_utils.c /^void find_drive_rr_nodes_switch_box(int switch_box_x,$/;" f +find_expansion_edge_of_pattern pack/prepack.c /^static t_pb_graph_edge * find_expansion_edge_of_pattern(INP int pattern_index,$/;" f file: +find_fanin_rr_node pack/output_blif.c /^static int find_fanin_rr_node(t_pb *cur_pb, enum PORTS type, int rr_node_index) {$/;" f file: +find_ff_clock_tnode timing/path_delay.c /^static t_tnode * find_ff_clock_tnode(int inode, boolean is_prepacked) {$/;" f file: +find_grid_mapped_logical_block fpga_spice/fpga_spice_utils.c /^int find_grid_mapped_logical_block(int x, int y,$/;" f +find_index base/verilog_writer.c /^int find_index(char *row,int inputs)\/*returns the index of the 64bit truth table that this temporary truth table row corresponds to*\/$/;" f +find_input timing/path_delay.c /^static int find_input(char * net_name) {$/;" f file: +find_interc_fan_in_des_pb_graph_pin spice/spice_pbtypes.c /^void find_interc_fan_in_des_pb_graph_pin(t_pb_graph_pin* des_pb_graph_pin,$/;" f +find_iopad_spice_model fpga_spice/fpga_spice_utils.c /^t_spice_model* find_iopad_spice_model(int num_spice_model,$/;" f +find_label_of_track route/rr_graph2.c /^static int find_label_of_track(int *wire_mux_on_track, int num_wire_muxes,$/;" f file: +find_length_llist ../../libarchfpga/linkedlist.c /^int find_length_llist(t_llist* head) {$/;" f +find_mosfet_tech_lib fpga_spice/fpga_spice_utils.c /^t_spice_transistor_type* find_mosfet_tech_lib(t_spice_tech_lib tech_lib,$/;" f +find_name_matched_spice_model fpga_spice/fpga_spice_utils.c /^t_spice_model* find_name_matched_spice_model(char* spice_model_name,$/;" f +find_new_root_atom_for_chain pack/prepack.c /^static int find_new_root_atom_for_chain(INP int block_index, INP t_pack_patterns *list_of_pack_pattern) {$/;" f file: +find_number_of_inputs base/verilog_writer.c /^int find_number_of_inputs(t_pb *pb)$/;" f +find_output timing/path_delay.c /^static int find_output(char * net_name) {$/;" f file: +find_parent_pb_type_child_index fpga_spice/fpga_spice_utils.c /^int find_parent_pb_type_child_index(t_pb_type* parent_pb_type,$/;" f +find_path_id_between_pb_rr_nodes fpga_spice/fpga_spice_utils.c /^int find_path_id_between_pb_rr_nodes(t_rr_node* local_rr_graph,$/;" f +find_path_id_prev_rr_node fpga_spice/fpga_spice_utils.c /^int find_path_id_prev_rr_node(int num_drive_rr_nodes,$/;" f +find_pb_graph_pin_in_edges_interc_spice_model fpga_spice/fpga_spice_utils.c /^t_spice_model* find_pb_graph_pin_in_edges_interc_spice_model(t_pb_graph_pin pb_graph_pin) {$/;" f +find_pb_graph_pin_in_edges_interc_type fpga_spice/fpga_spice_utils.c /^enum e_interconnect find_pb_graph_pin_in_edges_interc_type(t_pb_graph_pin pb_graph_pin) {$/;" f +find_pb_graph_pin_in_edges_interc_verilog_model syn_verilog/verilog_pbtypes.c /^t_spice_model* find_pb_graph_pin_in_edges_interc_verilog_model(t_pb_graph_pin pb_graph_pin) {$/;" f +find_pb_mapped_logical_block_rec fpga_spice/fpga_spice_utils.c /^int find_pb_mapped_logical_block_rec(t_pb* cur_pb,$/;" f +find_pb_type_idle_mode_index fpga_spice/fpga_spice_utils.c /^int find_pb_type_idle_mode_index(t_pb_type cur_pb_type) {$/;" f +find_pb_type_physical_mode_index fpga_spice/fpga_spice_utils.c /^int find_pb_type_physical_mode_index(t_pb_type cur_pb_type) {$/;" f +find_pb_type_port_match_spice_model_port fpga_spice/fpga_spice_utils.c /^t_port* find_pb_type_port_match_spice_model_port(t_pb_type* pb_type,$/;" f +find_pb_type_ports_match_spice_model_port_type fpga_spice/fpga_spice_utils.c /^t_port** find_pb_type_ports_match_spice_model_port_type(t_pb_type* pb_type,$/;" f +find_prev_rr_nodes_with_src fpga_spice/fpga_spice_utils.c /^void find_prev_rr_nodes_with_src(t_rr_node* src_rr_node,$/;" f +find_rr_nodes_ipin_driver_switch route/rr_graph_opincb.c /^void find_rr_nodes_ipin_driver_switch() {$/;" f file: +find_spice_model_config_done_ports fpga_spice/fpga_spice_utils.c /^t_spice_model_port** find_spice_model_config_done_ports(t_spice_model* spice_model,$/;" f +find_spice_model_ports fpga_spice/fpga_spice_utils.c /^t_spice_model_port** find_spice_model_ports(t_spice_model* spice_model,$/;" f +find_spice_mux_arch_special_basis_size fpga_spice/fpga_spice_utils.c /^int find_spice_mux_arch_special_basis_size(t_spice_mux_arch spice_mux_arch) {$/;" f +find_spice_testbench_pb_pin_mux_load_inv_size spice/spice_utils.c /^float find_spice_testbench_pb_pin_mux_load_inv_size(t_spice_model* fan_out_spice_model) {$/;" f +find_spice_testbench_rr_mux_load_inv_size spice/spice_utils.c /^float find_spice_testbench_rr_mux_load_inv_size(t_rr_node* load_rr_node,$/;" f +find_src_pb_pin_to_rr_nodes clb_pin_remap/clb_pin_remap_util.c /^void find_src_pb_pin_to_rr_nodes(t_pb* src_pb,$/;" f +find_tnode_net_name timing/path_delay.c /^static char * find_tnode_net_name(int inode, boolean is_prepacked) {$/;" f file: +find_to place/place.c /^static boolean find_to(int x_from, int y_from, t_type_ptr type, float rlim, int *x_to, int *y_to) {$/;" f file: +find_type_col base/SetupGrid.c /^static t_type_ptr find_type_col(INP int x) {$/;" f file: +findfontsize base/graphics.c /^int findfontsize(float ymax) { }$/;" f +findfontsize base/graphics.c /^int findfontsize(float ymax) {$/;" f +first_iter_pres_fac base/ReadOptions.h /^ float first_iter_pres_fac;$/;" m struct:s_options +first_iter_pres_fac base/vpr_types.h /^ float first_iter_pres_fac;$/;" m struct:s_router_opts +fix_name base/verilog_writer.c /^char *fix_name(char *name)$/;" f +fixed_channel_width base/vpr_types.h /^ int fixed_channel_width;$/;" m struct:s_router_opts +fixup_branch timing/slre.c /^static void fixup_branch(struct slre *r, int fixup) {$/;" f file: +flags ../../libarchfpga/include/ezxml.h /^ short flags; \/* additional information *\/$/;" m struct:ezxml +flush_intermediate_queues pack/cluster_placement.c /^static void flush_intermediate_queues($/;" f file: +flushinput base/graphics.c /^flushinput (void) $/;" f +flushinput base/graphics.c /^void flushinput (void) { }$/;" f +font_info base/graphics.c /^static LOGFONT *font_info[MAX_FONT_SIZE+1]; \/* Data for each size *\/$/;" v file: +font_info base/graphics.c /^static XFontStruct *font_info[MAX_FONT_SIZE+1]; \/* Data for each size *\/$/;" v file: +font_is_loaded base/graphics.c /^static bool font_is_loaded[MAX_FONT_SIZE + 1];$/;" v file: +force_post_place_route_cb_input_pins pack/cluster_legality.c /^void force_post_place_route_cb_input_pins(int iblock) {$/;" f +force_setcolor base/graphics.c /^static void force_setcolor (int cindex) $/;" f file: +force_setfontsize base/graphics.c /^static void force_setfontsize (int pointsize) $/;" f file: +force_setlinestyle base/graphics.c /^static void force_setlinestyle (int linestyle) $/;" f file: +force_setlinewidth base/graphics.c /^static void force_setlinewidth (int linewidth) $/;" f file: +format ../../libarchfpga/include/physical_types.h /^ enum e_pin_to_pin_annotation_format format;$/;" m struct:s_pin_to_pin_annotation typeref:enum:s_pin_to_pin_annotation::e_pin_to_pin_annotation_format +format_dir_path fpga_spice/fpga_spice_utils.c /^char* format_dir_path(char* dir_path) {$/;" f +format_spice_node_prefix fpga_spice/fpga_spice_utils.c /^char* format_spice_node_prefix(char* spice_node_prefix) {$/;" f +format_verilog_node_prefix syn_verilog/verilog_utils.c /^char* format_verilog_node_prefix(char* verilog_node_prefix) {$/;" f +forward_expand_pack_pattern_from_edge pack/prepack.c /^static void forward_expand_pack_pattern_from_edge($/;" f file: +forward_infer_pattern pack/prepack.c /^static void forward_infer_pattern(INOUTP t_pb_graph_pin *pb_graph_pin) {$/;" f file: +forward_weight base/vpr_types.h /^ float forward_weight, backward_weight; \/* Weightings of the importance of paths $/;" m struct:s_tnode +found_connectivity base/verilog_writer.h /^typedef struct found_connectivity{$/;" s +found_pins base/verilog_writer.h /^typedef struct found_pins{$/;" s +fpga_spice_free fpga_spice/fpga_spice_setup.c /^void fpga_spice_free(t_arch* Arch) {$/;" f +fpga_spice_inpad_model fpga_spice/fpga_spice_globals.c /^t_spice_model* fpga_spice_inpad_model = NULL;$/;" v +fpga_spice_iopad_model fpga_spice/fpga_spice_globals.c /^t_spice_model* fpga_spice_iopad_model = NULL;$/;" v +fpga_spice_leakage_only base/vpr_types.h /^ boolean fpga_spice_leakage_only;$/;" m struct:s_spice_opts +fpga_spice_outpad_model fpga_spice/fpga_spice_globals.c /^t_spice_model* fpga_spice_outpad_model = NULL;$/;" v +fpga_spice_parasitic_net_estimation_off base/vpr_types.h /^ boolean fpga_spice_parasitic_net_estimation_off;$/;" m struct:s_spice_opts +fpga_spice_setup fpga_spice/fpga_spice_setup.c /^void fpga_spice_setup(t_vpr_setup vpr_setup,$/;" f +fpga_spice_sram_model fpga_spice/fpga_spice_globals.c /^t_spice_model* fpga_spice_sram_model = NULL;$/;" v +fpga_spice_sram_orgz_type fpga_spice/fpga_spice_globals.c /^enum e_sram_orgz fpga_spice_sram_orgz_type = SPICE_SRAM_STANDALONE;$/;" v typeref:enum:e_sram_orgz +fpga_spice_testbench_load_extraction_off base/vpr_types.h /^ boolean fpga_spice_testbench_load_extraction_off;$/;" m struct:s_spice_opts +fprint_call_defined_channels spice/spice_utils.c /^void fprint_call_defined_channels(FILE* fp,$/;" f +fprint_call_defined_connection_boxes spice/spice_utils.c /^void fprint_call_defined_connection_boxes(FILE* fp) {$/;" f +fprint_call_defined_grids spice/spice_utils.c /^void fprint_call_defined_grids(FILE* fp) {$/;" f +fprint_call_defined_one_channel spice/spice_utils.c /^void fprint_call_defined_one_channel(FILE* fp,$/;" f +fprint_call_defined_one_connection_box spice/spice_utils.c /^void fprint_call_defined_one_connection_box(FILE* fp,$/;" f +fprint_call_defined_one_switch_box spice/spice_utils.c /^void fprint_call_defined_one_switch_box(FILE* fp,$/;" f +fprint_call_defined_switch_boxes spice/spice_utils.c /^void fprint_call_defined_switch_boxes(FILE* fp) {$/;" f +fprint_commented_sram_bits fpga_spice/fpga_spice_utils.c /^void fprint_commented_sram_bits(FILE* fp,$/;" f +fprint_connection_box_interc spice/spice_routing.c /^void fprint_connection_box_interc(FILE* fp,$/;" f +fprint_connection_box_mux spice/spice_routing.c /^void fprint_connection_box_mux(FILE* fp,$/;" f +fprint_connection_box_short_interc spice/spice_routing.c /^void fprint_connection_box_short_interc(FILE* fp,$/;" f +fprint_global_pad_ports_spice_model spice/spice_utils.c /^void fprint_global_pad_ports_spice_model(FILE* fp, $/;" f +fprint_global_vdds_logical_block_spice_model spice/spice_utils.c /^void fprint_global_vdds_logical_block_spice_model(FILE* fp,$/;" f +fprint_global_vdds_spice_model spice/spice_utils.c /^void fprint_global_vdds_spice_model(FILE* fp, $/;" f +fprint_grid_block_subckt_pins spice/spice_pbtypes.c /^void fprint_grid_block_subckt_pins(FILE* fp,$/;" f +fprint_grid_blocks spice/spice_pbtypes.c /^void fprint_grid_blocks(FILE* fp,$/;" f +fprint_grid_float_port_stimulation spice/spice_utils.c /^void fprint_grid_float_port_stimulation(FILE* fp) {$/;" f +fprint_grid_global_vdds_spice_model spice/spice_utils.c /^void fprint_grid_global_vdds_spice_model(FILE* fp, int x, int y, $/;" f +fprint_grid_physical_blocks spice/spice_pbtypes.c /^void fprint_grid_physical_blocks(FILE* fp,$/;" f +fprint_grid_pins spice/spice_pbtypes.c /^void fprint_grid_pins(FILE* fp,$/;" f +fprint_grid_side_pin_with_given_index spice/spice_routing.c /^void fprint_grid_side_pin_with_given_index(FILE* fp,$/;" f +fprint_grid_side_pins spice/spice_routing.c /^void fprint_grid_side_pins(FILE* fp,$/;" f +fprint_grid_splited_vdds_spice_model spice/spice_utils.c /^void fprint_grid_splited_vdds_spice_model(FILE* fp, int grid_x, int grid_y,$/;" f +fprint_grid_testbench_one_grid_stimulation spice/spice_grid_testbench.c /^void fprint_grid_testbench_one_grid_stimulation(FILE* fp, $/;" f +fprint_include_user_defined_netlists spice/spice_utils.c /^void fprint_include_user_defined_netlists(FILE* fp,$/;" f +fprint_io_grid_block_subckt_pins spice/spice_pbtypes.c /^void fprint_io_grid_block_subckt_pins(FILE* fp,$/;" f +fprint_io_grid_pins spice/spice_pbtypes.c /^void fprint_io_grid_pins(FILE* fp,$/;" f +fprint_measure_grid_vdds_spice_model spice/spice_utils.c /^void fprint_measure_grid_vdds_spice_model(FILE* fp, int grid_x, int grid_y,$/;" f +fprint_measure_vdds_cbs spice/spice_top_netlist.c /^void fprint_measure_vdds_cbs(FILE* fp,$/;" f file: +fprint_measure_vdds_logical_block_spice_model spice/spice_utils.c /^void fprint_measure_vdds_logical_block_spice_model(FILE* fp,$/;" f +fprint_measure_vdds_sbs spice/spice_top_netlist.c /^void fprint_measure_vdds_sbs(FILE* fp,$/;" f file: +fprint_measure_vdds_spice_model spice/spice_utils.c /^void fprint_measure_vdds_spice_model(FILE* fp,$/;" f +fprint_one_design_param_w_wo_variation spice/spice_utils.c /^void fprint_one_design_param_w_wo_variation(FILE* fp,$/;" f +fprint_pb_primitive_ff spice/spice_primitives.c /^void fprint_pb_primitive_ff(FILE* fp,$/;" f +fprint_pb_primitive_hardlogic spice/spice_primitives.c /^void fprint_pb_primitive_hardlogic(FILE* fp,$/;" f +fprint_pb_primitive_io spice/spice_primitives.c /^void fprint_pb_primitive_io(FILE* fp,$/;" f +fprint_pb_primitive_lut spice/spice_lut.c /^void fprint_pb_primitive_lut(FILE* fp,$/;" f +fprint_pb_primitive_spice_model spice/spice_pbtypes.c /^void fprint_pb_primitive_spice_model(FILE* fp,$/;" f +fprint_pb_type_ports spice/spice_pbtypes.c /^void fprint_pb_type_ports(FILE* fp,$/;" f +fprint_routing_chan_subckt spice/spice_routing.c /^void fprint_routing_chan_subckt(FILE* fp,$/;" f +fprint_routing_connection_box_subckt spice/spice_routing.c /^void fprint_routing_connection_box_subckt(FILE* fp, t_cb cur_cb_info,$/;" f +fprint_routing_switch_box_subckt spice/spice_routing.c /^void fprint_routing_switch_box_subckt(FILE* fp, t_sb cur_sb_info,$/;" f +fprint_run_hspice_shell_script spice/spice_run_scripts.c /^void fprint_run_hspice_shell_script(t_spice spice,$/;" f +fprint_spice_block spice/spice_pbtypes.c /^void fprint_spice_block(FILE* fp,$/;" f +fprint_spice_cb_testbench_global_ports spice/spice_routing_testbench.c /^void fprint_spice_cb_testbench_global_ports(FILE* fp,$/;" f file: +fprint_spice_circuit_param spice/spice_utils.c /^void fprint_spice_circuit_param(FILE* fp,$/;" f +fprint_spice_cmos_mux_multilevel_structure spice/spice_mux.c /^void fprint_spice_cmos_mux_multilevel_structure(FILE* fp, $/;" f +fprint_spice_cmos_mux_onelevel_structure spice/spice_mux.c /^void fprint_spice_cmos_mux_onelevel_structure(FILE* fp, char* mux_basis_subckt_name,$/;" f +fprint_spice_cmos_mux_tree_structure spice/spice_mux.c /^void fprint_spice_cmos_mux_tree_structure(FILE* fp, char* mux_basis_subckt_name,$/;" f +fprint_spice_dangling_des_pb_graph_pin_interc spice/spice_pbtypes.c /^void fprint_spice_dangling_des_pb_graph_pin_interc(FILE* fp,$/;" f +fprint_spice_design_param_header spice/spice_heads.c /^void fprint_spice_design_param_header(char* design_param_file_name,$/;" f file: +fprint_spice_generic_testbench_global_ports spice/spice_utils.c /^void fprint_spice_generic_testbench_global_ports(FILE* fp, $/;" f +fprint_spice_global_ports spice/spice_utils.c /^int fprint_spice_global_ports(FILE* fp, t_llist* head) {$/;" f +fprint_spice_global_vdd_connection_boxes spice/spice_utils.c /^void fprint_spice_global_vdd_connection_boxes(FILE* fp) {$/;" f +fprint_spice_global_vdd_switch_boxes spice/spice_utils.c /^void fprint_spice_global_vdd_switch_boxes(FILE* fp) {$/;" f +fprint_spice_grid_testbench_call_defined_core_grids spice/spice_grid_testbench.c /^void fprint_spice_grid_testbench_call_defined_core_grids(FILE* fp) {$/;" f +fprint_spice_grid_testbench_call_one_defined_grid spice/spice_grid_testbench.c /^void fprint_spice_grid_testbench_call_one_defined_grid(FILE* fp, int ix, int iy) {$/;" f +fprint_spice_grid_testbench_global_ports spice/spice_grid_testbench.c /^void fprint_spice_grid_testbench_global_ports(FILE* fp, int x, int y,$/;" f file: +fprint_spice_grid_testbench_measurements spice/spice_grid_testbench.c /^void fprint_spice_grid_testbench_measurements(FILE* fp, int grid_x, int grid_y, $/;" f file: +fprint_spice_grid_testbench_stimulations spice/spice_grid_testbench.c /^void fprint_spice_grid_testbench_stimulations(FILE* fp, $/;" f file: +fprint_spice_hardlogic_testbench_call_defined_hardlogics spice/spice_hardlogic_testbench.c /^void fprint_spice_hardlogic_testbench_call_defined_hardlogics(FILE* fp, $/;" f +fprint_spice_hardlogic_testbench_call_one_grid_defined_hardlogics spice/spice_hardlogic_testbench.c /^void fprint_spice_hardlogic_testbench_call_one_grid_defined_hardlogics(FILE* fp,$/;" f +fprint_spice_hardlogic_testbench_global_ports spice/spice_hardlogic_testbench.c /^void fprint_spice_hardlogic_testbench_global_ports(FILE* fp, int grid_x, int grid_y, $/;" f file: +fprint_spice_hardlogic_testbench_measurements spice/spice_hardlogic_testbench.c /^void fprint_spice_hardlogic_testbench_measurements(FILE* fp, int grid_x, int grid_y, $/;" f +fprint_spice_hardlogic_testbench_one_hardlogic spice/spice_hardlogic_testbench.c /^void fprint_spice_hardlogic_testbench_one_hardlogic(FILE* fp, $/;" f +fprint_spice_hardlogic_testbench_one_pb_graph_node_hardlogic spice/spice_hardlogic_testbench.c /^void fprint_spice_hardlogic_testbench_one_pb_graph_node_hardlogic(FILE* fp, $/;" f +fprint_spice_hardlogic_testbench_rec_pb_graph_node_hardlogics spice/spice_hardlogic_testbench.c /^void fprint_spice_hardlogic_testbench_rec_pb_graph_node_hardlogics(FILE* fp,$/;" f +fprint_spice_hardlogic_testbench_rec_pb_hardlogics spice/spice_hardlogic_testbench.c /^void fprint_spice_hardlogic_testbench_rec_pb_hardlogics(FILE* fp, $/;" f +fprint_spice_hardlogic_testbench_stimulations spice/spice_hardlogic_testbench.c /^void fprint_spice_hardlogic_testbench_stimulations(FILE* fp, int grid_x, int grid_y, $/;" f file: +fprint_spice_head spice/spice_utils.c /^void fprint_spice_head(FILE* fp,$/;" f +fprint_spice_headers spice/spice_heads.c /^void fprint_spice_headers(char* include_dir_path,$/;" f +fprint_spice_idle_block spice/spice_pbtypes.c /^void fprint_spice_idle_block(FILE* fp,$/;" f +fprint_spice_idle_pb_graph_node_rec spice/spice_pbtypes.c /^void fprint_spice_idle_pb_graph_node_rec(FILE* fp,$/;" f +fprint_spice_include_key_subckts spice/spice_utils.c /^void fprint_spice_include_key_subckts(FILE* fp,$/;" f +fprint_spice_include_param_headers spice/spice_utils.c /^void fprint_spice_include_param_headers(FILE* fp,$/;" f +fprint_spice_lut_subckt spice/spice_lut.c /^void fprint_spice_lut_subckt(FILE* fp,$/;" f +fprint_spice_lut_testbench_call_defined_luts spice/spice_lut_testbench.c /^void fprint_spice_lut_testbench_call_defined_luts(FILE* fp, t_ivec*** LL_rr_node_indices) {$/;" f +fprint_spice_lut_testbench_call_one_grid_defined_luts spice/spice_lut_testbench.c /^void fprint_spice_lut_testbench_call_one_grid_defined_luts(FILE* fp, int ix, int iy,$/;" f +fprint_spice_lut_testbench_conkt_lut_scan_chains spice/spice_lut_testbench.c /^void fprint_spice_lut_testbench_conkt_lut_scan_chains(FILE* fp, int grid_x, int grid_y, $/;" f +fprint_spice_lut_testbench_global_ports spice/spice_lut_testbench.c /^void fprint_spice_lut_testbench_global_ports(FILE* fp, int grid_x, int grid_y,$/;" f file: +fprint_spice_lut_testbench_measurements spice/spice_lut_testbench.c /^void fprint_spice_lut_testbench_measurements(FILE* fp, int grid_x, int grid_y, $/;" f +fprint_spice_lut_testbench_one_lut spice/spice_lut_testbench.c /^void fprint_spice_lut_testbench_one_lut(FILE* fp, $/;" f +fprint_spice_lut_testbench_one_pb_graph_node_lut spice/spice_lut_testbench.c /^void fprint_spice_lut_testbench_one_pb_graph_node_lut(FILE* fp, $/;" f +fprint_spice_lut_testbench_rec_pb_graph_node_luts spice/spice_lut_testbench.c /^void fprint_spice_lut_testbench_rec_pb_graph_node_luts(FILE* fp,$/;" f +fprint_spice_lut_testbench_rec_pb_luts spice/spice_lut_testbench.c /^void fprint_spice_lut_testbench_rec_pb_luts(FILE* fp, $/;" f +fprint_spice_lut_testbench_stimulations spice/spice_lut_testbench.c /^void fprint_spice_lut_testbench_stimulations(FILE* fp, int grid_x, int grid_y,$/;" f +fprint_spice_meas_header spice/spice_heads.c /^void fprint_spice_meas_header(char* meas_file_name,$/;" f file: +fprint_spice_mux_model_basis_cmos_subckt spice/spice_mux.c /^void fprint_spice_mux_model_basis_cmos_subckt(FILE* fp, char* subckt_name,$/;" f file: +fprint_spice_mux_model_basis_rram_subckt spice/spice_mux.c /^void fprint_spice_mux_model_basis_rram_subckt(FILE* fp, char* subckt_name,$/;" f file: +fprint_spice_mux_model_basis_subckt spice/spice_mux.c /^void fprint_spice_mux_model_basis_subckt(FILE* fp, $/;" f file: +fprint_spice_mux_model_cmos_subckt spice/spice_mux.c /^void fprint_spice_mux_model_cmos_subckt(FILE* fp,$/;" f +fprint_spice_mux_model_rram_subckt spice/spice_mux.c /^void fprint_spice_mux_model_rram_subckt(FILE* fp,$/;" f +fprint_spice_mux_model_subckt spice/spice_mux.c /^void fprint_spice_mux_model_subckt(FILE* fp,$/;" f file: +fprint_spice_mux_testbench_call_one_grid_cb_muxes spice/spice_mux_testbench.c /^int fprint_spice_mux_testbench_call_one_grid_cb_muxes(FILE* fp, $/;" f file: +fprint_spice_mux_testbench_call_one_grid_pb_muxes spice/spice_mux_testbench.c /^int fprint_spice_mux_testbench_call_one_grid_pb_muxes(FILE* fp, int ix, int iy,$/;" f file: +fprint_spice_mux_testbench_call_one_grid_sb_muxes spice/spice_mux_testbench.c /^int fprint_spice_mux_testbench_call_one_grid_sb_muxes(FILE* fp, $/;" f file: +fprint_spice_mux_testbench_cb_interc spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_cb_interc(FILE* fp, $/;" f +fprint_spice_mux_testbench_cb_mux_meas spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_cb_mux_meas(FILE* fp,$/;" f file: +fprint_spice_mux_testbench_cb_one_mux spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_cb_one_mux(FILE* fp,$/;" f file: +fprint_spice_mux_testbench_global_ports spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_global_ports(FILE* fp,$/;" f file: +fprint_spice_mux_testbench_idle_pb_graph_node_muxes_rec spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_idle_pb_graph_node_muxes_rec(FILE* fp, $/;" f +fprint_spice_mux_testbench_measurements spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_measurements(FILE* fp, $/;" f file: +fprint_spice_mux_testbench_one_mux spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_one_mux(FILE* fp,$/;" f file: +fprint_spice_mux_testbench_pb_graph_node_interc spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_pb_graph_node_interc(FILE* fp,$/;" f file: +fprint_spice_mux_testbench_pb_graph_node_pin_interc spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_pb_graph_node_pin_interc(FILE* fp,$/;" f file: +fprint_spice_mux_testbench_pb_graph_node_pin_mux spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_pb_graph_node_pin_mux(FILE* fp,$/;" f file: +fprint_spice_mux_testbench_pb_interc spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_pb_interc(FILE* fp,$/;" f file: +fprint_spice_mux_testbench_pb_mux_meas spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_pb_mux_meas(FILE* fp,$/;" f file: +fprint_spice_mux_testbench_pb_muxes_rec spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_pb_muxes_rec(FILE* fp,$/;" f file: +fprint_spice_mux_testbench_pb_pin_interc spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_pb_pin_interc(FILE* fp,$/;" f file: +fprint_spice_mux_testbench_pb_pin_mux spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_pb_pin_mux(FILE* fp,$/;" f file: +fprint_spice_mux_testbench_sb_mux_meas spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_sb_mux_meas(FILE* fp,$/;" f file: +fprint_spice_mux_testbench_sb_one_mux spice/spice_mux_testbench.c /^int fprint_spice_mux_testbench_sb_one_mux(FILE* fp,$/;" f file: +fprint_spice_mux_testbench_stimulations spice/spice_mux_testbench.c /^void fprint_spice_mux_testbench_stimulations(FILE* fp, $/;" f file: +fprint_spice_netlist_generic_measurements spice/spice_utils.c /^void fprint_spice_netlist_generic_measurements(FILE* fp, $/;" f +fprint_spice_netlist_measurement_one_design_param spice/spice_utils.c /^void fprint_spice_netlist_measurement_one_design_param(FILE* fp,$/;" f +fprint_spice_netlist_transient_setting spice/spice_utils.c /^void fprint_spice_netlist_transient_setting(FILE* fp, $/;" f +fprint_spice_one_cb_testbench spice/spice_routing_testbench.c /^int fprint_spice_one_cb_testbench(char* formatted_spice_dir,$/;" f +fprint_spice_one_grid_testbench spice/spice_grid_testbench.c /^int fprint_spice_one_grid_testbench(char* formatted_spice_dir,$/;" f +fprint_spice_one_hardlogic_testbench spice/spice_hardlogic_testbench.c /^int fprint_spice_one_hardlogic_testbench(char* formatted_spice_dir,$/;" f +fprint_spice_one_lut_testbench spice/spice_lut_testbench.c /^int fprint_spice_one_lut_testbench(char* formatted_spice_dir,$/;" f +fprint_spice_one_mux_testbench spice/spice_mux_testbench.c /^int fprint_spice_one_mux_testbench(char* formatted_spice_dir,$/;" f +fprint_spice_one_sb_testbench spice/spice_routing_testbench.c /^int fprint_spice_one_sb_testbench(char* formatted_spice_dir,$/;" f +fprint_spice_one_specific_sram_subckt spice/spice_utils.c /^void fprint_spice_one_specific_sram_subckt(FILE* fp,$/;" f +fprint_spice_one_sram_subckt spice/spice_utils.c /^void fprint_spice_one_sram_subckt(FILE* fp,$/;" f +fprint_spice_options spice/spice_utils.c /^void fprint_spice_options(FILE* fp,$/;" f +fprint_spice_pb_graph_interc spice/spice_pbtypes.c /^void fprint_spice_pb_graph_interc(FILE* fp, $/;" f +fprint_spice_pb_graph_node_rec spice/spice_pbtypes.c /^void fprint_spice_pb_graph_node_rec(FILE* fp, $/;" f +fprint_spice_pb_graph_primitive_node spice/spice_pbtypes.c /^void fprint_spice_pb_graph_primitive_node(FILE* fp,$/;" f +fprint_spice_phy_pb_graph_node_rec spice/spice_pbtypes.c /^void fprint_spice_phy_pb_graph_node_rec(FILE* fp, $/;" f +fprint_spice_physical_block spice/spice_pbtypes.c /^void fprint_spice_physical_block(FILE* fp,$/;" f +fprint_spice_routing_testbench_call_one_cb_tb spice/spice_routing_testbench.c /^int fprint_spice_routing_testbench_call_one_cb_tb(FILE* fp,$/;" f file: +fprint_spice_routing_testbench_call_one_sb_tb spice/spice_routing_testbench.c /^int fprint_spice_routing_testbench_call_one_sb_tb(FILE* fp, $/;" f file: +fprint_spice_routing_testbench_global_ports spice/spice_routing_testbench.c /^void fprint_spice_routing_testbench_global_ports(FILE* fp,$/;" f file: +fprint_spice_rram_mux_multilevel_structure spice/spice_mux.c /^void fprint_spice_rram_mux_multilevel_structure(FILE* fp, char* mux_basis_subckt_name,$/;" f +fprint_spice_rram_mux_onelevel_structure spice/spice_mux.c /^void fprint_spice_rram_mux_onelevel_structure(FILE* fp, $/;" f +fprint_spice_rram_mux_tree_structure spice/spice_mux.c /^void fprint_spice_rram_mux_tree_structure(FILE* fp, char* mux_basis_subckt_name,$/;" f +fprint_spice_sb_testbench_global_ports spice/spice_routing_testbench.c /^void fprint_spice_sb_testbench_global_ports(FILE* fp,$/;" f file: +fprint_spice_sram_one_outport spice/spice_utils.c /^void fprint_spice_sram_one_outport(FILE* fp,$/;" f +fprint_spice_stimulate_header spice/spice_heads.c /^void fprint_spice_stimulate_header(char* stimulate_file_name,$/;" f file: +fprint_spice_testbench_generic_global_ports_stimuli spice/spice_utils.c /^void fprint_spice_testbench_generic_global_ports_stimuli(FILE* fp,$/;" f +fprint_spice_testbench_global_ports_stimuli spice/spice_utils.c /^void fprint_spice_testbench_global_ports_stimuli(FILE* fp, $/;" f +fprint_spice_testbench_global_sram_inport_stimuli spice/spice_utils.c /^void fprint_spice_testbench_global_sram_inport_stimuli(FILE* fp,$/;" f +fprint_spice_testbench_global_vdd_port_stimuli spice/spice_utils.c /^void fprint_spice_testbench_global_vdd_port_stimuli(FILE* fp,$/;" f +fprint_spice_testbench_one_cb_mux_loads spice/spice_utils.c /^void fprint_spice_testbench_one_cb_mux_loads(FILE* fp, int* testbench_load_cnt,$/;" f +fprint_spice_testbench_one_grid_pin_loads spice/spice_utils.c /^void fprint_spice_testbench_one_grid_pin_loads(FILE* fp, int x, int y, $/;" f +fprint_spice_testbench_one_grid_pin_stimulation spice/spice_utils.c /^void fprint_spice_testbench_one_grid_pin_stimulation(FILE* fp, int x, int y, $/;" f +fprint_spice_testbench_pb_graph_pin_inv_loads_rec spice/spice_utils.c /^void fprint_spice_testbench_pb_graph_pin_inv_loads_rec(FILE* fp, int* testbench_load_cnt, $/;" f +fprint_spice_testbench_rr_node_load_version spice/spice_utils.c /^char* fprint_spice_testbench_rr_node_load_version(FILE* fp, int* testbench_load_cnt,$/;" f +fprint_spice_testbench_wire_one_global_port_stimuli spice/spice_utils.c /^void fprint_spice_testbench_wire_one_global_port_stimuli(FILE* fp, $/;" f +fprint_spice_wire_model spice/spice_subckt.c /^void fprint_spice_wire_model(FILE* fp,$/;" f +fprint_splited_vdds_logical_block_spice_model spice/spice_utils.c /^void fprint_splited_vdds_logical_block_spice_model(FILE* fp,$/;" f +fprint_splited_vdds_spice_model spice/spice_utils.c /^void fprint_splited_vdds_spice_model(FILE* fp,$/;" f +fprint_stimulate_dangling_grid_pins spice/spice_utils.c /^void fprint_stimulate_dangling_grid_pins(FILE* fp) {$/;" f +fprint_stimulate_dangling_io_grid_pins spice/spice_utils.c /^void fprint_stimulate_dangling_io_grid_pins(FILE* fp,$/;" f +fprint_stimulate_dangling_normal_grid_pins spice/spice_utils.c /^void fprint_stimulate_dangling_normal_grid_pins(FILE* fp,$/;" f +fprint_stimulate_dangling_one_grid_pin spice/spice_utils.c /^void fprint_stimulate_dangling_one_grid_pin(FILE* fp,$/;" f +fprint_switch_box_chan_port spice/spice_routing.c /^void fprint_switch_box_chan_port(FILE* fp,$/;" f +fprint_switch_box_interc spice/spice_routing.c /^void fprint_switch_box_interc(FILE* fp, $/;" f +fprint_switch_box_mux spice/spice_routing.c /^void fprint_switch_box_mux(FILE* fp, $/;" f +fprint_switch_box_short_interc spice/spice_routing.c /^void fprint_switch_box_short_interc(FILE* fp, $/;" f +fprint_tech_lib spice/spice_utils.c /^void fprint_tech_lib(FILE* fp,$/;" f +fprint_top_netlist_global_ports spice/spice_top_netlist.c /^void fprint_top_netlist_global_ports(FILE* fp,$/;" f file: +fprint_top_netlist_measurements spice/spice_top_netlist.c /^void fprint_top_netlist_measurements(FILE* fp, $/;" f file: +fprint_top_netlist_stimulations spice/spice_top_netlist.c /^void fprint_top_netlist_stimulations(FILE* fp,$/;" f file: +fprint_voltage_pulse_params spice/spice_utils.c /^void fprint_voltage_pulse_params(FILE* fp,$/;" f +fprintf_spice_pb_graph_pin_interc spice/spice_pbtypes.c /^void fprintf_spice_pb_graph_pin_interc(FILE* fp,$/;" f +fprintf_spice_routing_testbench_generic_stimuli spice/spice_routing_testbench.c /^void fprintf_spice_routing_testbench_generic_stimuli(FILE* fp,$/;" f file: +fptr base/vpr_types.h /^ float *fptr;$/;" m struct:s_linked_f_pointer +frac_cb ../../libarchfpga/include/physical_types.h /^ float frac_cb;$/;" m struct:s_segment_inf +frac_sb ../../libarchfpga/include/physical_types.h /^ float frac_sb;$/;" m struct:s_segment_inf +freeGrid base/SetupGrid.c /^void freeGrid() {$/;" f +freeTokens util/token.c /^void freeTokens(INP t_token *tokens, INP int num_tokens) {$/;" f +free_all_pb_graph_nodes pack/pb_type_graph.c /^void free_all_pb_graph_nodes(void) {$/;" f +free_and_reset_internal_structures place/timing_place_lookup.c /^static void free_and_reset_internal_structures(struct s_net *original_net,$/;" f file: +free_arch base/vpr_api.c /^void free_arch(t_arch* Arch) {$/;" f +free_backannotate_vpr_post_route_info fpga_spice/fpga_spice_backannotate_utils.c /^void free_backannotate_vpr_post_route_info() {$/;" f +free_best_buffer_list mrfpga/buffer_insertion.c /^static void free_best_buffer_list( )$/;" f file: +free_blk_pin_from_port_pin util/vpr_utils.c /^void free_blk_pin_from_port_pin(void) {$/;" f +free_buffer_list mrfpga/buffer_insertion.c /^static void free_buffer_list( t_buffer_plan_list list )$/;" f file: +free_cb util/vpr_utils.c /^void free_cb(t_pb *pb) {$/;" f +free_cb_info_array fpga_spice/fpga_spice_backannotate_utils.c /^void free_cb_info_array(t_cb*** LL_cb_info, int LL_nx, int LL_ny) {$/;" f +free_chunk_memory ../../libarchfpga/util.c /^void free_chunk_memory(t_chunk *chunk_info) {$/;" f +free_chunk_memory_trace route/route_common.c /^void free_chunk_memory_trace(void) {$/;" f +free_circuit base/vpr_api.c /^void free_circuit() {$/;" f +free_clb_nets_spice_net_info fpga_spice/fpga_spice_backannotate_utils.c /^void free_clb_nets_spice_net_info() {$/;" f +free_clock_constraint timing/read_sdc.c /^static void free_clock_constraint(t_clock *& clock_array, int num_clocks) {$/;" f file: +free_cluster_legality_checker pack/cluster_legality.c /^void free_cluster_legality_checker(void) {$/;" f +free_cluster_placement_stats pack/cluster_placement.c /^void free_cluster_placement_stats($/;" f +free_complex_block_types base/vpr_api.c /^static void free_complex_block_types(void) {$/;" f file: +free_conf_bit fpga_spice/fpga_spice_utils.c /^void free_conf_bit(t_conf_bit* conf_bit) {$/;" f +free_conf_bit_info fpga_spice/fpga_spice_utils.c /^void free_conf_bit_info(t_conf_bit_info* conf_bit_info) {$/;" f +free_crit place/timing_place.c /^static void free_crit(t_chunk *chunk_list_ptr){$/;" f file: +free_delta_arrays place/timing_place_lookup.c /^static void free_delta_arrays(void) {$/;" f file: +free_draw_structs base/draw.c /^void free_draw_structs(void) {$/;" f +free_echo_file_info base/ReadOptions.c /^void free_echo_file_info() {$/;" f +free_edge_list_head route/rr_graph2.c /^t_linked_edge *free_edge_list_head = NULL;$/;" v +free_fast_cost_update place/place.c /^static void free_fast_cost_update(void) {$/;" f file: +free_global_routing_conf_bits syn_verilog/syn_verilog_api.c /^void free_global_routing_conf_bits() {$/;" f file: +free_hash_table util/hash.c /^void free_hash_table(struct s_hash **hash_table) {$/;" f +free_heap_data route/route_common.c /^void free_heap_data(struct s_heap *hptr) {$/;" f +free_imacro_from_iblk place/place_macro.c /^static void free_imacro_from_iblk(void) {$/;" f file: +free_int_list ../../libarchfpga/util.c /^void free_int_list(t_linked_int ** int_list_head_ptr) {$/;" f +free_io_constraint timing/read_sdc.c /^static void free_io_constraint(t_io *& io_array, int num_ios) {$/;" f file: +free_ivec_matrix ../../libarchfpga/util.c /^void free_ivec_matrix(struct s_ivec **ivec_matrix, int nrmin, int nrmax,$/;" f +free_ivec_matrix3 ../../libarchfpga/util.c /^void free_ivec_matrix3(struct s_ivec ***ivec_matrix3, int nrmin, int nrmax,$/;" f +free_ivec_vector ../../libarchfpga/util.c /^void free_ivec_vector(struct s_ivec *ivec_vector, int nrmin, int nrmax) {$/;" f +free_legal_placements place/place.c /^static void free_legal_placements() {$/;" f file: +free_legalizer_for_cluster pack/cluster_legality.c /^void free_legalizer_for_cluster(INP t_block* clb, boolean free_local_rr_graph) {$/;" f +free_linked_list base/verilog_writer.c /^pb_list *free_linked_list(pb_list *list)$/;" f +free_linked_list_conn base/verilog_writer.c /^conn_list *free_linked_list_conn(conn_list *list)$/;" f +free_linked_rc_edge timing/net_delay.c /^void free_linked_rc_edge(t_linked_rc_edge * rc_edge,$/;" f +free_linked_rt_edge route/route_tree_timing.c /^static void free_linked_rt_edge(t_linked_rt_edge * rt_edge) {$/;" f file: +free_list_of_pack_patterns pack/prepack.c /^void free_list_of_pack_patterns(INP t_pack_patterns *list_of_pack_patterns, INP int num_packing_patterns) {$/;" f +free_llist ../../libarchfpga/linkedlist.c /^void free_llist(t_llist* head) {$/;" f +free_logical_blocks base/read_netlist.c /^void free_logical_blocks(void) {$/;" f +free_logical_nets base/read_netlist.c /^void free_logical_nets(void) {$/;" f +free_lookups_and_criticalities place/timing_place.c /^void free_lookups_and_criticalities(float ***net_delay, t_slack * slacks) {$/;" f +free_matrix ../../libarchfpga/util.c /^void free_matrix(void *vptr, int nrmin, int nrmax, int ncmin, size_t elsize) {$/;" f +free_matrix3 ../../libarchfpga/util.c /^void free_matrix3(void *vptr, int nrmin, int nrmax, int ncmin, int ncmax,$/;" f +free_matrix4 ../../libarchfpga/util.c /^void free_matrix4(void *vptr, int nrmin, int nrmax, int ncmin, int ncmax,$/;" f +free_muxes_llist fpga_spice/fpga_spice_utils.c /^void free_muxes_llist(t_llist* muxes_head) {$/;" f +free_net_delay timing/net_delay.c /^void free_net_delay(float **net_delay,$/;" f +free_one_cb_info fpga_spice/fpga_spice_backannotate_utils.c /^void free_one_cb_info(t_cb* cur_cb) {$/;" f +free_one_mem_bank_info fpga_spice/fpga_spice_utils.c /^void free_one_mem_bank_info(t_mem_bank_info* mem_bank_info) {$/;" f +free_one_sb_info fpga_spice/fpga_spice_backannotate_utils.c /^void free_one_sb_info(t_sb* cur_sb) {$/;" f +free_one_scff_info fpga_spice/fpga_spice_utils.c /^void free_one_scff_info(t_scff_info* scff_info) {$/;" f +free_one_spice_model_grid_index_low_high fpga_spice/fpga_spice_utils.c /^void free_one_spice_model_grid_index_low_high(t_spice_model* cur_spice_model) {$/;" f +free_one_spice_model_routing_index_low_high fpga_spice/fpga_spice_utils.c /^void free_one_spice_model_routing_index_low_high(t_spice_model* cur_spice_model) {$/;" f +free_one_standalone_sram_info fpga_spice/fpga_spice_utils.c /^void free_one_standalone_sram_info(t_standalone_sram_info* standalone_sram_info) {$/;" f +free_options base/vpr_api.c /^void free_options(t_options *options) {$/;" f +free_output_file_names base/ReadOptions.c /^void free_output_file_names() {$/;" f +free_override_constraint timing/read_sdc.c /^void free_override_constraint(t_override_constraint *& constraint_array, int num_constraints) {$/;" f +free_pack_pattern pack/prepack.c /^static void free_pack_pattern(INOUTP t_pack_pattern_block *pattern_block, INOUTP t_pack_pattern_block **pattern_block_list) {$/;" f file: +free_parse base/read_blif.c /^static void free_parse(void) {$/;" f file: +free_pb util/vpr_utils.c /^void free_pb(t_pb *pb) {$/;" f +free_pb_data base/place_and_route.c /^void free_pb_data(t_pb *pb) {$/;" f +free_pb_graph pack/pb_type_graph.c /^static void free_pb_graph(INOUTP t_pb_graph_node *pb_graph_node) {$/;" f file: +free_pb_stats util/vpr_utils.c /^void free_pb_stats(t_pb *pb) {$/;" f +free_pb_stats_recursive pack/cluster.c /^static void free_pb_stats_recursive(t_pb *pb) {$/;" f file: +free_pb_type base/vpr_api.c /^static void free_pb_type(t_pb_type *pb_type) {$/;" f file: +free_place_lookup_structs place/timing_place_lookup.c /^void free_place_lookup_structs(void) {$/;" f +free_placement_macros_structs place/place_macro.c /^void free_placement_macros_structs(void) {$/;" f +free_placement_structs place/place.c /^static void free_placement_structs($/;" f file: +free_port_pin_from_blk_pin util/vpr_utils.c /^void free_port_pin_from_blk_pin(void) {$/;" f +free_rc_edge_free_list timing/net_delay.c /^void free_rc_edge_free_list(t_linked_rc_edge * rc_edge_free_list) {$/;" f +free_rc_node timing/net_delay.c /^void free_rc_node(t_rc_node * rc_node,$/;" f +free_rc_node_free_list timing/net_delay.c /^void free_rc_node_free_list(t_rc_node * rc_node_free_list) {$/;" f +free_rc_tree timing/net_delay.c /^void free_rc_tree(t_rc_node * rc_root,$/;" f +free_route_structs route/route_common.c /^void free_route_structs() {$/;" f +free_route_tree route/route_tree_timing.c /^void free_route_tree(t_rt_node * rt_node) {$/;" f +free_route_tree_timing_structs route/route_tree_timing.c /^void free_route_tree_timing_structs(void) {$/;" f +free_routing_structs place/timing_place_lookup.c /^static void free_routing_structs(struct s_router_opts router_opts,$/;" f file: +free_rr_graph route/rr_graph.c /^void free_rr_graph(void) {$/;" f +free_rr_node_indices route/rr_graph2.c /^void free_rr_node_indices(INP t_ivec *** L_rr_node_indices) {$/;" f +free_rr_node_route_structs route/route_common.c /^void free_rr_node_route_structs(void) {$/;" f +free_rt_node route/route_tree_timing.c /^static void free_rt_node(t_rt_node * rt_node) {$/;" f file: +free_saved_routing route/route_common.c /^void free_saved_routing(struct s_trace **best_routing,$/;" f +free_sb_info_array fpga_spice/fpga_spice_backannotate_utils.c /^void free_sb_info_array(t_sb*** LL_sb_info, int LL_nx, int LL_ny) {$/;" f +free_sblock_pattern_lookup route/rr_graph2.c /^void free_sblock_pattern_lookup(INOUTP short *****sblock_pattern) {$/;" f +free_sdc_related_structs timing/read_sdc.c /^void free_sdc_related_structs(void) {$/;" f +free_seg_details route/rr_graph2.c /^void free_seg_details(t_seg_details * seg_details, int nodes_per_chan) {$/;" f +free_spice_model_grid_index_low_high fpga_spice/fpga_spice_utils.c /^void free_spice_model_grid_index_low_high(int num_spice_models, $/;" f +free_spice_model_routing_index_low_high fpga_spice/fpga_spice_utils.c /^void free_spice_model_routing_index_low_high(int num_spice_models, $/;" f +free_spice_tb_llist spice/spice_api.c /^void free_spice_tb_llist() {$/;" f file: +free_sram_orgz_info fpga_spice/fpga_spice_utils.c /^void free_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info,$/;" f +free_switch_block_conn route/rr_graph_sbox.c /^void free_switch_block_conn(struct s_ivec ***switch_block_conn,$/;" f +free_timing_driven_route_structs route/route_timing.c /^void free_timing_driven_route_structs(float *pin_criticality, int *sink_order,$/;" f +free_timing_graph timing/path_delay.c /^void free_timing_graph(t_slack * slacks) {$/;" f +free_timing_stats timing/path_delay.c /^void free_timing_stats(void) {$/;" f +free_trace_data route/route_common.c /^static void free_trace_data(struct s_trace *tptr) {$/;" f file: +free_trace_structs route/route_common.c /^void free_trace_structs(void) {$/;" f +free_traceback route/route_common.c /^void free_traceback(int inet) {$/;" f +free_try_swap_arrays place/place.c /^static void free_try_swap_arrays(void) {$/;" f file: +free_type_pin_to_track_map route/rr_graph.c /^static void free_type_pin_to_track_map(int***** ipin_to_track_map,$/;" f file: +free_type_track_to_ipin_map route/rr_graph.c /^static void free_type_track_to_ipin_map(struct s_ivec**** track_to_pin_map,$/;" f file: +freq ../../libarchfpga/fpga_spice_include/spice_types.h /^ float freq; $/;" m struct:s_spice_net_info +frequency ../../libarchfpga/include/physical_types.h /^ int frequency;$/;" m struct:s_segment_inf +from_block ../../libarchfpga/include/cad_types.h /^ t_pack_pattern_block *from_block;$/;" m struct:s_pack_pattern_connections +from_clb_pin_end_index route/pb_pin_eq_auto_detect.c /^ int from_clb_pin_end_index;$/;" m struct:s_clb_to_clb_directs file: +from_clb_pin_end_index route/rr_graph.c /^ int from_clb_pin_end_index;$/;" m struct:s_clb_to_clb_directs file: +from_clb_pin_start_index route/pb_pin_eq_auto_detect.c /^ int from_clb_pin_start_index;$/;" m struct:s_clb_to_clb_directs file: +from_clb_pin_start_index route/rr_graph.c /^ int from_clb_pin_start_index;$/;" m struct:s_clb_to_clb_directs file: +from_clb_type route/pb_pin_eq_auto_detect.c /^ t_type_descriptor *from_clb_type;$/;" m struct:s_clb_to_clb_directs file: +from_clb_type route/rr_graph.c /^ t_type_descriptor *from_clb_type;$/;" m struct:s_clb_to_clb_directs file: +from_pin ../../libarchfpga/include/cad_types.h /^ t_pb_graph_pin *from_pin;$/;" m struct:s_pack_pattern_connections +from_pin ../../libarchfpga/include/physical_types.h /^ char *from_pin;$/;" m struct:s_direct_inf +front mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan_list { t_buffer_plan_node* front; } t_buffer_plan_list;$/;" m struct:s_buffer_plan_list file: +fs base/place_and_route.h /^ int fs; \/* at this fs *\/$/;" m struct:s_fmap_cell +fs base/vpr_types.h /^ int fs;$/;" m struct:s_sb +full_stats base/vpr_types.h /^ boolean full_stats;$/;" m struct:s_router_opts +g_MTA_area power/power_sizing.c /^static double g_MTA_area;$/;" v file: +g_buffer_strength_last_searched power/power_cmos_tech.c /^static t_power_buffer_strength_inf * g_buffer_strength_last_searched;$/;" v file: +g_clock_arch base/globals.c /^t_clock_arch * g_clock_arch;$/;" v +g_mux_volt_last_searched power/power_cmos_tech.c /^static t_power_mux_volt_inf * g_mux_volt_last_searched;$/;" v file: +g_power_arch power/power.c /^t_power_arch * g_power_arch;$/;" v +g_power_by_component power/power_components.c /^t_power_components g_power_by_component;$/;" v +g_power_commonly_used power/power.c /^t_power_commonly_used * g_power_commonly_used;$/;" v +g_power_output power/power.c /^t_power_output * g_power_output;$/;" v +g_power_searching_nmos_leakage_info power/power_cmos_tech.c /^t_power_nmos_leakage_inf * g_power_searching_nmos_leakage_info;$/;" v +g_power_tech power/power.c /^t_power_tech * g_power_tech;$/;" v +g_sdc timing/read_sdc.c /^t_timing_constraints * g_sdc = NULL;$/;" v +g_solution_inf power/power.c /^t_solution_inf g_solution_inf;$/;" v +g_transistor_last_searched power/power_cmos_tech.c /^static t_transistor_inf * g_transistor_last_searched;$/;" v file: +gain base/vpr_types.h /^ std::map gain; \/* Attraction (inverse of cost) function *\/$/;" m struct:s_pb_stats +gc base/graphics.c /^static GC gc, gcxor, gc_menus, current_gc;$/;" v file: +gc_menus base/graphics.c /^static GC gc, gcxor, gc_menus, current_gc;$/;" v file: +gcxor base/graphics.c /^static GC gc, gcxor, gc_menus, current_gc;$/;" v file: +gen_spice_name_tag_pb_rec fpga_spice/fpga_spice_utils.c /^void gen_spice_name_tag_pb_rec(t_pb* cur_pb,$/;" f +gen_spice_name_tags_all_pbs fpga_spice/fpga_spice_utils.c /^void gen_spice_name_tags_all_pbs() {$/;" f +gen_str_spice_model_structure fpga_spice/fpga_spice_utils.c /^char* gen_str_spice_model_structure(enum e_spice_model_structure spice_model_structure) {$/;" f +generate_lut_sram_bits fpga_spice/fpga_spice_utils.c /^int* generate_lut_sram_bits(int truth_table_len,$/;" f +generate_nets_sinks_prefer_sides clb_pin_remap/place_clb_pin_remap.c /^int generate_nets_sinks_prefer_sides(int n_nets, t_net* nets,$/;" f +generate_spice_basics spice/spice_subckt.c /^int generate_spice_basics(char* subckt_dir, t_spice spice) {$/;" f file: +generate_spice_logic_blocks spice/spice_pbtypes.c /^void generate_spice_logic_blocks(char* subckt_dir,$/;" f +generate_spice_luts spice/spice_lut.c /^void generate_spice_luts(char* subckt_dir, $/;" f +generate_spice_muxes spice/spice_mux.c /^void generate_spice_muxes(char* subckt_dir,$/;" f +generate_spice_nmos_pmos spice/spice_subckt.c /^int generate_spice_nmos_pmos(char* subckt_dir,$/;" f +generate_spice_routing_resources spice/spice_routing.c /^void generate_spice_routing_resources(char* subckt_dir,$/;" f +generate_spice_rram_veriloga spice/spice_subckt.c /^void generate_spice_rram_veriloga(char* subckt_dir, $/;" f +generate_spice_src_des_pb_graph_pin_prefix spice/spice_pbtypes.c /^void generate_spice_src_des_pb_graph_pin_prefix(t_pb_graph_node* src_pb_graph_node,$/;" f +generate_spice_subckt_powergated_tapbuf spice/spice_subckt.c /^void generate_spice_subckt_powergated_tapbuf(FILE* fp, $/;" f +generate_spice_subckt_tapbuf spice/spice_subckt.c /^void generate_spice_subckt_tapbuf(FILE* fp, $/;" f +generate_spice_subckts spice/spice_subckt.c /^void generate_spice_subckts(char* subckt_dir,$/;" f +generate_spice_wires spice/spice_subckt.c /^void generate_spice_wires(char* subckt_dir,$/;" f +generate_string_spice_model_type fpga_spice/fpga_spice_utils.c /^char* generate_string_spice_model_type(enum e_spice_model_type spice_model_type) {$/;" f +generate_verilog_src_des_pb_graph_pin_prefix syn_verilog/verilog_pbtypes.c /^void generate_verilog_src_des_pb_graph_pin_prefix(t_pb_graph_node* src_pb_graph_node,$/;" f +generic_compute_matrix place/timing_place_lookup.c /^static void generic_compute_matrix(float ***matrix_ptr, t_type_ptr source_type,$/;" f file: +getEchoEnabled base/ReadOptions.c /^boolean getEchoEnabled(void) {$/;" f +getEchoFileName base/ReadOptions.c /^char *getEchoFileName(enum e_echo_files echo_option) {$/;" f +getOutputFileName base/ReadOptions.c /^char *getOutputFileName(enum e_output_files ename) {$/;" f +get_array_size_of_molecule pack/cluster_placement.c /^int get_array_size_of_molecule(t_pack_molecule *molecule) {$/;" f +get_average_opin_delay route/rr_graph_indexed_data.c /^static float get_average_opin_delay(t_ivec *** L_rr_node_indices,$/;" f file: +get_bb_from_scratch place/place.c /^static void get_bb_from_scratch(int inet, struct s_bb *coords,$/;" f file: +get_bidir_opin_connections route/rr_graph2.c /^int get_bidir_opin_connections(INP int i, INP int j, INP int ipin,$/;" f +get_bidir_track_to_chan_seg route/rr_graph2.c /^static int get_bidir_track_to_chan_seg(INP struct s_ivec conn_tracks,$/;" f file: +get_blif_tok base/read_blif.c /^static void get_blif_tok(char *buffer, int doall, boolean *done,$/;" f file: +get_blk_pin_from_port_pin util/vpr_utils.c /^void get_blk_pin_from_port_pin(int blk_type_index, int port,int port_pin, $/;" f +get_block_center base/draw.c /^static void get_block_center(int bnum, float *x, float *y) {$/;" f file: +get_cblock_trans route/rr_graph_area.c /^static float get_cblock_trans(int *num_inputs_to_cblock, int* switches_to_cblock,$/;" f file: +get_chan_rr_node_coorindate_in_sb_info fpga_spice/fpga_spice_backannotate_utils.c /^void get_chan_rr_node_coorindate_in_sb_info(t_sb cur_sb_info,$/;" f +get_chan_rr_nodes fpga_spice/fpga_spice_backannotate_utils.c /^t_rr_node** get_chan_rr_nodes(int* num_chan_rr_nodes,$/;" f +get_channel_occupancy_stats base/stats.c /^static void get_channel_occupancy_stats(void) {$/;" f file: +get_child_pb_for_phy_pb_graph_node fpga_spice/fpga_spice_utils.c /^t_pb* get_child_pb_for_phy_pb_graph_node(t_pb* cur_pb, int ipb, int jpb) {$/;" f +get_class_range_for_block util/vpr_utils.c /^void get_class_range_for_block(INP int iblk, OUTP int *class_low,$/;" f +get_critical_path_delay timing/path_delay.c /^float get_critical_path_delay(void) {$/;" f +get_crossing_penalty clb_pin_remap/post_place_timing.c /^float get_crossing_penalty(int num_sinks) {$/;" f +get_default_spice_model fpga_spice/fpga_spice_utils.c /^t_spice_model* get_default_spice_model(enum e_spice_model_type default_spice_model_type,$/;" f +get_delay_normalization_fac route/rr_graph_indexed_data.c /^static float get_delay_normalization_fac(int nodes_per_chan,$/;" f file: +get_empty_buffer_plan_list mrfpga/buffer_insertion.c /^static t_buffer_plan_list get_empty_buffer_plan_list( )$/;" f file: +get_entry power/PowerSpicedComponent.c /^PowerCallibInputs * PowerSpicedComponent::get_entry(int num_inputs) {$/;" f class:PowerSpicedComponent +get_entry_bound power/PowerSpicedComponent.c /^PowerCallibInputs * PowerSpicedComponent::get_entry_bound(bool lower,$/;" f class:PowerSpicedComponent +get_entry_bound power/PowerSpicedComponent.c /^PowerCallibSize * PowerCallibInputs::get_entry_bound(bool lower,$/;" f class:PowerCallibInputs +get_escape_char timing/slre.c /^static int get_escape_char(const char **re) {$/;" f file: +get_expected_lowest_cost_primitive_for_logical_block pack/prepack.c /^static t_pb_graph_node *get_expected_lowest_cost_primitive_for_logical_block(INP int ilogical_block) {$/;" f file: +get_expected_lowest_cost_primitive_for_logical_block_in_pb_graph_node pack/prepack.c /^static t_pb_graph_node *get_expected_lowest_cost_primitive_for_logical_block_in_pb_graph_node(INP int ilogical_block, INP t_pb_graph_node *curr_pb_graph_node, OUTP float *cost) {$/;" f file: +get_expected_segs_to_target route/route_timing.c /^static int get_expected_segs_to_target(int inode, int target_node,$/;" f file: +get_first_pin place/timing_place_lookup.c /^static int get_first_pin(enum e_pin_type pintype, t_type_ptr type) {$/;" f file: +get_free_molecule_with_most_ext_inputs_for_cluster pack/cluster.c /^static t_pack_molecule *get_free_molecule_with_most_ext_inputs_for_cluster($/;" f file: +get_grid_block_subckt_name spice/spice_pbtypes.c /^char* get_grid_block_subckt_name(int x,$/;" f +get_grid_phy_block_subckt_name spice/spice_pbtypes.c /^char* get_grid_phy_block_subckt_name(int x, int y, int z,$/;" f +get_grid_pin_height fpga_spice/fpga_spice_utils.c /^int get_grid_pin_height(int grid_x, int grid_y, int pin_index) {$/;" f +get_grid_side_pin_rr_nodes fpga_spice/fpga_spice_backannotate_utils.c /^t_rr_node** get_grid_side_pin_rr_nodes(int* num_pin_rr_nodes,$/;" f +get_grid_side_pins route/rr_graph_opincb.c /^void get_grid_side_pins(int grid_x, int grid_y, $/;" f file: +get_grid_testbench_one_grid_num_sim_clock_cycles spice/spice_grid_testbench.c /^int get_grid_testbench_one_grid_num_sim_clock_cycles(FILE* fp, $/;" f +get_hash_entry util/hash.c /^get_hash_entry(struct s_hash **hash_table, char *name) {$/;" f +get_hash_stats util/hash.c /^void get_hash_stats(struct s_hash **hash_table, char *hash_table_name){$/;" f +get_heap_head route/route_common.c /^get_heap_head(void) {$/;" f +get_highest_gain_molecule pack/cluster.c /^static t_pack_molecule *get_highest_gain_molecule($/;" f file: +get_imacro_from_iblk place/place_macro.c /^void get_imacro_from_iblk(int * imacro, int iblk, t_pl_macro * macros, int num_macros) {$/;" f +get_init_buffer_plan mrfpga/buffer_insertion.c /^static t_buffer_plan get_init_buffer_plan( int inode, int num_pins, int* isink_to_inode )$/;" f file: +get_init_buffer_plan_list mrfpga/buffer_insertion.c /^static t_buffer_plan_list get_init_buffer_plan_list( int inode, int num_pins, int* isink_to_inode )$/;" f file: +get_int_list_length mrfpga/buffer_insertion.c /^static int get_int_list_length( t_linked_int* list )$/;" f file: +get_ipin_switch_index route/rr_graph_opincb.c /^int get_ipin_switch_index(t_rr_node* ipin) {$/;" f file: +get_keypress_input base/graphics.c /^static bool get_keypress_input, get_mouse_move_input;$/;" v file: +get_length_and_bends_stats base/stats.c /^void get_length_and_bends_stats(void) {$/;" f +get_longest_segment_length place/timing_place_lookup.c /^static int get_longest_segment_length($/;" f file: +get_lut_child_pb fpga_spice/fpga_spice_utils.c /^t_pb* get_lut_child_pb(t_pb* cur_lut_pb,$/;" f +get_lut_output_init_val fpga_spice/fpga_spice_utils.c /^int get_lut_output_init_val(t_logical_block* lut_logical_block) {$/;" f +get_max_depth_of_pb_graph_node pack/cluster_feasibility_filter.c /^static int get_max_depth_of_pb_graph_node(INP t_pb_graph_node *pb_graph_node) {$/;" f file: +get_max_depth_of_pb_type util/vpr_utils.c /^int get_max_depth_of_pb_type(t_pb_type *pb_type) {$/;" f +get_max_nets_in_pb_type util/vpr_utils.c /^int get_max_nets_in_pb_type(const t_pb_type *pb_type) {$/;" f +get_max_pins_per_net route/route_timing.c /^static int get_max_pins_per_net(void) {$/;" f file: +get_max_primitives_in_pb_type util/vpr_utils.c /^int get_max_primitives_in_pb_type(t_pb_type *pb_type) {$/;" f +get_mem_bank_info_reserved_blwl fpga_spice/fpga_spice_utils.c /^void get_mem_bank_info_reserved_blwl(t_mem_bank_info* cur_mem_bank_info,$/;" f +get_molecule_by_num_ext_inputs pack/cluster.c /^static t_pack_molecule *get_molecule_by_num_ext_inputs($/;" f file: +get_molecule_for_cluster pack/cluster.c /^static t_pack_molecule *get_molecule_for_cluster($/;" f file: +get_molecule_gain pack/cluster.c /^static float get_molecule_gain(t_pack_molecule *molecule, std::map &blk_gain) {$/;" f file: +get_most_critical_seed_molecule pack/cluster.c /^static t_pack_molecule* get_most_critical_seed_molecule(int * indexofcrit) {$/;" f file: +get_mouse_move_input base/graphics.c /^static bool get_keypress_input, get_mouse_move_input;$/;" v file: +get_mrfpga_switch_type mrfpga/mrfpga_api.c /^void get_mrfpga_switch_type(boolean is_from_sbox,$/;" f +get_net_corresponding_to_pb_graph_pin pack/cluster.c /^static int get_net_corresponding_to_pb_graph_pin(t_pb *cur_pb,$/;" f file: +get_net_cost place/place.c /^static float get_net_cost(int inet, struct s_bb *bbptr) {$/;" f file: +get_net_wirelength_estimate place/place.c /^static double get_net_wirelength_estimate(int inet, struct s_bb *bbptr) {$/;" f file: +get_next_hash util/hash.c /^get_next_hash(struct s_hash **hash_table, struct s_hash_iterator *hash_iterator) {$/;" f +get_next_primitive_list pack/cluster_placement.c /^boolean get_next_primitive_list($/;" f +get_non_updateable_bb place/place.c /^static void get_non_updateable_bb(int inet, struct s_bb *bb_coord_new) {$/;" f file: +get_num_bends_and_length base/stats.c /^void get_num_bends_and_length(int inet, int *bends_ptr, int *len_ptr,$/;" f +get_num_conn base/check_netlist.c /^static int get_num_conn(int bnum) {$/;" f file: +get_opin_direct_connecions route/rr_graph.c /^static int get_opin_direct_connecions(int x, int y, int opin, INOUTP t_linked_edge ** edge_list_ptr, INP t_ivec *** L_rr_node_indices, $/;" f file: +get_pb_graph_node_pin_from_block_pin util/vpr_utils.c /^t_pb_graph_pin* get_pb_graph_node_pin_from_block_pin(int iblock, int ipin) {$/;" f +get_pb_graph_node_pin_from_clb_net util/vpr_utils.c /^t_pb_graph_pin* get_pb_graph_node_pin_from_clb_net(int inet, int ipin) {$/;" f +get_pb_graph_node_pin_from_model_port_pin util/vpr_utils.c /^t_pb_graph_pin* get_pb_graph_node_pin_from_model_port_pin(t_model_ports *model_port, int model_pin, t_pb_graph_node *pb_graph_node) {$/;" f +get_pb_graph_node_pin_from_vpack_net util/vpr_utils.c /^t_pb_graph_pin* get_pb_graph_node_pin_from_vpack_net(int inet, int ipin) {$/;" f +get_pb_graph_pin_from_name pack/pb_type_graph.c /^static t_pb_graph_pin * get_pb_graph_pin_from_name(INP const char * port_name,$/;" f file: +get_port_pin_from_blk_pin util/vpr_utils.c /^void get_port_pin_from_blk_pin(int blk_type_index, int blk_pin, int * port,$/;" f +get_rr_cong_cost route/route_common.c /^float get_rr_cong_cost(int inode) {$/;" f +get_rr_node_index route/rr_graph2.c /^int get_rr_node_index(int x, int y, t_rr_type rr_type, int ptc,$/;" f +get_rr_node_index_in_cb_info fpga_spice/fpga_spice_backannotate_utils.c /^int get_rr_node_index_in_cb_info(t_rr_node* cur_rr_node,$/;" f +get_rr_node_index_in_sb_info fpga_spice/fpga_spice_backannotate_utils.c /^int get_rr_node_index_in_sb_info(t_rr_node* cur_rr_node,$/;" f +get_rr_node_net_density fpga_spice/fpga_spice_utils.c /^float get_rr_node_net_density(t_rr_node node) {$/;" f +get_rr_node_net_init_value fpga_spice/fpga_spice_utils.c /^int get_rr_node_net_init_value(t_rr_node node) {$/;" f +get_rr_node_net_probability fpga_spice/fpga_spice_utils.c /^float get_rr_node_net_probability(t_rr_node node) {$/;" f +get_rr_node_side_and_index_in_cb_info fpga_spice/fpga_spice_backannotate_utils.c /^void get_rr_node_side_and_index_in_cb_info(t_rr_node* cur_rr_node,$/;" f +get_rr_node_side_and_index_in_sb_info fpga_spice/fpga_spice_backannotate_utils.c /^void get_rr_node_side_and_index_in_sb_info(t_rr_node* cur_rr_node,$/;" f +get_rr_pin_draw_coords base/draw.c /^static void get_rr_pin_draw_coords(int inode, int iside, int ioff, float *xcen,$/;" f file: +get_sdc_tok timing/read_sdc.c /^static boolean get_sdc_tok(char * buf) {$/;" f file: +get_seed_logical_molecule_with_most_ext_inputs pack/cluster.c /^static t_pack_molecule* get_seed_logical_molecule_with_most_ext_inputs($/;" f file: +get_seg_end route/rr_graph2.c /^int get_seg_end(INP t_seg_details * seg_details, INP int itrack, INP int istart,$/;" f +get_seg_start route/rr_graph2.c /^int get_seg_start(INP t_seg_details * seg_details, INP int itrack,$/;" f +get_seg_track_counts route/rr_graph2.c /^get_seg_track_counts(INP int num_sets, INP int num_seg_types,$/;" f file: +get_segment_usage_stats route/segment_stats.c /^void get_segment_usage_stats(int num_segment, t_segment_inf * segment_inf) {$/;" f +get_serial_num route/route_common.c /^void get_serial_num(void) {$/;" f +get_simple_switch_block_track route/rr_graph_sbox.c /^int get_simple_switch_block_track(INP enum e_side from_side,$/;" f +get_sram_orgz_info_mem_model fpga_spice/fpga_spice_utils.c /^void get_sram_orgz_info_mem_model(t_sram_orgz_info* cur_sram_orgz_info,$/;" f +get_sram_orgz_info_num_blwl fpga_spice/fpga_spice_utils.c /^void get_sram_orgz_info_num_blwl(t_sram_orgz_info* cur_sram_orgz_info,$/;" f +get_sram_orgz_info_num_mem_bit fpga_spice/fpga_spice_utils.c /^int get_sram_orgz_info_num_mem_bit(t_sram_orgz_info* cur_sram_orgz_info) {$/;" f +get_sram_orgz_info_reserved_blwl fpga_spice/fpga_spice_utils.c /^void get_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info,$/;" f +get_start_end_points_one_macro place/place_macro.c /^void get_start_end_points_one_macro(t_pl_macro pl_macro,$/;" f +get_std_dev place/place.c /^static double get_std_dev(int n, double sum_x_squared, double av_x) {$/;" f file: +get_switch_info pack/pack.c /^float get_switch_info(short switch_index, float &Tdel_switch, float &R_switch, float &Cout_switch) {$/;" f +get_switch_type route/rr_graph2.c /^static void get_switch_type(boolean is_from_sbox, boolean is_to_sbox,$/;" f file: +get_timing_driven_expected_cost route/route_timing.c /^static float get_timing_driven_expected_cost(int inode, int target_node,$/;" f file: +get_tnode_block_and_output_net timing/path_delay.c /^void get_tnode_block_and_output_net(int inode, int *iblk_ptr, int *inet_ptr) {$/;" f +get_tnode_index timing/path_delay.c /^static inline int get_tnode_index(t_tnode * node) {$/;" f file: +get_top_of_heap_index util/heapsort.c /^static int get_top_of_heap_index(int *heap, float *sort_values, int heap_tail,$/;" f file: +get_track_num base/draw.c /^static int get_track_num(int inode, int **chanx_track, int **chany_track) {$/;" f file: +get_track_to_ipins route/rr_graph2.c /^int get_track_to_ipins(int seg, int chan, int track,$/;" f +get_track_to_tracks route/rr_graph2.c /^int get_track_to_tracks(INP int from_chan, INP int from_seg, INP int from_track,$/;" f +get_unidir_opin_connections route/rr_graph2.c /^int get_unidir_opin_connections(INP int chan, INP int seg, INP int Fc,$/;" f +get_unidir_track_to_chan_seg route/rr_graph2.c /^static int get_unidir_track_to_chan_seg(INP boolean is_end_sb,$/;" f file: +getcolor base/graphics.c /^int getcolor (void) { return 0; }$/;" f +getcolor base/graphics.c /^int getcolor() {$/;" f +gio_inout_prefix fpga_spice/fpga_spice_globals.c /^char* gio_inout_prefix = "gfpga_pad_";$/;" v +gl_state base/graphics.c /^static t_gl_state gl_state = {false, SCREEN, 0};$/;" v file: +global_clocks base/ReadOptions.h /^ boolean global_clocks;$/;" m struct:s_options +global_clocks base/vpr_types.h /^ boolean global_clocks;$/;" m struct:s_packer_opts +global_ports_head fpga_spice/fpga_spice_globals.c /^t_llist* global_ports_head = NULL;$/;" v +global_route_switch base/vpr_types.h /^ short global_route_switch;$/;" m struct:s_det_routing_arch +gr_automode base/draw.c /^static int gr_automode; \/* Need user input after: 0: each t, *$/;" v file: +grid base/globals.c /^struct s_grid_tile **grid = NULL; \/* [0..(nx+1)][0..(ny+1)] Physical block list *\/$/;" v typeref:struct:s_grid_tile +grid base/globals_declare.h /^struct s_grid_tile **grid;$/;" v typeref:struct:s_grid_tile +grid_backup place/timing_place_lookup.c /^static struct s_grid_tile **grid_backup;$/;" v typeref:struct:s_grid_tile file: +grid_conf_bits_lsb ../../libarchfpga/fpga_spice_include/spice_types.h /^ int** grid_conf_bits_lsb;$/;" m struct:s_sram_orgz_info +grid_conf_bits_msb ../../libarchfpga/fpga_spice_include/spice_types.h /^ int** grid_conf_bits_msb;$/;" m struct:s_sram_orgz_info +grid_index_high ../../libarchfpga/fpga_spice_include/spice_types.h /^ int** grid_index_high;$/;" m struct:s_spice_model +grid_index_low ../../libarchfpga/fpga_spice_include/spice_types.h /^ int** grid_index_low;$/;" m struct:s_spice_model +grid_loc_def ../../libarchfpga/include/physical_types.h /^ struct s_grid_loc_def *grid_loc_def; \/* [0..num_def-1] *\/$/;" m struct:s_type_descriptor typeref:struct:s_type_descriptor::s_grid_loc_def +grid_loc_type ../../libarchfpga/include/physical_types.h /^ enum e_grid_loc_type grid_loc_type;$/;" m struct:s_grid_loc_def typeref:enum:s_grid_loc_def::e_grid_loc_type +grid_logic_tile_area ../../libarchfpga/include/physical_types.h /^ float grid_logic_tile_area;$/;" m struct:s_arch +grid_logic_tile_area base/globals.c /^float grid_logic_tile_area = 0;$/;" v +grid_reserved_conf_bits ../../libarchfpga/fpga_spice_include/spice_types.h /^ int** grid_reserved_conf_bits;$/;" m struct:s_sram_orgz_info +group_size base/vpr_types.h /^ int group_size;$/;" m struct:s_seg_details +group_start base/vpr_types.h /^ int group_start;$/;" m struct:s_seg_details +hAllObjtestDC base/graphics.c /^hObjtestDC, hAllObjtestDC; \/* object test *\/$/;" v file: +hBackgroundDC base/graphics.c /^static HDC hGraphicsDC, hForegroundDC, hBackgroundDC,$/;" v file: +hButtonsWnd base/graphics.c /^static HWND hMainWnd, hGraphicsWnd, hButtonsWnd, hStatusWnd;$/;" v file: +hCurrentDC base/graphics.c /^hCurrentDC, \/* WC : double-buffer *\/$/;" v file: +hForegroundDC base/graphics.c /^static HDC hGraphicsDC, hForegroundDC, hBackgroundDC,$/;" v file: +hGraphicsBrush base/graphics.c /^static HBRUSH hGraphicsBrush, hGrayBrush;$/;" v file: +hGraphicsDC base/graphics.c /^static HDC hGraphicsDC, hForegroundDC, hBackgroundDC,$/;" v file: +hGraphicsFont base/graphics.c /^static HFONT hGraphicsFont;$/;" v file: +hGraphicsPen base/graphics.c /^static HPEN hGraphicsPen;$/;" v file: +hGraphicsWnd base/graphics.c /^static HWND hMainWnd, hGraphicsWnd, hButtonsWnd, hStatusWnd;$/;" v file: +hGrayBrush base/graphics.c /^static HBRUSH hGraphicsBrush, hGrayBrush;$/;" v file: +hMainWnd base/graphics.c /^static HWND hMainWnd, hGraphicsWnd, hButtonsWnd, hStatusWnd;$/;" v file: +hObjtestDC base/graphics.c /^hObjtestDC, hAllObjtestDC; \/* object test *\/$/;" v file: +hStatusWnd base/graphics.c /^static HWND hMainWnd, hGraphicsWnd, hButtonsWnd, hStatusWnd;$/;" v file: +h_ptr util/hash.h /^ struct s_hash *h_ptr;$/;" m struct:s_hash_iterator typeref:struct:s_hash_iterator::s_hash +hack_switch_to_rram base/SetupVPR.c /^static void hack_switch_to_rram(struct s_det_routing_arch *det_routing_arch) {$/;" f file: +has_printhandler_pre_vpr base/vpr_api.c /^static boolean has_printhandler_pre_vpr = FALSE;$/;" v file: +has_valid_T_arr timing/path_delay.c /^static inline boolean has_valid_T_arr(int inode) {$/;" f file: +has_valid_T_req timing/path_delay.c /^static inline boolean has_valid_T_req(int inode) {$/;" f file: +has_valid_normalized_T_arr timing/path_delay.c /^boolean has_valid_normalized_T_arr(int inode) {$/;" f +hash_value util/hash.c /^int hash_value(char *name) {$/;" f +heap route/route_common.c /^static struct s_heap **heap; \/* Indexed from [1..heap_size] *\/$/;" v typeref:struct:s_heap file: +heap_ch route/route_common.c /^static t_chunk heap_ch = {NULL, 0, NULL};$/;" v file: +heap_free_head route/route_common.c /^static struct s_heap *heap_free_head = NULL;$/;" v typeref:struct:s_heap file: +heap_size route/route_common.c /^static int heap_size; \/* Number of slots in the heap array *\/$/;" v file: +heap_tail route/route_common.c /^static int heap_tail; \/* Index of first unused slot in the heap array *\/$/;" v file: +heapsort util/heapsort.c /^void heapsort(int *sort_index, float *sort_values, int nelem, int start_index) {$/;" f +height ../../libarchfpga/include/physical_types.h /^ int height;$/;" m struct:s_type_descriptor +height base/graphics.c /^ int height; $/;" m struct:__anon4 file: +highlight_blocks base/draw.c /^static void highlight_blocks(float x, float y) {$/;" f file: +highlight_crit_path base/draw.c /^static void highlight_crit_path(void (*drawscreen_ptr)(void)) {$/;" f file: +highlight_nets base/draw.c /^static void highlight_nets(char *message) {$/;" f file: +highlight_rr_nodes base/draw.c /^static void highlight_rr_nodes(float x, float y) {$/;" f file: +hill_climbing_flag base/ReadOptions.h /^ boolean hill_climbing_flag;$/;" m struct:s_options +hill_climbing_flag base/vpr_types.h /^ boolean hill_climbing_flag;$/;" m struct:s_packer_opts +hillgain base/vpr_types.h /^ std::map hillgain;$/;" m struct:s_pb_stats +hwnd base/graphics.c /^ HWND hwnd;$/;" m struct:__anon4 file: +i util/hash.h /^ int i;$/;" m struct:s_hash_iterator +i_ds power/power.h /^ float i_ds;$/;" m struct:s_power_nmos_leakage_pair +iblock base/vpr_types.h /^ int iblock;$/;" m struct:s_trace +identify_rr_node_driver_switch fpga_spice/fpga_spice_backannotate_utils.c /^void identify_rr_node_driver_switch(t_det_routing_arch RoutingArch,$/;" f file: +idle_mode_name ../../libarchfpga/include/physical_types.h /^ char* idle_mode_name;$/;" m struct:s_pb_type +ilines base/read_blif.c /^static int ilines, olines, model_lines, endlines;$/;" v file: +in_dens power/power.h /^ float * in_dens; \/* Switching density of inputs *\/$/;" m struct:s_rr_node_power +in_flight base/vpr_types.h /^ t_cluster_placement_primitive *in_flight; \/* ptrs to primitives currently being considered *\/$/;" m struct:s_cluster_placement_stats +in_prob power/power.h /^ float * in_prob; \/* Static probability of inputs *\/$/;" m struct:s_rr_node_power +include_dir base/vpr_types.h /^ char* include_dir;$/;" m struct:s_spice_opts +include_netlist ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_netlist* include_netlist;$/;" m struct:s_spice_model +include_netlists ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_netlist* include_netlists; $/;" m struct:s_spice +included ../../libarchfpga/fpga_spice_include/spice_types.h /^ int included;$/;" m struct:s_spice_model_netlist +incremental_cost ../../libarchfpga/include/cad_types.h /^ float incremental_cost; \/* cost dependant on current status of packing *\/$/;" m struct:s_cluster_placement_primitive +index ../../libarchfpga/fpga_spice_include/spice_types.h /^ int index;$/;" m struct:s_conf_bit_info +index ../../libarchfpga/include/cad_types.h /^ int index; \/* array index for pattern*\/$/;" m struct:s_pack_patterns +index ../../libarchfpga/include/logic_types.h /^ int index; \/* indexing for array look-up *\/$/;" m struct:s_model_ports +index ../../libarchfpga/include/logic_types.h /^ int index;$/;" m struct:s_model +index ../../libarchfpga/include/physical_types.h /^ int index; \/* index of type descriptor in array (allows for index referencing) *\/$/;" m struct:s_type_descriptor +index ../../libarchfpga/include/physical_types.h /^ int index;$/;" m struct:s_mode +index ../../libarchfpga/include/physical_types.h /^ int index;$/;" m struct:s_port +index base/vpr_types.h /^ int index; \/* Index in array that this block can be found *\/$/;" m struct:s_logical_block +index base/vpr_types.h /^ int index;$/;" m struct:s_seg_details +index base/vpr_types.h /^ int index;$/;" m struct:s_trace +index route/route_common.h /^ int index;$/;" m struct:s_heap +index util/hash.h /^ int index;$/;" m struct:s_hash +index_in_top_tb ../../libarchfpga/fpga_spice_include/spice_types.h /^ int index_in_top_tb;$/;" m struct:s_conf_bit_info +infer_annotations ../../libarchfpga/include/physical_types.h /^ boolean infer_annotations;$/;" m struct:s_interconnect +infer_pattern ../../libarchfpga/include/physical_types.h /^ boolean infer_pattern; \/*If TRUE, infer pattern based on patterns connected to it*\/$/;" m struct:s_pb_graph_edge +init_and_check_one_sram_inf_orgz fpga_spice/fpga_spice_setup.c /^void init_and_check_one_sram_inf_orgz(t_sram_inf_orgz* cur_sram_inf_orgz,$/;" f file: +init_and_check_sram_inf fpga_spice/fpga_spice_setup.c /^void init_and_check_sram_inf(t_arch* arch,$/;" f file: +init_arch_mrfpga ../../libarchfpga/read_xml_mrfpga.c /^void init_arch_mrfpga(t_arch_mrfpga* arch_mrfpga) {$/;" f +init_buffer_inf ../../libarchfpga/read_xml_mrfpga.c /^void init_buffer_inf(t_buffer_inf* buffer_inf) {$/;" f +init_chan base/place_and_route.c /^void init_chan(int cfactor, t_chan_width_dist chan_width_dist) {$/;" f +init_chan_seg_detail_params route/rr_graph_swseg.c /^static int init_chan_seg_detail_params(INP char* chan_type,$/;" f file: +init_check_arch_spice_models fpga_spice/fpga_spice_setup.c /^void init_check_arch_spice_models(t_arch* arch,$/;" f +init_draw_coords base/draw.c /^void init_draw_coords(float width_val) {$/;" f +init_graphics base/graphics.c /^init_graphics (const char *window_name, int cindex) $/;" f +init_graphics base/graphics.c /^void init_graphics (const char *window_name, int cindex) { }$/;" f +init_grids_num_conf_bits fpga_spice/fpga_spice_utils.c /^void init_grids_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info) {$/;" f +init_grids_num_iopads fpga_spice/fpga_spice_utils.c /^void init_grids_num_iopads() {$/;" f +init_grids_num_mode_bits fpga_spice/fpga_spice_utils.c /^void init_grids_num_mode_bits() {$/;" f +init_include_user_defined_netlists spice/spice_utils.c /^void init_include_user_defined_netlists(t_spice spice) {$/;" f +init_include_user_defined_verilog_netlists syn_verilog/verilog_utils.c /^void init_include_user_defined_verilog_netlists(t_spice spice) {$/;" f +init_list_include_netlists spice/spice_api.c /^void init_list_include_netlists(t_spice* spice) { $/;" f file: +init_list_include_verilog_netlists syn_verilog/verilog_utils.c /^void init_list_include_verilog_netlists(t_spice* spice) { $/;" f +init_llist_global_ports fpga_spice/fpga_spice_setup.c /^t_llist* init_llist_global_ports(t_spice* spice) {$/;" f file: +init_llist_verilog_and_spice_syntax_char fpga_spice/fpga_spice_setup.c /^t_llist* init_llist_verilog_and_spice_syntax_char() {$/;" f file: +init_logical_block_spice_model_temp_used spice/spice_utils.c /^void init_logical_block_spice_model_temp_used(t_spice_model* spice_model) {$/;" f +init_logical_block_spice_model_type_temp_used spice/spice_utils.c /^void init_logical_block_spice_model_type_temp_used(int num_spice_models, t_spice_model* spice_model,$/;" f +init_mem_bank_info fpga_spice/fpga_spice_utils.c /^void init_mem_bank_info(t_mem_bank_info* cur_mem_bank_info,$/;" f +init_memristor_inf ../../libarchfpga/read_xml_mrfpga.c /^void init_memristor_inf(t_memristor_inf* memristor_inf) {$/;" f +init_mux_arch_default power/power_util.c /^static void init_mux_arch_default(t_mux_arch * mux_arch, int levels,$/;" f file: +init_one_cb_info fpga_spice/fpga_spice_backannotate_utils.c /^void init_one_cb_info(t_cb* cur_cb) { $/;" f +init_one_grid_num_conf_bits fpga_spice/fpga_spice_utils.c /^void init_one_grid_num_conf_bits(int ix, int iy, $/;" f +init_one_grid_num_iopads fpga_spice/fpga_spice_utils.c /^void init_one_grid_num_iopads(int ix, int iy) {$/;" f +init_one_grid_num_mode_bits fpga_spice/fpga_spice_utils.c /^void init_one_grid_num_mode_bits(int ix, int iy) {$/;" f +init_one_sb_info fpga_spice/fpga_spice_backannotate_utils.c /^void init_one_sb_info(t_sb* cur_sb) { $/;" f +init_parse base/read_blif.c /^static void init_parse(int doall) {$/;" f file: +init_postscript base/graphics.c /^int init_postscript (const char *fname) $/;" f +init_postscript base/graphics.c /^int init_postscript (const char *fname) { $/;" f +init_reserved_syntax_char fpga_spice/fpga_spice_utils.c /^void init_reserved_syntax_char(t_reserved_syntax_char* cur_reserved_syntax_char,$/;" f +init_route_structs route/route_common.c /^void init_route_structs(int bb_factor) {$/;" f +init_route_tree_to_source route/route_tree_timing.c /^init_route_tree_to_source(int inet) {$/;" f +init_rr_nodes_vpack_net_num_changed fpga_spice/fpga_spice_utils.c /^void init_rr_nodes_vpack_net_num_changed(int LL_num_rr_nodes,$/;" f +init_scff_info fpga_spice/fpga_spice_utils.c /^void init_scff_info(t_scff_info* cur_scff_info,$/;" f +init_spice_grid_testbench_globals spice/spice_grid_testbench.c /^void init_spice_grid_testbench_globals(t_spice spice) {$/;" f file: +init_spice_hardlogic_testbench_globals spice/spice_hardlogic_testbench.c /^void init_spice_hardlogic_testbench_globals(t_spice spice) {$/;" f file: +init_spice_lut_testbench_globals spice/spice_lut_testbench.c /^void init_spice_lut_testbench_globals(t_spice spice) {$/;" f file: +init_spice_models_grid_tb_cnt fpga_spice/fpga_spice_utils.c /^void init_spice_models_grid_tb_cnt(int num_spice_models,$/;" f +init_spice_models_tb_cnt fpga_spice/fpga_spice_utils.c /^void init_spice_models_tb_cnt(int num_spice_models,$/;" f +init_spice_mux_arch fpga_spice/fpga_spice_utils.c /^void init_spice_mux_arch(t_spice_model* spice_model,$/;" f +init_spice_mux_testbench_globals spice/spice_mux_testbench.c /^static void init_spice_mux_testbench_globals(t_spice spice) {$/;" f file: +init_spice_net_info fpga_spice/fpga_spice_utils.c /^void init_spice_net_info(t_spice_net_info* spice_net_info) {$/;" f +init_spice_routing_testbench_globals spice/spice_routing_testbench.c /^static void init_spice_routing_testbench_globals(t_spice spice) {$/;" f file: +init_sram_orgz_info fpga_spice/fpga_spice_utils.c /^void init_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info,$/;" f +init_standalone_sram_info fpga_spice/fpga_spice_utils.c /^void init_standalone_sram_info(t_standalone_sram_info* cur_standalone_sram_info,$/;" f +init_t base/vpr_types.h /^ float init_t;$/;" m struct:s_annealing_sched +init_val ../../libarchfpga/fpga_spice_include/spice_types.h /^ int init_val;$/;" m struct:s_spice_net_info +init_val base/vpr_types.h /^ int init_val;$/;" m struct:s_logical_block +init_world base/graphics.c /^init_world (float x1, float y1, float x2, float y2) $/;" f +init_world base/graphics.c /^void init_world (float xl, float yt, float xr, float yb) { }$/;" f +initial_placement place/place.c /^static void initial_placement(enum e_pad_loc_type pad_loc_type,$/;" f file: +initial_placement_blocks place/place.c /^static void initial_placement_blocks(int * free_locations, enum e_pad_loc_type pad_loc_type) {$/;" f file: +initial_placement_pl_macros place/place.c /^static void initial_placement_pl_macros(int macros_max_num_tries, int * free_locations) {$/;" f file: +initial_pres_fac base/ReadOptions.h /^ float initial_pres_fac;$/;" m struct:s_options +initial_pres_fac base/vpr_types.h /^ float initial_pres_fac;$/;" m struct:s_router_opts +initialized base/graphics.c /^ bool initialized;$/;" m struct:__anon5 file: +inner_loop_recompute_divider base/ReadOptions.h /^ int inner_loop_recompute_divider;$/;" m struct:s_options +inner_loop_recompute_divider base/vpr_types.h /^ int inner_loop_recompute_divider;$/;" m struct:s_placer_opts +inner_num base/vpr_types.h /^ float inner_num;$/;" m struct:s_annealing_sched +inode route/route_tree_timing.h /^ int inode;$/;" m struct:s_rt_node +inode timing/net_delay_types.h /^ int inode;$/;" m struct:s_rc_node +inode_head mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan {t_linked_int* inode_head; t_linked_int* sink_head; float* sink_delay; float C_downstream; float Tdel;} t_buffer_plan;$/;" m struct:s_buffer_plan file: +inport_link_pin ../../libarchfpga/include/cad_types.h /^ int inport_link_pin; \/* applicable pin of chain input port *\/$/;" m struct:s_model_chain_pattern +input_buffer ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_buffer* input_buffer;$/;" m struct:s_spice_model +input_edges ../../libarchfpga/include/physical_types.h /^ struct s_pb_graph_edge** input_edges; \/* [0..num_input_edges] *\/$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_edge +input_level ../../libarchfpga/fpga_spice_include/spice_types.h /^ int* input_level; \/* [0...num_input] *\/$/;" m struct:s_spice_mux_arch +input_link_port ../../libarchfpga/include/cad_types.h /^ t_model_ports *input_link_port; \/* pointer to port of chain input *\/$/;" m struct:s_model_chain_pattern +input_net_tnodes base/vpr_types.h /^ struct s_tnode ***input_net_tnodes; \/* [0..num_input_ports-1][0..num_pins -1] correspnding input net tnode *\/$/;" m struct:s_logical_block typeref:struct:s_logical_block::s_tnode +input_nets base/vpr_types.h /^ int **input_nets; \/* [0..num_input_ports-1][0..num_port_pins-1] List of input nets connected to this logical_block. *\/$/;" m struct:s_logical_block +input_offset ../../libarchfpga/fpga_spice_include/spice_types.h /^ int* input_offset; \/* [0...num_input] *\/ $/;" m struct:s_spice_mux_arch +input_pin_class_size ../../libarchfpga/include/physical_types.h /^ int *input_pin_class_size; \/* Stores the number of pins that belong to a particular input pin class *\/$/;" m struct:s_pb_graph_node +input_pins ../../libarchfpga/include/physical_types.h /^ char * input_pins;$/;" m struct:s_pin_to_pin_annotation +input_pins ../../libarchfpga/include/physical_types.h /^ struct s_pb_graph_pin *** input_pins; \/\/ [0..num_input_ports-1][0..num_pins_per_port-1]$/;" m struct:s_interconnect_pins typeref:struct:s_interconnect_pins::s_pb_graph_pin +input_pins ../../libarchfpga/include/physical_types.h /^ t_pb_graph_pin **input_pins; \/* [0..num_input_ports-1] [0..num_port_pins-1]*\/$/;" m struct:s_pb_graph_node +input_pins ../../libarchfpga/include/physical_types.h /^ t_pb_graph_pin **input_pins;$/;" m struct:s_pb_graph_edge +input_pins_used base/vpr_types.h /^ int **input_pins_used; \/* [0..pb_graph_node->num_pin_classes-1][0..pin_class_size] number of input pins of this class that are used *\/$/;" m struct:s_pb_stats +input_ports_eq_auto_detect ../../libarchfpga/include/physical_types.h /^ boolean input_ports_eq_auto_detect;$/;" m struct:s_type_descriptor +input_slew_fall_time ../../libarchfpga/fpga_spice_include/spice_types.h /^ float input_slew_fall_time; $/;" m struct:s_spice_stimulate_params +input_slew_fall_type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type input_slew_fall_type;$/;" m struct:s_spice_stimulate_params typeref:enum:s_spice_stimulate_params::e_spice_accuracy_type +input_slew_rise_time ../../libarchfpga/fpga_spice_include/spice_types.h /^ float input_slew_rise_time; $/;" m struct:s_spice_stimulate_params +input_slew_rise_type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type input_slew_rise_type;$/;" m struct:s_spice_stimulate_params typeref:enum:s_spice_stimulate_params::e_spice_accuracy_type +input_string ../../libarchfpga/include/physical_types.h /^ char *input_string;$/;" m struct:s_interconnect +input_thres_pct_fall ../../libarchfpga/fpga_spice_include/spice_types.h /^ float input_thres_pct_fall;$/;" m struct:s_spice_meas_params +input_thres_pct_rise ../../libarchfpga/fpga_spice_include/spice_types.h /^ float input_thres_pct_rise;$/;" m struct:s_spice_meas_params +inputs ../../libarchfpga/include/logic_types.h /^ t_model_ports *inputs; \/* linked list of input\/clock ports *\/$/;" m struct:s_model +inputs_per_cluster base/ReadOptions.h /^ int inputs_per_cluster;$/;" m struct:s_options +insert_buffer mrfpga/buffer_insertion.c /^static t_buffer_plan_list insert_buffer( t_buffer_plan_list list, int inode, float C, float R, float Tdel, int num_pins )$/;" f file: +insert_buffer_plan_to_list mrfpga/buffer_insertion.c /^static t_buffer_plan_list insert_buffer_plan_to_list( t_buffer_plan plan, t_buffer_plan_list list ) {$/;" f file: +insert_in_edge_list route/rr_graph_util.c /^insert_in_edge_list(INP t_linked_edge * head, INP int edge, INP short iswitch) {$/;" f +insert_in_hash_table util/hash.c /^insert_in_hash_table(struct s_hash **hash_table, char *name,$/;" f +insert_in_int_list ../../libarchfpga/util.c /^insert_in_int_list(t_linked_int * head, int data,$/;" f +insert_in_int_list2 mrfpga/mrfpga_util.c /^t_linked_int* insert_in_int_list2 (t_linked_int *head, int data )$/;" f +insert_in_vptr_list ../../libarchfpga/util.c /^insert_in_vptr_list(struct s_linked_vptr *head, void *vptr_to_add) {$/;" f +insert_llist_node ../../libarchfpga/linkedlist.c /^t_llist* insert_llist_node(t_llist* cur) {$/;" f +insert_llist_node_before_head ../../libarchfpga/linkedlist.c /^t_llist* insert_llist_node_before_head(t_llist* old_head) {$/;" f +insert_node_to_int_list ../../libarchfpga/util.c /^insert_node_to_int_list(struct s_linked_int *head, int int_to_add) {$/;" f +insert_switch_to_buffer_list mrfpga/buffer_insertion.c /^static void insert_switch_to_buffer_list( t_buffer_plan_list list, struct s_switch_inf switch_inf_local)$/;" f file: +insert_switch_to_buffer_plan mrfpga/buffer_insertion.c /^static t_buffer_plan insert_switch_to_buffer_plan( t_buffer_plan plan, struct s_switch_inf switch_inf_local)$/;" f file: +insert_to_linked_list base/verilog_writer.c /^pb_list *insert_to_linked_list(t_pb *pb_new , pb_list *list)$/;" f +insert_to_linked_list_conn base/verilog_writer.c /^conn_list *insert_to_linked_list_conn(t_pb *driver_new , t_pb *load_new , t_pb_graph_pin *driver_pin_ , t_pb_graph_pin *load_pin_ , float path_delay , conn_list *list)$/;" f +insert_wire_to_buffer_list mrfpga/buffer_insertion.c /^static void insert_wire_to_buffer_list( t_buffer_plan_list list, float C,float R )$/;" f file: +insert_wire_to_buffer_plan mrfpga/buffer_insertion.c /^static t_buffer_plan insert_wire_to_buffer_plan( t_buffer_plan plan, float C, float R )$/;" f file: +instances ../../libarchfpga/include/logic_types.h /^ void *instances;$/;" m struct:s_model +instantiate_SDF_header base/verilog_writer.c /^void instantiate_SDF_header(FILE *SDF)$/;" f +instantiate_input_interconnect base/verilog_writer.c /^void instantiate_input_interconnect(FILE *verilog , FILE *SDF , char *clock_name)$/;" f +instantiate_interconnect base/verilog_writer.c /^void instantiate_interconnect(FILE *verilog , int block_num , t_pb *pb , FILE *SDF)$/;" f +instantiate_primitive_modules base/verilog_writer.c /^void instantiate_primitive_modules(FILE *fp, char *clock_name , FILE *SDF)$/;" f +instantiate_top_level_module base/verilog_writer.c /^void instantiate_top_level_module(FILE *verilog)$/;" f +instantiate_wires base/verilog_writer.c /^void instantiate_wires(FILE *verilog)$/;" f +int_2_binary_str power/power_util.c /^static void int_2_binary_str(char * binary_str, int value, int str_length) {$/;" f file: +inter_cluster_net_delay base/ReadOptions.h /^ float inter_cluster_net_delay;$/;" m struct:s_options +inter_cluster_net_delay base/vpr_types.h /^ float inter_cluster_net_delay;$/;" m struct:s_packer_opts +interconnect ../../libarchfpga/include/physical_types.h /^ t_interconnect * interconnect;$/;" m struct:s_interconnect_pins +interconnect ../../libarchfpga/include/physical_types.h /^ t_interconnect * interconnect;$/;" m struct:s_pb_graph_edge +interconnect ../../libarchfpga/include/physical_types.h /^ t_interconnect *interconnect;$/;" m struct:s_mode +interconnect_pins ../../libarchfpga/include/physical_types.h /^ t_interconnect_pins ** interconnect_pins; \/* [0..num_modes-1][0..num_interconnect_in_mode] *\/$/;" m struct:s_pb_graph_node +interconnect_power ../../libarchfpga/include/physical_types.h /^ t_interconnect_power * interconnect_power;$/;" m struct:s_interconnect +interconnect_printing base/verilog_writer.c /^void interconnect_printing(FILE *fp , conn_list *downhill)$/;" f +interconnect_type_name power/power_util.c /^char * interconnect_type_name(enum e_interconnect type) {$/;" f +intra_cluster_net_delay base/ReadOptions.h /^ float intra_cluster_net_delay;$/;" m struct:s_options +intra_cluster_net_delay base/vpr_types.h /^ float intra_cluster_net_delay;$/;" m struct:s_packer_opts +inv_capacity base/vpr_types.h /^ float inv_capacity;$/;" m struct:s_place_region +inv_length base/vpr_types.h /^ float inv_length;$/;" m struct:s_rr_indexed_data +inv_spice_model ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model* inv_spice_model;$/;" m struct:s_spice_model_port +inv_spice_model_name ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* inv_spice_model_name;$/;" m struct:s_spice_model_port +invalid base/vpr_types.h /^ t_cluster_placement_primitive *invalid; \/* ptrs to primitives that are invalid *\/$/;" m struct:s_cluster_placement_stats +invalidate_heap_entries route/route_common.c /^void invalidate_heap_entries(int sink_node, int ipin_node) {$/;" f +invalidate_screen base/graphics.c /^static void invalidate_screen(void)$/;" f file: +io_line base/read_blif.c /^static void io_line(int in_or_out, int doall, t_model *io_model) {$/;" f file: +io_nmos_subckt_name spice/spice_globals.c /^char* io_nmos_subckt_name = "vpr_io_nmos";$/;" v +io_pmos_subckt_name spice/spice_globals.c /^char* io_pmos_subckt_name = "vpr_io_pmos";$/;" v +io_vdd ../../libarchfpga/fpga_spice_include/spice_types.h /^ float io_vdd;$/;" m struct:s_spice_tech_lib +iopad_spice_model spice/spice_globals.c /^t_spice_model* iopad_spice_model = NULL;$/;" v +iopad_verilog_model syn_verilog/verilog_global.c /^t_spice_model* iopad_verilog_model = NULL;$/;" v +ipin_mux_trans_size ../../libarchfpga/include/physical_types.h /^ float ipin_mux_trans_size;$/;" m struct:s_arch +ipin_mux_trans_size base/globals.c /^float ipin_mux_trans_size = 0;$/;" v +ipin_rr_node base/vpr_types.h /^ t_rr_node*** ipin_rr_node;$/;" m struct:s_cb +ipin_rr_node base/vpr_types.h /^ t_rr_node*** ipin_rr_node;$/;" m struct:s_sb +ipin_rr_node_grid_side base/vpr_types.h /^ int** ipin_rr_node_grid_side; \/* We need to record the side of a IPIN, because a IPIN may locate on more than one sides *\/$/;" m struct:s_cb +ipin_rr_node_grid_side base/vpr_types.h /^ int** ipin_rr_node_grid_side; \/* We need to record the side of a IPIN, because a IPIN may locate on more than one sides *\/$/;" m struct:s_sb +ipin_rr_nodes_vpack_net_num_changed fpga_spice/fpga_spice_backannotate_utils.c /^boolean ipin_rr_nodes_vpack_net_num_changed(int LL_num_rr_nodes,$/;" f file: +ipow ../../libarchfpga/util.c /^int ipow(int base, int exp) {$/;" f +isEchoFileEnabled base/ReadOptions.c /^boolean isEchoFileEnabled(enum e_echo_files echo_option) {$/;" f +isFixed base/vpr_types.h /^ boolean isFixed;$/;" m struct:s_block +is_Fc_frac ../../libarchfpga/include/physical_types.h /^ boolean *is_Fc_frac; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor +is_Fc_full_flex ../../libarchfpga/include/physical_types.h /^ boolean *is_Fc_full_flex; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor +is_accurate ../../libarchfpga/include/arch_types_mrfpga.h /^ boolean is_accurate;$/;" m struct:s_arch_mrfpga +is_any_but timing/slre.c /^static int is_any_but(const unsigned char *p, int len, const char *s,$/;" f file: +is_any_of timing/slre.c /^static int is_any_of(const unsigned char *p, int len, const char *s, int *ofs) {$/;" f file: +is_block_optional ../../libarchfpga/include/cad_types.h /^ boolean *is_block_optional; \/* [0..num_blocks-1] is the block_id in this pattern mandatory or optional to form a molecule *\/$/;" m struct:s_pack_patterns +is_cbox route/rr_graph2.c /^boolean is_cbox(INP int chan, INP int seg, INP int track,$/;" f +is_chain ../../libarchfpga/include/cad_types.h /^ boolean is_chain; \/* Does this pattern chain across logic blocks *\/$/;" m struct:s_pack_patterns +is_clock ../../libarchfpga/include/logic_types.h /^ boolean is_clock; \/* clock? *\/$/;" m struct:s_model_ports +is_clock ../../libarchfpga/include/physical_types.h /^ boolean is_clock;$/;" m struct:s_port +is_config_enable ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean is_config_enable;$/;" m struct:s_spice_model_port +is_const_gen base/vpr_types.h /^ boolean is_const_gen;$/;" m struct:s_net +is_default ../../libarchfpga/fpga_spice_include/spice_types.h /^ int is_default;$/;" m struct:s_spice_model +is_des_rr_node_in_src_rr_node_edges route/pb_pin_eq_auto_detect.c /^boolean is_des_rr_node_in_src_rr_node_edges(t_rr_node* src_rr_node,$/;" f +is_done_callibration power/PowerSpicedComponent.c /^bool PowerSpicedComponent::is_done_callibration(void) {$/;" f class:PowerSpicedComponent +is_empty_heap route/route_common.c /^boolean is_empty_heap(void) {$/;" f +is_forced_connection ../../libarchfpga/include/physical_types.h /^ boolean is_forced_connection; \/* This output pin connects to one and only one input pin *\/$/;" m struct:s_pb_graph_pin +is_forced_connection pack/cluster_feasibility_filter.c /^static boolean is_forced_connection(INP t_pb_graph_pin *pb_graph_pin) {$/;" f file: +is_global ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean is_global;$/;" m struct:s_spice_model_port +is_global base/globals_declare.h /^boolean *is_global;$/;" v +is_global base/vpr_types.h /^ boolean is_global;$/;" m struct:s_net +is_global_pin ../../libarchfpga/include/physical_types.h /^ boolean *is_global_pin; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor +is_in_heap base/vpr_types.h /^ boolean is_in_heap;$/;" m struct:s_rr_node +is_isolation ../../libarchfpga/include/arch_types_mrfpga.h /^ boolean is_isolation;$/;" m struct:s_arch_mrfpga +is_isolation mrfpga/mrfpga_globals.c /^boolean is_isolation = FALSE;$/;" v +is_junction ../../libarchfpga/include/arch_types_mrfpga.h /^ boolean is_junction;$/;" m struct:s_arch_mrfpga +is_junction mrfpga/mrfpga_globals.c /^boolean is_junction = FALSE;$/;" v +is_logical_blk_in_pb pack/cluster.c /^static boolean is_logical_blk_in_pb(int iblk, t_pb *pb) {$/;" f file: +is_mrFPGA ../../libarchfpga/include/arch_types_mrfpga.h /^ boolean is_mrFPGA;$/;" m struct:s_arch_mrfpga +is_mrFPGA mrfpga/mrfpga_globals.c /^boolean is_mrFPGA = FALSE;$/;" v +is_net_in_cluster pack/cluster_legality.c /^static boolean is_net_in_cluster(INP int inet) {$/;" f file: +is_net_pi fpga_spice/fpga_spice_utils.c /^boolean is_net_pi(t_net* cur_net) {$/;" f +is_netlist_clock base/vpr_types.h /^ boolean is_netlist_clock; \/* Is this a netlist or virtual (external) clock? *\/$/;" m struct:s_clock +is_non_clock_global ../../libarchfpga/include/logic_types.h /^ boolean is_non_clock_global; \/* not a clock but is a special, global, control signal (eg global asynchronous reset, etc) *\/$/;" m struct:s_model_ports +is_non_clock_global ../../libarchfpga/include/physical_types.h /^ boolean is_non_clock_global;$/;" m struct:s_port +is_number timing/read_sdc.c /^static boolean is_number(char * ptr) {$/;" f file: +is_opin util/vpr_utils.c /^boolean is_opin(int ipin, t_type_ptr type) {$/;" f +is_opin_cblock_defined ../../libarchfpga/include/arch_types_mrfpga.h /^ int is_opin_cblock_defined;$/;" m struct:s_arch_mrfpga +is_opin_in_direct_list route/pb_pin_eq_auto_detect.c /^boolean is_opin_in_direct_list(t_type_ptr cur_type_descriptor,$/;" f +is_pin_open pack/cluster_legality.c /^boolean is_pin_open(int i) {$/;" f +is_prog ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean is_prog;$/;" m struct:s_spice_model_port +is_reset ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean is_reset;$/;" m struct:s_spice_model_port +is_sb_interc_between_segments fpga_spice/fpga_spice_utils.c /^int is_sb_interc_between_segments(int switch_box_x, $/;" f +is_sbox route/rr_graph2.c /^boolean is_sbox(INP int chan, INP int wire_seg, INP int sb_seg, INP int track,$/;" f +is_set ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean is_set;$/;" m struct:s_spice_model_port +is_show_pass_trans ../../libarchfpga/include/arch_types_mrfpga.h /^ boolean is_show_pass_trans;$/;" m struct:s_arch_mrfpga +is_show_pass_trans mrfpga/mrfpga_globals.c /^boolean is_show_sram = FALSE, is_show_pass_trans = FALSE;$/;" v +is_show_sram ../../libarchfpga/include/arch_types_mrfpga.h /^ boolean is_show_sram;$/;" m struct:s_arch_mrfpga +is_show_sram mrfpga/mrfpga_globals.c /^boolean is_show_sram = FALSE, is_show_pass_trans = FALSE;$/;" v +is_stack ../../libarchfpga/include/arch_types_mrfpga.h /^ boolean is_stack;$/;" m struct:s_arch_mrfpga +is_stack mrfpga/mrfpga_globals.c /^boolean is_stack = FALSE;$/;" v +is_swap2pins_match_prefer_side clb_pin_remap/clb_pin_remap_util.c /^int is_swap2pins_match_prefer_side(int pin0_cur_side, int* pin0_prefer_side,$/;" f +is_type_pin_in_class clb_pin_remap/clb_pin_remap_util.c /^int is_type_pin_in_class(t_type_ptr type,$/;" f +is_verilog_and_spice_syntax_conflict_char fpga_spice/fpga_spice_setup.c /^boolean is_verilog_and_spice_syntax_conflict_char(t_llist* LL_reserved_syntax_char_head, $/;" f file: +is_wire_buffer ../../libarchfpga/include/arch_types_mrfpga.h /^ boolean is_wire_buffer;$/;" m struct:s_arch_mrfpga +is_wire_buffer mrfpga/mrfpga_globals.c /^boolean is_wire_buffer = FALSE;$/;" v +ispressed base/graphics.c /^ bool ispressed;$/;" m struct:__anon4 file: +iswitch base/vpr_types.h /^ short iswitch;$/;" m struct:s_trace +iswitch route/route_tree_timing.h /^ short iswitch;$/;" m struct:s_linked_rt_edge +iswitch route/rr_graph_util.h /^ short iswitch;$/;" m struct:s_linked_edge +iswitch timing/net_delay_types.h /^ short iswitch;$/;" m struct:s_linked_rc_edge +join_left_plan_list_into_whole mrfpga/buffer_insertion.c /^static t_buffer_plan_list join_left_plan_list_into_whole( t_buffer_plan_list left, t_buffer_plan_list* whole, int num_whole, t_buffer_plan_list current, int num_pins )$/;" f file: +keypress_ptr base/graphics.c /^static void (*keypress_ptr)(char entered_char);$/;" v file: +label_incoming_wires route/rr_graph2.c /^label_incoming_wires(INP int chan_num, INP int seg_num, INP int sb_seg,$/;" f file: +label_wire_muxes route/rr_graph2.c /^label_wire_muxes(INP int chan_num, INP int seg_num,$/;" f file: +label_wire_muxes_for_balance route/rr_graph2.c /^label_wire_muxes_for_balance(INP int chan_num, INP int seg_num,$/;" f file: +leakage ../../libarchfpga/include/physical_types.h /^ float leakage;$/;" m struct:s_power_usage +leakage_default_mode ../../libarchfpga/include/physical_types.h /^ int leakage_default_mode; \/* Default mode for leakage analysis, if block has no set mode *\/$/;" m struct:s_pb_type_power +leakage_gate power/power.h /^ float leakage_gate;$/;" m struct:s_transistor_size_inf +leakage_pairs power/power.h /^ t_power_nmos_leakage_pair * leakage_pairs;$/;" m struct:s_power_nmos_leakage_inf +leakage_subthreshold power/power.h /^ float leakage_subthreshold;$/;" m struct:s_transistor_size_inf +least_slack base/vpr_types.h /^ float ** least_slack;$/;" m struct:s_timing_stats +legal_pos place/place.c /^static t_legal_pos **legal_pos = NULL; \/* [0..num_types-1][0..type_tsize - 1] *\/$/;" v file: +len ../../libarchfpga/include/ezxml.h /^ size_t len; \/* length of allocated memory for mmap, -1 for malloc *\/$/;" m struct:ezxml_root +len timing/slre.c /^ int len; \/\/ Substring length$/;" m struct:cap file: +length ../../libarchfpga/include/physical_types.h /^ int length;$/;" m struct:s_segment_inf +length base/vpr_types.h /^ int length;$/;" m struct:s_seg_details +level ../../libarchfpga/fpga_spice_include/spice_types.h /^ int level;$/;" m struct:s_spice_model_wire_param +level power/power.h /^ int level; \/* Level in the full multilevel mux - 0 = primary inputs to mux *\/$/;" m struct:s_mux_node +level_restorer power/power.h /^ boolean level_restorer; \/* Whether the output of this mux is level restored *\/$/;" m struct:s_mux_node +levels power/power.h /^ int levels;$/;" m struct:s_mux_arch +library_models base/vpr_types.h /^ t_model * library_models; \/* blif models in VPR *\/$/;" m struct:s_vpr_setup +limit_value ../../libarchfpga/util.c /^int limit_value(int cur, int max, const char *name) {$/;" f +line ../../libarchfpga/include/ezxml.h /^ int line;$/;" m struct:ezxml +line ../../libarchfpga/include/physical_types.h /^ int line;$/;" m struct:s_direct_inf +line_fuz base/draw.c /^static float line_fuz = 0.3;$/;" v file: +line_num ../../libarchfpga/include/physical_types.h /^ int line_num; \/* Interconnect is processed later, need to know what line number it messed up on to give proper error message *\/$/;" m struct:s_interconnect +line_num ../../libarchfpga/include/physical_types.h /^ int line_num; \/* used to report what line number this annotation is found in architecture file *\/$/;" m struct:s_pin_to_pin_annotation +line_types base/easygl_constants.h /^enum line_types {SOLID, DASHED};$/;" g +linked_f_pointer_ch route/route_common.c /^static t_chunk linked_f_pointer_ch = {NULL, 0, NULL};$/;" v file: +linked_f_pointer_free_head route/route_common.c /^static struct s_linked_f_pointer *linked_f_pointer_free_head = NULL;$/;" v typeref:struct:s_linked_f_pointer file: +list ../../libarchfpga/include/util.h /^ int *list;$/;" m struct:s_ivec +list_of_connectable_input_pin_ptrs ../../libarchfpga/include/physical_types.h /^ struct s_pb_graph_pin ***list_of_connectable_input_pin_ptrs; \/* [0..depth-1][0..num_connectable_primtive_input_pins-1] what input pins this output can connect to without exiting cluster at given depth *\/$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_pin +load_best_buffer_list mrfpga/buffer_insertion.c /^void load_best_buffer_list( )$/;" f +load_chan_rr_indices route/rr_graph2.c /^static void load_chan_rr_indices(INP int nodes_per_chan, INP int chan_len,$/;" f file: +load_channel_occupancies base/stats.c /^static void load_channel_occupancies(int **chanx_occ, int **chany_occ) {$/;" f file: +load_clock_domain_and_clock_and_io_delay timing/path_delay.c /^static void load_clock_domain_and_clock_and_io_delay(boolean is_prepacked) {$/;" f file: +load_cluster_placement_stats_for_pb_graph_node pack/cluster_placement.c /^static void load_cluster_placement_stats_for_pb_graph_node($/;" f file: +load_constant_net_delay timing/net_delay.c /^void load_constant_net_delay(float **net_delay, float delay_value,$/;" f +load_critical_path_annotations pack/pb_type_graph_annotations.c /^static void load_critical_path_annotations(INP int line_num, $/;" f file: +load_criticalities place/timing_place.c /^void load_criticalities(t_slack * slacks, float crit_exponent) {$/;" f +load_default_models base/read_blif.c /^static void load_default_models(INP t_model *library_models,$/;" f file: +load_expected_remapped_net_delay clb_pin_remap/post_place_timing.c /^void load_expected_remapped_net_delay(float** net_delay, $/;" f +load_external_nets_and_cb base/read_netlist.c /^static void load_external_nets_and_cb(INP int L_num_blocks,$/;" f file: +load_font base/graphics.c /^load_font(int pointsize) $/;" f file: +load_internal_cb_nets base/read_netlist.c /^static void load_internal_cb_nets(INOUTP t_pb *top_level,$/;" f file: +load_internal_cb_rr_graph_net_nums base/read_netlist.c /^static void load_internal_cb_rr_graph_net_nums(INP t_rr_node * cur_rr_node,$/;" f file: +load_legal_placements place/place.c /^static void load_legal_placements() {$/;" f file: +load_list_of_connectable_input_pin_ptrs pack/cluster_feasibility_filter.c /^static void load_list_of_connectable_input_pin_ptrs($/;" f file: +load_net_delay_from_routing timing/net_delay.c /^void load_net_delay_from_routing(float **net_delay, struct s_net *nets,$/;" f +load_net_rr_terminals route/rr_graph.c /^void load_net_rr_terminals(t_ivec *** L_rr_node_indices) {$/;" f +load_new_path_R_upstream route/route_tree_timing.c /^static void load_new_path_R_upstream(t_rt_node * start_of_new_path_rt_node) {$/;" f file: +load_one_constant_net_delay timing/net_delay.c /^void load_one_constant_net_delay(float **net_delay, int inet,$/;" f +load_one_net_delay timing/net_delay.c /^void load_one_net_delay(float **net_delay, int inet, struct s_net* nets,$/;" f +load_one_pb_graph_pin_temp_net_num_from_pb fpga_spice/fpga_spice_utils.c /^void load_one_pb_graph_pin_temp_net_num_from_pb(t_pb* cur_pb,$/;" f +load_pack_pattern_annotations pack/pb_type_graph_annotations.c /^static void load_pack_pattern_annotations(INP int line_num, INOUTP t_pb_graph_node *pb_graph_node,$/;" f file: +load_pb base/verilog_writer.h /^ t_pb *load_pb;$/;" m struct:found_connectivity +load_pb_graph_node_temp_net_num_from_pb fpga_spice/fpga_spice_utils.c /^void load_pb_graph_node_temp_net_num_from_pb(t_pb* cur_pb) {$/;" f +load_pb_graph_pin_to_pin_annotations pack/pb_type_graph_annotations.c /^void load_pb_graph_pin_to_pin_annotations(INOUTP t_pb_graph_node *pb_graph_node) {$/;" f +load_perturbed_switch_pattern route/rr_graph.c /^static void load_perturbed_switch_pattern(INP t_type_ptr type,$/;" f file: +load_pin base/verilog_writer.h /^ t_pb_graph_pin *load_pin;$/;" m struct:found_connectivity +load_pin_class_by_depth pack/cluster_feasibility_filter.c /^static void load_pin_class_by_depth(INOUTP t_pb_graph_node *pb_graph_node,$/;" f file: +load_pin_classes_in_pb_graph_head pack/cluster_feasibility_filter.c /^void load_pin_classes_in_pb_graph_head(INOUTP t_pb_graph_node *pb_graph_node) {$/;" f +load_post_place_net_delay clb_pin_remap/post_place_timing.c /^void load_post_place_net_delay(float** net_delay,$/;" f +load_rc_tree_C timing/net_delay.c /^float load_rc_tree_C(t_rc_node * rc_node) {$/;" f +load_rc_tree_Ctotal mrfpga/cal_capacitance.c /^static float load_rc_tree_Ctotal (t_rc_node *rc_node) {$/;" f file: +load_rc_tree_T timing/net_delay.c /^void load_rc_tree_T(t_rc_node * rc_node, float T_arrival) {$/;" f +load_route_bb route/route_common.c /^static void load_route_bb(int bb_factor) {$/;" f file: +load_rr_indexed_data_T_values route/rr_graph_indexed_data.c /^static void load_rr_indexed_data_T_values(int index_start,$/;" f file: +load_rr_indexed_data_base_costs route/rr_graph_indexed_data.c /^static void load_rr_indexed_data_base_costs(int nodes_per_chan,$/;" f file: +load_rt_subtree_Tdel route/route_tree_timing.c /^static void load_rt_subtree_Tdel(t_rt_node * subtree_rt_root, float Tarrival) {$/;" f file: +load_sblock_pattern_lookup route/rr_graph2.c /^void load_sblock_pattern_lookup(INP int i, INP int j, INP int nodes_per_chan,$/;" f +load_simplified_device place/timing_place_lookup.c /^static void load_simplified_device(void) {$/;" f file: +load_timing_graph_net_delays timing/path_delay.c /^void load_timing_graph_net_delays(float **net_delay) {$/;" f +load_tnode timing/path_delay.c /^static void load_tnode(INP t_pb_graph_pin *pb_graph_pin, INP int iblock,$/;" f file: +load_truth_table base/verilog_writer.c /^char *load_truth_table(int inputs , t_pb *pb)$/;" f +load_uniform_switch_pattern route/rr_graph.c /^static void load_uniform_switch_pattern(INP t_type_ptr type,$/;" f file: +local_cross_count clb_pin_remap/post_place_timing.c /^static const float local_cross_count[50] = { \/* [0..49] *\/1.0, 1.0, 1.0, 1.0828, 1.1536, 1.2206, 1.2823, 1.3385, 1.3991, 1.4493, 1.4974,$/;" v file: +local_interc_factor ../../libarchfpga/include/physical_types.h /^ float local_interc_factor;$/;" m struct:s_power_arch +local_nets base/vpr_types.h /^ struct s_net *local_nets; \/* Records post-packing connections, valid only for top-level *\/$/;" m struct:s_pb typeref:struct:s_pb::s_net +log_msg power/power_util.c /^static void log_msg(t_log * log_ptr, char * msg) {$/;" f file: +logic_block_spice_file_name spice/spice_globals.c /^char* logic_block_spice_file_name = "logic_blocks.sp";$/;" v +logic_block_verilog_file_name syn_verilog/verilog_global.c /^char* logic_block_verilog_file_name = "logic_blocks.v";$/;" v +logical_block base/globals.c /^struct s_logical_block *logical_block = NULL;$/;" v typeref:struct:s_logical_block +logical_block base/vpr_types.h /^ int logical_block; \/* If this is a terminating pb, gives the logical (netlist) block that it contains *\/$/;" m struct:s_pb +logical_block_input_count base/read_blif.c /^static int *logical_block_input_count, *logical_block_output_count;$/;" v file: +logical_block_output_count base/read_blif.c /^static int *logical_block_input_count, *logical_block_output_count;$/;" v file: +logical_block_ptrs base/vpr_types.h /^ t_logical_block **logical_block_ptrs; \/* [0..num_blocks-1] ptrs to logical blocks that implements this molecule, index on pack_pattern_block->index of pack pattern *\/$/;" m struct:s_pack_molecule +logical_block_types base/vpr_types.h /^enum logical_block_types {$/;" g +logical_effort_factor ../../libarchfpga/include/physical_types.h /^ float logical_effort_factor;$/;" m struct:s_power_arch +logs power/power.h /^ t_log * logs;$/;" m struct:s_power_output +long_trans_inf power/power.h /^ t_transistor_size_inf * long_trans_inf; \/* Long transistor (W=1,L=2) *\/$/;" m struct:s_transistor_inf +longline ../../libarchfpga/include/physical_types.h /^ boolean longline;$/;" m struct:s_segment_inf +longline base/vpr_types.h /^ boolean longline;$/;" m struct:s_seg_details +lookahead_input_pins_used base/vpr_types.h /^ int **lookahead_input_pins_used; \/* [0..pb_graph_node->num_pin_classes-1][0..pin_class_size] number of input pins of this class that are speculatively used *\/$/;" m struct:s_pb_stats +lookahead_output_pins_used base/vpr_types.h /^ int **lookahead_output_pins_used; \/* [0..pb_graph_node->num_pin_classes-1][0..pin_class_size] number of output pins of this class that are speculatively used *\/$/;" m struct:s_pb_stats +lookup_dump place/timing_place_lookup.c /^static FILE *lookup_dump; \/* If debugging mode is on, print out to$/;" v file: +loop_greedy timing/slre.c /^static void loop_greedy(const struct slre *r, int pc, const char *s, int len,$/;" f file: +loop_non_greedy timing/slre.c /^static void loop_non_greedy(const struct slre *r, int pc, const char *s,$/;" f file: +lowercase timing/slre.c /^static int lowercase(const char *s) {$/;" f file: +lut_input_buffer ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_buffer* lut_input_buffer;$/;" m struct:s_spice_model +lut_pin_remap base/vpr_types.h /^ int *lut_pin_remap; \/* [0..num_lut_inputs-1] applies only to LUT primitives, stores how LUT inputs were swapped during CAD flow, $/;" m struct:s_pb +lut_size base/ReadOptions.h /^ int lut_size;$/;" m struct:s_options +luts_spice_file_name spice/spice_globals.c /^char* luts_spice_file_name = "luts.sp";$/;" v +luts_verilog_file_name syn_verilog/verilog_global.c /^char* luts_verilog_file_name = "luts.v";$/;" v +m ../../libarchfpga/include/ezxml.h /^ char *m; \/* original xml string *\/$/;" m struct:ezxml_root +main ../../libarchfpga/ezxml.c /^main(int argc,$/;" f +main ../../libarchfpga/main.c /^int main(int argc, char **argv) {$/;" f +main main.c /^int main(int argc, char **argv) {$/;" f +main_best_buffer_list ../../libarchfpga/include/arch_types_mrfpga.h /^ t_linked_int* main_best_buffer_list;$/;" m struct:s_arch_mrfpga +main_best_buffer_list mrfpga/mrfpga_globals.c /^t_linked_int* main_best_buffer_list;$/;" v +map_button base/graphics.c /^static void map_button (int bnum) $/;" f file: +map_pb_type_port_to_spice_model_ports fpga_spice/fpga_spice_setup.c /^int map_pb_type_port_to_spice_model_ports(t_pb_type* cur_pb_type,$/;" f file: +mapped_spice_model base/vpr_types.h /^ t_spice_model* mapped_spice_model;$/;" m struct:s_logical_block +mapped_spice_model_index base/vpr_types.h /^ int mapped_spice_model_index; \/* index of spice_model in completed FPGA netlist *\/$/;" m struct:s_logical_block +mark_and_update_partial_gain pack/cluster.c /^static void mark_and_update_partial_gain(int inet, enum e_gain_update gain_flag,$/;" f file: +mark_blk_pins_nets_sink_index clb_pin_remap/clb_pin_remap_util.c /^void mark_blk_pins_nets_sink_index(int n_nets, t_net* nets,$/;" f +mark_constant_generators base/read_netlist.c /^static void mark_constant_generators(INP int L_num_blocks,$/;" f file: +mark_constant_generators_rec base/read_netlist.c /^static void mark_constant_generators_rec(INP t_pb *pb, INP t_rr_node *rr_graph,$/;" f file: +mark_direct_of_pins util/vpr_utils.c /^static void mark_direct_of_pins(int start_pin_index, int end_pin_index, int itype, $/;" f file: +mark_direct_of_ports util/vpr_utils.c /^static void mark_direct_of_ports (int idirect, int direct_type, char * pb_type_name, $/;" f file: +mark_ends route/route_common.c /^void mark_ends(int inet) {$/;" f +mark_ends_cluster pack/cluster_legality.c /^static void mark_ends_cluster(int inet) {$/;" f file: +mark_grid_type_pb_graph_node_pins_temp_net_num fpga_spice/fpga_spice_utils.c /^void mark_grid_type_pb_graph_node_pins_temp_net_num(int x, int y) {$/;" f +mark_node_expansion_by_bin route/route_timing.c /^static int mark_node_expansion_by_bin(int inet, int target_node,$/;" f file: +mark_one_pb_parasitic_nets fpga_spice/fpga_spice_utils.c /^void mark_one_pb_parasitic_nets(t_pb* cur_pb) {$/;" f +mark_pb_graph_node_clock_pins_temp_net_num fpga_spice/fpga_spice_utils.c /^void mark_pb_graph_node_clock_pins_temp_net_num(t_pb_graph_node* cur_pb_graph_node,$/;" f +mark_pb_graph_node_input_pins_temp_net_num fpga_spice/fpga_spice_utils.c /^void mark_pb_graph_node_input_pins_temp_net_num(t_pb_graph_node* cur_pb_graph_node,$/;" f +mark_pb_graph_node_output_pins_temp_net_num fpga_spice/fpga_spice_utils.c /^void mark_pb_graph_node_output_pins_temp_net_num(t_pb_graph_node* cur_pb_graph_node,$/;" f +marked_blocks base/vpr_types.h /^ int *marked_nets, *marked_blocks;$/;" m struct:s_pb_stats +marked_nets base/vpr_types.h /^ int *marked_nets, *marked_blocks;$/;" m struct:s_pb_stats +match timing/slre.c /^static const char *match(const struct slre *r, int pc, const char *s, int len,$/;" f file: +match2 timing/slre.c /^static const char *match2(const struct slre *r, const char *buf, int len,$/;" f file: +match_pb_types_spice_model_rec fpga_spice/fpga_spice_setup.c /^void match_pb_types_spice_model_rec(t_pb_type* cur_pb_type,$/;" f file: +match_pb_types_verilog_model_rec syn_verilog/verilog_pbtypes.c /^void match_pb_types_verilog_model_rec(t_pb_type* cur_pb_type,$/;" f +max base/graphics.c 171;" d file: +max mrfpga/mrfpga_util.h 6;" d +max_IPIN_fanin power/power.h /^ int max_IPIN_fanin;$/;" m struct:s_power_commonly_used +max_buffer_size power/power.h /^ int max_buffer_size;$/;" m struct:s_power_tech +max_criticality base/ReadOptions.h /^ float max_criticality;$/;" m struct:s_options +max_criticality base/vpr_types.h /^ float max_criticality;$/;" m struct:s_router_opts +max_ext_index pack/cluster_legality.c /^ ext_clock_rr_node_index, max_ext_index;$/;" v file: +max_index route/rr_graph.c /^ int max_index;$/;" m struct:s_mux_size_distribution file: +max_internal_delay ../../libarchfpga/include/physical_types.h /^ float max_internal_delay;$/;" m struct:s_pb_type +max_len_pl_macros place/place_macro.c /^int max_len_pl_macros(int num_pl_macros, $/;" f +max_mux_sl_size power/power.h /^ int max_mux_sl_size;$/;" m struct:s_power_nmos_mux_inf +max_pins_per_side ../../libarchfpga/include/arch_types_mrfpga.h /^ int max_pins_per_side;$/;" m struct:s_arch_mrfpga +max_pins_per_side mrfpga/mrfpga_globals.c /^int max_pins_per_side;$/;" v +max_router_iterations base/ReadOptions.h /^ int max_router_iterations;$/;" m struct:s_options +max_router_iterations base/vpr_types.h /^ int max_router_iterations;$/;" m struct:s_router_opts +max_routing_mux_size power/power.h /^ int max_routing_mux_size;$/;" m struct:s_power_commonly_used +max_seg_fanout power/power.h /^ int max_seg_fanout;$/;" m struct:s_power_commonly_used +max_seg_to_IPIN_fanout power/power.h /^ int max_seg_to_IPIN_fanout;$/;" m struct:s_power_commonly_used +max_seg_to_seg_fanout power/power.h /^ int max_seg_to_seg_fanout;$/;" m struct:s_power_commonly_used +max_sim_num_clock_cycles spice/spice_grid_testbench.c /^static int max_sim_num_clock_cycles = 2;$/;" v file: +max_sim_num_clock_cycles spice/spice_hardlogic_testbench.c /^static int max_sim_num_clock_cycles = 2;$/;" v file: +max_sim_num_clock_cycles spice/spice_lut_testbench.c /^static int max_sim_num_clock_cycles = 2;$/;" v file: +max_sim_num_clock_cycles spice/spice_mux_testbench.c /^static int max_sim_num_clock_cycles = 2;$/;" v file: +max_sim_num_clock_cycles spice/spice_routing_testbench.c /^static int max_sim_num_clock_cycles = 2;$/;" v file: +max_width_per_trans spice/spice_globals.c /^float max_width_per_trans = 5.;$/;" v +mc_params ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_mc_params mc_params;$/;" m struct:s_spice_params +mc_sim ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean mc_sim;$/;" m struct:s_spice_mc_params +meas_header_file_name spice/spice_globals.c /^char* meas_header_file_name = "meas_params.sp";$/;" v +meas_params ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_meas_params meas_params;$/;" m struct:s_spice_params +mem_avail ../../libarchfpga/include/util.h /^ int mem_avail; \/* number of bytes left in the current chunk *\/$/;" m struct:s_chunk +mem_bank_info ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_mem_bank_info* mem_bank_info; \/* Only be allocated when orgz type is memory bank *\/$/;" m struct:s_sram_orgz_info +mem_model ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model* mem_model; \/* SPICE model of a memory bit *\/$/;" m struct:s_mem_bank_info +mem_model ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model* mem_model; \/* SPICE model of a memory bit *\/$/;" m struct:s_scff_info +mem_model ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model* mem_model; \/* SPICE model of a memory bit *\/$/;" m struct:s_standalone_sram_info +members place/place_macro.h /^ t_pl_macro_member* members;$/;" m struct:s_pl_macro +memory_pool pack/cluster.c /^static struct s_molecule_link *memory_pool; \/*Declared here so I can free easily.*\/$/;" v typeref:struct:s_molecule_link file: +memristor_inf ../../libarchfpga/include/arch_types_mrfpga.h /^ t_memristor_inf memristor_inf;$/;" m struct:s_arch_mrfpga +memristor_inf mrfpga/mrfpga_globals.c /^t_memristor_inf memristor_inf;$/;" v +menu base/graphics.c /^static Window toplevel, menu, textarea; \/* various windows *\/$/;" v file: +menu_font_size base/graphics.c /^static const int menu_font_size = 12; \/* Font for menus and dialog boxes. *\/$/;" v file: +menutext base/graphics.c /^static void menutext(Window win, int xc, int yc, const char *text) $/;" f file: +messagelogger ../../libarchfpga/include/util.h /^typedef unsigned char (*messagelogger)( TIO_MessageMode_t messageMode,$/;" t +messages power/power.h /^ char ** messages;$/;" m struct:s_log +meta_characters timing/slre.c /^static const char *meta_characters = "|.*+?()[\\\\";$/;" v file: +min base/graphics.c 174;" d file: +min mrfpga/mrfpga_util.h 10;" d +min_size ../../libarchfpga/include/logic_types.h /^ int min_size; \/* minimum number of pins *\/$/;" m struct:s_model_ports +min_width ../../libarchfpga/fpga_spice_include/spice_types.h /^ float min_width;$/;" m struct:s_spice_transistor_type +mode base/vpr_types.h /^ int mode; \/* mode that this pb is set to *\/$/;" m struct:s_pb +mode_bits ../../libarchfpga/include/physical_types.h /^ char* mode_bits; \/* Mode bits to select *\/$/;" m struct:s_pb_type +mode_power ../../libarchfpga/include/physical_types.h /^ t_mode_power * mode_power;$/;" m struct:s_mode +mode_select ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean mode_select;$/;" m struct:s_spice_model_port +model ../../libarchfpga/include/cad_types.h /^ t_model *model; \/* block associated with chain *\/$/;" m struct:s_model_chain_pattern +model ../../libarchfpga/include/physical_types.h /^ t_model *model;$/;" m struct:s_pb_type +model base/read_blif.c /^ t_model * model;$/;" m struct:s_model_stats file: +model base/read_blif.c /^static char *model = NULL;$/;" v file: +model base/vpr_types.h /^ t_model* model; \/* Technology-mapped type (eg. LUT, Flip-flop, memory slice, inpad, etc) *\/$/;" m struct:s_logical_block +model_library ../../libarchfpga/include/physical_types.h /^ t_model *model_library;$/;" m struct:s_arch +model_lines base/read_blif.c /^static int ilines, olines, model_lines, endlines;$/;" v file: +model_name ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* model_name;$/;" m struct:s_spice_transistor_type +model_netlist ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* model_netlist; \/* SPICE netlist provided by user *\/$/;" m struct:s_spice_model +model_pin base/vpr_types.h /^ int model_port, model_pin; \/* technology mapped model pin *\/$/;" m struct:s_prepacked_tnode_data +model_port ../../libarchfpga/include/physical_types.h /^ t_model_ports *model_port;$/;" m struct:s_port +model_port base/vpr_types.h /^ int model_port, model_pin; \/* technology mapped model pin *\/$/;" m struct:s_prepacked_tnode_data +model_port_ptr base/vpr_types.h /^ t_model_ports *model_port_ptr;$/;" m struct:s_prepacked_tnode_data +model_ref ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* model_ref;$/;" m struct:s_spice_tech_lib +models ../../libarchfpga/include/physical_types.h /^ t_model *models;$/;" m struct:s_arch +modes ../../libarchfpga/include/physical_types.h /^ t_mode *modes; \/* [0..num_modes-1] *\/$/;" m struct:s_pb_type +moleculeptr pack/cluster.c /^ t_pack_molecule *moleculeptr;$/;" m struct:s_molecule_link file: +mouseclick_ptr base/graphics.c /^static void (*mouseclick_ptr)(float x, float y);$/;" v file: +mousemove_ptr base/graphics.c /^static void (*mousemove_ptr)(float x, float y);$/;" v file: +moved_blocks place/place.c /^ t_pl_moved_block * moved_blocks;$/;" m struct:s_pl_blocks_to_be_moved file: +multilevel_mux_last_level_input_num fpga_spice/fpga_spice_utils.c /^int multilevel_mux_last_level_input_num(int num_level, int num_input_per_unit,$/;" f +mux_arch power/power.h /^ t_mux_arch * mux_arch;$/;" m struct:s_power_mux_info +mux_arch_fix_levels power/power_util.c /^void mux_arch_fix_levels(t_mux_arch * mux_arch) {$/;" f +mux_arch_max_size power/power.h /^ int mux_arch_max_size;$/;" m struct:s_power_mux_info +mux_basis_posfix spice/spice_globals.c /^char* mux_basis_posfix = "_basis";$/;" v +mux_count route/rr_graph.c /^ int mux_count;$/;" m struct:s_mux_size_distribution file: +mux_find_selector_values power/power_util.c /^boolean mux_find_selector_values(int * selector_values, t_mux_node * mux_node,$/;" f +mux_graph_head power/power.h /^ t_mux_node * mux_graph_head;$/;" m struct:s_mux_arch +mux_info power/power.h /^ std::map mux_info;$/;" m struct:s_power_commonly_used +mux_num_level ../../libarchfpga/fpga_spice_include/spice_types.h /^ int mux_num_level;$/;" m struct:s_spice_model_design_tech_info +mux_size power/power.h /^ int mux_size;$/;" m struct:s_power_buffer_sc_levr_inf +mux_special_basis_posfix spice/spice_globals.c /^char* mux_special_basis_posfix = "_special_basis";$/;" v +mux_trans_size ../../libarchfpga/include/physical_types.h /^ float mux_trans_size;$/;" m struct:s_switch_inf +mux_transistor_size ../../libarchfpga/include/physical_types.h /^ float mux_transistor_size;$/;" m struct:s_power_arch +mux_voltage_inf power/power.h /^ t_power_mux_volt_inf * mux_voltage_inf;$/;" m struct:s_power_nmos_mux_inf +mux_voltage_pairs power/power.h /^ t_power_mux_volt_pair * mux_voltage_pairs;$/;" m struct:s_power_mux_volt_inf +muxes_spice_file_name spice/spice_globals.c /^char* muxes_spice_file_name = "muxes.sp";$/;" v +muxes_verilog_file_name syn_verilog/verilog_global.c /^char* muxes_verilog_file_name = "muxes.v";$/;" v +my_atof_2D util/token.c /^void my_atof_2D(INOUTP float **matrix, INP int max_i, INP int max_j,$/;" f +my_atoi ../../libarchfpga/util.c /^int my_atoi(const char *str) {$/;" f +my_calloc ../../libarchfpga/util.c /^my_calloc(size_t nelem, size_t size) {$/;" f +my_chunk_malloc ../../libarchfpga/util.c /^my_chunk_malloc(size_t size, t_chunk *chunk_info) {$/;" f +my_decimal2binary fpga_spice/fpga_spice_utils.c /^int* my_decimal2binary(int decimal,$/;" f +my_fgets ../../libarchfpga/util.c /^my_fgets(char *buf, int max_size, FILE * fp) {$/;" f +my_fopen ../../libarchfpga/util.c /^my_fopen(const char *fname, const char *flag, int prompt) {$/;" f +my_frand ../../libarchfpga/util.c /^float my_frand(void) {$/;" f +my_free ../../libarchfpga/read_xml_spice_util.c /^void my_free(void* ptr) {$/;" f +my_gettime fpga_spice/fpga_spice_utils.c /^char* my_gettime() {$/;" f +my_irand ../../libarchfpga/util.c /^int my_irand(int imax) {$/;" f +my_itoa fpga_spice/fpga_spice_utils.c /^char* my_itoa(int input) {$/;" f +my_malloc ../../libarchfpga/util.c /^my_malloc(size_t size) {$/;" f +my_malloc base/graphics.c /^static void *my_malloc(int ibytes) {$/;" f file: +my_realloc ../../libarchfpga/util.c /^my_realloc(void *ptr, size_t size) {$/;" f +my_realloc base/graphics.c /^static void *my_realloc(void *memblk, int ibytes) {$/;" f file: +my_remove_file fpga_spice/fpga_spice_utils.c /^void my_remove_file(char* file_path) {$/;" f +my_srandom ../../libarchfpga/util.c /^void my_srandom(int seed) {$/;" f +my_strcat fpga_spice/fpga_spice_utils.c /^char* my_strcat(char* str1,$/;" f +my_strdup ../../libarchfpga/util.c /^my_strdup(const char *str) {$/;" f +my_strncpy ../../libarchfpga/util.c /^my_strncpy(char *dest, const char *src, size_t size) {$/;" f +my_strtok ../../libarchfpga/util.c /^my_strtok(char *ptr, const char *tokens, FILE * fp, char *buf) {$/;" f +my_strtok fpga_spice/fpga_spice_utils.c /^char** my_strtok(char* str, $/;" f +name ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* name;$/;" m struct:s_spice_model +name ../../libarchfpga/include/cad_types.h /^ char *name; \/* name of this chain of logic *\/$/;" m struct:s_model_chain_pattern +name ../../libarchfpga/include/cad_types.h /^ char *name; \/* name of this logic model pattern *\/$/;" m struct:s_pack_patterns +name ../../libarchfpga/include/ezxml.h /^ char *name; \/* tag name *\/$/;" m struct:ezxml +name ../../libarchfpga/include/logic_types.h /^ char *name; \/* name of this logic model *\/$/;" m struct:s_model +name ../../libarchfpga/include/logic_types.h /^ char *name; \/* name of this port *\/$/;" m struct:s_model_ports +name ../../libarchfpga/include/physical_types.h /^ char *name;$/;" m struct:s_direct_inf +name ../../libarchfpga/include/physical_types.h /^ char *name;$/;" m struct:s_interconnect +name ../../libarchfpga/include/physical_types.h /^ char *name;$/;" m struct:s_switch_inf +name ../../libarchfpga/include/physical_types.h /^ char *name;$/;" m struct:s_type_descriptor +name ../../libarchfpga/include/physical_types.h /^ char* name;$/;" m struct:s_mode +name ../../libarchfpga/include/physical_types.h /^ char* name;$/;" m struct:s_pb_type +name ../../libarchfpga/include/physical_types.h /^ char* name;$/;" m struct:s_port +name base/vpr_types.h /^ char * name; \/* I\/O port name with an SDC constraint *\/$/;" m struct:s_io +name base/vpr_types.h /^ char * name;$/;" m struct:s_clock +name base/vpr_types.h /^ char *name; \/* Name of this physical block *\/$/;" m struct:s_pb +name base/vpr_types.h /^ char *name; \/* Taken from the first vpack_net which it drives. *\/$/;" m struct:s_logical_block +name base/vpr_types.h /^ char *name;$/;" m struct:s_block +name base/vpr_types.h /^ char *name;$/;" m struct:s_net +name power/power.h /^ char * name;$/;" m struct:s_log +name timing/read_sdc.c /^ char * name;$/;" m struct:s_sdc_clock file: +name util/hash.h /^ char *name;$/;" m struct:s_hash +name_type base/draw.c /^static const char *name_type[] = { "SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY",$/;" v file: +nelem ../../libarchfpga/include/util.h /^ int nelem;$/;" m struct:s_ivec +net base/globals_declare.h /^struct s_net *net;$/;" v typeref:struct:s_net +net_cnt route/pb_pin_eq_auto_detect.c /^ int net_cnt;$/;" m struct:s_num_mapped_opins_stats file: +net_color base/draw.c /^static enum color_types *net_color, *block_color;$/;" v typeref:enum:color_types file: +net_cost place/place.c /^static float *net_cost = NULL, *temp_net_cost = NULL; \/* [0..num_nets-1] *\/$/;" v file: +net_delay place/timing_place_lookup.c /^static float **net_delay;$/;" v file: +net_delay_ch place/timing_place.c /^static t_chunk net_delay_ch = {NULL, 0, NULL};$/;" v file: +net_num base/vpr_types.h /^ int net_num;$/;" m struct:s_rr_node +net_num_in_pack base/vpr_types.h /^ int net_num_in_pack;$/;" m struct:s_rr_node +net_output_feeds_driving_block_input pack/cluster.c /^static int *net_output_feeds_driving_block_input;$/;" v file: +net_pin_index place/place.c /^static int **net_pin_index = NULL;$/;" v file: +net_power base/vpr_types.h /^ t_net_power * net_power;$/;" m struct:s_net +net_rr_terminals base/globals.c /^int **net_rr_terminals = NULL; \/* [0..num_nets-1][0..num_pins-1] *\/$/;" v +net_rr_terminals base/globals_declare.h /^int **net_rr_terminals; \/* [0..num_nets-1][0..num_pins-1] *\/$/;" v +netlist_clocks timing/read_sdc.c /^char ** netlist_clocks; \/* [0..num_netlist_clocks - 1] array of names of clocks in netlist *\/$/;" v +netlist_ios timing/read_sdc.c /^char ** netlist_ios; \/* [0..num_netlist_clocks - 1] array of names of ios in netlist *\/$/;" v +nets base/vpr_types.h /^ int *nets;$/;" m struct:s_block +nets_in_cluster pack/cluster_legality.c /^static int *nets_in_cluster; \/* [0..num_nets_in_cluster-1] *\/$/;" v file: +nets_sink_index base/vpr_types.h /^ int* nets_sink_index;$/;" m struct:s_block +next ../../libarchfpga/fpga_spice_include/linkedlist.h /^ t_llist* next;$/;" m struct:s_llist +next ../../libarchfpga/include/cad_types.h /^ struct s_model_chain_pattern *next; \/* next chain (linked list) *\/$/;" m struct:s_model_chain_pattern typeref:struct:s_model_chain_pattern::s_model_chain_pattern +next ../../libarchfpga/include/cad_types.h /^ struct s_pack_pattern_connections *next;$/;" m struct:s_pack_pattern_connections typeref:struct:s_pack_pattern_connections::s_pack_pattern_connections +next ../../libarchfpga/include/ezxml.h /^ ezxml_t next; \/* next tag with same name in this section at this depth *\/$/;" m struct:ezxml +next ../../libarchfpga/include/logic_types.h /^ struct s_model *next; \/* next model (linked list) *\/$/;" m struct:s_model typeref:struct:s_model::s_model +next ../../libarchfpga/include/logic_types.h /^ struct s_model_ports *next; \/* next port *\/$/;" m struct:s_model_ports typeref:struct:s_model_ports::s_model_ports +next ../../libarchfpga/include/util.h /^ struct s_linked_int *next;$/;" m struct:s_linked_int typeref:struct:s_linked_int::s_linked_int +next ../../libarchfpga/include/util.h /^ struct s_linked_vptr *next;$/;" m struct:s_linked_vptr typeref:struct:s_linked_vptr::s_linked_vptr +next base/place_and_route.h /^ struct s_fmap_cell *next;$/;" m struct:s_fmap_cell typeref:struct:s_fmap_cell::s_fmap_cell +next base/verilog_writer.h /^ struct found_connectivity *next;$/;" m struct:found_connectivity typeref:struct:found_connectivity::found_connectivity +next base/verilog_writer.h /^ struct found_pins *next;$/;" m struct:found_pins typeref:struct:found_pins::found_pins +next base/vpr_types.h /^ struct s_linked_f_pointer *next;$/;" m struct:s_linked_f_pointer typeref:struct:s_linked_f_pointer::s_linked_f_pointer +next base/vpr_types.h /^ struct s_pack_molecule *next;$/;" m struct:s_pack_molecule typeref:struct:s_pack_molecule::s_pack_molecule +next base/vpr_types.h /^ struct s_trace *next;$/;" m struct:s_trace typeref:struct:s_trace::s_trace +next mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan_node { t_buffer_plan value; struct s_buffer_plan_node* next;} t_buffer_plan_node;$/;" m struct:s_buffer_plan_node typeref:struct:s_buffer_plan_node::s_buffer_plan_node file: +next pack/cluster.c /^ struct s_molecule_link *next;$/;" m struct:s_molecule_link typeref:struct:s_molecule_link::s_molecule_link file: +next route/route_common.h /^ struct s_heap *next;$/;" m union:s_heap::__anon14 typeref:struct:s_heap::__anon14::s_heap +next route/route_tree_timing.h /^ struct s_rt_node *next;$/;" m union:s_rt_node::__anon16 typeref:struct:s_rt_node::__anon16::s_rt_node +next route/route_tree_timing.h /^ struct s_linked_rt_edge *next;$/;" m struct:s_linked_rt_edge typeref:struct:s_linked_rt_edge::s_linked_rt_edge +next route/rr_graph.c /^ struct s_mux *next;$/;" m struct:s_mux typeref:struct:s_mux::s_mux file: +next route/rr_graph.c /^ struct s_mux_size_distribution *next;$/;" m struct:s_mux_size_distribution typeref:struct:s_mux_size_distribution::s_mux_size_distribution file: +next route/rr_graph_util.h /^ struct s_linked_edge *next;$/;" m struct:s_linked_edge typeref:struct:s_linked_edge::s_linked_edge +next timing/net_delay_types.h /^ struct s_rc_node *next;$/;" m union:s_rc_node::__anon18 typeref:struct:s_rc_node::__anon18::s_rc_node +next timing/net_delay_types.h /^ struct s_linked_rc_edge *next;$/;" m struct:s_linked_rc_edge typeref:struct:s_linked_rc_edge::s_linked_rc_edge +next timing/net_delay_types.h /^ struct s_linked_rc_ptr *next;$/;" m struct:s_linked_rc_ptr typeref:struct:s_linked_rc_ptr::s_linked_rc_ptr +next util/hash.h /^ struct s_hash *next;$/;" m struct:s_hash typeref:struct:s_hash::s_hash +next_mem_loc_ptr ../../libarchfpga/include/util.h /^ char *next_mem_loc_ptr;\/* pointer to the first available (free) *$/;" m struct:s_chunk +next_primitive ../../libarchfpga/include/cad_types.h /^ struct s_cluster_placement_primitive *next_primitive;$/;" m struct:s_cluster_placement_primitive typeref:struct:s_cluster_placement_primitive::s_cluster_placement_primitive +nint ../../libarchfpga/include/util.h 24;" d +nmos_leakage_info power/power.h /^ t_power_nmos_leakage_inf * nmos_leakage_info;$/;" m struct:s_power_tech +nmos_mux_info power/power.h /^ t_power_nmos_mux_inf * nmos_mux_info;$/;" m struct:s_power_tech +nmos_pmos_spice_file_name spice/spice_globals.c /^char* nmos_pmos_spice_file_name = "nmos_pmos.sp";$/;" v +nmos_size ../../libarchfpga/fpga_spice_include/spice_types.h /^ float nmos_size;$/;" m struct:s_spice_model_pass_gate_logic +nmos_size power/power.h /^ float nmos_size;$/;" m struct:s_power_nmos_leakage_inf +nmos_size power/power.h /^ float nmos_size;$/;" m struct:s_power_nmos_mux_inf +nmos_subckt_name spice/spice_globals.c /^char* nmos_subckt_name = "vpr_nmos";$/;" v +node_block base/vpr_types.h /^ int *node_block;$/;" m struct:s_net +node_block_pin base/vpr_types.h /^ int *node_block_pin;$/;" m struct:s_net +node_block_port base/vpr_types.h /^ int *node_block_port;$/;" m struct:s_net +node_to_heap route/route_common.c /^void node_to_heap(int inode, float cost, int prev_node, int prev_edge,$/;" f +nominal_vdd ../../libarchfpga/fpga_spice_include/spice_types.h /^ float nominal_vdd;$/;" m struct:s_spice_tech_lib +normalized_T_arr base/vpr_types.h /^ float normalized_T_arr; \/* arrival time (normalized with respect to max time) *\/$/;" m struct:s_prepacked_tnode_data +normalized_slack base/vpr_types.h /^ float normalized_slack; \/* slack (normalized with respect to max slack) *\/$/;" m struct:s_prepacked_tnode_data +normalized_total_critical_paths base/vpr_types.h /^ float normalized_total_critical_paths; \/* critical path count (normalized with respect to max count) *\/$/;" m struct:s_prepacked_tnode_data +num_annotations ../../libarchfpga/include/physical_types.h /^ int num_annotations;$/;" m struct:s_interconnect +num_annotations ../../libarchfpga/include/physical_types.h /^ int num_annotations;$/;" m struct:s_pb_type +num_bl ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_bl; \/* Number of Bit Lines in total *\/$/;" m struct:s_mem_bank_info +num_blif_models base/read_blif.c /^static int num_blif_models;$/;" v file: +num_blocks ../../libarchfpga/include/cad_types.h /^ int num_blocks; \/* number of blocks in pattern *\/$/;" m struct:s_pack_patterns +num_blocks base/globals.c /^int num_blocks = 0;$/;" v +num_blocks base/globals_declare.h /^int num_nets, num_blocks;$/;" v +num_blocks base/vpr_types.h /^ int num_blocks; \/* number of logical blocks of molecule *\/$/;" m struct:s_pack_molecule +num_blocks place/place_macro.h /^ int num_blocks;$/;" m struct:s_pl_macro +num_buttons base/graphics.c /^static int num_buttons = 0; \/* Number of menu buttons *\/$/;" v file: +num_caps timing/slre.c /^ int num_caps; \/\/ Number of bracket pairs$/;" m struct:slre file: +num_cb_buffers power/power.h /^ int num_cb_buffers;$/;" m struct:s_power_commonly_used +num_cb_switch ../../libarchfpga/include/physical_types.h /^ int num_cb_switch;$/;" m struct:s_arch +num_cc_constraints base/vpr_types.h /^ int num_cc_constraints; \/* number of special-case clock-to-clock constraints overriding default, calculated, timing constraints *\/$/;" m struct:s_timing_constraints +num_cf_constraints base/vpr_types.h /^ int num_cf_constraints; \/* number of special-case clock-to-flipflop constraints *\/$/;" m struct:s_timing_constraints +num_child_blocks_in_pb base/vpr_types.h /^ int num_child_blocks_in_pb;$/;" m struct:s_pb_stats +num_class ../../libarchfpga/include/physical_types.h /^ int num_class;$/;" m struct:s_type_descriptor +num_clock_names timing/read_sdc.c /^ int num_clock_names;$/;" m struct:s_sdc_exclusive_group file: +num_clock_pins ../../libarchfpga/include/physical_types.h /^ int *num_clock_pins; \/* [0..num_clock_ports - 1] *\/$/;" m struct:s_pb_graph_node +num_clock_pins ../../libarchfpga/include/physical_types.h /^ int num_clock_pins;$/;" m struct:s_pb_type +num_clock_ports ../../libarchfpga/include/physical_types.h /^ int num_clock_ports;$/;" m struct:s_pb_graph_node +num_clocks ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_clocks;$/;" m struct:s_spice_stimulate_params +num_conf_bits base/vpr_types.h /^ int num_conf_bits;$/;" m struct:s_pb +num_conf_bits_cbx fpga_spice/fpga_spice_globals.c /^int** num_conf_bits_cbx = NULL;$/;" v +num_conf_bits_cby fpga_spice/fpga_spice_globals.c /^int** num_conf_bits_cby = NULL;$/;" v +num_conf_bits_sb fpga_spice/fpga_spice_globals.c /^int** num_conf_bits_sb = NULL;$/;" v +num_connectable_primtive_input_pins ../../libarchfpga/include/physical_types.h /^ int *num_connectable_primtive_input_pins; \/* [0..depth-1] number of input pins that this output pin can reach without exiting cluster at given depth *\/$/;" m struct:s_pb_graph_pin +num_constrained_clocks base/vpr_types.h /^ int num_constrained_clocks; \/* number of clocks with timing constraints *\/$/;" m struct:s_timing_constraints +num_constrained_inputs base/vpr_types.h /^ int num_constrained_inputs; \/* number of inputs with timing constraints *\/$/;" m struct:s_timing_constraints +num_constrained_outputs base/vpr_types.h /^ int num_constrained_outputs; \/* number of outputs with timing constraints *\/$/;" m struct:s_timing_constraints +num_critical_input_paths base/vpr_types.h /^ long num_critical_input_paths, num_critical_output_paths; \/* count of critical paths fanning into\/out of this tnode *\/$/;" m struct:s_prepacked_tnode_data +num_critical_output_paths base/vpr_types.h /^ long num_critical_input_paths, num_critical_output_paths; \/* count of critical paths fanning into\/out of this tnode *\/$/;" m struct:s_prepacked_tnode_data +num_directs ../../libarchfpga/include/physical_types.h /^ int num_directs;$/;" m struct:s_arch +num_drive_rr_nodes base/vpr_types.h /^ int num_drive_rr_nodes;$/;" m struct:s_rr_node +num_driver base/read_blif.c /^static int *num_driver, *temp_num_pins;$/;" v file: +num_drivers ../../libarchfpga/include/physical_types.h /^ int num_drivers;$/;" m struct:s_type_descriptor +num_edges base/vpr_types.h /^ int num_edges;$/;" m struct:s_tnode +num_edges base/vpr_types.h /^ short num_edges;$/;" m struct:s_rr_node +num_edges_head pack/pb_type_graph.c /^static struct s_linked_vptr *num_edges_head;$/;" v typeref:struct:s_linked_vptr file: +num_ext_inputs base/vpr_types.h /^ int num_ext_inputs; \/* number of input pins used by molecule that are not self-contained by pattern molecule matches *\/$/;" m struct:s_pack_molecule +num_ext_inputs_logical_block util/vpr_utils.c /^int num_ext_inputs_logical_block(int iblk) {$/;" f +num_fc_constraints base/vpr_types.h /^ int num_fc_constraints; \/* number of special-case flipflop-to-clock constraints *\/$/;" m struct:s_timing_constraints +num_feasible_blocks base/vpr_types.h /^ int num_feasible_blocks; \/* [0..num_marked_models-1] *\/$/;" m struct:s_pb_stats +num_ff_constraints base/vpr_types.h /^ int num_ff_constraints; \/* number of special-case flipflop-to-flipflop constraints *\/$/;" m struct:s_timing_constraints +num_global_clocks ../../libarchfpga/include/physical_types.h /^ int num_global_clocks;$/;" m struct:s_clock_arch +num_grid_loc_def ../../libarchfpga/include/physical_types.h /^ int num_grid_loc_def;$/;" m struct:s_type_descriptor +num_heap_allocated route/route_common.c /^static int num_heap_allocated = 0;$/;" v file: +num_include_netlist ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_include_netlist;$/;" m struct:s_spice +num_inpads base/vpr_types.h /^ int num_inpads;$/;" m struct:s_pb +num_input ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_input;$/;" m struct:s_spice_mux_arch +num_input_basis ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_input_basis;$/;" m struct:s_spice_mux_arch +num_input_edges ../../libarchfpga/include/physical_types.h /^ int num_input_edges;$/;" m struct:s_pb_graph_pin +num_input_last_level ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_input_last_level;$/;" m struct:s_spice_mux_arch +num_input_per_level ../../libarchfpga/fpga_spice_include/spice_types.h /^ int* num_input_per_level; \/* [0...num_level] *\/$/;" m struct:s_spice_mux_arch +num_input_pin_class ../../libarchfpga/include/physical_types.h /^ int num_input_pin_class; \/* number of pin classes that this input pb_graph_node has *\/$/;" m struct:s_pb_graph_node +num_input_pins ../../libarchfpga/include/physical_types.h /^ int *num_input_pins; \/* [0..num_input_ports - 1] *\/$/;" m struct:s_pb_graph_node +num_input_pins ../../libarchfpga/include/physical_types.h /^ int num_input_pins; \/* inputs not including clock pins *\/$/;" m struct:s_pb_type +num_input_pins ../../libarchfpga/include/physical_types.h /^ int num_input_pins;$/;" m struct:s_pb_graph_edge +num_input_ports ../../libarchfpga/include/physical_types.h /^ int num_input_ports;$/;" m struct:s_interconnect_power +num_input_ports ../../libarchfpga/include/physical_types.h /^ int num_input_ports;$/;" m struct:s_pb_graph_node +num_inputs power/PowerSpicedComponent.h /^ int num_inputs;$/;" m class:PowerCallibInputs +num_inputs power/power.h /^ int num_inputs; \/* Number of inputs *\/$/;" m struct:s_mux_node +num_inputs power/power.h /^ int num_inputs;$/;" m struct:s_mux_arch +num_inputs power/power.h /^ short num_inputs; \/* Number of inputs *\/$/;" m struct:s_rr_node_power +num_interconnect ../../libarchfpga/include/physical_types.h /^ int num_interconnect;$/;" m struct:s_mode +num_iopads base/vpr_types.h /^ int num_iopads;$/;" m struct:s_pb +num_ipin_rr_nodes base/vpr_types.h /^ int* num_ipin_rr_nodes; \/* Switch block has some inputs that are CLB IPIN*\/$/;" m struct:s_cb +num_ipin_rr_nodes base/vpr_types.h /^ int* num_ipin_rr_nodes; \/* Switch block has some inputs that are CLB IPIN*\/$/;" m struct:s_sb +num_latches base/read_blif.c /^static int num_luts = 0, num_latches = 0, num_subckts = 0;$/;" v file: +num_leakage_pairs power/power.h /^ int num_leakage_pairs;$/;" m struct:s_power_nmos_leakage_inf +num_legal_pos place/place.c /^static int *num_legal_pos = NULL; \/* [0..num_legal_pos-1] *\/$/;" v file: +num_level ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_level;$/;" m struct:s_spice_mux_arch +num_levr_entries power/power.h /^ int num_levr_entries;$/;" m struct:s_power_buffer_strength_inf +num_linked_f_pointer_allocated route/route_common.c /^static int num_linked_f_pointer_allocated = 0;$/;" v file: +num_local_nets base/vpr_types.h /^ int num_local_nets; \/* Records post-packing connections, valid only for top-level *\/$/;" m struct:s_pb +num_logical_blocks base/globals.c /^int num_logical_nets = 0, num_logical_blocks = 0;$/;" v +num_logical_nets base/globals.c /^int num_logical_nets = 0, num_logical_blocks = 0;$/;" v +num_logs power/power.h /^ int num_logs;$/;" m struct:s_power_output +num_luts base/read_blif.c /^static int num_luts = 0, num_latches = 0, num_subckts = 0;$/;" v file: +num_mapped_opins base/vpr_types.h /^ int num_mapped_opins;$/;" m struct:s_net +num_mapped_opins route/pb_pin_eq_auto_detect.c /^ int num_mapped_opins;$/;" m struct:s_num_mapped_opins_stats file: +num_marked_blocks base/vpr_types.h /^ int num_marked_nets, num_marked_blocks;$/;" m struct:s_pb_stats +num_marked_nets base/vpr_types.h /^ int num_marked_nets, num_marked_blocks;$/;" m struct:s_pb_stats +num_mc_points ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_mc_points;$/;" m struct:s_spice_mc_params +num_mem_bit ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_mem_bit; \/* Number of memory bits in total *\/$/;" m struct:s_mem_bank_info +num_mem_bit ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_mem_bit; \/* Number of memory bits in total *\/$/;" m struct:s_scff_info +num_mem_bit ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_mem_bit; \/* Number of memory bits in total *\/$/;" m struct:s_standalone_sram_info +num_messages power/power.h /^ int num_messages;$/;" m struct:s_log +num_mode_bits base/vpr_types.h /^ int num_mode_bits;$/;" m struct:s_pb +num_modes ../../libarchfpga/include/physical_types.h /^ int num_modes;$/;" m struct:s_pb_type +num_moved_blocks place/place.c /^ int num_moved_blocks;$/;" m struct:s_pl_blocks_to_be_moved file: +num_multicycles base/vpr_types.h /^ int num_multicycles;$/;" m struct:s_override_constraint +num_mux ../../libarchfpga/include/physical_types.h /^ int num_mux;$/;" m struct:s_interconnect +num_netlist_clocks timing/read_sdc.c /^int num_netlist_clocks = 0; \/* number of clocks in netlist *\/$/;" v +num_netlist_ios timing/read_sdc.c /^int num_netlist_ios = 0; \/* number of clocks in netlist *\/$/;" v +num_nets base/globals.c /^int num_nets = 0;$/;" v +num_nets base/globals_declare.h /^int num_nets, num_blocks;$/;" v +num_nets_in_cluster pack/cluster_legality.c /^static int num_nets_in_cluster;$/;" v file: +num_nmos_leakage_info power/power.h /^ int num_nmos_leakage_info;$/;" m struct:s_power_tech +num_nmos_mux_info power/power.h /^ int num_nmos_mux_info;$/;" m struct:s_power_tech +num_normal_switch ../../libarchfpga/include/arch_types_mrfpga.h /^ short num_normal_switch;$/;" m struct:s_arch_mrfpga +num_normal_switch mrfpga/mrfpga_globals.c /^short num_normal_switch;$/;" v +num_opin_drivers base/vpr_types.h /^ int num_opin_drivers; \/* UDSD by WMF (could use "short") *\/$/;" m struct:s_rr_node +num_opin_rr_nodes base/vpr_types.h /^ int* num_opin_rr_nodes; \/* Connection block has some outputs that are CLB OPIN *\/$/;" m struct:s_cb +num_opin_rr_nodes base/vpr_types.h /^ int* num_opin_rr_nodes; \/* Connection block has some outputs that are CLB OPIN *\/$/;" m struct:s_sb +num_outpads base/vpr_types.h /^ int num_outpads;$/;" m struct:s_pb +num_output_edges ../../libarchfpga/include/physical_types.h /^ int num_output_edges;$/;" m struct:s_pb_graph_pin +num_output_pin_class ../../libarchfpga/include/physical_types.h /^ int num_output_pin_class; \/* number of output pin classes that this pb_graph_node has *\/$/;" m struct:s_pb_graph_node +num_output_pins ../../libarchfpga/include/physical_types.h /^ int *num_output_pins; \/* [0..num_output_ports - 1] *\/$/;" m struct:s_pb_graph_node +num_output_pins ../../libarchfpga/include/physical_types.h /^ int num_output_pins;$/;" m struct:s_pb_graph_edge +num_output_pins ../../libarchfpga/include/physical_types.h /^ int num_output_pins;$/;" m struct:s_pb_type +num_output_ports ../../libarchfpga/include/physical_types.h /^ int num_output_ports;$/;" m struct:s_interconnect_power +num_output_ports ../../libarchfpga/include/physical_types.h /^ int num_output_ports;$/;" m struct:s_pb_graph_node +num_p_inputs base/globals.c /^int num_p_inputs = 0, num_p_outputs = 0;$/;" v +num_p_outputs base/globals.c /^int num_p_inputs = 0, num_p_outputs = 0;$/;" v +num_pack_patterns ../../libarchfpga/include/physical_types.h /^ int num_pack_patterns;$/;" m struct:s_pb_graph_edge +num_pb ../../libarchfpga/include/physical_types.h /^ int num_pb;$/;" m struct:s_pb_type +num_pb_type_children ../../libarchfpga/include/physical_types.h /^ int num_pb_type_children;$/;" m struct:s_mode +num_pb_types base/vpr_types.h /^ int num_pb_types; \/* num primitive pb_types inside complex block *\/$/;" m struct:s_cluster_placement_stats +num_pin_loc_assignments ../../libarchfpga/include/physical_types.h /^ int **num_pin_loc_assignments; \/* [0..height-1][0..3] *\/$/;" m struct:s_type_descriptor +num_pin_timing ../../libarchfpga/include/physical_types.h /^ int num_pin_timing; \/* primitive ipin to opin timing *\/$/;" m struct:s_pb_graph_pin +num_pins ../../libarchfpga/include/physical_types.h /^ int num_pins;$/;" m struct:s_class +num_pins ../../libarchfpga/include/physical_types.h /^ int num_pins;$/;" m struct:s_port +num_pins ../../libarchfpga/include/physical_types.h /^ int num_pins;$/;" m struct:s_type_descriptor +num_pins_of_net_in_pb base/vpr_types.h /^ std::map num_pins_of_net_in_pb;$/;" m struct:s_pb_stats +num_pins_per_port ../../libarchfpga/include/physical_types.h /^ int num_pins_per_port;$/;" m struct:s_interconnect_power +num_pl_macros place/place.c /^static int num_pl_macros;$/;" v file: +num_port ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_port;$/;" m struct:s_spice_model +num_ports ../../libarchfpga/include/physical_types.h /^ int num_ports;$/;" m struct:s_pb_type +num_receivers ../../libarchfpga/include/physical_types.h /^ int num_receivers;$/;" m struct:s_type_descriptor +num_reserved_conf_bits base/vpr_types.h /^ int num_reserved_conf_bits;$/;" m struct:s_pb +num_reserved_conf_bits base/vpr_types.h /^ int num_reserved_conf_bits; \/* number of reserved configuration bits *\/$/;" m struct:s_cb +num_reserved_conf_bits base/vpr_types.h /^ int num_reserved_conf_bits; \/* number of reserved configuration bits *\/$/;" m struct:s_sb +num_rp place/place_stats.c /^ int num_rp[MAX_LEN];$/;" m struct:relapos_rec_s file: +num_rr_indexed_data base/globals.c /^int num_rr_indexed_data = 0;$/;" v +num_rr_indexed_data base/globals_declare.h /^int num_rr_indexed_data;$/;" v +num_rr_nodes base/globals.c /^int num_rr_nodes = 0;$/;" v +num_rr_nodes base/globals_declare.h /^int num_rr_nodes;$/;" v +num_sb_buffers power/power.h /^ int num_sb_buffers;$/;" m struct:s_power_commonly_used +num_scff ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_scff; \/* Number of Scan-chain flip-flops *\/$/;" m struct:s_scff_info +num_segment base/vpr_types.h /^ int num_segment;$/;" m struct:s_det_routing_arch +num_segments ../../libarchfpga/include/physical_types.h /^ int num_segments;$/;" m struct:s_arch +num_segments spice/spice_mux_testbench.c /^static int num_segments;$/;" v file: +num_segments spice/spice_routing_testbench.c /^static int num_segments;$/;" v file: +num_siblings base/vpr_types.h /^ int num_siblings;$/;" m struct:s_trace +num_sides base/vpr_types.h /^ int num_sides; \/* Should be fixed to 4 *\/$/;" m struct:s_cb +num_sides base/vpr_types.h /^ int num_sides; \/* Should be fixed to 4 *\/$/;" m struct:s_sb +num_sigma ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_sigma;$/;" m struct:s_spice_mc_variation_params +num_sim_clock_cycles ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_sim_clock_cycles;$/;" m struct:s_spicetb_info +num_sink base/vpr_types.h /^ int num_sink;$/;" m struct:s_override_constraint +num_sinks base/vpr_types.h /^ int num_sinks;$/;" m struct:s_net +num_size_entries power/power.h /^ int num_size_entries;$/;" m struct:s_transistor_inf +num_source base/vpr_types.h /^ int num_source;$/;" m struct:s_override_constraint +num_spice_model ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_spice_model;$/;" m struct:s_spice +num_sram ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_sram; \/* Number of SRAMs in total *\/$/;" m struct:s_standalone_sram_info +num_strengths power/power.h /^ int num_strengths;$/;" m struct:s_power_buffer_size_inf +num_subckts base/read_blif.c /^static int num_luts = 0, num_latches = 0, num_subckts = 0;$/;" v file: +num_swap_aborted place/place.c /^static int num_swap_aborted = 0;$/;" v file: +num_swap_accepted place/place.c /^static int num_swap_accepted = 0;$/;" v file: +num_swap_rejected place/place.c /^static int num_swap_rejected = 0;$/;" v file: +num_switch base/vpr_types.h /^ short num_switch;$/;" m struct:s_det_routing_arch +num_switches ../../libarchfpga/include/physical_types.h /^ int num_switches;$/;" m struct:s_arch +num_swseg_pattern ../../libarchfpga/include/physical_types.h /^ int num_swseg_pattern;$/;" m struct:s_arch +num_swseg_pattern base/vpr_types.h /^ int num_swseg_pattern; \/*Xifan TANG: Switch Segment Pattern Support*\/$/;" m struct:s_det_routing_arch +num_timing_nets timing/path_delay.c /^static int num_timing_nets = 0;$/;" v file: +num_tnode_levels timing/path_delay2.c /^int num_tnode_levels; \/* Number of levels in the timing graph. *\/$/;" v +num_tnodes timing/path_delay.c /^int num_tnodes = 0; \/* Number of nodes (pins) in the timing graph *\/$/;" v +num_trace_allocated route/route_common.c /^static int num_trace_allocated = 0; \/* To watch for memory leaks. *\/$/;" v file: +num_transistor_type ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_transistor_type;$/;" m struct:s_spice_tech_lib +num_ts_called place/place.c /^static int num_ts_called = 0;$/;" v file: +num_types base/globals.c /^int num_types = 0;$/;" v +num_types_backup place/timing_place_lookup.c /^static int num_types_backup;$/;" v file: +num_used_cb_mux_tb spice/spice_globals.c /^int num_used_cb_mux_tb = 0;$/;" v +num_used_cb_tb spice/spice_globals.c /^int num_used_cb_tb = 0;$/;" v +num_used_dff_tb spice/spice_globals.c /^int num_used_dff_tb = 0;$/;" v +num_used_grid_mux_tb spice/spice_globals.c /^int num_used_grid_mux_tb = 0;$/;" v +num_used_grid_tb spice/spice_globals.c /^int num_used_grid_tb = 0;$/;" v +num_used_hardlogic_tb spice/spice_globals.c /^int num_used_hardlogic_tb = 0;$/;" v +num_used_io_tb spice/spice_globals.c /^int num_used_io_tb = 0;$/;" v +num_used_lut_tb spice/spice_globals.c /^int num_used_lut_tb = 0;$/;" v +num_used_sb_mux_tb spice/spice_globals.c /^int num_used_sb_mux_tb = 0;$/;" v +num_used_sb_tb spice/spice_globals.c /^int num_used_sb_tb = 0;$/;" v +num_value_prop_pairs ../../libarchfpga/include/physical_types.h /^ int num_value_prop_pairs;$/;" m struct:s_pin_to_pin_annotation +num_voltage_pairs power/power.h /^ int num_voltage_pairs;$/;" m struct:s_power_mux_volt_inf +num_wire_drivers base/vpr_types.h /^ int num_wire_drivers; \/* UDSD by WMF *\/$/;" m struct:s_rr_node +num_wl ../../libarchfpga/fpga_spice_include/spice_types.h /^ int num_wl; \/* Number of Word Lines in total *\/$/;" m struct:s_mem_bank_info +nx base/globals.c /^int nx = 0;$/;" v +nx base/globals_declare.h /^int nx, ny;$/;" v +ny base/globals.c /^int ny = 0;$/;" v +ny base/globals_declare.h /^int nx, ny;$/;" v +object_end base/graphics.c /^void object_end() { }$/;" f +object_end base/graphics.c /^void object_end() {$/;" f +object_start base/graphics.c /^void object_start(int all) { }$/;" f +object_start base/graphics.c /^void object_start(int all) {$/;" f +occ base/vpr_types.h /^ short occ;$/;" m struct:s_rr_node +occupancy base/vpr_types.h /^ float occupancy;$/;" m struct:s_place_region +off ../../libarchfpga/include/ezxml.h /^ size_t off; \/* tag offset from start of parent tag character content *\/$/;" m struct:ezxml +offset base/vpr_types.h /^ int offset;$/;" m struct:s_grid_tile +old_num_rr_nodes base/draw.c /^static int old_num_rr_nodes = 0;$/;" v file: +olines base/read_blif.c /^static int ilines, olines, model_lines, endlines;$/;" v file: +op_clock_freq ../../libarchfpga/fpga_spice_include/spice_types.h /^ float op_clock_freq; \/* Operation clock frequency*\/$/;" m struct:s_spice_stimulate_params +open ../../libarchfpga/ezxml.c 58;" d file: +operator < power/PowerSpicedComponent.h /^ const bool operator<(const PowerCallibSize & rhs) {$/;" f class:PowerCallibSize +opin_rr_node base/vpr_types.h /^ t_rr_node*** opin_rr_node;$/;" m struct:s_cb +opin_rr_node base/vpr_types.h /^ t_rr_node*** opin_rr_node;$/;" m struct:s_sb +opin_rr_node_grid_side base/vpr_types.h /^ int** opin_rr_node_grid_side; \/* We need to record the side of a OPIN, because a OPIN may locate on more than one sides *\/$/;" m struct:s_cb +opin_rr_node_grid_side base/vpr_types.h /^ int** opin_rr_node_grid_side; \/* We need to record the side of a OPIN, because a OPIN may locate on more than one sides *\/$/;" m struct:s_sb +opin_switch ../../libarchfpga/include/physical_types.h /^ short opin_switch;$/;" m struct:s_segment_inf +opin_switch base/vpr_types.h /^ short opin_switch;$/;" m struct:s_seg_details +opin_to_cb ../../libarchfpga/include/physical_types.h /^ boolean opin_to_cb;$/;" m struct:s_type_descriptor +opin_to_wire_switch base/vpr_types.h /^ short opin_to_wire_switch; \/* mrFPGA: Xifan TANG*\/$/;" m struct:s_det_routing_arch +options timing/slre.c /^ enum slre_option options;$/;" m struct:slre typeref:enum:slre::slre_option file: +ordered ../../libarchfpga/include/ezxml.h /^ ezxml_t ordered; \/* next tag, same section and depth, in original order *\/$/;" m struct:ezxml +ortho_cost_index base/vpr_types.h /^ int ortho_cost_index;$/;" m struct:s_rr_indexed_data +out power/power.h /^ FILE * out;$/;" m struct:s_power_output +out_edges base/vpr_types.h /^ t_tedge *out_edges; \/* [0..num_edges - 1] array of edges fanning out from this tnode.$/;" m struct:s_tnode +out_file_prefix ../../libarchfpga/util.c /^char *out_file_prefix = NULL;$/;" v +out_file_prefix base/ReadOptions.h /^ char *out_file_prefix;$/;" m struct:s_options +out_file_prefix base/vpr_types.h /^ char *out_file_prefix;$/;" m struct:s_file_name_opts +outport_link_pin ../../libarchfpga/include/cad_types.h /^ int outport_link_pin; \/* applicable pin of chain output port *\/$/;" m struct:s_model_chain_pattern +outputFileNames base/ReadOptions.c /^static char **outputFileNames = NULL;$/;" v file: +output_blif pack/output_blif.c /^void output_blif (t_block *clb, int num_clusters, boolean global_clocks,$/;" f +output_buffer ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_buffer* output_buffer;$/;" m struct:s_spice_model +output_clustering pack/output_clustering.c /^void output_clustering(t_block *clb, int num_clusters, boolean global_clocks,$/;" f +output_edges ../../libarchfpga/include/physical_types.h /^ struct s_pb_graph_edge** output_edges; \/* [0..num_output_edges] *\/$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_edge +output_file base/vpr_types.h /^ char *output_file;$/;" m struct:s_packer_opts +output_link_port ../../libarchfpga/include/cad_types.h /^ t_model_ports *output_link_port; \/* pointer to port of chain output *\/$/;" m struct:s_model_chain_pattern +output_log power/power_util.c /^void output_log(t_log * log_ptr, FILE * fp) {$/;" f +output_logs power/power_util.c /^void output_logs(FILE * fp, t_log * logs, int num_logs) {$/;" f +output_net_tnodes base/vpr_types.h /^ struct s_tnode ***output_net_tnodes; \/* [0..num_output_ports-1][0..num_pins -1] correspnding output net tnode *\/$/;" m struct:s_logical_block typeref:struct:s_logical_block::s_tnode +output_nets base/vpr_types.h /^ int **output_nets; \/* [0..num_output_ports-1][0..num_port_pins-1] List of output nets connected to this logical_block. *\/$/;" m struct:s_logical_block +output_pin_class_size ../../libarchfpga/include/physical_types.h /^ int *output_pin_class_size; \/* Stores the number of pins that belong to a particular output pin class *\/$/;" m struct:s_pb_graph_node +output_pins ../../libarchfpga/include/physical_types.h /^ char * output_pins;$/;" m struct:s_pin_to_pin_annotation +output_pins ../../libarchfpga/include/physical_types.h /^ struct s_pb_graph_pin *** output_pins; \/\/ [0..num_output_ports-1][0..num_pins_per_port-1]$/;" m struct:s_interconnect_pins typeref:struct:s_interconnect_pins::s_pb_graph_pin +output_pins ../../libarchfpga/include/physical_types.h /^ t_pb_graph_pin **output_pins; \/* [0..num_output_ports-1] [0..num_port_pins-1]*\/$/;" m struct:s_pb_graph_node +output_pins ../../libarchfpga/include/physical_types.h /^ t_pb_graph_pin **output_pins;$/;" m struct:s_pb_graph_edge +output_pins_used base/vpr_types.h /^ int **output_pins_used; \/* [0..pb_graph_node->num_pin_classes-1][0..pin_class_size] number of output pins of this class that are used *\/$/;" m struct:s_pb_stats +output_ports_eq_auto_detect ../../libarchfpga/include/physical_types.h /^ boolean output_ports_eq_auto_detect;$/;" m struct:s_type_descriptor +output_string ../../libarchfpga/include/physical_types.h /^ char *output_string;$/;" m struct:s_interconnect +output_thres_pct_fall ../../libarchfpga/fpga_spice_include/spice_types.h /^ float output_thres_pct_fall;$/;" m struct:s_spice_meas_params +output_thres_pct_rise ../../libarchfpga/fpga_spice_include/spice_types.h /^ float output_thres_pct_rise;$/;" m struct:s_spice_meas_params +outputs ../../libarchfpga/include/logic_types.h /^ t_model_ports *outputs; \/* linked list of output ports *\/$/;" m struct:s_model +pack_clb_pin_remap base/vpr_types.h /^ boolean pack_clb_pin_remap;$/;" m struct:s_packer_opts +pack_intrinsic_cost base/vpr_types.h /^ float pack_intrinsic_cost;$/;" m struct:s_rr_node +pack_pattern base/vpr_types.h /^ t_pack_patterns *pack_pattern; \/* If this is a forced_pack molecule, pattern this molecule matches *\/$/;" m struct:s_pack_molecule +pack_pattern_indices ../../libarchfpga/include/physical_types.h /^ int *pack_pattern_indices; \/*[0..num_pack_patterns(of_edge)-1]*\/$/;" m struct:s_pb_graph_edge +pack_pattern_names ../../libarchfpga/include/physical_types.h /^ char **pack_pattern_names; \/*[0..num_pack_patterns(of_edge)-1]*\/$/;" m struct:s_pb_graph_edge +pack_route_time base/globals.c /^float pack_route_time = 0.;$/;" v +packed_molecules base/vpr_types.h /^ struct s_linked_vptr *packed_molecules; \/* List of t_pack_molecules that this logical block is a part of *\/$/;" m struct:s_logical_block typeref:struct:s_logical_block::s_linked_vptr +packer_algorithm base/ReadOptions.h /^ enum e_packer_algorithm packer_algorithm;$/;" m struct:s_options typeref:enum:s_options::e_packer_algorithm +packer_algorithm base/vpr_types.h /^ enum e_packer_algorithm packer_algorithm;$/;" m struct:s_packer_opts typeref:enum:s_packer_opts::e_packer_algorithm +pad_loc_file base/vpr_types.h /^ char *pad_loc_file;$/;" m struct:s_placer_opts +pad_loc_type base/vpr_types.h /^ enum e_pad_loc_type pad_loc_type;$/;" m struct:s_placer_opts typeref:enum:s_placer_opts::e_pad_loc_type +parasitic_net_estimation fpga_spice/fpga_spice_backannotate_utils.c /^void parasitic_net_estimation() {$/;" f file: +parent ../../libarchfpga/include/ezxml.h /^ ezxml_t parent; \/* parent tag, NULL if current tag is root tag *\/$/;" m struct:ezxml +parent power/PowerSpicedComponent.h /^ PowerSpicedComponent * parent;$/;" m class:PowerCallibInputs +parent_mode ../../libarchfpga/include/physical_types.h /^ t_mode * parent_mode;$/;" m struct:s_interconnect +parent_mode ../../libarchfpga/include/physical_types.h /^ t_mode *parent_mode;$/;" m struct:s_pb_type +parent_mode_index ../../libarchfpga/include/physical_types.h /^ int parent_mode_index;$/;" m struct:s_interconnect +parent_node ../../libarchfpga/include/physical_types.h /^ struct s_pb_graph_node *parent_node;$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_node +parent_node route/route_tree_timing.h /^ struct s_rt_node *parent_node;$/;" m struct:s_rt_node typeref:struct:s_rt_node::s_rt_node +parent_pb base/vpr_types.h /^ struct s_pb *parent_pb; \/* pointer to parent node *\/$/;" m struct:s_pb typeref:struct:s_pb::s_pb +parent_pb_graph_node ../../libarchfpga/include/physical_types.h /^ struct s_pb_graph_node *parent_pb_graph_node;$/;" m struct:s_pb_graph_node typeref:struct:s_pb_graph_node::s_pb_graph_node +parent_pb_type ../../libarchfpga/include/physical_types.h /^ struct s_pb_type *parent_pb_type;$/;" m struct:s_mode typeref:struct:s_mode::s_pb_type +parent_pb_type ../../libarchfpga/include/physical_types.h /^ struct s_pb_type *parent_pb_type;$/;" m struct:s_port typeref:struct:s_port::s_pb_type +parent_pin_class ../../libarchfpga/include/physical_types.h /^ int *parent_pin_class; \/* [0..depth-1] the grouping of pins that this particular pin belongs to *\/$/;" m struct:s_pb_graph_pin +parent_spice_model ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model* parent_spice_model;$/;" m struct:s_conf_bit_info +parent_spice_model_index ../../libarchfpga/fpga_spice_include/spice_types.h /^ int parent_spice_model_index;$/;" m struct:s_conf_bit_info +parent_switch route/route_tree_timing.h /^ short parent_switch;$/;" m struct:s_rt_node +parse_direct_pin_name util/vpr_utils.c /^void parse_direct_pin_name(char * src_string, int line, int * start_pin_index, $/;" f +partition fpga_spice/quicksort.c /^int partition(int len, float* sort_value, int pivot_index) {$/;" f file: +partition_index fpga_spice/quicksort.c /^int partition_index(int len, int* sort_index, $/;" f file: +pass_gate_info ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_pass_gate_logic* pass_gate_info;$/;" m struct:s_spice_model_design_tech_info +pass_gate_logic ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_pass_gate_logic* pass_gate_logic;$/;" m struct:s_spice_model +path ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* path;$/;" m struct:s_spice_model_netlist +path ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* path;$/;" m struct:s_spice_tech_lib +path_cost route/route_common.h /^ float path_cost;$/;" m struct:__anon15 +path_criticality base/vpr_types.h /^ float ** path_criticality;$/;" m struct:s_slack +pathfinder_update_cost route/route_common.c /^void pathfinder_update_cost(float pres_fac, float acc_fac) {$/;" f +pathfinder_update_one_cost route/route_common.c /^void pathfinder_update_one_cost(struct s_trace *route_segment_start,$/;" f +pattern_index ../../libarchfpga/include/cad_types.h /^ int pattern_index; \/* index of pattern that this block is a part of *\/$/;" m struct:s_pack_pattern_block +pattern_length ../../libarchfpga/include/physical_types.h /^ int pattern_length;$/;" m struct:s_swseg_pattern_inf +patterns ../../libarchfpga/include/physical_types.h /^ boolean* patterns;$/;" m struct:s_swseg_pattern_inf +pb base/verilog_writer.h /^ t_pb *pb;$/;" m struct:found_pins +pb base/vpr_types.h /^ t_pb *pb;$/;" m struct:s_block +pb base/vpr_types.h /^ t_pb* pb; \/* pb primitive that this block is packed into *\/$/;" m struct:s_logical_block +pb base/vpr_types.h /^ t_pb* pb;$/;" m struct:s_rr_node +pb_graph_head ../../libarchfpga/include/physical_types.h /^ t_pb_graph_node *pb_graph_head;$/;" m struct:s_type_descriptor +pb_graph_node ../../libarchfpga/include/cad_types.h /^ t_pb_graph_node *pb_graph_node;$/;" m struct:s_cluster_placement_primitive +pb_graph_node base/vpr_types.h /^ t_pb_graph_node *pb_graph_node; \/* pointer to pb_graph_node this pb corresponds to *\/$/;" m struct:s_pb +pb_graph_pin base/vpr_types.h /^ t_pb_graph_pin *pb_graph_pin; \/* pb_graph_pin that this block is connected to *\/$/;" m struct:s_tnode +pb_graph_pin base/vpr_types.h /^ t_pb_graph_pin *pb_graph_pin;$/;" m struct:s_rr_node +pb_list base/verilog_writer.h /^}pb_list;$/;" t typeref:struct:found_pins +pb_max_internal_delay base/globals.c /^float pb_max_internal_delay = UNDEFINED; \/* biggest internal delay of physical block *\/$/;" v +pb_node_power ../../libarchfpga/include/physical_types.h /^ t_pb_graph_node_power * pb_node_power;$/;" m struct:s_pb_graph_node +pb_pin_density fpga_spice/fpga_spice_utils.c /^float pb_pin_density(t_rr_node* pb_rr_graph, $/;" f +pb_pin_init_value fpga_spice/fpga_spice_utils.c /^int pb_pin_init_value(t_rr_node* pb_rr_graph, $/;" f +pb_pin_net_num fpga_spice/fpga_spice_utils.c /^int pb_pin_net_num(t_rr_node* pb_rr_graph, $/;" f +pb_pin_probability fpga_spice/fpga_spice_utils.c /^float pb_pin_probability(t_rr_node* pb_rr_graph, $/;" f +pb_stats base/vpr_types.h /^ struct s_pb_stats *pb_stats; \/* statistics for current pb *\/$/;" m struct:s_pb typeref:struct:s_pb::s_pb_stats +pb_type ../../libarchfpga/include/cad_types.h /^ const t_pb_type *pb_type; \/* pb_type that this block is an instance of *\/$/;" m struct:s_pack_pattern_block +pb_type ../../libarchfpga/include/physical_types.h /^ struct s_pb_type *pb_type;$/;" m struct:s_pb_graph_node typeref:struct:s_pb_graph_node::s_pb_type +pb_type ../../libarchfpga/include/physical_types.h /^ struct s_pb_type *pb_type;$/;" m struct:s_type_descriptor typeref:struct:s_type_descriptor::s_pb_type +pb_type_children ../../libarchfpga/include/physical_types.h /^ struct s_pb_type *pb_type_children; \/* [0..num_child_pb_types] *\/$/;" m struct:s_mode typeref:struct:s_mode::s_pb_type +pb_type_power ../../libarchfpga/include/physical_types.h /^ t_pb_type_power * pb_type_power;$/;" m struct:s_pb_type +pb_types ../../libarchfpga/include/logic_types.h /^ struct s_linked_vptr *pb_types; \/* Physical block types that implement this model *\/$/;" m struct:s_model typeref:struct:s_model::s_linked_vptr +pbtype_max_internal_delay base/globals.c /^const t_pb_type *pbtype_max_internal_delay = NULL; \/* physical block type with highest internal delay *\/$/;" v +peak ../../libarchfpga/include/physical_types.h /^ float peak;$/;" m struct:s_chan +period ../../libarchfpga/include/physical_types.h /^ float period; \/* Period of clock *\/$/;" m struct:s_clock_network +period timing/read_sdc.c /^ float period;$/;" m struct:s_sdc_clock file: +pfreq base/vpr_types.h /^enum pfreq {$/;" g +physical_mode_name ../../libarchfpga/include/physical_types.h /^ char* physical_mode_name;$/;" m struct:s_pb_type +physical_mode_num_conf_bits ../../libarchfpga/include/physical_types.h /^ int physical_mode_num_conf_bits;$/;" m struct:s_pb_type +physical_mode_num_iopads ../../libarchfpga/include/physical_types.h /^ int physical_mode_num_iopads;$/;" m struct:s_pb_type +physical_mode_num_reserved_conf_bits ../../libarchfpga/include/physical_types.h /^ int physical_mode_num_reserved_conf_bits;$/;" m struct:s_pb_type +pi ../../libarchfpga/include/ezxml.h /^ char ***pi; \/* processing instructions *\/$/;" m struct:ezxml_root +pic_on_screen base/draw.c /^static enum pic_type pic_on_screen = NO_PICTURE; \/* What do I draw? *\/$/;" v typeref:enum:pic_type file: +pic_type base/vpr_types.h /^enum pic_type {$/;" g +pin_and_chan_adjacent route/check_route.c /^static int pin_and_chan_adjacent(int pin_node, int chan_node) {$/;" f file: +pin_class ../../libarchfpga/include/physical_types.h /^ int *pin_class; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor +pin_class ../../libarchfpga/include/physical_types.h /^ int pin_class;$/;" m struct:s_pb_graph_pin +pin_count_in_cluster ../../libarchfpga/include/physical_types.h /^ int pin_count_in_cluster;$/;" m struct:s_pb_graph_pin +pin_count_in_cluster pack/pb_type_graph.c /^static int pin_count_in_cluster;$/;" v file: +pin_criticality place/timing_place_lookup.c /^static float *pin_criticality;$/;" v file: +pin_dens power/power_util.c /^float pin_dens(t_pb * pb, t_pb_graph_pin * pin) {$/;" f +pin_height ../../libarchfpga/include/physical_types.h /^ int *pin_height; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor +pin_index_per_side ../../libarchfpga/include/physical_types.h /^ int* pin_index_per_side;$/;" m struct:s_type_descriptor +pin_loc_assignments ../../libarchfpga/include/physical_types.h /^ char ****pin_loc_assignments; \/* [0..height-1][0..3][0..num_tokens-1][0..string_name] *\/$/;" m struct:s_type_descriptor +pin_location_distribution ../../libarchfpga/include/physical_types.h /^ enum e_pin_location_distr pin_location_distribution;$/;" m struct:s_type_descriptor typeref:enum:s_type_descriptor::e_pin_location_distr +pin_number ../../libarchfpga/include/physical_types.h /^ int pin_number;$/;" m struct:s_pb_graph_pin +pin_power ../../libarchfpga/include/physical_types.h /^ t_pb_graph_pin_power * pin_power;$/;" m struct:s_pb_graph_pin +pin_prefer_side base/vpr_types.h /^ int** pin_prefer_side; \/* [0..num_pins-1][0..3] *\/$/;" m struct:s_block +pin_prob power/power_util.c /^float pin_prob(t_pb * pb, t_pb_graph_pin * pin) {$/;" f +pin_ptc_to_side ../../libarchfpga/include/physical_types.h /^ int* pin_ptc_to_side;$/;" m struct:s_type_descriptor +pin_side_count clb_pin_remap/clb_pin_remap_util.c /^int pin_side_count(int pin_side[]) {$/;" f +pin_size base/draw.c /^static float tile_width, pin_size;$/;" v file: +pin_timing ../../libarchfpga/include/physical_types.h /^ struct s_pb_graph_pin** pin_timing; \/* primitive ipin to opin timing *\/$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_pin +pin_timing_del_max ../../libarchfpga/include/physical_types.h /^ float *pin_timing_del_max; \/* primitive ipin to opin timing *\/$/;" m struct:s_pb_graph_pin +pin_toggle_initialized ../../libarchfpga/include/physical_types.h /^ boolean pin_toggle_initialized;$/;" m struct:s_port_power +pinlist ../../libarchfpga/include/physical_types.h /^ int *pinlist; \/* [0..num_pins - 1] *\/$/;" m struct:s_class +pinloc ../../libarchfpga/include/physical_types.h /^ int ***pinloc; \/* [0..height-1][0..3][0..num_pins-1] *\/$/;" m struct:s_type_descriptor +pl_macros place/place.c /^static t_pl_macro * pl_macros = NULL;$/;" v file: +place_algorithm base/vpr_types.h /^ enum e_place_algorithm place_algorithm;$/;" m struct:s_placer_opts typeref:enum:s_placer_opts::e_place_algorithm +place_and_route base/place_and_route.c /^void place_and_route(enum e_operation operation,$/;" f +place_chan_width base/vpr_types.h /^ int place_chan_width;$/;" m struct:s_placer_opts +place_clb_pin_remap base/vpr_types.h /^ boolean place_clb_pin_remap;$/;" m struct:s_placer_opts +place_cost_exp base/ReadOptions.h /^ float place_cost_exp;$/;" m struct:s_options +place_cost_exp base/vpr_types.h /^ float place_cost_exp;$/;" m struct:s_placer_opts +place_exp_first base/ReadOptions.h /^ float place_exp_first;$/;" m struct:s_options +place_exp_last base/ReadOptions.h /^ float place_exp_last;$/;" m struct:s_options +place_freq base/vpr_types.h /^ enum pfreq place_freq;$/;" m struct:s_placer_opts typeref:enum:s_placer_opts::pfreq +placement_index ../../libarchfpga/include/physical_types.h /^ int placement_index;$/;" m struct:s_pb_graph_node +pmos_size ../../libarchfpga/fpga_spice_include/spice_types.h /^ float pmos_size;$/;" m struct:s_spice_model_pass_gate_logic +pmos_subckt_name spice/spice_globals.c /^char* pmos_subckt_name = "vpr_pmos";$/;" v +pn_ratio ../../libarchfpga/fpga_spice_include/spice_types.h /^ float pn_ratio;$/;" m struct:s_spice_tech_lib +point_to_point_delay_cost place/place.c /^static float **point_to_point_delay_cost = NULL;$/;" v file: +point_to_point_timing_cost place/place.c /^static float **point_to_point_timing_cost = NULL;$/;" v file: +poly base/graphics.c /^ int poly[3][2]; $/;" m struct:__anon4 file: +port ../../libarchfpga/include/physical_types.h /^ t_port *port;$/;" m struct:s_pb_graph_pin +port_class ../../libarchfpga/include/physical_types.h /^ char * port_class;$/;" m struct:s_port +port_index_by_type ../../libarchfpga/include/physical_types.h /^ int port_index_by_type;$/;" m struct:s_port +port_info_initialized ../../libarchfpga/include/physical_types.h /^ boolean port_info_initialized;$/;" m struct:s_interconnect_power +port_power ../../libarchfpga/include/physical_types.h /^ t_port_power * port_power;$/;" m struct:s_port +ports ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_port* ports;$/;" m struct:s_spice_model +ports ../../libarchfpga/include/physical_types.h /^ t_port *ports; \/* [0..num_ports] *\/$/;" m struct:s_pb_type +post ../../libarchfpga/fpga_spice_include/spice_types.h /^ int post;$/;" m struct:s_spice_params +post_place_sync base/place_and_route.c /^void post_place_sync(INP int L_num_blocks,$/;" f +postscript base/graphics.c /^postscript (void (*drawscreen) (void)) $/;" f file: +power ../../libarchfpga/include/physical_types.h /^ t_power_arch * power;$/;" m struct:s_arch +power power/PowerSpicedComponent.h /^ float power;$/;" m class:PowerCallibSize +power_MTAs power/power_sizing.c /^static double power_MTAs(float W_size) {$/;" f file: +power_MTAs_L power/power_sizing.c /^static double power_MTAs_L(float L_size) {$/;" f file: +power_add_usage power/power_util.c /^void power_add_usage(t_power_usage * dest, const t_power_usage * src) {$/;" f +power_alloc_and_init_pb_pin power/power.c /^void power_alloc_and_init_pb_pin(t_pb_graph_pin * pin) {$/;" f +power_buffer_size ../../libarchfpga/include/physical_types.h /^ float power_buffer_size;$/;" m struct:s_switch_inf +power_buffer_size_from_logical_effort power/power_util.c /^float power_buffer_size_from_logical_effort(float C_load) {$/;" f +power_buffer_type ../../libarchfpga/include/physical_types.h /^ e_power_buffer_type power_buffer_type;$/;" m struct:s_switch_inf +power_calc_buffer_num_stages power/power_util.c /^int power_calc_buffer_num_stages(float final_stage_size,$/;" f +power_calc_buffer_size_from_Cout power/power_lowlevel.c /^float power_calc_buffer_size_from_Cout(float C_out) {$/;" f +power_calc_leakage_gate power/power_lowlevel.c /^static float power_calc_leakage_gate(e_tx_type transistor_type, float size) {$/;" f file: +power_calc_leakage_st power/power_lowlevel.c /^static float power_calc_leakage_st(e_tx_type transistor_type, float size) {$/;" f file: +power_calc_leakage_st_pass_transistor power/power_lowlevel.c /^static float power_calc_leakage_st_pass_transistor(float size, float v_ds) {$/;" f file: +power_calc_mux_v_out power/power_lowlevel.c /^float power_calc_mux_v_out(int num_inputs, float transistor_size, float v_in,$/;" f +power_calc_node_switching power/power_lowlevel.c /^float power_calc_node_switching(float capacitance, float density,$/;" f +power_calc_node_switching_v power/power_lowlevel.c /^static float power_calc_node_switching_v(float capacitance, float density,$/;" f file: +power_calc_transistor_capacitance power/power_lowlevel.c /^static void power_calc_transistor_capacitance(float *C_d, float *C_s,$/;" f file: +power_callib_period power/power_callibrate.h /^const float power_callib_period = 5e-9;$/;" v +power_callibrate power/power_callibrate.c /^void power_callibrate(void) {$/;" f +power_compare_buffer_sc_levr power/power_cmos_tech.c /^static int power_compare_buffer_sc_levr(const void * key_void,$/;" f file: +power_compare_buffer_strength power/power_cmos_tech.c /^static int power_compare_buffer_strength(const void * key_void,$/;" f file: +power_compare_leakage_pair power/power_cmos_tech.c /^static int power_compare_leakage_pair(const void * key_void,$/;" f file: +power_compare_transistor_size power/power_cmos_tech.c /^static int power_compare_transistor_size(const void * key_void,$/;" f file: +power_compare_voltage_pair power/power_cmos_tech.c /^static int power_compare_voltage_pair(const void * key_void,$/;" f file: +power_component_add_usage power/power_components.c /^void power_component_add_usage(t_power_usage * power_usage,$/;" f +power_component_get_usage power/power_components.c /^void power_component_get_usage(t_power_usage * power_usage,$/;" f +power_component_get_usage_sum power/power_components.c /^float power_component_get_usage_sum(e_power_component_type component_idx) {$/;" f +power_components_init power/power_components.c /^void power_components_init(void) {$/;" f +power_components_uninit power/power_components.c /^void power_components_uninit(void) {$/;" f +power_count_transistor_SRAM_bit power/power_sizing.c /^static double power_count_transistor_SRAM_bit(void) {$/;" f file: +power_count_transistors_FF power/power_sizing.c /^static double power_count_transistors_FF(float size) {$/;" f file: +power_count_transistors_LUT power/power_sizing.c /^static double power_count_transistors_LUT(int LUT_inputs,$/;" f file: +power_count_transistors_buffer power/power_sizing.c /^double power_count_transistors_buffer(float buffer_size) {$/;" f +power_count_transistors_connectionbox power/power_sizing.c /^static double power_count_transistors_connectionbox(void) {$/;" f file: +power_count_transistors_interc power/power_sizing.c /^static double power_count_transistors_interc(t_interconnect * interc) {$/;" f file: +power_count_transistors_inv power/power_sizing.c /^static double power_count_transistors_inv(float size) {$/;" f file: +power_count_transistors_levr power/power_sizing.c /^static double power_count_transistors_levr() {$/;" f file: +power_count_transistors_mux power/power_sizing.c /^static double power_count_transistors_mux(t_mux_arch * mux_arch) {$/;" f file: +power_count_transistors_mux_node power/power_sizing.c /^static double power_count_transistors_mux_node(t_mux_node * mux_node,$/;" f file: +power_count_transistors_pb_node power/power_sizing.c /^static double power_count_transistors_pb_node(t_pb_graph_node * pb_node) {$/;" f file: +power_count_transistors_primitive power/power_sizing.c /^static double power_count_transistors_primitive(t_pb_type * pb_type) {$/;" f file: +power_count_transistors_switchbox power/power_sizing.c /^static double power_count_transistors_switchbox(t_arch * arch) {$/;" f file: +power_count_transistors_trans_gate power/power_sizing.c /^static double power_count_transistors_trans_gate(float size) {$/;" f file: +power_estimation_method_name power/power.c /^static char * power_estimation_method_name($/;" f file: +power_find_buffer_sc_levr power/power_cmos_tech.c /^void power_find_buffer_sc_levr(t_power_buffer_sc_levr_inf ** lower,$/;" f +power_find_buffer_strength_inf power/power_cmos_tech.c /^void power_find_buffer_strength_inf(t_power_buffer_strength_inf ** lower,$/;" f +power_find_mux_volt_inf power/power_cmos_tech.c /^void power_find_mux_volt_inf(t_power_mux_volt_pair ** lower,$/;" f +power_find_nmos_leakage power/power_cmos_tech.c /^void power_find_nmos_leakage(t_power_nmos_leakage_inf * nmos_leakage_info,$/;" f +power_find_transistor_info power/power_cmos_tech.c /^boolean power_find_transistor_info(t_transistor_size_inf ** lower,$/;" f +power_gated ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean power_gated;$/;" m struct:s_spice_model_design_tech_info +power_get_mux_arch power/power_util.c /^t_mux_arch * power_get_mux_arch(int num_mux_inputs, float transistor_size) {$/;" f +power_init power/power.c /^boolean power_init(char * power_out_filepath,$/;" f +power_init_pb_pins_rec power/power.c /^void power_init_pb_pins_rec(t_pb_graph_node * pb_node) {$/;" f +power_log_msg power/power_util.c /^void power_log_msg(e_power_log_type log_type, char * msg) {$/;" f +power_lowlevel_init power/power_lowlevel.c /^void power_lowlevel_init() {$/;" f +power_method_inherited ../../libarchfpga/read_xml_arch_file.c /^e_power_estimation_method power_method_inherited($/;" f +power_method_is_recursive power/power_util.c /^boolean power_method_is_recursive(e_power_estimation_method method) {$/;" f +power_method_is_transistor_level power/power_util.c /^boolean power_method_is_transistor_level($/;" f +power_mux_node_max_inputs power/power_sizing.c /^static void power_mux_node_max_inputs(t_mux_node * mux_node,$/;" f file: +power_pb_pins_init power/power.c /^void power_pb_pins_init() {$/;" f +power_perc_dynamic power/power_util.c /^float power_perc_dynamic(t_power_usage * power_usage) {$/;" f +power_print_breakdown_component power/power.c /^static void power_print_breakdown_component(FILE * fp, char * name,$/;" f file: +power_print_breakdown_entry power/power.c /^static void power_print_breakdown_entry(FILE * fp, int indent,$/;" f file: +power_print_breakdown_pb power/power.c /^static void power_print_breakdown_pb(FILE * fp) {$/;" f file: +power_print_breakdown_pb_rec power/power.c /^static void power_print_breakdown_pb_rec(FILE * fp, t_pb_type * pb_type,$/;" f file: +power_print_breakdown_summary power/power.c /^static void power_print_breakdown_summary(FILE * fp) {$/;" f file: +power_print_spice_comparison power/power_callibrate.c /^void power_print_spice_comparison(void) {$/;" f +power_print_summary power/power.c /^static void power_print_summary(FILE * fp, t_vpr_setup vpr_setup) {$/;" f file: +power_print_title power/power_util.c /^void power_print_title(FILE * fp, char * title) {$/;" f +power_reset_pb_type power/power.c /^static void power_reset_pb_type(t_pb_type * pb_type) {$/;" f file: +power_reset_tile_usage power/power.c /^static void power_reset_tile_usage(void) {$/;" f file: +power_routing_init power/power.c /^void power_routing_init(t_det_routing_arch * routing_arch) {$/;" f +power_scale_usage power/power_util.c /^void power_scale_usage(t_power_usage * power_usage, float scale_factor) {$/;" f +power_size_pb power/power_sizing.c /^static void power_size_pb(void) {$/;" f file: +power_size_pb_rec power/power_sizing.c /^static void power_size_pb_rec(t_pb_graph_node * pb_node) {$/;" f file: +power_size_pin_buffers_and_wires power/power_sizing.c /^static void power_size_pin_buffers_and_wires(t_pb_graph_pin * pin,$/;" f file: +power_size_pin_to_interconnect power/power_sizing.c /^static void power_size_pin_to_interconnect(t_interconnect * interc,$/;" f file: +power_sizing_init power/power_sizing.c /^void power_sizing_init(t_arch * arch) {$/;" f +power_sum_usage power/power_util.c /^float power_sum_usage(t_power_usage * power_usage) {$/;" f +power_tech_init power/power_cmos_tech.c /^void power_tech_init(char * cmos_tech_behavior_filepath) {$/;" f +power_tech_load_xml_file power/power_cmos_tech.c /^void power_tech_load_xml_file(char * cmos_tech_behavior_filepath) {$/;" f +power_tech_xml_load_component power/power_cmos_tech.c /^static void power_tech_xml_load_component(ezxml_t parent,$/;" f file: +power_tech_xml_load_components power/power_cmos_tech.c /^static void power_tech_xml_load_components(ezxml_t parent) {$/;" f file: +power_tech_xml_load_multiplexer_info power/power_cmos_tech.c /^static void power_tech_xml_load_multiplexer_info(ezxml_t parent) {$/;" f file: +power_tech_xml_load_nmos_st_leakages power/power_cmos_tech.c /^static void power_tech_xml_load_nmos_st_leakages(ezxml_t parent) {$/;" f file: +power_total power/power.c /^e_power_ret_code power_total(float * run_time_s, t_vpr_setup vpr_setup,$/;" f +power_transistor_area power/power_sizing.c /^double power_transistor_area(double num_MTAs) {$/;" f +power_transistors_for_pb_node power/power_sizing.c /^static double power_transistors_for_pb_node(t_pb_graph_node * pb_node) {$/;" f file: +power_transistors_per_tile power/power_sizing.c /^static double power_transistors_per_tile(t_arch * arch) {$/;" f file: +power_uninit power/power.c /^boolean power_uninit(void) {$/;" f +power_usage ../../libarchfpga/include/physical_types.h /^ t_power_usage power_usage; \/* Power usage of this mode *\/$/;" m struct:s_mode_power +power_usage ../../libarchfpga/include/physical_types.h /^ t_power_usage power_usage; \/* Total power usage of this pb type *\/$/;" m struct:s_pb_type_power +power_usage ../../libarchfpga/include/physical_types.h /^ t_power_usage power_usage;$/;" m struct:s_interconnect_power +power_usage_MUX2_transmission power/power_lowlevel.c /^void power_usage_MUX2_transmission(t_power_usage * power_usage, float size,$/;" f +power_usage_blocks power/power.c /^static void power_usage_blocks(t_power_usage * power_usage) {$/;" f file: +power_usage_buf_for_callibration power/power_callibrate.c /^float power_usage_buf_for_callibration(int num_inputs, float transistor_size) {$/;" f +power_usage_buf_levr_for_callibration power/power_callibrate.c /^float power_usage_buf_levr_for_callibration(int num_inputs,$/;" f +power_usage_buffer power/power_components.c /^void power_usage_buffer(t_power_usage * power_usage, float size, float in_prob,$/;" f +power_usage_bufs_wires ../../libarchfpga/include/physical_types.h /^ t_power_usage power_usage_bufs_wires; \/* Power dissipated in local buffers and wire switching (Subset of total power) *\/$/;" m struct:s_pb_type_power +power_usage_clock power/power.c /^static void power_usage_clock(t_power_usage * power_usage,$/;" f file: +power_usage_clock_single power/power.c /^static void power_usage_clock_single(t_power_usage * power_usage,$/;" f file: +power_usage_ff power/power_components.c /^void power_usage_ff(t_power_usage * power_usage, float size, float D_prob,$/;" f +power_usage_ff_for_callibration power/power_callibrate.c /^float power_usage_ff_for_callibration(int num_inputs, float transistor_size) {$/;" f +power_usage_inverter power/power_lowlevel.c /^void power_usage_inverter(t_power_usage * power_usage, float in_dens,$/;" f +power_usage_inverter_irregular power/power_lowlevel.c /^void power_usage_inverter_irregular(t_power_usage * power_usage,$/;" f +power_usage_level_restorer power/power_lowlevel.c /^void power_usage_level_restorer(t_power_usage * power_usage,$/;" f +power_usage_local_buffers_and_wires power/power.c /^static void power_usage_local_buffers_and_wires(t_power_usage * power_usage,$/;" f file: +power_usage_local_interc_mux power/power_components.c /^void power_usage_local_interc_mux(t_power_usage * power_usage, t_pb * pb,$/;" f +power_usage_local_pin_buffer_and_wire power/power.c /^void power_usage_local_pin_buffer_and_wire(t_power_usage * power_usage,$/;" f +power_usage_local_pin_toggle power/power.c /^void power_usage_local_pin_toggle(t_power_usage * power_usage, t_pb * pb,$/;" f +power_usage_lut power/power_components.c /^void power_usage_lut(t_power_usage * power_usage, int lut_size,$/;" f +power_usage_lut_for_callibration power/power_callibrate.c /^float power_usage_lut_for_callibration(int num_inputs, float transistor_size) {$/;" f +power_usage_mux_for_callibration power/power_callibrate.c /^float power_usage_mux_for_callibration(int num_inputs, float transistor_size) {$/;" f +power_usage_mux_multilevel power/power_components.c /^void power_usage_mux_multilevel(t_power_usage * power_usage,$/;" f +power_usage_mux_rec power/power_components.c /^static void power_usage_mux_rec(t_power_usage * power_usage, float * out_prob,$/;" f file: +power_usage_mux_singlelevel_dynamic power/power_lowlevel.c /^void power_usage_mux_singlelevel_dynamic(t_power_usage * power_usage,$/;" f +power_usage_mux_singlelevel_static power/power_lowlevel.c /^void power_usage_mux_singlelevel_static(t_power_usage * power_usage,$/;" f +power_usage_pb power/power.c /^static void power_usage_pb(t_power_usage * power_usage, t_pb * pb,$/;" f file: +power_usage_primitive power/power.c /^static void power_usage_primitive(t_power_usage * power_usage, t_pb * pb,$/;" f file: +power_usage_routing power/power.c /^static void power_usage_routing(t_power_usage * power_usage,$/;" f file: +power_usage_wire power/power_lowlevel.c /^void power_usage_wire(t_power_usage * power_usage, float capacitance,$/;" f +power_zero_usage power/power_util.c /^void power_zero_usage(t_power_usage * power_usage) {$/;" f +prefer_side base/vpr_types.h /^ int** prefer_side; \/* [0..num_sinks][0..3] *\/$/;" m struct:s_net +prefix ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* prefix; $/;" m struct:s_spice_model_port +prefix ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* prefix; \/* Prefix when it show up in the spice netlist *\/$/;" m struct:s_spice_model +prepacked_data base/vpr_types.h /^ t_prepacked_tnode_data * prepacked_data;$/;" m struct:s_tnode +pres_cost route/route_common.h /^ float pres_cost;$/;" m struct:__anon15 +pres_fac pack/cluster_legality.c /^static float pres_fac;$/;" v file: +pres_fac_mult base/ReadOptions.h /^ float pres_fac_mult;$/;" m struct:s_options +pres_fac_mult base/vpr_types.h /^ float pres_fac_mult;$/;" m struct:s_router_opts +prev_edge base/vpr_types.h /^ int prev_edge;$/;" m struct:s_rr_node +prev_edge route/route_common.h /^ int prev_edge;$/;" m struct:s_heap +prev_edge route/route_common.h /^ short prev_edge;$/;" m struct:__anon15 +prev_edge_in_pack base/vpr_types.h /^ int prev_edge_in_pack;$/;" m struct:s_rr_node +prev_node base/vpr_types.h /^ int prev_node;$/;" m struct:s_rr_node +prev_node route/route_common.h /^ int prev_node;$/;" m union:s_heap::__anon14 +prev_node route/route_common.h /^ int prev_node;$/;" m struct:__anon15 +prev_node_in_pack base/vpr_types.h /^ int prev_node_in_pack; $/;" m struct:s_rr_node +prevconnectiongainincr base/vpr_types.h /^ std::map prevconnectiongainincr; \/* [0..num_logical_blocks-1] Prev sum to weighted sum of connections to attraction function *\/$/;" m struct:s_pb_stats +primitive_feasible pack/cluster.c /^static boolean primitive_feasible(int iblk, t_pb *cur_pb) {$/;" f file: +primitive_type_and_memory_feasible pack/cluster.c /^static boolean primitive_type_and_memory_feasible(int iblk,$/;" f file: +primitive_type_feasible util/vpr_utils.c /^boolean primitive_type_feasible(int iblk, const t_pb_type *cur_pb_type) {$/;" f +printClusteredNetlistStats base/ShowSetup.c /^void printClusteredNetlistStats() {$/;" f +print_array place/timing_place_lookup.c /^print_array(float **array_to_print,$/;" f file: +print_block_criticalities pack/cluster.c /^static void print_block_criticalities(const char * fname) {$/;" f file: +print_clb_placement place/place.c /^static void print_clb_placement(const char *fname) {$/;" f file: +print_clustering_timing_info timing/path_delay.c /^void print_clustering_timing_info(const char *fname) {$/;" f +print_clusters pack/output_blif.c /^static void print_clusters(t_block *clb, int num_clusters, FILE * fpout) {$/;" f file: +print_clusters pack/output_clustering.c /^static void print_clusters(t_block *clb, int num_clusters, FILE * fpout) {$/;" f file: +print_complete_net_trace base/vpr_api.c /^static void print_complete_net_trace(t_trace* trace, const char *file_name) {$/;" f file: +print_critical_path timing/path_delay.c /^void print_critical_path(const char *fname) {$/;" f +print_critical_path_node timing/path_delay2.c /^float print_critical_path_node(FILE * fp, t_linked_int * critical_path_node) {$/;" f +print_criticality timing/path_delay.c /^void print_criticality(t_slack * slacks, boolean criticality_is_normalized, const char *fname) {$/;" f +print_distribution route/rr_graph.c /^print_distribution(FILE * fptr,$/;" f file: +print_global_criticality_stats timing/path_delay.c /^static void print_global_criticality_stats(FILE * fp, float ** criticality, const char * singular_name, const char * capitalized_plural_name) {$/;" f file: +print_help ../../libarchfpga/main.c /^void print_help() {$/;" f +print_int_matrix3 ../../libarchfpga/util.c /^void print_int_matrix3(int ***vptr, int nrmin, int nrmax, int ncmin, int ncmax,$/;" f +print_interconnect pack/output_clustering.c /^static void print_interconnect(int inode, int *column, int num_tabs,$/;" f file: +print_lambda base/stats.c /^void print_lambda(void) {$/;" f +print_lut_remapping timing/path_delay.c /^void print_lut_remapping(const char *fname) {$/;" f +print_net_delay timing/path_delay.c /^void print_net_delay(float **net_delay, const char *fname) {$/;" f +print_net_name pack/output_blif.c /^static void print_net_name(int inet, int *column, FILE * fpout) {$/;" f file: +print_net_name pack/output_clustering.c /^static void print_net_name(int inet, int *column, int num_tabs, FILE * fpout) {$/;" f file: +print_net_opin_llist route/pb_pin_eq_auto_detect.c /^void print_net_opin_llist(t_llist* head) {$/;" f +print_net_opin_occupancy route/pb_pin_eq_auto_detect.c /^void print_net_opin_occupancy() {$/;" f +print_netlist pack/print_netlist.c /^void print_netlist(char *foutput, char *net_file) {$/;" f +print_open_pb_graph_node pack/output_clustering.c /^static void print_open_pb_graph_node(t_pb_graph_node * pb_graph_node,$/;" f file: +print_pack_molecules pack/prepack.c /^static void print_pack_molecules(INP const char *fname,$/;" f file: +print_pb pack/output_blif.c /^static void print_pb(FILE *fpout, t_pb * pb, int clb_index) {$/;" f file: +print_pb pack/output_clustering.c /^static void print_pb(FILE *fpout, t_pb * pb, int pb_index, int tab_depth) {$/;" f file: +print_pinnum pack/print_netlist.c /^static void print_pinnum(FILE * fp, int pinnum) {$/;" f file: +print_place base/read_place.c /^void print_place(char *place_file, char *net_file, char *arch_file) {$/;" f +print_primitive pack/output_blif.c /^static void print_primitive(FILE *fpout, int iblk) {$/;" f file: +print_primitive_as_blif timing/path_delay.c /^static void print_primitive_as_blif (FILE *fpout, int iblk) {$/;" f file: +print_relative_pos_distr place/place_stats.c /^print_relative_pos_distr(void)$/;" f +print_route route/route_common.c /^void print_route(char *route_file) {$/;" f +print_rr_indexed_data route/rr_graph.c /^void print_rr_indexed_data(FILE * fp, int index) {$/;" f +print_rr_node route/rr_graph.c /^void print_rr_node(FILE * fp, t_rr_node * L_rr_node, int inode) {$/;" f +print_sink_delays place/timing_place.c /^void print_sink_delays(const char *fname) {$/;" f +print_slack timing/path_delay.c /^void print_slack(float ** slack, boolean slack_is_normalized, const char *fname) {$/;" f +print_spaces timing/path_delay.c /^static void print_spaces(FILE * fp, int num_spaces) {$/;" f file: +print_stat_memristor_buffer mrfpga/buffer_insertion.c /^int print_stat_memristor_buffer( char* fname, float buffer_size )$/;" f +print_stats pack/output_clustering.c /^static void print_stats(t_block *clb, int num_clusters) {$/;" f file: +print_string pack/output_blif.c /^static void print_string(const char *str_ptr, int *column, FILE * fpout) {$/;" f file: +print_string pack/output_clustering.c /^static void print_string(const char *str_ptr, int *column, int num_tabs, FILE * fpout) {$/;" f file: +print_tabs pack/output_clustering.c /^static void print_tabs(FILE *fpout, int num_tabs) {$/;" f file: +print_tabs util/vpr_utils.c /^void print_tabs(FILE * fpout, int num_tab) {$/;" f +print_timing_constraint_info timing/path_delay.c /^static void print_timing_constraint_info(const char *fname) {$/;" f file: +print_timing_graph timing/path_delay.c /^void print_timing_graph(const char *fname) {$/;" f +print_timing_graph_as_blif timing/path_delay.c /^void print_timing_graph_as_blif (const char *fname, t_model *models) {$/;" f +print_timing_stats timing/path_delay.c /^void print_timing_stats(void) {$/;" f +print_wirelen_prob_dist base/stats.c /^void print_wirelen_prob_dist(void) {$/;" f +priority ../../libarchfpga/include/physical_types.h /^ int priority;$/;" m struct:s_grid_loc_def +private_cmap base/graphics.c /^static Colormap private_cmap; \/* "None" unless a private cmap was allocated. *\/$/;" v file: +prob ../../libarchfpga/include/physical_types.h /^ float prob; \/* Static probability of net assigned to this clock *\/$/;" m struct:s_clock_network +probability ../../libarchfpga/fpga_spice_include/spice_types.h /^ float probability;$/;" m struct:s_spice_net_info +probability base/vpr_types.h /^ float probability;$/;" m struct:s_net_power +proc_time base/place_and_route.h /^ int proc_time;$/;" m struct:s_fmap_cell +proceed base/graphics.c /^proceed (void (*drawscreen) (void)) $/;" f file: +processComplexBlock base/read_netlist.c /^static void processComplexBlock(INOUTP ezxml_t Parent, INOUTP t_block *cb,$/;" f file: +processPb base/read_netlist.c /^static void processPb(INOUTP ezxml_t Parent, INOUTP t_pb* pb,$/;" f file: +processPorts base/read_netlist.c /^static void processPorts(INOUTP ezxml_t Parent, INOUTP t_pb* pb,$/;" f file: +process_constraints timing/path_delay.c /^static void process_constraints(void) {$/;" f file: +process_settings base/read_settings.c /^static int process_settings(ezxml_t Cur, char ** outv)$/;" f file: +process_tech_xml_load_transistor_info power/power_cmos_tech.c /^static void process_tech_xml_load_transistor_info(ezxml_t parent) {$/;" f file: +prog_clock_freq ../../libarchfpga/fpga_spice_include/spice_types.h /^ float prog_clock_freq; \/* Programming clock frequency, used during programming phase only *\/$/;" m struct:s_spice_stimulate_params +prop ../../libarchfpga/include/physical_types.h /^ int * prop; \/* [0..num_value_prop_pairs - 1] *\/$/;" m struct:s_pin_to_pin_annotation +propagate_clock_domain_and_skew timing/path_delay.c /^static void propagate_clock_domain_and_skew(int inode) {$/;" f file: +ps base/graphics.c /^static FILE *ps;$/;" v file: +ps_bot base/graphics.c /^static float ps_left, ps_right, ps_top, ps_bot; \/* Figure boundaries for *$/;" v file: +ps_cnames base/graphics.c /^static const char *ps_cnames[NUM_COLOR] = {"white", "black", "grey55", "grey75",$/;" v file: +ps_left base/graphics.c /^static float ps_left, ps_right, ps_top, ps_bot; \/* Figure boundaries for *$/;" v file: +ps_right base/graphics.c /^static float ps_left, ps_right, ps_top, ps_bot; \/* Figure boundaries for *$/;" v file: +ps_top base/graphics.c /^static float ps_left, ps_right, ps_top, ps_bot; \/* Figure boundaries for *$/;" v file: +ps_xmult base/graphics.c /^static float ps_xmult, ps_ymult; \/* Transformation for PostScript. *\/$/;" v file: +ps_xmult base/graphics.h /^ float ps_xmult, ps_ymult;$/;" m struct:__anon6 +ps_ymult base/graphics.c /^static float ps_xmult, ps_ymult; \/* Transformation for PostScript. *\/$/;" v file: +ps_ymult base/graphics.h /^ float ps_xmult, ps_ymult;$/;" m struct:__anon6 +pt_on_object base/graphics.c /^int pt_on_object(float x, float y) { }$/;" f +pt_on_object base/graphics.c /^int pt_on_object(int all, float x, float y) {$/;" f +ptc_num base/vpr_types.h /^ short ptc_num;$/;" m struct:s_rr_node +ptr timing/slre.c /^ const char *ptr; \/\/ Pointer to the substring$/;" m struct:cap file: +pwh ../../libarchfpga/fpga_spice_include/spice_types.h /^ float pwh;$/;" m struct:s_spice_net_info +pwl ../../libarchfpga/fpga_spice_include/spice_types.h /^ float pwl;$/;" m struct:s_spice_net_info +quantifier timing/slre.c /^static void quantifier(struct slre *r, int prev, int op) {$/;" f file: +quicksort_float fpga_spice/quicksort.c /^void quicksort_float(int len, $/;" f +quicksort_float_index fpga_spice/quicksort.c /^void quicksort_float_index(int len, $/;" f +quit base/graphics.c /^quit (void (*drawscreen) (void)) $/;" f file: +rc_node timing/net_delay_types.h /^ struct s_rc_node *rc_node;$/;" m struct:s_linked_rc_ptr typeref:struct:s_linked_rc_ptr::s_rc_node +re_expand route/route_tree_timing.h /^ short re_expand;$/;" m struct:s_rt_node +read ../../libarchfpga/ezxml.c 59;" d file: +read_act_file base/vpr_types.h /^ boolean read_act_file;$/;" m struct:s_fpga_spice_opts +read_activity base/read_blif.c /^static void read_activity(char * activity_file) {$/;" f file: +read_and_process_blif base/read_blif.c /^void read_and_process_blif(char *blif_file,$/;" f +read_blif base/read_blif.c /^static void read_blif(char *blif_file, boolean sweep_hanging_nets_and_inputs,$/;" f file: +read_netlist base/read_netlist.c /^void read_netlist(INP const char *net_file, INP const t_arch *arch,$/;" f +read_place base/read_place.c /^void read_place(INP const char *place_file, INP const char *arch_file,$/;" f +read_sdc timing/read_sdc.c /^void read_sdc(t_timing_inf timing_inf) {$/;" f +read_settings base/ReadOptions.h /^ int read_settings;$/;" m struct:s_options +read_settings_file base/read_settings.c /^int read_settings_file(char * file_name, char *** outv)$/;" f +read_user_pad_loc base/read_place.c /^void read_user_pad_loc(char *pad_loc_file) {$/;" f +read_xml_spice ../../libarchfpga/include/physical_types.h /^ boolean read_xml_spice;$/;" m struct:s_arch +realloc_and_load_pb_graph_pin_ptrs_at_var pack/pb_type_graph.c /^static boolean realloc_and_load_pb_graph_pin_ptrs_at_var(INP int line_num,$/;" f file: +reassign_rr_node_net_num_from_scratch route/pb_pin_eq_auto_detect.c /^void reassign_rr_node_net_num_from_scratch() {$/;" f +rec_add_pb_type_keywords_to_list fpga_spice/fpga_spice_setup.c /^void rec_add_pb_type_keywords_to_list(t_pb_type* cur_pb_type,$/;" f file: +rec_backannotate_rr_node_net_num fpga_spice/fpga_spice_backannotate_utils.c /^void rec_backannotate_rr_node_net_num(int LL_num_rr_nodes,$/;" f +rec_count_num_conf_bits_pb fpga_spice/fpga_spice_utils.c /^int rec_count_num_conf_bits_pb(t_pb* cur_pb, $/;" f +rec_count_num_conf_bits_pb_type_default_mode fpga_spice/fpga_spice_utils.c /^int rec_count_num_conf_bits_pb_type_default_mode(t_pb_type* cur_pb_type,$/;" f +rec_count_num_conf_bits_pb_type_physical_mode fpga_spice/fpga_spice_utils.c /^int rec_count_num_conf_bits_pb_type_physical_mode(t_pb_type* cur_pb_type,$/;" f +rec_count_num_iopads_pb fpga_spice/fpga_spice_utils.c /^void rec_count_num_iopads_pb(t_pb* cur_pb) {$/;" f +rec_count_num_iopads_pb_type_default_mode fpga_spice/fpga_spice_utils.c /^void rec_count_num_iopads_pb_type_default_mode(t_pb_type* cur_pb_type) {$/;" f +rec_count_num_iopads_pb_type_physical_mode fpga_spice/fpga_spice_utils.c /^void rec_count_num_iopads_pb_type_physical_mode(t_pb_type* cur_pb_type) {$/;" f +rec_count_num_mode_bits_pb fpga_spice/fpga_spice_utils.c /^void rec_count_num_mode_bits_pb(t_pb* cur_pb) {$/;" f +rec_count_num_mode_bits_pb_type_default_mode fpga_spice/fpga_spice_utils.c /^void rec_count_num_mode_bits_pb_type_default_mode(t_pb_type* cur_pb_type) {$/;" f +rec_dump_conf_bits_to_bitstream_file fpga_spice/fpga_spice_bitstream.c /^void rec_dump_conf_bits_to_bitstream_file(FILE* fp, $/;" f file: +rec_dump_verilog_spice_model_global_ports syn_verilog/verilog_utils.c /^int rec_dump_verilog_spice_model_global_ports(FILE* fp, $/;" f +rec_fprint_spice_model_global_ports spice/spice_utils.c /^int rec_fprint_spice_model_global_ports(FILE* fp, $/;" f +rec_load_unused_pb_graph_node_temp_net_num_to_pb fpga_spice/fpga_spice_utils.c /^void rec_load_unused_pb_graph_node_temp_net_num_to_pb(t_pb* cur_pb) {$/;" f +rec_mark_one_pb_unused_pb_graph_node_temp_net_num fpga_spice/fpga_spice_utils.c /^void rec_mark_one_pb_unused_pb_graph_node_temp_net_num(t_pb* cur_pb) {$/;" f +rec_mark_pb_graph_node_temp_net_num fpga_spice/fpga_spice_utils.c /^void rec_mark_pb_graph_node_temp_net_num(t_pb_graph_node* cur_pb_graph_node) {$/;" f +rec_stat_pb_type_keywords fpga_spice/fpga_spice_setup.c /^void rec_stat_pb_type_keywords(t_pb_type* cur_pb_type,$/;" f file: +rec_update_net_info_local_rr_node_tree clb_pin_remap/clb_pin_remap_util.c /^void rec_update_net_info_local_rr_node_tree(t_pb* src_pb,$/;" f +recommend_num_sim_clock_cycle fpga_spice/fpga_spice_utils.c /^int recommend_num_sim_clock_cycle(float sim_window_size) {$/;" f +recompute_bb_cost place/place.c /^static float recompute_bb_cost(void) {$/;" f file: +recompute_crit_iter base/vpr_types.h /^ int recompute_crit_iter;$/;" m struct:s_placer_opts +recompute_occupancy_from_scratch route/check_route.c /^static void recompute_occupancy_from_scratch(t_ivec ** clb_opins_used_locally) {$/;" f file: +recompute_timing_after base/ReadOptions.h /^ int recompute_timing_after;$/;" m struct:s_options +recompute_timing_after base/vpr_types.h /^ int recompute_timing_after;$/;" m struct:s_packer_opts +recover_rr_nodes_ipin_driver_switch route/rr_graph_opincb.c /^void recover_rr_nodes_ipin_driver_switch() {$/;" f file: +rect_off_screen base/graphics.c /^rect_off_screen (float x1, float y1, float x2, float y2) $/;" f file: +redraw_screen base/draw.c /^static void redraw_screen() {$/;" f file: +regex_match timing/read_sdc.c /^static boolean regex_match (char * string, char * regular_expression) {$/;" f file: +relapos_rec_s place/place_stats.c /^typedef struct relapos_rec_s {$/;" s file: +relapos_rec_t place/place_stats.c /^} relapos_rec_t;$/;" t typeref:struct:relapos_rec_s file: +relative_length ../../libarchfpga/include/physical_types.h /^ float relative_length;$/;" m union:s_port_power::__anon22 +reload_ext_net_rr_terminal_cluster pack/cluster_legality.c /^void reload_ext_net_rr_terminal_cluster(void) {$/;" f +reload_intra_cluster_nets base/vpr_api.c /^static void reload_intra_cluster_nets(t_pb *pb) {$/;" f file: +relocate timing/slre.c /^static void relocate(struct slre *r, int begin, int shift) {$/;" f file: +remove_llist_node ../../libarchfpga/linkedlist.c /^void remove_llist_node(t_llist* cur) { $/;" f +rename_illegal_port base/vpr_types.h /^ boolean rename_illegal_port; \/* Rename illegal port names that is not compatible with verilog\/SPICE syntax *\/$/;" m struct:s_fpga_spice_opts +renaming_report_postfix fpga_spice/fpga_spice_globals.c /^char* renaming_report_postfix = "_io_renaming.rpt";$/;" v +repeat ../../libarchfpga/include/physical_types.h /^ int repeat;$/;" m struct:s_grid_loc_def +report_structure base/graphics.c /^void report_structure(t_report *report) {$/;" f +report_structure base/graphics.c /^void report_structure(t_report*) { }$/;" f +requeue_primitive pack/cluster_placement.c /^static void requeue_primitive($/;" f file: +res_val ../../libarchfpga/fpga_spice_include/spice_types.h /^ float res_val;$/;" m struct:s_spice_model_wire_param +reserve_locally_used_opins route/route_common.c /^void reserve_locally_used_opins(float pres_fac, boolean rip_up_local_opins,$/;" f +reserved_bl ../../libarchfpga/fpga_spice_include/spice_types.h /^ int reserved_bl; \/* Number of reserved BLs shared by overall RRAM circuits *\/$/;" m struct:s_mem_bank_info +reserved_syntax_char_head fpga_spice/fpga_spice_globals.c /^t_llist* reserved_syntax_char_head = NULL;$/;" v +reserved_wl ../../libarchfpga/fpga_spice_include/spice_types.h /^ int reserved_wl; \/* Number of reserved WLs shared by overall RRAM circuits *\/$/;" m struct:s_mem_bank_info +reset_cluster_placement_stats pack/cluster_placement.c /^void reset_cluster_placement_stats($/;" f +reset_common_state base/graphics.c /^static void reset_common_state () {$/;" f file: +reset_flags route/check_route.c /^static void reset_flags(int inet, boolean * connected_to_route) {$/;" f file: +reset_legalizer_for_cluster pack/cluster_legality.c /^void reset_legalizer_for_cluster(t_block *clb) {$/;" f +reset_lookahead_pins_used pack/cluster.c /^static void reset_lookahead_pins_used(t_pb *cur_pb) {$/;" f file: +reset_path_costs route/route_common.c /^void reset_path_costs(void) {$/;" f +reset_pin_class_scratch_pad_rec pack/cluster_feasibility_filter.c /^static void reset_pin_class_scratch_pad_rec($/;" f file: +reset_placement place/timing_place_lookup.c /^static void reset_placement(void) {$/;" f file: +reset_rr_node_route_structs route/route_common.c /^void reset_rr_node_route_structs(void) {$/;" f +reset_rr_node_to_rc_node timing/net_delay.c /^void reset_rr_node_to_rc_node(t_linked_rc_ptr * rr_node_to_rc_node,$/;" f +reset_tried_but_unused_cluster_placements pack/cluster_placement.c /^void reset_tried_but_unused_cluster_placements($/;" f +reset_win32_state base/graphics.c /^void reset_win32_state () {$/;" f +restore_original_device place/timing_place_lookup.c /^static void restore_original_device(void) {$/;" f file: +restore_routing route/route_common.c /^void restore_routing(struct s_trace **best_routing,$/;" f +restore_routing_cluster pack/cluster_legality.c /^void restore_routing_cluster(void) {$/;" f +resync_pb_graph_nodes_in_pb base/vpr_api.c /^static void resync_pb_graph_nodes_in_pb(t_pb_graph_node *pb_graph_node,$/;" f file: +resync_post_route_netlist base/vpr_api.c /^void resync_post_route_netlist() {$/;" f +ret_track_swseg_pattern route/rr_graph_swseg.c /^enum ret_track_swseg_pattern {$/;" g file: +reverse_llist ../../libarchfpga/linkedlist.c /^t_llist* reverse_llist(t_llist* head) {$/;" f +reverse_scaled ../../libarchfpga/include/physical_types.h /^ boolean reverse_scaled; \/* Scale by (1-prob) *\/$/;" m struct:s_port_power +revert_place_logical_block pack/cluster.c /^static void revert_place_logical_block(INP int iblock, INP int max_models) {$/;" f file: +rising_edge timing/read_sdc.c /^ float rising_edge;$/;" m struct:s_sdc_clock file: +roff ../../libarchfpga/fpga_spice_include/spice_types.h /^ float roff;$/;" m struct:s_spice_model_design_tech_info +ron ../../libarchfpga/fpga_spice_include/spice_types.h /^ float ron;$/;" m struct:s_spice_model_design_tech_info +root base/vpr_types.h /^ int root; \/* root index of molecule, logical_block_ptrs[root] is ptr to root logical block *\/$/;" m struct:s_pack_molecule +root_block ../../libarchfpga/include/cad_types.h /^ t_pack_pattern_block *root_block; \/* root block used by this pattern *\/$/;" m struct:s_pack_patterns +root_passes_early_filter pack/cluster_placement.c /^static boolean root_passes_early_filter(INP t_pb_graph_node *root, INP t_pack_molecule *molecule, INP int clb_index) {$/;" f file: +rotate_shift_swseg_pattern route/rr_graph_swseg.c /^boolean* rotate_shift_swseg_pattern(int pattern_length,$/;" f file: +route_bb route/route_common.c /^struct s_bb *route_bb = NULL; \/* [0..num_nets-1]. Limits area in which each *\/$/;" v typeref:struct:s_bb +route_type base/vpr_types.h /^ enum e_route_type route_type;$/;" m struct:s_router_opts typeref:enum:s_router_opts::e_route_type +router_algorithm base/vpr_types.h /^ enum e_router_algorithm router_algorithm;$/;" m struct:s_router_opts typeref:enum:s_router_opts::e_router_algorithm +routing_spice_file_name spice/spice_globals.c /^char* routing_spice_file_name = "routing.sp";$/;" v +routing_stats base/stats.c /^void routing_stats(boolean full_stats, enum e_route_type route_type,$/;" f +routing_verilog_file_name syn_verilog/verilog_global.c /^char* routing_verilog_file_name = "routing.v";$/;" v +rr_blk_source base/globals.c /^int **rr_blk_source = NULL; \/* [0..(num_blocks-1)][0..(num_class-1)] *\/$/;" v +rr_blk_source base/globals_declare.h /^int **rr_blk_source; \/* [0..num_blocks-1][0..num_class-1] *\/$/;" v +rr_graph base/vpr_types.h /^ struct s_rr_node *rr_graph; \/* pointer to rr_graph connecting pbs of cluster *\/$/;" m struct:s_pb typeref:struct:s_pb::s_rr_node +rr_graph_externals route/rr_graph.c /^static void rr_graph_externals(t_timing_inf timing_inf,$/;" f file: +rr_indexed_data base/globals.c /^t_rr_indexed_data *rr_indexed_data = NULL; \/* [0..(num_rr_indexed_data-1)] *\/$/;" v +rr_indexed_data base/globals_declare.h /^t_rr_indexed_data *rr_indexed_data; \/* [0 .. num_rr_indexed_data-1] *\/$/;" v +rr_mem_ch pack/cluster_legality.c /^static t_chunk rr_mem_ch = {NULL, 0, NULL};$/;" v file: +rr_mem_ch route/rr_graph.c /^static t_chunk rr_mem_ch = {NULL, 0, NULL};$/;" v file: +rr_modified_head route/route_common.c /^static struct s_linked_f_pointer *rr_modified_head = NULL;$/;" v typeref:struct:s_linked_f_pointer file: +rr_node base/globals.c /^t_rr_node *rr_node = NULL; \/* [0..(num_rr_nodes-1)] *\/$/;" v +rr_node base/globals_declare.h /^t_rr_node *rr_node; \/* [0..num_rr_nodes-1] *\/$/;" v +rr_node_color base/draw.c /^static enum color_types *rr_node_color = NULL;$/;" v typeref:enum:color_types file: +rr_node_drive_switch_box fpga_spice/fpga_spice_utils.c /^int rr_node_drive_switch_box(t_rr_node* src_rr_node,$/;" f +rr_node_indices base/globals.c /^t_ivec ***rr_node_indices = NULL;$/;" v +rr_node_indices base/globals_declare.h /^t_ivec ***rr_node_indices;$/;" v +rr_node_intrinsic_cost pack/cluster_legality.c /^static float rr_node_intrinsic_cost(int inode) {$/;" f file: +rr_node_is_global_clb_ipin route/check_rr_graph.c /^static boolean rr_node_is_global_clb_ipin(int inode) {$/;" f file: +rr_node_power power/power.c /^static t_rr_node_power * rr_node_power;$/;" v file: +rr_node_route_inf route/route_common.c /^t_rr_node_route_inf *rr_node_route_inf = NULL; \/* [0..num_rr_nodes-1] *\/$/;" v +rr_node_to_pb_mapping base/vpr_types.h /^ struct s_pb **rr_node_to_pb_mapping; \/* [0..num_local_rr_nodes-1] pointer look-up of which pb this rr_node belongs based on index, NULL if pb does not exist *\/$/;" m struct:s_pb typeref:struct:s_pb::s_pb +rr_node_to_rt_node route/route_tree_timing.c /^static t_rt_node **rr_node_to_rt_node = NULL; \/* [0..num_rr_nodes-1] *\/$/;" v file: +rram_design_tech spice/spice_globals.c /^int rram_design_tech = 0;$/;" v +rram_pass_tran_value ../../libarchfpga/include/arch_types_mrfpga.h /^ float rram_pass_tran_value;$/;" m struct:s_arch_mrfpga +rram_pass_tran_value mrfpga/mrfpga_globals.c /^float rram_pass_tran_value = 0;$/;" v +rram_variation ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_mc_variation_params rram_variation;$/;" m struct:s_spice_mc_params +rram_veriloga_file_name spice/spice_globals.c /^char* rram_veriloga_file_name = "rram_behavior.va";$/;" v +rt_edge_free_list route/route_tree_timing.c /^static t_linked_rt_edge *rt_edge_free_list = NULL;$/;" v file: +rt_node_free_list route/route_tree_timing.c /^static t_rt_node *rt_node_free_list = NULL;$/;" v file: +rt_node_of_sink place/timing_place_lookup.c /^static t_rt_node **rt_node_of_sink;$/;" v file: +run_hspice_shell_script_name spice/spice_run_scripts.c /^static char* run_hspice_shell_script_name = "run_hspice_sim.sh";$/;" v file: +run_parasitic_net_estimation fpga_spice/fpga_spice_globals.c /^boolean run_parasitic_net_estimation = TRUE;$/;" v +run_testbench_load_extraction fpga_spice/fpga_spice_globals.c /^boolean run_testbench_load_extraction = TRUE;$/;" v +s ../../libarchfpga/include/ezxml.h /^ char *s; \/* start of work area *\/$/;" m struct:ezxml_root +s_TokenPair base/vpr_types.h /^struct s_TokenPair {$/;" s +s_annealing_sched base/vpr_types.h /^struct s_annealing_sched {$/;" s +s_arch ../../libarchfpga/include/physical_types.h /^struct s_arch {$/;" s +s_arch_mrfpga ../../libarchfpga/include/arch_types_mrfpga.h /^struct s_arch_mrfpga {$/;" s +s_bb base/vpr_types.h /^struct s_bb {$/;" s +s_block base/vpr_types.h /^struct s_block {$/;" s +s_buffer_inf ../../libarchfpga/include/arch_types_mrfpga.h /^struct s_buffer_inf { $/;" s +s_buffer_plan mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan {t_linked_int* inode_head; t_linked_int* sink_head; float* sink_delay; float C_downstream; float Tdel;} t_buffer_plan;$/;" s file: +s_buffer_plan_list mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan_list { t_buffer_plan_node* front; } t_buffer_plan_list;$/;" s file: +s_buffer_plan_node mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan_node { t_buffer_plan value; struct s_buffer_plan_node* next;} t_buffer_plan_node;$/;" s file: +s_cb base/vpr_types.h /^struct s_cb {$/;" s +s_chan ../../libarchfpga/include/physical_types.h /^typedef struct s_chan {$/;" s +s_chan_width_dist ../../libarchfpga/include/physical_types.h /^typedef struct s_chan_width_dist {$/;" s +s_chunk ../../libarchfpga/include/util.h /^typedef struct s_chunk {$/;" s +s_class ../../libarchfpga/include/physical_types.h /^struct s_class {$/;" s +s_clb_grid ../../libarchfpga/include/physical_types.h /^struct s_clb_grid {$/;" s +s_clb_to_clb_directs route/pb_pin_eq_auto_detect.c /^typedef struct s_clb_to_clb_directs {$/;" s file: +s_clb_to_clb_directs route/rr_graph.c /^typedef struct s_clb_to_clb_directs {$/;" s file: +s_clock base/vpr_types.h /^typedef struct s_clock {$/;" s +s_clock_arch ../../libarchfpga/include/physical_types.h /^struct s_clock_arch {$/;" s +s_clock_network ../../libarchfpga/include/physical_types.h /^struct s_clock_network {$/;" s +s_cluster_placement_primitive ../../libarchfpga/include/cad_types.h /^typedef struct s_cluster_placement_primitive {$/;" s +s_cluster_placement_stats base/vpr_types.h /^typedef struct s_cluster_placement_stats {$/;" s +s_conf_bit ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_conf_bit {$/;" s +s_conf_bit_info ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_conf_bit_info {$/;" s +s_det_routing_arch base/vpr_types.h /^struct s_det_routing_arch {$/;" s +s_direct_inf ../../libarchfpga/include/physical_types.h /^typedef struct s_direct_inf {$/;" s +s_file_name_opts base/vpr_types.h /^struct s_file_name_opts {$/;" s +s_fmap_cell base/place_and_route.h /^typedef struct s_fmap_cell {$/;" s +s_fpga_spice_opts base/vpr_types.h /^struct s_fpga_spice_opts {$/;" s +s_grid_loc_def ../../libarchfpga/include/physical_types.h /^typedef struct s_grid_loc_def {$/;" s +s_grid_tile base/vpr_types.h /^typedef struct s_grid_tile {$/;" s +s_hash util/hash.h /^struct s_hash {$/;" s +s_hash_iterator util/hash.h /^struct s_hash_iterator {$/;" s +s_heap route/route_common.h /^struct s_heap {$/;" s +s_interconnect ../../libarchfpga/include/physical_types.h /^struct s_interconnect {$/;" s +s_interconnect_pins ../../libarchfpga/include/physical_types.h /^struct s_interconnect_pins {$/;" s +s_interconnect_power ../../libarchfpga/include/physical_types.h /^struct s_interconnect_power {$/;" s +s_io base/vpr_types.h /^typedef struct s_io {$/;" s +s_ivec ../../libarchfpga/include/util.h /^typedef struct s_ivec {$/;" s +s_legal_pos place/place.c /^typedef struct s_legal_pos {$/;" s file: +s_linked_edge route/rr_graph_util.h /^struct s_linked_edge {$/;" s +s_linked_f_pointer base/vpr_types.h /^struct s_linked_f_pointer {$/;" s +s_linked_int ../../libarchfpga/include/util.h /^typedef struct s_linked_int {$/;" s +s_linked_rc_edge timing/net_delay_types.h /^struct s_linked_rc_edge {$/;" s +s_linked_rc_ptr timing/net_delay_types.h /^struct s_linked_rc_ptr {$/;" s +s_linked_rt_edge route/route_tree_timing.h /^struct s_linked_rt_edge {$/;" s +s_linked_vptr ../../libarchfpga/include/util.h /^typedef struct s_linked_vptr {$/;" s +s_llist ../../libarchfpga/fpga_spice_include/linkedlist.h /^struct s_llist$/;" s +s_log power/power.h /^struct s_log {$/;" s +s_logical_block base/vpr_types.h /^typedef struct s_logical_block {$/;" s +s_mem_bank_info ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_mem_bank_info {$/;" s +s_memristor_inf ../../libarchfpga/include/arch_types_mrfpga.h /^struct s_memristor_inf { $/;" s +s_mode ../../libarchfpga/include/physical_types.h /^struct s_mode {$/;" s +s_mode_power ../../libarchfpga/include/physical_types.h /^struct s_mode_power {$/;" s +s_model ../../libarchfpga/include/logic_types.h /^typedef struct s_model {$/;" s +s_model_chain_pattern ../../libarchfpga/include/cad_types.h /^typedef struct s_model_chain_pattern {$/;" s +s_model_ports ../../libarchfpga/include/logic_types.h /^typedef struct s_model_ports {$/;" s +s_model_stats base/read_blif.c /^struct s_model_stats {$/;" s file: +s_molecule_link pack/cluster.c /^struct s_molecule_link {$/;" s file: +s_mux route/rr_graph.c /^typedef struct s_mux {$/;" s file: +s_mux_arch power/power.h /^struct s_mux_arch {$/;" s +s_mux_node power/power.h /^struct s_mux_node {$/;" s +s_mux_size_distribution route/rr_graph.c /^typedef struct s_mux_size_distribution {$/;" s file: +s_net base/vpr_types.h /^typedef struct s_net {$/;" s +s_net_power base/vpr_types.h /^struct s_net_power {$/;" s +s_num_mapped_opins_stats route/pb_pin_eq_auto_detect.c /^struct s_num_mapped_opins_stats{$/;" s file: +s_options base/ReadOptions.h /^struct s_options {$/;" s +s_override_constraint base/vpr_types.h /^typedef struct s_override_constraint {$/;" s +s_pack_molecule base/vpr_types.h /^typedef struct s_pack_molecule {$/;" s +s_pack_pattern_block ../../libarchfpga/include/cad_types.h /^typedef struct s_pack_pattern_block {$/;" s +s_pack_pattern_connections ../../libarchfpga/include/cad_types.h /^typedef struct s_pack_pattern_connections {$/;" s +s_pack_patterns ../../libarchfpga/include/cad_types.h /^typedef struct s_pack_patterns {$/;" s +s_packer_opts base/vpr_types.h /^struct s_packer_opts {$/;" s +s_pb base/vpr_types.h /^typedef struct s_pb {$/;" s +s_pb_graph_edge ../../libarchfpga/include/physical_types.h /^struct s_pb_graph_edge {$/;" s +s_pb_graph_node ../../libarchfpga/include/physical_types.h /^struct s_pb_graph_node {$/;" s +s_pb_graph_node_power ../../libarchfpga/include/physical_types.h /^struct s_pb_graph_node_power {$/;" s +s_pb_graph_pin ../../libarchfpga/include/physical_types.h /^struct s_pb_graph_pin {$/;" s +s_pb_graph_pin_power ../../libarchfpga/include/physical_types.h /^struct s_pb_graph_pin_power {$/;" s +s_pb_stats base/vpr_types.h /^typedef struct s_pb_stats {$/;" s +s_pb_type ../../libarchfpga/include/physical_types.h /^struct s_pb_type {$/;" s +s_pb_type_power ../../libarchfpga/include/physical_types.h /^struct s_pb_type_power {$/;" s +s_pin_to_pin_annotation ../../libarchfpga/include/physical_types.h /^struct s_pin_to_pin_annotation {$/;" s +s_pl_blocks_to_be_moved place/place.c /^typedef struct s_pl_blocks_to_be_moved {$/;" s file: +s_pl_macro place/place_macro.h /^typedef struct s_pl_macro{$/;" s +s_pl_macro_member place/place_macro.h /^typedef struct s_pl_macro_member{$/;" s +s_pl_moved_block place/place.c /^typedef struct s_pl_moved_block {$/;" s file: +s_place_region base/vpr_types.h /^struct s_place_region {$/;" s +s_placer_opts base/vpr_types.h /^struct s_placer_opts {$/;" s +s_port ../../libarchfpga/include/physical_types.h /^struct s_port {$/;" s +s_port_power ../../libarchfpga/include/physical_types.h /^struct s_port_power {$/;" s +s_power_arch ../../libarchfpga/include/physical_types.h /^struct s_power_arch {$/;" s +s_power_breakdown power/power_components.h /^struct s_power_breakdown {$/;" s +s_power_buffer_sc_levr_inf power/power.h /^struct s_power_buffer_sc_levr_inf {$/;" s +s_power_buffer_size_inf power/power.h /^struct s_power_buffer_size_inf {$/;" s +s_power_buffer_strength_inf power/power.h /^struct s_power_buffer_strength_inf {$/;" s +s_power_commonly_used power/power.h /^struct s_power_commonly_used {$/;" s +s_power_mux_info power/power.h /^struct s_power_mux_info {$/;" s +s_power_mux_volt_inf power/power.h /^struct s_power_mux_volt_inf {$/;" s +s_power_mux_volt_pair power/power.h /^struct s_power_mux_volt_pair {$/;" s +s_power_nmos_leakage_inf power/power.h /^struct s_power_nmos_leakage_inf {$/;" s +s_power_nmos_leakage_pair power/power.h /^struct s_power_nmos_leakage_pair {$/;" s +s_power_nmos_mux_inf power/power.h /^struct s_power_nmos_mux_inf {$/;" s +s_power_opts base/vpr_types.h /^struct s_power_opts {$/;" s +s_power_output power/power.h /^struct s_power_output {$/;" s +s_power_tech power/power.h /^struct s_power_tech {$/;" s +s_power_usage ../../libarchfpga/include/physical_types.h /^struct s_power_usage {$/;" s +s_prepacked_tnode_data base/vpr_types.h /^typedef struct s_prepacked_tnode_data {$/;" s +s_rc_node timing/net_delay_types.h /^struct s_rc_node {$/;" s +s_reserved_syntax_char ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_reserved_syntax_char {$/;" s +s_router_opts base/vpr_types.h /^struct s_router_opts {$/;" s +s_rr_indexed_data base/vpr_types.h /^typedef struct s_rr_indexed_data {$/;" s +s_rr_node base/vpr_types.h /^struct s_rr_node {$/;" s +s_rr_node_power power/power.h /^struct s_rr_node_power {$/;" s +s_rt_node route/route_tree_timing.h /^struct s_rt_node {$/;" s +s_sb base/vpr_types.h /^struct s_sb {$/;" s +s_scff_info ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_scff_info {$/;" s +s_sdc_clock timing/read_sdc.c /^typedef struct s_sdc_clock {$/;" s file: +s_sdc_exclusive_group timing/read_sdc.c /^typedef struct s_sdc_exclusive_group {$/;" s file: +s_seg_details base/vpr_types.h /^typedef struct s_seg_details {$/;" s +s_segment_inf ../../libarchfpga/include/physical_types.h /^typedef struct s_segment_inf {$/;" s +s_slack base/vpr_types.h /^typedef struct s_slack {$/;" s +s_solution_inf power/power.h /^struct s_solution_inf {$/;" s +s_spice ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice {$/;" s +s_spice_mc_params ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_mc_params {$/;" s +s_spice_mc_variation_params ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_mc_variation_params {$/;" s +s_spice_meas_params ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_meas_params {$/;" s +s_spice_model ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_model {$/;" s +s_spice_model_buffer ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_model_buffer {$/;" s +s_spice_model_design_tech_info ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_model_design_tech_info {$/;" s +s_spice_model_netlist ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_model_netlist {$/;" s +s_spice_model_pass_gate_logic ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_model_pass_gate_logic {$/;" s +s_spice_model_port ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_model_port {$/;" s +s_spice_model_wire_param ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_model_wire_param {$/;" s +s_spice_mux_arch ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_mux_arch {$/;" s +s_spice_mux_model ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_mux_model {$/;" s +s_spice_net_info ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_net_info {$/;" s +s_spice_opts base/vpr_types.h /^struct s_spice_opts {$/;" s +s_spice_params ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_params {$/;" s +s_spice_stimulate_params ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_stimulate_params {$/;" s +s_spice_tech_lib ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_tech_lib {$/;" s +s_spice_transistor_type ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spice_transistor_type {$/;" s +s_spicetb_info ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_spicetb_info {$/;" s +s_sram_inf ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_sram_inf {$/;" s +s_sram_inf_orgz ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_sram_inf_orgz {$/;" s +s_sram_orgz_info ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_sram_orgz_info {$/;" s +s_standalone_sram_info ../../libarchfpga/fpga_spice_include/spice_types.h /^struct s_standalone_sram_info {$/;" s +s_switch_inf ../../libarchfpga/include/physical_types.h /^typedef struct s_switch_inf {$/;" s +s_swseg_pattern_inf ../../libarchfpga/include/physical_types.h /^struct s_swseg_pattern_inf {$/;" s +s_syn_verilog_opts base/vpr_types.h /^struct s_syn_verilog_opts {$/;" s +s_tedge base/vpr_types.h /^typedef struct s_tedge {$/;" s +s_timing_constraints base/vpr_types.h /^typedef struct s_timing_constraints { \/* Container structure for all SDC timing constraints. $/;" s +s_timing_inf ../../libarchfpga/include/physical_types.h /^typedef struct s_timing_inf {$/;" s +s_timing_stats base/vpr_types.h /^typedef struct s_timing_stats {$/;" s +s_tnode base/vpr_types.h /^typedef struct s_tnode {$/;" s +s_token util/token.h /^struct s_token {$/;" s +s_trace base/vpr_types.h /^typedef struct s_trace {$/;" s +s_transistor_inf power/power.h /^struct s_transistor_inf {$/;" s +s_transistor_size_inf power/power.h /^struct s_transistor_size_inf {$/;" s +s_type_descriptor ../../libarchfpga/include/physical_types.h /^struct s_type_descriptor \/* TODO rename this. maybe physical type descriptor or complex logic block or physical logic block*\/$/;" s +s_vpr_setup base/vpr_types.h /^typedef struct s_vpr_setup {$/;" s +sat_blks_pins_prefer_side clb_pin_remap/place_clb_pin_remap.c /^int sat_blks_pins_prefer_side(int n_nets, t_net* nets, $/;" f +sat_one_blk_pins_prefer_side clb_pin_remap/place_clb_pin_remap.c /^int sat_one_blk_pins_prefer_side(int n_nets, t_net* nets, $/;" f +save_and_reset_routing_cluster pack/cluster_legality.c /^void save_and_reset_routing_cluster(void) {$/;" f +save_best_buffer_list mrfpga/buffer_insertion.c /^static void save_best_buffer_list( t_linked_int* best_list )$/;" f file: +save_best_timing mrfpga/buffer_insertion.c /^static void save_best_timing( float* sink_delay, t_linked_int* index, float* net_delay )$/;" f file: +save_cluster_solution pack/cluster_legality.c /^void save_cluster_solution(void) {$/;" f +save_routing route/route_common.c /^void save_routing(struct s_trace **best_routing,$/;" f +saved_base_cost base/vpr_types.h /^ float saved_base_cost;$/;" m struct:s_rr_indexed_data +saved_net_rr_terminals pack/cluster_legality.c /^static int **saved_net_rr_terminals;$/;" v file: +saved_num_nets_in_cluster pack/cluster_legality.c /^static int saved_num_nets_in_cluster;$/;" v file: +saved_xleft base/graphics.c /^static float saved_xleft, saved_xright, saved_ytop, saved_ybot; $/;" v file: +saved_xright base/graphics.c /^static float saved_xleft, saved_xright, saved_ytop, saved_ybot; $/;" v file: +saved_ybot base/graphics.c /^static float saved_xleft, saved_xright, saved_ytop, saved_ybot; $/;" v file: +saved_ytop base/graphics.c /^static float saved_xleft, saved_xright, saved_ytop, saved_ybot; $/;" v file: +sb ../../libarchfpga/include/physical_types.h /^ boolean *sb;$/;" m struct:s_segment_inf +sb base/vpr_types.h /^ boolean *sb;$/;" m struct:s_seg_details +sb_drive_rr_nodes base/vpr_types.h /^ t_rr_node** sb_drive_rr_nodes;$/;" m struct:s_rr_node +sb_drive_switches base/vpr_types.h /^ int* sb_drive_switches;$/;" m struct:s_rr_node +sb_index_high ../../libarchfpga/fpga_spice_include/spice_types.h /^ int** sb_index_high;$/;" m struct:s_spice_model +sb_index_low ../../libarchfpga/fpga_spice_include/spice_types.h /^ int** sb_index_low;$/;" m struct:s_spice_model +sb_info base/globals.c /^t_sb** sb_info = NULL;$/;" v +sb_len ../../libarchfpga/include/physical_types.h /^ int sb_len;$/;" m struct:s_segment_inf +sb_num_drive_rr_nodes base/vpr_types.h /^ int sb_num_drive_rr_nodes;$/;" m struct:s_rr_node +sc_levr power/power.h /^ float sc_levr;$/;" m struct:s_power_buffer_sc_levr_inf +sc_levr_inf power/power.h /^ t_power_buffer_sc_levr_inf * sc_levr_inf;$/;" m struct:s_power_buffer_strength_inf +sc_no_levr power/power.h /^ float sc_no_levr;$/;" m struct:s_power_buffer_strength_inf +scale_factor power/PowerSpicedComponent.c /^float PowerSpicedComponent::scale_factor(int num_inputs,$/;" f class:PowerSpicedComponent +scaled_by_pin ../../libarchfpga/include/physical_types.h /^ t_pb_graph_pin * scaled_by_pin;$/;" m struct:s_pb_graph_pin_power +scaled_by_port ../../libarchfpga/include/physical_types.h /^ t_port * scaled_by_port;$/;" m struct:s_port_power +scaled_by_port_pin_idx ../../libarchfpga/include/physical_types.h /^ int scaled_by_port_pin_idx;$/;" m struct:s_port_power +scan_chain_heads spice/spice_globals.c /^t_llist* scan_chain_heads = NULL;$/;" v +scff_info ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_scff_info* scff_info; \/* Only be allocated when orgz type is scan-chain *\/$/;" m struct:s_sram_orgz_info +sched_type base/vpr_types.h /^enum sched_type {$/;" g +scratch_pad ../../libarchfpga/include/physical_types.h /^ int scratch_pad; \/* temporary data structure useful to store traversal info *\/$/;" m struct:s_pb_graph_pin +screen_num base/graphics.c /^static int screen_num;$/;" v file: +sdc timing/read_sdc.c /^static FILE *sdc;$/;" v file: +sdc_clocks timing/read_sdc.c /^t_sdc_clock * sdc_clocks = NULL; \/* List of clock periods and offsets from create_clock commands *\/$/;" v +sdc_file_name base/vpr_types.h /^ char *sdc_file_name;$/;" m struct:s_packer_opts +sdf_DFF_delay_printing base/verilog_writer.c /^void sdf_DFF_delay_printing(FILE *SDF , t_pb *pb)$/;" f +sdf_LUT_delay_printing base/verilog_writer.c /^void sdf_LUT_delay_printing(FILE *SDF , t_pb *pb)$/;" f +search_and_add_num_mapped_opin_llist route/pb_pin_eq_auto_detect.c /^t_llist* search_and_add_num_mapped_opin_llist(t_llist* head, $/;" f +search_in_int_list ../../libarchfpga/util.c /^t_linked_int* search_in_int_list(t_linked_int* int_list_head, $/;" f +search_llist_tail ../../libarchfpga/linkedlist.c /^t_llist* search_llist_tail(t_llist* head) {$/;" f +search_mapped_block fpga_spice/fpga_spice_utils.c /^t_block* search_mapped_block(int x, int y, int z) {$/;" f +search_mux_linked_list fpga_spice/fpga_spice_utils.c /^t_llist* search_mux_linked_list(t_llist* mux_head,$/;" f +search_swseg_pattern_seg_len route/rr_graph_swseg.c /^t_swseg_pattern_inf* search_swseg_pattern_seg_len(INP int num_swseg_pattern,$/;" f file: +search_tapbuf_llist_same_settings spice/spice_subckt.c /^int search_tapbuf_llist_same_settings(t_llist* head,$/;" f file: +seed base/vpr_types.h /^ int seed;$/;" m struct:s_placer_opts +seg_direction_type ../../libarchfpga/include/physical_types.h /^ enum e_directionality seg_direction_type;$/;" m struct:s_swseg_pattern_inf typeref:enum:s_swseg_pattern_inf::e_directionality +seg_index base/vpr_types.h /^ int seg_index;$/;" m struct:s_rr_indexed_data +seg_index_of_cblock route/rr_graph_util.c /^int seg_index_of_cblock(t_rr_type from_rr_type, int to_node) {$/;" f +seg_index_of_sblock route/rr_graph_util.c /^int seg_index_of_sblock(int from_node, int to_node) {$/;" f +seg_length ../../libarchfpga/include/physical_types.h /^ int seg_length;$/;" m struct:s_swseg_pattern_inf +seg_switch ../../libarchfpga/include/physical_types.h /^ short seg_switch;$/;" m struct:s_segment_inf +seg_switch base/vpr_types.h /^ short seg_switch;$/;" m struct:s_seg_details +segments spice/spice_mux_testbench.c /^static t_segment_inf* segments;$/;" v file: +segments spice/spice_routing_testbench.c /^static t_segment_inf* segments;$/;" v file: +selected_input power/power.h /^ short selected_input; \/* Input index that is selected *\/$/;" m struct:s_rr_node_power +setAllEchoFileEnabled base/ReadOptions.c /^void setAllEchoFileEnabled(boolean value) {$/;" f +setEchoEnabled base/ReadOptions.c /^void setEchoEnabled(boolean echo_enabled) {$/;" f +setEchoFileEnabled base/ReadOptions.c /^void setEchoFileEnabled(enum e_echo_files echo_option, boolean value) {$/;" f +setEchoFileName base/ReadOptions.c /^void setEchoFileName(enum e_echo_files echo_option, const char *name) {$/;" f +setOutputFileName base/ReadOptions.c /^void setOutputFileName(enum e_output_files ename, const char *name, const char *default_name) {$/;" f +set_and_balance_arrival_time timing/path_delay.c /^static void set_and_balance_arrival_time(int to_node, int from_node, float Tdel, boolean do_lut_input_balancing) {$/;" f file: +set_blk_net_one_sink_prefer_side clb_pin_remap/place_clb_pin_remap.c /^void set_blk_net_one_sink_prefer_side(int* prefer_side, \/* [0..3] array, should be allocated before *\/$/;" f +set_draw_mode base/graphics.c /^void set_draw_mode (enum e_draw_mode draw_mode) { }$/;" f +set_draw_mode base/graphics.c /^void set_draw_mode (enum e_draw_mode draw_mode) {$/;" f +set_graphics_state base/draw.c /^void set_graphics_state(boolean show_graphics_val, int gr_automode_val,$/;" f +set_jump_offset timing/slre.c /^static void set_jump_offset(struct slre *r, int pc, int offset) {$/;" f file: +set_keypress_input base/graphics.c /^void set_keypress_input (bool enable) {$/;" f +set_keypress_input base/graphics.c /^void set_keypress_input (bool) { }$/;" f +set_max_pins_per_side base/SetupVPR.c /^static void set_max_pins_per_side() {$/;" f file: +set_mode_cluster_placement_stats pack/cluster_placement.c /^void set_mode_cluster_placement_stats(INP t_pb_graph_node *pb_graph_node,$/;" f +set_mouse_move_input base/graphics.c /^void set_mouse_move_input (bool enable) {$/;" f +set_mouse_move_input base/graphics.c /^void set_mouse_move_input (bool) { }$/;" f +set_one_pb_rr_node_default_prev_node_edge fpga_spice/fpga_spice_backannotate_utils.c /^void set_one_pb_rr_node_default_prev_node_edge(t_rr_node* pb_rr_graph, $/;" f file: +set_one_pb_rr_node_net_num fpga_spice/fpga_spice_backannotate_utils.c /^void set_one_pb_rr_node_net_num(t_rr_node* pb_rr_graph, $/;" f file: +set_pb_graph_mode pack/cluster_legality.c /^void set_pb_graph_mode(t_pb_graph_node *pb_graph_node, int mode, int isOn) {$/;" f +set_src_bottom_side_net_one_sink_prefer_side clb_pin_remap/place_clb_pin_remap.c /^void set_src_bottom_side_net_one_sink_prefer_side(int* prefer_side, $/;" f +set_src_left_side_net_one_sink_prefer_side clb_pin_remap/place_clb_pin_remap.c /^void set_src_left_side_net_one_sink_prefer_side(int* prefer_side, $/;" f +set_src_right_side_net_one_sink_prefer_side clb_pin_remap/place_clb_pin_remap.c /^void set_src_right_side_net_one_sink_prefer_side(int* prefer_side, $/;" f +set_src_top_side_net_one_sink_prefer_side clb_pin_remap/place_clb_pin_remap.c /^void set_src_top_side_net_one_sink_prefer_side(int* prefer_side, $/;" f +set_unroute_blk_pins_prefer_sides clb_pin_remap/place_clb_pin_remap.c /^int set_unroute_blk_pins_prefer_sides(int n_blk, t_block* blk) {$/;" f +setcolor base/graphics.c /^void setcolor (int cindex) $/;" f +setcolor base/graphics.c /^void setcolor (int cindex) { }$/;" f +setcolor base/graphics.c /^void setcolor (string cname) {$/;" f +setfontsize base/graphics.c /^void setfontsize (int pointsize) $/;" f +setfontsize base/graphics.c /^void setfontsize (int pointsize) { }$/;" f +setlinestyle base/graphics.c /^void setlinestyle (int linestyle) $/;" f +setlinestyle base/graphics.c /^void setlinestyle (int linestyle) { }$/;" f +setlinewidth base/graphics.c /^void setlinewidth (int linewidth) $/;" f +setlinewidth base/graphics.c /^void setlinewidth (int linewidth) { }$/;" f +setpoly base/graphics.c /^static void setpoly (int bnum, int xc, int yc, int r, float theta) $/;" f file: +setup_blocks_affected place/place.c /^static int setup_blocks_affected(int b_from, int x_to, int y_to, int z_to) {$/;" f file: +setup_chan_width place/timing_place_lookup.c /^static void setup_chan_width(struct s_router_opts router_opts,$/;" f file: +setup_intracluster_routing_for_logical_block pack/cluster_legality.c /^void setup_intracluster_routing_for_logical_block(INP int iblock,$/;" f +setup_intracluster_routing_for_molecule pack/cluster_legality.c /^void setup_intracluster_routing_for_molecule(INP t_pack_molecule *molecule,$/;" f +setup_junction_switch base/SetupVPR.c /^static void setup_junction_switch(struct s_det_routing_arch *det_routing_arch) {$/;" f file: +sharinggain base/vpr_types.h /^ std::map sharinggain; \/* [0..num_logical_blocks-1]. How many nets on this logical_block are already in the pb under consideration *\/$/;" m struct:s_pb_stats +show_blif_stats base/read_blif.c /^static void show_blif_stats(t_model *user_models, t_model *library_models) {$/;" f file: +show_combinational_cycle_candidates timing/path_delay2.c /^static void show_combinational_cycle_candidates() {$/;" f file: +show_congestion base/draw.c /^static boolean show_congestion = FALSE;$/;" v file: +show_defects base/draw.c /^static boolean show_defects = FALSE; \/* Show defective stuff *\/$/;" v file: +show_graphics base/draw.c /^static boolean show_graphics; \/* Graphics enabled or not? *\/$/;" v file: +show_nets base/draw.c /^static boolean show_nets = FALSE; \/* Show nets of placement or routing? *\/$/;" v file: +sibling ../../libarchfpga/include/ezxml.h /^ ezxml_t sibling; \/* next tag with different name in same section and depth *\/$/;" m struct:ezxml +signal_density_weight base/ReadOptions.h /^ float signal_density_weight;$/;" m struct:s_options +signal_density_weight base/vpr_types.h /^ float signal_density_weight;$/;" m struct:s_fpga_spice_opts +sim_clock_freq_slack ../../libarchfpga/fpga_spice_include/spice_types.h /^ float sim_clock_freq_slack;$/;" m struct:s_spice_stimulate_params +sim_num_clock_cycle ../../libarchfpga/fpga_spice_include/spice_types.h /^ int sim_num_clock_cycle; \/* Number of clock cycle in simulation *\/$/;" m struct:s_spice_meas_params +sim_results_dir_name spice/spice_run_scripts.c /^static char* sim_results_dir_name = "results\/";$/;" v file: +sim_temp ../../libarchfpga/fpga_spice_include/spice_types.h /^ int sim_temp; \/* Simulation Temperature*\/$/;" m struct:s_spice_params +sim_window_size base/ReadOptions.h /^ float sim_window_size;$/;" m struct:s_options +sim_window_size base/vpr_types.h /^ float sim_window_size;$/;" m struct:s_fpga_spice_opts +sink_delay mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan {t_linked_int* inode_head; t_linked_int* sink_head; float* sink_delay; float C_downstream; float Tdel;} t_buffer_plan;$/;" m struct:s_buffer_plan file: +sink_head mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan {t_linked_int* inode_head; t_linked_int* sink_head; float* sink_delay; float C_downstream; float Tdel;} t_buffer_plan;$/;" m struct:s_buffer_plan file: +sink_list base/vpr_types.h /^ char ** sink_list;$/;" m struct:s_override_constraint +sink_order place/timing_place_lookup.c /^static int *sink_order;$/;" v file: +size ../../libarchfpga/fpga_spice_include/spice_types.h /^ float size;$/;" m struct:s_spice_model_buffer +size ../../libarchfpga/fpga_spice_include/spice_types.h /^ int size;$/;" m struct:s_spice_model_port +size ../../libarchfpga/fpga_spice_include/spice_types.h /^ int size;$/;" m struct:s_spice_mux_model +size ../../libarchfpga/include/logic_types.h /^ int size; \/* maximum number of pins *\/$/;" m struct:s_model_ports +size power/power.h /^ float size;$/;" m struct:s_transistor_size_inf +size route/rr_graph.c /^ int size;$/;" m struct:s_mux file: +size_inf power/power.h /^ t_transistor_size_inf * size_inf; \/* Array of transistor sizes *\/$/;" m struct:s_transistor_inf +skip_clustering base/ReadOptions.h /^ boolean skip_clustering;$/;" m struct:s_options +skip_clustering base/vpr_types.h /^ boolean skip_clustering;$/;" m struct:s_packer_opts +slack base/vpr_types.h /^ float ** slack;$/;" m struct:s_slack +slew_fall ../../libarchfpga/fpga_spice_include/spice_types.h /^ float slew_fall;$/;" m struct:s_spice_net_info +slew_lower_thres_pct_fall ../../libarchfpga/fpga_spice_include/spice_types.h /^ float slew_lower_thres_pct_fall;$/;" m struct:s_spice_meas_params +slew_lower_thres_pct_rise ../../libarchfpga/fpga_spice_include/spice_types.h /^ float slew_lower_thres_pct_rise;$/;" m struct:s_spice_meas_params +slew_rise ../../libarchfpga/fpga_spice_include/spice_types.h /^ float slew_rise;$/;" m struct:s_spice_net_info +slew_upper_thres_pct_fall ../../libarchfpga/fpga_spice_include/spice_types.h /^ float slew_upper_thres_pct_fall;$/;" m struct:s_spice_meas_params +slew_upper_thres_pct_rise ../../libarchfpga/fpga_spice_include/spice_types.h /^ float slew_upper_thres_pct_rise;$/;" m struct:s_spice_meas_params +slre timing/slre.c /^struct slre {$/;" s file: +slre_capture timing/slre.h /^enum slre_capture {SLRE_STRING, SLRE_INT, SLRE_FLOAT};$/;" g +slre_match timing/slre.c /^const char *slre_match(enum slre_option options, const char *re,$/;" f +slre_option timing/slre.h /^enum slre_option {SLRE_CASE_INSENSITIVE = 1};$/;" g +snprintf ../../libarchfpga/ezxml.c 57;" d file: +sort_me power/PowerSpicedComponent.c /^void PowerCallibInputs::sort_me() {$/;" f class:PowerCallibInputs +sort_me power/PowerSpicedComponent.c /^void PowerSpicedComponent::sort_me(void) {$/;" f class:PowerSpicedComponent +sort_one_class_conflict_pins_by_low_slack clb_pin_remap/clb_pin_remap_util.c /^int* sort_one_class_conflict_pins_by_low_slack(t_block* target_blk, int class_index,$/;" f +sorted power/PowerSpicedComponent.h /^ bool sorted;$/;" m class:PowerCallibInputs +sorted power/PowerSpicedComponent.h /^ bool sorted;$/;" m class:PowerSpicedComponent +sorter_PowerCallibInputs power/PowerSpicedComponent.c /^bool sorter_PowerCallibInputs(PowerCallibInputs * a, PowerCallibInputs * b) {$/;" f +sorter_PowerCallibSize power/PowerSpicedComponent.c /^bool sorter_PowerCallibSize(PowerCallibSize * a, PowerCallibSize * b) {$/;" f +source_list base/vpr_types.h /^ char ** source_list; \/* Array of net names of flip-flops or clocks *\/$/;" m struct:s_override_constraint +spice ../../libarchfpga/include/physical_types.h /^ t_spice* spice;$/;" m struct:s_arch +spice_backannotate_vpr_post_route_info fpga_spice/fpga_spice_backannotate_utils.c /^void spice_backannotate_vpr_post_route_info(t_det_routing_arch RoutingArch,$/;" f +spice_cb_mux_tb_dir_name spice/spice_api.c /^static char* spice_cb_mux_tb_dir_name = "cb_mux_tb\/";$/;" v file: +spice_cb_mux_testbench_postfix spice/spice_globals.c /^char* spice_cb_mux_testbench_postfix = "_cbmux_testbench.sp";$/;" v +spice_cb_tb_dir_name spice/spice_api.c /^static char* spice_cb_tb_dir_name = "cb_tb\/";$/;" v file: +spice_cb_testbench_postfix spice/spice_globals.c /^char* spice_cb_testbench_postfix = "_cb_testbench.sp";$/;" v +spice_dff_testbench_postfix spice/spice_globals.c /^char* spice_dff_testbench_postfix = "_dff_testbench.sp";$/;" v +spice_dir base/ReadOptions.h /^ char* spice_dir;$/;" m struct:s_options +spice_dir base/vpr_types.h /^ char* spice_dir;$/;" m struct:s_spice_opts +spice_grid_tb_dir_name spice/spice_api.c /^static char* spice_grid_tb_dir_name = "grid_tb\/";$/;" v file: +spice_grid_testbench_postfix spice/spice_globals.c /^char* spice_grid_testbench_postfix = "_grid_testbench.sp";$/;" v +spice_hardlogic_tb_dir_name spice/spice_api.c /^static char* spice_hardlogic_tb_dir_name = "hardlogic_tb\/";$/;" v file: +spice_hardlogic_testbench_postfix spice/spice_globals.c /^char* spice_hardlogic_testbench_postfix = "_hardlogic_testbench.sp";$/;" v +spice_io_testbench_postfix spice/spice_globals.c /^char* spice_io_testbench_postfix = "_io_testbench.sp";$/;" v +spice_lut_tb_dir_name spice/spice_api.c /^static char* spice_lut_tb_dir_name = "lut_tb\/";$/;" v file: +spice_lut_testbench_postfix spice/spice_globals.c /^char* spice_lut_testbench_postfix = "_lut_testbench.sp";$/;" v +spice_model ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model* spice_model; \/\/ Xifan TANG: Spice Support$/;" m struct:s_sram_inf_orgz +spice_model ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model* spice_model;$/;" m struct:s_spice_model_buffer +spice_model ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model* spice_model;$/;" m struct:s_spice_model_pass_gate_logic +spice_model ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model* spice_model;$/;" m struct:s_spice_model_port +spice_model ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model* spice_model;$/;" m struct:s_spice_mux_model +spice_model ../../libarchfpga/include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_interconnect +spice_model ../../libarchfpga/include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_pb_type +spice_model ../../libarchfpga/include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_segment_inf +spice_model ../../libarchfpga/include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_switch_inf +spice_model_name ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* spice_model_name; \/\/ Xifan TANG: Spice Support$/;" m struct:s_sram_inf_orgz +spice_model_name ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* spice_model_name;$/;" m struct:s_spice_model_buffer +spice_model_name ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* spice_model_name;$/;" m struct:s_spice_model_pass_gate_logic +spice_model_name ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* spice_model_name;$/;" m struct:s_spice_model_port +spice_model_name ../../libarchfpga/include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_interconnect +spice_model_name ../../libarchfpga/include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_pb_type +spice_model_name ../../libarchfpga/include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_segment_inf +spice_model_name ../../libarchfpga/include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_switch_inf +spice_model_port ../../libarchfpga/include/physical_types.h /^ t_spice_model_port* spice_model_port;$/;" m struct:s_port +spice_models ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model* spice_models;$/;" m struct:s_spice +spice_mux_arch ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_mux_arch* spice_mux_arch;$/;" m struct:s_spice_mux_model +spice_name_tag base/vpr_types.h /^ char* spice_name_tag;$/;" m struct:s_pb +spice_net_info base/vpr_types.h /^ t_spice_net_info* spice_net_info;$/;" m struct:s_net +spice_net_info_add_density_weight fpga_spice/fpga_spice_setup.c /^void spice_net_info_add_density_weight(float signal_density_weight) {$/;" f file: +spice_params ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_params spice_params;$/;" m struct:s_spice +spice_pb_mux_tb_dir_name spice/spice_api.c /^static char* spice_pb_mux_tb_dir_name = "pb_mux_tb\/";$/;" v file: +spice_pb_mux_testbench_postfix spice/spice_globals.c /^char* spice_pb_mux_testbench_postfix = "_pbmux_testbench.sp";$/;" v +spice_print_cb_mux_testbench base/vpr_types.h /^ boolean spice_print_cb_mux_testbench; $/;" m struct:s_spice_opts +spice_print_cb_testbench base/vpr_types.h /^ boolean spice_print_cb_testbench; $/;" m struct:s_spice_opts +spice_print_cb_testbench spice/spice_routing_testbench.c /^void spice_print_cb_testbench(char* formatted_spice_dir,$/;" f +spice_print_grid_testbench base/vpr_types.h /^ boolean spice_print_grid_testbench; $/;" m struct:s_spice_opts +spice_print_grid_testbench spice/spice_grid_testbench.c /^void spice_print_grid_testbench(char* formatted_spice_dir,$/;" f +spice_print_hardlogic_testbench base/vpr_types.h /^ boolean spice_print_hardlogic_testbench; $/;" m struct:s_spice_opts +spice_print_hardlogic_testbench spice/spice_hardlogic_testbench.c /^void spice_print_hardlogic_testbench(char* formatted_spice_dir,$/;" f +spice_print_lut_testbench base/vpr_types.h /^ boolean spice_print_lut_testbench; $/;" m struct:s_spice_opts +spice_print_lut_testbench spice/spice_lut_testbench.c /^void spice_print_lut_testbench(char* formatted_spice_dir,$/;" f +spice_print_mux_testbench spice/spice_mux_testbench.c /^void spice_print_mux_testbench(char* formatted_spice_dir,$/;" f +spice_print_pb_mux_testbench base/vpr_types.h /^ boolean spice_print_pb_mux_testbench; $/;" m struct:s_spice_opts +spice_print_sb_mux_testbench base/vpr_types.h /^ boolean spice_print_sb_mux_testbench; $/;" m struct:s_spice_opts +spice_print_sb_testbench base/vpr_types.h /^ boolean spice_print_sb_testbench; $/;" m struct:s_spice_opts +spice_print_sb_testbench spice/spice_routing_testbench.c /^void spice_print_sb_testbench(char* formatted_spice_dir,$/;" f +spice_print_top_netlist spice/spice_top_netlist.c /^void spice_print_top_netlist(char* circuit_name,$/;" f +spice_print_top_testbench base/vpr_types.h /^ boolean spice_print_top_testbench; $/;" m struct:s_spice_opts +spice_reserved ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean spice_reserved;$/;" m struct:s_reserved_syntax_char +spice_sb_mux_tb_dir_name spice/spice_api.c /^static char* spice_sb_mux_tb_dir_name = "sb_mux_tb\/";$/;" v file: +spice_sb_mux_testbench_postfix spice/spice_globals.c /^char* spice_sb_mux_testbench_postfix = "_sbmux_testbench.sp";$/;" v +spice_sb_tb_dir_name spice/spice_api.c /^static char* spice_sb_tb_dir_name = "sb_tb\/";$/;" v file: +spice_sb_testbench_postfix spice/spice_globals.c /^char* spice_sb_testbench_postfix = "_sb_testbench.sp";$/;" v +spice_sim_mt_num base/ReadOptions.h /^ int spice_sim_mt_num;$/;" m struct:s_options +spice_sim_multi_thread_num base/vpr_types.h /^ int spice_sim_multi_thread_num;$/;" m struct:s_spice_opts +spice_sim_multi_thread_num spice/spice_globals.c /^int spice_sim_multi_thread_num = 8;$/;" v +spice_sram_inf_orgz ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_sram_inf_orgz* spice_sram_inf_orgz;$/;" m struct:s_sram_inf +spice_tb_global_clock_port_name spice/spice_globals.c /^char* spice_tb_global_clock_port_name = "gclock";$/;" v +spice_tb_global_config_done_port_name spice/spice_globals.c /^char* spice_tb_global_config_done_port_name = "gconfig_done";$/;" v +spice_tb_global_gnd_port_name spice/spice_globals.c /^char* spice_tb_global_gnd_port_name = "ggnd";$/;" v +spice_tb_global_port_inv_postfix spice/spice_globals.c /^char* spice_tb_global_port_inv_postfix = "_inv";$/;" v +spice_tb_global_reset_port_name spice/spice_globals.c /^char* spice_tb_global_reset_port_name = "greset";$/;" v +spice_tb_global_set_port_name spice/spice_globals.c /^char* spice_tb_global_set_port_name = "gset";$/;" v +spice_tb_global_vdd_cb_sram_port_name spice/spice_globals.c /^char* spice_tb_global_vdd_cb_sram_port_name = "gvdd_sram_cbs";$/;" v +spice_tb_global_vdd_hardlogic_port_name spice/spice_globals.c /^char* spice_tb_global_vdd_hardlogic_port_name = "gvdd_hardlogic";$/;" v +spice_tb_global_vdd_hardlogic_sram_port_name spice/spice_globals.c /^char* spice_tb_global_vdd_hardlogic_sram_port_name = "gvdd_sram_hardlogic";$/;" v +spice_tb_global_vdd_io_port_name spice/spice_globals.c /^char* spice_tb_global_vdd_io_port_name = "gvdd_io";$/;" v +spice_tb_global_vdd_io_sram_port_name spice/spice_globals.c /^char* spice_tb_global_vdd_io_sram_port_name = "gvdd_sram_io";$/;" v +spice_tb_global_vdd_load_port_name spice/spice_globals.c /^char* spice_tb_global_vdd_load_port_name = "gvdd_load";$/;" v +spice_tb_global_vdd_localrouting_port_name spice/spice_globals.c /^char* spice_tb_global_vdd_localrouting_port_name = "gvdd_local_interc";$/;" v +spice_tb_global_vdd_localrouting_sram_port_name spice/spice_globals.c /^char* spice_tb_global_vdd_localrouting_sram_port_name = "gvdd_sram_local_routing";$/;" v +spice_tb_global_vdd_lut_sram_port_name spice/spice_globals.c /^char* spice_tb_global_vdd_lut_sram_port_name = "gvdd_sram_luts";$/;" v +spice_tb_global_vdd_port_name spice/spice_globals.c /^char* spice_tb_global_vdd_port_name = "gvdd";$/;" v +spice_tb_global_vdd_sb_sram_port_name spice/spice_globals.c /^char* spice_tb_global_vdd_sb_sram_port_name = "gvdd_sram_sbs";$/;" v +spice_tb_global_vdd_sram_port_name spice/spice_globals.c /^char* spice_tb_global_vdd_sram_port_name = "gvdd_sram";$/;" v +spice_top_tb_dir_name spice/spice_api.c /^static char* spice_top_tb_dir_name = "top_tb\/";$/;" v file: +spice_top_testbench_postfix spice/spice_globals.c /^char* spice_top_testbench_postfix = "_top.sp";$/;" v +split_path_prog_name fpga_spice/fpga_spice_utils.c /^int split_path_prog_name(char* prog_path,$/;" f +spot_blk_position_in_a_macro place/place_macro.c /^int spot_blk_position_in_a_macro(t_pl_macro pl_macros,$/;" f +spot_int_in_array ../../libarchfpga/util.c /^int spot_int_in_array(int array_len, int* array,$/;" f +sram_bit ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_conf_bit* sram_bit;$/;" m struct:s_conf_bit_info +sram_inf ../../libarchfpga/include/physical_types.h /^ t_sram_inf sram_inf;$/;" m struct:s_arch +sram_spice_model spice/spice_globals.c /^t_spice_model* sram_spice_model = NULL;$/;" v +sram_spice_orgz_info spice/spice_globals.c /^t_sram_orgz_info* sram_spice_orgz_info = NULL;$/;" v +sram_spice_orgz_type spice/spice_globals.c /^enum e_sram_orgz sram_spice_orgz_type = SPICE_SRAM_STANDALONE;$/;" v typeref:enum:e_sram_orgz +sram_verilog_model syn_verilog/verilog_global.c /^t_spice_model* sram_verilog_model = NULL;$/;" v +sram_verilog_orgz_info syn_verilog/verilog_global.c /^t_sram_orgz_info* sram_verilog_orgz_info = NULL;$/;" v +sram_verilog_orgz_type syn_verilog/verilog_global.c /^enum e_sram_orgz sram_verilog_orgz_type = SPICE_SRAM_STANDALONE;$/;" v typeref:enum:e_sram_orgz +stage_gain power/power.h /^ float stage_gain;$/;" m struct:s_power_buffer_strength_inf +standalone ../../libarchfpga/include/ezxml.h /^ short standalone; \/* non-zero if *\/$/;" m struct:ezxml_root +standalone_sram_info ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_standalone_sram_info* standalone_sram_info; \/* Only be allocated when orgz type is standalone *\/$/;" m struct:s_sram_orgz_info +start base/vpr_types.h /^ int start;$/;" m struct:s_seg_details +start_col ../../libarchfpga/include/physical_types.h /^ int start_col;$/;" m struct:s_grid_loc_def +start_hash_table_iterator util/hash.c /^struct s_hash_iterator start_hash_table_iterator(void) {$/;" f +start_new_cluster pack/cluster.c /^static void start_new_cluster($/;" f file: +start_seg_switch ../../libarchfpga/include/arch_types_mrfpga.h /^ short start_seg_switch;$/;" m struct:s_arch_mrfpga +start_seg_switch mrfpga/mrfpga_globals.c /^short start_seg_switch;$/;" v +starting_pin_idx power/power.h /^ int starting_pin_idx; \/* Applicable to level 0 only, the overall mux primary input index *\/$/;" m struct:s_mux_node +starting_t place/place.c /^static float starting_t(float *cost_ptr, float *bb_cost_ptr,$/;" f file: +stats_lut_spice_mux fpga_spice/fpga_spice_utils.c /^void stats_lut_spice_mux(t_llist** muxes_head,$/;" f +stats_mux_spice_model_pb_node_rec fpga_spice/fpga_spice_utils.c /^void stats_mux_spice_model_pb_node_rec(t_llist** muxes_head,$/;" f +stats_mux_spice_model_pb_type_rec fpga_spice/fpga_spice_utils.c /^void stats_mux_spice_model_pb_type_rec(t_llist** muxes_head,$/;" f +stats_mux_verilog_model_pb_node_rec syn_verilog/verilog_pbtypes.c /^void stats_mux_verilog_model_pb_node_rec(t_llist** muxes_head,$/;" f +stats_mux_verilog_model_pb_type_rec syn_verilog/verilog_pbtypes.c /^void stats_mux_verilog_model_pb_type_rec(t_llist** muxes_head,$/;" f +stats_pb_graph_node_port_pin_numbers fpga_spice/fpga_spice_utils.c /^void stats_pb_graph_node_port_pin_numbers(t_pb_graph_node* cur_pb_graph_node,$/;" f +stats_spice_muxes fpga_spice/fpga_spice_utils.c /^t_llist* stats_spice_muxes(int num_switches,$/;" f +stats_spice_muxes_routing_arch fpga_spice/fpga_spice_utils.c /^void stats_spice_muxes_routing_arch(t_llist** muxes_head,$/;" f +statusMessage base/graphics.c /^static char statusMessage[BUFSIZE] = ""; \/* User message to display *\/$/;" v file: +std base/graphics.c /^using namespace std;$/;" v +std power/PowerSpicedComponent.c /^using namespace std;$/;" v +std power/power.c /^using namespace std;$/;" v +std power/power_cmos_tech.c /^using namespace std;$/;" v +std power/power_components.c /^using namespace std;$/;" v +std power/power_sizing.c /^using namespace std;$/;" v +std power/power_util.c /^using namespace std;$/;" v +stimu_header_file_name spice/spice_globals.c /^char* stimu_header_file_name = "stimulate_params.sp";$/;" v +stimulate_params ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_stimulate_params stimulate_params;$/;" m struct:s_spice_params +store_char_in_data timing/slre.c /^static void store_char_in_data(struct slre *r, int ch) {$/;" f file: +strength_inf power/power.h /^ t_power_buffer_strength_inf * strength_inf;$/;" m struct:s_power_buffer_size_inf +structure ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_model_structure structure;$/;" m struct:s_spice_model_design_tech_info typeref:enum:s_spice_model_design_tech_info::e_spice_model_structure +structure ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_model_structure structure;$/;" m struct:s_spice_mux_arch typeref:enum:s_spice_mux_arch::e_spice_model_structure +structure ../../libarchfpga/include/physical_types.h /^ enum e_spice_model_structure structure;$/;" m struct:s_switch_inf typeref:enum:s_switch_inf::e_spice_model_structure +subckt_dir base/vpr_types.h /^ char* subckt_dir;$/;" m struct:s_spice_opts +sum_pin_class pack/cluster_feasibility_filter.c /^static void sum_pin_class(INOUTP t_pb_graph_node *pb_graph_node) {$/;" f file: +swap_blk_same_class_2pins clb_pin_remap/clb_pin_remap_util.c /^void swap_blk_same_class_2pins(t_block* target_blk, int n_nets, t_net* nets,$/;" f +swap_float fpga_spice/quicksort.c /^void swap_float(float* int_a, float* int_b) {$/;" f file: +swap_int fpga_spice/quicksort.c /^void swap_int(int* int_a, int* int_b) {$/;" f file: +swap_result place/place.c /^enum swap_result {$/;" g file: +swapped_to_empty place/place.c /^ int swapped_to_empty;$/;" m struct:s_pl_moved_block file: +sweep_hanging_nets_and_inputs base/ReadOptions.h /^ boolean sweep_hanging_nets_and_inputs;$/;" m struct:s_options +sweep_hanging_nets_and_inputs base/vpr_types.h /^ boolean sweep_hanging_nets_and_inputs;$/;" m struct:s_packer_opts +switch_block_type base/vpr_types.h /^ enum e_switch_block_type switch_block_type;$/;" m struct:s_det_routing_arch typeref:enum:s_det_routing_arch::e_switch_block_type +switch_inf base/globals.c /^struct s_switch_inf *switch_inf = NULL; \/* [0..(det_routing_arch.num_switch-1)] *\/$/;" v typeref:struct:s_switch_inf +switch_inf base/globals_declare.h /^struct s_switch_inf *switch_inf; \/* [0..det_routing_arch.num_switch-1] *\/$/;" v typeref:struct:s_switch_inf +switch_num_level ../../libarchfpga/include/physical_types.h /^ int switch_num_level;$/;" m struct:s_switch_inf +switches base/vpr_types.h /^ short *switches;$/;" m struct:s_rr_node +swseg_pattern_change_switch_type route/rr_graph_swseg.c /^int swseg_pattern_change_switch_type(int cur_node,$/;" f file: +swseg_patterns ../../libarchfpga/include/physical_types.h /^ t_swseg_pattern_inf* swseg_patterns;$/;" m struct:s_arch +swseg_patterns base/vpr_types.h /^ t_swseg_pattern_inf* swseg_patterns; \/* Xifan TANG: Switch Segment Pattern Support *\/$/;" m struct:s_vpr_setup +syn_verilog_dir base/ReadOptions.h /^ char* syn_verilog_dir;$/;" m struct:s_options +syn_verilog_dump_dir base/vpr_types.h /^ char* syn_verilog_dump_dir;$/;" m struct:s_syn_verilog_opts +sync_arch_mrfpga_globals mrfpga/mrfpga_api.c /^void sync_arch_mrfpga_globals(t_arch_mrfpga arch_mrfpga) {$/;" f +sync_grid_to_blocks util/vpr_utils.c /^void sync_grid_to_blocks(INP int L_num_blocks,$/;" f +syntax_char ../../libarchfpga/fpga_spice_include/spice_types.h /^ char syntax_char;$/;" m struct:s_reserved_syntax_char +szAppName base/graphics.c /^static TCHAR szAppName[256], $/;" v file: +szButtonsName base/graphics.c /^szButtonsName[] = TEXT("VPR Buttons");$/;" v file: +szGraphicsName base/graphics.c /^szGraphicsName[] = TEXT("VPR Graphics"), $/;" v file: +szStatusName base/graphics.c /^szStatusName[] = TEXT("VPR Status"),$/;" v file: +t_arch ../../libarchfpga/include/physical_types.h /^typedef struct s_arch t_arch;$/;" t typeref:struct:s_arch +t_arch_mrfpga ../../libarchfpga/include/arch_types_mrfpga.h /^typedef struct s_arch_mrfpga t_arch_mrfpga;$/;" t typeref:struct:s_arch_mrfpga +t_block base/vpr_types.h /^typedef struct s_block t_block;$/;" t typeref:struct:s_block +t_buffer_inf ../../libarchfpga/include/arch_types_mrfpga.h /^typedef struct s_buffer_inf t_buffer_inf;$/;" t typeref:struct:s_buffer_inf +t_buffer_plan mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan {t_linked_int* inode_head; t_linked_int* sink_head; float* sink_delay; float C_downstream; float Tdel;} t_buffer_plan;$/;" t typeref:struct:s_buffer_plan file: +t_buffer_plan_list mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan_list { t_buffer_plan_node* front; } t_buffer_plan_list;$/;" t typeref:struct:s_buffer_plan_list file: +t_buffer_plan_node mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan_node { t_buffer_plan value; struct s_buffer_plan_node* next;} t_buffer_plan_node;$/;" t typeref:struct:s_buffer_plan_node file: +t_button base/graphics.c /^} t_button;$/;" t typeref:struct:__anon4 file: +t_button_type base/graphics.c /^} t_button_type;$/;" t typeref:enum:__anon3 file: +t_cb base/vpr_types.h /^typedef struct s_cb t_cb;$/;" t typeref:struct:s_cb +t_chan ../../libarchfpga/include/physical_types.h /^} t_chan;$/;" t typeref:struct:s_chan +t_chan_width_dist ../../libarchfpga/include/physical_types.h /^} t_chan_width_dist;$/;" t typeref:struct:s_chan_width_dist +t_chunk ../../libarchfpga/include/util.h /^} t_chunk;$/;" t typeref:struct:s_chunk +t_class ../../libarchfpga/include/physical_types.h /^typedef struct s_class t_class;$/;" t typeref:struct:s_class +t_clb_to_clb_directs route/pb_pin_eq_auto_detect.c /^} t_clb_to_clb_directs;$/;" t typeref:struct:s_clb_to_clb_directs file: +t_clb_to_clb_directs route/rr_graph.c /^} t_clb_to_clb_directs;$/;" t typeref:struct:s_clb_to_clb_directs file: +t_clock base/vpr_types.h /^} t_clock;$/;" t typeref:struct:s_clock +t_clock_arch ../../libarchfpga/include/physical_types.h /^typedef struct s_clock_arch t_clock_arch;$/;" t typeref:struct:s_clock_arch +t_clock_network ../../libarchfpga/include/physical_types.h /^typedef struct s_clock_network t_clock_network;$/;" t typeref:struct:s_clock_network +t_cluster_placement_primitive ../../libarchfpga/include/cad_types.h /^} t_cluster_placement_primitive;$/;" t typeref:struct:s_cluster_placement_primitive +t_cluster_placement_stats base/vpr_types.h /^} t_cluster_placement_stats;$/;" t typeref:struct:s_cluster_placement_stats +t_conf_bit ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_conf_bit t_conf_bit;$/;" t typeref:struct:s_conf_bit +t_conf_bit_info ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_conf_bit_info t_conf_bit_info;$/;" t typeref:struct:s_conf_bit_info +t_det_routing_arch base/vpr_types.h /^typedef struct s_det_routing_arch t_det_routing_arch;$/;" t typeref:struct:s_det_routing_arch +t_direct_inf ../../libarchfpga/include/physical_types.h /^} t_direct_inf;$/;" t typeref:struct:s_direct_inf +t_display_type base/graphics.c /^} t_display_type;$/;" t typeref:enum:__anon2 file: +t_fmap_cell base/place_and_route.h /^} t_fmap_cell;$/;" t typeref:struct:s_fmap_cell +t_fpga_spice_opts base/vpr_types.h /^typedef struct s_fpga_spice_opts t_fpga_spice_opts;$/;" t typeref:struct:s_fpga_spice_opts +t_gl_state base/graphics.c /^} t_gl_state;$/;" t typeref:struct:__anon5 file: +t_graph_type route/rr_graph.h /^typedef enum e_graph_type t_graph_type;$/;" t typeref:enum:e_graph_type +t_grid_loc_def ../../libarchfpga/include/physical_types.h /^} t_grid_loc_def;$/;" t typeref:struct:s_grid_loc_def +t_grid_tile base/vpr_types.h /^} t_grid_tile;$/;" t typeref:struct:s_grid_tile +t_interconnect ../../libarchfpga/include/physical_types.h /^typedef struct s_interconnect t_interconnect;$/;" t typeref:struct:s_interconnect +t_interconnect_pins ../../libarchfpga/include/physical_types.h /^typedef struct s_interconnect_pins t_interconnect_pins;$/;" t typeref:struct:s_interconnect_pins +t_interconnect_power ../../libarchfpga/include/physical_types.h /^typedef struct s_interconnect_power t_interconnect_power;$/;" t typeref:struct:s_interconnect_power +t_io base/vpr_types.h /^} t_io;$/;" t typeref:struct:s_io +t_ivec ../../libarchfpga/include/util.h /^} t_ivec;$/;" t typeref:struct:s_ivec +t_legal_pos place/place.c /^}t_legal_pos;$/;" t typeref:struct:s_legal_pos file: +t_linked_edge route/rr_graph_util.h /^typedef struct s_linked_edge t_linked_edge;$/;" t typeref:struct:s_linked_edge +t_linked_int ../../libarchfpga/include/util.h /^} t_linked_int;$/;" t typeref:struct:s_linked_int +t_linked_rc_edge timing/net_delay_types.h /^typedef struct s_linked_rc_edge t_linked_rc_edge;$/;" t typeref:struct:s_linked_rc_edge +t_linked_rc_ptr timing/net_delay_types.h /^typedef struct s_linked_rc_ptr t_linked_rc_ptr;$/;" t typeref:struct:s_linked_rc_ptr +t_linked_rt_edge route/route_tree_timing.h /^typedef struct s_linked_rt_edge t_linked_rt_edge;$/;" t typeref:struct:s_linked_rt_edge +t_linked_vptr ../../libarchfpga/include/util.h /^} t_linked_vptr;$/;" t typeref:struct:s_linked_vptr +t_llist ../../libarchfpga/fpga_spice_include/linkedlist.h /^typedef struct s_llist t_llist;$/;" t typeref:struct:s_llist +t_log power/power.h /^typedef struct s_log t_log;$/;" t typeref:struct:s_log +t_logical_block base/vpr_types.h /^} t_logical_block;$/;" t typeref:struct:s_logical_block +t_mem_bank_info ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_mem_bank_info t_mem_bank_info;$/;" t typeref:struct:s_mem_bank_info +t_memristor_inf ../../libarchfpga/include/arch_types_mrfpga.h /^typedef struct s_memristor_inf t_memristor_inf;$/;" t typeref:struct:s_memristor_inf +t_mode ../../libarchfpga/include/physical_types.h /^typedef struct s_mode t_mode;$/;" t typeref:struct:s_mode +t_mode_power ../../libarchfpga/include/physical_types.h /^typedef struct s_mode_power t_mode_power;$/;" t typeref:struct:s_mode_power +t_model ../../libarchfpga/include/logic_types.h /^} t_model;$/;" t typeref:struct:s_model +t_model_chain_pattern ../../libarchfpga/include/cad_types.h /^} t_model_chain_pattern;$/;" t typeref:struct:s_model_chain_pattern +t_model_ports ../../libarchfpga/include/logic_types.h /^} t_model_ports;$/;" t typeref:struct:s_model_ports +t_mux route/rr_graph.c /^} t_mux;$/;" t typeref:struct:s_mux file: +t_mux_arch power/power.h /^typedef struct s_mux_arch t_mux_arch;$/;" t typeref:struct:s_mux_arch +t_mux_node power/power.h /^typedef struct s_mux_node t_mux_node;$/;" t typeref:struct:s_mux_node +t_mux_size_distribution route/rr_graph.c /^} t_mux_size_distribution;$/;" t typeref:struct:s_mux_size_distribution file: +t_net base/vpr_types.h /^} t_net;$/;" t typeref:struct:s_net +t_net_power base/vpr_types.h /^typedef struct s_net_power t_net_power;$/;" t typeref:struct:s_net_power +t_num_mapped_opins_stats route/pb_pin_eq_auto_detect.c /^typedef struct s_num_mapped_opins_stats t_num_mapped_opins_stats;$/;" t typeref:struct:s_num_mapped_opins_stats file: +t_options base/ReadOptions.h /^typedef struct s_options t_options;$/;" t typeref:struct:s_options +t_override_constraint base/vpr_types.h /^} t_override_constraint;$/;" t typeref:struct:s_override_constraint +t_pack_molecule base/vpr_types.h /^} t_pack_molecule;$/;" t typeref:struct:s_pack_molecule +t_pack_pattern_block ../../libarchfpga/include/cad_types.h /^} t_pack_pattern_block;$/;" t typeref:struct:s_pack_pattern_block +t_pack_pattern_connections ../../libarchfpga/include/cad_types.h /^} t_pack_pattern_connections;$/;" t typeref:struct:s_pack_pattern_connections +t_pack_patterns ../../libarchfpga/include/cad_types.h /^} t_pack_patterns;$/;" t typeref:struct:s_pack_patterns +t_pb base/vpr_types.h /^} t_pb;$/;" t typeref:struct:s_pb +t_pb_graph_edge ../../libarchfpga/include/physical_types.h /^typedef struct s_pb_graph_edge t_pb_graph_edge;$/;" t typeref:struct:s_pb_graph_edge +t_pb_graph_node ../../libarchfpga/include/physical_types.h /^typedef struct s_pb_graph_node t_pb_graph_node;$/;" t typeref:struct:s_pb_graph_node +t_pb_graph_node_power ../../libarchfpga/include/physical_types.h /^typedef struct s_pb_graph_node_power t_pb_graph_node_power;$/;" t typeref:struct:s_pb_graph_node_power +t_pb_graph_pin ../../libarchfpga/include/physical_types.h /^typedef struct s_pb_graph_pin t_pb_graph_pin;$/;" t typeref:struct:s_pb_graph_pin +t_pb_graph_pin_power ../../libarchfpga/include/physical_types.h /^typedef struct s_pb_graph_pin_power t_pb_graph_pin_power;$/;" t typeref:struct:s_pb_graph_pin_power +t_pb_stats base/vpr_types.h /^} t_pb_stats;$/;" t typeref:struct:s_pb_stats +t_pb_type ../../libarchfpga/include/physical_types.h /^typedef struct s_pb_type t_pb_type;$/;" t typeref:struct:s_pb_type +t_pb_type_power ../../libarchfpga/include/physical_types.h /^typedef struct s_pb_type_power t_pb_type_power;$/;" t typeref:struct:s_pb_type_power +t_pin_to_pin_annotation ../../libarchfpga/include/physical_types.h /^typedef struct s_pin_to_pin_annotation t_pin_to_pin_annotation;$/;" t typeref:struct:s_pin_to_pin_annotation +t_pl_blocks_to_be_moved place/place.c /^}t_pl_blocks_to_be_moved;$/;" t typeref:struct:s_pl_blocks_to_be_moved file: +t_pl_macro place/place_macro.h /^} t_pl_macro;$/;" t typeref:struct:s_pl_macro +t_pl_macro_member place/place_macro.h /^} t_pl_macro_member;$/;" t typeref:struct:s_pl_macro_member +t_pl_moved_block place/place.c /^}t_pl_moved_block;$/;" t typeref:struct:s_pl_moved_block file: +t_point base/easygl_constants.h /^} t_point; \/* Used in calls to fillpoly *\/$/;" t typeref:struct:__anon1 +t_port ../../libarchfpga/include/physical_types.h /^typedef struct s_port t_port;$/;" t typeref:struct:s_port +t_port_power ../../libarchfpga/include/physical_types.h /^typedef struct s_port_power t_port_power;$/;" t typeref:struct:s_port_power +t_power_arch ../../libarchfpga/include/physical_types.h /^typedef struct s_power_arch t_power_arch;$/;" t typeref:struct:s_power_arch +t_power_buffer_sc_levr_inf power/power.h /^typedef struct s_power_buffer_sc_levr_inf t_power_buffer_sc_levr_inf;$/;" t typeref:struct:s_power_buffer_sc_levr_inf +t_power_buffer_size_inf power/power.h /^typedef struct s_power_buffer_size_inf t_power_buffer_size_inf;$/;" t typeref:struct:s_power_buffer_size_inf +t_power_buffer_strength_inf power/power.h /^typedef struct s_power_buffer_strength_inf t_power_buffer_strength_inf;$/;" t typeref:struct:s_power_buffer_strength_inf +t_power_commonly_used power/power.h /^typedef struct s_power_commonly_used t_power_commonly_used;$/;" t typeref:struct:s_power_commonly_used +t_power_components power/power_components.h /^typedef struct s_power_breakdown t_power_components;$/;" t typeref:struct:s_power_breakdown +t_power_estimation_method ../../libarchfpga/include/physical_types.h /^typedef enum e_power_estimation_method_ t_power_estimation_method;$/;" t typeref:enum:e_power_estimation_method_ +t_power_mux_info power/power.h /^typedef struct s_power_mux_info t_power_mux_info;$/;" t typeref:struct:s_power_mux_info +t_power_mux_volt_inf power/power.h /^typedef struct s_power_mux_volt_inf t_power_mux_volt_inf;$/;" t typeref:struct:s_power_mux_volt_inf +t_power_mux_volt_pair power/power.h /^typedef struct s_power_mux_volt_pair t_power_mux_volt_pair;$/;" t typeref:struct:s_power_mux_volt_pair +t_power_nmos_leakage_inf power/power.h /^typedef struct s_power_nmos_leakage_inf t_power_nmos_leakage_inf;$/;" t typeref:struct:s_power_nmos_leakage_inf +t_power_nmos_leakage_pair power/power.h /^typedef struct s_power_nmos_leakage_pair t_power_nmos_leakage_pair;$/;" t typeref:struct:s_power_nmos_leakage_pair +t_power_nmos_leakages power/power.h /^typedef struct s_power_nmos_leakages t_power_nmos_leakages;$/;" t typeref:struct:s_power_nmos_leakages +t_power_nmos_mux_inf power/power.h /^typedef struct s_power_nmos_mux_inf t_power_nmos_mux_inf;$/;" t typeref:struct:s_power_nmos_mux_inf +t_power_opts base/vpr_types.h /^typedef struct s_power_opts t_power_opts;$/;" t typeref:struct:s_power_opts +t_power_output power/power.h /^typedef struct s_power_output t_power_output;$/;" t typeref:struct:s_power_output +t_power_tech power/power.h /^typedef struct s_power_tech t_power_tech;$/;" t typeref:struct:s_power_tech +t_power_usage ../../libarchfpga/include/physical_types.h /^typedef struct s_power_usage t_power_usage;$/;" t typeref:struct:s_power_usage +t_prepacked_tnode_data base/vpr_types.h /^} t_prepacked_tnode_data;$/;" t typeref:struct:s_prepacked_tnode_data +t_rc_node timing/net_delay_types.h /^typedef struct s_rc_node t_rc_node;$/;" t typeref:struct:s_rc_node +t_report base/graphics.h /^} t_report;$/;" t typeref:struct:__anon6 +t_reserved_syntax_char ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_reserved_syntax_char t_reserved_syntax_char;$/;" t typeref:struct:s_reserved_syntax_char +t_router_opts base/vpr_types.h /^typedef struct s_router_opts t_router_opts;$/;" t typeref:struct:s_router_opts +t_rr_indexed_data base/vpr_types.h /^} t_rr_indexed_data;$/;" t typeref:struct:s_rr_indexed_data +t_rr_node base/vpr_types.h /^typedef struct s_rr_node t_rr_node;$/;" t typeref:struct:s_rr_node +t_rr_node_power power/power.h /^typedef struct s_rr_node_power t_rr_node_power;$/;" t typeref:struct:s_rr_node_power +t_rr_node_route_inf route/route_common.h /^} t_rr_node_route_inf;$/;" t typeref:struct:__anon15 +t_rr_type base/vpr_types.h /^} t_rr_type;$/;" t typeref:enum:e_rr_type +t_rt_node route/route_tree_timing.h /^typedef struct s_rt_node t_rt_node;$/;" t typeref:struct:s_rt_node +t_sb base/vpr_types.h /^typedef struct s_sb t_sb;$/;" t typeref:struct:s_sb +t_scff_info ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_scff_info t_scff_info;$/;" t typeref:struct:s_scff_info +t_sdc_clock timing/read_sdc.c /^} t_sdc_clock;$/;" t typeref:struct:s_sdc_clock file: +t_sdc_exclusive_group timing/read_sdc.c /^} t_sdc_exclusive_group;$/;" t typeref:struct:s_sdc_exclusive_group file: +t_seg_details base/vpr_types.h /^} t_seg_details;$/;" t typeref:struct:s_seg_details +t_segment_inf ../../libarchfpga/include/physical_types.h /^} t_segment_inf;$/;" t typeref:struct:s_segment_inf +t_slack base/vpr_types.h /^} t_slack;$/;" t typeref:struct:s_slack +t_solution_inf power/power.h /^typedef struct s_solution_inf t_solution_inf;$/;" t typeref:struct:s_solution_inf +t_spice ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice t_spice;$/;" t typeref:struct:s_spice +t_spice_mc_params ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_mc_params t_spice_mc_params;$/;" t typeref:struct:s_spice_mc_params +t_spice_mc_variation_params ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_mc_variation_params t_spice_mc_variation_params;$/;" t typeref:struct:s_spice_mc_variation_params +t_spice_meas_params ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_meas_params t_spice_meas_params;$/;" t typeref:struct:s_spice_meas_params +t_spice_model ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_model t_spice_model;$/;" t typeref:struct:s_spice_model +t_spice_model_buffer ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_buffer t_spice_model_buffer;$/;" t typeref:struct:s_spice_model_buffer +t_spice_model_design_tech_info ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_design_tech_info t_spice_model_design_tech_info;$/;" t typeref:struct:s_spice_model_design_tech_info +t_spice_model_netlist ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_netlist t_spice_model_netlist;$/;" t typeref:struct:s_spice_model_netlist +t_spice_model_pass_gate_logic ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_pass_gate_logic t_spice_model_pass_gate_logic;$/;" t typeref:struct:s_spice_model_pass_gate_logic +t_spice_model_port ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_port t_spice_model_port;$/;" t typeref:struct:s_spice_model_port +t_spice_model_wire_param ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_wire_param t_spice_model_wire_param;$/;" t typeref:struct:s_spice_model_wire_param +t_spice_mux_arch ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_mux_arch t_spice_mux_arch;$/;" t typeref:struct:s_spice_mux_arch +t_spice_mux_model ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_mux_model t_spice_mux_model;$/;" t typeref:struct:s_spice_mux_model +t_spice_net_info ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_net_info t_spice_net_info;$/;" t typeref:struct:s_spice_net_info +t_spice_opts base/vpr_types.h /^typedef struct s_spice_opts t_spice_opts;$/;" t typeref:struct:s_spice_opts +t_spice_params ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_params t_spice_params;$/;" t typeref:struct:s_spice_params +t_spice_stimulate_params ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_stimulate_params t_spice_stimulate_params;$/;" t typeref:struct:s_spice_stimulate_params +t_spice_tech_lib ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_tech_lib t_spice_tech_lib;$/;" t typeref:struct:s_spice_tech_lib +t_spice_transistor_type ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spice_transistor_type t_spice_transistor_type;$/;" t typeref:struct:s_spice_transistor_type +t_spicetb_info ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_spicetb_info t_spicetb_info;$/;" t typeref:struct:s_spicetb_info +t_sram_inf ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_sram_inf t_sram_inf;$/;" t typeref:struct:s_sram_inf +t_sram_inf_orgz ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_sram_inf_orgz t_sram_inf_orgz;$/;" t typeref:struct:s_sram_inf_orgz +t_sram_orgz_info ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_sram_orgz_info t_sram_orgz_info;$/;" t typeref:struct:s_sram_orgz_info +t_standalone_sram_info ../../libarchfpga/fpga_spice_include/spice_types.h /^typedef struct s_standalone_sram_info t_standalone_sram_info;$/;" t typeref:struct:s_standalone_sram_info +t_switch_block_type ../../libarchfpga/include/physical_types.h /^typedef enum e_switch_block_type t_switch_block_type;$/;" t typeref:enum:e_switch_block_type +t_switch_inf ../../libarchfpga/include/physical_types.h /^} t_switch_inf;$/;" t typeref:struct:s_switch_inf +t_swseg_pattern_inf ../../libarchfpga/include/physical_types.h /^typedef struct s_swseg_pattern_inf t_swseg_pattern_inf;$/;" t typeref:struct:s_swseg_pattern_inf +t_syn_verilog_opts base/vpr_types.h /^typedef struct s_syn_verilog_opts t_syn_verilog_opts;$/;" t typeref:struct:s_syn_verilog_opts +t_tedge base/vpr_types.h /^} t_tedge;$/;" t typeref:struct:s_tedge +t_timing_constraints base/vpr_types.h /^} t_timing_constraints;$/;" t typeref:struct:s_timing_constraints +t_timing_inf ../../libarchfpga/include/physical_types.h /^} t_timing_inf;$/;" t typeref:struct:s_timing_inf +t_timing_stats base/vpr_types.h /^} t_timing_stats;$/;" t typeref:struct:s_timing_stats +t_tnode base/vpr_types.h /^} t_tnode;$/;" t typeref:struct:s_tnode +t_token util/token.h /^typedef struct s_token t_token;$/;" t typeref:struct:s_token +t_trace base/vpr_types.h /^} t_trace;$/;" t typeref:struct:s_trace +t_transistor_inf power/power.h /^typedef struct s_transistor_inf t_transistor_inf;$/;" t typeref:struct:s_transistor_inf +t_transistor_size_inf power/power.h /^typedef struct s_transistor_size_inf t_transistor_size_inf;$/;" t typeref:struct:s_transistor_size_inf +t_type_descriptor ../../libarchfpga/include/physical_types.h /^typedef struct s_type_descriptor t_type_descriptor;$/;" t typeref:struct:s_type_descriptor +t_type_ptr ../../libarchfpga/include/physical_types.h /^typedef const struct s_type_descriptor *t_type_ptr;$/;" t typeref:struct:s_type_descriptor +t_vpr_setup base/vpr_types.h /^} t_vpr_setup;$/;" t typeref:struct:s_vpr_setup +tap_buf_level ../../libarchfpga/fpga_spice_include/spice_types.h /^ int tap_buf_level;$/;" m struct:s_spice_model_buffer +tapered_buf ../../libarchfpga/fpga_spice_include/spice_types.h /^ int tapered_buf; \/*Valid only when this is a buffer*\/$/;" m struct:s_spice_model_buffer +target_flag route/route_common.h /^ short target_flag;$/;" m struct:__anon15 +tb_cnt ../../libarchfpga/fpga_spice_include/spice_types.h /^ int tb_cnt;$/;" m struct:s_spice_model +tb_head spice/spice_globals.c /^t_llist* tb_head = NULL;$/;" v +tb_name ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* tb_name;$/;" m struct:s_spicetb_info +tb_num_grid spice/spice_grid_testbench.c /^static int tb_num_grid = 0;$/;" v file: +tb_num_hardlogic spice/spice_hardlogic_testbench.c /^static int tb_num_hardlogic = 0;$/;" v file: +tb_num_luts spice/spice_lut_testbench.c /^static int tb_num_luts = 0;$/;" v file: +tb_serial_config_mode base/vpr_types.h /^ boolean tb_serial_config_mode;$/;" m struct:s_syn_verilog_opts +td_place_exp_first base/vpr_types.h /^ float td_place_exp_first;$/;" m struct:s_placer_opts +td_place_exp_last base/vpr_types.h /^ float td_place_exp_last;$/;" m struct:s_placer_opts +tech_comp ../../libarchfpga/include/arch_types_mrfpga.h /^ enum e_tech_comp tech_comp;$/;" m struct:s_arch_mrfpga typeref:enum:s_arch_mrfpga::e_tech_comp +tech_lib ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_tech_lib tech_lib;$/;" m struct:s_spice +tech_size power/power.h /^ float tech_size; \/* Tech size in nm, for example 90e-9 for 90nm *\/$/;" m struct:s_power_tech +tedge_ch timing/path_delay.c /^static t_chunk tedge_ch = {NULL, 0, NULL};$/;" v file: +temp_net_cost place/place.c /^static float *net_cost = NULL, *temp_net_cost = NULL; \/* [0..num_nets-1] *\/$/;" v file: +temp_net_num ../../libarchfpga/include/physical_types.h /^ int temp_net_num;$/;" m struct:s_pb_graph_pin +temp_num_pins base/read_blif.c /^static int *num_driver, *temp_num_pins;$/;" v file: +temp_point_to_point_delay_cost place/place.c /^static float **temp_point_to_point_delay_cost = NULL;$/;" v file: +temp_point_to_point_timing_cost place/place.c /^static float **temp_point_to_point_timing_cost = NULL;$/;" v file: +temp_scratch_pad ../../libarchfpga/include/physical_types.h /^ void *temp_scratch_pad; \/* temporary data, useful for keeping track of things when traversing data structure *\/$/;" m struct:s_pb_graph_node +temp_used base/vpr_types.h /^ int temp_used;$/;" m struct:s_logical_block +temperature power/power.h /^ float temperature; \/* Temp in C *\/$/;" m struct:s_power_tech +test_if_exposed base/graphics.c /^static Bool test_if_exposed (Display *disp, XEvent *event_ptr, XPointer dummy) $/;" f file: +testbench_cb_mux_cnt spice/spice_mux_testbench.c /^static int testbench_cb_mux_cnt = 0;$/;" v file: +testbench_load_cnt spice/spice_grid_testbench.c /^static int testbench_load_cnt = 0;$/;" v file: +testbench_load_cnt spice/spice_hardlogic_testbench.c /^static int testbench_load_cnt = 0;$/;" v file: +testbench_load_cnt spice/spice_lut_testbench.c /^static int testbench_load_cnt = 0;$/;" v file: +testbench_load_cnt spice/spice_mux_testbench.c /^static int testbench_load_cnt = 0;$/;" v file: +testbench_load_cnt spice/spice_routing_testbench.c /^static int testbench_load_cnt = 0;$/;" v file: +testbench_mux_cnt spice/spice_mux_testbench.c /^static int testbench_mux_cnt = 0;$/;" v file: +testbench_muxes_head spice/spice_mux_testbench.c /^static t_llist* testbench_muxes_head = NULL; $/;" v file: +testbench_pb_mux_cnt spice/spice_mux_testbench.c /^static int testbench_pb_mux_cnt = 0;$/;" v file: +testbench_sb_mux_cnt spice/spice_mux_testbench.c /^static int testbench_sb_mux_cnt = 0;$/;" v file: +testbench_sram_cnt spice/spice_mux_testbench.c /^static int testbench_sram_cnt = 0;$/;" v file: +text base/graphics.c /^ char text[BUTTON_TEXT_LEN]; $/;" m struct:__anon4 file: +textarea base/graphics.c /^static Window toplevel, menu, textarea; \/* various windows *\/$/;" v file: +tie_break_high_fanout_net base/vpr_types.h /^ int tie_break_high_fanout_net; \/* If no marked candidate atoms, use this high fanout net to determine the next candidate atom *\/$/;" m struct:s_pb_stats +tile_length power/power.h /^ float tile_length;$/;" m struct:s_power_commonly_used +tile_width base/draw.c /^static float tile_width, pin_size;$/;" v file: +tile_x base/draw.c /^static float *tile_x, *tile_y;$/;" v file: +tile_y base/draw.c /^static float *tile_x, *tile_y;$/;" v file: +timing_analysis_enabled ../../libarchfpga/include/physical_types.h /^ boolean timing_analysis_enabled;$/;" m struct:s_timing_inf +timing_criticality base/vpr_types.h /^ float ** timing_criticality;$/;" m struct:s_slack +timing_driven base/ReadOptions.h /^ boolean timing_driven;$/;" m struct:s_options +timing_driven base/vpr_types.h /^ boolean timing_driven;$/;" m struct:s_packer_opts +timing_driven_check_net_delays route/route_timing.c /^static void timing_driven_check_net_delays(float **net_delay) {$/;" f file: +timing_driven_expand_neighbours route/route_timing.c /^static void timing_driven_expand_neighbours(struct s_heap *current, int inet,$/;" f file: +timing_driven_route_net route/route_timing.c /^boolean timing_driven_route_net(int inet, float pres_fac, float max_criticality,$/;" f +timing_nets timing/path_delay.c /^static struct s_net *timing_nets = NULL;$/;" v typeref:struct:s_net file: +timing_place_crit place/timing_place.c /^float **timing_place_crit; \/*available externally *\/$/;" v +timing_place_crit_ch place/timing_place.c /^static t_chunk timing_place_crit_ch = {NULL, 0, NULL};$/;" v file: +timing_tradeoff base/vpr_types.h /^ float timing_tradeoff;$/;" m struct:s_placer_opts +timinggain base/vpr_types.h /^ std::map timinggain; \/* [0..num_logical_blocks-1]. The timing criticality score of this logical_block. $/;" m struct:s_pb_stats +tnode base/vpr_types.h /^ t_tnode *tnode;$/;" m struct:s_rr_node +tnode timing/path_delay.c /^t_tnode *tnode = NULL; \/* [0..num_tnodes - 1] *\/$/;" v +tnodes_at_level timing/path_delay2.c /^struct s_ivec *tnodes_at_level;$/;" v typeref:struct:s_ivec +to_block ../../libarchfpga/include/cad_types.h /^ t_pack_pattern_block *to_block;$/;" m struct:s_pack_pattern_connections +to_clb_pin_end_index route/pb_pin_eq_auto_detect.c /^ int to_clb_pin_end_index;$/;" m struct:s_clb_to_clb_directs file: +to_clb_pin_end_index route/rr_graph.c /^ int to_clb_pin_end_index;$/;" m struct:s_clb_to_clb_directs file: +to_clb_pin_start_index route/pb_pin_eq_auto_detect.c /^ int to_clb_pin_start_index;$/;" m struct:s_clb_to_clb_directs file: +to_clb_pin_start_index route/rr_graph.c /^ int to_clb_pin_start_index;$/;" m struct:s_clb_to_clb_directs file: +to_clb_type route/pb_pin_eq_auto_detect.c /^ t_type_descriptor *to_clb_type;$/;" m struct:s_clb_to_clb_directs file: +to_clb_type route/rr_graph.c /^ t_type_descriptor *to_clb_type;$/;" m struct:s_clb_to_clb_directs file: +to_node base/vpr_types.h /^ int to_node; \/* index of node at the sink end of this edge *\/$/;" m struct:s_tedge +to_pin ../../libarchfpga/include/cad_types.h /^ t_pb_graph_pin *to_pin;$/;" m struct:s_pack_pattern_connections +to_pin ../../libarchfpga/include/physical_types.h /^ char *to_pin;$/;" m struct:s_direct_inf +toggle_congestion base/draw.c /^static void toggle_congestion(void (*drawscreen_ptr)(void)) {$/;" f file: +toggle_defects base/draw.c /^static void toggle_defects(void (*drawscreen_ptr)(void)) {$/;" f file: +toggle_nets base/draw.c /^static void toggle_nets(void (*drawscreen_ptr)(void)) {$/;" f file: +toggle_rr base/draw.c /^static void toggle_rr(void (*drawscreen_ptr)(void)) {$/;" f file: +top_height base/graphics.c /^static int top_width, top_height; \/* window size *\/$/;" v file: +top_height base/graphics.h /^ int top_width, top_height;$/;" m struct:__anon6 +top_netlist_addr_bl_port_name syn_verilog/verilog_top_netlist.c /^static char* top_netlist_addr_bl_port_name = "addr_bl";$/;" v file: +top_netlist_addr_wl_port_name syn_verilog/verilog_top_netlist.c /^static char* top_netlist_addr_wl_port_name = "addr_wl";$/;" v file: +top_netlist_array_bl_port_name syn_verilog/verilog_top_netlist.c /^static char* top_netlist_array_bl_port_name = "bl_bus";$/;" v file: +top_netlist_array_blb_port_name syn_verilog/verilog_top_netlist.c /^static char* top_netlist_array_blb_port_name = "blb_bus";$/;" v file: +top_netlist_array_wl_port_name syn_verilog/verilog_top_netlist.c /^static char* top_netlist_array_wl_port_name = "wl_bus";$/;" v file: +top_netlist_array_wlb_port_name syn_verilog/verilog_top_netlist.c /^static char* top_netlist_array_wlb_port_name = "wlb_bus";$/;" v file: +top_netlist_bl_data_in_port_name syn_verilog/verilog_top_netlist.c /^static char* top_netlist_bl_data_in_port_name = "data_in";$/;" v file: +top_netlist_bl_enable_port_name syn_verilog/verilog_top_netlist.c /^static char* top_netlist_bl_enable_port_name = "en_bl";$/;" v file: +top_netlist_normal_bl_port_postfix syn_verilog/verilog_top_netlist.c /^static char* top_netlist_normal_bl_port_postfix = "_bl";$/;" v file: +top_netlist_normal_blb_port_postfix syn_verilog/verilog_top_netlist.c /^static char* top_netlist_normal_blb_port_postfix = "_blb";$/;" v file: +top_netlist_normal_wl_port_postfix syn_verilog/verilog_top_netlist.c /^static char* top_netlist_normal_wl_port_postfix = "_wl";$/;" v file: +top_netlist_normal_wlb_port_postfix syn_verilog/verilog_top_netlist.c /^static char* top_netlist_normal_wlb_port_postfix = "_wlb";$/;" v file: +top_netlist_reserved_bl_port_postfix syn_verilog/verilog_top_netlist.c /^static char* top_netlist_reserved_bl_port_postfix = "_reserved_bl";$/;" v file: +top_netlist_reserved_wl_port_postfix syn_verilog/verilog_top_netlist.c /^static char* top_netlist_reserved_wl_port_postfix = "_reserved_wl";$/;" v file: +top_netlist_scan_chain_head_prefix syn_verilog/verilog_top_netlist.c /^static char* top_netlist_scan_chain_head_prefix = "sc_in";$/;" v file: +top_netlist_wl_enable_port_name syn_verilog/verilog_top_netlist.c /^static char* top_netlist_wl_enable_port_name = "en_wl";$/;" v file: +top_tb_clock_reg_postfix syn_verilog/verilog_top_netlist.c /^static char* top_tb_clock_reg_postfix = "_reg";$/;" v file: +top_tb_config_done_port_name syn_verilog/verilog_top_netlist.c /^static char* top_tb_config_done_port_name = "config_done";$/;" v file: +top_tb_inout_reg_postfix syn_verilog/verilog_top_netlist.c /^static char* top_tb_inout_reg_postfix = "_reg";$/;" v file: +top_tb_op_clock_port_name syn_verilog/verilog_top_netlist.c /^static char* top_tb_op_clock_port_name = "op_clock";$/;" v file: +top_tb_prog_clock_port_name syn_verilog/verilog_top_netlist.c /^static char* top_tb_prog_clock_port_name = "prog_clock";$/;" v file: +top_tb_prog_reset_port_name syn_verilog/verilog_top_netlist.c /^static char* top_tb_prog_reset_port_name = "prog_reset";$/;" v file: +top_tb_prog_set_port_name syn_verilog/verilog_top_netlist.c /^static char* top_tb_prog_set_port_name = "prog_set";$/;" v file: +top_tb_reset_port_name syn_verilog/verilog_top_netlist.c /^static char* top_tb_reset_port_name = "greset";$/;" v file: +top_tb_set_port_name syn_verilog/verilog_top_netlist.c /^static char* top_tb_set_port_name = "gset";$/;" v file: +top_testbench_verilog_file_postfix syn_verilog/verilog_global.c /^char* top_testbench_verilog_file_postfix = "_top_tb.v";$/;" v +top_width base/graphics.c /^static int top_width, top_height; \/* window size *\/$/;" v file: +top_width base/graphics.h /^ int top_width, top_height;$/;" m struct:__anon6 +toplevel base/graphics.c /^static Window toplevel, menu, textarea; \/* various windows *\/$/;" v file: +total_cb_buffer_size power/power.h /^ float total_cb_buffer_size;$/;" m struct:s_power_commonly_used +total_cb_mux_input_density spice/spice_mux_testbench.c /^static float total_cb_mux_input_density = 0.;$/;" v file: +total_pb_mux_input_density spice/spice_mux_testbench.c /^static float total_pb_mux_input_density = 0.;$/;" v file: +total_pb_pins ../../libarchfpga/include/physical_types.h /^ int total_pb_pins; \/* only valid for top-level *\/$/;" m struct:s_pb_graph_node +total_sb_buffer_size power/power.h /^ float total_sb_buffer_size;$/;" m struct:s_power_commonly_used +total_sb_mux_input_density spice/spice_mux_testbench.c /^static float total_sb_mux_input_density = 0.;$/;" v file: +trace_ch route/route_common.c /^static t_chunk trace_ch = {NULL, 0, NULL};$/;" v file: +trace_free_head route/route_common.c /^static struct s_trace *trace_free_head = NULL;$/;" v typeref:struct:s_trace file: +trace_head base/globals.c /^struct s_trace **trace_head = NULL; \/* [0..(num_nets-1)] *\/$/;" v typeref:struct:s_trace +trace_head base/globals_declare.h /^struct s_trace **trace_head, **trace_tail;$/;" v typeref:struct:s_trace +trace_tail base/globals.c /^struct s_trace **trace_tail = NULL; \/* [0..(num_nets-1)] *\/$/;" v typeref:struct:s_trace +trace_tail base/globals_declare.h /^struct s_trace **trace_head, **trace_tail;$/;" v typeref:struct: +trans_per_R route/rr_graph_area.c /^static float trans_per_R(float Rtrans, float R_minW_trans) {$/;" f file: +trans_per_buf route/rr_graph_area.c /^float trans_per_buf(float Rbuf, float R_minW_nmos, float R_minW_pmos) {$/;" f +trans_per_mux route/rr_graph_area.c /^static float trans_per_mux(int num_inputs, float trans_sram_bit,$/;" f file: +transistor_cnt ../../libarchfpga/include/physical_types.h /^ float transistor_cnt;$/;" m struct:s_interconnect_power +transistor_cnt_buffers ../../libarchfpga/include/physical_types.h /^ float transistor_cnt_buffers;$/;" m struct:s_pb_graph_node_power +transistor_cnt_interc ../../libarchfpga/include/physical_types.h /^ float transistor_cnt_interc; \/* Total transistor size of the interconnect in this pb *\/$/;" m struct:s_pb_graph_node_power +transistor_cnt_pb_children ../../libarchfpga/include/physical_types.h /^ float transistor_cnt_pb_children; \/* Total transistor size of this pb *\/$/;" m struct:s_pb_graph_node_power +transistor_size power/PowerSpicedComponent.h /^ float transistor_size;$/;" m class:PowerCallibSize +transistor_size power/power.h /^ float transistor_size;$/;" m struct:s_mux_arch +transistor_type ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* transistor_type;$/;" m struct:s_spice_tech_lib +transistor_type_name power/power_util.c /^char * transistor_type_name(e_tx_type type) {$/;" f +transistor_types ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_transistor_type* transistor_types;$/;" m struct:s_spice_tech_lib +transistors_per_SRAM_bit ../../libarchfpga/include/physical_types.h /^ float transistors_per_SRAM_bit;$/;" m struct:s_power_arch +translate_down base/graphics.c /^translate_down (void (*drawscreen) (void)) $/;" f file: +translate_left base/graphics.c /^translate_left (void (*drawscreen) (void)) $/;" f file: +translate_right base/graphics.c /^translate_right (void (*drawscreen) (void)) $/;" f file: +translate_up base/graphics.c /^translate_up (void (*drawscreen) (void)) $/;" f file: +traverse_clb base/verilog_writer.c /^pb_list *traverse_clb(t_pb *pb , pb_list *prim_list)$/;" f +traverse_linked_list base/verilog_writer.c /^void traverse_linked_list(pb_list *list)$/;" f +traverse_linked_list_conn base/verilog_writer.c /^void traverse_linked_list_conn(conn_list *list)$/;" f +tree_mux_last_level_input_num fpga_spice/fpga_spice_utils.c /^int tree_mux_last_level_input_num(int num_level,$/;" f +tried base/vpr_types.h /^ t_cluster_placement_primitive *tried; \/* ptrs to primitives that are open but current logic block unable to pack to *\/$/;" m struct:s_cluster_placement_stats +trigger_type base/vpr_types.h /^ char* trigger_type;$/;" m struct:s_logical_block +truth_table base/vpr_types.h /^ struct s_linked_vptr *truth_table; \/* If this is a LUT (.names), then this is the logic that the LUT implements *\/$/;" m struct:s_logical_block typeref:struct:s_logical_block::s_linked_vptr +try_access_dir fpga_spice/fpga_spice_utils.c /^enum e_dir_err try_access_dir(char* dir_path) {$/;" f +try_access_file fpga_spice/fpga_spice_utils.c /^int try_access_file(char* file_path) {$/;" f +try_breadth_first_route route/route_breadth_first.c /^boolean try_breadth_first_route(struct s_router_opts router_opts,$/;" f +try_breadth_first_route_cluster pack/cluster_legality.c /^boolean try_breadth_first_route_cluster(void) {$/;" f +try_buffer_for_net mrfpga/buffer_insertion.c /^void try_buffer_for_net( int inet, t_rc_node** rc_node_free_list, t_linked_rc_edge** rc_edge_free_list, t_linked_rc_ptr* rr_node_to_rc_node, float* net_delay ) {$/;" f +try_buffer_for_routing mrfpga/buffer_insertion.c /^void try_buffer_for_routing ( float** net_delay ) {$/;" f +try_buffer_rc_tree mrfpga/buffer_insertion.c /^static t_buffer_plan_list try_buffer_rc_tree (t_rc_node *rc_node, int num_pins, int* isink_to_inode) {$/;" f file: +try_clb_pin_remap_after_placement clb_pin_remap/place_clb_pin_remap.c /^void try_clb_pin_remap_after_placement(t_det_routing_arch det_routing_arch,$/;" f +try_create_molecule pack/prepack.c /^static t_pack_molecule *try_create_molecule($/;" f file: +try_expand_molecule pack/prepack.c /^static boolean try_expand_molecule(INOUTP t_pack_molecule *molecule,$/;" f file: +try_pack pack/pack.c /^void try_pack(INP struct s_packer_opts *packer_opts, INP const t_arch * arch,$/;" f +try_pack_molecule pack/cluster.c /^static enum e_block_pack_status try_pack_molecule($/;" f file: +try_place place/place.c /^void try_place(struct s_placer_opts placer_opts,$/;" f +try_place_logical_block_rec pack/cluster.c /^static enum e_block_pack_status try_place_logical_block_rec($/;" f file: +try_place_macro place/place.c /^static int try_place_macro(int itype, int ichoice, int imacro, int * free_locations){$/;" f file: +try_place_molecule pack/cluster_placement.c /^static float try_place_molecule(INP t_pack_molecule *molecule,$/;" f file: +try_remap_blk_class_one_conflict_pin clb_pin_remap/place_clb_pin_remap.c /^int try_remap_blk_class_one_conflict_pin(t_block* target_blk, int class_index, int pin_index,$/;" f +try_route route/route_common.c /^boolean try_route(int width_fac, struct s_router_opts router_opts,$/;" f +try_sat_one_blk_pin_class_prefer_side clb_pin_remap/place_clb_pin_remap.c /^int try_sat_one_blk_pin_class_prefer_side(t_block* target_blk,$/;" f +try_swap place/place.c /^static enum swap_result try_swap(float t, float *cost, float *bb_cost, float *timing_cost,$/;" f file: +try_timing_driven_route route/route_timing.c /^boolean try_timing_driven_route(struct s_router_opts router_opts,$/;" f +try_update_lookahead_pins_used pack/cluster.c /^static void try_update_lookahead_pins_used(t_pb *cur_pb) {$/;" f file: +try_update_sram_orgz_info_reserved_blwl fpga_spice/fpga_spice_utils.c /^void try_update_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info,$/;" f +ts_bb_coord_new place/place.c /^static struct s_bb *ts_bb_coord_new = NULL;$/;" v typeref:struct:s_bb file: +ts_bb_edge_new place/place.c /^static struct s_bb *ts_bb_edge_new = NULL;$/;" v typeref:struct:s_bb file: +ts_nets_to_update place/place.c /^static int *ts_nets_to_update = NULL;$/;" v file: +tsu_tco ../../libarchfpga/include/physical_types.h /^ float tsu_tco; \/* For sequential logic elements, this is the setup time (if input) or clock-to-q time (if output) *\/$/;" m struct:s_pb_graph_pin +turn_on_off base/graphics.c /^static void turn_on_off (int pressed) {$/;" f file: +twisted base/vpr_types.h /^ boolean twisted;$/;" m struct:s_seg_details +txt ../../libarchfpga/include/ezxml.h /^ char *txt; \/* tag character content, empty string if none *\/$/;" m struct:ezxml +type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_model_buffer_type type;$/;" m struct:s_spice_model_buffer typeref:enum:s_spice_model_buffer::e_spice_model_buffer_type +type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_model_pass_gate_logic_type type;$/;" m struct:s_spice_model_pass_gate_logic typeref:enum:s_spice_model_pass_gate_logic::e_spice_model_pass_gate_logic_type +type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_model_port_type type;$/;" m struct:s_spice_model_port typeref:enum:s_spice_model_port::e_spice_model_port_type +type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_model_type type;$/;" m struct:s_spice_model typeref:enum:s_spice_model::e_spice_model_type +type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_tech_lib_type type;$/;" m struct:s_spice_tech_lib typeref:enum:s_spice_tech_lib::e_spice_tech_lib_type +type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_spice_trans_type type;$/;" m struct:s_spice_transistor_type typeref:enum:s_spice_transistor_type::e_spice_trans_type +type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_sram_orgz type;$/;" m struct:s_sram_inf_orgz typeref:enum:s_sram_inf_orgz::e_sram_orgz +type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_sram_orgz type;$/;" m struct:s_sram_orgz_info typeref:enum:s_sram_orgz_info::e_sram_orgz +type ../../libarchfpga/fpga_spice_include/spice_types.h /^ enum e_wire_model_type type;$/;" m struct:s_spice_model_wire_param typeref:enum:s_spice_model_wire_param::e_wire_model_type +type ../../libarchfpga/include/physical_types.h /^ enum PORTS type;$/;" m struct:s_port typeref:enum:s_port::PORTS +type ../../libarchfpga/include/physical_types.h /^ enum e_interconnect type;$/;" m struct:s_interconnect typeref:enum:s_interconnect::e_interconnect +type ../../libarchfpga/include/physical_types.h /^ enum e_pb_graph_pin_type type; \/* Is a sequential logic element (TRUE), inpad\/outpad (TRUE), or neither (FALSE) *\/$/;" m struct:s_pb_graph_pin typeref:enum:s_pb_graph_pin::e_pb_graph_pin_type +type ../../libarchfpga/include/physical_types.h /^ enum e_pin_to_pin_annotation_type type;$/;" m struct:s_pin_to_pin_annotation typeref:enum:s_pin_to_pin_annotation::e_pin_to_pin_annotation_type +type ../../libarchfpga/include/physical_types.h /^ enum e_pin_type type;$/;" m struct:s_class typeref:enum:s_class::e_pin_type +type ../../libarchfpga/include/physical_types.h /^ enum e_stat type;$/;" m struct:s_chan typeref:enum:s_chan::e_stat +type ../../libarchfpga/include/physical_types.h /^ char* type;$/;" m struct:s_switch_inf +type ../../libarchfpga/include/physical_types.h /^ enum e_swseg_pattern_type type;$/;" m struct:s_swseg_pattern_inf typeref:enum:s_swseg_pattern_inf::e_swseg_pattern_type +type base/graphics.c /^ t_button_type type;$/;" m struct:__anon4 file: +type base/vpr_types.h /^ e_tnode_type type; \/* see the above enum *\/$/;" m struct:s_tnode +type base/vpr_types.h /^ enum e_pack_pattern_molecule_type type; \/* what kind of molecule is this? *\/$/;" m struct:s_pack_molecule typeref:enum:s_pack_molecule::e_pack_pattern_molecule_type +type base/vpr_types.h /^ enum logical_block_types type; \/* I\/O, combinational logic, or latch *\/$/;" m struct:s_logical_block typeref:enum:s_logical_block::logical_block_types +type base/vpr_types.h /^ enum sched_type type;$/;" m struct:s_annealing_sched typeref:enum:s_annealing_sched::sched_type +type base/vpr_types.h /^ t_rr_type type;$/;" m struct:s_rr_node +type base/vpr_types.h /^ t_type_ptr type;$/;" m struct:s_block +type base/vpr_types.h /^ t_type_ptr type;$/;" m struct:s_grid_tile +type base/vpr_types.h /^ t_rr_type type;$/;" m struct:s_cb +type util/token.h /^ enum e_token_type type;$/;" m struct:s_token typeref:enum:s_token::e_token_type +type_descriptors base/globals.c /^struct s_type_descriptor *type_descriptors = NULL;$/;" v typeref:struct:s_type_descriptor +type_descriptors_backup place/timing_place_lookup.c /^static t_type_descriptor *type_descriptors_backup;$/;" v file: +u ../../libarchfpga/include/ezxml.h /^ char *u; \/* UTF-8 conversion of string if original was UTF-16 *\/$/;" m struct:ezxml_root +u route/route_common.h /^ } u;$/;" m struct:s_heap typeref:union:s_heap::__anon14 +u route/route_tree_timing.h /^ } u;$/;" m struct:s_rt_node typeref:union:s_rt_node::__anon16 +u timing/net_delay_types.h /^ } u;$/;" m struct:s_rc_node typeref:union:s_rc_node::__anon18 +unbuf_switch ../../libarchfpga/include/physical_types.h /^ short unbuf_switch;$/;" m struct:s_swseg_pattern_inf +unbuf_switched base/vpr_types.h /^ int unbuf_switched; \/* Xifan TANG: Switch Segment Pattern Support*\/$/;" m struct:s_rr_node +unclustered_list_head pack/cluster.c /^static struct s_molecule_link *unclustered_list_head;$/;" v typeref:struct:s_molecule_link file: +unclustered_list_head_size pack/cluster.c /^int unclustered_list_head_size;$/;" v +unmap_button base/graphics.c /^static void unmap_button (int bnum) $/;" f file: +unmark_fanout_intermediate_nodes pack/cluster_feasibility_filter.c /^static void unmark_fanout_intermediate_nodes($/;" f file: +upbound_sim_num_clock_cycles spice/spice_grid_testbench.c /^static int upbound_sim_num_clock_cycles = 2;$/;" v file: +upbound_sim_num_clock_cycles spice/spice_hardlogic_testbench.c /^static int upbound_sim_num_clock_cycles = 2;$/;" v file: +upbound_sim_num_clock_cycles spice/spice_lut_testbench.c /^static int upbound_sim_num_clock_cycles = 2;$/;" v file: +upbound_sim_num_clock_cycles spice/spice_mux_testbench.c /^static int upbound_sim_num_clock_cycles = 2;$/;" v file: +upbound_sim_num_clock_cycles spice/spice_routing_testbench.c /^static int upbound_sim_num_clock_cycles = 2;$/;" v file: +updateRect base/graphics.c /^static RECT adjustRect, updateRect;$/;" v file: +update_bb place/place.c /^static void update_bb(int inet, struct s_bb *bb_coord_new,$/;" f file: +update_cluster_stats pack/cluster.c /^static void update_cluster_stats( INP t_pack_molecule *molecule,$/;" f file: +update_connection_gain_values pack/cluster.c /^static void update_connection_gain_values(int inet, int clustered_block,$/;" f file: +update_grid_pb_pins_parasitic_nets fpga_spice/fpga_spice_backannotate_utils.c /^void update_grid_pb_pins_parasitic_nets() {$/;" f +update_grid_pbs_post_route_rr_graph fpga_spice/fpga_spice_backannotate_utils.c /^void update_grid_pbs_post_route_rr_graph() {$/;" f +update_mem_bank_info_num_blwl fpga_spice/fpga_spice_utils.c /^void update_mem_bank_info_num_blwl(t_mem_bank_info* cur_mem_bank_info,$/;" f +update_mem_bank_info_num_mem_bit fpga_spice/fpga_spice_utils.c /^void update_mem_bank_info_num_mem_bit(t_mem_bank_info* cur_mem_bank_info,$/;" f +update_mem_bank_info_reserved_blwl fpga_spice/fpga_spice_utils.c /^void update_mem_bank_info_reserved_blwl(t_mem_bank_info* cur_mem_bank_info,$/;" f +update_message base/graphics.c /^update_message (const char *msg) $/;" f +update_message base/graphics.c /^void update_message (const char *msg) { }$/;" f +update_net_delays_from_route_tree route/route_tree_timing.c /^void update_net_delays_from_route_tree(float *net_delay,$/;" f +update_normalized_costs timing/path_delay.c /^static void update_normalized_costs(float criticality_denom, long max_critical_input_paths,$/;" f file: +update_one_grid_pack_prev_node_edge fpga_spice/fpga_spice_backannotate_utils.c /^void update_one_grid_pack_prev_node_edge(int x, int y) {$/;" f +update_one_grid_pb_pins_parasitic_nets fpga_spice/fpga_spice_backannotate_utils.c /^void update_one_grid_pb_pins_parasitic_nets(int ix, int iy) {$/;" f +update_one_spice_model_grid_index_high fpga_spice/fpga_spice_utils.c /^void update_one_spice_model_grid_index_high(int x, int y, $/;" f +update_one_spice_model_grid_index_low fpga_spice/fpga_spice_utils.c /^void update_one_spice_model_grid_index_low(int x, int y, $/;" f +update_one_spice_model_routing_index_high fpga_spice/fpga_spice_utils.c /^void update_one_spice_model_routing_index_high(int x, int y, t_rr_type chan_type,$/;" f +update_one_spice_model_routing_index_low fpga_spice/fpga_spice_utils.c /^void update_one_spice_model_routing_index_low(int x, int y, t_rr_type chan_type,$/;" f +update_one_unused_grid_output_pins_parasitic_nets fpga_spice/fpga_spice_backannotate_utils.c /^void update_one_unused_grid_output_pins_parasitic_nets(int ix, int iy) {$/;" f +update_one_used_grid_pb_pins_parasitic_nets fpga_spice/fpga_spice_backannotate_utils.c /^void update_one_used_grid_pb_pins_parasitic_nets(t_pb* cur_pb,$/;" f +update_pb_graph_node_temp_net_num_to_pb fpga_spice/fpga_spice_utils.c /^void update_pb_graph_node_temp_net_num_to_pb(t_pb_graph_node* cur_pb_graph_node,$/;" f +update_pb_vpack_net_num_from_temp_net_num fpga_spice/fpga_spice_utils.c /^void update_pb_vpack_net_num_from_temp_net_num(t_pb* cur_pb, $/;" f +update_primitive_cost_or_status pack/cluster_placement.c /^static void update_primitive_cost_or_status(INP t_pb_graph_node *pb_graph_node,$/;" f file: +update_ps_transform base/graphics.c /^update_ps_transform (void) $/;" f file: +update_rlim place/place.c /^static void update_rlim(float *rlim, float success_rat) {$/;" f file: +update_route_tree route/route_tree_timing.c /^update_route_tree(struct s_heap * hptr) {$/;" f +update_rr_base_costs route/route_timing.c /^static void update_rr_base_costs(int inet, float largest_criticality) {$/;" f file: +update_rr_nodes_driver_switch route/rr_graph_swseg.c /^void update_rr_nodes_driver_switch(enum e_directionality directionality) {$/;" f +update_scff_info_num_mem_bit fpga_spice/fpga_spice_utils.c /^void update_scff_info_num_mem_bit(t_scff_info* cur_scff_info,$/;" f +update_screen base/draw.c /^void update_screen(int priority, char *msg, enum pic_type pic_on_screen_val,$/;" f +update_slacks timing/path_delay.c /^static void update_slacks(t_slack * slacks, int source_clock_domain, int sink_clock_domain, float criticality_denom,$/;" f file: +update_spice_models_grid_index_high fpga_spice/fpga_spice_utils.c /^void update_spice_models_grid_index_high(int x, int y, $/;" f +update_spice_models_grid_index_low fpga_spice/fpga_spice_utils.c /^void update_spice_models_grid_index_low(int x, int y, $/;" f +update_spice_models_routing_index_high fpga_spice/fpga_spice_utils.c /^void update_spice_models_routing_index_high(int x, int y, t_rr_type chan_type,$/;" f +update_spice_models_routing_index_low fpga_spice/fpga_spice_utils.c /^void update_spice_models_routing_index_low(int x, int y, t_rr_type chan_type, $/;" f +update_sram_orgz_info_num_blwl fpga_spice/fpga_spice_utils.c /^void update_sram_orgz_info_num_blwl(t_sram_orgz_info* cur_sram_orgz_info,$/;" f +update_sram_orgz_info_num_mem_bit fpga_spice/fpga_spice_utils.c /^void update_sram_orgz_info_num_mem_bit(t_sram_orgz_info* cur_sram_orgz_info,$/;" f +update_sram_orgz_info_reserved_blwl fpga_spice/fpga_spice_utils.c /^void update_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info,$/;" f +update_standalone_sram_info_num_mem_bit fpga_spice/fpga_spice_utils.c /^void update_standalone_sram_info_num_mem_bit(t_standalone_sram_info* cur_standalone_sram_info,$/;" f +update_t place/place.c /^static void update_t(float *t, float std_dev, float rlim, float success_rat,$/;" f file: +update_td_cost place/place.c /^static void update_td_cost(void) {$/;" f file: +update_timing_gain_values pack/cluster.c /^static void update_timing_gain_values(int inet, int clustered_block,$/;" f file: +update_total_gain pack/cluster.c /^static void update_total_gain(float alpha, float beta, boolean timing_driven,$/;" f file: +update_traceback route/route_common.c /^update_traceback(struct s_heap *hptr, int inet) {$/;" f +update_transform base/graphics.c /^update_transform (void) $/;" f file: +update_unbuffered_ancestors_C_downstream route/route_tree_timing.c /^update_unbuffered_ancestors_C_downstream(t_rt_node * start_of_new_path_rt_node) {$/;" f file: +update_win base/graphics.c /^update_win (int x[2], int y[2], void (*drawscreen)(void)) $/;" f file: +usage base/vpr_types.h /^ int usage;$/;" m struct:s_grid_tile +use_default_timing_constraints timing/read_sdc.c /^static void use_default_timing_constraints(void) {$/;" f file: +used ../../libarchfpga/include/logic_types.h /^ int used;$/;" m struct:s_model +used_input_pins base/vpr_types.h /^ int used_input_pins; \/* Number of used input pins *\/$/;" m struct:s_logical_block +user_models base/vpr_types.h /^ t_model * user_models; \/* blif models defined by the user *\/$/;" m struct:s_vpr_setup +v_ds power/power.h /^ float v_ds;$/;" m struct:s_power_nmos_leakage_pair +v_in power/power.h /^ float v_in;$/;" m struct:s_power_mux_volt_pair +v_out_max power/power.h /^ float v_out_max;$/;" m struct:s_power_mux_volt_pair +v_out_min power/power.h /^ float v_out_min;$/;" m struct:s_power_mux_volt_pair +val ../../libarchfpga/fpga_spice_include/spice_types.h /^ int val; \/* binary value to be writtent: either 0 or 1 *\/$/;" m struct:s_conf_bit +valid ../../libarchfpga/include/cad_types.h /^ boolean valid;$/;" m struct:s_cluster_placement_primitive +valid base/vpr_types.h /^ boolean valid; \/* Whether or not this molecule is still valid *\/$/;" m struct:s_pack_molecule +valid_primitives base/vpr_types.h /^ t_cluster_placement_primitive **valid_primitives; \/* [0..num_pb_types-1] ptrs to linked list of valid primitives, for convenience, each linked list head is empty *\/$/;" m struct:s_cluster_placement_stats +value ../../libarchfpga/include/physical_types.h /^ char ** value; \/* [0..num_value_prop_pairs - 1] *\/$/;" m struct:s_pin_to_pin_annotation +value mrfpga/buffer_insertion.c /^typedef struct s_buffer_plan_node { t_buffer_plan value; struct s_buffer_plan_node* next;} t_buffer_plan_node;$/;" m struct:s_buffer_plan_node file: +variation_on ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean variation_on;$/;" m struct:s_spice_mc_variation_params +verify_binary_search base/vpr_types.h /^ boolean verify_binary_search;$/;" m struct:s_router_opts +verilog_convert_port_type_to_string syn_verilog/verilog_utils.c /^char* verilog_convert_port_type_to_string(enum e_spice_model_port_type port_type) {$/;" f +verilog_default_signal_init_value syn_verilog/verilog_global.c /^int verilog_default_signal_init_value = 0;$/;" v +verilog_determine_src_chan_coordinate_switch_box syn_verilog/verilog_routing.c /^void verilog_determine_src_chan_coordinate_switch_box(t_rr_node* src_rr_node,$/;" f +verilog_find_interc_fan_in_des_pb_graph_pin syn_verilog/verilog_pbtypes.c /^void verilog_find_interc_fan_in_des_pb_graph_pin(t_pb_graph_pin* des_pb_graph_pin,$/;" f +verilog_find_path_id_between_pb_rr_nodes syn_verilog/verilog_pbtypes.c /^int verilog_find_path_id_between_pb_rr_nodes(t_rr_node* local_rr_graph,$/;" f +verilog_find_pb_graph_pin_in_edges_interc_type syn_verilog/verilog_pbtypes.c /^enum e_interconnect verilog_find_pb_graph_pin_in_edges_interc_type(t_pb_graph_pin pb_graph_pin) {$/;" f +verilog_get_grid_block_subckt_name syn_verilog/verilog_pbtypes.c /^char* verilog_get_grid_block_subckt_name(int x, int y, int z,$/;" f +verilog_get_grid_phy_block_subckt_name syn_verilog/verilog_pbtypes.c /^char* verilog_get_grid_phy_block_subckt_name(int x, int y, int z,$/;" f +verilog_get_grid_side_pin_rr_nodes syn_verilog/verilog_routing.c /^t_rr_node** verilog_get_grid_side_pin_rr_nodes(int* num_pin_rr_nodes,$/;" f +verilog_mux_basis_posfix syn_verilog/verilog_global.c /^char* verilog_mux_basis_posfix = "_basis";$/;" v +verilog_mux_special_basis_posfix syn_verilog/verilog_global.c /^char* verilog_mux_special_basis_posfix = "_special_basis";$/;" v +verilog_netlist ../../libarchfpga/fpga_spice_include/spice_types.h /^ char* verilog_netlist; \/* Verilog netlist provided by user *\/$/;" m struct:s_spice_model +verilog_reserved ../../libarchfpga/fpga_spice_include/spice_types.h /^ boolean verilog_reserved;$/;" m struct:s_reserved_syntax_char +verilog_sim_timescale syn_verilog/verilog_top_netlist.c /^static float verilog_sim_timescale = 1e-9; \/\/ Verilog Simulation time scale (minimum time unit) : 1ns$/;" v file: +verilog_sram_inf_orgz ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_sram_inf_orgz* verilog_sram_inf_orgz;$/;" m struct:s_sram_inf +verilog_top_postfix syn_verilog/verilog_global.c /^char* verilog_top_postfix = "_top.v";$/;" v +verilog_writer base/verilog_writer.c /^void verilog_writer(void)$/;" f +view_mux_size_distribution route/rr_graph.c /^view_mux_size_distribution(t_ivec *** L_rr_node_indices,$/;" f file: +visited power/power.h /^ boolean visited; \/* When traversing netlist, need to track whether the node has been processed *\/$/;" m struct:s_rr_node_power +vpack_net base/globals.c /^struct s_net *vpack_net = NULL;$/;" v typeref:struct:s_net +vpack_net_num base/vpr_types.h /^ int vpack_net_num;$/;" m struct:s_rr_node +vpack_net_num_changed base/vpr_types.h /^ boolean vpack_net_num_changed;$/;" m struct:s_rr_node +vpack_to_clb_net_mapping base/globals.c /^int *vpack_to_clb_net_mapping = NULL; \/* [0..num_vpack_nets - 1] *\/$/;" v +vpr_alloc_and_load_output_file_names base/vpr_api.c /^void vpr_alloc_and_load_output_file_names(const char* default_name) {$/;" f +vpr_check_arch base/vpr_api.c /^void vpr_check_arch(INP t_arch Arch, INP boolean TimingEnabled) {$/;" f +vpr_check_options base/vpr_api.c /^void vpr_check_options(INP t_options Options, INP boolean TimingEnabled) {$/;" f +vpr_check_setup base/vpr_api.c /^void vpr_check_setup(INP enum e_operation Operation,$/;" f +vpr_crit_path_delay ../../libarchfpga/fpga_spice_include/spice_types.h /^ float vpr_crit_path_delay; \/* Reference operation clock frequency *\/$/;" m struct:s_spice_stimulate_params +vpr_dump_syn_verilog syn_verilog/syn_verilog_api.c /^void vpr_dump_syn_verilog(t_vpr_setup vpr_setup,$/;" f +vpr_fpga_spice_tool_suites fpga_spice/fpga_spice_api.c /^void vpr_fpga_spice_tool_suites(t_vpr_setup vpr_setup,$/;" f +vpr_free_all base/vpr_api.c /^void vpr_free_all(INOUTP t_arch Arch, INOUTP t_options options,$/;" f +vpr_free_vpr_data_structures base/vpr_api.c /^void vpr_free_vpr_data_structures(INOUTP t_arch Arch, INOUTP t_options options,$/;" f +vpr_get_output_file_name base/vpr_api.c /^char *vpr_get_output_file_name(enum e_output_files ename) {$/;" f +vpr_init base/vpr_api.c /^void vpr_init(INP int argc, INP char **argv, OUTP t_options *options,$/;" f +vpr_init_pre_place_and_route base/vpr_api.c /^void vpr_init_pre_place_and_route(INP t_vpr_setup vpr_setup, INP t_arch Arch) {$/;" f +vpr_pack base/vpr_api.c /^void vpr_pack(INP t_vpr_setup vpr_setup, INP t_arch arch) {$/;" f +vpr_place_and_route base/vpr_api.c /^void vpr_place_and_route(INP t_vpr_setup vpr_setup, INP t_arch arch) {$/;" f +vpr_power_estimation base/vpr_api.c /^void vpr_power_estimation(t_vpr_setup vpr_setup, t_arch Arch) {$/;" f +vpr_print_title base/vpr_api.c /^void vpr_print_title(void) {$/;" f +vpr_print_usage base/vpr_api.c /^void vpr_print_usage(void) {$/;" f +vpr_printf ../../libarchfpga/util.c /^messagelogger vpr_printf = PrintHandlerMessage;$/;" v +vpr_read_and_process_blif base/vpr_api.c /^void vpr_read_and_process_blif(INP char *blif_file,$/;" f +vpr_read_options base/vpr_api.c /^void vpr_read_options(INP int argc, INP char **argv, OUTP t_options * options) {$/;" f +vpr_resync_post_route_netlist_to_TI_CLAY_v1_architecture base/vpr_api.c /^t_trace* vpr_resync_post_route_netlist_to_TI_CLAY_v1_architecture($/;" f +vpr_set_output_file_name base/vpr_api.c /^void vpr_set_output_file_name(enum e_output_files ename, const char *name,$/;" f +vpr_setup_vpr base/vpr_api.c /^void vpr_setup_vpr(INP t_options *Options, INP boolean TimingEnabled,$/;" f +vpr_show_setup base/vpr_api.c /^void vpr_show_setup(INP t_options options, INP t_vpr_setup vpr_setup) {$/;" f +vpr_spice_print_netlists spice/spice_api.c /^void vpr_spice_print_netlists(t_vpr_setup vpr_setup,$/;" f +vpr_to_phy_track route/rr_graph2.c /^static int vpr_to_phy_track(INP int itrack, INP int chan_num, INP int seg_num,$/;" f file: +watch_edges route/rr_graph.c /^void watch_edges(int inode, t_linked_edge * edge_list_head) {$/;" f +which_button base/graphics.c /^static int which_button (Window win) $/;" f file: +width ../../libarchfpga/include/physical_types.h /^ float width;$/;" m struct:s_chan +width base/graphics.c /^ int width; $/;" m struct:__anon4 file: +win base/graphics.c /^ Window win; $/;" m struct:__anon4 file: +win32_colors base/graphics.c /^static const COLORREF win32_colors[NUM_COLOR] = { RGB(255, 255, 255),$/;" v file: +win32_drain_message_queue base/graphics.c /^void win32_drain_message_queue () {$/;" f +win32_line_styles base/graphics.c /^static const int win32_line_styles[2] = { PS_SOLID, PS_DASH };$/;" v file: +windowAdjustFlag base/graphics.c /^static int windowAdjustFlag = 0, adjustButton = -1;$/;" v file: +wire ../../libarchfpga/include/physical_types.h /^ } wire;$/;" m struct:s_port_power typeref:union:s_port_power::__anon22 +wire_buffer_inf ../../libarchfpga/include/arch_types_mrfpga.h /^ t_buffer_inf wire_buffer_inf;$/;" m struct:s_arch_mrfpga +wire_buffer_inf mrfpga/mrfpga_globals.c /^t_buffer_inf wire_buffer_inf;$/;" v +wire_param ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_model_wire_param* wire_param;$/;" m struct:s_spice_model +wire_switch ../../libarchfpga/include/physical_types.h /^ short wire_switch;$/;" m struct:s_segment_inf +wire_switch base/vpr_types.h /^ short wire_switch;$/;" m struct:s_seg_details +wire_to_ipin_switch base/vpr_types.h /^ short wire_to_ipin_switch;$/;" m struct:s_det_routing_arch +wire_type ../../libarchfpga/include/physical_types.h /^ e_power_wire_type wire_type;$/;" m struct:s_port_power +wire_variation ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_spice_mc_variation_params wire_variation;$/;" m struct:s_spice_mc_params +wirelength base/place_and_route.h /^ int wirelength; \/* corresponding wirelength of successful routing at wneed *\/$/;" m struct:s_fmap_cell +wires_spice_file_name spice/spice_globals.c /^char* wires_spice_file_name = "wires.sp";$/;" v +wires_verilog_file_name syn_verilog/verilog_global.c /^char* wires_verilog_file_name = "wires.v";$/;" v +wl ../../libarchfpga/fpga_spice_include/spice_types.h /^ t_conf_bit* wl;$/;" m struct:s_conf_bit_info +wneed base/place_and_route.h /^ int wneed; \/* need wneed to route *\/$/;" m struct:s_fmap_cell +wprog_reset_nmos ../../libarchfpga/fpga_spice_include/spice_types.h /^ float wprog_reset_nmos;$/;" m struct:s_spice_model_design_tech_info +wprog_reset_pmos ../../libarchfpga/fpga_spice_include/spice_types.h /^ float wprog_reset_pmos;$/;" m struct:s_spice_model_design_tech_info +wprog_set_nmos ../../libarchfpga/fpga_spice_include/spice_types.h /^ float wprog_set_nmos;$/;" m struct:s_spice_model_design_tech_info +wprog_set_pmos ../../libarchfpga/fpga_spice_include/spice_types.h /^ float wprog_set_pmos;$/;" m struct:s_spice_model_design_tech_info +write ../../libarchfpga/ezxml.c 60;" d file: +x base/easygl_constants.h /^ float x; $/;" m struct:__anon1 +x base/vpr_types.h /^ int x;$/;" m struct:s_block +x base/vpr_types.h /^ int x;$/;" m struct:s_cb +x base/vpr_types.h /^ int x;$/;" m struct:s_sb +x place/place.c /^ int x;$/;" m struct:s_legal_pos file: +x_offset ../../libarchfpga/include/physical_types.h /^ int x_offset;$/;" m struct:s_direct_inf +x_offset place/place_macro.h /^ int x_offset;$/;" m struct:s_pl_macro_member +x_rr_node_left base/draw.c /^static float *x_rr_node_left = NULL;$/;" v file: +x_rr_node_right base/draw.c /^static float *x_rr_node_right = NULL;$/;" v file: +xcoord base/graphics.c /^static int xcoord (float worldx) $/;" f file: +xdiv base/graphics.c /^static float xdiv, ydiv;$/;" v file: +xhigh base/vpr_types.h /^ short xhigh;$/;" m struct:s_rr_node +xleft base/graphics.c /^ int xleft; $/;" m struct:__anon4 file: +xleft base/graphics.c /^static float xleft, xright, ytop, ybot; \/* world coordinates *\/$/;" v file: +xleft base/graphics.h /^ float xleft, xright, ytop, ybot;$/;" m struct:__anon6 +xlow base/vpr_types.h /^ short xlow;$/;" m struct:s_rr_node +xmax base/vpr_types.h /^ int xmax;$/;" m struct:s_bb +xmin base/vpr_types.h /^ int xmin;$/;" m struct:s_bb +xml ../../libarchfpga/include/ezxml.h /^ struct ezxml xml; \/* is a super-struct built on top of ezxml struct *\/$/;" m struct:ezxml_root typeref:struct:ezxml_root::ezxml +xmult base/graphics.c /^static float xmult, ymult; \/* Transformation factors *\/$/;" v file: +xmult base/graphics.h /^ float xmult, ymult;$/;" m struct:__anon6 +xnew place/place.c /^ int xnew;$/;" m struct:s_pl_moved_block file: +xold place/place.c /^ int xold;$/;" m struct:s_pl_moved_block file: +xpeak ../../libarchfpga/include/physical_types.h /^ float xpeak;$/;" m struct:s_chan +xright base/graphics.c /^static float xleft, xright, ytop, ybot; \/* world coordinates *\/$/;" v file: +xright base/graphics.h /^ float xleft, xright, ytop, ybot;$/;" m struct:__anon6 +y base/easygl_constants.h /^ float y;$/;" m struct:__anon1 +y base/vpr_types.h /^ int y;$/;" m struct:s_block +y base/vpr_types.h /^ int y;$/;" m struct:s_cb +y base/vpr_types.h /^ int y;$/;" m struct:s_sb +y place/place.c /^ int y;$/;" m struct:s_legal_pos file: +y_offset ../../libarchfpga/include/physical_types.h /^ int y_offset;$/;" m struct:s_direct_inf +y_offset place/place_macro.h /^ int y_offset; $/;" m struct:s_pl_macro_member +y_rr_node_bottom base/draw.c /^static float *y_rr_node_bottom = NULL;$/;" v file: +y_rr_node_top base/draw.c /^static float *y_rr_node_top = NULL;$/;" v file: +ybot base/graphics.c /^static float xleft, xright, ytop, ybot; \/* world coordinates *\/$/;" v file: +ybot base/graphics.h /^ float xleft, xright, ytop, ybot;$/;" m struct:__anon6 +ycoord base/graphics.c /^static int ycoord (float worldy) $/;" f file: +ydiv base/graphics.c /^static float xdiv, ydiv;$/;" v file: +yhigh base/vpr_types.h /^ short yhigh;$/;" m struct:s_rr_node +ylow base/vpr_types.h /^ short ylow;$/;" m struct:s_rr_node +ymax base/vpr_types.h /^ int ymax;$/;" m struct:s_bb +ymin base/vpr_types.h /^ int ymin;$/;" m struct:s_bb +ymult base/graphics.c /^static float xmult, ymult; \/* Transformation factors *\/$/;" v file: +ymult base/graphics.h /^ float xmult, ymult;$/;" m struct:__anon6 +ynew place/place.c /^ int ynew;$/;" m struct:s_pl_moved_block file: +yold place/place.c /^ int yold;$/;" m struct:s_pl_moved_block file: +ytop base/graphics.c /^ int ytop;$/;" m struct:__anon4 file: +ytop base/graphics.c /^static float xleft, xright, ytop, ybot; \/* world coordinates *\/$/;" v file: +ytop base/graphics.h /^ float xleft, xright, ytop, ybot;$/;" m struct:__anon6 +z base/vpr_types.h /^ int z; \/* For IPIN, source, and sink nodes, helps identify which location this rr_node belongs to *\/$/;" m struct:s_rr_node +z base/vpr_types.h /^ int z;$/;" m struct:s_block +z place/place.c /^ int z;$/;" m struct:s_legal_pos file: +z_offset ../../libarchfpga/include/physical_types.h /^ int z_offset;$/;" m struct:s_direct_inf +z_offset place/place_macro.h /^ int z_offset;$/;" m struct:s_pl_macro_member +zero_one_spice_model_grid_index_low_high fpga_spice/fpga_spice_utils.c /^void zero_one_spice_model_grid_index_low_high(t_spice_model* cur_spice_model) {$/;" f +zero_one_spice_model_routing_index_low_high fpga_spice/fpga_spice_utils.c /^void zero_one_spice_model_routing_index_low_high(t_spice_model* cur_spice_model) {$/;" f +zero_spice_model_grid_index_low_high fpga_spice/fpga_spice_utils.c /^void zero_spice_model_grid_index_low_high(int num_spice_models, $/;" f +zero_spice_models_cnt fpga_spice/fpga_spice_utils.c /^void zero_spice_models_cnt(int num_spice_models, t_spice_model* spice_model) {$/;" f +zero_spice_models_routing_index_low_high fpga_spice/fpga_spice_utils.c /^void zero_spice_models_routing_index_low_high(int num_spice_models, $/;" f +znew place/place.c /^ int znew;$/;" m struct:s_pl_moved_block file: +zold place/place.c /^ int zold;$/;" m struct:s_pl_moved_block file: +zoom_fit base/graphics.c /^zoom_fit (void (*drawscreen) (void)) $/;" f file: +zoom_in base/graphics.c /^zoom_in (void (*drawscreen) (void)) $/;" f file: +zoom_out base/graphics.c /^zoom_out (void (*drawscreen) (void)) $/;" f file: diff --git a/vpr7_rram/vpr/SRC/timing/net_delay.c b/vpr7_rram/vpr/SRC/timing/net_delay.c new file mode 100755 index 000000000..441dc8cca --- /dev/null +++ b/vpr7_rram/vpr/SRC/timing/net_delay.c @@ -0,0 +1,562 @@ +#include +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +/* Xifan TANG: move the data structures to another header file so that to share them*/ +#include "net_delay_types.h" +#include "net_delay_local_void.h" +/* END */ +#include "net_delay.h" + +/* mrFPGA: Xifan TANG */ +#include "mrfpga_globals.h" +#include "cal_capacitance.h" +/* end */ + +/*************************** Subroutine definitions **************************/ + +float ** +alloc_net_delay(t_chunk *chunk_list_ptr, struct s_net *nets, + int n_nets){ + + /* Allocates space for the net_delay data structure * + * [0..num_nets-1][1..num_pins-1]. I chunk the data to save space on large * + * problems. */ + + float **net_delay; /* [0..num_nets-1][1..num_pins-1] */ + float *tmp_ptr; + int inet; + + net_delay = (float **) my_malloc(n_nets * sizeof(float *)); + + for (inet = 0; inet < n_nets; inet++) { + tmp_ptr = (float *) my_chunk_malloc( + ((nets[inet].num_sinks + 1) - 1) * sizeof(float), + chunk_list_ptr); + + net_delay[inet] = tmp_ptr - 1; /* [1..num_pins-1] */ + } + + return (net_delay); +} + +void free_net_delay(float **net_delay, + t_chunk *chunk_list_ptr){ + + /* Frees the net_delay structure. Assumes it was chunk allocated. */ + + free(net_delay); + free_chunk_memory(chunk_list_ptr); +} + +void load_net_delay_from_routing(float **net_delay, struct s_net *nets, + int n_nets) { + + /* This routine loads net_delay[0..num_nets-1][1..num_pins-1]. Each entry * + * is the Elmore delay from the net source to the appropriate sink. Both * + * the rr_graph and the routing traceback must be completely constructed * + * before this routine is called, and the net_delay array must have been * + * allocated. */ + + t_rc_node *rc_node_free_list, *rc_root; + t_linked_rc_edge *rc_edge_free_list; + int inet; + t_linked_rc_ptr *rr_node_to_rc_node; /* [0..num_rr_nodes-1] */ + + rr_node_to_rc_node = (t_linked_rc_ptr *) my_calloc(num_rr_nodes, + sizeof(t_linked_rc_ptr)); + + rc_node_free_list = NULL; + rc_edge_free_list = NULL; + + for (inet = 0; inet < n_nets; inet++) { + if (nets[inet].is_global) { + load_one_constant_net_delay(net_delay, inet, nets, 0.); + } else { + rc_root = alloc_and_load_rc_tree(inet, &rc_node_free_list, + &rc_edge_free_list, rr_node_to_rc_node); + load_rc_tree_C(rc_root); + load_rc_tree_T(rc_root, 0.); + load_one_net_delay(net_delay, inet, nets, rr_node_to_rc_node); + free_rc_tree(rc_root, &rc_node_free_list, &rc_edge_free_list); + reset_rr_node_to_rc_node(rr_node_to_rc_node, inet); + } + } + + free_rc_node_free_list(rc_node_free_list); + free_rc_edge_free_list(rc_edge_free_list); + free(rr_node_to_rc_node); +} + +void load_constant_net_delay(float **net_delay, float delay_value, + struct s_net *nets, int n_nets) { + + /* Loads the net_delay array with delay_value for every source - sink * + * connection that is not on a global resource, and with 0. for every source * + * - sink connection on a global net. (This can be used to allow timing * + * analysis before routing is done with a constant net delay model). */ + + int inet; + + for (inet = 0; inet < n_nets; inet++) { + if (nets[inet].is_global) { + load_one_constant_net_delay(net_delay, inet, nets, 0.); + } else { + load_one_constant_net_delay(net_delay, inet, nets, delay_value); + } + } +} + +/* mrFPGA: Xifan TANG, let's share these functions*/ +//static +/* END */ +t_rc_node * +alloc_and_load_rc_tree(int inet, t_rc_node ** rc_node_free_list_ptr, + t_linked_rc_edge ** rc_edge_free_list_ptr, + t_linked_rc_ptr * rr_node_to_rc_node) { + + /* Builds a tree describing the routing of net inet. Allocates all the data * + * and inserts all the connections in the tree. */ + + t_rc_node *curr_rc, *prev_rc, *root_rc; + struct s_trace *tptr; + int inode, prev_node; + short iswitch; + t_linked_rc_ptr *linked_rc_ptr; + + root_rc = alloc_rc_node(rc_node_free_list_ptr); + tptr = trace_head[inet]; + + if (tptr == NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "in alloc_and_load_rc_tree: Traceback for net %d does not exist.\n", inet); + exit(1); + } + + inode = tptr->index; + iswitch = tptr->iswitch; + root_rc->inode = inode; + root_rc->u.child_list = NULL; + rr_node_to_rc_node[inode].rc_node = root_rc; + + prev_rc = root_rc; + tptr = tptr->next; + + while (tptr != NULL) { + inode = tptr->index; + + /* Is this node a "stitch-in" point to part of the existing routing or a * + * new piece of routing along the current routing "arm?" */ + + if (rr_node_to_rc_node[inode].rc_node == NULL) { /* Part of current "arm" */ + curr_rc = alloc_rc_node(rc_node_free_list_ptr); + add_to_rc_tree(prev_rc, curr_rc, iswitch, inode, + rc_edge_free_list_ptr); + rr_node_to_rc_node[inode].rc_node = curr_rc; + prev_rc = curr_rc; + } + + else if (rr_node[inode].type != SINK) { /* Connection to old stuff. */ + +#ifdef DEBUG + prev_node = prev_rc->inode; + if (rr_node[prev_node].type != SINK) { + vpr_printf(TIO_MESSAGE_ERROR, "in alloc_and_load_rc_tree: Routing of net %d is not a tree.\n", inet); + exit(1); + } +#endif + + prev_rc = rr_node_to_rc_node[inode].rc_node; + } + + else { /* SINK that this net has connected to more than once. */ + + /* I can connect to a SINK node more than once in some weird architectures. * + * That means the routing isn't really a tree -- there is reconvergent * + * fanout from two or more IPINs into one SINK. I convert this structure * + * into a true RC tree on the fly by creating a new rc_node each time I hit * + * the same sink. This means I need to keep a linked list of the rc_nodes * + * associated with the rr_node (inode) associated with that SINK. */ + + curr_rc = alloc_rc_node(rc_node_free_list_ptr); + add_to_rc_tree(prev_rc, curr_rc, iswitch, inode, + rc_edge_free_list_ptr); + + linked_rc_ptr = (t_linked_rc_ptr *) my_malloc( + sizeof(t_linked_rc_ptr)); + linked_rc_ptr->next = rr_node_to_rc_node[inode].next; + rr_node_to_rc_node[inode].next = linked_rc_ptr; + linked_rc_ptr->rc_node = curr_rc; + + prev_rc = curr_rc; + } + iswitch = tptr->iswitch; + tptr = tptr->next; + } + + return (root_rc); +} + +/* mrFPGA: Xifan TANG, let's share these functions*/ +//static +/* END */ +void add_to_rc_tree(t_rc_node * parent_rc, t_rc_node * child_rc, + short iswitch, int inode, t_linked_rc_edge ** rc_edge_free_list_ptr) { + + /* Adds child_rc to the child list of parent_rc, and sets the switch between * + * them to iswitch. This routine also intitializes the child_rc properly * + * and sets its node value to inode. */ + + t_linked_rc_edge *linked_rc_edge; + + linked_rc_edge = alloc_linked_rc_edge(rc_edge_free_list_ptr); + + linked_rc_edge->next = parent_rc->u.child_list; + parent_rc->u.child_list = linked_rc_edge; + + linked_rc_edge->child = child_rc; + linked_rc_edge->iswitch = iswitch; + + child_rc->u.child_list = NULL; + child_rc->inode = inode; +} + +/* mrFPGA: Xifan TANG, let's share these functions*/ +//static +/* END */ +t_rc_node * +alloc_rc_node(t_rc_node ** rc_node_free_list_ptr) { + + /* Allocates a new rc_node, from the free list if possible, from the free * + * store otherwise. */ + + t_rc_node *rc_node; + + rc_node = *rc_node_free_list_ptr; + + if (rc_node != NULL) { + *rc_node_free_list_ptr = rc_node->u.next; + } else { + rc_node = (t_rc_node *) my_malloc(sizeof(t_rc_node)); + } + + return (rc_node); +} + + +/* mrFPGA: Xifan TANG, let's share these functions*/ +//static +/* END */ +void free_rc_node(t_rc_node * rc_node, + t_rc_node ** rc_node_free_list_ptr) { + + /* Adds rc_node to the proper free list. */ + + rc_node->u.next = *rc_node_free_list_ptr; + *rc_node_free_list_ptr = rc_node; +} + + +/* mrFPGA: Xifan TANG, let's share these functions*/ +//static +/* END */ +t_linked_rc_edge * +alloc_linked_rc_edge(t_linked_rc_edge ** rc_edge_free_list_ptr) { + + /* Allocates a new linked_rc_edge, from the free list if possible, from the * + * free store otherwise. */ + + t_linked_rc_edge *linked_rc_edge; + + linked_rc_edge = *rc_edge_free_list_ptr; + + if (linked_rc_edge != NULL) { + *rc_edge_free_list_ptr = linked_rc_edge->next; + } else { + linked_rc_edge = (t_linked_rc_edge *) my_malloc( + sizeof(t_linked_rc_edge)); + } + + return (linked_rc_edge); +} + +/* mrFPGA: Xifan TANG, let's share these functions*/ +//static +/* END */ +void free_linked_rc_edge(t_linked_rc_edge * rc_edge, + t_linked_rc_edge ** rc_edge_free_list_ptr) { + + /* Adds the rc_edge to the rc_edge free list. */ + + rc_edge->next = *rc_edge_free_list_ptr; + *rc_edge_free_list_ptr = rc_edge; +} + +/* mrFPGA: Xifan TANG, let's share these functions*/ +//static +/* END */ +float load_rc_tree_C(t_rc_node * rc_node) { + + /* Does a post-order traversal of the rc tree to load each node's * + * C_downstream with the proper sum of all the downstream capacitances. * + * This routine calls itself recursively to perform the traversal. */ + + t_linked_rc_edge *linked_rc_edge; + t_rc_node *child_node; + int inode; + short iswitch; + float C, C_downstream; + + linked_rc_edge = rc_node->u.child_list; + inode = rc_node->inode; + C = rr_node[inode].C; + + while (linked_rc_edge != NULL) { /* For all children */ + iswitch = linked_rc_edge->iswitch; + child_node = linked_rc_edge->child; + C_downstream = load_rc_tree_C(child_node); + + /* mrFPGA : Xifan TANG */ + if (is_isolation) { + C_downstream += switch_inf[iswitch].Cout; + C += switch_inf[iswitch].Cin; + } + /* end */ + + if (switch_inf[iswitch].buffered == FALSE) + C += C_downstream; + + linked_rc_edge = linked_rc_edge->next; + } + + /* mrFPGA : Xifan TANG */ + if (is_mrFPGA && rr_node[inode].buffered) { + rc_node->Tdel = (wire_buffer_inf.R + 0.5 * rr_node[inode].R) * C; + C = wire_buffer_inf.C; + if ((CHANX == rr_node[inode].type && rr_node[child_node->inode].yhigh <= rr_node[inode].ylow) + ||(rr_node[inode].type == CHANY && rr_node[child_node->inode].xhigh <= rr_node[inode].xlow)) { + rr_node[inode].buffered = -1; + } + } else { + rc_node->Tdel = 0.; + } + /* end */ + + rc_node->C_downstream = C; + return (C); +} + +/* mrFPGA: Xifan TANG, let's share these functions*/ +//static +/* END */ +void load_rc_tree_T(t_rc_node * rc_node, float T_arrival) { + + /* This routine does a pre-order depth-first traversal of the rc tree to * + * compute the Tdel to each node in the rc tree. The T_arrival is the time * + * at which the signal hits the input to this node. This routine calls * + * itself recursively to perform the traversal. */ + + float Tdel, Rmetal, Tchild; + t_linked_rc_edge *linked_rc_edge; + t_rc_node *child_node; + short iswitch; + int inode; + + Tdel = T_arrival; + inode = rc_node->inode; + Rmetal = rr_node[inode].R; + + /* NB: rr_node[inode].C gives the capacitance of this node, while * + * rc_node->C_downstream gives the unbuffered downstream capacitance rooted * + * at this node, including the C of the node itself. I want to multiply * + * the C of this node by 0.5 Rmetal, since it's a distributed RC line. * + * Hence 0.5 Rmetal * Cnode is a pessimistic estimate of delay (i.e. end to * + * end). For the downstream capacitance rooted at this node (not including * + * the capacitance of the node itself), I assume it is, on average, * + * connected halfway along the line, so I also multiply by 0.5 Rmetal. To * + * be totally pessimistic I would multiply the downstream part of the * + * capacitance by Rmetal. Play with this equation if you like. */ + + /* Rmetal is distributed so x0.5 */ + /* mrFPGA : Xifan TANG */ + if (is_mrFPGA && rr_node[inode].buffered) { + Tdel += wire_buffer_inf.Tdel; + rc_node->Tdel += Tdel; + Tdel = rc_node->Tdel; + /* end */ + } else { + /* Original VPR */ + Tdel += 0.5 * rc_node->C_downstream * Rmetal; + rc_node->Tdel = Tdel; + /* end */ + } + + /* Now expand the children of this node to load their Tdel values. */ + + linked_rc_edge = rc_node->u.child_list; + + while (linked_rc_edge != NULL) { /* For all children */ + iswitch = linked_rc_edge->iswitch; + child_node = linked_rc_edge->child; + + Tchild = Tdel + switch_inf[iswitch].R * child_node->C_downstream; + Tchild += switch_inf[iswitch].Tdel; /* Intrinsic switch delay. */ + load_rc_tree_T(child_node, Tchild); + + linked_rc_edge = linked_rc_edge->next; + } +} + +/* mrFPGA: Xifan TANG, let's share these functions*/ +//static +/* END */ +void load_one_net_delay(float **net_delay, int inet, struct s_net* nets, + t_linked_rc_ptr * rr_node_to_rc_node) { + + /* Loads the net delay array for net inet. The rc tree for that net must * + * have already been completely built and loaded. */ + + int ipin, inode; + float Tmax; + t_rc_node *rc_node; + t_linked_rc_ptr *linked_rc_ptr, *next_ptr; + + for (ipin = 1; ipin < (nets[inet].num_sinks + 1); ipin++) { + + inode = net_rr_terminals[inet][ipin]; + + linked_rc_ptr = rr_node_to_rc_node[inode].next; + rc_node = rr_node_to_rc_node[inode].rc_node; + Tmax = rc_node->Tdel; + + /* If below only executes when one net connects several times to the * + * same SINK. In this case, I can't tell which net pin each connection * + * to this SINK corresponds to (I can just choose arbitrarily). To make * + * sure the timing behaviour converges, I pessimistically set the delay * + * for all of the connections to this SINK by this net to be the max. of * + * the delays from this net to this SINK. NB: This code only occurs * + * when a net connect more than once to the same pin class on the same * + * logic block. Only a weird architecture would allow this. */ + + if (linked_rc_ptr != NULL) { + + /* The first time I hit a multiply-used SINK, I choose the largest delay * + * from this net to this SINK and use it for every connection to this * + * SINK by this net. */ + + do { + rc_node = linked_rc_ptr->rc_node; + if (rc_node->Tdel > Tmax) { + Tmax = rc_node->Tdel; + rr_node_to_rc_node[inode].rc_node = rc_node; + } + next_ptr = linked_rc_ptr->next; + free(linked_rc_ptr); + linked_rc_ptr = next_ptr; + } while (linked_rc_ptr != NULL); /* End do while */ + + rr_node_to_rc_node[inode].next = NULL; + } + /* End of if multiply-used SINK */ + net_delay[inet][ipin] = Tmax; + } +} + +/* mrFPGA: Xifan TANG, let's share these functions*/ +//static +/* END */ +void load_one_constant_net_delay(float **net_delay, int inet, + struct s_net *nets, float delay_value) { + + /* Sets each entry of the net_delay array for net inet to delay_value. */ + + int ipin; + + for (ipin = 1; ipin < (nets[inet].num_sinks + 1); ipin++) + net_delay[inet][ipin] = delay_value; +} + +/* mrFPGA: Xifan TANG, let's share these functions*/ +//static +/* END */ +void free_rc_tree(t_rc_node * rc_root, + t_rc_node ** rc_node_free_list_ptr, + t_linked_rc_edge ** rc_edge_free_list_ptr) { + + /* Puts the rc tree pointed to by rc_root back on the free list. Depth- * + * first post-order traversal via recursion. */ + + t_rc_node *rc_node, *child_node; + t_linked_rc_edge *rc_edge, *next_edge; + + rc_node = rc_root; + rc_edge = rc_node->u.child_list; + + while (rc_edge != NULL) { /* For all children */ + child_node = rc_edge->child; + free_rc_tree(child_node, rc_node_free_list_ptr, rc_edge_free_list_ptr); + next_edge = rc_edge->next; + free_linked_rc_edge(rc_edge, rc_edge_free_list_ptr); + rc_edge = next_edge; + } + + free_rc_node(rc_node, rc_node_free_list_ptr); +} + +/* mrFPGA: Xifan TANG, let's share these functions*/ +//static +/* END */ +void reset_rr_node_to_rc_node(t_linked_rc_ptr * rr_node_to_rc_node, + int inet) { + + /* Resets the rr_node_to_rc_node mapping entries that were set during * + * construction of the RC tree for net inet. Any extra linked list entries * + * added to deal with a SINK being connected to multiple times have already * + * been freed by load_one_net_delay. */ + + struct s_trace *tptr; + int inode; + + tptr = trace_head[inet]; + + while (tptr != NULL) { + inode = tptr->index; + rr_node_to_rc_node[inode].rc_node = NULL; + tptr = tptr->next; + } +} + +/* mrFPGA: Xifan TANG, let's share these functions*/ +//static +/* END */ +void free_rc_node_free_list(t_rc_node * rc_node_free_list) { + + /* Really frees (i.e. calls free()) all the rc_nodes on the free list. */ + + t_rc_node *rc_node, *next_node; + + rc_node = rc_node_free_list; + + while (rc_node != NULL) { + next_node = rc_node->u.next; + free(rc_node); + rc_node = next_node; + } +} + +/* mrFPGA: Xifan TANG, let's share these functions*/ +//static +/* END */ +void free_rc_edge_free_list(t_linked_rc_edge * rc_edge_free_list) { + + /* Really frees (i.e. calls free()) all the rc_edges on the free list. */ + + t_linked_rc_edge *rc_edge, *next_edge; + + rc_edge = rc_edge_free_list; + + while (rc_edge != NULL) { + next_edge = rc_edge->next; + free(rc_edge); + rc_edge = next_edge; + } +} diff --git a/vpr7_rram/vpr/SRC/timing/net_delay.h b/vpr7_rram/vpr/SRC/timing/net_delay.h new file mode 100755 index 000000000..1a879ff9b --- /dev/null +++ b/vpr7_rram/vpr/SRC/timing/net_delay.h @@ -0,0 +1,19 @@ +/*float **alloc_net_delay(struct s_linked_vptr **chunk_list_head_ptr, + struct s_net *nets, int n_nets);*/ + +float **alloc_net_delay(t_chunk *chunk_list_ptr, + struct s_net *nets, int n_nets); + +/*void free_net_delay(float **net_delay, + struct s_linked_vptr **chunk_list_head_ptr);*/ + +void free_net_delay(float **net_delay, + t_chunk *chunk_list_ptr); + +void load_net_delay_from_routing(float **net_delay, struct s_net *nets, + int n_nets); + +void load_constant_net_delay(float **net_delay, float delay_value, + struct s_net *nets, int n_nets); + + diff --git a/vpr7_rram/vpr/SRC/timing/net_delay_local_void.h b/vpr7_rram/vpr/SRC/timing/net_delay_local_void.h new file mode 100644 index 000000000..22de9e89f --- /dev/null +++ b/vpr7_rram/vpr/SRC/timing/net_delay_local_void.h @@ -0,0 +1,57 @@ + +/*********************** Subroutines local to this module ********************/ + +//static +t_rc_node *alloc_and_load_rc_tree(int inet, + t_rc_node ** rc_node_free_list_ptr, + t_linked_rc_edge ** rc_edge_free_list_ptr, + t_linked_rc_ptr * rr_node_to_rc_node); + +//static +void add_to_rc_tree(t_rc_node * parent_rc, t_rc_node * child_rc, + short iswitch, int inode, t_linked_rc_edge ** rc_edge_free_list_ptr); + +//static +t_rc_node *alloc_rc_node(t_rc_node ** rc_node_free_list_ptr); + +//static +void free_rc_node(t_rc_node * rc_node, + t_rc_node ** rc_node_free_list_ptr); + +//static +t_linked_rc_edge *alloc_linked_rc_edge( + t_linked_rc_edge ** rc_edge_free_list_ptr); + +//static +void free_linked_rc_edge(t_linked_rc_edge * rc_edge, + t_linked_rc_edge ** rc_edge_free_list_ptr); + +//static +float load_rc_tree_C(t_rc_node * rc_node); + +//static +void load_rc_tree_T(t_rc_node * rc_node, float T_arrival); + +//static +void load_one_net_delay(float **net_delay, int inet, struct s_net *nets, + t_linked_rc_ptr * rr_node_to_rc_node); + +//static +void load_one_constant_net_delay(float **net_delay, int inet, + struct s_net *nets, float delay_value); + +//static +void free_rc_tree(t_rc_node * rc_root, + t_rc_node ** rc_node_free_list_ptr, + t_linked_rc_edge ** rc_edge_free_list_ptr); + +//static +void reset_rr_node_to_rc_node(t_linked_rc_ptr * rr_node_to_rc_node, + int inet); + +//static +void free_rc_node_free_list(t_rc_node * rc_node_free_list); + +//static +void free_rc_edge_free_list(t_linked_rc_edge * rc_edge_free_list); + diff --git a/vpr7_rram/vpr/SRC/timing/net_delay_types.h b/vpr7_rram/vpr/SRC/timing/net_delay_types.h new file mode 100644 index 000000000..cc7d7dcde --- /dev/null +++ b/vpr7_rram/vpr/SRC/timing/net_delay_types.h @@ -0,0 +1,51 @@ +/***************** Types and defines local to this module ********************/ + +struct s_linked_rc_edge { + struct s_rc_node *child; + short iswitch; + struct s_linked_rc_edge *next; +}; + +typedef struct s_linked_rc_edge t_linked_rc_edge; + +/* Linked list listing the children of an rc_node. * + * child: Pointer to an rc_node (child of the current node). * + * iswitch: Index of the switch type used to connect to the child node. * + * next: Pointer to the next linked_rc_edge in the linked list (allows * + * you to get the next child of the current rc_node). */ + +struct s_rc_node { + union { + t_linked_rc_edge *child_list; + struct s_rc_node *next; + } u; + int inode; + float C_downstream; + float Tdel; +}; + +typedef struct s_rc_node t_rc_node; + +/* Structure describing one node in an RC tree (used to get net delays). * + * u.child_list: Pointer to a linked list of linked_rc_edge. Each one of * + * the linked list entries gives a child of this node. * + * u.next: Used only when this node is on the free list. Gives the next * + * node on the free list. * + * inode: index (ID) of the rr_node that corresponds to this rc_node. * + * C_downstream: Total downstream capacitance from this rc_node. That is, * + * the total C of the subtree rooted at the current node, * + * including the C of the current node. * + * Tdel: Time delay for the signal to get from the net source to this node. * + * Includes the time to go through this node. */ + +struct s_linked_rc_ptr { + struct s_rc_node *rc_node; + struct s_linked_rc_ptr *next; +}; + +typedef struct s_linked_rc_ptr t_linked_rc_ptr; + +/* Linked list of pointers to rc_nodes. * + * rc_node: Pointer to an rc_node. * + * next: Next list element. */ + diff --git a/vpr7_rram/vpr/SRC/timing/path_delay.c b/vpr7_rram/vpr/SRC/timing/path_delay.c new file mode 100755 index 000000000..51b228555 --- /dev/null +++ b/vpr7_rram/vpr/SRC/timing/path_delay.c @@ -0,0 +1,3823 @@ +#include +#include +#include +#include +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "path_delay.h" +#include "path_delay2.h" +#include "net_delay.h" +#include "vpr_utils.h" +#include +#include "read_xml_arch_file.h" +#include "ReadOptions.h" +#include "read_sdc.h" +#include "stats.h" + +/**************************** Top-level summary ****************************** + +Timing analysis by Vaughn Betz, Jason Luu, and Michael Wainberg. + +Timing analysis is a three-step process: +1. Interpret the constraints specified by the user in an SDC (Synopsys Design +Constraints) file or, if none is specified, use default constraints. +2. Convert the pre- or post-packed netlist (depending on the stage of the +flow) into a timing graph, where nodes represent pins and edges represent +dependencies and delays between pins (see "Timing graph structure", below). +3. Traverse the timing graph to obtain information about which connections +to optimize, as well as statistics for the user. + +Steps 1 and 2 are performed through one of two helper functions: +alloc_and_load_timing_graph and alloc_and_load_pre_packing_timing_graph. +The first step is to create the timing graph, which is stored in the array +tnode ("timing node"). This is done through alloc_and_load_tnodes (post- +packed) or alloc_and_load_tnodes_from_prepacked_netlist. Then, the timing +graph is topologically sorted ("levelized") in +alloc_and_load_timing_graph_levels, to allow for faster traversals later. + +read_sdc reads the SDC file, interprets its contents and stores them in +the data structure g_sdc. (This data structure does not need to remain +global but it is probably easier, since its information is used in both +netlists and only needs to be read in once.) + +load_clock_domain_and_clock_and_io_delay then gives each flip-flop and I/O +the index of a constrained clock from the SDC file in g_sdc->constrained_ +clocks, or -1 if an I/O is unconstrained. + +process_constraints does a pre-traversal through the timing graph and prunes +all constraints between domains that never intersect so they are not analysed. + +Step 3 is performed through do_timing_analysis. For each constraint between +a pair of clock domains we do a forward traversal from the "source" domain +to the "sink" domain to compute each tnode's arrival time, the time when the +latest signal would arrive at the node. We also do a backward traversal to +compute required time, the time when the earliest signal has to leave the +node to meet the constraint. The "slack" of each sink pin on each net is +basically the difference between the two times. + +If path counting is on, we calculate a forward and backward path weight in +do_path_counting. These represent the importance of paths fanning, +respectively, into and out of this pin, in such a way that paths with a +higher slack are discounted exponentially in importance. + +If path counting is off and we are using the pre-packed netlist, we also +calculate normalized costs for the clusterer (normalized arrival time, slack +and number of critical paths) in normalized_costs. The clusterer uses these +to calculate a criticality for each block. + +Finally, in update_slacks, we calculate the slack for each sink pin on each net +for printing, as well as a derived metric, timing criticality, which the +optimizers actually use. If path counting is on, we calculate a path criticality +from the forward and backward weights on each tnode. */ + +/************************* Timing graph structure **************************** + +Author: V. Betz + +We can build timing graphs that match either the primitive (logical_block) +netlist (of basic elements before clustering, like FFs and LUTs) or that +match the clustered netlist (block). You pass in the is_pre_packed flag to +say which kind of netlist and timing graph you are working with. + +Every used (not OPEN) block pin becomes a timing node, both on primitive +blocks and (if you’re building the timing graph that matches a clustered +netlist) on clustered blocks. For the clustered (not pre_packed) timing +graph, every used pin within a clustered (pb_type) block also becomes a timing +node. So a CLB that contains ALMs that contains LUTs will have nodes created +for the CLB pins, ALM pins and LUT pins, with edges that connect them as +specified in the clustered netlist. Unused (OPEN) pins don't create any +timing nodes. + +The primitive blocks have edges from the tnodes that represent input pins and +output pins that represent the timing dependencies within these lowest level +blocks (e.g. LUTs and FFs and IOs). The exact edges created come from reading +the architecture file. A LUT for example will have delays specified from all +its inputs to its output, and hence we will create a tedge from each tnode +corresponding to an input pin of the LUT to the tnode that represents the LUT +output pin. The delay marked on each edge is read from the architecture file. + +A FF has nodes representing its pins, but also two extra nodes, representing +the TN_FF_SINK and TN_FF_SOURCE. Those two nodes represent the internal storage +node of the FF. The TN_FF_SINK has edges going to it from the regular FF inputs +(but not the clock input), with appropriate delays. It has no outgoing edges, +since it terminates timing paths. The TN_FF_SOURCE has an edge going from it to +the FF output pin, with the appropriate delay. TN_FF_SOURCES have no edges; they +start timing paths. FF clock pins have no outgoing edges, but the delay to +them can be looked up, and is used in the timing traversals to compute clock +delay for slack computations. + +In the timing graph I create, input pads and constant generators have no +inputs (incoming edges), just like TN_FF_SOURCES. Every input pad and output +pad is represented by two tnodes -- an input pin/source and an output pin/ +sink. For an input pad the input source comes from off chip and has no fanin, +while the output pin drives signals within the chip. For output pads, the +input pin is driven by signal (net) within the chip, and the output sink node +goes off chip and has no fanout (out-edges). I need two nodes to respresent +things like pads because I mark all delay on tedges, not on tnodes. + +One other subblock that needs special attention is a constant generator. +This has no used inputs, but its output is used. I create an extra tnode, +a dummy input, in addition to the output pin tnode. The dummy tnode has +no fanin. Since constant generators really generate their outputs at T = +-infinity, I set the delay from the input tnode to the output to a large- +magnitude negative number. This guarantees every block that needs the +output of a constant generator sees it available very early. + +The main structure of the timing graph is given by the nodes and the edges +that connect them. We also store some extra information on tnodes that +(1) lets us figure out how to map from a tnode back to the netlist pin (or +other item) it represents and (2) figure out what clock domain it is on, if +it is a timing path start point (no incoming edges) or end point (no outgoing +edges) and (3) lets us figure out the delay of the clock to that node, if it +is a timing path start or end point. + +To map efficiently from tedges back to the netlist pins, we create the tedge +array driven by a tnode the represents a netlist output pin *in the same order +as the netlist net pins*. That means the edge index for the tedge array from +such a tnode guarantees iedge = net_pin_index 1. The code to map slacks +from the timing graph back to the netlist relies on this. */ + +/*************************** Global variables *******************************/ + +t_tnode *tnode = NULL; /* [0..num_tnodes - 1] */ +int num_tnodes = 0; /* Number of nodes (pins) in the timing graph */ + +/******************** Variables local to this module ************************/ + +#define NUM_BUCKETS 5 /* Used when printing slack and criticality. */ + +/* Variables for "chunking" the tedge memory. If the head pointer in tedge_ch is NULL, * + * no timing graph exists now. */ + +static t_chunk tedge_ch = {NULL, 0, NULL}; + +static struct s_net *timing_nets = NULL; + +static int num_timing_nets = 0; + +static t_timing_stats * f_timing_stats = NULL; /* Critical path delay and worst-case slack per constraint. */ + +static int * f_net_to_driver_tnode; +/* [0..num_nets - 1]. Gives the index of the tnode that drives each net. +Used for both pre- and post-packed netlists. If you just want the number +of edges on the driver tnode, use: + num_edges = timing_nets[inet].num_sinks; +instead of the equivalent but more convoluted: + driver_tnode = f_net_to_driver_tnode[inet]; + num_edges = tnode[driver_tnode].num_edges; +Only use this array if you want the actual edges themselves or the index +of the driver tnode. */ + +/***************** Subroutines local to this module *************************/ + +static t_slack * alloc_slacks(void); + +static void update_slacks(t_slack * slacks, int source_clock_domain, int sink_clock_domain, float criticality_denom, + boolean update_slack); + +static void alloc_and_load_tnodes(t_timing_inf timing_inf); + +static void alloc_and_load_tnodes_from_prepacked_netlist(float block_delay, + float inter_cluster_net_delay); + +static void alloc_timing_stats(void); + +static float do_timing_analysis_for_constraint(int source_clock_domain, int sink_clock_domain, + boolean is_prepacked, boolean is_final_analysis, long * max_critical_input_paths_ptr, + long * max_critical_output_paths_ptr); + +#ifdef PATH_COUNTING +static void do_path_counting(float criticality_denom); +#endif + +static void do_lut_rebalancing(); +static void load_tnode(INP t_pb_graph_pin *pb_graph_pin, INP int iblock, + INOUTP int *inode, INP t_timing_inf timing_inf); + +#ifndef PATH_COUNTING +static void update_normalized_costs(float T_arr_max_this_domain, long max_critical_input_paths, + long max_critical_output_paths); +#endif + +static void print_primitive_as_blif (FILE *fpout, int iblk); + +static void set_and_balance_arrival_time(int to_node, int from_node, float Tdel, boolean do_lut_input_balancing); + +static void load_clock_domain_and_clock_and_io_delay(boolean is_prepacked); + +static char * find_tnode_net_name(int inode, boolean is_prepacked); + +static t_tnode * find_ff_clock_tnode(int inode, boolean is_prepacked); + +static inline int get_tnode_index(t_tnode * node); + +static inline boolean has_valid_T_arr(int inode); + +static inline boolean has_valid_T_req(int inode); + +static int find_clock(char * net_name); + +static int find_input(char * net_name); + +static int find_output(char * net_name); + +static int find_cf_constraint(char * source_clock_name, char * sink_ff_name); + +static void propagate_clock_domain_and_skew(int inode); + +static void process_constraints(void); + +static void print_global_criticality_stats(FILE * fp, float ** criticality, const char * singular_name, const char * capitalized_plural_name); + +static void print_timing_constraint_info(const char *fname); + +static void print_spaces(FILE * fp, int num_spaces); + +/********************* Subroutine definitions *******************************/ + +t_slack * alloc_and_load_timing_graph(t_timing_inf timing_inf) { + + /* This routine builds the graph used for timing analysis. Every cb pin is a + * timing node (tnode). The connectivity between pins is * + * represented by timing edges (tedges). All delay is marked on edges, not * + * on nodes. Returns two arrays that will store slack values: * + * slack and criticality ([0..num_nets-1][1..num_pins]). */ + + /* For pads, only the first two pin locations are used (input to pad is first, + * output of pad is second). For CLBs, all OPEN pins on the cb have their + * mapping set to OPEN so I won't use it by mistake. */ + + int num_sinks; + t_slack * slacks = NULL; + boolean do_process_constraints = FALSE; + + if (tedge_ch.chunk_ptr_head != NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "in alloc_and_load_timing_graph: An old timing graph still exists.\n"); + exit(1); + } + num_timing_nets = num_nets; + timing_nets = clb_net; + + alloc_and_load_tnodes(timing_inf); + + num_sinks = alloc_and_load_timing_graph_levels(); + + check_timing_graph(num_sinks); + + slacks = alloc_slacks(); + + if (g_sdc == NULL) { + /* the SDC timing constraints only need to be read in once; * + * if they haven't been already, do it now */ + read_sdc(timing_inf); + do_process_constraints = TRUE; + } + + load_clock_domain_and_clock_and_io_delay(FALSE); + + if (do_process_constraints) + process_constraints(); + + if (f_timing_stats == NULL) + alloc_timing_stats(); + + return slacks; +} + +t_slack * alloc_and_load_pre_packing_timing_graph(float block_delay, + float inter_cluster_net_delay, t_model *models, t_timing_inf timing_inf) { + + /* This routine builds the graph used for timing analysis. Every technology- + * mapped netlist pin is a timing node (tnode). The connectivity between pins is * + * represented by timing edges (tedges). All delay is marked on edges, not * + * on nodes. Returns two arrays that will store slack values: * + * slack and criticality ([0..num_nets-1][1..num_pins]). */ + + /* For pads, only the first two pin locations are used (input to pad is first, + * output of pad is second). For CLBs, all OPEN pins on the cb have their + * mapping set to OPEN so I won't use it by mistake. */ + + int num_sinks; + t_slack * slacks = NULL; + boolean do_process_constraints = FALSE; + + if (tedge_ch.chunk_ptr_head != NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "in alloc_and_load_timing_graph: An old timing graph still exists.\n"); + exit(1); + } + + num_timing_nets = num_logical_nets; + timing_nets = vpack_net; + + alloc_and_load_tnodes_from_prepacked_netlist(block_delay, + inter_cluster_net_delay); + + num_sinks = alloc_and_load_timing_graph_levels(); + + slacks = alloc_slacks(); + + check_timing_graph(num_sinks); + + if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_PRE_PACKING_TIMING_GRAPH_AS_BLIF)) { + print_timing_graph_as_blif(getEchoFileName(E_ECHO_PRE_PACKING_TIMING_GRAPH_AS_BLIF), models); + } + + if (g_sdc == NULL) { + /* the SDC timing constraints only need to be read in once; * + * if they haven't been already, do it now */ + read_sdc(timing_inf); + do_process_constraints = TRUE; + } + + load_clock_domain_and_clock_and_io_delay(TRUE); + + if (do_process_constraints) + process_constraints(); + + if (f_timing_stats == NULL) + alloc_timing_stats(); + + return slacks; +} + +static t_slack * alloc_slacks(void) { + + /* Allocates the slack, criticality and path_criticality structures + ([0..num_nets-1][1..num_pins-1]). Chunk allocated to save space. */ + + int inet; + t_slack * slacks = (t_slack *) my_malloc(sizeof(t_slack)); + + slacks->slack = (float **) my_malloc(num_timing_nets * sizeof(float *)); + slacks->timing_criticality = (float **) my_malloc(num_timing_nets * sizeof(float *)); +#ifdef PATH_COUNTING + slacks->path_criticality = (float **) my_malloc(num_timing_nets * sizeof(float *)); +#endif + for (inet = 0; inet < num_timing_nets; inet++) { + slacks->slack[inet] = (float *) my_chunk_malloc((timing_nets[inet].num_sinks + 1) * sizeof(float), &tedge_ch); + slacks->timing_criticality[inet] = (float *) my_chunk_malloc((timing_nets[inet].num_sinks + 1) * sizeof(float), &tedge_ch); +#ifdef PATH_COUNTING + slacks->path_criticality[inet] = (float *) my_chunk_malloc((timing_nets[inet].num_sinks + 1) * sizeof(float), &tedge_ch); +#endif + } + + return slacks; +} + +void load_timing_graph_net_delays(float **net_delay) { + + /* Sets the delays of the inter-CLB nets to the values specified by * + * net_delay[0..num_nets-1][1..num_pins-1]. These net delays should have * + * been allocated and loaded with the net_delay routines. This routine * + * marks the corresponding edges in the timing graph with the proper delay. */ + + int inet, ipin, inode; + t_tedge *tedge; + + for (inet = 0; inet < num_timing_nets; inet++) { + inode = f_net_to_driver_tnode[inet]; + tedge = tnode[inode].out_edges; + + /* Note that the edges of a tnode corresponding to a CLB or INPAD opin must * + * be in the same order as the pins of the net driven by the tnode. */ + + for (ipin = 1; ipin < (timing_nets[inet].num_sinks + 1); ipin++) + tedge[ipin - 1].Tdel = net_delay[inet][ipin]; + } +} + +void free_timing_graph(t_slack * slacks) { + + int inode; + + if (tedge_ch.chunk_ptr_head == NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "in free_timing_graph: No timing graph to free.\n"); + exit(1); + } + + free_chunk_memory(&tedge_ch); + + if (tnode[0].prepacked_data) { + /* If we allocated prepacked_data for the first node, + it must be allocated for all other nodes too. */ + for (inode = 0; inode < num_tnodes; inode++) { + free(tnode[inode].prepacked_data); + } + } + free(tnode); + free(f_net_to_driver_tnode); + free_ivec_vector(tnodes_at_level, 0, num_tnode_levels - 1); + + free(slacks->slack); + free(slacks->timing_criticality); +#ifdef PATH_COUNTING + free(slacks->path_criticality); +#endif + free(slacks); + + tnode = NULL; + num_tnodes = 0; + f_net_to_driver_tnode = NULL; + tnodes_at_level = NULL; + num_tnode_levels = 0; + slacks = NULL; +} + +void free_timing_stats(void) { + int i; + if(f_timing_stats != NULL) { + for (i = 0; i < g_sdc->num_constrained_clocks; i++) { + free(f_timing_stats->cpd[i]); + free(f_timing_stats->least_slack[i]); + } + free(f_timing_stats->cpd); + free(f_timing_stats->least_slack); + free(f_timing_stats); + } + f_timing_stats = NULL; +} + +void print_slack(float ** slack, boolean slack_is_normalized, const char *fname) { + + /* Prints slacks into a file. */ + + int inet, iedge, ibucket, driver_tnode, num_edges, num_unused_slacks = 0; + t_tedge * tedge; + FILE *fp; + float max_slack = HUGE_NEGATIVE_FLOAT, min_slack = HUGE_POSITIVE_FLOAT, + total_slack = 0, total_negative_slack = 0, bucket_size, slk; + int slacks_in_bucket[NUM_BUCKETS]; + + fp = my_fopen(fname, "w", 0); + + if (slack_is_normalized) { + fprintf(fp, "The following slacks have been normalized to be non-negative by " + "relaxing the required times to the maximum arrival time.\n\n"); + } + + /* Go through slack once to get the largest and smallest slack, both for reporting and + so that we can delimit the buckets. Also calculate the total negative slack in the design. */ + for (inet = 0; inet < num_timing_nets; inet++) { + num_edges = timing_nets[inet].num_sinks; + for (iedge = 0; iedge < num_edges; iedge++) { + slk = slack[inet][iedge + 1]; + if (slk < HUGE_POSITIVE_FLOAT - 1) { /* if slack was analysed */ + max_slack = std::max(max_slack, slk); + min_slack = std::min(min_slack, slk); + total_slack += slk; + if (slk < NEGATIVE_EPSILON) { + total_negative_slack -= slk; /* By convention, we'll have total_negative_slack be a positive number. */ + } + } else { /* slack was never analysed */ + num_unused_slacks++; + } + } + } + + if (max_slack > HUGE_NEGATIVE_FLOAT + 1) { + fprintf(fp, "Largest slack in design: %g\n", max_slack); + } else { + fprintf(fp, "Largest slack in design: --\n"); + } + + if (min_slack < HUGE_POSITIVE_FLOAT - 1) { + fprintf(fp, "Smallest slack in design: %g\n", min_slack); + } else { + fprintf(fp, "Smallest slack in design: --\n"); + } + + fprintf(fp, "Total slack in design: %g\n", total_slack); + fprintf(fp, "Total negative slack: %g\n", total_negative_slack); + + if (max_slack - min_slack > EPSILON) { /* Only sort the slacks into buckets if not all slacks are the same (if they are identical, no need to sort). */ + /* Initialize slacks_in_bucket, an array counting how many slacks are within certain linearly-spaced ranges (buckets). */ + for (ibucket = 0; ibucket < NUM_BUCKETS; ibucket++) { + slacks_in_bucket[ibucket] = 0; + } + + /* The size of each bucket is the range of slacks, divided by the number of buckets. */ + bucket_size = (max_slack - min_slack)/NUM_BUCKETS; + + /* Now, pass through again, incrementing the number of slacks in the nth bucket + for each slack between (min_slack + n*bucket_size) and (min_slack + (n+1)*bucket_size). */ + + for (inet = 0; inet < num_timing_nets; inet++) { + num_edges = timing_nets[inet].num_sinks; + for (iedge = 0; iedge < num_edges; iedge++) { + slk = slack[inet][iedge + 1]; + if (slk < HUGE_POSITIVE_FLOAT - 1) { + /* We have to watch out for the special case where slack = max_slack, in which case ibucket = NUM_BUCKETS and we go out of bounds of the array. */ + ibucket = std::min(NUM_BUCKETS - 1, (int) ((slk - min_slack)/bucket_size)); + assert(ibucket >= 0 && ibucket < NUM_BUCKETS); + slacks_in_bucket[ibucket]++; + } + } + } + + /* Now print how many slacks are in each bucket. */ + fprintf(fp, "\n\nRange\t\t"); + for (ibucket = 0; ibucket < NUM_BUCKETS; ibucket++) { + fprintf(fp, "%.1e to ", min_slack); + min_slack += bucket_size; + fprintf(fp, "%.1e\t", min_slack); + } + fprintf(fp, "Not analysed"); + fprintf(fp, "\nSlacks in range\t\t"); + for (ibucket = 0; ibucket < NUM_BUCKETS; ibucket++) { + fprintf(fp, "%d\t\t\t", slacks_in_bucket[ibucket]); + } + fprintf(fp, "%d", num_unused_slacks); + } + + /* Finally, print all the slacks, organized by net. */ + fprintf(fp, "\n\nNet #\tDriver_tnode\tto_node\tSlack\n\n"); + + for (inet = 0; inet < num_timing_nets; inet++) { + driver_tnode = f_net_to_driver_tnode[inet]; + num_edges = tnode[driver_tnode].num_edges; + tedge = tnode[driver_tnode].out_edges; + slk = slack[inet][1]; + if (slk < HUGE_POSITIVE_FLOAT - 1) { + fprintf(fp, "%5d\t%5d\t\t%5d\t%g\n", inet, driver_tnode, tedge[0].to_node, slk); + } else { /* Slack is meaningless, so replace with --. */ + fprintf(fp, "%5d\t%5d\t\t%5d\t--\n", inet, driver_tnode, tedge[0].to_node); + } + for (iedge = 1; iedge < num_edges; iedge++) { /* newline and indent subsequent edges after the first */ + slk = slack[inet][iedge+1]; + if (slk < HUGE_POSITIVE_FLOAT - 1) { + fprintf(fp, "\t\t\t%5d\t%g\n", tedge[iedge].to_node, slk); + } else { /* Slack is meaningless, so replace with --. */ + fprintf(fp, "\t\t\t%5d\t--\n", tedge[iedge].to_node); + } + } + } + + fclose(fp); +} + +void print_criticality(t_slack * slacks, boolean criticality_is_normalized, const char *fname) { + + /* Prints timing criticalities (and path criticalities if enabled) into a file. */ + + int inet, iedge, driver_tnode, num_edges; + t_tedge * tedge; + FILE *fp; + + fp = my_fopen(fname, "w", 0); + + if (criticality_is_normalized) { + fprintf(fp, "Timing criticalities have been normalized to be non-negative by " + "relaxing the required times to the maximum arrival time.\n\n"); + } + + print_global_criticality_stats(fp, slacks->timing_criticality, "timing criticality", "Timing criticalities"); +#ifdef PATH_COUNTING + print_global_criticality_stats(fp, slacks->path_criticality, "path criticality", "Path criticalities"); +#endif + + /* Finally, print all the criticalities, organized by net. */ + fprintf(fp, "\n\nNet #\tDriver_tnode\t to_node\tTiming criticality" +#ifdef PATH_COUNTING + "\tPath criticality" +#endif + "\n"); + + for (inet = 0; inet < num_timing_nets; inet++) { + driver_tnode = f_net_to_driver_tnode[inet]; + num_edges = tnode[driver_tnode].num_edges; + tedge = tnode[driver_tnode].out_edges; + + fprintf(fp, "\n%5d\t%5d\t\t%5d\t\t%.6f", inet, driver_tnode, tedge[0].to_node, slacks->timing_criticality[inet][1]); +#ifdef PATH_COUNTING + fprintf(fp, "\t\t%g", slacks->path_criticality[inet][1]); +#endif + for (iedge = 1; iedge < num_edges; iedge++) { /* newline and indent subsequent edges after the first */ + fprintf(fp, "\n\t\t\t%5d\t\t%.6f", tedge[iedge].to_node, slacks->timing_criticality[inet][iedge+1]); +#ifdef PATH_COUNTING + fprintf(fp, "\t\t%g", slacks->path_criticality[inet][iedge+1]); +#endif + } + } + + fclose(fp); +} + +static void print_global_criticality_stats(FILE * fp, float ** criticality, const char * singular_name, const char * capitalized_plural_name) { + + /* Prints global stats for timing or path criticality to the file pointed to by fp, + including maximum criticality, minimum criticality, total criticality in the design, + and the number of criticalities within various ranges, or buckets. */ + + int inet, iedge, num_edges, ibucket, criticalities_in_bucket[NUM_BUCKETS]; + float crit, max_criticality = HUGE_NEGATIVE_FLOAT, min_criticality = HUGE_POSITIVE_FLOAT, + total_criticality = 0, bucket_size; + + /* Go through criticality once to get the largest and smallest timing criticality, + both for reporting and so that we can delimit the buckets. */ + for (inet = 0; inet < num_timing_nets; inet++) { + num_edges = timing_nets[inet].num_sinks; + for (iedge = 0; iedge < num_edges; iedge++) { + crit = criticality[inet][iedge + 1]; + max_criticality = std::max(max_criticality, crit); + min_criticality = std::min(min_criticality, crit); + total_criticality += crit; + } + } + + fprintf(fp, "Largest %s in design: %g\n", singular_name, max_criticality); + fprintf(fp, "Smallest %s in design: %g\n", singular_name, min_criticality); + fprintf(fp, "Total %s in design: %g\n", singular_name, total_criticality); + + if (max_criticality - min_criticality > EPSILON) { /* Only sort the criticalities into buckets if not all criticalities are the same (if they are identical, no need to sort). */ + /* Initialize criticalities_in_bucket, an array counting how many criticalities are within certain linearly-spaced ranges (buckets). */ + for (ibucket = 0; ibucket < NUM_BUCKETS; ibucket++) { + criticalities_in_bucket[ibucket] = 0; + } + + /* The size of each bucket is the range of criticalities, divided by the number of buckets. */ + bucket_size = (max_criticality - min_criticality)/NUM_BUCKETS; + + /* Now, pass through again, incrementing the number of criticalities in the nth bucket + for each criticality between (min_criticality + n*bucket_size) and (min_criticality + (n+1)*bucket_size). */ + + for (inet = 0; inet < num_timing_nets; inet++) { + num_edges = timing_nets[inet].num_sinks; + for (iedge = 0; iedge < num_edges; iedge++) { + crit = criticality[inet][iedge + 1]; + /* We have to watch out for the special case where criticality = max_criticality, in which case ibucket = NUM_BUCKETS and we go out of bounds of the array. */ + ibucket = std::min(NUM_BUCKETS - 1, (int) ((crit - min_criticality)/bucket_size)); + assert(ibucket >= 0 && ibucket < NUM_BUCKETS); + criticalities_in_bucket[ibucket]++; + } + } + + /* Now print how many criticalities are in each bucket. */ + fprintf(fp, "\nRange\t\t"); + for (ibucket = 0; ibucket < NUM_BUCKETS; ibucket++) { + fprintf(fp, "%.1e to ", min_criticality); + min_criticality += bucket_size; + fprintf(fp, "%.1e\t", min_criticality); + } + fprintf(fp, "\n%s in range\t\t", capitalized_plural_name); + for (ibucket = 0; ibucket < NUM_BUCKETS; ibucket++) { + fprintf(fp, "%d\t\t\t", criticalities_in_bucket[ibucket]); + } + } + fprintf(fp, "\n\n"); +} + +void print_net_delay(float **net_delay, const char *fname) { + + /* Prints the net delays into a file. */ + + int inet, iedge, driver_tnode, num_edges; + t_tedge * tedge; + FILE *fp; + + fp = my_fopen(fname, "w", 0); + + fprintf(fp, "Net #\tDriver_tnode\tto_node\tDelay\n\n"); + + for (inet = 0; inet < num_timing_nets; inet++) { + driver_tnode = f_net_to_driver_tnode[inet]; + num_edges = tnode[driver_tnode].num_edges; + tedge = tnode[driver_tnode].out_edges; + fprintf(fp, "%5d\t%5d\t\t%5d\t%g\n", inet, driver_tnode, tedge[0].to_node, net_delay[inet][1]); + for (iedge = 1; iedge < num_edges; iedge++) { /* newline and indent subsequent edges after the first */ + fprintf(fp, "\t\t\t%5d\t%g\n", tedge[iedge].to_node, net_delay[inet][iedge+1]); + } + } + + fclose(fp); +} + +#ifndef PATH_COUNTING +void print_clustering_timing_info(const char *fname) { + /* Print information from tnodes which is used by the clusterer. */ + int inode; + FILE *fp; + + fp = my_fopen(fname, "w", 0); + + fprintf(fp, "inode "); + if (g_sdc->num_constrained_clocks <= 1) { + /* These values are from the last constraint analysed, + so they're not meaningful unless there was only one constraint. */ + fprintf(fp, "Critical input paths Critical output paths "); + } + fprintf(fp, "Normalized slack Normalized Tarr Normalized total crit paths\n"); + for (inode = 0; inode < num_tnodes; inode++) { + fprintf(fp, "%d\t", inode); + /* Only print normalized values for tnodes which have valid normalized values. (If normalized_T_arr is valid, the others will be too.) */ + if (has_valid_normalized_T_arr(inode)) { + if (g_sdc->num_constrained_clocks <= 1) { + fprintf(fp, "%ld\t\t\t%ld\t\t\t", tnode[inode].prepacked_data->num_critical_input_paths, tnode[inode].prepacked_data->num_critical_output_paths); + } + fprintf(fp, "%f\t%f\t%f\n", tnode[inode].prepacked_data->normalized_slack, tnode[inode].prepacked_data->normalized_T_arr, tnode[inode].prepacked_data->normalized_total_critical_paths); + } else { + if (g_sdc->num_constrained_clocks <= 1) { + fprintf(fp, "--\t\t\t--\t\t\t"); + } + fprintf(fp, "--\t\t--\t\t--\n"); + } + } + + fclose(fp); +} +#endif +/* Count # of tnodes, allocates space, and loads the tnodes and its associated edges */ +static void alloc_and_load_tnodes(t_timing_inf timing_inf) { + int i, j, k; + int inode; + int num_nodes_in_block; + int count; + int iblock, irr_node; + int inet, dport, dpin, dblock, dnode; + int normalized_pin, normalization; + t_pb_graph_pin *ipb_graph_pin; + t_rr_node *local_rr_graph, *d_rr_graph; + int num_dangling_pins; + + f_net_to_driver_tnode = (int*)my_malloc(num_timing_nets * sizeof(int)); + + for (i = 0; i < num_timing_nets; i++) { + f_net_to_driver_tnode[i] = OPEN; + } + + /* allocate space for tnodes */ + num_tnodes = 0; + for (i = 0; i < num_blocks; i++) { + num_nodes_in_block = 0; + for (j = 0; j < block[i].pb->pb_graph_node->total_pb_pins; j++) { + if (block[i].pb->rr_graph[j].net_num != OPEN) { + if (block[i].pb->rr_graph[j].pb_graph_pin->type == PB_PIN_INPAD + || block[i].pb->rr_graph[j].pb_graph_pin->type + == PB_PIN_OUTPAD + || block[i].pb->rr_graph[j].pb_graph_pin->type + == PB_PIN_SEQUENTIAL) { + num_nodes_in_block += 2; + } else { + num_nodes_in_block++; + } + } + } + num_tnodes += num_nodes_in_block; + } + tnode = (t_tnode*)my_calloc(num_tnodes, sizeof(t_tnode)); + + /* load tnodes with all info except edge info */ + /* populate tnode lookups for edge info */ + inode = 0; + for (i = 0; i < num_blocks; i++) { + for (j = 0; j < block[i].pb->pb_graph_node->total_pb_pins; j++) { + if (block[i].pb->rr_graph[j].net_num != OPEN) { + assert(tnode[inode].pb_graph_pin == NULL); + load_tnode(block[i].pb->rr_graph[j].pb_graph_pin, i, &inode, + timing_inf); + } + } + } + assert(inode == num_tnodes); + num_dangling_pins = 0; + + /* load edge delays and initialize clock domains to OPEN + and prepacked_data (which is not used post-packing) to NULL. */ + for (i = 0; i < num_tnodes; i++) { + tnode[i].clock_domain = OPEN; + tnode[i].prepacked_data = NULL; + + /* 3 primary scenarios for edge delays + 1. Point-to-point delays inside block + 2. + */ + count = 0; + iblock = tnode[i].block; + switch (tnode[i].type) { + case TN_INPAD_OPIN: + case TN_INTERMEDIATE_NODE: + case TN_PRIMITIVE_OPIN: + case TN_FF_OPIN: + case TN_CB_IPIN: + /* fanout is determined by intra-cluster connections */ + /* Allocate space for edges */ + irr_node = tnode[i].pb_graph_pin->pin_count_in_cluster; + local_rr_graph = block[iblock].pb->rr_graph; + ipb_graph_pin = local_rr_graph[irr_node].pb_graph_pin; + + if (ipb_graph_pin->parent_node->pb_type->max_internal_delay + != UNDEFINED) { + if (pb_max_internal_delay == UNDEFINED) { + pb_max_internal_delay = + ipb_graph_pin->parent_node->pb_type->max_internal_delay; + pbtype_max_internal_delay = + ipb_graph_pin->parent_node->pb_type; + } else if (pb_max_internal_delay + < ipb_graph_pin->parent_node->pb_type->max_internal_delay) { + pb_max_internal_delay = + ipb_graph_pin->parent_node->pb_type->max_internal_delay; + pbtype_max_internal_delay = + ipb_graph_pin->parent_node->pb_type; + } + } + + for (j = 0; j < block[iblock].pb->rr_graph[irr_node].num_edges; + j++) { + dnode = local_rr_graph[irr_node].edges[j]; + if ((local_rr_graph[dnode].prev_node == irr_node) + && (j == local_rr_graph[dnode].prev_edge)) { + count++; + } + } + assert(count > 0); + tnode[i].num_edges = count; + tnode[i].out_edges = (t_tedge *) my_chunk_malloc( + count * sizeof(t_tedge), &tedge_ch); + + /* Load edges */ + count = 0; + for (j = 0; j < local_rr_graph[irr_node].num_edges; j++) { + dnode = local_rr_graph[irr_node].edges[j]; + if ((local_rr_graph[dnode].prev_node == irr_node) + && (j == local_rr_graph[dnode].prev_edge)) { + assert( + (ipb_graph_pin->output_edges[j]->num_output_pins == 1) && (local_rr_graph[ipb_graph_pin->output_edges[j]->output_pins[0]->pin_count_in_cluster].net_num == local_rr_graph[irr_node].net_num)); + + tnode[i].out_edges[count].Tdel = + ipb_graph_pin->output_edges[j]->delay_max; + tnode[i].out_edges[count].to_node = + get_tnode_index(local_rr_graph[dnode].tnode); + + if (vpack_net[local_rr_graph[irr_node].net_num].is_const_gen + == TRUE && tnode[i].type == TN_PRIMITIVE_OPIN) { + tnode[i].out_edges[count].Tdel = HUGE_NEGATIVE_FLOAT; + tnode[i].type = TN_CONSTANT_GEN_SOURCE; + } + + count++; + } + } + assert(count > 0); + + break; + case TN_PRIMITIVE_IPIN: + /* Pin info comes from pb_graph block delays + */ + /*there would be no slack information if timing analysis is off*/ + if (timing_inf.timing_analysis_enabled) + { + irr_node = tnode[i].pb_graph_pin->pin_count_in_cluster; + local_rr_graph = block[iblock].pb->rr_graph; + ipb_graph_pin = local_rr_graph[irr_node].pb_graph_pin; + tnode[i].num_edges = ipb_graph_pin->num_pin_timing; + tnode[i].out_edges = (t_tedge *) my_chunk_malloc( + ipb_graph_pin->num_pin_timing * sizeof(t_tedge), + &tedge_ch); + k = 0; + + for (j = 0; j < tnode[i].num_edges; j++) { + /* Some outpins aren't used, ignore these. Only consider output pins that are used */ + if (local_rr_graph[ipb_graph_pin->pin_timing[j]->pin_count_in_cluster].net_num + != OPEN) { + tnode[i].out_edges[k].Tdel = + ipb_graph_pin->pin_timing_del_max[j]; + tnode[i].out_edges[k].to_node = + get_tnode_index(local_rr_graph[ipb_graph_pin->pin_timing[j]->pin_count_in_cluster].tnode); + assert(tnode[i].out_edges[k].to_node != OPEN); + k++; + } + } + tnode[i].num_edges -= (j - k); /* remove unused edges */ + if (tnode[i].num_edges == 0) { + /* Dangling pin */ + num_dangling_pins++; + } + } + break; + case TN_CB_OPIN: + /* load up net info */ + irr_node = tnode[i].pb_graph_pin->pin_count_in_cluster; + local_rr_graph = block[iblock].pb->rr_graph; + ipb_graph_pin = local_rr_graph[irr_node].pb_graph_pin; + assert(local_rr_graph[irr_node].net_num != OPEN); + inet = vpack_to_clb_net_mapping[local_rr_graph[irr_node].net_num]; + assert(inet != OPEN); + f_net_to_driver_tnode[inet] = i; + tnode[i].num_edges = clb_net[inet].num_sinks; + tnode[i].out_edges = (t_tedge *) my_chunk_malloc( + clb_net[inet].num_sinks * sizeof(t_tedge), + &tedge_ch); + for (j = 1; j <= clb_net[inet].num_sinks; j++) { + dblock = clb_net[inet].node_block[j]; + normalization = block[dblock].type->num_pins + / block[dblock].type->capacity; + normalized_pin = clb_net[inet].node_block_pin[j] + % normalization; + d_rr_graph = block[dblock].pb->rr_graph; + dpin = OPEN; + dport = OPEN; + count = 0; + + for (k = 0; + k < block[dblock].pb->pb_graph_node->num_input_ports + && dpin == OPEN; k++) { + if (normalized_pin >= count + && (count + + block[dblock].pb->pb_graph_node->num_input_pins[k] + > normalized_pin)) { + dpin = normalized_pin - count; + dport = k; + break; + } + count += block[dblock].pb->pb_graph_node->num_input_pins[k]; + } + if (dpin == OPEN) { + for (k = 0; + k + < block[dblock].pb->pb_graph_node->num_output_ports + && dpin == OPEN; k++) { + count += + block[dblock].pb->pb_graph_node->num_output_pins[k]; + } + for (k = 0; + k < block[dblock].pb->pb_graph_node->num_clock_ports + && dpin == OPEN; k++) { + if (normalized_pin >= count + && (count + + block[dblock].pb->pb_graph_node->num_clock_pins[k] + > normalized_pin)) { + dpin = normalized_pin - count; + dport = k; + } + count += + block[dblock].pb->pb_graph_node->num_clock_pins[k]; + } + assert(dpin != OPEN); + assert( + inet == vpack_to_clb_net_mapping[d_rr_graph[block[dblock].pb->pb_graph_node->clock_pins[dport][dpin].pin_count_in_cluster].net_num]); + tnode[i].out_edges[j - 1].to_node = + get_tnode_index(d_rr_graph[block[dblock].pb->pb_graph_node->clock_pins[dport][dpin].pin_count_in_cluster].tnode); + } else { + assert(dpin != OPEN); + assert(inet == vpack_to_clb_net_mapping[d_rr_graph[block[dblock].pb->pb_graph_node->input_pins[dport][dpin].pin_count_in_cluster].net_num]); + /* delays are assigned post routing */ + tnode[i].out_edges[j - 1].to_node = + get_tnode_index(d_rr_graph[block[dblock].pb->pb_graph_node->input_pins[dport][dpin].pin_count_in_cluster].tnode); + } + tnode[i].out_edges[j - 1].Tdel = 0; + assert(inet != OPEN); + } + break; + case TN_OUTPAD_IPIN: + case TN_INPAD_SOURCE: + case TN_OUTPAD_SINK: + case TN_FF_SINK: + case TN_FF_SOURCE: + case TN_FF_IPIN: + case TN_FF_CLOCK: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "Consistency check failed: Unknown tnode type %d.\n", tnode[i].type); + assert(0); + break; + } + } + if(num_dangling_pins > 0) { + vpr_printf(TIO_MESSAGE_WARNING, "Unconnected logic in design, number of dangling tnodes = %d\n", num_dangling_pins); + } +} + +/* Allocate timing graph for pre packed netlist + Count number of tnodes first + Then connect up tnodes with edges + */ +static void alloc_and_load_tnodes_from_prepacked_netlist(float block_delay, + float inter_cluster_net_delay) { + int i, j, k; + t_model *model; + t_model_ports *model_port; + t_pb_graph_pin *from_pb_graph_pin, *to_pb_graph_pin; + int inode, inet; + int incr; + int count; + + f_net_to_driver_tnode = (int*)my_malloc(num_logical_nets * sizeof(int)); + + for (i = 0; i < num_logical_nets; i++) { + f_net_to_driver_tnode[i] = OPEN; + } + + /* allocate space for tnodes */ + num_tnodes = 0; + for (i = 0; i < num_logical_blocks; i++) { + model = logical_block[i].model; + logical_block[i].clock_net_tnode = NULL; + if (logical_block[i].type == VPACK_INPAD) { + logical_block[i].output_net_tnodes = (t_tnode***)my_calloc(1, + sizeof(t_tnode**)); + num_tnodes += 2; + } else if (logical_block[i].type == VPACK_OUTPAD) { + logical_block[i].input_net_tnodes = (t_tnode***)my_calloc(1, sizeof(t_tnode**)); + num_tnodes += 2; + } else { + if (logical_block[i].clock_net == OPEN) { + incr = 1; + } else { + incr = 2; + } + j = 0; + model_port = model->inputs; + while (model_port) { + if (model_port->is_clock == FALSE) { + for (k = 0; k < model_port->size; k++) { + if (logical_block[i].input_nets[j][k] != OPEN) { + num_tnodes += incr; + } + } + j++; + } else { + num_tnodes++; + } + model_port = model_port->next; + } + logical_block[i].input_net_tnodes = (t_tnode ***)my_calloc(j, sizeof(t_tnode**)); + + j = 0; + model_port = model->outputs; + while (model_port) { + for (k = 0; k < model_port->size; k++) { + if (logical_block[i].output_nets[j][k] != OPEN) { + num_tnodes += incr; + } + } + j++; + model_port = model_port->next; + } + logical_block[i].output_net_tnodes = (t_tnode ***)my_calloc(j, + sizeof(t_tnode**)); + } + } + tnode = (t_tnode *)my_calloc(num_tnodes, sizeof(t_tnode)); + + /* Allocate space for prepacked_data, which is only used pre-packing. */ + for (inode = 0; inode < num_tnodes; inode++) { + tnode[inode].prepacked_data = (t_prepacked_tnode_data *) my_malloc(sizeof(t_prepacked_tnode_data)); + } + + /* load tnodes, alloc edges for tnodes, load all known tnodes */ + inode = 0; + for (i = 0; i < num_logical_blocks; i++) { + model = logical_block[i].model; + if (logical_block[i].type == VPACK_INPAD) { + logical_block[i].output_net_tnodes[0] = (t_tnode **)my_calloc(1, + sizeof(t_tnode*)); + logical_block[i].output_net_tnodes[0][0] = &tnode[inode]; + f_net_to_driver_tnode[logical_block[i].output_nets[0][0]] = inode; + tnode[inode].prepacked_data->model_pin = 0; + tnode[inode].prepacked_data->model_port = 0; + tnode[inode].prepacked_data->model_port_ptr = model->outputs; + tnode[inode].block = i; + tnode[inode].type = TN_INPAD_OPIN; + + tnode[inode].num_edges = + vpack_net[logical_block[i].output_nets[0][0]].num_sinks; + tnode[inode].out_edges = (t_tedge *) my_chunk_malloc( + tnode[inode].num_edges * sizeof(t_tedge), + &tedge_ch); + tnode[inode + 1].num_edges = 1; + tnode[inode + 1].out_edges = (t_tedge *) my_chunk_malloc( + 1 * sizeof(t_tedge), &tedge_ch); + tnode[inode + 1].out_edges->Tdel = 0; + tnode[inode + 1].out_edges->to_node = inode; + tnode[inode + 1].type = TN_INPAD_SOURCE; + tnode[inode + 1].block = i; + inode += 2; + } else if (logical_block[i].type == VPACK_OUTPAD) { + logical_block[i].input_net_tnodes[0] = (t_tnode **)my_calloc(1, + sizeof(t_tnode*)); + logical_block[i].input_net_tnodes[0][0] = &tnode[inode]; + tnode[inode].prepacked_data->model_pin = 0; + tnode[inode].prepacked_data->model_port = 0; + tnode[inode].prepacked_data->model_port_ptr = model->inputs; + tnode[inode].block = i; + tnode[inode].type = TN_OUTPAD_IPIN; + tnode[inode].num_edges = 1; + tnode[inode].out_edges = (t_tedge *) my_chunk_malloc( + 1 * sizeof(t_tedge), &tedge_ch); + tnode[inode].out_edges->Tdel = 0; + tnode[inode].out_edges->to_node = inode + 1; + tnode[inode + 1].type = TN_OUTPAD_SINK; + tnode[inode + 1].block = i; + tnode[inode + 1].num_edges = 0; + tnode[inode + 1].out_edges = NULL; + inode += 2; + } else { + j = 0; + model_port = model->outputs; + while (model_port) { + logical_block[i].output_net_tnodes[j] = (t_tnode **)my_calloc( + model_port->size, sizeof(t_tnode*)); + for (k = 0; k < model_port->size; k++) { + if (logical_block[i].output_nets[j][k] != OPEN) { + tnode[inode].prepacked_data->model_pin = k; + tnode[inode].prepacked_data->model_port = j; + tnode[inode].prepacked_data->model_port_ptr = model_port; + tnode[inode].block = i; + f_net_to_driver_tnode[logical_block[i].output_nets[j][k]] = + inode; + logical_block[i].output_net_tnodes[j][k] = + &tnode[inode]; + + tnode[inode].num_edges = + vpack_net[logical_block[i].output_nets[j][k]].num_sinks; + tnode[inode].out_edges = (t_tedge *) my_chunk_malloc( + tnode[inode].num_edges * sizeof(t_tedge), + &tedge_ch); + + if (logical_block[i].clock_net == OPEN) { + tnode[inode].type = TN_PRIMITIVE_OPIN; + inode++; + } else { + /* load delays from predicted clock-to-Q time */ + from_pb_graph_pin = get_pb_graph_node_pin_from_model_port_pin(model_port, k, logical_block[i].expected_lowest_cost_primitive); + tnode[inode].type = TN_FF_OPIN; + tnode[inode + 1].num_edges = 1; + tnode[inode + 1].out_edges = + (t_tedge *) my_chunk_malloc( + 1 * sizeof(t_tedge), + &tedge_ch); + tnode[inode + 1].out_edges->to_node = inode; + tnode[inode + 1].out_edges->Tdel = from_pb_graph_pin->tsu_tco; + tnode[inode + 1].type = TN_FF_SOURCE; + tnode[inode + 1].block = i; + inode += 2; + } + } + } + j++; + model_port = model_port->next; + } + + j = 0; + model_port = model->inputs; + while (model_port) { + if (model_port->is_clock == FALSE) { + logical_block[i].input_net_tnodes[j] = (t_tnode **)my_calloc( + model_port->size, sizeof(t_tnode*)); + for (k = 0; k < model_port->size; k++) { + if (logical_block[i].input_nets[j][k] != OPEN) { + tnode[inode].prepacked_data->model_pin = k; + tnode[inode].prepacked_data->model_port = j; + tnode[inode].prepacked_data->model_port_ptr = model_port; + tnode[inode].block = i; + logical_block[i].input_net_tnodes[j][k] = + &tnode[inode]; + from_pb_graph_pin = get_pb_graph_node_pin_from_model_port_pin(model_port, k, logical_block[i].expected_lowest_cost_primitive); + if (logical_block[i].clock_net == OPEN) { + /* load predicted combinational delays to predicted edges */ + tnode[inode].type = TN_PRIMITIVE_IPIN; + tnode[inode].out_edges = + (t_tedge *) my_chunk_malloc( + from_pb_graph_pin->num_pin_timing * sizeof(t_tedge), + &tedge_ch); + count = 0; + for(int m = 0; m < from_pb_graph_pin->num_pin_timing; m++) { + to_pb_graph_pin = from_pb_graph_pin->pin_timing[m]; + if(logical_block[i].output_nets[to_pb_graph_pin->port->model_port->index][to_pb_graph_pin->pin_number] == OPEN) { + continue; + } + tnode[inode].out_edges[count].Tdel = from_pb_graph_pin->pin_timing_del_max[m]; + tnode[inode].out_edges[count].to_node = + get_tnode_index(logical_block[i].output_net_tnodes[to_pb_graph_pin->port->model_port->index][to_pb_graph_pin->pin_number]); + count++; + } + tnode[inode].num_edges = count; + inode++; + } else { + /* load predicted setup time */ + tnode[inode].type = TN_FF_IPIN; + tnode[inode].num_edges = 1; + tnode[inode].out_edges = + (t_tedge *) my_chunk_malloc( + 1 * sizeof(t_tedge), + &tedge_ch); + tnode[inode].out_edges->to_node = inode + 1; + tnode[inode].out_edges->Tdel = from_pb_graph_pin->tsu_tco; + tnode[inode + 1].type = TN_FF_SINK; + tnode[inode + 1].num_edges = 0; + tnode[inode + 1].out_edges = NULL; + tnode[inode + 1].block = i; + inode += 2; + } + } + } + j++; + } else { + if (logical_block[i].clock_net != OPEN) { + assert(logical_block[i].clock_net_tnode == NULL); + logical_block[i].clock_net_tnode = &tnode[inode]; + tnode[inode].block = i; + tnode[inode].prepacked_data->model_pin = 0; + tnode[inode].prepacked_data->model_port = 0; + tnode[inode].prepacked_data->model_port_ptr = model_port; + tnode[inode].num_edges = 0; + tnode[inode].out_edges = NULL; + tnode[inode].type = TN_FF_CLOCK; + inode++; + } + } + model_port = model_port->next; + } + } + } + assert(inode == num_tnodes); + + /* load edge delays and initialize clock domains to OPEN. */ + for (i = 0; i < num_tnodes; i++) { + tnode[i].clock_domain = OPEN; + + /* 3 primary scenarios for edge delays + 1. Point-to-point delays inside block + 2. + */ + count = 0; + switch (tnode[i].type) { + case TN_INPAD_OPIN: + case TN_PRIMITIVE_OPIN: + case TN_FF_OPIN: + /* fanout is determined by intra-cluster connections */ + /* Allocate space for edges */ + inet = + logical_block[tnode[i].block].output_nets[tnode[i].prepacked_data->model_port][tnode[i].prepacked_data->model_pin]; + assert(inet != OPEN); + + for (j = 1; j <= vpack_net[inet].num_sinks; j++) { + if (vpack_net[inet].is_const_gen) { + tnode[i].out_edges[j - 1].Tdel = HUGE_NEGATIVE_FLOAT; + tnode[i].type = TN_CONSTANT_GEN_SOURCE; + } else { + tnode[i].out_edges[j - 1].Tdel = inter_cluster_net_delay; + } + if (vpack_net[inet].is_global) { + assert( + logical_block[vpack_net[inet].node_block[j]].clock_net == inet); + tnode[i].out_edges[j - 1].to_node = + get_tnode_index(logical_block[vpack_net[inet].node_block[j]].clock_net_tnode); + } else { + assert( + logical_block[vpack_net[inet].node_block[j]].input_net_tnodes[vpack_net[inet].node_block_port[j]][vpack_net[inet].node_block_pin[j]] != NULL); + tnode[i].out_edges[j - 1].to_node = + get_tnode_index(logical_block[vpack_net[inet].node_block[j]].input_net_tnodes[vpack_net[inet].node_block_port[j]][vpack_net[inet].node_block_pin[j]]); + } + } + assert(tnode[i].num_edges == vpack_net[inet].num_sinks); + break; + case TN_PRIMITIVE_IPIN: + case TN_OUTPAD_IPIN: + case TN_INPAD_SOURCE: + case TN_OUTPAD_SINK: + case TN_FF_SINK: + case TN_FF_SOURCE: + case TN_FF_IPIN: + case TN_FF_CLOCK: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "Consistency check failed: Unknown tnode type %d.\n", tnode[i].type); + assert(0); + break; + } + } + + for (i = 0; i < num_logical_nets; i++) { + assert(f_net_to_driver_tnode[i] != OPEN); + } +} + +static void load_tnode(INP t_pb_graph_pin *pb_graph_pin, INP int iblock, + INOUTP int *inode, INP t_timing_inf timing_inf) { + int i; + i = *inode; + tnode[i].pb_graph_pin = pb_graph_pin; + tnode[i].block = iblock; + block[iblock].pb->rr_graph[pb_graph_pin->pin_count_in_cluster].tnode = + &tnode[i]; + if (tnode[i].pb_graph_pin->parent_node->pb_type->blif_model == NULL) { + assert(tnode[i].pb_graph_pin->type == PB_PIN_NORMAL); + if (tnode[i].pb_graph_pin->parent_node->parent_pb_graph_node == NULL) { + if (tnode[i].pb_graph_pin->port->type == IN_PORT) { + tnode[i].type = TN_CB_IPIN; + } else { + assert(tnode[i].pb_graph_pin->port->type == OUT_PORT); + tnode[i].type = TN_CB_OPIN; + } + } else { + tnode[i].type = TN_INTERMEDIATE_NODE; + } + } else { + if (tnode[i].pb_graph_pin->type == PB_PIN_INPAD) { + assert(tnode[i].pb_graph_pin->port->type == OUT_PORT); + tnode[i].type = TN_INPAD_OPIN; + tnode[i + 1].num_edges = 1; + tnode[i + 1].out_edges = (t_tedge *) my_chunk_malloc( + 1 * sizeof(t_tedge), &tedge_ch); + tnode[i + 1].out_edges->Tdel = 0; + tnode[i + 1].out_edges->to_node = i; + tnode[i + 1].pb_graph_pin = pb_graph_pin; /* Necessary for propagate_clock_domain_and_skew(). */ + tnode[i + 1].type = TN_INPAD_SOURCE; + tnode[i + 1].block = iblock; + (*inode)++; + } else if (tnode[i].pb_graph_pin->type == PB_PIN_OUTPAD) { + assert(tnode[i].pb_graph_pin->port->type == IN_PORT); + tnode[i].type = TN_OUTPAD_IPIN; + tnode[i].num_edges = 1; + tnode[i].out_edges = (t_tedge *) my_chunk_malloc( + 1 * sizeof(t_tedge), &tedge_ch); + tnode[i].out_edges->Tdel = 0; + tnode[i].out_edges->to_node = i + 1; + tnode[i + 1].pb_graph_pin = pb_graph_pin; /* Necessary for find_tnode_net_name(). */ + tnode[i + 1].type = TN_OUTPAD_SINK; + tnode[i + 1].block = iblock; + tnode[i + 1].num_edges = 0; + tnode[i + 1].out_edges = NULL; + (*inode)++; + } else if (tnode[i].pb_graph_pin->type == PB_PIN_SEQUENTIAL) { + if (tnode[i].pb_graph_pin->port->type == IN_PORT) { + tnode[i].type = TN_FF_IPIN; + tnode[i].num_edges = 1; + tnode[i].out_edges = (t_tedge *) my_chunk_malloc( + 1 * sizeof(t_tedge), &tedge_ch); + tnode[i].out_edges->Tdel = pb_graph_pin->tsu_tco; + tnode[i].out_edges->to_node = i + 1; + tnode[i + 1].pb_graph_pin = pb_graph_pin; + tnode[i + 1].type = TN_FF_SINK; + tnode[i + 1].block = iblock; + tnode[i + 1].num_edges = 0; + tnode[i + 1].out_edges = NULL; + } else { + assert(tnode[i].pb_graph_pin->port->type == OUT_PORT); + tnode[i].type = TN_FF_OPIN; + tnode[i + 1].num_edges = 1; + tnode[i + 1].out_edges = (t_tedge *) my_chunk_malloc( + 1 * sizeof(t_tedge), &tedge_ch); + tnode[i + 1].out_edges->Tdel = pb_graph_pin->tsu_tco; + tnode[i + 1].out_edges->to_node = i; + tnode[i + 1].pb_graph_pin = pb_graph_pin; + tnode[i + 1].type = TN_FF_SOURCE; + tnode[i + 1].block = iblock; + } + (*inode)++; + } else if (tnode[i].pb_graph_pin->type == PB_PIN_CLOCK) { + tnode[i].type = TN_FF_CLOCK; + tnode[i].num_edges = 0; + tnode[i].out_edges = NULL; + } else { + if (tnode[i].pb_graph_pin->port->type == IN_PORT) { + assert(tnode[i].pb_graph_pin->type == PB_PIN_TERMINAL); + tnode[i].type = TN_PRIMITIVE_IPIN; + } else { + assert(tnode[i].pb_graph_pin->port->type == OUT_PORT); + assert(tnode[i].pb_graph_pin->type == PB_PIN_TERMINAL); + tnode[i].type = TN_PRIMITIVE_OPIN; + } + } + } + (*inode)++; +} + +void print_timing_graph(const char *fname) { + + /* Prints the timing graph into a file. */ + + FILE *fp; + int inode, iedge, ilevel, i; + t_tedge *tedge; + e_tnode_type itype; + const char *tnode_type_names[] = { "TN_INPAD_SOURCE", "TN_INPAD_OPIN", "TN_OUTPAD_IPIN", + + "TN_OUTPAD_SINK", "TN_CB_IPIN", "TN_CB_OPIN", "TN_INTERMEDIATE_NODE", + "TN_PRIMITIVE_IPIN", "TN_PRIMITIVE_OPIN", "TN_FF_IPIN", "TN_FF_OPIN", "TN_FF_SINK", + "TN_FF_SOURCE", "TN_FF_CLOCK", "TN_CONSTANT_GEN_SOURCE" }; + + fp = my_fopen(fname, "w", 0); + + fprintf(fp, "num_tnodes: %d\n", num_tnodes); + fprintf(fp, "Node #\tType\t\tipin\tiblk\tDomain\tSkew\tI/O Delay\t# edges\t" + "to_node Tdel\n\n"); + + for (inode = 0; inode < num_tnodes; inode++) { + fprintf(fp, "%d\t", inode); + + itype = tnode[inode].type; + fprintf(fp, "%-15.15s\t", tnode_type_names[itype]); + + if (tnode[inode].pb_graph_pin != NULL) { + fprintf(fp, "%d\t%d\t", + tnode[inode].pb_graph_pin->pin_count_in_cluster, + tnode[inode].block); + } else { + fprintf(fp, "\t%d\t", tnode[inode].block); + } + + if (itype == TN_FF_CLOCK || itype == TN_FF_SOURCE || itype == TN_FF_SINK) { + fprintf(fp, "%d\t%.3e\t\t", tnode[inode].clock_domain, tnode[inode].clock_delay); + } else if (itype == TN_INPAD_SOURCE) { + fprintf(fp, "%d\t\t%.3e\t", tnode[inode].clock_domain, tnode[inode].out_edges[0].Tdel); + } else if (itype == TN_OUTPAD_SINK) { + assert(tnode[inode-1].type == TN_OUTPAD_IPIN); /* Outpad ipins should be one prior in the tnode array */ + fprintf(fp, "%d\t\t%.3e\t", tnode[inode].clock_domain, tnode[inode-1].out_edges[0].Tdel); + } else { + fprintf(fp, "\t\t\t\t"); + } + + fprintf(fp, "%d", tnode[inode].num_edges); + + /* Print all edges after edge 0 on separate lines */ + tedge = tnode[inode].out_edges; + if (tnode[inode].num_edges > 0) { + fprintf(fp, "\t%4d\t%7.3g", tedge[0].to_node, tedge[0].Tdel); + for (iedge = 1; iedge < tnode[inode].num_edges; iedge++) { + fprintf(fp, "\n\t\t\t\t\t\t\t\t\t\t%4d\t%7.3g", tedge[iedge].to_node, tedge[iedge].Tdel); + } + } + fprintf(fp, "\n"); + } + + fprintf(fp, "\n\nnum_tnode_levels: %d\n", num_tnode_levels); + + for (ilevel = 0; ilevel < num_tnode_levels; ilevel++) { + fprintf(fp, "\n\nLevel: %d Num_nodes: %d\nNodes:", ilevel, + tnodes_at_level[ilevel].nelem); + for (i = 0; i < tnodes_at_level[ilevel].nelem; i++) + fprintf(fp, "\t%d", tnodes_at_level[ilevel].list[i]); + } + + fprintf(fp, "\n"); + fprintf(fp, "\n\nNet #\tNet_to_driver_tnode\n"); + + for (i = 0; i < num_nets; i++) + fprintf(fp, "%4d\t%6d\n", i, f_net_to_driver_tnode[i]); + + if (g_sdc->num_constrained_clocks == 1) { + /* Arrival and required times, and forward and backward weights, will be meaningless for multiclock + designs, since the values currently on the graph will only correspond to the most recent traversal. */ + fprintf(fp, "\n\nNode #\t\tT_arr\t\tT_req" +#ifdef PATH_COUNTING + "\tForward weight\tBackward weight" +#endif + "\n\n"); + + for (inode = 0; inode < num_tnodes; inode++) { + if (tnode[inode].T_arr > HUGE_NEGATIVE_FLOAT + 1) { + fprintf(fp, "%d\t%12g", inode, tnode[inode].T_arr); + } else { + fprintf(fp, "%d\t\t -", inode); + } + if (tnode[inode].T_req < HUGE_POSITIVE_FLOAT - 1) { + fprintf(fp, "\t%12g", tnode[inode].T_req); + } else { + fprintf(fp, "\t\t -"); + } +#ifdef PATH_COUNTING + fprintf(fp, "\t%12g\t%12g\n", tnode[inode].forward_weight, tnode[inode].backward_weight); +#endif + } + } + + fclose(fp); +} +static void process_constraints(void) { + /* Removes all constraints between domains which never intersect. We need to do this + so that criticality_denom in do_timing_analysis is not affected by unused constraints. + BFS through the levelized graph once for each source domain. Whenever we get to a sink, + mark off that we've used that sink clock domain. After each traversal, set all unused + constraints to DO_NOT_ANALYSE. + + Also, print g_sdc->domain_constraints, constrained I/Os and override constraints, + and convert g_sdc->domain_constraints and flip-flop-level override constraints + to be in seconds rather than nanoseconds. We don't need to normalize g_sdc->cc_constraints + because they're already on the g_sdc->domain_constraints matrix, and we don't need + to normalize constrained_ios because we already did the normalization when + we put the delays onto the timing graph in load_clock_domain_and_clock_and_io_delay. */ + + int source_clock_domain, sink_clock_domain, inode, ilevel, num_at_level, i, + num_edges, iedge, to_node, icf, ifc, iff; + t_tedge * tedge; + float constraint; + boolean * constraint_used = (boolean *) my_malloc(g_sdc->num_constrained_clocks * sizeof(boolean)); + + for (source_clock_domain = 0; source_clock_domain < g_sdc->num_constrained_clocks; source_clock_domain++) { + /* We're going to use arrival time to flag which nodes we've reached, + even though the values we put in will not correspond to actual arrival times. + Nodes which are reached on this traversal will get an arrival time of 0. + Reset arrival times now to an invalid number. */ + for (inode = 0; inode < num_tnodes; inode++) { + tnode[inode].T_arr = HUGE_NEGATIVE_FLOAT; + } + + /* Reset all constraint_used entries. */ + for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { + constraint_used[sink_clock_domain] = FALSE; + } + + /* Set arrival times for each top-level tnode on this clock domain. */ + num_at_level = tnodes_at_level[0].nelem; + for (i = 0; i < num_at_level; i++) { + inode = tnodes_at_level[0].list[i]; + if (tnode[inode].clock_domain == source_clock_domain) { + tnode[inode].T_arr = 0.; + } + } + + for (ilevel = 0; ilevel < num_tnode_levels; ilevel++) { /* Go down one level at a time. */ + num_at_level = tnodes_at_level[ilevel].nelem; + + for (i = 0; i < num_at_level; i++) { + inode = tnodes_at_level[ilevel].list[i]; /* Go through each of the tnodes at the level we're on. */ + if (has_valid_T_arr(inode)) { /* If this tnode has been used */ + num_edges = tnode[inode].num_edges; + if (num_edges == 0) { /* sink */ + /* We've reached the sink domain of this tnode, so set constraint_used + to true for this tnode's clock domain (if it has a valid one). */ + sink_clock_domain = tnode[inode].clock_domain; + if (sink_clock_domain != -1) { + constraint_used[sink_clock_domain] = TRUE; + } + } else { + /* Set arrival time to a valid value (0.) for each tnode in this tnode's fanout. */ + tedge = tnode[inode].out_edges; + for (iedge = 0; iedge < num_edges; iedge++) { + to_node = tedge[iedge].to_node; + tnode[to_node].T_arr = 0.; + } + } + } + } + } + + /* At the end of the source domain traversal, see which sink domains haven't been hit, + and set the constraint for the pair of source and sink domains to DO_NOT_ANALYSE */ + + for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { + if (!constraint_used[sink_clock_domain]) { + g_sdc->domain_constraint[source_clock_domain][sink_clock_domain] = DO_NOT_ANALYSE; + } + } + } + + free(constraint_used); + + /* Print constraints */ + if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_TIMING_CONSTRAINTS)) { + print_timing_constraint_info(getEchoFileName(E_ECHO_TIMING_CONSTRAINTS)); + } + + /* Convert g_sdc->domain_constraint and ff-level override constraints to be in seconds, not nanoseconds. */ + for (source_clock_domain = 0; source_clock_domain < g_sdc->num_constrained_clocks; source_clock_domain++) { + for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { + constraint = g_sdc->domain_constraint[source_clock_domain][sink_clock_domain]; + if (constraint > NEGATIVE_EPSILON) { /* if constraint does not equal DO_NOT_ANALYSE */ + g_sdc->domain_constraint[source_clock_domain][sink_clock_domain] = constraint * 1e-9; + } + } + } + for (icf = 0; icf < g_sdc->num_cf_constraints; icf++) { + g_sdc->cf_constraints[icf].constraint *= 1e-9; + } + for (ifc = 0; ifc < g_sdc->num_fc_constraints; ifc++) { + g_sdc->fc_constraints[ifc].constraint *= 1e-9; + } + for (iff = 0; iff < g_sdc->num_ff_constraints; iff++) { + g_sdc->ff_constraints[iff].constraint *= 1e-9; + } + + /* Finally, free g_sdc->cc_constraints since all of its info is contained in g_sdc->domain_constraint. */ + free_override_constraint(g_sdc->cc_constraints, g_sdc->num_cc_constraints); +} + +static void alloc_timing_stats(void) { + + /* Allocate f_timing_stats data structure. */ + + int i; + + f_timing_stats = (t_timing_stats *) my_malloc(sizeof(t_timing_stats)); + f_timing_stats->cpd = (float **) my_malloc(g_sdc->num_constrained_clocks * sizeof(float *)); + f_timing_stats->least_slack = (float **) my_malloc(g_sdc->num_constrained_clocks * sizeof(float *)); + for (i = 0; i < g_sdc->num_constrained_clocks; i++) { + f_timing_stats->cpd[i] = (float *) my_malloc(g_sdc->num_constrained_clocks * sizeof(float)); + f_timing_stats->least_slack[i] = (float *) my_malloc(g_sdc->num_constrained_clocks * sizeof(float)); + } +} + +void do_timing_analysis(t_slack * slacks, boolean is_prepacked, boolean do_lut_input_balancing, boolean is_final_analysis) { + +/* Performs timing analysis on the circuit. Before this routine is called, t_slack * slacks + must have been allocated, and the circuit must have been converted into a timing graph. + The nodes of the timing graph represent pins and the edges between them represent delays + and m dependencies from one pin to another. Most elements are modeled as a pair of nodes so + that the delay through the element can be marked on the edge between them (e.g. + TN_INPAD_SOURCE->TN_INPAD_OPIN, TN_OUTPAD_IPIN->TN_OUTPAD_SINK, TN_PRIMITIVE_OPIN-> + TN_PRIMITIVE_OPIN, etc.). + + The timing graph nodes are stored as an array, tnode [0..num_tnodes - 1]. Each tnode + includes an array of all edges, tedge, which fan out from it. Each tedge includes the + index of the node on its far end (in the tnode array), and the delay to that node. + + The timing graph has sources at each TN_FF_SOURCE (Q output), TN_INPAD_SOURCE (input I/O pad) + and TN_CONSTANT_GEN_SOURCE (constant 1 or 0 generator) node and sinks at TN_FF_SINK (D input) + and TN_OUTPAD_SINK (output I/O pad) nodes. Two traversals, one forward (sources to sinks) + and one backward, are performed for each valid constraint (one which is not DO_NOT_ANALYSE) + between a source and a sink clock domain in the matrix g_sdc->domain_constraint + [0..g_sdc->num_constrained_clocks - 1][0..g_sdc->num_constrained_clocks - 1]. This matrix has been + pruned so that all domain pairs with no paths between them have been set to DO_NOT_ANALYSE. + + During the traversal pair for each constraint, all nodes in the fanout of sources on the + source clock domain are assigned a T_arr, the arrival time of the last input signal to the node. + All nodes in the fanin of sinks on the sink clock domain are assigned a T_req, the required + arrival time of the last input signal to the node if the critical path for this constraint is + not to be lengthened. Nodes which receive both a valid T_arr and T_req are flagged with + used_on_this_traversal, and nodes which are used on at least one traversal pair are flagged + with has_valid_slack so that later functions know the slack is valid. + + After each traversal pair, a slack is calculated for each sink pin on each net (or equivalently, + each connection or tedge fanning out from that net's driver tnode). Slack is calculated as: + T_req (dest node) - T_arr (source node) - Tdel (edge) + and represents the amount of delay which could be added to this connection before the critical + path delay for this constraint would worsen. Edges on the critical path have a slack of 0. + Slacks which are never used are set to HUGE_POSITIVE_FLOAT. + + The optimizers actually use a metric called timing_criticality. Timing criticality is defined + as 1 - slack / criticality_denom, where the normalization factor criticality_denom is the max + of all arrival times in the constraint and the constraint itself (T_req-relaxed slacks) or + all arrival times and constraints in the design (shifted slacks). See below for a further + discussion of these two regimes. Timing criticality is always between 0 (not critical) and 1 + (very critical). Unlike slack, which is set to HUGE_POSITIVE_FLOAT for unanalysed connections, + timing criticality is 0 for these, meaning no special check has to be made for which connections + have been analysed. + + If path counting is on (PATH_COUNTING is defined in vpr_types.h), the optimizers use a weighted + sum of timing_criticality and path_criticality, the latter of which is an estimate of the + importance of the number of paths using a particular connection. As a path's timing_criticality + decreases, it will become exponentially less important to the path_criticality of any connection + which this path uses. Path criticality also goes from 0 (not critical or unanalysed) to 1. + + Slack and criticalities are only calculated if both the driver of the net and the sink pin were + used_on_this_traversal, and are only overwritten if lower than previously-obtained values. + The optimizers actually use criticality rather than slack, but slack is useful for human + designers and so we calculate it only if we need to print it. + + This routine outputs slack and criticality to t_slack * slacks. It also stores least slack and + critical path delay per constraint [0..g_sdc->num_constrained_clocks - 1][0..g_sdc->num_constrained_clocks - 1] + in the file-scope variable f_timing_stats. + + Is_prepacked flags whether to calculate normalized costs for the clusterer (normalized_slack, + normalized_Tarr, normalized_total_critical_paths). Setting this to FALSE saves time in post- + packed timing analyses. + + Do_lut_input_balancing flags whether to rebalance LUT inputs. LUT rebalancing takes advantage of + the fact that different LUT inputs often have different delays. Since we can freely permute which + LUT inputs are used by just changing the logic in the LUT, these LUT permutations can be performed + late into the routing stage of the flow. + + Is_final_analysis flags whether this is the final, analysis pass. If it is, the analyser will + compute actual slacks instead of relaxed ones. We "relax" slacks by setting the required time to + the maximum arrival time for tight constraints so that no slacks are negative (which confuses + the optimizers). This is called "T_req-relaxed" slack. However, human designers want to see + actual slack values, so we report those in the final analysis. The alternative way of making + slacks positive is shifting them upwards by the value of the largest negative slack, after + all traversals are complete ("shifted slacks"), which can be enabled by changing SLACK_DEFINITION + from 'R' to 'S' in path_delay.h. + + To do: flip-flop to flip-flop and flip-flop to clock domain constraints (set_false_path, set_max_delay, + and especially set_multicycle_path). All the info for these constraints is contained in g_sdc->fc_constraints and + g_sdc->ff_constraints, but graph traversals are not included yet. Probably, an entire traversal will be needed for + each constraint. Clock domain to flip-flop constraints are coded but not tested, and are done within + existing traversals. */ + + int i, j, source_clock_domain, sink_clock_domain, inode, inet, ipin; + +#if defined PATH_COUNTING || SLACK_DEFINITION == 'S' + int iedge, num_edges; +#endif + +#ifdef PATH_COUNTING + float max_path_criticality = HUGE_NEGATIVE_FLOAT /* used to normalize path_criticalities */; +#endif + + boolean update_slack = (boolean) (is_final_analysis || getEchoEnabled()); + /* Only update slack values if we need to print it, i.e. + for the final output file (is_final_analysis) or echo files. */ + + float criticality_denom; /* (SLACK_DEFINITION == 'R' only) For a particular constraint, the maximum of + the constraint and all arrival times for the constraint's traversal. Used to + normalize the clusterer's normalized_slack and, more importantly, criticality. */ + + long max_critical_output_paths, max_critical_input_paths; + t_pb *pb; + +#if SLACK_DEFINITION == 'S' + float smallest_slack_in_design = HUGE_POSITIVE_FLOAT; + /* Shift all slacks upwards by this number if it is negative. */ + + float criticality_denom_global = HUGE_NEGATIVE_FLOAT; + /* Denominator of criticality for shifted - max of all arrival times and all constraints. */ +#endif + + /* Reset LUT input rebalancing. */ + for (inode = 0; inode < num_tnodes; inode++) { + if (tnode[inode].type == TN_PRIMITIVE_OPIN && tnode[inode].pb_graph_pin != NULL) { + pb = block[tnode[inode].block].pb->rr_node_to_pb_mapping[tnode[inode].pb_graph_pin->pin_count_in_cluster]; + if (pb != NULL && pb->lut_pin_remap != NULL) { + /* this is a LUT primitive, do pin swapping */ + assert(pb->pb_graph_node->pb_type->num_output_pins == 1 && pb->pb_graph_node->pb_type->num_clock_pins == 0); /* ensure LUT properties are valid */ + assert(pb->pb_graph_node->num_input_ports == 1); + /* If all input pins are known, perform LUT input delay rebalancing, do nothing otherwise */ + for (i = 0; i < pb->pb_graph_node->num_input_pins[0]; i++) { + pb->lut_pin_remap[i] = OPEN; + } + } + } + } + + /* Reset all values which need to be reset once per + timing analysis, rather than once per traversal pair. */ + + /* Reset slack and criticality */ + for (inet = 0; inet < num_timing_nets; inet++) { + for (ipin = 1; ipin <= timing_nets[inet].num_sinks; ipin++) { + slacks->slack[inet][ipin] = HUGE_POSITIVE_FLOAT; + slacks->timing_criticality[inet][ipin] = 0.; +#ifdef PATH_COUNTING + slacks->path_criticality[inet][ipin] = 0.; +#endif + } + } + + /* Reset f_timing_stats. */ + for (i = 0; i < g_sdc->num_constrained_clocks; i++) { + for (j = 0; j < g_sdc->num_constrained_clocks; j++) { + f_timing_stats->cpd[i][j] = HUGE_NEGATIVE_FLOAT; + f_timing_stats->least_slack[i][j] = HUGE_POSITIVE_FLOAT; + } + } + +#ifndef PATH_COUNTING + /* Reset normalized values for clusterer. */ + if (is_prepacked) { + for (inode = 0; inode < num_tnodes; inode++) { + tnode[inode].prepacked_data->normalized_slack = HUGE_POSITIVE_FLOAT; + tnode[inode].prepacked_data->normalized_T_arr = HUGE_NEGATIVE_FLOAT; + tnode[inode].prepacked_data->normalized_total_critical_paths = HUGE_NEGATIVE_FLOAT; + } + } +#endif + + if (do_lut_input_balancing) { + do_lut_rebalancing(); + } + + /* For each valid constraint (pair of source and sink clock domains), we do one + forward and one backward topological traversal to find arrival and required times, + in do_timing_analysis_for_constraint. If path counting is on, we then do another, + simpler traversal to find forward and backward weights, relying on the largest + required time we found from the first traversal. After each constraint's traversals, + we update the slacks, timing criticalities and (if necessary) path criticalities or + normalized costs used by the clusterer. */ + + for (source_clock_domain = 0; source_clock_domain < g_sdc->num_constrained_clocks; source_clock_domain++) { + for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { + if (g_sdc->domain_constraint[source_clock_domain][sink_clock_domain] > NEGATIVE_EPSILON) { /* i.e. != DO_NOT_ANALYSE */ + + /* Perform the forward and backward traversal for this constraint. */ + criticality_denom = do_timing_analysis_for_constraint(source_clock_domain, sink_clock_domain, + is_prepacked, is_final_analysis, &max_critical_input_paths, &max_critical_output_paths); +#ifdef PATH_COUNTING + /* Weight the importance of each net, used in slack calculation. */ + do_path_counting(criticality_denom); +#endif + + /* Update the slack and criticality for each edge of each net which was + analysed on the most recent traversal and has a lower (slack) or + higher (criticality) value than before. */ + update_slacks(slacks, source_clock_domain, sink_clock_domain, criticality_denom, update_slack); + +#ifndef PATH_COUNTING + /* Update the normalized costs used by the clusterer. */ + if (is_prepacked) { + update_normalized_costs(criticality_denom, max_critical_input_paths, max_critical_output_paths); + } +#endif + +#if SLACK_DEFINITION == 'S' + /* Set criticality_denom_global to the max of criticality_denom over all traversals. */ + criticality_denom_global = std::max(criticality_denom_global, criticality_denom); +#endif + } + } + } + +#ifdef PATH_COUNTING + /* Normalize path criticalities by the largest value in the + circuit. Otherwise, path criticalities would be unbounded. */ + + for (inet = 0; inet < num_timing_nets; inet++) { + num_edges = timing_nets[inet].num_sinks; + for (iedge = 0; iedge < num_edges; iedge++) { + max_path_criticality = std::max(max_path_criticality, slacks->path_criticality[inet][iedge + 1]); + } + } + + for (inet = 0; inet < num_timing_nets; inet++) { + num_edges = timing_nets[inet].num_sinks; + for (iedge = 0; iedge < num_edges; iedge++) { + slacks->path_criticality[inet][iedge + 1] /= max_path_criticality; + } + } + +#endif + +#if SLACK_DEFINITION == 'S' + if (!is_final_analysis) { + + /* Find the smallest slack in the design. */ + for (i = 0; i < g_sdc->num_constrained_clocks; i++) { + for (j = 0; j < g_sdc->num_constrained_clocks; j++) { + smallest_slack_in_design = std::min(smallest_slack_in_design, f_timing_stats->least_slack[i][j]); + } + } + + /* Increase all slacks by the value of the smallest slack in the design, if it's negative. */ + if (smallest_slack_in_design < 0) { + for (inet = 0; inet < num_timing_nets; inet++) { + num_edges = timing_nets[inet].num_sinks; + for (iedge = 0; iedge < num_edges; iedge++) { + slacks->slack[inet][iedge + 1] -= smallest_slack_in_design; + /* Remember, smallest_slack_in_design is negative, so we're INCREASING all the slacks. */ + /* Note that if slack was equal to HUGE_POSITIVE_FLOAT, it will still be equal to more than this, + so it will still be ignored when we calculate criticalities. */ + } + } + } + } + + /* We can now calculate criticalities, only after we normalize slacks. */ + for (inet = 0; inet < num_timing_nets; inet++) { + num_edges = timing_nets[inet].num_sinks; + for (iedge = 0; iedge < num_edges; iedge++) { + if (slacks->slack[inet][iedge + 1] < HUGE_POSITIVE_FLOAT - 1) { /* if the slack is valid */ + slacks->timing_criticality[inet][iedge + 1] = 1 - slacks->slack[inet][iedge + 1]/criticality_denom_global; + } + /* otherwise, criticality remains 0, as it was initialized */ + } + } +#endif +} + +static void do_lut_rebalancing() { + + int inode, num_at_level, i, ilevel, num_edges, iedge, to_node; + t_tedge * tedge; + + /* Reset all arrival times to a very large negative number. */ + for (inode = 0; inode < num_tnodes; inode++) { + tnode[inode].T_arr = HUGE_NEGATIVE_FLOAT; + } + + /* Set arrival times for each top-level tnode. */ + num_at_level = tnodes_at_level[0].nelem; + for (i = 0; i < num_at_level; i++) { + inode = tnodes_at_level[0].list[i]; + if (tnode[inode].type == TN_FF_SOURCE) { + /* Set the arrival time of this flip-flop tnode to its clock skew. */ + tnode[inode].T_arr = tnode[inode].clock_delay; + } else if (tnode[inode].type == TN_INPAD_SOURCE) { + /* There's no such thing as clock skew for external clocks. The closest equivalent, + input delay, is already marked on the edge coming out from this node. + As a result, the signal can be said to arrive at t = 0. */ + tnode[inode].T_arr = 0.; + } + } + + /* Now we actually start the forward topological traversal, to compute arrival times. */ + for (ilevel = 0; ilevel < num_tnode_levels; ilevel++) { /* For each level of our levelized timing graph... */ + num_at_level = tnodes_at_level[ilevel].nelem; /* ...there are num_at_level tnodes at that level. */ + + for (i = 0; i < num_at_level; i++) { + inode = tnodes_at_level[ilevel].list[i]; /* Go through each of the tnodes at the level we're on. */ + + num_edges = tnode[inode].num_edges; /* Get the number of edges fanning out from the node we're visiting */ + tedge = tnode[inode].out_edges; /* Get the list of edges from the node we're visiting */ + + for (iedge = 0; iedge < num_edges; iedge++) { /* Now go through each edge coming out from this tnode */ + to_node = tedge[iedge].to_node; /* Get the index of the destination tnode of this edge. */ + + /* The arrival time T_arr at the destination node is set to the maximum of all the + possible arrival times from all edges fanning in to the node. + The arrival time represents the latest time that all inputs must arrive at a node. + LUT input rebalancing also occurs at this step. */ + set_and_balance_arrival_time(to_node, inode, tedge[iedge].Tdel, TRUE); + } + } + } +} + + +static float do_timing_analysis_for_constraint(int source_clock_domain, int sink_clock_domain, + boolean is_prepacked, boolean is_final_analysis, long * max_critical_input_paths_ptr, + long * max_critical_output_paths_ptr) { + + /* Performs a single forward and backward traversal for the domain pair + source_clock_domain and sink_clock_domain. Returns the denominator that + will be later used to normalize criticality - the maximum of all arrival + times from this traversal and the constraint for this pair of domains. + Also returns the maximum number of critical input and output paths of any + node analysed for this constraint, passed by reference from do_timing_analysis. */ + + int inode, num_at_level, i, total, ilevel, num_edges, iedge, to_node, icf; + float constraint, Tdel, T_req, max_Tarr = HUGE_NEGATIVE_FLOAT; + /* Max of all arrival times for this constraint - + used to relax required times. */ + t_tedge * tedge; + int num_dangling_nodes; + boolean found; + long max_critical_input_paths = 0, max_critical_output_paths = 0; + + /* Reset all values which need to be reset once per + traversal pair, rather than once per timing analysis. */ + + /* Reset all arrival and required times. */ + for (inode = 0; inode < num_tnodes; inode++) { + tnode[inode].T_arr = HUGE_NEGATIVE_FLOAT; + tnode[inode].T_req = HUGE_POSITIVE_FLOAT; + } + +#ifndef PATH_COUNTING + /* Reset num_critical_output_paths. */ + if (is_prepacked) { + for (inode = 0; inode < num_tnodes; inode++) { + tnode[inode].prepacked_data->num_critical_output_paths = 0; + } + } +#endif + + /* Set arrival times for each top-level tnode on this source domain. */ + num_at_level = tnodes_at_level[0].nelem; + for (i = 0; i < num_at_level; i++) { + inode = tnodes_at_level[0].list[i]; + + if (tnode[inode].clock_domain == source_clock_domain) { + + if (tnode[inode].type == TN_FF_SOURCE) { + /* Set the arrival time of this flip-flop tnode to its clock skew. */ + tnode[inode].T_arr = tnode[inode].clock_delay; + + } else if (tnode[inode].type == TN_INPAD_SOURCE) { + /* There's no such thing as clock skew for external clocks, and + input delay is already marked on the edge coming out from this node. + As a result, the signal can be said to arrive at t = 0. */ + tnode[inode].T_arr = 0.; + } + + } + } + + /* Compute arrival times with a forward topological traversal from sources + (TN_FF_SOURCE, TN_INPAD_SOURCE, TN_CONSTANT_GEN_SOURCE) to sinks (TN_FF_SINK, TN_OUTPAD_SINK). */ + + total = 0; /* We count up all tnodes to error-check at the end. */ + for (ilevel = 0; ilevel < num_tnode_levels; ilevel++) { /* For each level of our levelized timing graph... */ + num_at_level = tnodes_at_level[ilevel].nelem; /* ...there are num_at_level tnodes at that level. */ + total += num_at_level; + + for (i = 0; i < num_at_level; i++) { + inode = tnodes_at_level[ilevel].list[i]; /* Go through each of the tnodes at the level we're on. */ + if (tnode[inode].T_arr < NEGATIVE_EPSILON) { /* If the arrival time is less than 0 (i.e. HUGE_NEGATIVE_FLOAT)... */ + continue; /* End this iteration of the num_at_level for loop since + this node is not part of the clock domain we're analyzing. + (If it were, it would have received an arrival time already.) */ + } + + num_edges = tnode[inode].num_edges; /* Get the number of edges fanning out from the node we're visiting */ + tedge = tnode[inode].out_edges; /* Get the list of edges from the node we're visiting */ +#ifndef PATH_COUNTING + if (is_prepacked && ilevel == 0) { + tnode[inode].prepacked_data->num_critical_input_paths = 1; /* Top-level tnodes have one locally-critical input path. */ + } + + /* Using a somewhat convoluted procedure inherited from T-VPack, + count how many locally-critical input paths fan into each tnode, + and also find the maximum number over all tnodes. */ + if (is_prepacked) { + for (iedge = 0; iedge < num_edges; iedge++) { + to_node = tedge[iedge].to_node; + if (fabs(tnode[to_node].T_arr - (tnode[inode].T_arr + tedge[iedge].Tdel)) < EPSILON) { + /* If the "local forward slack" (T_arr(to_node) - T_arr(inode) - T_del) for this edge + is 0 (i.e. the path from inode to to_node is locally as critical as any other path to + to_node), add to_node's num critical input paths to inode's number. */ + tnode[to_node].prepacked_data->num_critical_input_paths += tnode[inode].prepacked_data->num_critical_input_paths; + } else if (tnode[to_node].T_arr < (tnode[inode].T_arr + tedge[iedge].Tdel)) { + /* If the "local forward slack" for this edge is negative, + reset to_node's num critical input paths to inode's number. */ + tnode[to_node].prepacked_data->num_critical_input_paths = tnode[inode].prepacked_data->num_critical_input_paths; + } + /* Set max_critical_input_paths to the maximum number of critical + input paths for all tnodes analysed on this traversal. */ + if (tnode[to_node].prepacked_data->num_critical_input_paths > max_critical_input_paths) { + max_critical_input_paths = tnode[to_node].prepacked_data->num_critical_input_paths; + } + } + } +#endif + for (iedge = 0; iedge < num_edges; iedge++) { /* Now go through each edge coming out from this tnode */ + to_node = tedge[iedge].to_node; /* Get the index of the destination tnode of this edge. */ + + /* The arrival time T_arr at the destination node is set to the maximum of all + the possible arrival times from all edges fanning in to the node. The arrival + time represents the latest time that all inputs must arrive at a node. LUT input + rebalancing also occurs at this step. */ + set_and_balance_arrival_time(to_node, inode, tedge[iedge].Tdel, FALSE); + + /* Since we updated the destination node (to_node), change the max arrival + time for the forward traversal if to_node's arrival time is greater than + the existing maximum. */ + max_Tarr = std::max(max_Tarr, tnode[to_node].T_arr); + } + } + } + + assert(total == num_tnodes); + num_dangling_nodes = 0; + /* Compute required times with a backward topological traversal from sinks to sources. */ + + for (ilevel = num_tnode_levels - 1; ilevel >= 0; ilevel--) { + num_at_level = tnodes_at_level[ilevel].nelem; + + for (i = 0; i < num_at_level; i++) { + inode = tnodes_at_level[ilevel].list[i]; + num_edges = tnode[inode].num_edges; + + if (ilevel == 0) { + if (!(tnode[inode].type == TN_INPAD_SOURCE || tnode[inode].type == TN_FF_SOURCE || tnode[inode].type == TN_CONSTANT_GEN_SOURCE)) { + vpr_printf(TIO_MESSAGE_ERROR, "Timing graph started on unexpected node %s.%s[%d].\n", + tnode[inode].pb_graph_pin->parent_node->pb_type->name, + tnode[inode].pb_graph_pin->port->name, + tnode[inode].pb_graph_pin->pin_number); + vpr_printf(TIO_MESSAGE_ERROR, "This is a VPR internal error, contact VPR development team.\n"); + exit(1); + } + } else { + if ((tnode[inode].type == TN_INPAD_SOURCE || tnode[inode].type == TN_FF_SOURCE || tnode[inode].type == TN_CONSTANT_GEN_SOURCE)) { + vpr_printf(TIO_MESSAGE_ERROR, "Timing graph discovered unexpected edge to node %s.%s[%d].\n", + tnode[inode].pb_graph_pin->parent_node->pb_type->name, + tnode[inode].pb_graph_pin->port->name, + tnode[inode].pb_graph_pin->pin_number); + vpr_printf(TIO_MESSAGE_ERROR, "This is a VPR internal error, contact VPR development team.\n"); + exit(1); + } + } + + /* Unlike the forward traversal, the sinks are all on different levels, so we always have to + check whether a node is a sink. We give every sink on the sink clock domain we're considering + a valid required time. Every non-sink node in the fanin of one of these sinks and the fanout of + some source from the forward traversal also gets a valid required time. */ + + if (num_edges == 0) { /* sink */ + + if (tnode[inode].type == TN_FF_CLOCK || tnode[inode].T_arr < HUGE_NEGATIVE_FLOAT + 1) { + continue; /* Skip nodes on the clock net itself, and nodes with unset arrival times. */ + } + + if (!(tnode[inode].type == TN_OUTPAD_SINK || tnode[inode].type == TN_FF_SINK)) { + if(is_prepacked) { + vpr_printf(TIO_MESSAGE_WARNING, "Pin on block %s.%s[%d] not used\n", + logical_block[tnode[inode].block].name, + tnode[inode].prepacked_data->model_port_ptr->name, + tnode[inode].prepacked_data->model_pin); + } + num_dangling_nodes++; + /* Note: Still need to do standard traversals with dangling pins so that algorithm runs properly, but T_arr and T_Req to values such that it dangling nodes do not affect actual timing values */ + } + + /* Skip nodes not on the sink clock domain of the + constraint we're currently considering */ + if (tnode[inode].clock_domain != sink_clock_domain) { + continue; + } + + /* See if there's an override constraint between the source clock domain (name is + g_sdc->constrained_clocks[source_clock_domain].name) and the flip-flop or outpad we're at + now (name is find_tnode_net_name(inode, is_prepacked)). We test if + g_sdc->num_cf_constraints > 0 first so that we can save time looking up names in the vast + majority of cases where there are no such constraints. */ + + if (g_sdc->num_cf_constraints > 0 && (icf = find_cf_constraint(g_sdc->constrained_clocks[source_clock_domain].name, find_tnode_net_name(inode, is_prepacked))) != -1) { + constraint = g_sdc->cf_constraints[icf].constraint; + if (constraint < NEGATIVE_EPSILON) { + /* Constraint is DO_NOT_ANALYSE (-1) for this particular sink. */ + continue; + } + } else { /* Use the default constraint from g_sdc->domain_constraint. */ + constraint = g_sdc->domain_constraint[source_clock_domain][sink_clock_domain]; + /* Constraint is guaranteed to be valid since we checked for it at the very beginning. */ + } + + /* Now we know we should analyse this tnode. */ + +#if SLACK_DEFINITION == 'R' + /* Assign the required time T_req for this leaf node, taking into account clock skew. T_req is the + time all inputs to a tnode must arrive by before it would degrade this constraint's critical path delay. + + Relax the required time at the sink node to be non-negative by taking the max of the "real" required + time (constraint + tnode[inode].clock_delay) and the max arrival time in this domain (max_Tarr), except + for the final analysis where we report actual slack. We do this to prevent any slacks from being + negative, since negative slacks are not used effectively by the optimizers. + + E.g. if we have a 10 ns constraint and it takes 14 ns to get here, we'll have a slack of at most -4 ns + for any edge along the path that got us here. If we say the required time is 14 ns (no less than the + arrival time), we don't have a negative slack anymore. However, in the final timing analysis, the real + slacks are computed (that's what human designers care about), not the relaxed ones. */ + + if (is_final_analysis) { + tnode[inode].T_req = constraint + tnode[inode].clock_delay; + } else { + tnode[inode].T_req = std::max(constraint + tnode[inode].clock_delay, max_Tarr); + } +#else + /* Don't do the relaxation and always set T_req equal to the "real" required time. */ + tnode[inode].T_req = constraint + tnode[inode].clock_delay; +#endif + + /* Store the largest critical path delay for this constraint (source domain AND sink domain) + in the matrix critical_path_delay. C.P.D. = T_arr at destination - clock skew at destination + = (datapath delay + clock delay to source) - clock delay to destination. + + Critical path delay is really telling us how fast we can run the source clock before we can no + longer meet this constraint. e.g. If the datapath delay is 10 ns, the clock delay at source is + 2 ns and the clock delay at destination is 5 ns, then C.P.D. is 7 ns by the above formula. We + can run the source clock at 7 ns because the clock skew gives us 3 ns extra to meet the 10 ns + datapath delay. */ + + f_timing_stats->cpd[source_clock_domain][sink_clock_domain] = + std::max(f_timing_stats->cpd[source_clock_domain][sink_clock_domain], + (tnode[inode].T_arr - tnode[inode].clock_delay)); + +#ifndef PATH_COUNTING + if (is_prepacked) { + tnode[inode].prepacked_data->num_critical_output_paths = 1; /* Bottom-level tnodes have one locally-critical input path. */ + } +#endif + } else { /* not a sink */ + + assert(!(tnode[inode].type == TN_OUTPAD_SINK || tnode[inode].type == TN_FF_SINK || tnode[inode].type == TN_FF_CLOCK)); + + /* We need to skip this node unless it is on a path from source_clock_domain to + sink_clock_domain. We need to skip all nodes which: + 1. Fan out to the sink domain but do not fan in from the source domain. + 2. Fan in from the source domain but do not fan out to the sink domain. + 3. Do not fan in or out to either domain. + If a node does not fan in from the source domain, it will not have a valid arrival time. + So cases 1 and 3 can be skipped by continuing if T_arr = HUGE_NEGATIVE_FLOAT. We cannot + treat case 2 as simply since the required time for this node has not yet been assigned, + so we have to look at the required time for every node in its immediate fanout instead. */ + + /* Cases 1 and 3 */ + if (tnode[inode].T_arr < HUGE_NEGATIVE_FLOAT + 1) { + continue; /* Skip nodes with unset arrival times. */ + } + + /* Case 2 */ + found = FALSE; + tedge = tnode[inode].out_edges; + for (iedge = 0; iedge < num_edges && !found; iedge++) { + to_node = tedge[iedge].to_node; + if (tnode[to_node].T_req < HUGE_POSITIVE_FLOAT) { + found = TRUE; + } + } + if (!found) { + continue; + } + + /* Now we know this node is on a path from source_clock_domain to + sink_clock_domain, and needs to be analyzed. */ + + /* Opposite to T_arr, set T_req to the MINIMUM of the + required times of all edges fanning OUT from this node. */ + for (iedge = 0; iedge < num_edges; iedge++) { + to_node = tedge[iedge].to_node; + Tdel = tedge[iedge].Tdel; + T_req = tnode[to_node].T_req; + tnode[inode].T_req = std::min(tnode[inode].T_req, T_req - Tdel); + + /* Update least slack per constraint. This is NOT the same as the minimum slack we will + calculate on this traversal for post-packed netlists, which only count inter-cluster + slacks. We only look at edges adjacent to sink nodes on the sink clock domain since + all paths go through one of these edges. */ + if (tnode[to_node].num_edges == 0 && tnode[to_node].clock_domain == sink_clock_domain) { + f_timing_stats->least_slack[source_clock_domain][sink_clock_domain] = + std::min(f_timing_stats->least_slack[source_clock_domain][sink_clock_domain], + (T_req - Tdel - tnode[inode].T_arr)); + } + } +#ifndef PATH_COUNTING + + /* Similar to before, we count how many locally-critical output paths fan out from each tnode, + and also find the maximum number over all tnodes. Unlike for input paths, where we haven't set + the arrival time at to_node before analysing it, here the required time is set at both nodes, + so the "local backward slack" (T_req(to_node) - T_req(inode) - T_del) will never be negative. + Hence, we only have to test if the "local backward slack" is 0. */ + if (is_prepacked) { + for (iedge = 0; iedge < num_edges; iedge++) { + to_node = tedge[iedge].to_node; + /* If the "local backward slack" (T_arr(to_node) - T_arr(inode) - T_del) for this edge + is 0 (i.e. the path from inode to to_node is locally as critical as any other path to + to_node), add to_node's num critical output paths to inode's number. */ + if (fabs(tnode[to_node].T_req - (tnode[inode].T_req + tedge[iedge].Tdel)) < EPSILON) { + tnode[inode].prepacked_data->num_critical_output_paths += tnode[to_node].prepacked_data->num_critical_output_paths; + } + /* Set max_critical_output_paths to the maximum number of critical + output paths for all tnodes analysed on this traversal. */ + if (tnode[to_node].prepacked_data->num_critical_output_paths > max_critical_output_paths) { + max_critical_output_paths = tnode[to_node].prepacked_data->num_critical_output_paths; + } + } + } +#endif + } + } + } + + /* Return max critical input/output paths for this constraint through + the pointers we passed in. */ + if (max_critical_input_paths_ptr && max_critical_output_paths_ptr) { + *max_critical_input_paths_ptr = max_critical_input_paths; + *max_critical_output_paths_ptr = max_critical_output_paths; + } + + if(num_dangling_nodes > 0 && (is_final_analysis || is_prepacked)) { + vpr_printf(TIO_MESSAGE_WARNING, "%d unused pins \n", num_dangling_nodes); + } + + /* The criticality denominator is the maximum of the max + arrival time and the constraint for this domain pair. */ + return std::max(max_Tarr, g_sdc->domain_constraint[source_clock_domain][sink_clock_domain]); +} +#ifdef PATH_COUNTING +static void do_path_counting(float criticality_denom) { + /* Count the importance of the number of paths going through each net + by giving each net a forward and backward path weight. This is the first step of + "A Novel Net Weighting Algorithm for Timing-Driven Placement" (Kong, 2002). + We only visit nodes with set arrival and required times, so this function + must be called after do_timing_analysis_for_constraints, which sets T_arr and T_req. */ + + int inode, num_at_level, i, ilevel, num_edges, iedge, to_node; + t_tedge * tedge; + float forward_local_slack, backward_local_slack, discount; + + /* Reset forward and backward weights for all tnodes. */ + for (inode = 0; inode < num_tnodes; inode++) { + tnode[inode].forward_weight = 0; + tnode[inode].backward_weight = 0; + } + + /* Set foward weights for each top-level tnode. */ + num_at_level = tnodes_at_level[0].nelem; + for (i = 0; i < num_at_level; i++) { + inode = tnodes_at_level[0].list[i]; + tnode[inode].forward_weight = 1.; + } + + /* Do a forward topological traversal to populate forward weights. */ + for (ilevel = 0; ilevel < num_tnode_levels; ilevel++) { + num_at_level = tnodes_at_level[ilevel].nelem; + + for (i = 0; i < num_at_level; i++) { + inode = tnodes_at_level[ilevel].list[i]; + if (!(has_valid_T_arr(inode) && has_valid_T_req(inode))) { + continue; + } + tedge = tnode[inode].out_edges; + num_edges = tnode[inode].num_edges; + for (iedge = 0; iedge < num_edges; iedge++) { + to_node = tedge[iedge].to_node; + if (!(has_valid_T_arr(to_node) && has_valid_T_req(to_node))) { + continue; + } + forward_local_slack = tnode[to_node].T_arr - tnode[inode].T_arr - tedge[iedge].Tdel; + discount = pow((float) DISCOUNT_FUNCTION_BASE, -1 * forward_local_slack / criticality_denom); + tnode[to_node].forward_weight += discount * tnode[inode].forward_weight; + } + } + } + + /* Do a backward topological traversal to populate backward weights. + Since the sinks are all on different levels, we have to check for them as we go. */ + for (ilevel = num_tnode_levels - 1; ilevel >= 0; ilevel--) { + num_at_level = tnodes_at_level[ilevel].nelem; + + for (i = 0; i < num_at_level; i++) { + inode = tnodes_at_level[ilevel].list[i]; + if (!(has_valid_T_arr(inode) && has_valid_T_req(inode))) { + continue; + } + num_edges = tnode[inode].num_edges; + if (num_edges == 0) { /* sink */ + tnode[inode].backward_weight = 1.; + } else { + tedge = tnode[inode].out_edges; + for (iedge = 0; iedge < num_edges; iedge++) { + to_node = tedge[iedge].to_node; + if (!(has_valid_T_arr(to_node) && has_valid_T_req(to_node))) { + continue; + } + backward_local_slack = tnode[to_node].T_req - tnode[inode].T_req - tedge[iedge].Tdel; + discount = pow((float) DISCOUNT_FUNCTION_BASE, -1 * backward_local_slack / criticality_denom); + tnode[inode].backward_weight += discount * tnode[to_node].backward_weight; + } + } + } + } +} +#endif + +static void update_slacks(t_slack * slacks, int source_clock_domain, int sink_clock_domain, float criticality_denom, + boolean update_slack) { + + /* Updates the slack and criticality of each sink pin, or equivalently + each edge, of each net. Go through the list of nets. If the net's + driver tnode has been used, go through each tedge of that tnode and + take the minimum of the slack/criticality for this traversal and the + existing values. Since the criticality_denom can vary greatly between + traversals, we have to update slack and criticality separately. + Only update slack if we need to print it later (update_slack == TRUE). + + Note: there is a correspondence in indexing between out_edges and the + net data structure: out_edges[iedge] = net[inet].node_block[iedge + 1] + There is an offset of 1 because net[inet].node_block includes the driver + node at index 0, while out_edges is part of the driver node and does + not bother to refer to itself. */ + + int inet, iedge, inode, to_node, num_edges; + t_tedge *tedge; + float T_arr, Tdel, T_req, slk, timing_criticality; + + for (inet = 0; inet < num_timing_nets; inet++) { + inode = f_net_to_driver_tnode[inet]; + T_arr = tnode[inode].T_arr; + + if (!(has_valid_T_arr(inode) && has_valid_T_req(inode))) { + continue; /* Only update this net on this traversal if its + driver node has been updated on this traversal. */ + } + + num_edges = tnode[inode].num_edges; + tedge = tnode[inode].out_edges; + + for (iedge = 0; iedge < num_edges; iedge++) { + to_node = tedge[iedge].to_node; + if (!(has_valid_T_arr(to_node) && has_valid_T_req(to_node))) { + continue; /* Only update this edge on this traversal if this + particular sink node has been updated on this traversal. */ + } + Tdel = tedge[iedge].Tdel; + T_req = tnode[to_node].T_req; + + if (update_slack) { + /* Update the slack for this edge. */ + slk = T_req - T_arr - Tdel; + if (slk < slacks->slack[inet][iedge + 1]) { + /* Only update on this traversal if this edge would have + lower slack from this traversal than its current value. */ + slacks->slack[inet][iedge + 1] = slk; + } + } + +#if SLACK_DEFINITION == 'R' + /* Since criticality_denom is not the same on each traversal, + we have to update criticality separately. */ + timing_criticality = 1 - (T_req - T_arr - Tdel)/criticality_denom; + if (timing_criticality > slacks->timing_criticality[inet][iedge + 1]) { + slacks->timing_criticality[inet][iedge + 1] = timing_criticality; + } + #ifdef PATH_COUNTING + /* Also update path criticality separately. Kong uses slack / T_crit for the exponent, + which is equivalent to criticality - 1. Depending on how PATH_COUNTING is defined, + different functional forms are used. */ + #if PATH_COUNTING == 'S' /* Use sum of forward and backward weights. */ + slacks->path_criticality[inet][iedge + 1] = max(slacks->path_criticality[inet][iedge + 1], + (tnode[inode].forward_weight + tnode[to_node].backward_weight) * + pow((float) FINAL_DISCOUNT_FUNCTION_BASE, timing_criticality - 1)); + #elif PATH_COUNTING == 'P' /* Use product of forward and backward weights. */ + slacks->path_criticality[inet][iedge + 1] = max(slacks->path_criticality[inet][iedge + 1], + tnode[inode].forward_weight * tnode[to_node].backward_weight * + pow((float) FINAL_DISCOUNT_FUNCTION_BASE, timing_criticality - 1)); + #elif PATH_COUNTING == 'L' /* Use natural log of product of forward and backward weights. */ + slacks->path_criticality[inet][iedge + 1] = max(slacks->path_criticality[inet][iedge + 1], + log(tnode[inode].forward_weight * tnode[to_node].backward_weight) * + pow((float) FINAL_DISCOUNT_FUNCTION_BASE, timing_criticality - 1)); + #elif PATH_COUNTING == 'R' /* Use product of natural logs of forward and backward weights. */ + slacks->path_criticality[inet][iedge + 1] = max(slacks->path_criticality[inet][iedge + 1], + log(tnode[inode].forward_weight) * log(tnode[to_node].backward_weight) * + pow((float) FINAL_DISCOUNT_FUNCTION_BASE, timing_criticality - 1)); + #endif + #endif +#endif + } + } +} + +void print_lut_remapping(const char *fname) { + FILE *fp; + int inode, i; + t_pb *pb; + + + fp = my_fopen(fname, "w", 0); + fprintf(fp, "# LUT_Name\tinput_pin_mapping\n"); + + for (inode = 0; inode < num_tnodes; inode++) { + /* Print LUT input rebalancing */ + if (tnode[inode].type == TN_PRIMITIVE_OPIN && tnode[inode].pb_graph_pin != NULL) { + pb = block[tnode[inode].block].pb->rr_node_to_pb_mapping[tnode[inode].pb_graph_pin->pin_count_in_cluster]; + if (pb != NULL && pb->lut_pin_remap != NULL) { + assert(pb->pb_graph_node->pb_type->num_output_pins == 1 && pb->pb_graph_node->pb_type->num_clock_pins == 0); /* ensure LUT properties are valid */ + assert(pb->pb_graph_node->num_input_ports == 1); + fprintf(fp, "%s", pb->name); + for (i = 0; i < pb->pb_graph_node->num_input_pins[0]; i++) { + fprintf(fp, "\t%d", pb->lut_pin_remap[i]); + } + fprintf(fp, "\n"); + } + } + } + + fclose(fp); +} + +void print_critical_path(const char *fname) { + + /* Prints the critical path to a file. */ + + t_linked_int *critical_path_head, *critical_path_node; + FILE *fp; + int non_global_nets_on_crit_path, global_nets_on_crit_path; + int tnodes_on_crit_path, inode, iblk, inet; + e_tnode_type type; + float total_net_delay, total_logic_delay, Tdel; + + critical_path_head = allocate_and_load_critical_path(); + critical_path_node = critical_path_head; + + fp = my_fopen(fname, "w", 0); + + non_global_nets_on_crit_path = 0; + global_nets_on_crit_path = 0; + tnodes_on_crit_path = 0; + total_net_delay = 0.; + total_logic_delay = 0.; + + while (critical_path_node != NULL) { + Tdel = print_critical_path_node(fp, critical_path_node); + inode = critical_path_node->data; + type = tnode[inode].type; + tnodes_on_crit_path++; + + if (type == TN_CB_OPIN) { + get_tnode_block_and_output_net(inode, &iblk, &inet); + + if (!timing_nets[inet].is_global) + non_global_nets_on_crit_path++; + else + global_nets_on_crit_path++; + + total_net_delay += Tdel; + } else { + total_logic_delay += Tdel; + } + + critical_path_node = critical_path_node->next; + } + + fprintf(fp, "\nTnodes on critical path: %d Non-global nets on critical path: %d." + "\n", tnodes_on_crit_path, non_global_nets_on_crit_path); + fprintf(fp, "Global nets on critical path: %d.\n", global_nets_on_crit_path); + fprintf(fp, "Total logic delay: %g (s) Total net delay: %g (s)\n", + total_logic_delay, total_net_delay); + + vpr_printf(TIO_MESSAGE_INFO, "Nets on critical path: %d normal, %d global.\n", + non_global_nets_on_crit_path, global_nets_on_crit_path); + + vpr_printf(TIO_MESSAGE_INFO, "Total logic delay: %g (s), total net delay: %g (s)\n", + total_logic_delay, total_net_delay); + + /* Make sure total_logic_delay and total_net_delay add + up to critical path delay,within 5 decimal places. */ + assert(total_logic_delay + total_net_delay - get_critical_path_delay()/1e9 < 1e-5); + + fclose(fp); + free_int_list(&critical_path_head); +} + +t_linked_int * allocate_and_load_critical_path(void) { + + /* Finds the critical path and returns a list of the tnodes on the critical * + * path in a linked list, from the path SOURCE to the path SINK. */ + + t_linked_int *critical_path_head, *curr_crit_node, *prev_crit_node; + int inode, iedge, to_node, num_at_level_zero, i, j, crit_node = OPEN, num_edges; + int source_clock_domain = UNDEFINED, sink_clock_domain = UNDEFINED; + float min_slack = HUGE_POSITIVE_FLOAT, slack; + t_tedge *tedge; + + /* If there's only one clock, we can use the arrival and required times + currently on the timing graph to find the critical path. If there are multiple + clocks, however, the values currently on the timing graph correspond to the + last constraint (pair of clock domains) analysed, which may not be the constraint + with the critical path. In this case, we have to find the constraint with the + least slack and redo the timing analysis for this constraint so we get the right + values onto the timing graph. */ + + if (g_sdc->num_constrained_clocks > 1) { + /* The critical path belongs to the source and sink clock domains + with the least slack. Find these clock domains now. */ + + for (i = 0; i < g_sdc->num_constrained_clocks; i++) { + for (j = 0; j < g_sdc->num_constrained_clocks; j++) { + if (min_slack > f_timing_stats->least_slack[i][j]) { + min_slack = f_timing_stats->least_slack[i][j]; + source_clock_domain = i; + sink_clock_domain = j; + } + } + } + + /* Do a timing analysis for this clock domain pair only. + Set is_prepacked to FALSE since we don't care about the clusterer's normalized values. + Set is_final_analysis to FALSE to get actual, rather than relaxed, slacks. + Set max critical input/output paths to NULL since they aren't used unless is_prepacked is TRUE. */ + do_timing_analysis_for_constraint(source_clock_domain, sink_clock_domain, FALSE, FALSE, (long*)NULL, (long*)NULL); + } + + /* Start at the source (level-0) tnode with the least slack (T_req-T_arr). + This will form the head of our linked list of tnodes on the critical path. */ + min_slack = HUGE_POSITIVE_FLOAT; + num_at_level_zero = tnodes_at_level[0].nelem; + for (i = 0; i < num_at_level_zero; i++) { + inode = tnodes_at_level[0].list[i]; + if (has_valid_T_arr(inode) && has_valid_T_req(inode)) { /* Valid arrival and required times */ + slack = tnode[inode].T_req - tnode[inode].T_arr; + if (slack < min_slack) { + crit_node = inode; + min_slack = slack; + } + } + } + critical_path_head = (t_linked_int *) my_malloc(sizeof(t_linked_int)); + critical_path_head->data = crit_node; + assert(crit_node != OPEN); + prev_crit_node = critical_path_head; + num_edges = tnode[crit_node].num_edges; + + /* Keep adding the tnode in this tnode's fanout which has the least slack + to our critical path linked list, then jump to that tnode and repeat, until + we hit a tnode with no edges, which is the sink of the critical path. */ + while (num_edges != 0) { + curr_crit_node = (t_linked_int *) my_malloc(sizeof(t_linked_int)); + prev_crit_node->next = curr_crit_node; + tedge = tnode[crit_node].out_edges; + min_slack = HUGE_POSITIVE_FLOAT; + + for (iedge = 0; iedge < num_edges; iedge++) { + to_node = tedge[iedge].to_node; + if (has_valid_T_arr(to_node) && has_valid_T_req(to_node)) { /* Valid arrival and required times */ + slack = tnode[to_node].T_req - tnode[to_node].T_arr; + if (slack < min_slack) { + crit_node = to_node; + min_slack = slack; + } + } + } + + curr_crit_node->data = crit_node; + prev_crit_node = curr_crit_node; + num_edges = tnode[crit_node].num_edges; + } + + prev_crit_node->next = NULL; + return (critical_path_head); +} + +void get_tnode_block_and_output_net(int inode, int *iblk_ptr, int *inet_ptr) { + + /* Returns the index of the block that this tnode is part of. If the tnode * + * is a TN_CB_OPIN or TN_INPAD_OPIN (i.e. if it drives a net), the net index is * + * returned via inet_ptr. Otherwise inet_ptr points at OPEN. */ + + int inet, ipin, iblk; + e_tnode_type tnode_type; + + iblk = tnode[inode].block; + tnode_type = tnode[inode].type; + + if (tnode_type == TN_CB_OPIN) { + ipin = tnode[inode].pb_graph_pin->pin_count_in_cluster; + inet = block[iblk].pb->rr_graph[ipin].net_num; + assert(inet != OPEN); + inet = vpack_to_clb_net_mapping[inet]; + } else { + inet = OPEN; + } + + *iblk_ptr = iblk; + *inet_ptr = inet; +} + +void do_constant_net_delay_timing_analysis(t_timing_inf timing_inf, + float constant_net_delay_value) { + + /* Does a timing analysis (simple) where it assumes that each net has a * + * constant delay value. Used only when operation == TIMING_ANALYSIS_ONLY. */ + + /*struct s_linked_vptr *net_delay_chunk_list_head;*/ + + t_chunk net_delay_ch = {NULL, 0, NULL}; + t_slack * slacks = NULL; + float **net_delay = NULL; + + slacks = alloc_and_load_timing_graph(timing_inf); + net_delay = alloc_net_delay(&net_delay_ch, timing_nets, + num_timing_nets); + + load_constant_net_delay(net_delay, constant_net_delay_value, timing_nets, + num_timing_nets); + load_timing_graph_net_delays(net_delay); + + do_timing_analysis(slacks, FALSE, FALSE, TRUE); + + if (getEchoEnabled()) { + if(isEchoFileEnabled(E_ECHO_CRITICAL_PATH)) + print_critical_path("critical_path.echo"); + if(isEchoFileEnabled(E_ECHO_TIMING_GRAPH)) + print_timing_graph(getEchoFileName(E_ECHO_TIMING_GRAPH)); + if(isEchoFileEnabled(E_ECHO_SLACK)) + print_slack(slacks->slack, TRUE, getEchoFileName(E_ECHO_SLACK)); + if(isEchoFileEnabled(E_ECHO_CRITICALITY)) + print_criticality(slacks, TRUE, getEchoFileName(E_ECHO_CRITICALITY)); + if(isEchoFileEnabled(E_ECHO_NET_DELAY)) + print_net_delay(net_delay, getEchoFileName(E_ECHO_NET_DELAY)); + } + + print_timing_stats(); + + free_timing_graph(slacks); + free_net_delay(net_delay, &net_delay_ch); +} +#ifndef PATH_COUNTING +static void update_normalized_costs(float criticality_denom, long max_critical_input_paths, + long max_critical_output_paths) { + int inode; + + /* Update the normalized costs for the clusterer. On each traversal, each cost is + updated for tnodes analysed on this traversal if it would give this tnode a higher + criticality when calculating block criticality for the clusterer. */ + + assert(criticality_denom != 0); /* Possible if timing analysis is being run pre-packing + with all delays set to 0. This is not currently done, + but if you're going to do it, you need to decide how + best to normalize these values to suit your purposes. */ + + for (inode = 0; inode < num_tnodes; inode++) { + /* Only calculate for tnodes which have valid arrival and required times. */ + if (has_valid_T_arr(inode) && has_valid_T_req(inode)) { + tnode[inode].prepacked_data->normalized_slack = std::min(tnode[inode].prepacked_data->normalized_slack, + (tnode[inode].T_req - tnode[inode].T_arr)/criticality_denom); + tnode[inode].prepacked_data->normalized_T_arr = std::max(tnode[inode].prepacked_data->normalized_T_arr, + tnode[inode].T_arr/criticality_denom); + tnode[inode].prepacked_data->normalized_total_critical_paths = std::max(tnode[inode].prepacked_data->normalized_total_critical_paths, + ((float) tnode[inode].prepacked_data->num_critical_input_paths + tnode[inode].prepacked_data->num_critical_output_paths) / + ((float) max_critical_input_paths + max_critical_output_paths)); + } + } +} +#endif +/* Set new arrival time + Special code for LUTs to enable LUT input delay balancing +*/ +static void set_and_balance_arrival_time(int to_node, int from_node, float Tdel, boolean do_lut_input_balancing) { + int i, j; + t_pb *pb; + boolean rebalance; + t_tnode *input_tnode; + + boolean *assigned = NULL; + int fastest_unassigned_pin, most_crit_tnode, most_crit_pin; + float min_delay, highest_T_arr, balanced_T_arr; + + /* Normal case for determining arrival time */ + tnode[to_node].T_arr = std::max(tnode[to_node].T_arr, tnode[from_node].T_arr + Tdel); + + /* Do LUT input rebalancing for LUTs */ + if (do_lut_input_balancing && tnode[to_node].type == TN_PRIMITIVE_OPIN && tnode[to_node].pb_graph_pin != NULL) { + pb = block[tnode[to_node].block].pb->rr_node_to_pb_mapping[tnode[to_node].pb_graph_pin->pin_count_in_cluster]; + if (pb != NULL && pb->lut_pin_remap != NULL) { + /* this is a LUT primitive, do pin swapping */ + assert(pb->pb_graph_node->pb_type->num_output_pins == 1 && pb->pb_graph_node->pb_type->num_clock_pins == 0); /* ensure LUT properties are valid */ + assert(pb->pb_graph_node->num_input_ports == 1); + assert(tnode[from_node].block == tnode[to_node].block); + + /* assign from_node to default location */ + assert(pb->lut_pin_remap[tnode[from_node].pb_graph_pin->pin_number] == OPEN); + pb->lut_pin_remap[tnode[from_node].pb_graph_pin->pin_number] = tnode[from_node].pb_graph_pin->pin_number; + + /* If all input pins are known, perform LUT input delay rebalancing, do nothing otherwise */ + rebalance = TRUE; + for (i = 0; i < pb->pb_graph_node->num_input_pins[0]; i++) { + input_tnode = block[tnode[to_node].block].pb->rr_graph[pb->pb_graph_node->input_pins[0][i].pin_count_in_cluster].tnode; + if (input_tnode != NULL && pb->lut_pin_remap[i] == OPEN) { + rebalance = FALSE; + } + } + if (rebalance == TRUE) { + /* Rebalance LUT inputs so that the most critical paths get the fastest inputs */ + balanced_T_arr = OPEN; + assigned = (boolean*)my_calloc(pb->pb_graph_node->num_input_pins[0], sizeof(boolean)); + /* Clear pin remapping */ + for (i = 0; i < pb->pb_graph_node->num_input_pins[0]; i++) { + pb->lut_pin_remap[i] = OPEN; + } + /* load new T_arr and pin mapping */ + for (i = 0; i < pb->pb_graph_node->num_input_pins[0]; i++) { + /* Find fastest physical input pin of LUT */ + fastest_unassigned_pin = OPEN; + min_delay = OPEN; + for (j = 0; j < pb->pb_graph_node->num_input_pins[0]; j++) { + if (pb->lut_pin_remap[j] == OPEN) { + if (fastest_unassigned_pin == OPEN) { + fastest_unassigned_pin = j; + min_delay = pb->pb_graph_node->input_pins[0][j].pin_timing_del_max[0]; + } else if (min_delay > pb->pb_graph_node->input_pins[0][j].pin_timing_del_max[0]) { + fastest_unassigned_pin = j; + min_delay = pb->pb_graph_node->input_pins[0][j].pin_timing_del_max[0]; + } + } + } + assert(fastest_unassigned_pin != OPEN); + + /* Find most critical LUT input pin in user circuit */ + most_crit_tnode = OPEN; + highest_T_arr = OPEN; + most_crit_pin = OPEN; + for (j = 0; j < pb->pb_graph_node->num_input_pins[0]; j++) { + input_tnode = block[tnode[to_node].block].pb->rr_graph[pb->pb_graph_node->input_pins[0][j].pin_count_in_cluster].tnode; + if (input_tnode != NULL && assigned[j] == FALSE) { + if (most_crit_tnode == OPEN) { + most_crit_tnode = get_tnode_index(input_tnode); + highest_T_arr = input_tnode->T_arr; + most_crit_pin = j; + } else if (highest_T_arr < input_tnode->T_arr) { + most_crit_tnode = get_tnode_index(input_tnode); + highest_T_arr = input_tnode->T_arr; + most_crit_pin = j; + } + } + } + + if (most_crit_tnode == OPEN) { + break; + } else { + assert(tnode[most_crit_tnode].num_edges == 1); + tnode[most_crit_tnode].out_edges[0].Tdel = min_delay; + pb->lut_pin_remap[fastest_unassigned_pin] = most_crit_pin; + assigned[most_crit_pin] = TRUE; + if (balanced_T_arr < min_delay + highest_T_arr) { + balanced_T_arr = min_delay + highest_T_arr; + } + } + } + free(assigned); + if (balanced_T_arr != OPEN) { + tnode[to_node].T_arr = balanced_T_arr; + } + } + } + } +} + +static void load_clock_domain_and_clock_and_io_delay(boolean is_prepacked) { +/* Loads clock domain and clock delay onto TN_FF_SOURCE and TN_FF_SINK tnodes. +The clock domain of each clock is its index in g_sdc->constrained_clocks. +We do this by matching each clock input pad to a constrained clock name, then +propagating forward its domain index to all flip-flops fed by it (TN_FF_CLOCK +tnodes), then later looking up the TN_FF_CLOCK tnode corresponding to every +TN_FF_SOURCE and TN_FF_SINK tnode. We also add up the delays along the clock net +to each TN_FF_CLOCK tnode to give it (and the SOURCE/SINK nodes) a clock delay. + +Also loads input delay/output delay (from set_input_delay or set_output_delay SDC +constraints) onto the tedges between TN_INPAD_SOURCE/OPIN and TN_OUTPAD_IPIN/SINK +tnodes. Finds fanout of each clock domain, including virtual (external) clocks. +Marks unconstrained I/Os with a dummy clock domain (-1). */ + + int i, iclock, inode, num_at_level, clock_index, input_index, output_index; + char * net_name; + t_tnode * clock_node; + + /* Wipe fanout of each clock domain in g_sdc->constrained_clocks. */ + for (iclock = 0; iclock < g_sdc->num_constrained_clocks; iclock++) { + g_sdc->constrained_clocks[iclock].fanout = 0; + } + + /* First, visit all TN_INPAD_SOURCE tnodes */ + num_at_level = tnodes_at_level[0].nelem; /* There are num_at_level top-level tnodes. */ + for (i = 0; i < num_at_level; i++) { + inode = tnodes_at_level[0].list[i]; /* Iterate through each tnode. inode is the index of the tnode in the array tnode. */ + if (tnode[inode].type == TN_INPAD_SOURCE) { /* See if this node is the start of an I/O pad (as oppposed to a flip-flop source). */ + net_name = find_tnode_net_name(inode, is_prepacked); + if ((clock_index = find_clock(net_name)) != -1) { /* We have a clock inpad. */ + /* Set clock skew to 0 at the source and propagate skew + recursively to all connected nodes, adding delay as we go. + Set the clock domain to the index of the clock in the + g_sdc->constrained_clocks array and propagate unchanged. */ + tnode[inode].clock_delay = 0.; + tnode[inode].clock_domain = clock_index; + propagate_clock_domain_and_skew(inode); + + /* Set the clock domain of this clock inpad to -1, so that we do not analyse it. + If we did not do this, the clock net would be analysed on the same iteration of + the timing analyzer as the flip-flops it drives! */ + tnode[inode].clock_domain = -1; + + } else if ((input_index = find_input(net_name)) != -1) { + /* We have a constrained non-clock inpad - find the clock it's constrained on. */ + clock_index = find_clock(g_sdc->constrained_inputs[input_index].clock_name); + assert(clock_index != -1); + /* The clock domain for this input is that of its virtual clock */ + tnode[inode].clock_domain = clock_index; + /* Increment the fanout of this virtual clock domain. */ + g_sdc->constrained_clocks[clock_index].fanout++; + /* Mark input delay specified in SDC file on the timing graph edge leading out from the TN_INPAD_SOURCE node. */ + tnode[inode].out_edges[0].Tdel = g_sdc->constrained_inputs[input_index].delay * 1e-9; /* normalize to be in seconds not ns */ + } else { /* We have an unconstrained input - mark with dummy clock domain and do not analyze. */ + tnode[inode].clock_domain = -1; + } + } + } + + /* Second, visit all TN_OUTPAD_SINK tnodes. Unlike for TN_INPAD_SOURCE tnodes, + we have to search the entire tnode array since these are all on different levels. */ + for (inode = 0; inode < num_tnodes; inode++) { + if (tnode[inode].type == TN_OUTPAD_SINK) { + /* Since the pb_graph_pin of TN_OUTPAD_SINK tnodes points to NULL, we have to find the net + from the pb_graph_pin of the corresponding TN_OUTPAD_IPIN node. + Exploit the fact that the TN_OUTPAD_IPIN node will always be one prior in the tnode array. */ + assert(tnode[inode - 1].type == TN_OUTPAD_IPIN); + net_name = find_tnode_net_name(inode, is_prepacked); + output_index = find_output(net_name + 4); /* the + 4 removes the prefix "out:" automatically prepended to outputs */ + if (output_index != -1) { + /* We have a constrained outpad, find the clock it's constrained on. */ + clock_index = find_clock(g_sdc->constrained_outputs[output_index].clock_name); + assert(clock_index != -1); + /* The clock doain for this output is that of its virtual clock */ + tnode[inode].clock_domain = clock_index; + /* Increment the fanout of this virtual clock domain. */ + g_sdc->constrained_clocks[clock_index].fanout++; + /* Mark output delay specified in SDC file on the timing graph edge leading into the TN_OUTPAD_SINK node. + However, this edge is part of the corresponding TN_OUTPAD_IPIN node. + Exploit the fact that the TN_OUTPAD_IPIN node will always be one prior in the tnode array. */ + tnode[inode - 1].out_edges[0].Tdel = g_sdc->constrained_outputs[output_index].delay * 1e-9; /* normalize to be in seconds not ns */ + + } else { /* We have an unconstrained input - mark with dummy clock domain and do not analyze. */ + tnode[inode].clock_domain = -1; + } + } + } + + /* Third, visit all TN_FF_SOURCE and TN_FF_SINK tnodes, and transfer the clock domain and skew from their corresponding TN_FF_CLOCK tnodes*/ + for (inode = 0; inode < num_tnodes; inode++) { + if (tnode[inode].type == TN_FF_SOURCE || tnode[inode].type == TN_FF_SINK) { + clock_node = find_ff_clock_tnode(inode, is_prepacked); + tnode[inode].clock_domain = clock_node->clock_domain; + tnode[inode].clock_delay = clock_node->clock_delay; + } + } +} + +static void propagate_clock_domain_and_skew(int inode) { +/* Given a tnode indexed by inode (which is part of a clock net), + * propagate forward the clock domain (unchanged) and skew (adding the delay of edges) to all nodes in its fanout. + * We then call recursively on all children in a depth-first search. If num_edges is 0, we should be at an TN_FF_CLOCK tnode; we then set the + * TN_FF_SOURCE and TN_FF_SINK nodes to have the same clock domain and skew as the TN_FF_CLOCK node. We implicitly rely on a tnode not being + * part of two separate clock nets, since undefined behaviour would result if one DFS overwrote the results of another. This may + * be problematic in cases of multiplexed or locally-generated clocks. */ + + int iedge, to_node; + t_tedge * tedge; + + tedge = tnode[inode].out_edges; /* Get the list of edges from the node we're visiting. */ + + if (!tedge) { /* Leaf/sink node; base case of the recursion. */ + assert(tnode[inode].type == TN_FF_CLOCK); + assert(tnode[inode].clock_domain != -1); /* Make sure clock domain is valid. */ + g_sdc->constrained_clocks[tnode[inode].clock_domain].fanout++; + return; + } + + for (iedge = 0; iedge < tnode[inode].num_edges; iedge++) { /* Go through each edge coming out from this tnode */ + to_node = tedge[iedge].to_node; + /* Propagate clock skew forward along this clock net, adding the delay of the wires (edges) of the clock network. */ + tnode[to_node].clock_delay = tnode[inode].clock_delay + tedge[iedge].Tdel; + /* Propagate clock domain forward unchanged */ + tnode[to_node].clock_domain = tnode[inode].clock_domain; + /* Finally, call recursively on the destination tnode. */ + propagate_clock_domain_and_skew(to_node); + } +} + +static char * find_tnode_net_name(int inode, boolean is_prepacked) { + /* Finds the name of the net which a tnode (inode) is on (different for pre-/post-packed netlists). */ + + int logic_block; /* Name chosen not to conflict with the array logical_block */ + char * net_name; + t_pb * physical_block; + t_pb_graph_pin * pb_graph_pin; + + logic_block = tnode[inode].block; + if (is_prepacked) { + net_name = logical_block[logic_block].name; + } else { + physical_block = block[logic_block].pb; + pb_graph_pin = tnode[inode].pb_graph_pin; + net_name = physical_block->rr_node_to_pb_mapping[pb_graph_pin->pin_count_in_cluster]->name; + } + return net_name; +} + +static t_tnode * find_ff_clock_tnode(int inode, boolean is_prepacked) { + /* Finds the TN_FF_CLOCK tnode on the same flipflop as an TN_FF_SOURCE or TN_FF_SINK tnode. */ + + int logic_block; /* Name chosen not to conflict with the array logical_block */ + t_tnode * ff_clock_tnode; + t_rr_node * rr_graph; + t_pb_graph_node * parent_pb_graph_node; + t_pb_graph_pin * ff_source_or_sink_pb_graph_pin, * clock_pb_graph_pin; + + logic_block = tnode[inode].block; + if (is_prepacked) { + ff_clock_tnode = logical_block[logic_block].clock_net_tnode; + } else { + rr_graph = block[logic_block].pb->rr_graph; + ff_source_or_sink_pb_graph_pin = tnode[inode].pb_graph_pin; + parent_pb_graph_node = ff_source_or_sink_pb_graph_pin->parent_node; + /* Make sure there's only one clock port and only one clock pin in that port */ + assert(parent_pb_graph_node->num_clock_ports == 1); + assert(parent_pb_graph_node->num_clock_pins[0] == 1); + clock_pb_graph_pin = &parent_pb_graph_node->clock_pins[0][0]; + ff_clock_tnode = rr_graph[clock_pb_graph_pin->pin_count_in_cluster].tnode; + } + assert(ff_clock_tnode != NULL); + assert(ff_clock_tnode->type == TN_FF_CLOCK); + return ff_clock_tnode; +} + +static int find_clock(char * net_name) { +/* Given a string net_name, find whether it's the name of a clock in the array g_sdc->constrained_clocks. * + * if it is, return the clock's index in g_sdc->constrained_clocks; if it's not, return -1. */ + int index; + for (index = 0; index < g_sdc->num_constrained_clocks; index++) { + if (strcmp(net_name, g_sdc->constrained_clocks[index].name) == 0) { + return index; + } + } + return -1; +} + +static int find_input(char * net_name) { +/* Given a string net_name, find whether it's the name of a constrained input in the array g_sdc->constrained_inputs. * + * if it is, return its index in g_sdc->constrained_inputs; if it's not, return -1. */ + int index; + for (index = 0; index < g_sdc->num_constrained_inputs; index++) { + if (strcmp(net_name, g_sdc->constrained_inputs[index].name) == 0) { + return index; + } + } + return -1; +} + +static int find_output(char * net_name) { +/* Given a string net_name, find whether it's the name of a constrained output in the array g_sdc->constrained_outputs. * + * if it is, return its index in g_sdc->constrained_outputs; if it's not, return -1. */ + int index; + for (index = 0; index < g_sdc->num_constrained_outputs; index++) { + if (strcmp(net_name, g_sdc->constrained_outputs[index].name) == 0) { + return index; + } + } + return -1; +} + +static int find_cf_constraint(char * source_clock_name, char * sink_ff_name) { + /* Given a source clock domain and a sink flip-flop, find out if there's an override constraint between them. + If there is, return the index in g_sdc->cf_constraints; if there is not, return -1. */ + int icf, isource, isink; + + for (icf = 0; icf < g_sdc->num_cf_constraints; icf++) { + for (isource = 0; isource < g_sdc->cf_constraints[icf].num_source; isource++) { + if (strcmp(g_sdc->cf_constraints[icf].source_list[isource], source_clock_name) == 0) { + for (isink = 0; isink < g_sdc->cf_constraints[icf].num_sink; isink++) { + if (strcmp(g_sdc->cf_constraints[icf].sink_list[isink], sink_ff_name) == 0) { + return icf; + } + } + } + } + } + return -1; +} + +static inline int get_tnode_index(t_tnode * node) { + /* Returns the index of pointer_to_tnode in the array tnode [0..num_tnodes - 1] + using pointer arithmetic. */ + return node - tnode; +} + +static inline boolean has_valid_T_arr(int inode) { + /* Has this tnode's arrival time been changed from its original value of HUGE_NEGATIVE_FLOAT? */ + return (boolean) (tnode[inode].T_arr > HUGE_NEGATIVE_FLOAT + 1); +} + +static inline boolean has_valid_T_req(int inode) { + /* Has this tnode's required time been changed from its original value of HUGE_POSITIVE_FLOAT? */ + return (boolean) (tnode[inode].T_req < HUGE_POSITIVE_FLOAT - 1); +} + +#ifndef PATH_COUNTING +boolean has_valid_normalized_T_arr(int inode) { + /* Has this tnode's normalized_T_arr been changed from its original value of HUGE_NEGATIVE_FLOAT? */ + return (boolean) (tnode[inode].prepacked_data->normalized_T_arr > HUGE_NEGATIVE_FLOAT + 1); +} +#endif + +float get_critical_path_delay(void) { + /* Finds the critical path delay, which is the minimum clock period required to meet the constraint + corresponding to the pair of source and sink clock domains with the least slack in the design. */ + + int source_clock_domain, sink_clock_domain; + float least_slack_in_design = HUGE_POSITIVE_FLOAT, critical_path_delay = UNDEFINED; + + if (!g_sdc) return UNDEFINED; /* If timing analysis is off, for instance. */ + + for (source_clock_domain = 0; source_clock_domain < g_sdc->num_constrained_clocks; source_clock_domain++) { + for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { + if (least_slack_in_design > f_timing_stats->least_slack[source_clock_domain][sink_clock_domain]) { + least_slack_in_design = f_timing_stats->least_slack[source_clock_domain][sink_clock_domain]; + critical_path_delay = f_timing_stats->cpd[source_clock_domain][sink_clock_domain]; + } + } + } + + return critical_path_delay * 1e9; /* Convert to nanoseconds */ +} + +void print_timing_stats(void) { + + /* Prints critical path delay/fmax, least slack in design, and, for multiple-clock designs, + minimum required clock period to meet each constraint, least slack per constraint, + geometric average clock frequency, and fanout-weighted geometric average clock frequency. */ + + int source_clock_domain, sink_clock_domain, clock_domain, fanout, total_fanout = 0, + num_netlist_clocks_with_intra_domain_paths = 0; + float geomean_period = 1., least_slack_in_design = HUGE_POSITIVE_FLOAT, critical_path_delay = UNDEFINED; + double fanout_weighted_geomean_period = 1.; + boolean found; + + /* Find critical path delay. If the pb_max_internal_delay is greater than this, it becomes + the limiting factor on critical path delay, so print that instead, with a special message. */ + + for (source_clock_domain = 0; source_clock_domain < g_sdc->num_constrained_clocks; source_clock_domain++) { + for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { + if (least_slack_in_design > f_timing_stats->least_slack[source_clock_domain][sink_clock_domain]) { + least_slack_in_design = f_timing_stats->least_slack[source_clock_domain][sink_clock_domain]; + critical_path_delay = f_timing_stats->cpd[source_clock_domain][sink_clock_domain]; + } + } + } + + if (pb_max_internal_delay != UNDEFINED && pb_max_internal_delay > critical_path_delay) { + critical_path_delay = pb_max_internal_delay; + vpr_printf(TIO_MESSAGE_INFO, "Final critical path: %g ns\n", 1e9 * critical_path_delay); + vpr_printf(TIO_MESSAGE_INFO, "\t(capped by fmax of block type %s)\n", pbtype_max_internal_delay->name); + + } else { + vpr_printf(TIO_MESSAGE_INFO, "Final critical path: %g ns\n", 1e9 * critical_path_delay); + } + + if (g_sdc->num_constrained_clocks <= 1) { + /* Although critical path delay is always well-defined, it doesn't make sense to talk about fmax for multi-clock circuits */ + vpr_printf(TIO_MESSAGE_INFO, "f_max: %g MHz\n", 1e-6 / critical_path_delay); + } + + /* Also print the least slack in the design */ + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "Least slack in design: %g ns\n", 1e9 * least_slack_in_design); + vpr_printf(TIO_MESSAGE_INFO, "\n"); + + if (g_sdc->num_constrained_clocks > 1) { /* Multiple-clock design */ + + /* Print minimum possible clock period to meet each constraint. Convert to nanoseconds. */ + + vpr_printf(TIO_MESSAGE_INFO, "Minimum possible clock period to meet each constraint (including skew effects):\n"); + for (source_clock_domain = 0; source_clock_domain < g_sdc->num_constrained_clocks; source_clock_domain++) { + /* Print the intra-domain constraint if it was analysed. */ + if (g_sdc->domain_constraint[source_clock_domain][source_clock_domain] > NEGATIVE_EPSILON) { + vpr_printf(TIO_MESSAGE_INFO, "%s to %s: %g ns (%g MHz)\n", + g_sdc->constrained_clocks[source_clock_domain].name, + g_sdc->constrained_clocks[source_clock_domain].name, + 1e9 * f_timing_stats->cpd[source_clock_domain][source_clock_domain], + 1e-6 / f_timing_stats->cpd[source_clock_domain][source_clock_domain]); + } else { + vpr_printf(TIO_MESSAGE_INFO, "%s to %s: --\n", + g_sdc->constrained_clocks[source_clock_domain].name, + g_sdc->constrained_clocks[source_clock_domain].name); + } + /* Then, print all other constraints on separate lines, indented. We re-print + the source clock domain's name so there's no ambiguity when parsing. */ + for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { + if (source_clock_domain == sink_clock_domain) continue; /* already done that */ + if (g_sdc->domain_constraint[source_clock_domain][sink_clock_domain] > NEGATIVE_EPSILON) { + /* If this domain pair was analysed */ + vpr_printf(TIO_MESSAGE_INFO, "\t%s to %s: %g ns (%g MHz)\n", + g_sdc->constrained_clocks[source_clock_domain].name, + g_sdc->constrained_clocks[sink_clock_domain].name, + 1e9 * f_timing_stats->cpd[source_clock_domain][sink_clock_domain], + 1e-6 / f_timing_stats->cpd[source_clock_domain][sink_clock_domain]); + } else { + vpr_printf(TIO_MESSAGE_INFO, "\t%s to %s: --\n", + g_sdc->constrained_clocks[source_clock_domain].name, + g_sdc->constrained_clocks[sink_clock_domain].name); + } + } + } + + /* Print least slack per constraint. */ + + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "Least slack per constraint:\n"); + for (source_clock_domain = 0; source_clock_domain < g_sdc->num_constrained_clocks; source_clock_domain++) { + /* Print the intra-domain slack if valid. */ + if (f_timing_stats->least_slack[source_clock_domain][source_clock_domain] < HUGE_POSITIVE_FLOAT - 1) { + vpr_printf(TIO_MESSAGE_INFO, "%s to %s: %g ns\n", + g_sdc->constrained_clocks[source_clock_domain].name, + g_sdc->constrained_clocks[source_clock_domain].name, + 1e9 * f_timing_stats->least_slack[source_clock_domain][source_clock_domain]); + } else { + vpr_printf(TIO_MESSAGE_INFO, "%s to %s: --\n", + g_sdc->constrained_clocks[source_clock_domain].name, + g_sdc->constrained_clocks[source_clock_domain].name); + } + /* Then, print all other slacks on separate lines. */ + for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { + if (source_clock_domain == sink_clock_domain) continue; /* already done that */ + if (f_timing_stats->least_slack[source_clock_domain][sink_clock_domain] < HUGE_POSITIVE_FLOAT - 1) { + /* If this domain pair was analysed and has a valid slack */ + vpr_printf(TIO_MESSAGE_INFO, "\t%s to %s: %g ns\n", + g_sdc->constrained_clocks[source_clock_domain].name, + g_sdc->constrained_clocks[sink_clock_domain].name, + 1e9 * f_timing_stats->least_slack[source_clock_domain][sink_clock_domain]); + } else { + vpr_printf(TIO_MESSAGE_INFO, "\t%s to %s: --\n", + g_sdc->constrained_clocks[source_clock_domain].name, + g_sdc->constrained_clocks[sink_clock_domain].name); + } + } + } + + /* Calculate geometric mean f_max (fanout-weighted and unweighted) from the diagonal (intra-domain) entries of critical_path_delay, + excluding domains without intra-domain paths (for which the timing constraint is DO_NOT_ANALYSE) and virtual clocks. */ + found = FALSE; + for (clock_domain = 0; clock_domain < g_sdc->num_constrained_clocks; clock_domain++) { + if (g_sdc->domain_constraint[clock_domain][clock_domain] > NEGATIVE_EPSILON && g_sdc->constrained_clocks[clock_domain].is_netlist_clock) { + geomean_period *= f_timing_stats->cpd[clock_domain][clock_domain]; + fanout = g_sdc->constrained_clocks[clock_domain].fanout; + fanout_weighted_geomean_period *= pow((double) f_timing_stats->cpd[clock_domain][clock_domain], fanout); + total_fanout += fanout; + num_netlist_clocks_with_intra_domain_paths++; + found = TRUE; + } + } + if (found) { /* Only print these if we found at least one clock domain with intra-domain paths. */ + geomean_period = pow(geomean_period, (float) 1/num_netlist_clocks_with_intra_domain_paths); + fanout_weighted_geomean_period = pow(fanout_weighted_geomean_period, (double) 1/total_fanout); + /* Convert to MHz */ + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "Geometric mean intra-domain period: %g ns (%g MHz)\n", + 1e9 * geomean_period, 1e-6 / geomean_period); + vpr_printf(TIO_MESSAGE_INFO, "Fanout-weighted geomean intra-domain period: %g ns (%g MHz)\n", + 1e9 * fanout_weighted_geomean_period, 1e-6 / fanout_weighted_geomean_period); + } + + vpr_printf(TIO_MESSAGE_INFO, "\n"); + } +} + +static void print_timing_constraint_info(const char *fname) { + /* Prints the contents of g_sdc->domain_constraint, g_sdc->constrained_clocks, constrained_ios and g_sdc->cc_constraints to a file. */ + + FILE * fp; + int source_clock_domain, sink_clock_domain, i, j; + int * clock_name_length = (int *) my_malloc(g_sdc->num_constrained_clocks * sizeof(int)); /* Array of clock name lengths */ + int max_clock_name_length = INT_MIN; + char * clock_name; + + fp = my_fopen(fname, "w", 0); + + /* Get lengths of each clock name and max length so we can space the columns properly. */ + for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { + clock_name = g_sdc->constrained_clocks[sink_clock_domain].name; + clock_name_length[sink_clock_domain] = strlen(clock_name); + if (clock_name_length[sink_clock_domain] > max_clock_name_length) { + max_clock_name_length = clock_name_length[sink_clock_domain]; + } + } + + /* First, combine info from g_sdc->domain_constraint and g_sdc->constrained_clocks into a matrix + (they're indexed the same as each other). */ + + fprintf(fp, "Timing constraints in ns (source clock domains down left side, sink along top).\n" + "A value of -1.00 means the pair of source and sink domains will not be analysed.\n\n"); + + print_spaces(fp, max_clock_name_length + 4); + + for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { + fprintf(fp, "%s", g_sdc->constrained_clocks[sink_clock_domain].name); + /* Minimum column width of 8 */ + print_spaces(fp, std::max(8 - clock_name_length[sink_clock_domain], 4)); + } + fprintf(fp, "\n"); + + for (source_clock_domain = 0; source_clock_domain < g_sdc->num_constrained_clocks; source_clock_domain++) { + fprintf(fp, "%s", g_sdc->constrained_clocks[source_clock_domain].name); + print_spaces(fp, max_clock_name_length + 4 - clock_name_length[source_clock_domain]); + for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { + fprintf(fp, "%5.2f", g_sdc->domain_constraint[source_clock_domain][sink_clock_domain]); + /* Minimum column width of 8 */ + print_spaces(fp, std::max(clock_name_length[sink_clock_domain] - 1, 3)); + } + fprintf(fp, "\n"); + } + + free(clock_name_length); + + /* Second, print I/O constraints. */ + fprintf(fp, "\nList of constrained inputs (note: constraining a clock net input has no effect):\n"); + for (i = 0; i < g_sdc->num_constrained_inputs; i++) { + fprintf(fp, "Input name %s on clock %s with input delay %.2f ns\n", + g_sdc->constrained_inputs[i].name, g_sdc->constrained_inputs[i].clock_name, g_sdc->constrained_inputs[i].delay); + } + + fprintf(fp, "\nList of constrained outputs:\n"); + for (i = 0; i < g_sdc->num_constrained_outputs; i++) { + fprintf(fp, "Output name %s on clock %s with output delay %.2f ns\n", + g_sdc->constrained_outputs[i].name, g_sdc->constrained_outputs[i].clock_name, g_sdc->constrained_outputs[i].delay); + } + + /* Third, print override constraints. */ + fprintf(fp, "\nList of override constraints (non-default constraints created by set_false_path, set_clock_groups, \nset_max_delay, and set_multicycle_path):\n"); + + for (i = 0; i < g_sdc->num_cc_constraints; i++) { + fprintf(fp, "Clock domain"); + for (j = 0; j < g_sdc->cc_constraints[i].num_source; j++) { + fprintf(fp, " %s,", g_sdc->cc_constraints[i].source_list[j]); + } + fprintf(fp, " to clock domain"); + for (j = 0; j < g_sdc->cc_constraints[i].num_sink - 1; j++) { + fprintf(fp, " %s,", g_sdc->cc_constraints[i].sink_list[j]); + } /* We have to print the last one separately because we don't want a comma after it. */ + if (g_sdc->cc_constraints[i].num_multicycles == 0) { /* not a multicycle constraint */ + fprintf(fp, " %s: %.2f ns\n", g_sdc->cc_constraints[i].sink_list[j], g_sdc->cc_constraints[i].constraint); + } else { /* multicycle constraint */ + fprintf(fp, " %s: %d multicycles\n", g_sdc->cc_constraints[i].sink_list[j], g_sdc->cc_constraints[i].num_multicycles); + } + } + + for (i = 0; i < g_sdc->num_cf_constraints; i++) { + fprintf(fp, "Clock domain"); + for (j = 0; j < g_sdc->cf_constraints[i].num_source; j++) { + fprintf(fp, " %s,", g_sdc->cf_constraints[i].source_list[j]); + } + fprintf(fp, " to flip-flop"); + for (j = 0; j < g_sdc->cf_constraints[i].num_sink - 1; j++) { + fprintf(fp, " %s,", g_sdc->cf_constraints[i].sink_list[j]); + } /* We have to print the last one separately because we don't want a comma after it. */ + if (g_sdc->cf_constraints[i].num_multicycles == 0) { /* not a multicycle constraint */ + fprintf(fp, " %s: %.2f ns\n", g_sdc->cf_constraints[i].sink_list[j], g_sdc->cf_constraints[i].constraint); + } else { /* multicycle constraint */ + fprintf(fp, " %s: %d multicycles\n", g_sdc->cf_constraints[i].sink_list[j], g_sdc->cf_constraints[i].num_multicycles); + } + } + + for (i = 0; i < g_sdc->num_fc_constraints; i++) { + fprintf(fp, "Flip-flop"); + for (j = 0; j < g_sdc->fc_constraints[i].num_source; j++) { + fprintf(fp, " %s,", g_sdc->fc_constraints[i].source_list[j]); + } + fprintf(fp, " to clock domain"); + for (j = 0; j < g_sdc->fc_constraints[i].num_sink - 1; j++) { + fprintf(fp, " %s,", g_sdc->fc_constraints[i].sink_list[j]); + } /* We have to print the last one separately because we don't want a comma after it. */ + if (g_sdc->fc_constraints[i].num_multicycles == 0) { /* not a multicycle constraint */ + fprintf(fp, " %s: %.2f ns\n", g_sdc->fc_constraints[i].sink_list[j], g_sdc->fc_constraints[i].constraint); + } else { /* multicycle constraint */ + fprintf(fp, " %s: %d multicycles\n", g_sdc->fc_constraints[i].sink_list[j], g_sdc->fc_constraints[i].num_multicycles); + } + } + + for (i = 0; i < g_sdc->num_ff_constraints; i++) { + fprintf(fp, "Flip-flop"); + for (j = 0; j < g_sdc->ff_constraints[i].num_source; j++) { + fprintf(fp, " %s,", g_sdc->ff_constraints[i].source_list[j]); + } + fprintf(fp, " to flip-flop"); + for (j = 0; j < g_sdc->ff_constraints[i].num_sink - 1; j++) { + fprintf(fp, " %s,", g_sdc->ff_constraints[i].sink_list[j]); + } /* We have to print the last one separately because we don't want a comma after it. */ + if (g_sdc->ff_constraints[i].num_multicycles == 0) { /* not a multicycle constraint */ + fprintf(fp, " %s: %.2f ns\n", g_sdc->ff_constraints[i].sink_list[j], g_sdc->ff_constraints[i].constraint); + } else { /* multicycle constraint */ + fprintf(fp, " %s: %d multicycles\n", g_sdc->ff_constraints[i].sink_list[j], g_sdc->ff_constraints[i].num_multicycles); + } + } + + fclose(fp); +} + +static void print_spaces(FILE * fp, int num_spaces) { + /* Prints num_spaces spaces to file pointed to by fp. */ + for ( ; num_spaces > 0; num_spaces--) { + fprintf(fp, " "); + } +} + +void print_timing_graph_as_blif (const char *fname, t_model *models) { + struct s_model_ports *port; + struct s_linked_vptr *p_io_removed; + /* Prints out the critical path to a file. */ + + FILE *fp; + int i, j; + + fp = my_fopen(fname, "w", 0); + + fprintf(fp, ".model %s\n", blif_circuit_name); + + fprintf(fp, ".inputs "); + for (i = 0; i < num_logical_blocks; i++) { + if (logical_block[i].type == VPACK_INPAD) { + fprintf(fp, "\\\n%s ", logical_block[i].name); + } + } + p_io_removed = circuit_p_io_removed; + while (p_io_removed) { + fprintf(fp, "\\\n%s ", (char *) p_io_removed->data_vptr); + p_io_removed = p_io_removed->next; + } + + fprintf(fp, "\n"); + + fprintf(fp, ".outputs "); + for (i = 0; i < num_logical_blocks; i++) { + if (logical_block[i].type == VPACK_OUTPAD) { + /* Outputs have a "out:" prepended to them, must remove */ + fprintf(fp, "\\\n%s ", &logical_block[i].name[4]); + } + } + fprintf(fp, "\n"); + fprintf(fp, ".names unconn\n"); + fprintf(fp, " 0\n\n"); + + /* Print out primitives */ + for (i = 0; i < num_logical_blocks; i++) { + print_primitive_as_blif (fp, i); + } + + /* Print out tnode connections */ + for (i = 0; i < num_tnodes; i++) { + if (tnode[i].type != TN_PRIMITIVE_IPIN && tnode[i].type != TN_FF_SOURCE + && tnode[i].type != TN_INPAD_SOURCE + && tnode[i].type != TN_OUTPAD_IPIN) { + for (j = 0; j < tnode[i].num_edges; j++) { + fprintf(fp, ".names tnode_%d tnode_%d\n", i, + tnode[i].out_edges[j].to_node); + fprintf(fp, "1 1\n\n"); + } + } + } + + fprintf(fp, ".end\n\n"); + + /* Print out .subckt models */ + while (models) { + fprintf(fp, ".model %s\n", models->name); + fprintf(fp, ".inputs "); + port = models->inputs; + while (port) { + if (port->size > 1) { + for (j = 0; j < port->size; j++) { + fprintf(fp, "%s[%d] ", port->name, j); + } + } else { + fprintf(fp, "%s ", port->name); + } + port = port->next; + } + fprintf(fp, "\n"); + fprintf(fp, ".outputs "); + port = models->outputs; + while (port) { + if (port->size > 1) { + for (j = 0; j < port->size; j++) { + fprintf(fp, "%s[%d] ", port->name, j); + } + } else { + fprintf(fp, "%s ", port->name); + } + port = port->next; + } + fprintf(fp, "\n.blackbox\n.end\n\n"); + fprintf(fp, "\n\n"); + models = models->next; + } + fclose(fp); +} + +static void print_primitive_as_blif (FILE *fpout, int iblk) { + int i, j; + struct s_model_ports *port; + struct s_linked_vptr *truth_table; + t_rr_node *irr_graph; + t_pb_graph_node *pb_graph_node; + int node; + + /* Print primitives found in timing graph in blif format based on whether this is a logical primitive or a physical primitive */ + + if (logical_block[iblk].type == VPACK_INPAD) { + if (logical_block[iblk].pb == NULL) { + fprintf(fpout, ".names %s tnode_%d\n", logical_block[iblk].name, + get_tnode_index(logical_block[iblk].output_net_tnodes[0][0])); + } else { + fprintf(fpout, ".names %s tnode_%d\n", logical_block[iblk].name, + get_tnode_index(logical_block[iblk].pb->rr_graph[logical_block[iblk].pb->pb_graph_node->output_pins[0][0].pin_count_in_cluster].tnode)); + } + fprintf(fpout, "1 1\n\n"); + } else if (logical_block[iblk].type == VPACK_OUTPAD) { + /* outputs have the symbol out: automatically prepended to it, must remove */ + if (logical_block[iblk].pb == NULL) { + fprintf(fpout, ".names tnode_%d %s\n", + get_tnode_index(logical_block[iblk].input_net_tnodes[0][0]), + &logical_block[iblk].name[4]); + } else { + /* avoid the out: from output pad naming */ + fprintf(fpout, ".names tnode_%d %s\n", + get_tnode_index(logical_block[iblk].pb->rr_graph[logical_block[iblk].pb->pb_graph_node->input_pins[0][0].pin_count_in_cluster].tnode), + (logical_block[iblk].name + 4)); + } + fprintf(fpout, "1 1\n\n"); + } else if (strcmp(logical_block[iblk].model->name, "latch") == 0) { + fprintf(fpout, ".latch "); + node = OPEN; + + if (logical_block[iblk].pb == NULL) { + i = 0; + port = logical_block[iblk].model->inputs; + while (port) { + if (!port->is_clock) { + assert(port->size == 1); + for (j = 0; j < port->size; j++) { + if (logical_block[iblk].input_net_tnodes[i][j] != NULL) { + fprintf(fpout, "tnode_%d ", + get_tnode_index(logical_block[iblk].input_net_tnodes[i][j])); + } else { + assert(0); + } + } + i++; + } + port = port->next; + } + assert(i == 1); + + i = 0; + port = logical_block[iblk].model->outputs; + while (port) { + assert(port->size == 1); + for (j = 0; j < port->size; j++) { + if (logical_block[iblk].output_net_tnodes[i][j] != NULL) { + node = + get_tnode_index(logical_block[iblk].output_net_tnodes[i][j]); + fprintf(fpout, "latch_%s re ", + logical_block[iblk].name); + } else { + assert(0); + } + } + i++; + port = port->next; + } + assert(i == 1); + + i = 0; + port = logical_block[iblk].model->inputs; + while (port) { + if (port->is_clock) { + for (j = 0; j < port->size; j++) { + if (logical_block[iblk].clock_net_tnode != NULL) { + fprintf(fpout, "tnode_%d 0\n\n", + get_tnode_index(logical_block[iblk].clock_net_tnode)); + } else { + assert(0); + } + } + i++; + } + port = port->next; + } + assert(i == 1); + } else { + irr_graph = logical_block[iblk].pb->rr_graph; + assert( + irr_graph[logical_block[iblk].pb->pb_graph_node->input_pins[0][0].pin_count_in_cluster].net_num != OPEN); + fprintf(fpout, "tnode_%d ", + get_tnode_index(irr_graph[logical_block[iblk].pb->pb_graph_node->input_pins[0][0].pin_count_in_cluster].tnode)); + node = + get_tnode_index(irr_graph[logical_block[iblk].pb->pb_graph_node->output_pins[0][0].pin_count_in_cluster].tnode); + fprintf(fpout, "latch_%s re ", logical_block[iblk].name); + assert( + irr_graph[logical_block[iblk].pb->pb_graph_node->clock_pins[0][0].pin_count_in_cluster].net_num != OPEN); + fprintf(fpout, "tnode_%d 0\n\n", + get_tnode_index(irr_graph[logical_block[iblk].pb->pb_graph_node->clock_pins[0][0].pin_count_in_cluster].tnode)); + } + assert(node != OPEN); + fprintf(fpout, ".names latch_%s tnode_%d\n", logical_block[iblk].name, + node); + fprintf(fpout, "1 1\n\n"); + } else if (strcmp(logical_block[iblk].model->name, "names") == 0) { + fprintf(fpout, ".names "); + node = OPEN; + + if (logical_block[iblk].pb == NULL) { + i = 0; + port = logical_block[iblk].model->inputs; + while (port) { + assert(!port->is_clock); + for (j = 0; j < port->size; j++) { + if (logical_block[iblk].input_net_tnodes[i][j] != NULL) { + fprintf(fpout, "tnode_%d ", + get_tnode_index(logical_block[iblk].input_net_tnodes[i][j])); + } else { + break; + } + } + i++; + port = port->next; + } + assert(i == 1); + + i = 0; + port = logical_block[iblk].model->outputs; + while (port) { + assert(port->size == 1); + fprintf(fpout, "lut_%s\n", logical_block[iblk].name); + node = get_tnode_index(logical_block[iblk].output_net_tnodes[0][0]); + assert(node != OPEN); + i++; + port = port->next; + } + assert(i == 1); + } else { + irr_graph = logical_block[iblk].pb->rr_graph; + assert(logical_block[iblk].pb->pb_graph_node->num_input_ports == 1); + for (i = 0; + i < logical_block[iblk].pb->pb_graph_node->num_input_pins[0]; + i++) { + if(logical_block[iblk].input_nets[0][i] != OPEN) { + for (j = 0; j < logical_block[iblk].pb->pb_graph_node->num_input_pins[0]; j++) { + if (irr_graph[logical_block[iblk].pb->pb_graph_node->input_pins[0][j].pin_count_in_cluster].net_num + != OPEN) { + if (irr_graph[logical_block[iblk].pb->pb_graph_node->input_pins[0][j].pin_count_in_cluster].net_num == logical_block[iblk].input_nets[0][i]) { + fprintf(fpout, "tnode_%d ", + get_tnode_index(irr_graph[logical_block[iblk].pb->pb_graph_node->input_pins[0][j].pin_count_in_cluster].tnode)); + break; + } + } + } + assert(j < logical_block[iblk].pb->pb_graph_node->num_input_pins[0]); + } + } + assert( + logical_block[iblk].pb->pb_graph_node->num_output_ports == 1); + assert( + logical_block[iblk].pb->pb_graph_node->num_output_pins[0] == 1); + fprintf(fpout, "lut_%s\n", logical_block[iblk].name); + node = + get_tnode_index(irr_graph[logical_block[iblk].pb->pb_graph_node->output_pins[0][0].pin_count_in_cluster].tnode); + } + assert(node != OPEN); + truth_table = logical_block[iblk].truth_table; + while (truth_table) { + fprintf(fpout, "%s\n", (char*) truth_table->data_vptr); + truth_table = truth_table->next; + } + fprintf(fpout, "\n"); + fprintf(fpout, ".names lut_%s tnode_%d\n", logical_block[iblk].name, + node); + fprintf(fpout, "1 1\n\n"); + } else { + /* This is a standard .subckt blif structure */ + fprintf(fpout, ".subckt %s ", logical_block[iblk].model->name); + if (logical_block[iblk].pb == NULL) { + i = 0; + port = logical_block[iblk].model->inputs; + while (port) { + if (!port->is_clock) { + for (j = 0; j < port->size; j++) { + if (logical_block[iblk].input_net_tnodes[i][j] != NULL) { + if (port->size > 1) { + fprintf(fpout, "\\\n%s[%d]=tnode_%d ", + port->name, j, + get_tnode_index(logical_block[iblk].input_net_tnodes[i][j])); + } else { + fprintf(fpout, "\\\n%s=tnode_%d ", port->name, + get_tnode_index(logical_block[iblk].input_net_tnodes[i][j])); + } + } else { + if (port->size > 1) { + fprintf(fpout, "\\\n%s[%d]=unconn ", port->name, + j); + } else { + fprintf(fpout, "\\\n%s=unconn ", port->name); + } + } + } + i++; + } + port = port->next; + } + + i = 0; + port = logical_block[iblk].model->outputs; + while (port) { + for (j = 0; j < port->size; j++) { + if (logical_block[iblk].output_net_tnodes[i][j] != NULL) { + if (port->size > 1) { + fprintf(fpout, "\\\n%s[%d]=%s ", port->name, j, + vpack_net[logical_block[iblk].output_nets[i][j]].name); + } else { + fprintf(fpout, "\\\n%s=%s ", port->name, + vpack_net[logical_block[iblk].output_nets[i][j]].name); + } + } else { + if (port->size > 1) { + fprintf(fpout, "\\\n%s[%d]=unconn_%d_%s_%d ", + port->name, j, iblk, port->name, j); + } else { + fprintf(fpout, "\\\n%s=unconn_%d_%s ", port->name, + iblk, port->name); + } + } + } + i++; + port = port->next; + } + + i = 0; + port = logical_block[iblk].model->inputs; + while (port) { + if (port->is_clock) { + assert(port->size == 1); + if (logical_block[iblk].clock_net_tnode != NULL) { + fprintf(fpout, "\\\n%s=tnode_%d ", port->name, + get_tnode_index(logical_block[iblk].clock_net_tnode)); + } else { + fprintf(fpout, "\\\n%s=unconn ", port->name); + } + i++; + } + port = port->next; + } + + fprintf(fpout, "\n\n"); + + i = 0; + port = logical_block[iblk].model->outputs; + while (port) { + for (j = 0; j < port->size; j++) { + if (logical_block[iblk].output_net_tnodes[i][j] != NULL) { + fprintf(fpout, ".names %s tnode_%d\n", + vpack_net[logical_block[iblk].output_nets[i][j]].name, + get_tnode_index(logical_block[iblk].output_net_tnodes[i][j])); + fprintf(fpout, "1 1\n\n"); + } + } + i++; + port = port->next; + } + } else { + irr_graph = logical_block[iblk].pb->rr_graph; + pb_graph_node = logical_block[iblk].pb->pb_graph_node; + for (i = 0; i < pb_graph_node->num_input_ports; i++) { + for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { + if (irr_graph[pb_graph_node->input_pins[i][j].pin_count_in_cluster].net_num + != OPEN) { + if (pb_graph_node->num_input_pins[i] > 1) { + fprintf(fpout, "\\\n%s[%d]=tnode_%d ", + pb_graph_node->input_pins[i][j].port->name, + j, + get_tnode_index(irr_graph[pb_graph_node->input_pins[i][j].pin_count_in_cluster].tnode)); + } else { + fprintf(fpout, "\\\n%s=tnode_%d ", + pb_graph_node->input_pins[i][j].port->name, + get_tnode_index(irr_graph[pb_graph_node->input_pins[i][j].pin_count_in_cluster].tnode)); + } + } else { + if (pb_graph_node->num_input_pins[i] > 1) { + fprintf(fpout, "\\\n%s[%d]=unconn ", + pb_graph_node->input_pins[i][j].port->name, + j); + } else { + fprintf(fpout, "\\\n%s=unconn ", + pb_graph_node->input_pins[i][j].port->name); + } + } + } + } + for (i = 0; i < pb_graph_node->num_output_ports; i++) { + for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { + if (irr_graph[pb_graph_node->output_pins[i][j].pin_count_in_cluster].net_num + != OPEN) { + if (pb_graph_node->num_output_pins[i] > 1) { + fprintf(fpout, "\\\n%s[%d]=%s ", + pb_graph_node->output_pins[i][j].port->name, + j, + vpack_net[irr_graph[pb_graph_node->output_pins[i][j].pin_count_in_cluster].net_num].name); + } else { + char* port_name = + pb_graph_node->output_pins[i][j].port->name; + int pin_count = + pb_graph_node->output_pins[i][j].pin_count_in_cluster; + int node_index = irr_graph[pin_count].net_num; + char* node_name = vpack_net[node_index].name; + fprintf(fpout, "\\\n%s=%s ", port_name, node_name); + } + } else { + if (pb_graph_node->num_output_pins[i] > 1) { + fprintf(fpout, "\\\n%s[%d]=unconn ", + pb_graph_node->output_pins[i][j].port->name, + j); + } else { + fprintf(fpout, "\\\n%s=unconn ", + pb_graph_node->output_pins[i][j].port->name); + } + } + } + } + for (i = 0; i < pb_graph_node->num_clock_ports; i++) { + for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { + if (irr_graph[pb_graph_node->clock_pins[i][j].pin_count_in_cluster].net_num + != OPEN) { + if (pb_graph_node->num_clock_pins[i] > 1) { + fprintf(fpout, "\\\n%s[%d]=tnode_%d ", + pb_graph_node->clock_pins[i][j].port->name, + j, + get_tnode_index(irr_graph[pb_graph_node->clock_pins[i][j].pin_count_in_cluster].tnode)); + } else { + fprintf(fpout, "\\\n%s=tnode_%d ", + pb_graph_node->clock_pins[i][j].port->name, + get_tnode_index(irr_graph[pb_graph_node->clock_pins[i][j].pin_count_in_cluster].tnode)); + } + } else { + if (pb_graph_node->num_clock_pins[i] > 1) { + fprintf(fpout, "\\\n%s[%d]=unconn ", + pb_graph_node->clock_pins[i][j].port->name, + j); + } else { + fprintf(fpout, "\\\n%s=unconn ", + pb_graph_node->clock_pins[i][j].port->name); + } + } + } + } + + fprintf(fpout, "\n\n"); + /* connect up output port names to output tnodes */ + for (i = 0; i < pb_graph_node->num_output_ports; i++) { + for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { + if (irr_graph[pb_graph_node->output_pins[i][j].pin_count_in_cluster].net_num + != OPEN) { + fprintf(fpout, ".names %s tnode_%d\n", + vpack_net[irr_graph[pb_graph_node->output_pins[i][j].pin_count_in_cluster].net_num].name, + get_tnode_index(irr_graph[pb_graph_node->output_pins[i][j].pin_count_in_cluster].tnode)); + fprintf(fpout, "1 1\n\n"); + } + } + } + } + } +} diff --git a/vpr7_rram/vpr/SRC/timing/path_delay.h b/vpr7_rram/vpr/SRC/timing/path_delay.h new file mode 100755 index 000000000..2870b6f8e --- /dev/null +++ b/vpr7_rram/vpr/SRC/timing/path_delay.h @@ -0,0 +1,96 @@ +#ifndef PATH_DELAY +#define PATH_DELAY + +#define DO_NOT_ANALYSE -1 + +/*********************** Defines for timing options *******************************/ + +#define SLACK_DEFINITION 'R' +/* Choose how to normalize negative slacks for the optimizers (not in the final timing analysis for output statistics): + 'R' (T_req-relaxed): For each constraint, set the required time at sink nodes to the max of the true required time + (constraint + tnode[inode].clock_skew) and the max arrival time. This means that the required time is "relaxed" + to the max arrival time for tight constraints which would otherwise give negative slack. + Criticalities are computed once per constraint, using a criticality denominator unique to that constraint + (maximum of the constraint and the max arrival time). + 'S' (Shifted): After all slacks are computed, increase the value of all slacks by the largest negative slack, + if it exists. Equivalent to 'R' for single-clock cases. + Criticalities are computed once per timing analysis, using a single criticality denominator for all constraints + (maximum of all constraints and all required times). + This can give unusual results with multiple, very dissimilar constraints. +*/ + +#ifdef PATH_COUNTING /* Path counting options: */ + #define DISCOUNT_FUNCTION_BASE 100 + /* The base of the exponential discount function used to calculate + forward and backward path weights. Higher values discount paths + with higher slacks more greatly. */ + + #define FINAL_DISCOUNT_FUNCTION_BASE DISCOUNT_FUNCTION_BASE + /* The base of the exponential disount function used to calculate + path criticality from forward and backward weights. Higher values + discount paths with higher slacks more greatly. By default, this + is the same as the original discount function base. */ + + #define PACK_PATH_WEIGHT 1 + #define TIMING_GAIN_PATH_WEIGHT PACK_PATH_WEIGHT + #define PLACE_PATH_WEIGHT 0 + #define ROUTE_PATH_WEIGHT 0 + /* The percentage of total criticality taken from path criticality + as opposed to timing criticality. A value of 0 uses only timing + criticality; a value of 1 uses only path criticality. */ +#endif + +/*************************** Function declarations ********************************/ + +t_slack * alloc_and_load_timing_graph(t_timing_inf timing_inf); + +t_slack * alloc_and_load_pre_packing_timing_graph(float block_delay, + float inter_cluster_net_delay, t_model *models, t_timing_inf timing_inf); + +t_linked_int *allocate_and_load_critical_path(void); + +void load_timing_graph_net_delays(float **net_delay); + +void do_timing_analysis(t_slack * slacks, boolean is_prepacked, boolean do_lut_input_balancing, boolean is_final_analysis); + +void free_timing_graph(t_slack * slack); + +void free_timing_stats(void); + +void print_timing_graph(const char *fname); + +void print_lut_remapping(const char *fname); + +void print_slack(float ** slack, boolean slack_is_normalized, const char *fname); + +void print_criticality(t_slack * slacks, boolean criticality_is_normalized, const char *fname); + +void print_net_delay(float **net_delay, const char *fname); + +#ifdef PATH_COUNTING +void print_path_criticality(float ** path_criticality, const char *fname); +#else +void print_clustering_timing_info(const char *fname); + +boolean has_valid_normalized_T_arr(int inode); +#endif + +void print_timing_stats(void); + +float get_critical_path_delay(void); + +void print_critical_path(const char *fname); + +void get_tnode_block_and_output_net(int inode, int *iblk_ptr, int *inet_ptr); + +void do_constant_net_delay_timing_analysis(t_timing_inf timing_inf, + float constant_net_delay_value); + +void print_timing_graph_as_blif (const char *fname, t_model *models); + +/*************************** Variable declarations ********************************/ + +extern int num_tnodes; /* Number of nodes (pins) in the timing graph */ +extern t_tnode *tnode; /* [0..num_tnodes - 1] nodes in the timing graph */ + +#endif diff --git a/vpr7_rram/vpr/SRC/timing/path_delay2.c b/vpr7_rram/vpr/SRC/timing/path_delay2.c new file mode 100755 index 000000000..ea7374b0b --- /dev/null +++ b/vpr7_rram/vpr/SRC/timing/path_delay2.c @@ -0,0 +1,293 @@ +#include +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "path_delay2.h" +#include "read_xml_arch_file.h" + +/************* Variables (globals) shared by all path_delay modules **********/ + +int num_tnode_levels; /* Number of levels in the timing graph. */ + +struct s_ivec *tnodes_at_level; +/* [0..num__tnode_levels - 1]. Count and list of tnodes at each level of + * the timing graph, to make topological searches easier. Level-0 nodes are + * sources to the timing graph (types TN_FF_SOURCE, TN_INPAD_SOURCE + * and TN_CONSTANT_GEN_SOURCE). Level-N nodes are in the immediate fanout of + * nodes with level at most N-1. */ + +/******************* Subroutines local to this module ************************/ + +static int *alloc_and_load_tnode_fanin_and_check_edges(int *num_sinks_ptr); +static void show_combinational_cycle_candidates(); + +/************************** Subroutine definitions ***************************/ + +static int * +alloc_and_load_tnode_fanin_and_check_edges(int *num_sinks_ptr) { + + /* Allocates an array and fills it with the number of in-edges (inputs) to * + * each tnode. While doing this it also checks that each edge in the timing * + * graph points to a valid tnode. Also counts the number of sinks. */ + + int inode, iedge, to_node, num_edges, error, num_sinks; + int *tnode_num_fanin; + t_tedge *tedge; + + tnode_num_fanin = (int *) my_calloc(num_tnodes, sizeof(int)); + error = 0; + num_sinks = 0; + + for (inode = 0; inode < num_tnodes; inode++) { + num_edges = tnode[inode].num_edges; + + if (num_edges > 0) { + tedge = tnode[inode].out_edges; + for (iedge = 0; iedge < num_edges; iedge++) { + to_node = tedge[iedge].to_node; + if (to_node < 0 || to_node >= num_tnodes) { + vpr_printf(TIO_MESSAGE_ERROR, "in alloc_and_load_tnode_fanin_and_check_edges:\n"); + vpr_printf(TIO_MESSAGE_ERROR, "\ttnode #%d edge #%d goes to illegal node #%d.\n", + inode, iedge, to_node); + error++; + } + + tnode_num_fanin[to_node]++; + } + } + + else if (num_edges == 0) { + num_sinks++; + } + + else { + vpr_printf(TIO_MESSAGE_ERROR, "in alloc_and_load_tnode_fanin_and_check_edges:\n"); + vpr_printf(TIO_MESSAGE_ERROR, "\ttnode #%d has %d edges.\n", + inode, num_edges); + error++; + } + + } + + if (error != 0) { + vpr_printf(TIO_MESSAGE_ERROR, "Found %d Errors in the timing graph. Aborting.\n", error); + exit(1); + } + + *num_sinks_ptr = num_sinks; + return (tnode_num_fanin); +} + +int alloc_and_load_timing_graph_levels(void) { + + /* Does a breadth-first search through the timing graph in order to levelize * + * it. This allows subsequent traversals to be done topologically for speed. * + * Also returns the number of sinks in the graph (nodes with no fanout). */ + + t_linked_int *free_list_head, *nodes_at_level_head; + int inode, num_at_level, iedge, to_node, num_edges, num_sinks, num_levels, + i; + t_tedge *tedge; + + /* [0..num_tnodes-1]. # of in-edges to each tnode that have not yet been * + * seen in this traversal. */ + + int *tnode_fanin_left; + + tnode_fanin_left = alloc_and_load_tnode_fanin_and_check_edges(&num_sinks); + + free_list_head = NULL; + nodes_at_level_head = NULL; + + /* Very conservative -> max number of levels = num_tnodes. Realloc later. * + * Temporarily need one extra level on the end because I look at the first * + * empty level. */ + + tnodes_at_level = (struct s_ivec *) my_malloc( + (num_tnodes + 1) * sizeof(struct s_ivec)); + + /* Scan through the timing graph, putting all the primary input nodes (no * + * fanin) into level 0 of the level structure. */ + + num_at_level = 0; + + for (inode = 0; inode < num_tnodes; inode++) { + if (tnode_fanin_left[inode] == 0) { + num_at_level++; + nodes_at_level_head = insert_in_int_list(nodes_at_level_head, inode, + &free_list_head); + } + } + + alloc_ivector_and_copy_int_list(&nodes_at_level_head, num_at_level, + &tnodes_at_level[0], &free_list_head); + + num_levels = 0; + + while (num_at_level != 0) { /* Until there's nothing in the queue. */ + num_levels++; + num_at_level = 0; + + for (i = 0; i < tnodes_at_level[num_levels - 1].nelem; i++) { + inode = tnodes_at_level[num_levels - 1].list[i]; + tedge = tnode[inode].out_edges; + num_edges = tnode[inode].num_edges; + + for (iedge = 0; iedge < num_edges; iedge++) { + to_node = tedge[iedge].to_node; + tnode_fanin_left[to_node]--; + + if (tnode_fanin_left[to_node] == 0) { + num_at_level++; + nodes_at_level_head = insert_in_int_list( + nodes_at_level_head, to_node, &free_list_head); + } + } + } + + alloc_ivector_and_copy_int_list(&nodes_at_level_head, num_at_level, + &tnodes_at_level[num_levels], &free_list_head); + } + + tnodes_at_level = (struct s_ivec *) my_realloc(tnodes_at_level, + num_levels * sizeof(struct s_ivec)); + num_tnode_levels = num_levels; + + free(tnode_fanin_left); + free_int_list(&free_list_head); + return (num_sinks); +} + +void check_timing_graph(int num_sinks) { + + /* Checks the timing graph to see that: (1) all the tnodes have been put * + * into some level of the timing graph; */ + + /* Addition error checks that need to be done but not yet implemented: (2) the number of primary inputs * + * to the timing graph is equal to the number of input pads + the number of * + * constant generators; and (3) the number of sinks (nodes with no fanout) * + * equals the number of output pads + the number of flip flops. */ + + int num_tnodes_check, ilevel, error; + + error = 0; + num_tnodes_check = 0; + + /* TODO: Rework error checks for I/Os*/ + + for (ilevel = 0; ilevel < num_tnode_levels; ilevel++) + num_tnodes_check += tnodes_at_level[ilevel].nelem; + + if (num_tnodes_check != num_tnodes) { + vpr_printf(TIO_MESSAGE_ERROR, "Error in check_timing_graph: %d tnodes appear in the tnode level structure. Expected %d.\n", + num_tnodes_check, num_tnodes); + vpr_printf(TIO_MESSAGE_INFO, "Check the netlist for combinational cycles.\n"); + if (num_tnodes > num_tnodes_check) { + show_combinational_cycle_candidates(); + } + error++; + } + /* Todo: Add error checks that # of flip-flops, memories, and other + black boxes match # of sinks/sources*/ + + if (error != 0) { + vpr_printf(TIO_MESSAGE_ERROR, "Found %d Errors in the timing graph. Aborting.\n", error); + exit(1); + } +} + +float print_critical_path_node(FILE * fp, t_linked_int * critical_path_node) { + + /* Prints one tnode on the critical path out to fp. Returns the delay to the next node. */ + + int inode, iblk, inet, downstream_node; + t_pb_graph_pin * pb_graph_pin; + e_tnode_type type; + static const char *tnode_type_names[] = { "TN_INPAD_SOURCE", "TN_INPAD_OPIN", + "TN_OUTPAD_IPIN", "TN_OUTPAD_SINK", "TN_CB_IPIN", "TN_CB_OPIN", + "TN_INTERMEDIATE_NODE", "TN_PRIMITIVE_IPIN", "TN_PRIMITIVE_OPIN", "TN_FF_IPIN", + "TN_FF_OPIN", "TN_FF_SINK", "TN_FF_SOURCE", "TN_FF_CLOCK", "TN_CONSTANT_GEN_SOURCE" }; + + t_linked_int *next_crit_node; + float Tdel; + + inode = critical_path_node->data; + type = tnode[inode].type; + iblk = tnode[inode].block; + pb_graph_pin = tnode[inode].pb_graph_pin; + + fprintf(fp, "Node: %d %s Block #%d (%s)\n", inode, tnode_type_names[type], + iblk, block[iblk].name); + + if (pb_graph_pin == NULL) { + assert( + type == TN_INPAD_SOURCE || type == TN_OUTPAD_SINK || type == TN_FF_SOURCE || type == TN_FF_SINK); + } + + if (pb_graph_pin != NULL) { + fprintf(fp, "Pin: %s.%s[%d] pb (%s)", pb_graph_pin->parent_node->pb_type->name, + pb_graph_pin->port->name, pb_graph_pin->pin_number, block[iblk].pb->rr_node_to_pb_mapping[pb_graph_pin->pin_count_in_cluster]->name); + } + if (type != TN_INPAD_SOURCE && type != TN_OUTPAD_SINK) { + fprintf(fp, "\n"); + } + + fprintf(fp, "T_arr: %g T_req: %g ", tnode[inode].T_arr, + tnode[inode].T_req); + + next_crit_node = critical_path_node->next; + if (next_crit_node != NULL) { + downstream_node = next_crit_node->data; + Tdel = tnode[downstream_node].T_arr - tnode[inode].T_arr; + fprintf(fp, "Tdel: %g\n", Tdel); + } else { /* last node, no Tdel. */ + Tdel = 0.; + fprintf(fp, "\n"); + } + + if (type == TN_CB_OPIN) { + inet = + block[iblk].pb->rr_graph[pb_graph_pin->pin_count_in_cluster].net_num; + inet = vpack_to_clb_net_mapping[inet]; + fprintf(fp, "External-to-Block Net: #%d (%s). Pins on net: %d.\n", + inet, clb_net[inet].name, (clb_net[inet].num_sinks + 1)); + } else if (pb_graph_pin != NULL) { + inet = + block[iblk].pb->rr_graph[pb_graph_pin->pin_count_in_cluster].net_num; + fprintf(fp, "Internal Net: #%d (%s). Pins on net: %d.\n", inet, + vpack_net[inet].name, (vpack_net[inet].num_sinks + 1)); + } + + fprintf(fp, "\n"); + return (Tdel); +} + +/* Display nodes that are likely in combinational cycles */ +static void show_combinational_cycle_candidates() { + boolean *found_tnode; + int ilevel, i, inode; + + found_tnode = (boolean*) my_calloc(num_tnodes, sizeof(boolean)); + + for (ilevel = 0; ilevel < num_tnode_levels; ilevel++) { + for (i = 0; i < tnodes_at_level[ilevel].nelem; i++) { + inode = tnodes_at_level[ilevel].list[i]; + found_tnode[inode] = TRUE; + } + } + + vpr_printf(TIO_MESSAGE_INFO, "\tProblematic nodes:\n"); + for (i = 0; i < num_tnodes; i++) { + if (found_tnode[i] == FALSE) { + vpr_printf(TIO_MESSAGE_INFO, "\t\ttnode %d ", i); + if (tnode[i].pb_graph_pin == NULL) { + vpr_printf(TIO_MESSAGE_INFO, "block %s port %d pin %d\n", logical_block[tnode[i].block].name, tnode[i].prepacked_data->model_port, tnode[i].prepacked_data->model_pin); + } else { + vpr_printf(TIO_MESSAGE_INFO, "\n"); + } + } + } + + free(found_tnode); +} + diff --git a/vpr7_rram/vpr/SRC/timing/path_delay2.h b/vpr7_rram/vpr/SRC/timing/path_delay2.h new file mode 100755 index 000000000..6e9459a1f --- /dev/null +++ b/vpr7_rram/vpr/SRC/timing/path_delay2.h @@ -0,0 +1,21 @@ +/*********** Types and defines used by all path_delay modules ****************/ + +extern t_tnode *tnode; /* [0..num_tnodes - 1] */ +extern int num_tnodes; /* Number of nodes in the timing graph */ + +extern int num_tnode_levels; /* Number of levels in the timing graph. */ + +extern struct s_ivec *tnodes_at_level; +/* [0..num__tnode_levels - 1]. Count and list of tnodes at each level of + * the timing graph, to make topological searches easier. Level-0 nodes are + * sources to the timing graph (types TN_FF_SOURCE, TN_INPAD_SOURCE + * and TN_CONSTANT_GEN_SOURCE). Level-N nodes are in the immediate fanout of + * nodes with level at most N-1. */ + +/***************** Subroutines exported by this module ***********************/ + +int alloc_and_load_timing_graph_levels(void); + +void check_timing_graph(int num_sinks); + +float print_critical_path_node(FILE * fp, t_linked_int * critical_path_node); diff --git a/vpr7_rram/vpr/SRC/timing/read_sdc.c b/vpr7_rram/vpr/SRC/timing/read_sdc.c new file mode 100644 index 000000000..b55689f11 --- /dev/null +++ b/vpr7_rram/vpr/SRC/timing/read_sdc.c @@ -0,0 +1,1337 @@ +#include +#include +#include +#include +#include "assert.h" +#include "util.h" +#include "vpr_types.h" +#include "globals.h" +#include "read_sdc.h" +#include "read_blif.h" +#include "path_delay.h" +#include "path_delay2.h" +#include "ReadOptions.h" +#include "slre.h" + +/***************************** Summary **********************************/ + +/* Author: Michael Wainberg + +Looks for an SDC (Synopsys Design Constraints) file called .sdc +(unless overridden with --sdc_file on the command-line, in which +case it looks for that filename), and parses the timing constraints in that file. +If it doesn't find a file with that name, it uses default timing constraints +(which differ depending on whether the circuit has 0, 1, or multiple clocks). + +The primary routine, read_sdc, populates a container structure, g_sdc. +One of the two key output data structures within is g_sdc->constrained_clocks, which +associates each clock given a timing constraint with a name, fanout and whether +it is a netlist or virtual (external) clock. From this point on, the only clocks +we care about are the ones in this array. During timing analysis and data output, +clocks are accessed using the indexing of this array. + +The other key data structure is the "constraint matrix" g_sdc->domain_constraint, which +has a timing constraint for each pair (source and sink) of clock domains. These +generally come from finding the smallest difference between the posedges of the +two clocks over the LCM clock period ("edge counting" - see calculate_constraint()). + +Alternatively, entries in g_sdc->domain_constraint can come from a special-case, "override +constraint" (so named because it overrides the default behaviour of edge counting). +Override constraints can cut paths (set_clock_groups, set_false_path commands), +create a multicycle (set_multicycle_path) or even override a constraint with a user- +specified one (set_max_delay). These entries are stored temporarily in g_sdc->cc_constraints +(cc = clock to clock), which is freed once the timing_constraints echo file is +created during process_constraints(). + +Flip-flop-level override constraints also exist and are stored in g_sdc->cf_constraints, +g_sdc->fc_constraints and g_sdc->ff_constraints (depending on whether the source, sink or neither +of the two is a clock domain).Unlike g_sdc->cc_constraints, they are placed on the timing +graph during timing analysis instead of going into g_sdc->domain_constraint, and are not +freed until the end of VPR's execution. + +I/O constraints from set_input_delay and set_output_delay are stored in constrained_ +inputs and g_sdc->constrained_outputs. These associate each I/O in the netlist given a +constraint with the clock (often virtual, but could be in the netlist) it was +constrained on, and the delay through the I/O in that constraint. + +The remaining data structures are temporary and local to this file: netlist_clocks, +netlist_inputs and netlist_outputs, which are used to match names of clocks and I/Os +in the SDC file to those in the netlist; sdc_clocks, which stores info on clock periods +and offsets from create_clock commands and is the raw info used in edge counting; and +exclusive_groups, used when parsing set_clock_groups commands into g_sdc->cc_constraints. */ + +/*********************** Externally-accessible variables **************************/ + +t_timing_constraints * g_sdc = NULL; + +/****************** Types local to this module **************************/ + +typedef struct s_sdc_clock { + char * name; + float period; + float rising_edge; + float falling_edge; +} t_sdc_clock; +/* Stores the name, period and offset of each constrained clock. */ + +typedef struct s_sdc_exclusive_group { + char ** clock_names; + int num_clock_names; +} t_sdc_exclusive_group; +/* Used to temporarily separate clock names into exclusive groups when parsing the +command set_clock_groups -exclusive. */ + +/****************** Variables local to this module **************************/ + +static FILE *sdc; +t_sdc_clock * sdc_clocks = NULL; /* List of clock periods and offsets from create_clock commands */ + +int num_netlist_clocks = 0; /* number of clocks in netlist */ +char ** netlist_clocks; /* [0..num_netlist_clocks - 1] array of names of clocks in netlist */ + +int num_netlist_ios = 0; /* number of clocks in netlist */ +char ** netlist_ios; /* [0..num_netlist_clocks - 1] array of names of ios in netlist */ + +/***************** Subroutines local to this module *************************/ + +static void alloc_and_load_netlist_clocks_and_ios(void); +static void use_default_timing_constraints(void); +static void count_netlist_clocks_as_constrained_clocks(void); +static boolean get_sdc_tok(char * buf); +static boolean is_number(char * ptr); +static int find_constrained_clock(char * ptr); +static float calculate_constraint(t_sdc_clock source_domain, t_sdc_clock sink_domain); +static void add_override_constraint(char ** from_list, int num_from, char ** to_list, int num_to, + float constraint, int num_multicycles, boolean domain_level_from, boolean domain_level_to, + boolean make_copies); +static int find_cc_constraint(char * source_clock_domain, char * sink_clock_domain); +static boolean regex_match (char *string, char *pattern); +static void count_netlist_ios_as_constrained_ios(char * clock_name, float io_delay); +static void free_io_constraint(t_io *& io_array, int num_ios); +static void free_clock_constraint(t_clock *& clock_array, int num_clocks); + +/********************* Subroutine definitions *******************************/ + +void read_sdc(t_timing_inf timing_inf) { + + char buf[BUFSIZE]; + int source_clock_domain, sink_clock_domain, iinput, ioutput, icc, isource, isink; + boolean found; + + /* Make sure we haven't called this subroutine before. */ + assert(!g_sdc); + + /* Allocate container structure for SDC constraints. */ + g_sdc = (t_timing_constraints *) my_calloc(1, sizeof(t_timing_constraints)); + + /* Reset file line number. */ + file_line_number = 0; + + /* If no SDC file is included or specified, or timing analysis is off, + use default behaviour of cutting paths between domains and optimizing each clock separately */ + + if (!timing_inf.timing_analysis_enabled) { + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "Timing analysis off; using default timing constraints.\n"); + use_default_timing_constraints(); + return; + } + + if ((sdc = fopen(timing_inf.SDCFile, "r")) == NULL) { + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "SDC file '%s' blank or not found.\n", timing_inf.SDCFile); + use_default_timing_constraints(); + return; + } + + /* Now we have an SDC file. */ + + /* Count how many clocks and I/Os are in the netlist. + Store the names of each clock and each I/O in netlist_clocks and netlist_ios. + The only purpose of these two lists is to compare clock names in the SDC file against them. + As a result, they will be freed after the SDC file is parsed. */ + alloc_and_load_netlist_clocks_and_ios(); + + /* Parse the file line-by-line. */ + found = FALSE; + while (my_fgets(buf, BUFSIZE, sdc) != NULL) { + if (get_sdc_tok(buf)) { + found = TRUE; + } + } + if (!found) { /* blank file or only comments found */ + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "SDC file '%s' blank or not found.\n", timing_inf.SDCFile); + use_default_timing_constraints(); + free(netlist_clocks); + free(netlist_ios); + return; + } + + fclose(sdc); + + /* Make sure that all virtual clocks referenced in g_sdc->constrained_inputs and g_sdc->constrained_outputs have been constrained. */ + for (iinput = 0; iinput < g_sdc->num_constrained_inputs; iinput++) { + if ((find_constrained_clock(g_sdc->constrained_inputs[iinput].clock_name)) == -1) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Input %s is associated with an unconstrained clock %s.\n", + g_sdc->constrained_inputs[iinput].file_line_number, + g_sdc->constrained_inputs[iinput].name, + g_sdc->constrained_inputs[iinput].clock_name); + exit(1); + } + } + + for (ioutput = 0; ioutput < g_sdc->num_constrained_outputs; ioutput++) { + if ((find_constrained_clock(g_sdc->constrained_outputs[ioutput].clock_name)) == -1) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Output %s is associated with an unconstrained clock %s.\n", + g_sdc->constrained_inputs[iinput].file_line_number, + g_sdc->constrained_outputs[ioutput].name, + g_sdc->constrained_outputs[ioutput].clock_name); + exit(1); + } + } + + /* Make sure that all clocks referenced in g_sdc->cc_constraints have been constrained. */ + for (icc = 0; icc < g_sdc->num_cc_constraints; icc++) { + for (isource = 0; isource < g_sdc->cc_constraints[icc].num_source; isource++) { + if ((find_constrained_clock(g_sdc->cc_constraints[icc].source_list[isource])) == -1) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Token %s is not a constrained clock.\n", + g_sdc->cc_constraints[icc].file_line_number, + g_sdc->cc_constraints[icc].source_list[isource]); + exit(1); + } + } + for (isink = 0; isink < g_sdc->cc_constraints[icc].num_sink; isink++) { + if ((find_constrained_clock(g_sdc->cc_constraints[icc].sink_list[isink])) == -1) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Token %s is not a constrained clock.\n", + g_sdc->cc_constraints[icc].file_line_number, + g_sdc->cc_constraints[icc].sink_list[isink]); + exit(1); + } + } + } + + /* Allocate matrix of timing constraints [0..g_sdc->num_constrained_clocks-1][0..g_sdc->num_constrained_clocks-1] and initialize to 0 */ + g_sdc->domain_constraint = (float **) alloc_matrix(0, g_sdc->num_constrained_clocks-1, 0, g_sdc->num_constrained_clocks-1, sizeof(float)); + + /* Based on the information from sdc_clocks, calculate constraints for all paths except ones with an override constraint. */ + for (source_clock_domain = 0; source_clock_domain < g_sdc->num_constrained_clocks; source_clock_domain++) { + for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { + if ((icc = find_cc_constraint(g_sdc->constrained_clocks[source_clock_domain].name, g_sdc->constrained_clocks[sink_clock_domain].name)) != -1) { + if (g_sdc->cc_constraints[icc].num_multicycles == 0) { + /* There's a special constraint from set_false_path, set_clock_groups + -exclusive or set_max_delay which overrides the default constraint. */ + g_sdc->domain_constraint[source_clock_domain][sink_clock_domain] = g_sdc->cc_constraints[icc].constraint; + } else { + /* There's a special constraint from set_multicycle_path which overrides the default constraint. + This constraint = default constraint (obtained via edge counting) + (num_multicycles - 1) * period of sink clock domain. */ + g_sdc->domain_constraint[source_clock_domain][sink_clock_domain] = + calculate_constraint(sdc_clocks[source_clock_domain], sdc_clocks[sink_clock_domain]) + + (g_sdc->cc_constraints[icc].num_multicycles - 1) * sdc_clocks[sink_clock_domain].period; + } + } else { + /* There's no special override constraint. */ + /* Calculate the constraint between clock domains by finding the smallest positive + difference between a posedge in the source domain and one in the sink domain. */ + g_sdc->domain_constraint[source_clock_domain][sink_clock_domain] = + calculate_constraint(sdc_clocks[source_clock_domain], sdc_clocks[sink_clock_domain]); + } + } + } + + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "SDC file '%s' parsed successfully.\n", + timing_inf.SDCFile ); + vpr_printf(TIO_MESSAGE_INFO, "%d clocks (including virtual clocks), %d inputs and %d outputs were constrained.\n", + g_sdc->num_constrained_clocks, g_sdc->num_constrained_inputs, g_sdc->num_constrained_outputs); + vpr_printf(TIO_MESSAGE_INFO, "\n"); + + /* Since all the information we need is stored in g_sdc->domain_constraint, g_sdc->constrained_clocks, + and constrained_ios, free other data structures used in this routine */ + free(sdc_clocks); + free(netlist_clocks); + free(netlist_ios); + return; +} + +static void use_default_timing_constraints(void) { + + int source_clock_domain, sink_clock_domain; + + /* Find all netlist clocks and add them as constrained clocks. */ + count_netlist_clocks_as_constrained_clocks(); + + /* We'll use separate defaults for multi-clock and single-clock/combinational circuits. */ + + if (g_sdc->num_constrained_clocks <= 1) { + /* Create one constrained clock with period 0... */ + g_sdc->domain_constraint = (float **) alloc_matrix(0, 0, 0, 0, sizeof(float)); + g_sdc->domain_constraint[0][0] = 0.; + + if (g_sdc->num_constrained_clocks == 0) { + /* We need to create a virtual clock to constrain I/Os on. */ + g_sdc->num_constrained_clocks = 1; + g_sdc->constrained_clocks = (t_clock *) my_malloc(sizeof(t_clock)); + g_sdc->constrained_clocks[0].name = my_strdup("virtual_io_clock"); + g_sdc->constrained_clocks[0].is_netlist_clock = FALSE; + + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "Defaulting to: constrain all %d inputs and %d outputs on a virtual external clock.\n", + g_sdc->num_constrained_inputs, g_sdc->num_constrained_outputs); + vpr_printf(TIO_MESSAGE_INFO, "Optimize this virtual clock to run as fast as possible.\n"); + } else { + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "Defaulting to: constrain all %d inputs and %d outputs on the netlist clock.\n", + g_sdc->num_constrained_inputs, g_sdc->num_constrained_outputs); + vpr_printf(TIO_MESSAGE_INFO, "Optimize this clock to run as fast as possible.\n"); + } + + /* Constrain all I/Os on the single constrained clock (whether real or virtual), with I/O delay 0. */ + count_netlist_ios_as_constrained_ios(g_sdc->constrained_clocks[0].name, 0.); + + } else { /* Multiclock circuit */ + + /* Constrain all I/Os on a separate virtual clock. Cut paths between all netlist + clocks, but analyse all paths between the virtual I/O clock and netlist clocks + and optimize all clocks to go as fast as possible. */ + + g_sdc->constrained_clocks = (t_clock *) my_realloc (g_sdc->constrained_clocks, ++g_sdc->num_constrained_clocks * sizeof(t_clock)); + g_sdc->constrained_clocks[g_sdc->num_constrained_clocks - 1].name = my_strdup("virtual_io_clock"); + g_sdc->constrained_clocks[g_sdc->num_constrained_clocks - 1].is_netlist_clock = FALSE; + count_netlist_ios_as_constrained_ios(g_sdc->constrained_clocks[g_sdc->num_constrained_clocks - 1].name, 0.); + + /* Allocate matrix of timing constraints [0..g_sdc->num_constrained_clocks-1][0..g_sdc->num_constrained_clocks-1] */ + g_sdc->domain_constraint = (float **) alloc_matrix(0, g_sdc->num_constrained_clocks-1, 0, g_sdc->num_constrained_clocks-1, sizeof(float)); + + for (source_clock_domain = 0; source_clock_domain < g_sdc->num_constrained_clocks; source_clock_domain++) { + for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { + if (source_clock_domain == sink_clock_domain || source_clock_domain == g_sdc->num_constrained_clocks - 1 + || sink_clock_domain == g_sdc->num_constrained_clocks - 1) { + g_sdc->domain_constraint[source_clock_domain][sink_clock_domain] = 0.; + } else { + g_sdc->domain_constraint[source_clock_domain][sink_clock_domain] = DO_NOT_ANALYSE; + } + } + } + + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "Defaulting to: constrain all %d inputs and %d outputs on a virtual external clock;\n", + g_sdc->num_constrained_inputs, g_sdc->num_constrained_outputs); + vpr_printf(TIO_MESSAGE_INFO, "\tcut paths between netlist clock domains; and\n"); + vpr_printf(TIO_MESSAGE_INFO, "\toptimize all clocks to run as fast as possible.\n"); + } +} + +static void alloc_and_load_netlist_clocks_and_ios(void) { + + /* Count how many clocks and I/Os are in the netlist. + Store the names of each clock and each I/O in netlist_clocks and netlist_ios. */ + + int iblock, i, clock_net; + char * name; + boolean found; + + for (iblock = 0; iblock < num_logical_blocks; iblock++) { + if (logical_block[iblock].clock_net != OPEN) { + clock_net = logical_block[iblock].clock_net; + assert(clock_net != OPEN); + name = logical_block[clock_net].name; + /* Now that we've found a clock, let's see if we've counted it already */ + found = FALSE; + for (i = 0; !found && i < num_netlist_clocks; i++) { + if (strcmp(netlist_clocks[i], name) == 0) { + found = TRUE; + } + } + if (!found) { + /* If we get here, the clock is new and so we dynamically grow the array netlist_clocks by one. */ + netlist_clocks = (char **) my_realloc (netlist_clocks, ++num_netlist_clocks * sizeof(char *)); + netlist_clocks[num_netlist_clocks - 1] = name; + } + } else if (logical_block[iblock].type == VPACK_INPAD || logical_block[iblock].type == VPACK_OUTPAD) { + name = logical_block[iblock].name; + /* Now that we've found an I/O, let's see if we've counted it already */ + found = FALSE; + for (i = 0; !found && i < num_netlist_ios; i++) { + if (strcmp(netlist_ios[i], name) == 0) { + found = TRUE; + } + } + if (!found) { + /* If we get here, the I/O is new and so we dynamically grow the array netlist_ios by one. */ + netlist_ios = (char **) my_realloc (netlist_ios, ++num_netlist_ios * sizeof(char *)); + netlist_ios[num_netlist_ios - 1] = logical_block[iblock].type == VPACK_OUTPAD ? name + 4 : name; + /* the + 4 removes the prefix "out:" automatically prepended to outputs */ + } + } + } +} + +static void count_netlist_clocks_as_constrained_clocks(void) { + /* Counts how many clocks are in the netlist, and adds them to the array g_sdc->constrained_clocks. */ + + int iblock, i, clock_net; + char * name; + boolean found; + + g_sdc->num_constrained_clocks = 0; + + for (iblock = 0; iblock < num_logical_blocks; iblock++) { + if (logical_block[iblock].clock_net != OPEN) { + clock_net = logical_block[iblock].clock_net; + assert(clock_net != OPEN); + name = logical_block[clock_net].name; + /* Now that we've found a clock, let's see if we've counted it already */ + found = FALSE; + for (i = 0; !found && i < g_sdc->num_constrained_clocks; i++) { + if (strcmp(g_sdc->constrained_clocks[i].name, name) == 0) { + found = TRUE; + } + } + if (!found) { + /* If we get here, the clock is new and so we dynamically grow the array g_sdc->constrained_clocks by one. */ + g_sdc->constrained_clocks = (t_clock *) my_realloc (g_sdc->constrained_clocks, ++g_sdc->num_constrained_clocks * sizeof(t_clock)); + g_sdc->constrained_clocks[g_sdc->num_constrained_clocks - 1].name = my_strdup(name); + g_sdc->constrained_clocks[g_sdc->num_constrained_clocks - 1].is_netlist_clock = TRUE; + /* Fanout will be filled out once the timing graph has been constructed. */ + } + } + } +} + +static void count_netlist_ios_as_constrained_ios(char * clock_name, float io_delay) { + /* Count how many I/Os are in the netlist, adds them to the arrays g_sdc->constrained_inputs/ + g_sdc->constrained_outputs with an I/O delay of 0 and constrains them to clock clock_name. */ + + int iblock, iinput, ioutput; + char * name; + boolean found; + + for (iblock = 0; iblock < num_logical_blocks; iblock++) { + if (logical_block[iblock].type == VPACK_INPAD) { + name = logical_block[iblock].name; + /* Now that we've found an I/O, let's see if we've counted it already */ + found = FALSE; + for (iinput = 0; !found && iinput < g_sdc->num_constrained_inputs; iinput++) { + if (strcmp(g_sdc->constrained_inputs[iinput].name, name) == 0) { + found = TRUE; + } + } + if (!found) { + /* If we get here, the input is new and so we add it to g_sdc->constrained_inputs. */ + g_sdc->constrained_inputs = (t_io *) my_realloc (g_sdc->constrained_inputs, ++g_sdc->num_constrained_inputs * sizeof(t_io)); + g_sdc->constrained_inputs[g_sdc->num_constrained_inputs - 1].name = my_strdup(name); + g_sdc->constrained_inputs[g_sdc->num_constrained_inputs - 1].clock_name = my_strdup(clock_name); + g_sdc->constrained_inputs[g_sdc->num_constrained_inputs - 1].delay = 0.; + } + } else if (logical_block[iblock].type == VPACK_OUTPAD) { + name = logical_block[iblock].name; + /* Now that we've found an I/O, let's see if we've counted it already */ + found = FALSE; + for (ioutput = 0; !found && ioutput < g_sdc->num_constrained_outputs; ioutput++) { + if (strcmp(g_sdc->constrained_outputs[ioutput].name, name) == 0) { + found = TRUE; + } + } + if (!found) { + /* If we get here, the output is new and so we add it to g_sdc->constrained_outputs. */ + g_sdc->constrained_outputs = (t_io *) my_realloc (g_sdc->constrained_outputs, ++g_sdc->num_constrained_outputs * sizeof(t_io)); + g_sdc->constrained_outputs[g_sdc->num_constrained_outputs - 1].name = my_strdup(name + 4); + /* the + 4 removes the prefix "out:" automatically prepended to outputs */ + g_sdc->constrained_outputs[g_sdc->num_constrained_outputs - 1].clock_name = my_strdup(clock_name); + g_sdc->constrained_outputs[g_sdc->num_constrained_outputs - 1].delay = 0.; + } + } + } +} + +static boolean get_sdc_tok(char * buf) { +/* Figures out which tokens are on this line and takes the appropriate actions. + Returns true if anything non-commented is found on this line. */ + +#define SDC_TOKENS " \t\n{}[]" /* We can ignore braces. */ + + char * ptr, ** from_list = NULL, ** to_list = NULL, * clock_name; + float clock_period, rising_edge, falling_edge, max_delay; + int iclock, iio, num_exclusive_groups = 0, + num_from = 0, num_to = 0, num_multicycles, i, j; + t_sdc_exclusive_group * exclusive_groups = NULL; + boolean found, domain_level_from = FALSE, domain_level_to = FALSE; + + /* my_strtok splits the string into tokens - little character arrays separated by the SDC_TOKENS + defined above. Throughout this code, ptr refers to the tokens we fetch, one at a time. The token + changes at each call of my_strtok. We call my_strtok with NULL as the first argument every time + AFTER the first, since this picks up tokenizing where we left off. We always wrap each call to + my_strtok with a check that ptr is non-null to avoid an exception from passing NULL into strcmp. */ + + + if ((ptr = my_strtok(buf, SDC_TOKENS, sdc, buf)) == NULL) {/* blank line */ + return FALSE; + } + + if (strcmp(ptr, "create_clock") == 0) { + /* Syntax: create_clock -period [-waveform {rising_edge falling_edge}] + or create_clock -period [-waveform {rising_edge falling_edge}] -name */ + + /* make sure clock has -period specified */ + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "-period") != 0) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Create_clock must be directly followed by '-period'.\n", + file_line_number); + exit(1); + } + + /* Check if the token following -period is actually a number. */ + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || !is_number(ptr)) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] A number must follow '-period'.\n", + file_line_number); + exit(1); + } + clock_period = (float) strtod(ptr, NULL); + + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Clock(s) not specified.\n", + file_line_number); + exit(1); + } + if (strcmp(ptr, "-waveform") == 0) { + + /* Get the first float, which is the rising edge, and the second, which is the falling edge. */ + + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || !is_number(ptr)) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] First token following '-waveform' should be rising edge, but is not a number.\n", + file_line_number); + } + rising_edge = (float) strtod(ptr, NULL); + + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || !is_number(ptr)) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Second token following '-waveform' should be falling edge, but is not a number.\n", + file_line_number); + exit(1); + } + falling_edge = (float) strtod(ptr, NULL); + + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Clock(s) not specified.\n", + file_line_number); + exit(1); + } /* We need this extra call to my_strtok to advance the ptr to the right spot. */ + + } else { + /* The clock's rising edge is by default at 0, and the falling edge is at the half-period. */ + rising_edge = 0.; + falling_edge = clock_period / 2.0; + } + + if (strcmp(ptr, "-name") == 0) { + /* For external virtual clocks only (used with I/O constraints). + Only one virtual clock can be specified per line, + so make sure there's only one token left on this line. */ + + /* Get the virtual clock name */ + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Virtual clock name not specified.\n", + file_line_number); + exit(1); + } /* We need this extra call to my_strtok to advance the ptr to the right spot. */ + + /* We've found a new clock! */ + + /* Store the clock's name, period and edges in the local array sdc_clocks. */ + sdc_clocks = (t_sdc_clock *) my_realloc(sdc_clocks, ++g_sdc->num_constrained_clocks * sizeof(t_sdc_clock)); + sdc_clocks[g_sdc->num_constrained_clocks - 1].name = ptr; + sdc_clocks[g_sdc->num_constrained_clocks - 1].period = clock_period; + sdc_clocks[g_sdc->num_constrained_clocks - 1].rising_edge = rising_edge; + sdc_clocks[g_sdc->num_constrained_clocks - 1].falling_edge = falling_edge; + + /* Also store the clock's name, and the fact that it is not a netlist clock, in g_sdc->constrained_clocks. */ + g_sdc->constrained_clocks = (t_clock *) my_realloc (g_sdc->constrained_clocks, g_sdc->num_constrained_clocks * sizeof(t_clock)); + g_sdc->constrained_clocks[g_sdc->num_constrained_clocks - 1].name = my_strdup(ptr); + g_sdc->constrained_clocks[g_sdc->num_constrained_clocks - 1].is_netlist_clock = FALSE; + /* Fanout will be filled out once the timing graph has been constructed. */ + + /* The next token should be NULL. If so, return; if not, print an error message and exit. */ + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) != NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] More than one virtual clock name is specified after '-name'.\n", + file_line_number); + exit(1); + } + + } else { + /* Parse through to the end of the line. All that should be left on this line are one or more + * regular expressions denoting netlist clocks to be associated with this clock period. An array sdc_clocks will + * store the period and offset of each clock at the same index which that clock has in netlist_clocks. Later, + * after everything has been parsed, we take the information from this array to calculate the actual timing constraints + * which these periods and offsets imply, and put them in the matrix g_sdc->domain_constraint. */ + + do { + /* See if the regular expression stored in ptr is legal and matches at least one clock net. + If it is not legal, it will fail during regex_match. We check for a match using boolean found. */ + found = FALSE; + for (iclock = 0; iclock < num_netlist_clocks; iclock++) { + if (regex_match(netlist_clocks[iclock], ptr)) { + /* We've found a new clock! (Note that we can't store ptr as the clock's + name since it could be a regex, unlike the virtual clock case).*/ + found = TRUE; + + /* Store the clock's name, period and edges in the local array sdc_clocks. */ + sdc_clocks = (t_sdc_clock *) my_realloc(sdc_clocks, ++g_sdc->num_constrained_clocks * sizeof(t_sdc_clock)); + sdc_clocks[g_sdc->num_constrained_clocks - 1].name = netlist_clocks[iclock]; + sdc_clocks[g_sdc->num_constrained_clocks - 1].period = clock_period; + sdc_clocks[g_sdc->num_constrained_clocks - 1].rising_edge = rising_edge; + sdc_clocks[g_sdc->num_constrained_clocks - 1].falling_edge = falling_edge; + + /* Also store the clock's name, and the fact that it is a netlist clock, in g_sdc->constrained_clocks. */ + g_sdc->constrained_clocks = (t_clock *) my_realloc (g_sdc->constrained_clocks, g_sdc->num_constrained_clocks * sizeof(t_clock)); + g_sdc->constrained_clocks[g_sdc->num_constrained_clocks - 1].name = my_strdup(netlist_clocks[iclock]); + g_sdc->constrained_clocks[g_sdc->num_constrained_clocks - 1].is_netlist_clock = TRUE; + /* Fanout will be filled out once the timing graph has been constructed. */ + } + } + + if (!found) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Clock name or regular expression does not correspond to any nets.\n", + file_line_number); + vpr_printf(TIO_MESSAGE_ERROR, "If you'd like to create a virtual clock, use the '-name' keyword.\n"); + exit(1); + } + } while ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) != NULL); /* Advance to the next token (or the end of the line). */ + } + + /* Warn if the clock has non-50% duty cycle. */ + if (fabs(rising_edge - falling_edge) - clock_period/2.0 > EPSILON) { + vpr_printf(TIO_MESSAGE_WARNING, "Clock %s does not have 50%% duty cycle.\n", + sdc_clocks[g_sdc->num_constrained_clocks - 1].name); + } + + return TRUE; + + } else if (strcmp(ptr, "set_clock_groups") == 0) { + /* Syntax: set_clock_groups -exclusive -group {} -group {} [-group {} ...] */ + + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "-exclusive") != 0) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_clock_groups must be directly followed by '-exclusive'.\n", + file_line_number); + exit(1); + } + + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "-group") != 0) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_clock_groups '-exclusive' must be followed by lists of clock names or regular expressions each starting with the '-group' command.\n", + file_line_number); + exit(1); + } + + /* Parse through to the end of the line. All that should be left on this line are a bunch of + -group commands, followed by groups of regexes. We need to ensure that paths are cut between + every clock matching a regex in one group and every clock matching a regex in any other group. */ + + do { + ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf); + + /* Create a new entry in exclusive groups */ + exclusive_groups = (t_sdc_exclusive_group *) my_realloc( + exclusive_groups, ++num_exclusive_groups * sizeof(t_sdc_exclusive_group)); + exclusive_groups[num_exclusive_groups - 1].clock_names = NULL; + exclusive_groups[num_exclusive_groups - 1].num_clock_names = 0; + do { + /* Check the regex ptr against each netlist clock and add it to the clock_names list if it matches. */ + found = FALSE; + for (iclock = 0; iclock < num_netlist_clocks; iclock++) { + if (regex_match(netlist_clocks[iclock], ptr)) { + found = TRUE; + exclusive_groups[num_exclusive_groups - 1].clock_names = (char **) my_realloc( + exclusive_groups[num_exclusive_groups - 1].clock_names, ++exclusive_groups[num_exclusive_groups - 1].num_clock_names * sizeof(char *)); + exclusive_groups[num_exclusive_groups - 1].clock_names + [exclusive_groups[num_exclusive_groups - 1].num_clock_names - 1] = + my_strdup(netlist_clocks[iclock]); + } + } + if (!found) { + /* If no clocks matched, assume ptr is the name of a virtual clock and add it to the list. + (If it's not a virtual clock, we'll catch it later when we check all override constraints.) */ + exclusive_groups[num_exclusive_groups - 1].clock_names = (char **) my_realloc( + exclusive_groups[num_exclusive_groups - 1].clock_names, ++exclusive_groups[num_exclusive_groups - 1].num_clock_names * sizeof(char *)); + exclusive_groups[num_exclusive_groups - 1].clock_names + [exclusive_groups[num_exclusive_groups - 1].num_clock_names - 1] = + my_strdup(ptr); + } + } while ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) != NULL && strcmp(ptr, "-group") != 0); + } while (ptr); + + if (num_exclusive_groups < 2) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] At least two '-group' commands required.", + file_line_number); + exit(1); + } + + /* Finally, create two DO_NOT_ANALYSE override constraints for each pair of entries + to cut paths bidirectionally between pairs of clock lists in different groups. + Set make_copies to TRUE because we have to use the lists of names in multiple + override constraints, and it's impossible to free them from multiple places at the + end without a whole lot of trouble. */ + + for (i = 0; i < num_exclusive_groups; i++) { + for (j = 0; j < num_exclusive_groups; j++) { + if (i != j) { + add_override_constraint(exclusive_groups[i].clock_names, exclusive_groups[i].num_clock_names, + exclusive_groups[j].clock_names, exclusive_groups[j].num_clock_names, DO_NOT_ANALYSE, 0, TRUE, TRUE, TRUE); + } + } + } + + /* Now that we've copied all the clock name lists + (2 * num_exlusive_groups - 1) times, free the original lists. */ + for (i = 0; i < num_exclusive_groups; i++) { + for (j = 0; j < exclusive_groups[i].num_clock_names; j++) { + free(exclusive_groups[i].clock_names[j]); + } + free(exclusive_groups[i].clock_names); + } + free (exclusive_groups); + + return TRUE; + + } else if (strcmp(ptr, "set_false_path") == 0) { + /* Syntax: set_false_path -from -to */ + + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "-from") != 0 || (ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_false_path must be directly followed by '-from '.\n", + file_line_number); + exit(1); + } + + if (strcmp(ptr, "get_clocks") == 0) { + domain_level_from = TRUE; + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_false_path must be directly followed by '-from '.\n", + file_line_number); + exit(1); + } + } + + do { + /* Keep adding clock names to from_list until we hit the -to command. */ + from_list = (char **) my_realloc(from_list, ++num_from * sizeof(char *)); + from_list[num_from - 1] = my_strdup(ptr); + + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { + /* We hit the end of the line before finding a -to. */ + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_false_path requires '-to ' after '-from '.\n", + file_line_number); + exit(1); + } + } while (strcmp(ptr, "-to") != 0); + + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_false_path requires '-to ' after '-from '.\n", + file_line_number); + } + + if (strcmp(ptr, "get_clocks") == 0) { + domain_level_to = TRUE; + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_false_path must be directly followed by '-from '.\n", + file_line_number); + exit(1); + } + } + + do { + /* Keep adding clock names to to_list until we hit the end of the line. */ + to_list = (char **) my_realloc(to_list, ++num_to * sizeof(char *)); + to_list[num_to - 1] = my_strdup(ptr); + } while ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) != NULL); + + /* Create a constraint between each element in from_list and each element in to_list with value DO_NOT_ANALYSE. + Set make_copies to false since, as we only need to use from_list and to_list once, we can just have the + override constraint entry point to those lists. */ + add_override_constraint(from_list, num_from, to_list, num_to, DO_NOT_ANALYSE, 0, domain_level_from, domain_level_to, FALSE); + + /* Finally, set from_list and to_list to NULL since they're both + being pointed to by the override constraint entry we just created. */ + from_list = NULL, to_list = NULL; + + return TRUE; + + } else if (strcmp(ptr, "set_max_delay") == 0) { + /* Syntax: set_max_delay -from -to */ + + /* Basically the same as set_false_path above, except we get a specific delay value for the constraint. */ + + /* check if the token following set_max_delay is actually a number*/ + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || !is_number(ptr)) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Token following set_max_delay should be a delay value, but is not a number.\n", + file_line_number); + exit(1); + } + max_delay = (float) strtod(ptr, NULL); + + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "-from") != 0 || (ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_max_delay requires '-from ' after max_delay.\n", + file_line_number); + exit(1); + } + + if (strcmp(ptr, "get_clocks") == 0) { + domain_level_from = TRUE; + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_max_delay requires '-from ' after max_delay.\n", + file_line_number); + exit(1); + } + } + + do { + /* Keep adding clock names to from_list until we hit the -to command. */ + from_list = (char **) my_realloc(from_list, ++num_from * sizeof(char *)); + from_list[num_from - 1] = my_strdup(ptr); + + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { + /* We hit the end of the line before finding a -to. */ + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_max_delay requires '-to ' after '-from '.\n", + file_line_number); + exit(1); + } + } while (strcmp(ptr, "-to") != 0); + + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_max_delay requires '-to ' after '-from '.\n", + file_line_number); + } + + if (strcmp(ptr, "get_clocks") == 0) { + domain_level_to = TRUE; + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_max_delay requires '-to ' after '-from '.\n", + file_line_number); + exit(1); + } + } + + do { + /* Keep adding clock names to to_list until we hit the end of the line. */ + to_list = (char **) my_realloc(to_list, ++num_to * sizeof(char *)); + to_list[num_to - 1] = my_strdup(ptr); + } while ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) != NULL); + + /* Create a constraint between each element in from_list and each element in to_list with value max_delay. */ + add_override_constraint(from_list, num_from, to_list, num_to, max_delay, 0, domain_level_from, domain_level_to, FALSE); + + /* Finally, set from_list and to_list to NULL since they're both + being pointed to by the override constraint entry we just created. */ + from_list = NULL, to_list = NULL; + + return TRUE; + + } else if (strcmp(ptr, "set_multicycle_path") == 0) { + /* Syntax: set_multicycle_path -setup -from -to */ + + /* Basically the same as set_false_path and set_max_delay above, except we have to calculate + the default value of the constraint (obtained via edge counting) first, and then set a + constraint equal to default constraint + (num_multicycles - 1) * period of sink clock domain. */ + + /* check if the token following set_max_delay is actually a number*/ + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "-setup") != 0) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_multicycle_path must be directly followed by '-setup'.\n", + file_line_number); + exit(1); + } + + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "-from") != 0 || (ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_multicycle_path requires '-from ' after '-setup'.\n", + file_line_number); + exit(1); + } + + if (strcmp(ptr, "get_clocks") == 0) { + domain_level_from = TRUE; + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_multicycle_path '-setup' must be followed by '-from '.\n", + file_line_number); + exit(1); + } + } + + do { + /* Keep adding clock names to from_list until we hit the -to command. */ + from_list = (char **) my_realloc(from_list, ++num_from * sizeof(char *)); + from_list[num_from - 1] = my_strdup(ptr); + + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { + /* We hit the end of the line before finding a -to. */ + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_multicycle_path requires '-to ' after '-from '.\n", + file_line_number); + exit(1); + } + } while (strcmp(ptr, "-to") != 0); + + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_multicycle_path requires '-to ' after '-from '.\n", + file_line_number); + } + + if (strcmp(ptr, "get_clocks") == 0) { + domain_level_to = TRUE; + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_multicycle_path requires '-to ' after '-from '.\n", + file_line_number); + exit(1); + } + } + + do { + /* Keep adding clock names to to_list until we hit a number (i.e. num_multicycles). */ + to_list = (char **) my_realloc(to_list, ++num_to * sizeof(char *)); + to_list[num_to - 1] = my_strdup(ptr); + } while (((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) != NULL) && !is_number(ptr)); + + if (!ptr) { + /* We hit the end of the line before finding a number. */ + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_multicycle_path requires num_multicycles after '-to '.\n", + file_line_number); + exit(1); + } + + num_multicycles = (int) strtod(ptr, NULL); + + /* Create an override constraint between from and to. Unlike the previous two commands, set_multicycle_path requires + information about the periods and offsets of the clock domains which from and to, which we have to fill in at the end. */ + add_override_constraint(from_list, num_from, to_list, num_to, HUGE_NEGATIVE_FLOAT /* irrelevant - never used */, + num_multicycles, domain_level_from, domain_level_to, FALSE); + + /* Finally, set from_list and to_list to NULL since they're both + being pointed to by the override constraint entry we just created. */ + from_list = NULL, to_list = NULL; + + return TRUE; + + } else if (strcmp(ptr, "set_input_delay") == 0) { + /* Syntax: set_input_delay -clock -max [get_ports {}] */ + + /* We want to assign virtual_clock to all input ports in port_list, and + set the input delay (from the external device to the FPGA) to max_delay. */ + + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "-clock") != 0 || (ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_input_delay must be directly followed by '-clock '.\n", + file_line_number); + exit(1); + } + + if (num_netlist_clocks == 1 && strcmp(ptr, "*") == 0) { + /* Allow the user to wildcard the clock name if there's only one clock (not standard SDC but very convenient). */ + clock_name = netlist_clocks[0]; + } else { + /* We have no way of error-checking whether this is an actual virtual clock until we finish parsing. */ + clock_name = ptr; + } + + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "-max") != 0) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_input_delay '-clock ' must be directly followed by '-max '.\n", + file_line_number); + exit(1); + } + + /* check if the token following -max is actually a number*/ + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || !is_number(ptr)) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Token following '-max' should be a delay value, but is not a number.\n", + file_line_number); + exit(1); + } + max_delay = (float) strtod(ptr, NULL); + + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "get_ports") != 0) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_input_delay requires a [get_ports {...}] command following '-max '.\n", + file_line_number); + exit(1); + } + + /* Parse through to the end of the line. Add each regular expression match we find to the list of + constrained inputs and give each entry the virtual clock name and max_delay we've just parsed. + We have no way of error-checking whether these tokens correspond to actual input ports until later. */ + + for (;;) { + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { /* end of line */ + return TRUE; + } + + found = FALSE; + + for (iio = 0; iio < num_netlist_ios; iio++) { + /* See if the regular expression stored in ptr is legal and matches at least one input port. + If it is not legal, it will fail during regex_match. We check for a match using boolean found. */ + if (regex_match(netlist_ios[iio], ptr)) { + /* We've found a new input! */ + g_sdc->num_constrained_inputs++; + found = TRUE; + + /* Fill in input information in the permanent array g_sdc->constrained_inputs. */ + g_sdc->constrained_inputs = (t_io *) my_realloc (g_sdc->constrained_inputs, g_sdc->num_constrained_inputs * sizeof(t_io)); + g_sdc->constrained_inputs[g_sdc->num_constrained_inputs - 1].name = my_strdup(netlist_ios[iio]); + g_sdc->constrained_inputs[g_sdc->num_constrained_inputs - 1].clock_name = my_strdup(clock_name); + g_sdc->constrained_inputs[g_sdc->num_constrained_inputs - 1].delay = max_delay; + g_sdc->constrained_inputs[g_sdc->num_constrained_inputs - 1].file_line_number = file_line_number; /* global var */ + } + } + + if (!found) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Output name or regular expression \"%s\" does not correspond to any nets.\n", + file_line_number, ptr); + exit(1); + } + } + + } else if (strcmp(ptr, "set_output_delay") == 0) { + /* Syntax: set_output_delay -clock -max [get_ports {}] */ + + /* We want to assign virtual_clock to all output ports in port_list, and + set the output delay (from the external device to the FPGA) to max_delay. */ + + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "-clock") != 0 || (ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_output_delay must be directly followed by '-clock '.\n", + file_line_number); + exit(1); + } + + if (num_netlist_clocks == 1 && strcmp(ptr, "*") == 0) { + /* Allow the user to wildcard the clock name if there's only one clock (not standard SDC but very convenient). */ + clock_name = netlist_clocks[0]; + } else { + /* We have no way of error-checking whether this is an actual virtual clock until we finish parsing. */ + clock_name = ptr; + } + + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "-max") != 0) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_output_delay -clock must be directly followed by '-max '.\n", + file_line_number); + exit(1); + } + + /* check if the token following -max is actually a number*/ + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || !is_number(ptr)) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Token following '-max' should be a delay value, but is not a number.\n", + file_line_number); + exit(1); + } + max_delay = (float) strtod(ptr, NULL); + + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "get_ports") != 0) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_output_delay requires a [get_ports {...}] command following '-max '.\n", + file_line_number); + exit(1); + } + + /* Parse through to the end of the line. Add each regular expression match we find to the list of + constrained outputs and give each entry the virtual clock name and max_delay we've just parsed. + We have no way of error-checking whether these tokens correspond to actual output ports until later. */ + + for (;;) { + if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { /* end of line */ + return TRUE; + } + + found = FALSE; + + for (iio = 0; iio < num_netlist_ios; iio++) { + /* See if the regular expression stored in ptr is legal and matches at least one output port. + If it is not legal, it will fail during regex_match. We check for a match using boolean found. */ + if (regex_match(netlist_ios[iio], ptr)) { + /* We've found a new output! */ + g_sdc->num_constrained_outputs++; + found = TRUE; + + /* Fill in output information in the permanent array g_sdc->constrained_outputs. */ + g_sdc->constrained_outputs = (t_io *) my_realloc (g_sdc->constrained_outputs, g_sdc->num_constrained_outputs * sizeof(t_io)); + g_sdc->constrained_outputs[g_sdc->num_constrained_outputs - 1].name = my_strdup(netlist_ios[iio]); + g_sdc->constrained_outputs[g_sdc->num_constrained_outputs - 1].clock_name = my_strdup(clock_name); + g_sdc->constrained_outputs[g_sdc->num_constrained_outputs - 1].delay = max_delay; + g_sdc->constrained_outputs[g_sdc->num_constrained_outputs - 1].file_line_number = file_line_number; /* global var */ + } + } + + if (!found) { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Output name or regular expression \"%s\" does not correspond to any nets.\n", + file_line_number, ptr); + exit(1); + } + } + + } else { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Incorrect or unsupported syntax near start of line.\n", + file_line_number); + exit(1); + } +} + +static boolean is_number(char * ptr) { +/* Checks if the character array ptr represents a valid floating-point number. * + * To return TRUE, all characters must be digits, although * + * there can also be no more than one decimal point. */ + int i, len, num_decimal_points = 0; + len = strlen(ptr); + for (i = 0; i < len; i++) { + if ((ptr[i] < '0' || ptr[i] > '9')) { + if (ptr[i] != '.') { + return FALSE; + } + num_decimal_points++; + if (num_decimal_points > 1) { + return FALSE; + } + } + } + return TRUE; +} + +static int find_constrained_clock(char * ptr) { +/* Given a string ptr, find whether it's the name of a clock in the array g_sdc->constrained_clocks. * + * if it is, return the clock's index in g_sdc->constrained_clocks; if it's not, return -1. */ + int index; + for (index = 0; index < g_sdc->num_constrained_clocks; index++) { + if (strcmp(ptr, g_sdc->constrained_clocks[index].name) == 0) { + return index; + } + } + return -1; +} + +static int find_cc_constraint(char * source_clock_name, char * sink_clock_name) { + /* Given a pair of source and sink clock domains, find out if there's an override constraint between them. + If there is, return the index in g_sdc->cc_constraints; if there is not, return -1. */ + int icc, isource, isink; + + for (icc = 0; icc < g_sdc->num_cc_constraints; icc++) { + for (isource = 0; isource < g_sdc->cc_constraints[icc].num_source; isource++) { + if (strcmp(g_sdc->cc_constraints[icc].source_list[isource], source_clock_name) == 0) { + for (isink = 0; isink < g_sdc->cc_constraints[icc].num_sink; isink++) { + if (strcmp(g_sdc->cc_constraints[icc].sink_list[isink], sink_clock_name) == 0) { + return icc; + } + } + } + } + } + return -1; +} + +static void add_override_constraint(char ** from_list, int num_from, char ** to_list, int num_to, + float constraint, int num_multicycles, boolean domain_level_from, boolean domain_level_to, + boolean make_copies) { + /* Add a special-case constraint to override the default, calculated timing constraint, + to one of four arrays depending on whether it's coming from/to a flip-flop or an entire clock domain. + + If make_copies is true, we make a copy of from_list and to_list for this override constraint entry; + if false, we just set the override constraint entry to point to the existing list. The latter is + more efficient, but it's almost impossible to free multiple identical pointers without freeing + the same thing twice and causing an error. */ + + t_override_constraint ** constraint_array; + /* Because we are reallocating the array and possibly changing + its address, we need to modify it through a reference. */ + + int num_constraints, i; + + if (domain_level_from) { + if (domain_level_to) { /* Clock-to-clock constraint */ + constraint_array = &g_sdc->cc_constraints; + num_constraints = ++g_sdc->num_cc_constraints; + } else { /* Clock-to-flipflop constraint */ + constraint_array = &g_sdc->cf_constraints; + num_constraints = ++g_sdc->num_cf_constraints; + } + } else { + if (domain_level_to) { /* Flipflop-to-clock constraint */ + constraint_array = &g_sdc->fc_constraints; + num_constraints = ++g_sdc->num_fc_constraints; + } else { /* Flipflop-to-flipflop constraint */ + constraint_array = &g_sdc->ff_constraints; + num_constraints = ++g_sdc->num_ff_constraints; + } + } + + *constraint_array = (t_override_constraint *) my_realloc(*constraint_array, num_constraints * sizeof(t_override_constraint)); + + if (make_copies) { + /* Copy from_list and to_list to constraint_array[num_constraints - 1].source_list and .sink_list. */ + (*constraint_array)[num_constraints - 1].source_list = (char **) my_malloc(num_from * sizeof(char *)); + (*constraint_array)[num_constraints - 1].sink_list = (char **) my_malloc(num_to * sizeof(char *)); + for (i = 0; i < num_from; i++) { + (*constraint_array)[num_constraints - 1].source_list[i] = my_strdup(from_list[i]); + } + for (i = 0; i < num_to; i++) { + (*constraint_array)[num_constraints - 1].sink_list[i] = my_strdup(to_list[i]); + } + } else { + /* Just set constraint array to point to from_list and to_list. */ + (*constraint_array)[num_constraints - 1].source_list = from_list; + (*constraint_array)[num_constraints - 1].sink_list = to_list; + } + (*constraint_array)[num_constraints - 1].num_source = num_from; + (*constraint_array)[num_constraints - 1].num_sink = num_to; + (*constraint_array)[num_constraints - 1].constraint = constraint; + (*constraint_array)[num_constraints - 1].num_multicycles = num_multicycles; + (*constraint_array)[num_constraints - 1].file_line_number = file_line_number; /* global var */ +} + +static float calculate_constraint(t_sdc_clock source_domain, t_sdc_clock sink_domain) { + /* Given information from the SDC file about the period and offset of two clocks, * + * determine the implied setup-time constraint between them via edge counting. */ + + int source_period, sink_period, source_rising_edge, sink_rising_edge, lcm_period, num_source_edges, num_sink_edges, + * source_edges, * sink_edges, i, j, time, constraint_as_int; + float constraint; + + /* If the source and sink domains have the same period and edges, the constraint is just the common clock period. */ + if (fabs(source_domain.period - sink_domain.period) < EPSILON && + fabs(source_domain.rising_edge - sink_domain.rising_edge) < EPSILON && + fabs(source_domain.falling_edge - sink_domain.falling_edge) < EPSILON) { + return source_domain.period; /* or, equivalently, sink_domain.period */ + } + + /* If either period is 0, the constraint is 0. */ + if (source_domain.period < EPSILON || sink_domain.period < EPSILON) { + return 0.; + } + + /* Multiply periods and edges by 1000 and round down * + * to the nearest integer, to avoid messy decimals. */ + + source_period = static_cast(source_domain.period * 1000); + sink_period = static_cast(sink_domain.period * 1000); + source_rising_edge = static_cast(source_domain.rising_edge * 1000); + sink_rising_edge = static_cast(sink_domain.rising_edge * 1000); + + /* If we get here, we have to use edge counting. Find the LCM of the two periods. * + * This determines how long it takes before the pattern of the two clocks starts repeating. */ + for (lcm_period = 1; lcm_period % source_period != 0 || lcm_period % sink_period != 0; lcm_period++) + ; + + /* Create an array of positive edges for each clock over one LCM clock period. */ + + num_source_edges = lcm_period/source_period + 1; + num_sink_edges = lcm_period/sink_period + 1; + + source_edges = (int *) my_malloc((num_source_edges + 1) * sizeof(int)); + sink_edges = (int *) my_malloc((num_sink_edges + 1) * sizeof(int)); + + for (i = 0, time = source_rising_edge; i < num_source_edges + 1; i++) { + source_edges[i] = time; + time += source_period; + } + + for (i = 0, time = sink_rising_edge; i < num_sink_edges + 1; i++) { + sink_edges[i] = time; + time += sink_period; + } + + /* Compare every edge in source_edges with every edge in sink_edges. * + * The lowest STRICTLY POSITIVE difference between a sink edge and a source edge * + * gives us the set-up time constraint. */ + + constraint_as_int = INT_MAX; /* constraint starts off at +ve infinity so that everything will be less than it */ + + for (i = 0; i < num_source_edges + 1; i++) { + for (j = 0; j < num_sink_edges + 1; j++) { + if (sink_edges[j] > source_edges[i]) { + constraint_as_int = std::min(constraint_as_int, sink_edges[j] - source_edges[i]); + } + } + } + + /* Divide by 1000 again and turn the constraint back into a float, and clean up memory. */ + + constraint = constraint_as_int / 1000.; + + free(source_edges); + free(sink_edges); + + return constraint; +} + +static boolean regex_match (char * string, char * regular_expression) { + /* Given a string and a regular expression, return TRUE if there's a match, + FALSE if not. Print an error and exit if regular_expression is invalid. */ + + const char * error; + + assert(string && regular_expression); + + /* The regex library reports a match if regular_expression is a substring of string + AND not equal to string. This is not appropriate for our purposes. For example, + we'd get both "clock" and "clock2" matching the regular expression "clock". + We have to manually return that there's no match in this special case. */ + if (strstr(string, regular_expression) && strcmp(string, regular_expression) != 0) + return FALSE; + + if (strcmp(regular_expression, "*") == 0) + return TRUE; /* The regex library hangs if it is fed "*" as a regular expression. */ + + error = slre_match((enum slre_option) 0, regular_expression, string, strlen(string)); + + if (!error) + return TRUE; + else if (strcmp(error, "No match") == 0) + return FALSE; + else { + vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Error matching regular expression \"%s\".\n", + file_line_number, regular_expression); + exit(1); + } +} + +void free_sdc_related_structs(void) { + if (!g_sdc) return; + + free_override_constraint(g_sdc->cc_constraints, g_sdc->num_cc_constraints); + /* Should already have been freed in process_constraints() */ + + free_override_constraint(g_sdc->cf_constraints, g_sdc->num_cf_constraints); + free_override_constraint(g_sdc->fc_constraints, g_sdc->num_fc_constraints); + free_override_constraint(g_sdc->ff_constraints, g_sdc->num_ff_constraints); + free_io_constraint(g_sdc->constrained_inputs, g_sdc->num_constrained_inputs); + free_io_constraint(g_sdc->constrained_outputs, g_sdc->num_constrained_outputs); + free_clock_constraint(g_sdc->constrained_clocks, g_sdc->num_constrained_clocks); + free_matrix(g_sdc->domain_constraint, 0, g_sdc->num_constrained_clocks - 1, 0, sizeof(float)); + free(g_sdc); + g_sdc = NULL; +} + +void free_override_constraint(t_override_constraint *& constraint_array, int num_constraints) { + int i, j; + + if (!constraint_array) return; + + for (i = 0; i < num_constraints; i++) { + for (j = 0; j < constraint_array[i].num_source; j++) { + free(constraint_array[i].source_list[j]); + constraint_array[i].source_list[j] = NULL; + } + for (j = 0; j < constraint_array[i].num_sink; j++) { + free(constraint_array[i].sink_list[j]); + constraint_array[i].sink_list[j] = NULL; + } + free(constraint_array[i].source_list); + free(constraint_array[i].sink_list); + } + free(constraint_array); + constraint_array = NULL; +} + +static void free_io_constraint(t_io *& io_array, int num_ios) { + int i; + + for (i = 0; i < num_ios; i++) { + free(io_array[i].name); + free(io_array[i].clock_name); + } + free(io_array); + io_array = NULL; +} + +static void free_clock_constraint(t_clock *& clock_array, int num_clocks) { + int i; + + for (i = 0; i < num_clocks; i++) { + free(clock_array[i].name); + } + free(clock_array); + clock_array = NULL; +} diff --git a/vpr7_rram/vpr/SRC/timing/read_sdc.h b/vpr7_rram/vpr/SRC/timing/read_sdc.h new file mode 100644 index 000000000..8ba93070e --- /dev/null +++ b/vpr7_rram/vpr/SRC/timing/read_sdc.h @@ -0,0 +1,14 @@ +#ifndef READ_SDC_H +#define READ_SDC_H + +/*********************** Externally-accessible variables **************************/ + +extern t_timing_constraints * g_sdc; + +/*************************** Function declarations ********************************/ + +void read_sdc(t_timing_inf timing_inf); +void free_sdc_related_structs(void); +void free_override_constraint(t_override_constraint *& constraint_array, int num_constraints); + +#endif diff --git a/vpr7_rram/vpr/SRC/timing/slre.c b/vpr7_rram/vpr/SRC/timing/slre.c new file mode 100644 index 000000000..516b3d611 --- /dev/null +++ b/vpr7_rram/vpr/SRC/timing/slre.c @@ -0,0 +1,662 @@ +// Copyright (c) 2004-2012 Sergey Lyubka +// All rights reserved +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. + +#include +#include +#include +#include +#include +#include +#include +#include "slre.h" + +// Compiled regular expression +struct slre { + unsigned char code[256]; + unsigned char data[256]; + int code_size; + int data_size; + int num_caps; // Number of bracket pairs + int anchored; // Must match from string start + enum slre_option options; + const char *error_string; // Error string +}; + +// Captured substring +struct cap { + const char *ptr; // Pointer to the substring + int len; // Substring length +}; + +enum { + END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS, + STARQ, PLUSQ, QUEST, SPACE, NONSPACE, DIGIT +}; + +// Commands and operands are all unsigned char (1 byte long). All code offsets +// are relative to current address, and positive (always point forward). Data +// offsets are absolute. Commands with operands: +// +// BRANCH offset1 offset2 +// Try to match the code block that follows the BRANCH instruction +// (code block ends with END). If no match, try to match code block that +// starts at offset1. If either of these match, jump to offset2. +// +// EXACT data_offset data_length +// Try to match exact string. String is recorded in data section from +// data_offset, and has length data_length. +// +// OPEN capture_number +// CLOSE capture_number +// If the user have passed 'struct cap' array for captures, OPEN +// records the beginning of the matched substring (cap->ptr), CLOSE +// sets the length (cap->len) for respective capture_number. +// +// STAR code_offset +// PLUS code_offset +// QUEST code_offset +// *, +, ?, respectively. Try to gobble as much as possible from the +// matched buffer while code block that follows these instructions +// matches. When the longest possible string is matched, +// jump to code_offset +// +// STARQ, PLUSQ are non-greedy versions of STAR and PLUS. + +static const char *meta_characters = "|.*+?()[\\"; +static const char *error_no_match = "No match"; + +static void set_jump_offset(struct slre *r, int pc, int offset) { + assert(offset < r->code_size); + if (r->code_size - offset > 0xff) { + r->error_string = "Jump offset is too big"; + } else { + r->code[pc] = (unsigned char) (r->code_size - offset); + } +} + +static void emit(struct slre *r, int code) { + if (r->code_size >= (int) (sizeof(r->code) / sizeof(r->code[0]))) { + r->error_string = "RE is too long (code overflow)"; + } else { + r->code[r->code_size++] = (unsigned char) code; + } +} + +static void store_char_in_data(struct slre *r, int ch) { + if (r->data_size >= (int) sizeof(r->data)) { + r->error_string = "RE is too long (data overflow)"; + } else { + r->data[r->data_size++] = ch; + } +} + +static void exact(struct slre *r, const char **re) { + int old_data_size = r->data_size; + + while (**re != '\0' && (strchr(meta_characters, **re)) == NULL) { + store_char_in_data(r, *(*re)++); + } + + emit(r, EXACT); + emit(r, old_data_size); + emit(r, r->data_size - old_data_size); +} + +static int get_escape_char(const char **re) { + int res; + + switch (*(*re)++) { + case 'n': res = '\n'; break; + case 'r': res = '\r'; break; + case 't': res = '\t'; break; + case '0': res = 0; break; + case 'S': res = NONSPACE << 8; break; + case 's': res = SPACE << 8; break; + case 'd': res = DIGIT << 8; break; + default: res = (*re)[-1]; break; + } + + return res; +} + +static void anyof(struct slre *r, const char **re) { + int esc, old_data_size = r->data_size, op = ANYOF; + + while (**re != '\0') + + switch (*(*re)++) { + case ']': + emit(r, op); + emit(r, old_data_size); + emit(r, r->data_size - old_data_size); + return; + // NOTREACHED + break; + case '\\': + esc = get_escape_char(re); + if ((esc & 0xff) == 0) { + store_char_in_data(r, 0); + store_char_in_data(r, esc >> 8); + } else { + store_char_in_data(r, esc); + } + break; + default: + store_char_in_data(r, (*re)[-1]); + break; + } + + r->error_string = "No closing ']' bracket"; +} + +static void relocate(struct slre *r, int begin, int shift) { + emit(r, END); + memmove(r->code + begin + shift, r->code + begin, r->code_size - begin); + r->code_size += shift; +} + +static void quantifier(struct slre *r, int prev, int op) { + if (r->code[prev] == EXACT && r->code[prev + 2] > 1) { + r->code[prev + 2]--; + emit(r, EXACT); + emit(r, r->code[prev + 1] + r->code[prev + 2]); + emit(r, 1); + prev = r->code_size - 3; + } + relocate(r, prev, 2); + r->code[prev] = op; + set_jump_offset(r, prev + 1, prev); +} + +static void exact_one_char(struct slre *r, int ch) { + emit(r, EXACT); + emit(r, r->data_size); + emit(r, 1); + store_char_in_data(r, ch); +} + +static void fixup_branch(struct slre *r, int fixup) { + if (fixup > 0) { + emit(r, END); + set_jump_offset(r, fixup, fixup - 2); + } +} + +static void compile(struct slre *r, const char **re) { + int op, esc, branch_start, last_op, fixup, cap_no, level; + + fixup = 0; + level = r->num_caps; + branch_start = last_op = r->code_size; + + for (;;) + switch (*(*re)++) { + + case '\0': + (*re)--; + return; + // NOTREACHED + break; + + case '.': + last_op = r->code_size; + emit(r, ANY); + break; + + case '[': + last_op = r->code_size; + anyof(r, re); + break; + + case '\\': + last_op = r->code_size; + esc = get_escape_char(re); + if (esc & 0xff00) { + emit(r, esc >> 8); + } else { + exact_one_char(r, esc); + } + break; + + case '(': + last_op = r->code_size; + cap_no = ++r->num_caps; + emit(r, OPEN); + emit(r, cap_no); + + compile(r, re); + if (*(*re)++ != ')') { + r->error_string = "No closing bracket"; + return; + } + + emit(r, CLOSE); + emit(r, cap_no); + break; + + case ')': + (*re)--; + fixup_branch(r, fixup); + if (level == 0) { + r->error_string = "Unbalanced brackets"; + return; + } + return; + // NOTREACHED + break; + + case '+': + case '*': + op = (*re)[-1] == '*' ? STAR: PLUS; + if (**re == '?') { + (*re)++; + op = op == STAR ? STARQ : PLUSQ; + } + quantifier(r, last_op, op); + break; + + case '?': + quantifier(r, last_op, QUEST); + break; + + case '|': + fixup_branch(r, fixup); + relocate(r, branch_start, 3); + r->code[branch_start] = BRANCH; + set_jump_offset(r, branch_start + 1, branch_start); + fixup = branch_start + 2; + r->code[fixup] = 0xff; + break; + + default: + (*re)--; + last_op = r->code_size; + exact(r, re); + break; + } +} + +// Compile regular expression. If success, 1 is returned. +// If error, 0 is returned and slre.error_string points to the error message. +static const char *compile2(struct slre *r, const char *re) { + r->error_string = NULL; + r->code_size = r->data_size = r->num_caps = r->anchored = 0; + + emit(r, OPEN); // This will capture what matches full RE + emit(r, 0); + + while (*re != '\0') { + compile(r, &re); + } + + if (r->code[2] == BRANCH) { + fixup_branch(r, 4); + } + + emit(r, CLOSE); + emit(r, 0); + emit(r, END); + +#if 0 + static void dump(const struct slre *, FILE *); + dump(r, stdout); +#endif + + return r->error_string; +} + +static const char *match(const struct slre *, int, const char *, int, int *, + struct cap *); + +static void loop_greedy(const struct slre *r, int pc, const char *s, int len, + int *ofs) { + int saved_offset, matched_offset; + + saved_offset = matched_offset = *ofs; + + while (!match(r, pc + 2, s, len, ofs, NULL)) { + saved_offset = *ofs; + if (!match(r, pc + r->code[pc + 1], s, len, ofs, NULL)) { + matched_offset = saved_offset; + } + *ofs = saved_offset; + } + + *ofs = matched_offset; +} + +static void loop_non_greedy(const struct slre *r, int pc, const char *s, + int len, int *ofs) { + int saved_offset = *ofs; + + while (!match(r, pc + 2, s, len, ofs, NULL)) { + saved_offset = *ofs; + if (!match(r, pc + r->code[pc + 1], s, len, ofs, NULL)) + break; + } + + *ofs = saved_offset; +} + +static int is_any_of(const unsigned char *p, int len, const char *s, int *ofs) { + int i, ch; + + ch = s[*ofs]; + + for (i = 0; i < len; i++) + if (p[i] == ch) { + (*ofs)++; + return 1; + } + + return 0; +} + +static int is_any_but(const unsigned char *p, int len, const char *s, + int *ofs) { + int i, ch; + + ch = s[*ofs]; + + for (i = 0; i < len; i++) + if (p[i] == ch) { + return 0; + } + + (*ofs)++; + return 1; +} + +static int lowercase(const char *s) { + return tolower(* (const unsigned char *) s); +} + +static int casecmp(const void *p1, const void *p2, size_t len) { + const char *s1 = (const char *) p1, *s2 = (const char *) p2; + int diff = 0; + + if (len > 0) + do { + diff = lowercase(s1++) - lowercase(s2++); + } while (diff == 0 && s1[-1] != '\0' && --len > 0); + + return diff; +} + +static const char *match(const struct slre *r, int pc, const char *s, int len, + int *ofs, struct cap *caps) { + int n, saved_offset; + const char *error_string = NULL; + int (*cmp)(const void *string1, const void *string2, size_t len); + + while (error_string == NULL && r->code[pc] != END) { + + assert(pc < r->code_size); + assert(pc < (int) (sizeof(r->code) / sizeof(r->code[0]))); + + switch (r->code[pc]) { + case BRANCH: + saved_offset = *ofs; + error_string = match(r, pc + 3, s, len, ofs, caps); + if (error_string != NULL) { + *ofs = saved_offset; + error_string = match(r, pc + r->code[pc + 1], s, len, ofs, caps); + } + pc += r->code[pc + 2]; + break; + + case EXACT: + error_string = error_no_match; + n = r->code[pc + 2]; // String length + cmp = r->options & SLRE_CASE_INSENSITIVE ? casecmp : memcmp; + if (n <= len - *ofs && !cmp(s + *ofs, r->data + r->code[pc + 1], n)) { + (*ofs) += n; + error_string = NULL; + } + pc += 3; + break; + + case QUEST: + error_string = NULL; + saved_offset = *ofs; + if (match(r, pc + 2, s, len, ofs, caps) != NULL) { + *ofs = saved_offset; + } + pc += r->code[pc + 1]; + break; + + case STAR: + error_string = NULL; + loop_greedy(r, pc, s, len, ofs); + pc += r->code[pc + 1]; + break; + + case STARQ: + error_string = NULL; + loop_non_greedy(r, pc, s, len, ofs); + pc += r->code[pc + 1]; + break; + + case PLUS: + if ((error_string = match(r, pc + 2, s, len, ofs, caps)) != NULL) + break; + + loop_greedy(r, pc, s, len, ofs); + pc += r->code[pc + 1]; + break; + + case PLUSQ: + if ((error_string = match(r, pc + 2, s, len, ofs, caps)) != NULL) + break; + + loop_non_greedy(r, pc, s, len, ofs); + pc += r->code[pc + 1]; + break; + + case SPACE: + error_string = error_no_match; + if (*ofs < len && isspace(((const unsigned char *)s)[*ofs])) { + (*ofs)++; + error_string = NULL; + } + pc++; + break; + + case NONSPACE: + error_string = error_no_match; + if (*ofs data + r->code[pc + 1], r->code[pc + 2], + s, ofs) ? NULL : error_no_match; + pc += 3; + break; + + case ANYBUT: + error_string = error_no_match; + if (*ofs < len) + error_string = is_any_but(r->data + r->code[pc + 1], r->code[pc + 2], + s, ofs) ? NULL : error_no_match; + pc += 3; + break; + + case BOL: + error_string = *ofs == 0 ? NULL : error_no_match; + pc++; + break; + + case EOL: + error_string = *ofs == len ? NULL : error_no_match; + pc++; + break; + + case OPEN: + if (caps != NULL) + caps[r->code[pc + 1]].ptr = s + *ofs; + pc += 2; + break; + + case CLOSE: + if (caps != NULL) + caps[r->code[pc + 1]].len = (s + *ofs) - + caps[r->code[pc + 1]].ptr; + pc += 2; + break; + + case END: + pc++; + break; + + default: + printf("unknown cmd (%d) at %d\n", r->code[pc], pc); + assert(0); + break; + } + } + + return error_string; +} + +// Return 1 if match, 0 if no match. +// If 'captured_substrings' array is not NULL, then it is filled with the +// values of captured substrings. captured_substrings[0] element is always +// a full matched substring. The round bracket captures start from +// captured_substrings[1]. +// It is assumed that the size of captured_substrings array is enough to +// hold all captures. The caller function must make sure it is! So, the +// array_size = number_of_round_bracket_pairs + 1 +static const char *match2(const struct slre *r, const char *buf, int len, + struct cap *caps) { + int i, ofs = 0; + const char *error_string = error_no_match; + + if (r->anchored) { + error_string = match(r, 0, buf, len, &ofs, caps); + } else { + for (i = 0; i < len && error_string != NULL; i++) { + ofs = i; + error_string = match(r, 0, buf, len, &ofs, caps); + } + } + + return error_string; +} + +static const char *capture_float(const struct cap *cap, void *p, size_t len) { + const char *fmt; + char buf[20]; + + switch (len) { + case sizeof(float): fmt = "f"; break; + case sizeof(double): fmt = "lf"; break; + default: return "SLRE_FLOAT: unsupported size"; + } + + sprintf(buf, "%%%d%s", cap->len, fmt); + return sscanf(cap->ptr, buf, p) == 1 ? NULL : "SLRE_FLOAT: capture failed"; +} + +static const char *capture_string(const struct cap *cap, void *p, size_t len) { + if ((int) len <= cap->len) { + return "SLRE_STRING: buffer size too small"; + } + memcpy(p, cap->ptr, cap->len); + ((char *) p)[cap->len] = '\0'; + return NULL; +} + +static const char *capture_int(const struct cap *cap, void *p, size_t len) { + const char *fmt; + char buf[20]; + + switch (len) { + case sizeof(char): fmt = "hh"; break; + case sizeof(short): fmt = "h"; break; + case sizeof(int): fmt = "d"; break; + default: return "SLRE_INT: unsupported size"; + } + + sprintf(buf, "%%%d%s", cap->len, fmt); + return sscanf(cap->ptr, buf, p) == 1 ? NULL : "SLRE_INT: capture failed"; +} + +static const char *capture(const struct cap *caps, int num_caps, va_list ap) { + int i, type; + size_t size; + void *p; + const char *err = NULL; + + for (i = 0; i < num_caps; i++) { + type = va_arg(ap, int); + size = va_arg(ap, size_t); + p = va_arg(ap, void *); + switch (type) { + case SLRE_INT: err = capture_int(&caps[i], p, size); break; + case SLRE_FLOAT: err = capture_float(&caps[i], p, size); break; + case SLRE_STRING: err = capture_string(&caps[i], p, size); break; + default: err = "Unknown type, expected SLRE_(INT|FLOAT|STRING)"; break; + } + } + return err; +} + +const char *slre_match(enum slre_option options, const char *re, + const char *buf, int buf_len, ...) { + struct slre slre; + struct cap caps[20]; + va_list ap; + const char *error_string = NULL; + + slre.options = options; + if ((error_string = compile2(&slre, re)) == NULL && + (error_string = match2(&slre, buf, buf_len, caps)) == NULL) { + va_start(ap, buf_len); + error_string = capture(caps + 1, slre.num_caps, ap); + va_end(ap); + } + + return error_string; +} diff --git a/vpr7_rram/vpr/SRC/timing/slre.h b/vpr7_rram/vpr/SRC/timing/slre.h new file mode 100644 index 000000000..ece4452d3 --- /dev/null +++ b/vpr7_rram/vpr/SRC/timing/slre.h @@ -0,0 +1,85 @@ +/* Copyright (c) 2004-2012 Sergey Lyubka + All rights reserved + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + THE SOFTWARE. + + This is a regular expression library that implements a subset of Perl RE. + Please refer to http://slre.googlecode.com for detailed description. + + Supported syntax: + ^ Match beginning of a buffer + $ Match end of a buffer + () Grouping and substring capturing + [...] Match any character from set + [^...] Match any character but ones from set + \s Match whitespace + \S Match non-whitespace + \d Match decimal digit + \r Match carriage return + \n Match newline + + Match one or more times (greedy) + +? Match one or more times (non-greedy) + * Match zero or more times (greedy) + *? Match zero or more times (non-greedy) + ? Match zero or once + \xDD Match byte with hex value 0xDD + \meta Match one of the meta character: ^$().[*+\? + + Match string buffer "buf" of length "buf_len" against "regexp", which should + conform the syntax outlined above. "options" could be either 0 or + SLRE_CASE_INSENSITIVE for case-insensitive match. If regular expression + "regexp" contains brackets, slre_match() will capture the respective + substring into the passed placeholder. Thus, each opening parenthesis + should correspond to three arguments passed: + placeholder_type, placeholder_size, placeholder_address + + Usage example: parsing HTTP request line. + + char method[10], uri[100]; + int http_version_minor, http_version_major; + const char *error; + const char *request = " \tGET /index.html HTTP/1.0\r\n\r\n"; + + error = slre_match(0, "^\\s*(GET|POST)\\s+(\\S+)\\s+HTTP/(\\d)\\.(\\d)", + request, strlen(request), + SLRE_STRING, sizeof(method), method, + SLRE_STRING, sizeof(uri), uri, + SLRE_INT,sizeof(http_version_major),&http_version_major, + SLRE_INT,sizeof(http_version_minor),&http_version_minor); + + if (error != NULL) { + printf("Error parsing HTTP request: %s\n", error); + } else { + printf("Requested URI: %s\n", uri); + } + + + Return: + NULL: string matched and all captures successfully made + non-NULL: in this case, the return value is an error string */ + +#ifndef SLRE_H +#define SLRE_H + +enum slre_option {SLRE_CASE_INSENSITIVE = 1}; +enum slre_capture {SLRE_STRING, SLRE_INT, SLRE_FLOAT}; +const char *slre_match(enum slre_option options, const char *regexp, + const char *buf, int buf_len, ...); + +#endif /* SLRE_H */ diff --git a/vpr7_rram/vpr/SRC/util/hash.c b/vpr7_rram/vpr/SRC/util/hash.c new file mode 100755 index 000000000..8bcb81fcb --- /dev/null +++ b/vpr7_rram/vpr/SRC/util/hash.c @@ -0,0 +1,200 @@ +#include +#include +#include "hash.h" +#include "util.h" + +struct s_hash ** +alloc_hash_table(void) { + + /* Creates a hash table with HASHSIZE different locations (hash values). */ + + struct s_hash **hash_table; + + hash_table = (struct s_hash **) my_calloc(sizeof(struct s_hash *), + HASHSIZE); + return (hash_table); +} + +void free_hash_table(struct s_hash **hash_table) { + + /* Frees all the storage associated with a hash table. */ + + int i; + struct s_hash *h_ptr, *temp_ptr; + + for (i = 0; i < HASHSIZE; i++) { + h_ptr = hash_table[i]; + while (h_ptr != NULL) { + free(h_ptr->name); + temp_ptr = h_ptr->next; + free(h_ptr); + h_ptr = temp_ptr; + } + } + + free(hash_table); +} + +struct s_hash_iterator start_hash_table_iterator(void) { + + /* Call this routine before you start going through all the elements in * + * a hash table. It sets the internal indices to the start of the table. */ + + struct s_hash_iterator hash_iterator; + + hash_iterator.i = -1; + hash_iterator.h_ptr = NULL; + return (hash_iterator); +} + +struct s_hash * +get_next_hash(struct s_hash **hash_table, struct s_hash_iterator *hash_iterator) { + + /* Returns the next occupied hash entry, and moves the iterator structure * + * forward so the next call gets the next entry. */ + + int i; + struct s_hash *h_ptr; + + i = hash_iterator->i; + h_ptr = hash_iterator->h_ptr; + + while (h_ptr == NULL) { + i++; + if (i >= HASHSIZE) + return (NULL); /* End of table */ + + h_ptr = hash_table[i]; + } + + hash_iterator->h_ptr = h_ptr->next; + hash_iterator->i = i; + return (h_ptr); +} + +struct s_hash * +insert_in_hash_table(struct s_hash **hash_table, char *name, + int next_free_index) { + + /* Adds the string pointed to by name to the hash table, and returns the * + * hash structure created or updated. If name is already in the hash table * + * the count member of that hash element is incremented. Otherwise a new * + * hash entry with a count of zero and an index of next_free_index is * + * created. */ + + int i; + struct s_hash *h_ptr, *prev_ptr; + + i = hash_value(name); + prev_ptr = NULL; + h_ptr = hash_table[i]; + + while (h_ptr != NULL) { + if (strcmp(h_ptr->name, name) == 0) { + h_ptr->count++; + return (h_ptr); + } + + prev_ptr = h_ptr; + h_ptr = h_ptr->next; + } + + /* Name string wasn't in the hash table. Add it. */ + + h_ptr = (struct s_hash *) my_malloc(sizeof(struct s_hash)); + if (prev_ptr == NULL) { + hash_table[i] = h_ptr; + } else { + prev_ptr->next = h_ptr; + } + h_ptr->next = NULL; + h_ptr->index = next_free_index; + h_ptr->count = 1; + h_ptr->name = (char *) my_malloc((strlen(name) + 1) * sizeof(char)); + strcpy(h_ptr->name, name); + return (h_ptr); +} + +struct s_hash * +get_hash_entry(struct s_hash **hash_table, char *name) { + + /* Returns the hash entry with this name, or NULL if there is no * + * corresponding entry. */ + + int i; + struct s_hash *h_ptr; + + i = hash_value(name); + h_ptr = hash_table[i]; + + while (h_ptr != NULL) { + if (strcmp(h_ptr->name, name) == 0) + return (h_ptr); + + h_ptr = h_ptr->next; + } + + return (NULL); +} + +int hash_value(char *name) { + /* Creates a hash key from a character string. The absolute value is taken * + * for the final val to compensate for long strlen that cause val to * + * overflow. */ + + int i; + int val = 0, mult = 1; + + i = strlen(name); + for (i = strlen(name) - 1; i >= 0; i--) { + val += mult * ((int) name[i]); + mult *= 7; + } + val += (int) name[0]; + val %= HASHSIZE; + + val = abs(val); + return (val); +} + +void get_hash_stats(struct s_hash **hash_table, char *hash_table_name){ + + /* Checks to see how well elements are distributed within the hash table. * + * Will traverse through the hash_table and count the length of the linked * + * list. Will output the hash number, the number of array elements that are * + * NULL, the average number of linked lists and the maximum length of linked * + * lists. */ + + int num_NULL = 0, total_elements = 0, max_num = 0, curr_num; + double avg_num = 0; + int i; + struct s_hash *h_ptr; + + for (i = 0; inext; + } + } + + if (curr_num > max_num) + max_num = curr_num; + + total_elements = total_elements + curr_num; + } + + avg_num = (float) total_elements / ((float)HASHSIZE - (float)num_NULL); + + vpr_printf(TIO_MESSAGE_INFO, "\n"); + vpr_printf(TIO_MESSAGE_INFO, "The hash table '%s' is of size %d.\n", + hash_table_name, HASHSIZE); + vpr_printf(TIO_MESSAGE_INFO, "It has: %d keys that are never used; total of %d elements; an average linked-list length of %.1f; and a maximum linked-list length of %d.\n", + num_NULL, total_elements, avg_num, max_num); + vpr_printf(TIO_MESSAGE_INFO, "\n"); +} diff --git a/vpr7_rram/vpr/SRC/util/hash.h b/vpr7_rram/vpr/SRC/util/hash.h new file mode 100755 index 000000000..f35157d14 --- /dev/null +++ b/vpr7_rram/vpr/SRC/util/hash.h @@ -0,0 +1,38 @@ +#define HASHSIZE 5000001 + +struct s_hash { + char *name; + int index; + int count; + struct s_hash *next; +}; + +/* name: The string referred to by this hash entry. * + * index: The integer identifier for this entry. * + * count: Number of times an element with this name has been inserted into * + * the table. EXCEPTION: For the structure for blif parsing/reading, * + * blif_hash, value of count is the number of pins on this vpack_net * + * so far. * + * next: A pointer to the next (string,index) entry that mapped to the * + * same hash value, or NULL if there are no more entries. */ + +struct s_hash_iterator { + int i; + struct s_hash *h_ptr; +}; + +/* i: current "line" of the hash table. That is, hash_table[i] is the * + * start of the hash linked list for this hash value. * + * h_ptr: Pointer to the next hash structure to be examined in the * + * iteration. */ + +struct s_hash **alloc_hash_table(void); +void free_hash_table(struct s_hash **hash_table); +struct s_hash_iterator start_hash_table_iterator(void); +struct s_hash *get_next_hash(struct s_hash **hash_table, + struct s_hash_iterator *hash_iterator); +struct s_hash *insert_in_hash_table(struct s_hash **hash_table, char *name, + int next_free_index); +struct s_hash *get_hash_entry(struct s_hash **hash_table, char *name); +int hash_value(char *name); +void get_hash_stats(struct s_hash **hash_table, char *hash_table_name); diff --git a/vpr7_rram/vpr/SRC/util/heapsort.c b/vpr7_rram/vpr/SRC/util/heapsort.c new file mode 100755 index 000000000..75545dc02 --- /dev/null +++ b/vpr7_rram/vpr/SRC/util/heapsort.c @@ -0,0 +1,96 @@ +#include "heapsort.h" + +/******************* Subroutines local to heapsort.c ************************/ + +static void add_to_sort_heap(int *heap, float *sort_values, int index, + int heap_tail); + +static int get_top_of_heap_index(int *heap, float *sort_values, int heap_tail, + int start_index); + +/********************* Subroutine definitions *******************************/ + +void heapsort(int *sort_index, float *sort_values, int nelem, int start_index) { + + /* This routine loads sort_index [1..nelem] with nelem values: the indices * + * of the sort_values [1..nelem] array that lead to sort_values[index] being * + * decreasing as one goes through sort_index. Sort_values is not changed. */ + + int i; + + sort_index -= start_index; + sort_values -= start_index; + + /* Build a heap with the *smallest* element at the top. */ + + for (i = 1; i <= nelem; i++) + add_to_sort_heap(sort_index, sort_values, i, i); + + /* Now pull items off the heap, smallest first. As the heap (in sort_index) * + * shrinks, I store the item pulled off (the smallest) in sort_index, * + * starting from the end. The heap and the stored smallest values never * + * overlap, so I get a nice sort-in-place. */ + + for (i = nelem; i >= 1; i--) + sort_index[i] = get_top_of_heap_index(sort_index, sort_values, i, + start_index); + + sort_index += start_index; + sort_values += start_index; +} + +static void add_to_sort_heap(int *heap, float *sort_values, int index, + int heap_tail) { + + /* Adds element index, with value = sort_values[index] to the heap. * + * Heap_tail is the number of elements in the heap *after* the insert. */ + + unsigned int ifrom, ito; /* Making these unsigned helps compiler opts. */ + int temp; + + heap[heap_tail] = index; + ifrom = heap_tail; + ito = ifrom / 2; + + while (ito >= 1 && sort_values[heap[ifrom]] < sort_values[heap[ito]]) { + temp = heap[ito]; + heap[ito] = heap[ifrom]; + heap[ifrom] = temp; + ifrom = ito; + ito = ifrom / 2; + } +} + +static int get_top_of_heap_index(int *heap, float *sort_values, int heap_tail, + int start_index) { + + /* Returns the index of the item at the top of the heap (the smallest one). * + * It then rebuilds the heap. Heap_tail is the number of items on the heap * + * before the top item is deleted. */ + + int index_of_smallest, temp; + unsigned int ifrom, ito, heap_end; + + index_of_smallest = heap[1]; + heap[1] = heap[heap_tail]; + heap_end = heap_tail - 1; /* One item deleted. */ + ifrom = 1; + ito = 2 * ifrom; + + while (ito <= heap_end) { + if (sort_values[heap[ito + 1]] < sort_values[heap[ito]]) + ito++; + + if (sort_values[heap[ito]] > sort_values[heap[ifrom]]) + break; + + temp = heap[ito]; + heap[ito] = heap[ifrom]; + heap[ifrom] = temp; + ifrom = ito; + ito = 2 * ifrom; + } + + /*index must have the start_index subracted to be consistent with the original array*/ + return (index_of_smallest - start_index); +} diff --git a/vpr7_rram/vpr/SRC/util/heapsort.h b/vpr7_rram/vpr/SRC/util/heapsort.h new file mode 100755 index 000000000..08daf2d05 --- /dev/null +++ b/vpr7_rram/vpr/SRC/util/heapsort.h @@ -0,0 +1 @@ +void heapsort(int *sort_index, float *sort_values, int nelem, int start_index); diff --git a/vpr7_rram/vpr/SRC/util/token.c b/vpr7_rram/vpr/SRC/util/token.c new file mode 100755 index 000000000..2a7bdf4ef --- /dev/null +++ b/vpr7_rram/vpr/SRC/util/token.c @@ -0,0 +1,173 @@ +/** + * Jason Luu + * July 22, 2009 + * Tokenizer + */ + +#include +#include +#include "util.h" +#include "token.h" +#include "ezxml.h" +#include "read_xml_util.h" + +enum e_token_type GetTokenTypeFromChar(INP enum e_token_type cur_token_type, + INP char cur); + +/* Returns a token list of the text for a given string. */ +t_token *GetTokensFromString(INP const char* inString, OUTP int * num_tokens) { + const char *cur; + t_token * tokens; + int i, in_string_index, prev_in_string_index; + boolean has_null; + enum e_token_type cur_token_type, new_token_type; + + *num_tokens = i = 0; + cur_token_type = TOKEN_NULL; + + if (inString == NULL) { + return NULL; + }; + + cur = inString; + + /* Count number of tokens */ + while (*cur) { + new_token_type = GetTokenTypeFromChar(cur_token_type, *cur); + if (new_token_type != cur_token_type) { + cur_token_type = new_token_type; + if (new_token_type != TOKEN_NULL) { + i++; + } + } + ++cur; + } + *num_tokens = i; + + if (*num_tokens > 0) { + tokens = (t_token*)my_calloc(*num_tokens + 1, sizeof(t_token)); + } else { + return NULL; + } + + /* populate tokens */ + i = 0; + in_string_index = 0; + has_null = TRUE; + prev_in_string_index = 0; + cur_token_type = TOKEN_NULL; + + cur = inString; + + while (*cur) { + + new_token_type = GetTokenTypeFromChar(cur_token_type, *cur); + if (new_token_type != cur_token_type) { + if (!has_null) { + tokens[i - 1].data[in_string_index - prev_in_string_index] = + '\0'; /* NULL the end of the data string */ + has_null = TRUE; + } + if (new_token_type != TOKEN_NULL) { + tokens[i].type = new_token_type; + tokens[i].data = my_strdup(inString + in_string_index); + prev_in_string_index = in_string_index; + has_null = FALSE; + i++; + } + cur_token_type = new_token_type; + } + ++cur; + in_string_index++; + } + + assert(i == *num_tokens); + + tokens[*num_tokens].type = TOKEN_NULL; + tokens[*num_tokens].data = NULL; + + /* Return the list */ + return tokens; +} + +void freeTokens(INP t_token *tokens, INP int num_tokens) { + int i; + for (i = 0; i < num_tokens; i++) { + free(tokens[i].data); + } + free(tokens); +} + +enum e_token_type GetTokenTypeFromChar(INP enum e_token_type cur_token_type, + INP char cur) { + if (IsWhitespace(cur)) { + return TOKEN_NULL; + } else { + if (cur == '[') { + return TOKEN_OPEN_SQUARE_BRACKET; + } else if (cur == ']') { + return TOKEN_CLOSE_SQUARE_BRACKET; + } else if (cur == '{') { + return TOKEN_OPEN_SQUIG_BRACKET; + } else if (cur == '}') { + return TOKEN_CLOSE_SQUIG_BRACKET; + } else if (cur == ':') { + return TOKEN_COLON; + } else if (cur == '.') { + return TOKEN_DOT; + } else if (cur >= '0' && cur <= '9' && cur_token_type != TOKEN_STRING) { + return TOKEN_INT; + } else { + return TOKEN_STRING; + } + } +} + +boolean checkTokenType(INP t_token token, OUTP enum e_token_type token_type) { + if (token.type != token_type) { + return FALSE; + } + return TRUE; +} + +void my_atof_2D(INOUTP float **matrix, INP int max_i, INP int max_j, + INP char *instring) { + int i, j; + char *cur, *cur2, *copy, *final; + + copy = my_strdup(instring); + final = copy; + while (*final != '\0') { + final++; + } + + cur = copy; + i = j = 0; + while (cur != final) { + while (IsWhitespace(*cur) && cur != final) { + if (j == max_j) { + i++; + j = 0; + } + cur++; + } + if (cur == final) { + break; + } + cur2 = cur; + while (!IsWhitespace(*cur2) && cur2 != final) { + cur2++; + } + *cur2 = '\0'; + assert(i < max_i && j < max_j); + matrix[i][j] = atof(cur); + j++; + cur = cur2; + *cur = ' '; + } + + assert((i == max_i && j == 0) || (i == max_i - 1 && j == max_j)); + + free(copy); +} + diff --git a/vpr7_rram/vpr/SRC/util/token.h b/vpr7_rram/vpr/SRC/util/token.h new file mode 100755 index 000000000..8c9dd39eb --- /dev/null +++ b/vpr7_rram/vpr/SRC/util/token.h @@ -0,0 +1,37 @@ +/** + * Jason Luu + * July 22, 2009 + * Tokenizer + */ + +#ifndef TOKEN_H +#define TOKEN_H + +enum e_token_type { + TOKEN_NULL, + TOKEN_STRING, + TOKEN_INT, + TOKEN_OPEN_SQUARE_BRACKET, + TOKEN_CLOSE_SQUARE_BRACKET, + TOKEN_OPEN_SQUIG_BRACKET, + TOKEN_CLOSE_SQUIG_BRACKET, + TOKEN_COLON, + TOKEN_DOT +}; + +struct s_token { + enum e_token_type type; + char *data; +}; +typedef struct s_token t_token; + +t_token *GetTokensFromString(INP const char* inString, OUTP int * num_tokens); + +void freeTokens(INP t_token *tokens, INP int num_tokens); + +boolean checkTokenType(INP t_token token, OUTP enum e_token_type token_type); + +void my_atof_2D(INOUTP float **matrix, INP int max_i, INP int max_j, INP char *instring); + +#endif + diff --git a/vpr7_rram/vpr/SRC/util/vpr_utils.c b/vpr7_rram/vpr/SRC/util/vpr_utils.c new file mode 100755 index 000000000..23acd0be5 --- /dev/null +++ b/vpr7_rram/vpr/SRC/util/vpr_utils.c @@ -0,0 +1,1156 @@ +#include +#include +#include "util.h" +#include "vpr_types.h" +#include "physical_types.h" +#include "globals.h" +#include "vpr_utils.h" +#include "cluster_placement.h" +#include "place_macro.h" +#include "string.h" + + +/* This module contains subroutines that are used in several unrelated parts * + * of VPR. They are VPR-specific utility routines. */ + +/* This defines the maximum string length that could be parsed by functions * + * in vpr_utils. */ +#define MAX_STRING_LEN 128 + +/******************** File-scope variables delcarations **********************/ + +/* These three mappings are needed since there are two different netlist * + * conventions - in the cluster level, ports and port pins are used * + * while in the post-pack level, block pins are used. The reason block * + * type is used instead of blocks is to save memories. */ + + /* f_port_from_blk_pin array allow us to quickly find what port a block * + * pin corresponds to. * + * [0...num_types-1][0...blk_pin_count-1] * + * */ +static int ** f_port_from_blk_pin = NULL; + +/* f_port_pin_from_blk_pin array allow us to quickly find what port pin a* + * block pin corresponds to. * + * [0...num_types-1][0...blk_pin_count-1] */ +static int ** f_port_pin_from_blk_pin = NULL; + +/* f_port_pin_to_block_pin array allows us to quickly find what block * + * pin a port pin corresponds to. * + * [0...num_types-1][0...num_ports-1][0...num_port_pins-1] */ +static int *** f_blk_pin_from_port_pin = NULL; + + +/******************** Subroutine declarations ********************************/ + +/* Allocates and loads f_port_from_blk_pin and f_port_pin_from_blk_pin * + * arrays. * + * The arrays are freed in free_placement_structs() */ +static void alloc_and_load_port_pin_from_blk_pin(void); + +/* Allocates and loads blk_pin_from_port_pin array. * + * The arrays are freed in free_placement_structs() */ +static void alloc_and_load_blk_pin_from_port_pin(void); + +/* Go through all the ports in all the blocks to find the port that has the same * + * name as port_name and belongs to the block type that has the name pb_type_name. * + * Then, check that whether start_pin_index and end_pin_index are specified. If * + * they are, mark down the pins from start_pin_index to end_pin_index, inclusive. * + * Otherwise, mark down all the pins in that port. */ +static void mark_direct_of_ports (int idirect, int direct_type, char * pb_type_name, + char * port_name, int end_pin_index, int start_pin_index, char * src_string, + int line, int ** idirect_from_blk_pin, int ** direct_type_from_blk_pin); + +/* Mark the pin entry in idirect_from_blk_pin with idirect and the pin entry in * + * direct_type_from_blk_pin with direct_type from start_pin_index to * + * end_pin_index. */ +static void mark_direct_of_pins(int start_pin_index, int end_pin_index, int itype, + int iport, int ** idirect_from_blk_pin, int idirect, + int ** direct_type_from_blk_pin, int direct_type, int line, char * src_string); + +/******************** Subroutine definitions *********************************/ + +/** + * print tabs given number of tabs to file + */ +void print_tabs(FILE * fpout, int num_tab) { + int i; + for (i = 0; i < num_tab; i++) { + fprintf(fpout, "\t"); + } +} + +/* Points the grid structure back to the blocks list */ +void sync_grid_to_blocks(INP int L_num_blocks, + INP const struct s_block block_list[], INP int L_nx, INP int L_ny, + INOUTP struct s_grid_tile **L_grid) { + int i, j, k; + + /* Reset usage and allocate blocks list if needed */ + for (j = 0; j <= (L_ny + 1); ++j) { + for (i = 0; i <= (L_nx + 1); ++i) { + L_grid[i][j].usage = 0; + if (L_grid[i][j].type) { + /* If already allocated, leave it since size doesn't change */ + if (NULL == L_grid[i][j].blocks) { + L_grid[i][j].blocks = (int *) my_malloc( + sizeof(int) * L_grid[i][j].type->capacity); + + /* Set them as unconnected */ + for (k = 0; k < L_grid[i][j].type->capacity; ++k) { + L_grid[i][j].blocks[k] = OPEN; + } + } + } + } + } + + /* Go through each block */ + for (i = 0; i < L_num_blocks; ++i) { + /* Check range of block coords */ + if (block[i].x < 0 || block[i].x > (L_nx + 1) || block[i].y < 0 + || (block[i].y + block[i].type->height - 1) > (L_ny + 1) + || block[i].z < 0 || block[i].z > (block[i].type->capacity)) { + vpr_printf(TIO_MESSAGE_ERROR, "Block %d is at invalid location (%d, %d, %d).\n", + i, block[i].x, block[i].y, block[i].z); + exit(1); + } + + /* Check types match */ + if (block[i].type != L_grid[block[i].x][block[i].y].type) { + vpr_printf(TIO_MESSAGE_ERROR, "A block is in a grid location (%d x %d) with a conflicting type.\n", + block[i].x, block[i].y); + exit(1); + } + + /* Check already in use */ + if (OPEN != L_grid[block[i].x][block[i].y].blocks[block[i].z]) { + vpr_printf(TIO_MESSAGE_ERROR, "Location (%d, %d, %d) is used more than once.\n", + block[i].x, block[i].y, block[i].z); + exit(1); + } + + if (L_grid[block[i].x][block[i].y].offset != 0) { + vpr_printf(TIO_MESSAGE_ERROR, "Large block not aligned in placment for block %d at (%d, %d, %d).", + i, block[i].x, block[i].y, block[i].z); + exit(1); + } + + /* Set the block */ + for (j = 0; j < block[i].type->height; j++) { + L_grid[block[i].x][block[i].y + j].blocks[block[i].z] = i; + L_grid[block[i].x][block[i].y + j].usage++; + assert(L_grid[block[i].x][block[i].y + j].offset == j); + } + } +} + +boolean is_opin(int ipin, t_type_ptr type) { + + /* Returns TRUE if this clb pin is an output, FALSE otherwise. */ + + int iclass; + + iclass = type->pin_class[ipin]; + + if (type->class_inf[iclass].type == DRIVER) + return (TRUE); + else + return (FALSE); +} + +void get_class_range_for_block(INP int iblk, OUTP int *class_low, + OUTP int *class_high) { + /* Assumes that the placement has been done so each block has a set of pins allocated to it */ + t_type_ptr type; + + type = block[iblk].type; + assert(type->num_class % type->capacity == 0); + *class_low = block[iblk].z * (type->num_class / type->capacity); + *class_high = (block[iblk].z + 1) * (type->num_class / type->capacity) - 1; +} + +int get_max_primitives_in_pb_type(t_pb_type *pb_type) { + int i, j; + int max_size, temp_size; + if (pb_type->modes == 0) { + max_size = 1; + } else { + max_size = 0; + temp_size = 0; + for (i = 0; i < pb_type->num_modes; i++) { + for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { + temp_size += pb_type->modes[i].pb_type_children[j].num_pb + * get_max_primitives_in_pb_type( + &pb_type->modes[i].pb_type_children[j]); + } + if (temp_size > max_size) { + max_size = temp_size; + } + } + } + return max_size; +} + +/* finds maximum number of nets that can be contained in pb_type, this is bounded by the number of driving pins */ +int get_max_nets_in_pb_type(const t_pb_type *pb_type) { + int i, j; + int max_nets, temp_nets; + if (pb_type->modes == 0) { + max_nets = pb_type->num_output_pins; + } else { + max_nets = 0; + for (i = 0; i < pb_type->num_modes; i++) { + temp_nets = 0; + for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { + temp_nets += pb_type->modes[i].pb_type_children[j].num_pb + * get_max_nets_in_pb_type( + &pb_type->modes[i].pb_type_children[j]); + } + if (temp_nets > max_nets) { + max_nets = temp_nets; + } + } + } + if (pb_type->parent_mode == NULL) { + max_nets += pb_type->num_input_pins + pb_type->num_output_pins + + pb_type->num_clock_pins; + } + return max_nets; +} + +int get_max_depth_of_pb_type(t_pb_type *pb_type) { + int i, j; + int max_depth, temp_depth; + max_depth = pb_type->depth; + for (i = 0; i < pb_type->num_modes; i++) { + for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { + temp_depth = get_max_depth_of_pb_type( + &pb_type->modes[i].pb_type_children[j]); + if (temp_depth > max_depth) { + max_depth = temp_depth; + } + } + } + return max_depth; +} + +/** + * given a primitive type and a logical block, is the mapping legal + */ +boolean primitive_type_feasible(int iblk, const t_pb_type *cur_pb_type) { + t_model_ports *port; + int i, j; + boolean second_pass; + + if (cur_pb_type == NULL) { + return FALSE; + } + + /* check if ports are big enough */ + port = logical_block[iblk].model->inputs; + second_pass = FALSE; + while (port || !second_pass) { + /* TODO: This is slow if the number of ports are large, fix if becomes a problem */ + if (!port) { + second_pass = TRUE; + port = logical_block[iblk].model->outputs; + } + for (i = 0; i < cur_pb_type->num_ports; i++) { + if (cur_pb_type->ports[i].model_port == port) { + for (j = cur_pb_type->ports[i].num_pins; j < port->size; j++) { + if (port->dir == IN_PORT && !port->is_clock) { + if (logical_block[iblk].input_nets[port->index][j] + != OPEN) { + return FALSE; + } + } else if (port->dir == OUT_PORT) { + if (logical_block[iblk].output_nets[port->index][j] + != OPEN) { + return FALSE; + } + } else { + assert(port->dir == IN_PORT && port->is_clock); + assert(j == 0); + if (logical_block[iblk].clock_net != OPEN) { + return FALSE; + } + } + } + break; + } + } + if (i == cur_pb_type->num_ports) { + if ((logical_block[iblk].model->inputs != NULL && !second_pass) + || (logical_block[iblk].model->outputs != NULL + && second_pass)) { + /* physical port not found */ + return FALSE; + } + } + if (port) { + port = port->next; + } + } + return TRUE; +} + + +/** + * Return pb_graph_node pin from model port and pin + * NULL if not found + */ +t_pb_graph_pin* get_pb_graph_node_pin_from_model_port_pin(t_model_ports *model_port, int model_pin, t_pb_graph_node *pb_graph_node) { + int i; + + if(model_port->dir == IN_PORT) { + if(model_port->is_clock == FALSE) { + for (i = 0; i < pb_graph_node->num_input_ports; i++) { + if (pb_graph_node->input_pins[i][0].port->model_port == model_port) { + if(pb_graph_node->num_input_pins[i] > model_pin) { + return &pb_graph_node->input_pins[i][model_pin]; + } else { + return NULL; + } + } + } + } else { + for (i = 0; i < pb_graph_node->num_clock_ports; i++) { + if (pb_graph_node->clock_pins[i][0].port->model_port == model_port) { + if(pb_graph_node->num_clock_pins[i] > model_pin) { + return &pb_graph_node->clock_pins[i][model_pin]; + } else { + return NULL; + } + } + } + } + } else { + assert(model_port->dir == OUT_PORT); + for (i = 0; i < pb_graph_node->num_output_ports; i++) { + if (pb_graph_node->output_pins[i][0].port->model_port == model_port) { + if(pb_graph_node->num_output_pins[i] > model_pin) { + return &pb_graph_node->output_pins[i][model_pin]; + } else { + return NULL; + } + } + } + } + return NULL; +} + +t_pb_graph_pin* get_pb_graph_node_pin_from_vpack_net(int inet, int ipin) { + int ilogical_block; + t_model_ports *port; + + ilogical_block = vpack_net[inet].node_block[ipin]; + + assert(ilogical_block != OPEN); + if(logical_block[ilogical_block].pb == NULL) { + /* This net has not been packed yet thus pb_graph_pin does not exist */ + return NULL; + } + + if(ipin > 0) { + port = logical_block[ilogical_block].model->inputs; + if(vpack_net[inet].is_global) { + while(port != NULL) { + if(port->is_clock) { + if(port->index == vpack_net[inet].node_block_port[ipin]) { + break; + } + } + port = port->next; + } + } else { + while(port != NULL) { + if(!port->is_clock) { + if(port->index == vpack_net[inet].node_block_port[ipin]) { + break; + } + } + port = port->next; + } + } + } else { + /* This is an output pin */ + port = logical_block[ilogical_block].model->outputs; + while(port != NULL) { + if(port->index == vpack_net[inet].node_block_port[ipin]) { + break; + } + port = port->next; + } + } + + assert(port != NULL); + return get_pb_graph_node_pin_from_model_port_pin(port, vpack_net[inet].node_block_pin[ipin], logical_block[ilogical_block].pb->pb_graph_node); +} + +t_pb_graph_pin* get_pb_graph_node_pin_from_clb_net(int inet, int ipin) { + int iblock, target_pin; + t_pb_graph_node *pb_graph_node; + + iblock = clb_net[inet].node_block[ipin]; + pb_graph_node = block[iblock].pb->pb_graph_node; + + target_pin = clb_net[inet].node_block_pin[ipin]; + + return get_pb_graph_node_pin_from_block_pin(iblock, target_pin); +} + +t_pb_graph_pin* get_pb_graph_node_pin_from_block_pin(int iblock, int ipin) { + int i, count; + const t_pb_type *pb_type; + t_pb_graph_node *pb_graph_node; + + pb_graph_node = block[iblock].pb->pb_graph_node; + pb_type = pb_graph_node->pb_type; + + /* If this is post-placed, then the ipin may have been shuffled up by the z * num_pins, + bring it back down to 0..num_pins-1 range for easier analysis */ + ipin %= (pb_type->num_input_pins + pb_type->num_output_pins + pb_type->num_clock_pins); + + if(ipin < pb_type->num_input_pins) { + count = ipin; + for(i = 0; i < pb_graph_node->num_input_ports; i++) { + if(count - pb_graph_node->num_input_pins[i] >= 0) { + count -= pb_graph_node->num_input_pins[i]; + } else { + return &pb_graph_node->input_pins[i][count]; + } + } + } else if (ipin < pb_type->num_input_pins + pb_type->num_output_pins) { + count = ipin - pb_type->num_input_pins; + for(i = 0; i < pb_graph_node->num_output_ports; i++) { + if(count - pb_graph_node->num_output_pins[i] >= 0) { + count -= pb_graph_node->num_output_pins[i]; + } else { + return &pb_graph_node->output_pins[i][count]; + } + } + } else { + count = ipin - pb_type->num_input_pins - pb_type->num_output_pins; + for(i = 0; i < pb_graph_node->num_clock_ports; i++) { + if(count - pb_graph_node->num_clock_pins[i] >= 0) { + count -= pb_graph_node->num_clock_pins[i]; + } else { + return &pb_graph_node->clock_pins[i][count]; + } + } + } + assert(0); + return NULL; +} + + +/** + * Determine cost for using primitive within a complex block, should use primitives of low cost before selecting primitives of high cost + For now, assume primitives that have a lot of pins are scarcer than those without so use primitives with less pins before those with more + */ +float compute_primitive_base_cost(INP t_pb_graph_node *primitive) { + return (primitive->pb_type->num_input_pins + + primitive->pb_type->num_output_pins + + primitive->pb_type->num_clock_pins); +} + +int num_ext_inputs_logical_block(int iblk) { + + /* Returns the number of input pins on this logical_block that must be hooked * + * up through external interconnect. That is, the number of input * + * pins used - the number which connect (internally) to the outputs. */ + + int ext_inps, output_net, ipin, opin; + + t_model_ports *port, *out_port; + + /* TODO: process to get ext_inps is slow, should cache in lookup table */ + ext_inps = 0; + port = logical_block[iblk].model->inputs; + while (port) { + if (port->is_clock == FALSE) { + for (ipin = 0; ipin < port->size; ipin++) { + if (logical_block[iblk].input_nets[port->index][ipin] != OPEN) { + ext_inps++; + } + out_port = logical_block[iblk].model->outputs; + while (out_port) { + for (opin = 0; opin < out_port->size; opin++) { + output_net = + logical_block[iblk].output_nets[out_port->index][opin]; + if (output_net == OPEN) + continue; + /* TODO: I could speed things up a bit by computing the number of inputs * + * and number of external inputs for each logic logical_block at the start of * + * clustering and storing them in arrays. Look into if speed is a * + * problem. */ + + if (logical_block[iblk].input_nets[port->index][ipin] + == output_net) { + ext_inps--; + break; + } + } + out_port = out_port->next; + } + } + } + port = port->next; + } + + assert(ext_inps >= 0); + + return (ext_inps); +} + + +void free_cb(t_pb *pb) { + const t_pb_type * pb_type; + int i, total_nodes; + + pb_type = pb->pb_graph_node->pb_type; + + total_nodes = pb->pb_graph_node->total_pb_pins + pb_type->num_input_pins + + pb_type->num_output_pins + pb_type->num_clock_pins; + + for (i = 0; i < total_nodes; i++) { + if (pb->rr_graph[i].edges != NULL) { + free(pb->rr_graph[i].edges); + } + if (pb->rr_graph[i].switches != NULL) { + free(pb->rr_graph[i].switches); + } + } + free(pb->rr_graph); + free_pb(pb); +} + +void free_pb(t_pb *pb) { + const t_pb_type * pb_type; + int i, j, mode; + struct s_linked_vptr *revalid_molecule; + t_pack_molecule *cur_molecule; + + pb_type = pb->pb_graph_node->pb_type; + + if (pb_type->blif_model == NULL) { + mode = pb->mode; + for (i = 0; + i < pb_type->modes[mode].num_pb_type_children + && pb->child_pbs != NULL; i++) { + for (j = 0; + j < pb_type->modes[mode].pb_type_children[i].num_pb + && pb->child_pbs[i] != NULL; j++) { + if (pb->child_pbs[i][j].name != NULL || pb->child_pbs[i][j].child_pbs != NULL) { + free_pb(&pb->child_pbs[i][j]); + } + } + if (pb->child_pbs[i]) + free(pb->child_pbs[i]); + } + if (pb->child_pbs) + free(pb->child_pbs); + pb->child_pbs = NULL; + + if (pb->local_nets != NULL) { + for (i = 0; i < pb->num_local_nets; i++) { + free(pb->local_nets[i].node_block); + free(pb->local_nets[i].node_block_port); + free(pb->local_nets[i].node_block_pin); + if (pb->local_nets[i].name != NULL) { + free(pb->local_nets[i].name); + } + } + free(pb->local_nets); + pb->local_nets = NULL; + } + + if (pb->rr_node_to_pb_mapping != NULL) { + free(pb->rr_node_to_pb_mapping); + pb->rr_node_to_pb_mapping = NULL; + } + + if (pb->name) + free(pb->name); + pb->name = NULL; + } else { + /* Primitive */ + if (pb->name) + free(pb->name); + pb->name = NULL; + if (pb->lut_pin_remap) { + free(pb->lut_pin_remap); + } + pb->lut_pin_remap = NULL; + if (pb->logical_block != OPEN && logical_block != NULL) { + logical_block[pb->logical_block].clb_index = NO_CLUSTER; + logical_block[pb->logical_block].pb = NULL; + /* If any molecules were marked invalid because of this logic block getting packed, mark them valid */ + revalid_molecule = logical_block[pb->logical_block].packed_molecules; + while (revalid_molecule != NULL) { + cur_molecule = (t_pack_molecule*)revalid_molecule->data_vptr; + if (cur_molecule->valid == FALSE) { + for (i = 0; i < get_array_size_of_molecule(cur_molecule); i++) { + if (cur_molecule->logical_block_ptrs[i] != NULL) { + if (cur_molecule->logical_block_ptrs[i]->clb_index != OPEN) { + break; + } + } + } + /* All logical blocks are open for this molecule, place back in queue */ + if (i == get_array_size_of_molecule(cur_molecule)) { + cur_molecule->valid = TRUE; + } + } + revalid_molecule = revalid_molecule->next; + } + } + pb->logical_block = OPEN; + } + free_pb_stats(pb); +} + +void free_pb_stats(t_pb *pb) { + int i; + t_pb_graph_node *pb_graph_node = pb->pb_graph_node; + + if(pb->pb_stats == NULL) { + return; + } + + pb->pb_stats->gain.clear(); + pb->pb_stats->timinggain.clear(); + pb->pb_stats->sharinggain.clear(); + pb->pb_stats->hillgain.clear(); + pb->pb_stats->connectiongain.clear(); + pb->pb_stats->num_pins_of_net_in_pb.clear(); + + if(pb->pb_stats->marked_blocks != NULL) { + for (i = 0; i < pb_graph_node->num_input_pin_class; i++) { + free(pb->pb_stats->input_pins_used[i]); + free(pb->pb_stats->lookahead_input_pins_used[i]); + } + free(pb->pb_stats->input_pins_used); + free(pb->pb_stats->lookahead_input_pins_used); + for (i = 0; i < pb_graph_node->num_output_pin_class; i++) { + free(pb->pb_stats->output_pins_used[i]); + free(pb->pb_stats->lookahead_output_pins_used[i]); + } + free(pb->pb_stats->output_pins_used); + free(pb->pb_stats->lookahead_output_pins_used); + free(pb->pb_stats->feasible_blocks); + free(pb->pb_stats->marked_nets); + free(pb->pb_stats->marked_blocks); + } + pb->pb_stats->marked_blocks = NULL; + delete pb->pb_stats; + pb->pb_stats = NULL; +} + +int ** alloc_and_load_net_pin_index() { + + /* Allocates and loads net_pin_index array, this array allows us to quickly * + * find what pin on the net a block pin corresponds to. Returns the pointer * + * to the 2D net_pin_index array. */ + + int inet, netpin, blk, iblk, ipin, itype, **temp_net_pin_index, max_pins_per_clb = 0; + t_type_ptr type; + + /* Compute required size. */ + for (itype = 0; itype < num_types; itype++) + max_pins_per_clb = std::max(max_pins_per_clb, type_descriptors[itype].num_pins); + + /* Allocate for maximum size. */ + temp_net_pin_index = (int **) alloc_matrix(0, num_blocks - 1, 0, + max_pins_per_clb - 1, sizeof(int)); + + /* Initialize values to OPEN */ + for (iblk = 0; iblk < num_blocks; iblk++) { + type = block[iblk].type; + for (ipin = 0; ipin < type->num_pins; ipin++) { + temp_net_pin_index[iblk][ipin] = OPEN; + } + } + + /* Load the values */ + for (inet = 0; inet < num_nets; inet++) { + if (clb_net[inet].is_global) + continue; + for (netpin = 0; netpin <= clb_net[inet].num_sinks; netpin++) { + blk = clb_net[inet].node_block[netpin]; + temp_net_pin_index[blk][clb_net[inet].node_block_pin[netpin]] = netpin; + } + } + + /* Returns the pointers to the 2D array. */ + return temp_net_pin_index; +} + +/*************************************************************************************** + Y.G.THIEN + 29 AUG 2012 + + * The following functions maps the block pins indices for all block types to the * + * corresponding port indices and port_pin indices. This is necessary since there are * + * different netlist conventions - in the cluster level, ports and port pins are used * + * while in the post-pack level, block pins are used. * + * * + ***************************************************************************************/ + +void get_port_pin_from_blk_pin(int blk_type_index, int blk_pin, int * port, + int * port_pin) { + + /* These two mappings are needed since there are two different netlist * + * conventions - in the cluster level, ports and port pins are used * + * while in the post-pack level, block pins are used. The reason block * + * type is used instead of blocks is that the mapping is the same for * + * blocks belonging to the same block type. * + * * + * f_port_from_blk_pin array allow us to quickly find what port a * + * block pin corresponds to. * + * [0...num_types-1][0...blk_pin_count-1] * + * * + * f_port_pin_from_blk_pin array allow us to quickly find what port * + * pin a block pin corresponds to. * + * [0...num_types-1][0...blk_pin_count-1] */ + + /* If either one of the arrays is not allocated and loaded, it is * + * corrupted, so free both of them. */ + if ((f_port_from_blk_pin == NULL && f_port_pin_from_blk_pin != NULL) + || (f_port_from_blk_pin != NULL && f_port_pin_from_blk_pin == NULL)){ + free_port_pin_from_blk_pin(); + } + + /* If the arrays are not allocated and loaded, allocate it. */ + if (f_port_from_blk_pin == NULL && f_port_pin_from_blk_pin == NULL) { + alloc_and_load_port_pin_from_blk_pin(); + } + + /* Return the port and port_pin for the pin. */ + *port = f_port_from_blk_pin[blk_type_index][blk_pin]; + *port_pin = f_port_pin_from_blk_pin[blk_type_index][blk_pin]; + +} + +void free_port_pin_from_blk_pin(void) { + + /* Frees the f_port_from_blk_pin and f_port_pin_from_blk_pin arrays. * + * * + * This function is called when the file-scope arrays are corrupted. * + * Otherwise, the arrays are freed in free_placement_structs() */ + + int itype; + + if (f_port_from_blk_pin != NULL) { + for (itype = 1; itype < num_types; itype++) { + free(f_port_from_blk_pin[itype]); + } + free(f_port_from_blk_pin); + + f_port_from_blk_pin = NULL; + } + + if (f_port_pin_from_blk_pin != NULL) { + for (itype = 1; itype < num_types; itype++) { + free(f_port_pin_from_blk_pin[itype]); + } + free(f_port_pin_from_blk_pin); + + f_port_pin_from_blk_pin = NULL; + } + +} + +static void alloc_and_load_port_pin_from_blk_pin(void) { + + /* Allocates and loads f_port_from_blk_pin and f_port_pin_from_blk_pin * + * arrays. * + * * + * The arrays are freed in free_placement_structs() */ + + int ** temp_port_from_blk_pin = NULL; + int ** temp_port_pin_from_blk_pin = NULL; + int itype, iblk_pin, iport, iport_pin; + int blk_pin_count, num_port_pins, num_ports; + + /* Allocate and initialize the values to OPEN (-1). */ + temp_port_from_blk_pin = (int **) my_malloc(num_types* sizeof(int*)); + temp_port_pin_from_blk_pin = (int **) my_malloc(num_types* sizeof(int*)); + for (itype = 1; itype < num_types; itype++) { + + blk_pin_count = type_descriptors[itype].num_pins; + + temp_port_from_blk_pin[itype] = (int *) my_malloc(blk_pin_count* sizeof(int)); + temp_port_pin_from_blk_pin[itype] = (int *) my_malloc(blk_pin_count* sizeof(int)); + + for (iblk_pin = 0; iblk_pin < blk_pin_count; iblk_pin++) { + temp_port_from_blk_pin[itype][iblk_pin] = OPEN; + temp_port_pin_from_blk_pin[itype][iblk_pin] = OPEN; + } + } + + /* Load the values */ + /* itype starts from 1 since type_descriptors[0] is the EMPTY_TYPE. */ + for (itype = 1; itype < num_types; itype++) { + + blk_pin_count = 0; + num_ports = type_descriptors[itype].pb_type->num_ports; + + for (iport = 0; iport < num_ports; iport++) { + + num_port_pins = type_descriptors[itype].pb_type->ports[iport].num_pins; + + for (iport_pin = 0; iport_pin < num_port_pins; iport_pin++) { + + temp_port_from_blk_pin[itype][blk_pin_count] = iport; + temp_port_pin_from_blk_pin[itype][blk_pin_count] = iport_pin; + blk_pin_count++; + } + } + } + + /* Sets the file_scope variables to point at the arrays. */ + f_port_from_blk_pin = temp_port_from_blk_pin; + f_port_pin_from_blk_pin = temp_port_pin_from_blk_pin; +} + +void get_blk_pin_from_port_pin(int blk_type_index, int port,int port_pin, + int * blk_pin) { + + /* This mapping is needed since there are two different netlist * + * conventions - in the cluster level, ports and port pins are used * + * while in the post-pack level, block pins are used. The reason block * + * type is used instead of blocks is to save memories. * + * * + * f_port_pin_to_block_pin array allows us to quickly find what block * + * pin a port pin corresponds to. * + * [0...num_types-1][0...num_ports-1][0...num_port_pins-1] */ + + /* If the array is not allocated and loaded, allocate it. */ + if (f_blk_pin_from_port_pin == NULL) { + alloc_and_load_blk_pin_from_port_pin(); + } + + /* Return the port and port_pin for the pin. */ + *blk_pin = f_blk_pin_from_port_pin[blk_type_index][port][port_pin]; + +} + +void free_blk_pin_from_port_pin(void) { + + /* Frees the f_blk_pin_from_port_pin array. * + * * + * This function is called when the arrays are freed in * + * free_placement_structs() */ + + int itype, iport, num_ports; + + if (f_blk_pin_from_port_pin != NULL) { + + for (itype = 1; itype < num_types; itype++) { + num_ports = type_descriptors[itype].pb_type->num_ports; + for (iport = 0; iport < num_ports; iport++) { + free(f_blk_pin_from_port_pin[itype][iport]); + } + free(f_blk_pin_from_port_pin[itype]); + } + free(f_blk_pin_from_port_pin); + + f_blk_pin_from_port_pin = NULL; + } + +} + +static void alloc_and_load_blk_pin_from_port_pin(void) { + + /* Allocates and loads blk_pin_from_port_pin array. * + * * + * The arrays are freed in free_placement_structs() */ + + int *** temp_blk_pin_from_port_pin = NULL; + int itype, iport, iport_pin; + int blk_pin_count, num_port_pins, num_ports; + + /* Allocate and initialize the values to OPEN (-1). */ + temp_blk_pin_from_port_pin = (int ***) my_malloc(num_types * sizeof(int**)); + for (itype = 1; itype < num_types; itype++) { + num_ports = type_descriptors[itype].pb_type->num_ports; + temp_blk_pin_from_port_pin[itype] = (int **) my_malloc(num_ports * sizeof(int*)); + for (iport = 0; iport < num_ports; iport++) { + num_port_pins = type_descriptors[itype].pb_type->ports[iport].num_pins; + temp_blk_pin_from_port_pin[itype][iport] = (int *) my_malloc(num_port_pins * sizeof(int)); + + for(iport_pin = 0; iport_pin < num_port_pins; iport_pin ++) { + temp_blk_pin_from_port_pin[itype][iport][iport_pin] = OPEN; + } + } + } + + /* Load the values */ + /* itype starts from 1 since type_descriptors[0] is the EMPTY_TYPE. */ + for (itype = 1; itype < num_types; itype++) { + blk_pin_count = 0; + num_ports = type_descriptors[itype].pb_type->num_ports; + for (iport = 0; iport < num_ports; iport++) { + num_port_pins = type_descriptors[itype].pb_type->ports[iport].num_pins; + for (iport_pin = 0; iport_pin < num_port_pins; iport_pin++) { + temp_blk_pin_from_port_pin[itype][iport][iport_pin] = blk_pin_count; + blk_pin_count++; + } + } + } + + /* Sets the file_scope variables to point at the arrays. */ + f_blk_pin_from_port_pin = temp_blk_pin_from_port_pin; +} + + +/*************************************************************************************** + Y.G.THIEN + 30 AUG 2012 + + * The following functions parses the direct connections' information obtained from * + * the arch file. Then, the functions map the block pins indices for all block types * + * to the corresponding idirect (the index of the direct connection as specified in * + * the arch file) and direct type (whether this pin is a SOURCE or a SINK for the * + * direct connection). If a pin is not part of any direct connections, the value * + * OPEN (-1) is stored in both entries. * + * * + * The mapping arrays are freed by the caller. Currently, this mapping is only used to * + * load placement macros in place_macro.c * + * * + ***************************************************************************************/ + +void parse_direct_pin_name(char * src_string, int line, int * start_pin_index, + int * end_pin_index, char * pb_type_name, char * port_name){ + + /* Parses out the pb_type_name and port_name from the direct passed in. * + * If the start_pin_index and end_pin_index is specified, parse them too. * + * Return the values parsed by reference. */ + + char source_string[MAX_STRING_LEN+1]; + char * find_format = NULL; + int ichar, match_count; + + // parse out the pb_type and port name, possibly pin_indices + find_format = strstr(src_string,"["); + if (find_format == NULL) { + /* Format "pb_type_name.port_name" */ + *start_pin_index = *end_pin_index = -1; + + strcpy (source_string, src_string); + for (ichar = 0; ichar < (int)(strlen(source_string)); ichar++) { + if (source_string[ichar] == '.') + source_string[ichar] = ' '; + } + + match_count = sscanf(source_string, "%s %s", pb_type_name, port_name); + if (match_count != 2){ + vpr_printf(TIO_MESSAGE_ERROR, "[LINE %d] Invalid pin - %s, " + "name should be in the format \"pb_type_name\".\"port_name\" or " + "\"pb_type_name\".\"port_name [end_pin_index:start_pin_index]\". " + " The end_pin_index and start_pin_index can be the same.\n", line, + src_string); + exit(1); + } + } else { + /* Format "pb_type_name.port_name [end_pin_index:start_pin_index]" */ + strcpy (source_string, src_string); + for (ichar = 0; ichar < (int)(strlen(source_string)); ichar++) { + if (source_string[ichar] == '.') + source_string[ichar] = ' '; + } + + match_count = sscanf(source_string, "%s %s [%d:%d]", + pb_type_name, port_name, + end_pin_index, start_pin_index); + if (match_count != 4){ + vpr_printf(TIO_MESSAGE_ERROR, "[LINE %d] Invalid pin - %s, " + "name should be in the format \"pb_type_name\".\"port_name\" or " + "\"pb_type_name\".\"port_name [end_pin_index:start_pin_index]\". " + " The end_pin_index and start_pin_index can be the same.\n", line, + src_string); + exit(1); + } + if (*end_pin_index < 0 || *start_pin_index < 0) { + vpr_printf(TIO_MESSAGE_ERROR, "[LINE %d] Invalid pin - %s, " + "the pin_index [end_pin_index:start_pin_index] should not " + "be a negative value.\n", line, src_string); + exit(1); + } + if ( *end_pin_index < *start_pin_index) { + vpr_printf(TIO_MESSAGE_ERROR, "[LINE %d] Invalid from_pin - %s, " + "the end_pin_index in [end_pin_index:start_pin_index] should " + "not be less than start_pin_index.\n", line, src_string); + exit(1); + } + } +} + +static void mark_direct_of_pins(int start_pin_index, int end_pin_index, int itype, + int iport, int ** idirect_from_blk_pin, int idirect, + int ** direct_type_from_blk_pin, int direct_type, int line, char * src_string) { + + /* Mark the pin entry in idirect_from_blk_pin with idirect and the pin entry in * + * direct_type_from_blk_pin with direct_type from start_pin_index to * + * end_pin_index. */ + + int iport_pin, iblk_pin; + + // Mark pins with indices from start_pin_index to end_pin_index, inclusive + for (iport_pin = start_pin_index; iport_pin <= end_pin_index; iport_pin++) { + get_blk_pin_from_port_pin(itype, iport, iport_pin, &iblk_pin); + + // Check the fc for the pin, direct chain link only if fc == 0 + if (type_descriptors[itype].Fc[iblk_pin] == 0) { + idirect_from_blk_pin[itype][iblk_pin] = idirect; + + // Check whether the pins are marked, errors out if so + if (direct_type_from_blk_pin[itype][iblk_pin] != OPEN) { + vpr_printf(TIO_MESSAGE_ERROR, "[LINE %d] Invalid pin - %s, " + "this pin is in more than one direct connection.\n", line, + src_string); + exit(1); + } else { + direct_type_from_blk_pin[itype][iblk_pin] = direct_type; + } + } + } // Finish marking all the pins + +} + +static void mark_direct_of_ports (int idirect, int direct_type, char * pb_type_name, + char * port_name, int end_pin_index, int start_pin_index, char * src_string, + int line, int ** idirect_from_blk_pin, int ** direct_type_from_blk_pin) { + + /* Go through all the ports in all the blocks to find the port that has the same * + * name as port_name and belongs to the block type that has the name pb_type_name. * + * Then, check that whether start_pin_index and end_pin_index are specified. If * + * they are, mark down the pins from start_pin_index to end_pin_index, inclusive. * + * Otherwise, mark down all the pins in that port. */ + + int num_ports, num_port_pins; + int itype, iport; + + // Go through all the block types + for (itype = 1; itype < num_types; itype++) { + + // Find blocks with the same pb_type_name + if (strcmp(type_descriptors[itype].pb_type->name, pb_type_name) == 0) { + num_ports = type_descriptors[itype].pb_type->num_ports; + for (iport = 0; iport < num_ports; iport++) { + // Find ports with the same port_name + if (strcmp(type_descriptors[itype].pb_type->ports[iport].name, port_name) == 0) { + num_port_pins = type_descriptors[itype].pb_type->ports[iport].num_pins; + + // Check whether the end_pin_index is valid + if (end_pin_index > num_port_pins) { + vpr_printf(TIO_MESSAGE_ERROR, "[LINE %d] Invalid pin - %s, " + "the end_pin_index in [end_pin_index:start_pin_index] should " + "be less than the num_port_pins %d.\n", line, + src_string, num_port_pins); + exit(1); + } + + // Check whether the pin indices are specified + if (start_pin_index >= 0 || end_pin_index >= 0) { + mark_direct_of_pins(start_pin_index, end_pin_index, itype, + iport, idirect_from_blk_pin, idirect, + direct_type_from_blk_pin, direct_type, line, src_string); + } else { + mark_direct_of_pins(0, num_port_pins-1, itype, + iport, idirect_from_blk_pin, idirect, + direct_type_from_blk_pin, direct_type, line, src_string); + } + } // Do nothing if port_name does not match + } // Finish going through all the ports + } // Do nothing if pb_type_name does not match + } // Finish going through all the blocks + +} + +void alloc_and_load_idirect_from_blk_pin(t_direct_inf* directs, int num_directs, + int *** idirect_from_blk_pin, int *** direct_type_from_blk_pin) { + + /* Allocates and loads idirect_from_blk_pin and direct_type_from_blk_pin arrays. * + * * + * For a bus (multiple bits) direct connection, all the pins in the bus are marked. * + * * + * idirect_from_blk_pin array allow us to quickly find pins that could be in a * + * direct connection. Values stored is the index of the possible direct connection * + * as specified in the arch file, OPEN (-1) is stored for pins that could not be * + * part of a direct chain conneciton. * + * * + * direct_type_from_blk_pin array stores the value SOURCE if the pin is the * + * from_pin, SINK if the pin is the to_pin in the direct connection as specified in * + * the arch file, OPEN (-1) is stored for pins that could not be part of a direct * + * chain conneciton. * + * * + * Stores the pointers to the two 2D arrays in the addresses passed in. * + * * + * The two arrays are freed by the caller(s). */ + + int itype, iblk_pin, idirect, num_type_pins; + int ** temp_idirect_from_blk_pin, ** temp_direct_type_from_blk_pin; + + char to_pb_type_name[MAX_STRING_LEN+1], to_port_name[MAX_STRING_LEN+1], + from_pb_type_name[MAX_STRING_LEN+1], from_port_name[MAX_STRING_LEN+1]; + int to_start_pin_index = -1, to_end_pin_index = -1; + int from_start_pin_index = -1, from_end_pin_index = -1; + + /* Allocate and initialize the values to OPEN (-1). */ + temp_idirect_from_blk_pin = (int **) my_malloc(num_types * sizeof(int *)); + temp_direct_type_from_blk_pin = (int **) my_malloc(num_types * sizeof(int *)); + for (itype = 1; itype < num_types; itype++) { + + num_type_pins = type_descriptors[itype].num_pins; + + temp_idirect_from_blk_pin[itype] = (int *) my_malloc(num_type_pins * sizeof(int)); + temp_direct_type_from_blk_pin[itype] = (int *) my_malloc(num_type_pins * sizeof(int)); + + /* Initialize values to OPEN */ + for (iblk_pin = 0; iblk_pin < num_type_pins; iblk_pin++) { + temp_idirect_from_blk_pin[itype][iblk_pin] = OPEN; + temp_direct_type_from_blk_pin[itype][iblk_pin] = OPEN; + } + } + + /* Load the values */ + // Go through directs and find pins with possible direct connections + for (idirect = 0; idirect < num_directs; idirect++) { + + // Parse out the pb_type and port name, possibly pin_indices from from_pin + parse_direct_pin_name(directs[idirect].from_pin, directs[idirect].line, + &from_end_pin_index, &from_start_pin_index, from_pb_type_name, from_port_name); + + // Parse out the pb_type and port name, possibly pin_indices from to_pin + parse_direct_pin_name(directs[idirect].to_pin, directs[idirect].line, + &to_end_pin_index, &to_start_pin_index, to_pb_type_name, to_port_name); + + + /* Now I have all the data that I need, I could go through all the block pins * + * in all the blocks to find all the pins that could have possible direct * + * connections. Mark all down all those pins with the idirect the pins belong * + * to and whether it is a source or a sink of the direct connection. */ + + // Find blocks with the same name as from_pb_type_name and from_port_name + mark_direct_of_ports (idirect, SOURCE, from_pb_type_name, from_port_name, + from_end_pin_index, from_start_pin_index, directs[idirect].from_pin, + directs[idirect].line, + temp_idirect_from_blk_pin, temp_direct_type_from_blk_pin); + + // Then, find blocks with the same name as to_pb_type_name and from_port_name + mark_direct_of_ports (idirect, SINK, to_pb_type_name, to_port_name, + to_end_pin_index, to_start_pin_index, directs[idirect].to_pin, + directs[idirect].line, + temp_idirect_from_blk_pin, temp_direct_type_from_blk_pin); + + } // Finish going through all the directs + + /* Returns the pointer to the 2D arrays by reference. */ + *idirect_from_blk_pin = temp_idirect_from_blk_pin; + *direct_type_from_blk_pin = temp_direct_type_from_blk_pin; + +} + diff --git a/vpr7_rram/vpr/SRC/util/vpr_utils.h b/vpr7_rram/vpr/SRC/util/vpr_utils.h new file mode 100755 index 000000000..8af30f3f7 --- /dev/null +++ b/vpr7_rram/vpr/SRC/util/vpr_utils.h @@ -0,0 +1,51 @@ +#ifndef VPR_UTILS_H +#define VPR_UTILS_H + +#include "util.h" + +void print_tabs(FILE * fpout, int num_tab); + +boolean is_opin(int ipin, t_type_ptr type); + +void get_class_range_for_block(INP int iblk, OUTP int *class_low, + OUTP int *class_high); + +void sync_grid_to_blocks(INP int L_num_blocks, + INP const struct s_block block_list[], INP int L_nx, INP int L_ny, + INOUTP struct s_grid_tile **L_grid); + +int get_max_primitives_in_pb_type(t_pb_type *pb_type); +int get_max_depth_of_pb_type(t_pb_type *pb_type); +int get_max_nets_in_pb_type(const t_pb_type *pb_type); +boolean primitive_type_feasible(int iblk, const t_pb_type *cur_pb_type); +t_pb_graph_pin* get_pb_graph_node_pin_from_model_port_pin(t_model_ports *model_port, int model_pin, t_pb_graph_node *pb_graph_node); +t_pb_graph_pin* get_pb_graph_node_pin_from_vpack_net(int inet, int ipin); +t_pb_graph_pin* get_pb_graph_node_pin_from_clb_net(int inet, int ipin); +t_pb_graph_pin* get_pb_graph_node_pin_from_block_pin(int iblock, int ipin); +float compute_primitive_base_cost(INP t_pb_graph_node *primitive); +int num_ext_inputs_logical_block(int iblk); + +int ** alloc_and_load_net_pin_index(); + +void get_port_pin_from_blk_pin(int blk_type_index, int blk_pin, int * port, + int * port_pin); +void free_port_pin_from_blk_pin(void); + +void get_blk_pin_from_port_pin(int blk_type_index, int port,int port_pin, + int * blk_pin); +void free_blk_pin_from_port_pin(void); + +void alloc_and_load_idirect_from_blk_pin(t_direct_inf* directs, int num_directs, + int *** idirect_from_blk_pin, int *** direct_type_from_blk_pin); + +void parse_direct_pin_name(char * src_string, int line, int * start_pin_index, + int * end_pin_index, char * pb_type_name, char * port_name); + + +void free_cb(t_pb *pb); +void free_pb_stats(t_pb *pb); +void free_pb(t_pb *pb); + + +#endif + diff --git a/vpr7_rram/vpr/SpiceNetlists/ff.sp b/vpr7_rram/vpr/SpiceNetlists/ff.sp new file mode 100644 index 000000000..e7261a945 --- /dev/null +++ b/vpr7_rram/vpr/SpiceNetlists/ff.sp @@ -0,0 +1,25 @@ +* Sub Circuits +* +* Static D Flip-flop +.subckt static_dff set rst clk D Q svdd sgnd size=1 +* Input inverter +Xinv_clk clk clk_b svdd sgnd inv size=size +Xinv_set set set_b svdd sgnd inv size=size +Xinv_rst rst rst_b svdd sgnd inv size=size +Xinv_d D s1_n1 svdd sgnd inv size=size +Xcpt0 s1_n1 s1_n2 clk_b clk svdd sgnd cpt nmos_size='size' pmos_size='size*beta' +Xset0 s1_n2 set_b svdd svdd vpr_pmos L=pl W='size*wp' +Xrst0 s1_n2 rst sgnd sgnd vpr_nmos L=nl W='size*wn' +Xinv1 s1_n2 s1_q svdd sgnd inv size=size +Xinv2 s1_q s1_n3 svdd sgnd inv size=size +Xcpt1 s1_n3 s1_n2 clk clk_b svdd sgnd cpt nmos_size='size' pmos_size='size*beta' +* Stage 2 +R3 s1_q s2_n1 0 +Xcpt2 s2_n1 s2_n2 clk clk_b svdd sgnd cpt nmos_size='size' pmos_size='size*beta' +Xrst1 s2_n2 rst_b svdd svdd vpr_pmos L=pl W='size*wp' +Xset1 s2_n2 set sgnd sgnd vpr_nmos L=nl W='size*wn' +Xinv4 s2_n2 Qb svdd sgnd inv size=size +Xinv5 Qb s2_n3 svdd sgnd inv size=size +Xcpt3 s2_n3 s2_n2 clk_b clk svdd sgnd cpt nmos_size='size' pmos_size='size*beta' +Xinv_out Qb Q svdd sgnd inv size=size +.eom static_dff diff --git a/vpr7_rram/vpr/SpiceNetlists/ff_tb.sp b/vpr7_rram/vpr/SpiceNetlists/ff_tb.sp new file mode 100644 index 000000000..efea18da4 --- /dev/null +++ b/vpr7_rram/vpr/SpiceNetlists/ff_tb.sp @@ -0,0 +1,68 @@ +Testbench for D-type Flip-flop with set and reset +********************************* +* HSPICE Netlist * +* Author: Xifan TANG * +* Organization: EPFL,LSI * +********************************* +* +* Use Standard CMOS Technology +****** Include Technology Library ****** +.lib '/home/xitang/tangxifan-eda-tools/branches/subvt_fpga/process/tsmc40nm/toplevel_crn45gs_2d5_v1d1_shrink0d9_embedded_usage.l' TOP_TT +****** Transistor Parameters ****** +.param beta=2 +.param nl=4e-08 +.param wn=1.4e-07 +.param pl=4e-08 +.param wp=1.4e-07 + +****** Include subckt netlists: NMOS and PMOS ***** +.include '/home/xitang/tangxifan-eda-tools/branches/vpr7_rram/vpr/spice_test/subckt/nmos_pmos.sp' +****** Include subckt netlists: Inverters, Buffers ***** +.include '/home/xitang/tangxifan-eda-tools/branches/vpr7_rram/vpr/spice_test/subckt/inv_buf_trans_gate.sp' + +.include '/home/xitang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' + +.param clk_freq = 1e9 +*Temperature +.temp 25 +*Global nodes +.global vdd gnd +*Print node capacitance +.option captab +*Print waveforms +.option POST +* Parameters for measurements +.param clk2d=3e-09 +.param clk_pwl=3e-09 +.param clk_pwh=1.5e-08 +.param slew=1e-11 +.param thold=3e-09 +.param vsp=0.9 +* Parameters for Measuring Slew +.param slew_upper_threshold_pct_rise=0.9 +.param slew_lower_threshold_pct_rise=0.1 +.param slew_upper_threshold_pct_fall=0.1 +.param slew_lower_threshold_pct_fall=0.9 +* Parameters for Measuring Delay +.param input_threshold_pct_rise=0.5 +.param input_threshold_pct_fall=0.5 +.param output_threshold_pct_rise=0.5 +.param output_threshold_pct_fall=0.5 + +Xdff[0] set rst clk d q vdd gnd static_dff + +Vsupply vdd gnd 'vsp' +*Stimulates +vset set gnd 0 +vrst rst gnd 0 +vclk_in clk gnd pulse (0 vsp '0.5/clk_freq' '0.025/clk_freq' '0.025/clk_freq' '0.4875/clk_freq' '1/clk_freq') +* Measuring Clk2Q, Setup Time and Hold Time +vdata D gnd pulse (0 vsp '0.25/clk_freq' '0.025/clk_freq' '0.025/clk_freq' '2*0.4875/clk_freq' '2/clk_freq') + +*Simulation +.tran 1e-15 '10/clk_freq' +.meas tran slew_q trig v(Q) val='slew_lower_threshold_pct_fall*vsp' fall=1 td='2*clk_pwl+clk_pwh+2*slew' ++ targ v(Q) val='slew_upper_threshold_pct_fall*vsp' fall=1 td='2*clk_pwl+clk_pwh+2*slew' +.meas tran clk2q trig v(CLK) val='input_threshold_pct_fall*vsp' rise=2 ++ targ v(Q) val='output_threshold_pct_fall*vsp' fall=1 td='2*clk_pwl+clk_pwh+2*slew' +.end TSPC Flip-flop with set and reset diff --git a/vpr7_rram/vpr/SpiceNetlists/io.sp b/vpr7_rram/vpr/SpiceNetlists/io.sp new file mode 100644 index 000000000..e5d757b16 --- /dev/null +++ b/vpr7_rram/vpr/SpiceNetlists/io.sp @@ -0,0 +1,11 @@ +* Sub Circuit +* IO pads +* When direction = 0, pad <= dout +* When direction = 1, pad => din +.subckt iopad zin dout din pad direction direction_inv svdd sgnd +Xbuf0 pad din_inter svdd sgnd buf size=2 +Xbuf1 dout pad_inter svdd sgnd buf size=2 +*Xinv0 direction direction_inv svdd sgnd inv size=1 +Xcpt0 din_inter din direction direction_inv svdd sgnd cpt +Xcpt1 pad_inter pad direction_inv direction svdd sgnd cpt +.eom iopad diff --git a/vpr7_rram/vpr/SpiceNetlists/sram.sp b/vpr7_rram/vpr/SpiceNetlists/sram.sp new file mode 100644 index 000000000..06d44db99 --- /dev/null +++ b/vpr7_rram/vpr/SpiceNetlists/sram.sp @@ -0,0 +1,10 @@ +* Sub Circuit +* SRAM +* Input to force write the stored bit +.subckt sram6T in out outb svdd sgnd size=1 +Xinv0 loop_out loop_outb svdd sgnd inv size=size +Xinv1 loop_outb loop_out svdd sgnd inv size=size +Xout_pt loop_out out svdd sgnd svdd sgnd cpt nmos_size='size' pmos_size='size*beta' +Xoutb_pt loop_outb outb svdd sgnd svdd sgnd cpt +Rin in loop_out 0 +.eom sram6T diff --git a/vpr7_rram/vpr/VerilogNetlists/ff.v b/vpr7_rram/vpr/VerilogNetlists/ff.v new file mode 100644 index 000000000..d88e1f289 --- /dev/null +++ b/vpr7_rram/vpr/VerilogNetlists/ff.v @@ -0,0 +1,100 @@ +//----------------------------------------------------- +// Design Name : static_dff +// File Name : ff.v +// Function : D flip-flop with asyn reset and set +// Coder : Xifan TANG +//----------------------------------------------------- +module static_dff ( +/* Global ports go first */ +input set, // set input +input reset, // Reset input +input clk, // Clock Input +/* Local ports follow */ +input D, // Data Input +output Q // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge clk or reset or set) +if (reset) begin + q_reg <= 1'b0; +end else if (set) begin + q_reg <= 1'b1; +end else begin + q_reg <= D; +end + +// Wire q_reg to Q +assign Q = q_reg; + +endmodule //End Of Module static_dff + +//----------------------------------------------------- +// Design Name : scan_chain_dff +// File Name : ff.v +// Function : D flip-flop with asyn reset and set +// Coder : Xifan TANG +//----------------------------------------------------- +module sc_dff ( +/* Global ports go first */ +input set, // set input +input reset, // Reset input +input clk, // Clock Input +/* Local ports follow */ +input D, // Data Input +output Q, // Q output +output Qb // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge clk or reset or set) +if (reset) begin + q_reg <= 1'b0; +end else if (set) begin + q_reg <= 1'b1; +end else begin + q_reg <= D; +end + +// Wire q_reg to Q +assign Q = q_reg; +assign Qb = ~Q; + +endmodule //End Of Module static_dff + +//----------------------------------------------------- +// Design Name : scan_chain_dff compact +// File Name : ff.v +// Function : Scan-chain D flip-flop without reset and set +// Coder : Xifan TANG +//----------------------------------------------------- +module sc_dff_compact ( +/* Global ports go first */ +input reset, // Reset input +input clk, // Clock Input +input clkb, // Clock Input +/* Local ports follow */ +input D, // Data Input +output Q, // Q output +output Qb // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge clk or reset) +if (reset) begin + q_reg <= 1'b0; +end else begin + q_reg <= D; +end + +// Wire q_reg to Q +assign Q = q_reg; +assign Qb = ~Q; + +endmodule //End Of Module static_dff diff --git a/vpr7_rram/vpr/VerilogNetlists/ff_tb.v b/vpr7_rram/vpr/VerilogNetlists/ff_tb.v new file mode 100644 index 000000000..183953d95 --- /dev/null +++ b/vpr7_rram/vpr/VerilogNetlists/ff_tb.v @@ -0,0 +1,64 @@ +//----------------------------------------------------- +// Design Name : testbench for static_dff +// File Name : ff_tb.v +// Function : D flip-flop with asyn reset and set +// Coder : Xifan TANG +//----------------------------------------------------- +//----- Time scale: simulation time step and accuracy ----- +`timescale 1ns / 1ps + +module static_dff_tb; +// voltage sources +wire set; +reg reset; +reg clk; +reg D; +wire Q; +// Parameters +parameter clk_period = 2; // [ns] a full clock period +parameter half_clk_period = clk_period / 2; // [ns] a half clock period +parameter d_period = 2 * clk_period; // [ns] two clock period +parameter reset_period = 8 * clk_period; // [ns] a full clock period + +// Unit Under Test +static_dff U0 (set, reset, clk, D, Q); + +// Voltage stimuli +// Reset : enable in the first clock cycle and then disabled +initial +begin + reset = 1'b1; + #clk_period reset = ~reset; +end +always +begin + #reset_period reset = ~reset; +end + +// set : alway disabled +assign set = 1'b0; + +// clk: clock generator +initial +begin + clk = 1'b0; +end +always +begin + #half_clk_period clk = ~clk; +end + +// D: input, flip every two clock cycles +initial +begin + D = 1'b0; +end +always +begin + #d_period D = ~D; +end + +// Q is an output +// + +endmodule diff --git a/vpr7_rram/vpr/VerilogNetlists/io.v b/vpr7_rram/vpr/VerilogNetlists/io.v new file mode 100644 index 000000000..e3468c370 --- /dev/null +++ b/vpr7_rram/vpr/VerilogNetlists/io.v @@ -0,0 +1,16 @@ +//------ Module: iopad -----// +//------ Verilog file: io.v -----// +//------ Author: Xifan TANG -----// +module iopad( +input zin, // Set output to be Z +input dout, // Data output +output din, // Data input +inout pad, // bi-directional pad +input direction, // enable signal to control direction of iopad +input direction_inv // enable signal to control direction of iopad +); + //----- when direction enabled, the signal is propagated from pad to din + assign din = direction ? pad : 1'bz; + //----- when direction is disabled, the signal is propagated from dout to pad + assign pad = direction ? 1'bz : dout; +endmodule diff --git a/vpr7_rram/vpr/VerilogNetlists/lb_tb.v b/vpr7_rram/vpr/VerilogNetlists/lb_tb.v new file mode 100644 index 000000000..705970fd6 --- /dev/null +++ b/vpr7_rram/vpr/VerilogNetlists/lb_tb.v @@ -0,0 +1,199 @@ +//----------------------------------------------------- +// Design Name : testbench for logic blocks +// File Name : lb_tb.v +// Function : Configurable logic block +// Coder : Xifan TANG +//----------------------------------------------------- +//----- Time scale: simulation time step and accuracy ----- +`timescale 1ns / 1ps + +module lb_tb; +// Parameters +parameter SIZE_IN = 40; //---- MUX input size +parameter SIZE_OUT = 10; //---- MUX input size +parameter SIZE_RESERV_BLWL = 49 + 1; //---- MUX input size +parameter SIZE_BLWL = 1019 - 310 + 1; //---- MUX input size +parameter prog_clk_period = 1; // [ns] half clock period +parameter op_clk_period = 1; // [ns] half clock period +parameter config_period = 2 * prog_clk_period; // [ns] One full clock period +parameter operating_period = SIZE_IN * 2 * op_clk_period; // [ns] One full clock period + +// Ports +wire [0:SIZE_IN-1] lb_in; +wire [0:SIZE_IN-1] lb_out; +wire lb_clk; +wire [0:SIZE_RESERV_BLWL-1] reserv_bl; +wire [0:SIZE_RESERV_BLWL-1] reserv_wl; +wire [0:SIZE_BLWL-1] bl; +wire [0:SIZE_BLWL-1] wl; +wire prog_EN; +wire prog_ENb; +wire zin; +wire nequalize; +wire read; +wire clk; +wire Reset; +wire Set; +// Clocks +wire prog_clock; +wire op_clock; + +// Registered port +reg [0:SIZE_IN-1] lb_in_reg; +reg [0:SIZE_RESERV_BLWL-1] reserv_bl_reg; +reg [0:SIZE_RESERV_BLWL-1] reserv_wl_reg; +reg [0:SIZE_BLWL-1] bl_reg; +reg [0:SIZE_BLWL-1] wl_reg; +reg prog_clock_reg; +reg op_clock_reg; + +// Config done signal; +reg config_done; +// Temp register for rotating shift +reg temp; + +// Unit under test +grid_1__1_ U0 ( +zin, +nequalize, +read, +clk, +Reset, +Set, +prog_ENb, +prog_EN, +// Top inputs +lb_in[0], lb_in[4], lb_in[8], lb_in[12], lb_in[16], +lb_in[20], lb_in[24], lb_in[28], lb_in[32], lb_in[36], +// Top outputs +lb_out[0], lb_out[4], lb_out[8], +// Right inputs +lb_in[1], lb_in[5], lb_in[9], lb_in[13], lb_in[17], +lb_in[21], lb_in[25], lb_in[29], lb_in[33], lb_in[37], +// Right outputs +lb_out[1], lb_out[5], lb_out[9], +// Bottom inputs +lb_in[2], lb_in[6], lb_in[10], lb_in[14], lb_in[18], +lb_in[22], lb_in[26], lb_in[30], lb_in[34], lb_in[38], +// Bottom outputs +lb_out[2], lb_out[6], +// Bottom inputs +lb_clk, +// left inputs +lb_in[3], lb_in[7], lb_in[11], lb_in[15], lb_in[19], +lb_in[23], lb_in[27], lb_in[31], lb_in[35], lb_in[39], +// left outputs +lb_out[3], lb_out[7], +reserv_bl, reserv_wl, +bl, wl +); + +// Task: assign BL and WL values +task prog_lb_blwl; + begin + @(posedge prog_clock); + // Rotate left shift + temp = reserv_bl_reg[SIZE_RESERV_BLWL-1]; + //bl_reg = bl_reg >> 1; + reserv_bl_reg[1:SIZE_RESERV_BLWL-1] = reserv_bl_reg[0:SIZE_RESERV_BLWL-2]; + reserv_bl_reg[0] = temp; + end +endtask + +// Task: assign inputs +task op_lb_in; + begin + @(posedge op_clock); + temp = lb_in_reg[SIZE_IN-1]; + lb_in_reg[1:SIZE_IN-1] = lb_in_reg[0:SIZE_IN-2]; + lb_in_reg[0] = temp; + end +endtask + +// Configuration done signal +initial +begin + config_done = 1'b0; +end +// Enabled during config_period, Disabled during op_period +always +begin + #config_period config_done = ~config_done; + #operating_period config_done = ~config_done; +end + +// Programming clocks +initial +begin + prog_clock_reg = 1'b0; +end +always +begin + #prog_clk_period prog_clock_reg = ~prog_clock_reg; +end + +// Operating clocks +initial +begin + op_clock_reg = 1'b0; +end +always +begin + #op_clk_period op_clock_reg = ~op_clock_reg; +end + +// Programming and Operating clocks +assign prog_clock = prog_clock_reg & (~config_done); +assign op_clock = op_clock_reg & config_done; + +// Programming Enable signals +assign prog_EN = prog_clock & (~config_done); +assign prog_ENb = ~prog_EN; + +// Programming phase: BL/WL +initial +begin + // Initialize BL/WL registers + reserv_bl_reg = {SIZE_RESERV_BLWL {1'b0}}; + reserv_bl_reg[0] = 1'b1; + reserv_wl_reg = {SIZE_RESERV_BLWL {1'b0}}; + // Reserved BL/WL + bl_reg = {SIZE_BLWL {1'b0}}; + wl_reg = {SIZE_BLWL {1'b1}}; + //wl_reg[SIZE_BLWL-1] = 1'b1; +end +always wait (~config_done) // Only invoked when config_done is 0 +begin + // Propagate input 1 to the output + // BL[0] = 1, WL[4] = 1 + prog_lb_blwl; +end + +// Operating Phase +initial +begin + lb_in_reg = {SIZE_IN {1'b0}}; + lb_in_reg[0] = 1'b1; // Last bit is 1 initially +end +always wait (config_done) // Only invoked when config_done is 1 +begin + /* Update inputs */ + op_lb_in; +end + +// Wire ports +assign lb_in = lb_in_reg; +assign reserv_bl = reserv_bl_reg; +assign reserv_wl = reserv_wl_reg; +assign bl = bl_reg; +assign wl = wl_reg; + +// Constant ports +assign zin = 1'b0; +assign nequalize = 1'b1; +assign read = 1'b0; +assign clk = op_clock; +assign Reset = ~config_done; +assign Set = 1'b0; + +endmodule diff --git a/vpr7_rram/vpr/VerilogNetlists/lut6.v b/vpr7_rram/vpr/VerilogNetlists/lut6.v new file mode 100644 index 000000000..d214e56db --- /dev/null +++ b/vpr7_rram/vpr/VerilogNetlists/lut6.v @@ -0,0 +1,15 @@ +//----------------------------------------------------- +// Design Name : lut6 +// File Name : lut6.v +// Function : 6-input Look Up Table +// Coder : Xifan TANG +//----------------------------------------------------- +module lut6 ( +input [5:0] in, +output out, +input [63:0] sram, +input [63:0] sram_inv); + + assign out = sram[in]; + +endmodule diff --git a/vpr7_rram/vpr/VerilogNetlists/mux_tb.v b/vpr7_rram/vpr/VerilogNetlists/mux_tb.v new file mode 100644 index 000000000..752bab00b --- /dev/null +++ b/vpr7_rram/vpr/VerilogNetlists/mux_tb.v @@ -0,0 +1,85 @@ +//----------------------------------------------------- +// Design Name : testbench for 2-level SRAM MUX +// File Name : mux_tb.v +// Function : SRAM-based 2-level MUXes +// Coder : Xifan TANG +//----------------------------------------------------- +//----- Time scale: simulation time step and accuracy ----- +`timescale 1ns / 1ps + +module cmos_mux2level_tb; +// Parameters +parameter SIZE_OF_MUX = 50; //---- MUX input size +parameter SIZE_OF_SRAM = 16; //---- MUX input size +parameter op_clk_period = 1; // [ns] half clock period +parameter operating_period = SIZE_OF_MUX * 2 * op_clk_period; // [ns] One full clock period + +// voltage sources +wire [0:SIZE_OF_MUX-1] in; +wire out; +wire [0:SIZE_OF_SRAM-1] sram; +wire [0:SIZE_OF_SRAM-1] sram_inv; +// clocks +wire op_clock; +// registered ports +reg op_clock_reg; +reg [0:SIZE_OF_MUX-1] in_reg; +reg [0:SIZE_OF_SRAM-1] sram_reg; +reg [0:SIZE_OF_SRAM-1] sram_inv_reg; +// Config done signal; +reg config_done; +// Temp register for rotating shift +reg temp; + +// Unit Under Test +mux_2level_size50 U0 (in, out, sram, sram_inv); + +// Task: assign inputs +task op_mux_input; + begin + @(posedge op_clock); + temp = in_reg[SIZE_OF_MUX-1]; + in_reg[1:SIZE_OF_MUX-1] = in_reg[0:SIZE_OF_MUX-2]; + in_reg[0] = temp; + end +endtask + +// Configuration done signal +initial +begin + config_done = 1'b1; +end + +// Operating clocks +initial +begin + op_clock_reg = 1'b0; +end +always +begin + #op_clk_period op_clock_reg = ~op_clock_reg; +end + +// Programming and Operating clocks +assign op_clock = op_clock_reg & config_done; + +// Operating Phase +initial +begin + in_reg = {SIZE_OF_MUX {1'b0}}; + in_reg[0] = 1'b1; // Last bit is 1 initially +end +always wait (config_done) // Only invoked when config_done is 1 +begin + /* Update inputs */ + op_mux_input; +end + +// Wire ports +assign in = in_reg; +assign sram[0:7] = 8'b00010000; +assign sram[8:15] = 8'b00010000; +assign sram_inv = ~sram; + +endmodule + diff --git a/vpr7_rram/vpr/VerilogNetlists/sram.v b/vpr7_rram/vpr/VerilogNetlists/sram.v new file mode 100644 index 000000000..881661b03 --- /dev/null +++ b/vpr7_rram/vpr/VerilogNetlists/sram.v @@ -0,0 +1,92 @@ +//------ Module: sram6T_blwl -----// +//------ Verilog file: sram.v -----// +//------ Author: Xifan TANG -----// +module sram6T_blwl( +//input read, +//input nequalize, +input din, // Data input +output dout, // Data output +output doutb, // Data output +input bl, // Bit line control signal +input wl, // Word line control signal +input blb // Inverted Bit line control signal +); + //----- local variable need to be registered + reg a; + + //----- when wl is enabled, we can read in data from bl + always @(bl, wl) + begin + //----- Cases to program internal memory bit + //----- case 1: bl = 1, wl = 1, a -> 0 + if ((1'b1 == bl)&&(1'b1 == wl)) begin + a <= 1'b1; + end + //----- case 2: bl = 0, wl = 1, a -> 0 + if ((1'b0 == bl)&&(1'b1 == wl)) begin + a <= 1'b0; + end + end + + // dout is short-wired to din + assign dout = a; + //---- doutb is always opposite to dout + assign doutb = ~dout; +endmodule + +module sram6T_rram( +input read, +input nequalize, +input din, // Data input +output dout, // Data output +output doutb, // Data output +// !!! Port bit position should start from LSB to MSB +// Follow this convention for BL/WLs in each module! +input [0:2] bl, // Bit line control signal +input [0:2] wl// Word line control signal +); + //----- local variable need to be registered + //----- Modeling two RRAMs + reg r0, r1; + + always @(bl[0], wl[2]) + begin + //----- Cases to program r0 + //----- case 1: bl[0] = 1, wl[2] = 1, r0 -> 0 + if ((1'b1 == bl[0])&&(1'b1 == wl[2])) begin + r0 <= 0; + end + end + + always @(bl[2], wl[0]) + begin + //----- case 2: bl[2] = 1, wl[0] = 1, r0 -> 1 + if ((1'b1 == bl[2])&&(1'b1 == wl[0])) begin + r0 <= 1; + end + end + + always @(bl[1], wl[2]) + begin + //----- Cases to program r1 + //----- case 1: bl[1] = 1, wl[2] = 1, r0 -> 0 + if ((1'b1 == bl[1])&&(1'b1 == wl[2])) begin + r1 <= 0; + end + end + + always @( bl[2], wl[1]) + begin + //----- case 2: bl[2] = 1, wl[1] = 1, r0 -> 1 + if ((1'b1 == bl[2])&&(1'b1 == wl[1])) begin + r1 <= 1; + end + end + + // dout is r0 AND r1 + assign dout = r0 | (~r1); + + //---- doutb is always opposite to dout + assign doutb = ~dout; + +endmodule diff --git a/vpr7_rram/vpr/VerilogNetlists/sram_tb.v b/vpr7_rram/vpr/VerilogNetlists/sram_tb.v new file mode 100644 index 000000000..611579f41 --- /dev/null +++ b/vpr7_rram/vpr/VerilogNetlists/sram_tb.v @@ -0,0 +1,88 @@ +//----------------------------------------------------- +// Design Name : testbench for static_dff +// File Name : ff_tb.v +// Function : D flip-flop with asyn reset and set +// Coder : Xifan TANG +//----------------------------------------------------- +//----- Time scale: simulation time step and accuracy ----- +`timescale 1ns / 1ps + +module sram6T_rram_tb; +// voltage sources +wire read; +wire nequalize; +wire din; +wire dout; +wire doutb; +reg [0:2] bl; +reg [0:2] wl; +reg prog_clock; + +// Parameters +parameter prog_clk_period = 2; // [ns] a full clock period + +// Unit Under Test +sram6T_rram U0 (read, nequalize, din, dout, doutb, bl, wl); + +// Voltage stimuli +// read : alway disabled +assign read = 1'b0; + +// nequalize: always disabled +assign nequalize = 1'b1; + +// din: always disabled +assign din = 1'b0; + +// Programming clock +initial +begin + prog_clock = 1'b0; +end +always +begin + #prog_clk_period prog_clock = ~prog_clock; +end + +// Task: assign BL and WL values +task prog_blwl; + input [0:2] bl_val; + input [0:2] wl_val; + begin + @(posedge prog_clock); + bl = bl_val; + wl = wl_val; + end +endtask + +// Test two cases: +// 1. Program dout to 0 +// bl[0] = 1, wl[2] = 1 +// bl[2] = 1, wl[0] = 1 +// 2. Program dout to 1 +// bl[1] = 1, wl[2] = 1 +// bl[2] = 1, wl[1] = 1 +initial +begin + bl = 3'b000; + wl = 3'b000; +// 1. Program dout to 0 +// bl[0] = 1, wl[2] = 1 + prog_blwl(3'b100, 3'b001); +// bl[2] = 1, wl[0] = 1 + prog_blwl(3'b001, 3'b100); +// 2. Program dout to 1 +// bl[1] = 1, wl[2] = 1 + prog_blwl(3'b010, 3'b001); +// bl[2] = 1, wl[1] = 1 + prog_blwl(3'b100, 3'b010); +// 3. Program dout to 0 +// bl[0] = 1, wl[2] = 1 + prog_blwl(3'b100, 3'b001); +// bl[2] = 1, wl[0] = 1 + prog_blwl(3'b001, 3'b100); +end + +// Outputs are wired to dout and doutb + +endmodule diff --git a/vpr7_rram/vpr/go.sh b/vpr7_rram/vpr/go.sh new file mode 100755 index 000000000..7f4d30249 --- /dev/null +++ b/vpr7_rram/vpr/go.sh @@ -0,0 +1,7 @@ +#!/bin/sh +# Example of how to run vpr + +# Pack, place, and route a heterogeneous FPGA +# Packing uses the AAPack algorithm +./vpr ../../fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml Circuits/s298_prevpr.blif --full_stats --nodisp --activity_file Circuits/s298_prevpr.act --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --spice_dir ./spice_test --spice_print_top_testbench --fpga_syn_verilog --fpga_syn_verilog_dir ./verilog_test +