[Engine] Upgrade fabric key writer to support BL/WL shift register banks

openfpga/src/base/openfpga_build_fabric.cpp

@@ -135,6 +135,7 @@ int build_fabric(OpenfpgaContext& openfpga_ctx,
     curr_status = write_fabric_key_to_xml_file(openfpga_ctx.module_graph(),
                                                fkey_fname,
                                                openfpga_ctx.arch().config_protocol,
+                                               openfpga_ctx.mutable_blwl_shift_register_banks(),
                                                cmd_context.option_enable(cmd, opt_verbose));
     /* If there is any error, final status cannot be overwritten by a success flag */
     if (CMD_EXEC_SUCCESS != curr_status) {

openfpga/src/fabric/fabric_key_writer.cpp

@@ -32,6 +32,7 @@ namespace openfpga {
 int write_fabric_key_to_xml_file(const ModuleManager& module_manager,
                                  const std::string& fname,
                                  const ConfigProtocol& config_protocol,
+                                 MemoryBankShiftRegisterBanks& blwl_sr_banks,
                                  const bool& verbose) {
   std::string timer_message = std::string("Write fabric key to XML file '") + fname + std::string("'");
 
@@ -65,10 +66,16 @@ int write_fabric_key_to_xml_file(const ModuleManager& module_manager,
   size_t num_regions = module_manager.regions(top_module).size();
   fabric_key.reserve_regions(num_regions);
 
-  /* Create regions for the keys and load keys by region */
+  /* Create regions and build a id map */
+  std::map<ConfigRegionId, FabricRegionId> region_id_map;
   for (const ConfigRegionId& config_region : module_manager.regions(top_module)) {
     FabricRegionId fabric_region = fabric_key.create_region();
+    region_id_map[config_region] = fabric_region;
+  } 
  
+  /* Create regions for the keys and load keys by region */
+  for (const ConfigRegionId& config_region : module_manager.regions(top_module)) {
+    FabricRegionId fabric_region = region_id_map[config_region];
     /* Each configuration protocol has some child which should not be in the list. They are typically decoders */
     size_t curr_region_num_config_child = module_manager.region_configurable_children(top_module, config_region).size();
     size_t num_child_to_skip = estimate_num_configurable_children_to_skip_by_config_protocol(config_protocol, curr_region_num_config_child);
@@ -97,6 +104,28 @@ int write_fabric_key_to_xml_file(const ModuleManager& module_manager,
     }
   }
 
+  /* Add BL shift register bank information, if there is any */
+  for (const ConfigRegionId& config_region : module_manager.regions(top_module)) {
+    FabricRegionId fabric_region = region_id_map[config_region];
+    for (const FabricBitLineBankId& bank : blwl_sr_banks.bl_banks(config_region)) {
+      FabricBitLineBankId fabric_bank = fabric_key.create_bl_shift_register_bank(fabric_region);
+      for (const BasicPort& data_port : blwl_sr_banks.bl_bank_data_ports(config_region, bank)) {
+        fabric_key.add_data_port_to_bl_shift_register_bank(fabric_region, fabric_bank, data_port);
+      }
+    }
+  }
+
+  /* Add WL shift register bank information, if there is any */
+  for (const ConfigRegionId& config_region : module_manager.regions(top_module)) {
+    FabricRegionId fabric_region = region_id_map[config_region];
+    for (const FabricWordLineBankId& bank : blwl_sr_banks.wl_banks(config_region)) {
+      FabricWordLineBankId fabric_bank = fabric_key.create_wl_shift_register_bank(fabric_region);
+      for (const BasicPort& data_port : blwl_sr_banks.wl_bank_data_ports(config_region, bank)) {
+        fabric_key.add_data_port_to_wl_shift_register_bank(fabric_region, fabric_bank, data_port);
+      }
+    }
+  }
+
   VTR_LOGV(verbose,
            "Created %lu regions and %lu keys for the top module %s.\n",
            num_regions, num_keys, top_module_name.c_str());

openfpga/src/fabric/fabric_key_writer.h

@@ -7,6 +7,7 @@
 #include <string.h>
 #include "module_manager.h"
 #include "config_protocol.h"
+#include "memory_bank_shift_register_banks.h"
 
 /********************************************************************
  * Function declaration
@@ -18,6 +19,7 @@ namespace openfpga {
 int write_fabric_key_to_xml_file(const ModuleManager& module_manager,
                                  const std::string& fname,
                                  const ConfigProtocol& config_protocol,
+                                 MemoryBankShiftRegisterBanks& blwl_sr_banks,
                                  const bool& verbose);
 
 } /* end namespace openfpga */