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[core] code format

This commit is contained in:
tangxifan 2024-10-07 14:21:19 -07:00
parent 4f96680e1f
commit b9a0b1cdf8
5 changed files with 15 additions and 12 deletions
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3
libs/libpcf/src/io/write_csv_io_pin_table.cpp
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@ -52,7 +52,8 @@ int write_csv_io_pin_table(const char* fname, const IoPinTable& io_pin_table) {
/* Print data */
for (const IoPinTableId& pin_id : io_pin_table.pins()) {
std::vector<std::string> data_row_str;
data_row_str.push_back(TOTAL_2D_SIDE_STRINGS[io_pin_table.pin_side(pin_id)]);
data_row_str.push_back(
TOTAL_2D_SIDE_STRINGS[io_pin_table.pin_side(pin_id)]);
data_row_str.push_back(
generate_xml_port_name(io_pin_table.internal_pin(pin_id)));
data_row_str.push_back(

10
openfpga/src/fabric/build_grid_modules.cpp
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@ -1430,8 +1430,8 @@ int build_grid_modules(
* i.e., one or more from {TOP, RIGHT, BOTTOM, LEFT},
* we will generate one module for each border side
* - If a I/O block locates in the center of FPGA fabric:
* we will generate one module with NUM_2D_SIDES (same treatment as regular
* grids)
* we will generate one module with NUM_2D_SIDES (same treatment as
* regular grids)
*/
std::set<e_side> io_type_sides =
find_physical_io_tile_located_sides(device_ctx.grid, &physical_tile);
@ -1449,9 +1449,9 @@ int build_grid_modules(
/* For CLB and heterogenenous blocks */
status = build_physical_tile_module(
module_manager, decoder_lib, device_annotation, circuit_lib,
sram_orgz_type, sram_model, &physical_tile, tile_annotation, NUM_2D_SIDES,
ql_memory_bank_config_setting, duplicate_grid_pin, group_config_block,
device_ctx.arch->perimeter_cb, verbose);
sram_orgz_type, sram_model, &physical_tile, tile_annotation,
NUM_2D_SIDES, ql_memory_bank_config_setting, duplicate_grid_pin,
group_config_block, device_ctx.arch->perimeter_cb, verbose);
if (status != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}

4
openfpga/src/fabric/build_top_module_child_tile_instance.cpp
View File

@ -1539,8 +1539,8 @@ static int build_top_module_global_net_from_tile_modules(
status = build_top_module_global_net_for_given_tile_module(
module_manager, top_module, top_module_port, tile_annotation,
tile_global_port, tile_port, vpr_device_annotation, grids, layer,
vtr::Point<size_t>(ix, iy), NUM_2D_SIDES, tile_instance_ids, fabric_tile,
perimeter_cb);
vtr::Point<size_t>(ix, iy), NUM_2D_SIDES, tile_instance_ids,
fabric_tile, perimeter_cb);
if (CMD_EXEC_FATAL_ERROR == status) {
return status;
}

7
openfpga/src/fpga_spice/spice_grid.cpp
View File

@ -393,8 +393,8 @@ void print_spice_grids(NetlistManager& netlist_manager,
* i.e., one or more from {TOP, RIGHT, BOTTOM, LEFT},
* we will generate one module for each border side
* - If a I/O block locates in the center of FPGA fabric:
* we will generate one module with NUM_2D_SIDES (same treatment as regular
* grids)
* we will generate one module with NUM_2D_SIDES (same treatment as
* regular grids)
*/
std::set<e_side> io_type_sides =
find_physical_io_tile_located_sides(device_ctx.grid, &physical_tile);
@ -407,7 +407,8 @@ void print_spice_grids(NetlistManager& netlist_manager,
} else {
/* For CLB and heterogenenous blocks */
print_spice_physical_tile_netlist(netlist_manager, module_manager,
subckt_dir, &physical_tile, NUM_2D_SIDES);
subckt_dir, &physical_tile,
NUM_2D_SIDES);
}
}
VTR_LOG("Building physical tiles...");

3
openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp
View File

@ -139,7 +139,8 @@ void print_verilog_simulation_info(
size_t io_index = io_location_map.io_index(
place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.x,
place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.y,
place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile,
place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)]
.loc.sub_tile,
module_io_port.get_name());
if (size_t(-1) == io_index) {