From b96cdbf857ceaf5d25e998e06696968f2735b751 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 22 Jul 2020 12:23:39 -0600 Subject: [PATCH] adapt preconfig test cases to use yosys_vpr flow --- .../configuration_chain/config/task.conf | 6 +++--- .../configuration_frame/config/task.conf | 6 +++--- .../preconfig_testbench/flatten_memory/config/task.conf | 6 +++--- .../tasks/preconfig_testbench/memory_bank/config/task.conf | 6 +++--- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/openfpga_flow/tasks/preconfig_testbench/configuration_chain/config/task.conf b/openfpga_flow/tasks/preconfig_testbench/configuration_chain/config/task.conf index 53354162b..7f113ce06 100644 --- a/openfpga_flow/tasks/preconfig_testbench/configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/preconfig_testbench/configuration_chain/config/task.conf @@ -14,7 +14,7 @@ power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= @@ -27,8 +27,8 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2. [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/preconfig_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/preconfig_testbench/configuration_frame/config/task.conf index dca01bcfd..a527516e5 100644 --- a/openfpga_flow/tasks/preconfig_testbench/configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/preconfig_testbench/configuration_frame/config/task.conf @@ -14,7 +14,7 @@ power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= @@ -27,8 +27,8 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2. [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/preconfig_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/preconfig_testbench/flatten_memory/config/task.conf index a413be671..1b1b3108e 100644 --- a/openfpga_flow/tasks/preconfig_testbench/flatten_memory/config/task.conf +++ b/openfpga_flow/tasks/preconfig_testbench/flatten_memory/config/task.conf @@ -14,7 +14,7 @@ power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= @@ -27,8 +27,8 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2. [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/preconfig_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/preconfig_testbench/memory_bank/config/task.conf index bb9f7c11f..1d8ef602e 100644 --- a/openfpga_flow/tasks/preconfig_testbench/memory_bank/config/task.conf +++ b/openfpga_flow/tasks/preconfig_testbench/memory_bank/config/task.conf @@ -14,7 +14,7 @@ power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 -fpga_flow=vpr_blif +fpga_flow=yosys_vpr openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= @@ -27,8 +27,8 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2. [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]