diff --git a/openfpga_flow/tasks/fpga_verilog/dsp/single_mode_mult_8x8/config/task.conf b/openfpga_flow/tasks/fpga_verilog/dsp/single_mode_mult_8x8/config/task.conf
index 94b56505e..99a78c217 100644
--- a/openfpga_flow/tasks/fpga_verilog/dsp/single_mode_mult_8x8/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/dsp/single_mode_mult_8x8/config/task.conf
@@ -34,7 +34,7 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac_8/mac_
 
 [SYNTHESIS_PARAM]
 bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.tcl
-bench_yostcl=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.tcl;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.tcl
+bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.tcl;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.tcl
 
 bench0_top = mac_8