diff --git a/openfpga/src/fpga_sdc/sdc_memory_utils.cpp b/openfpga/src/fpga_sdc/sdc_memory_utils.cpp
index 07b7d0804..c9459ebaf 100644
--- a/openfpga/src/fpga_sdc/sdc_memory_utils.cpp
+++ b/openfpga/src/fpga_sdc/sdc_memory_utils.cpp
@@ -100,12 +100,9 @@ void rec_print_pnr_sdc_disable_configurable_memory_module_output(std::fstream& f
 
   /* Disable timing for each output port of this module */
   for (const BasicPort& output_port : module_manager.module_ports_by_type(parent_module, ModuleManager::MODULE_OUTPUT_PORT)) {
-    for (const size_t& pin : output_port.pins()) {
-      BasicPort output_pin(output_port.get_name(), pin, pin);
-      fp << "set_disable_timing ";
-      fp << parent_module_path << generate_sdc_port(output_pin);
-      fp << std::endl;
-    }
+    fp << "set_disable_timing ";
+    fp << parent_module_path << output_port.get_name();
+    fp << std::endl;
   }
 }
 
diff --git a/openfpga/src/fpga_sdc/sdc_writer_utils.cpp b/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
index 0fcf450ad..85ff6edcb 100644
--- a/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
+++ b/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
@@ -71,12 +71,7 @@ std::string generate_sdc_port(const BasicPort& port) {
    *   <port_type>
    */
   if (1 == port.get_width()) {
-    if (0 != port.get_lsb()) {
-      size_str = "[" + std::to_string(port.get_lsb()) + "]";
-    } else {
-      VTR_ASSERT(0 == port.get_lsb());
-      size_str.clear();
-    }
+    size_str = "[" + std::to_string(port.get_lsb()) + "]";
   }
 
   sdc_line = port.get_name() + size_str;